Data Structures |
| struct | UART0_Type |
| | UART0 - Register Layout Typedef. More...
|
Modules |
| | UART0 Register Masks |
| | USB Peripheral Access Layer |
| | SDK Compatibility |
Variables |
| __IO uint8_t DATH |
| | DAC Data High Register, array offset: 0x1, array step: 0x2.
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| __IO uint8_t | SR |
| | DAC Status Register, offset: 0x20.
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| __IO uint8_t | C0 |
| | DAC Control Register, offset: 0x21.
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| __IO uint8_t | C1 |
| | DAC Control Register 1, offset: 0x22.
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| __IO uint8_t | C2 |
| | DAC Control Register 2, offset: 0x23.
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| __IO uint32_t DAR |
| | Destination Address Register, array offset: 0x104, array step: 0x10.
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| __IO uint8_t DSR |
| | DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10.
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| __IO uint32_t DCR |
| | DMA Control Register, array offset: 0x10C, array step: 0x10.
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| __O uint32_t | PSOR |
| | Port Set Output Register, offset: 0x4.
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| __O uint32_t | PCOR |
| | Port Clear Output Register, offset: 0x8.
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| __O uint32_t | PTOR |
| | Port Toggle Output Register, offset: 0xC.
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| __I uint32_t | PDIR |
| | Port Data Input Register, offset: 0x10.
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| __IO uint32_t | PDDR |
| | Port Data Direction Register, offset: 0x14.
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| __IO uint8_t | FCNFG |
| | Flash Configuration Register, offset: 0x1.
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| __I uint8_t | FSEC |
| | Flash Security Register, offset: 0x2.
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| __I uint8_t | FOPT |
| | Flash Option Register, offset: 0x3.
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| __IO uint8_t | FCCOB3 |
| | Flash Common Command Object Registers, offset: 0x4.
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| __IO uint8_t | FCCOB2 |
| | Flash Common Command Object Registers, offset: 0x5.
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| __IO uint8_t | FCCOB1 |
| | Flash Common Command Object Registers, offset: 0x6.
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| __IO uint8_t | FCCOB0 |
| | Flash Common Command Object Registers, offset: 0x7.
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| __IO uint8_t | FCCOB7 |
| | Flash Common Command Object Registers, offset: 0x8.
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| __IO uint8_t | FCCOB6 |
| | Flash Common Command Object Registers, offset: 0x9.
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| __IO uint8_t | FCCOB5 |
| | Flash Common Command Object Registers, offset: 0xA.
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| __IO uint8_t | FCCOB4 |
| | Flash Common Command Object Registers, offset: 0xB.
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| __IO uint8_t | FCCOBB |
| | Flash Common Command Object Registers, offset: 0xC.
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| __IO uint8_t | FCCOBA |
| | Flash Common Command Object Registers, offset: 0xD.
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| __IO uint8_t | FCCOB9 |
| | Flash Common Command Object Registers, offset: 0xE.
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| __IO uint8_t | FCCOB8 |
| | Flash Common Command Object Registers, offset: 0xF.
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| __IO uint8_t | FPROT3 |
| | Program Flash Protection Registers, offset: 0x10.
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| __IO uint8_t | FPROT2 |
| | Program Flash Protection Registers, offset: 0x11.
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| __IO uint8_t | FPROT1 |
| | Program Flash Protection Registers, offset: 0x12.
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| __IO uint8_t | FPROT0 |
| | Program Flash Protection Registers, offset: 0x13.
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| __I uint8_t | C9 |
| | MCG Control 9 Register, offset: 0xE.
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| __I uint8_t | C10 |
| | MCG Control 10 Register, offset: 0xF.
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| __I uint16_t | PLASC |
| | Crossbar Switch (AXBS) Slave Configuration, offset: 0x8.
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| __I uint16_t | PLAMC |
| | Crossbar Switch (AXBS) Master Configuration, offset: 0xA.
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| __IO uint32_t | PLACR |
| | Platform Control Register, offset: 0xC.
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| __IO uint32_t | CPO |
| | Compute Operation Control Register, offset: 0x40.
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| __IO uint32_t | MASTER |
| | MTB Master Register, offset: 0x4.
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| __IO uint32_t | FLOW |
| | MTB Flow Register, offset: 0x8.
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| __I uint32_t | BASE |
| | MTB Base Register, offset: 0xC.
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| __I uint32_t | MODECTRL |
| | Integration Mode Control Register, offset: 0xF00.
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| __I uint32_t | TAGSET |
| | Claim TAG Set Register, offset: 0xFA0.
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| __I uint32_t | TAGCLEAR |
| | Claim TAG Clear Register, offset: 0xFA4.
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| __I uint32_t | LOCKACCESS |
| | Lock Access Register, offset: 0xFB0.
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| __I uint32_t | LOCKSTAT |
| | Lock Status Register, offset: 0xFB4.
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| __I uint32_t | AUTHSTAT |
| | Authentication Status Register, offset: 0xFB8.
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| __I uint32_t | DEVICEARCH |
| | Device Architecture Register, offset: 0xFBC.
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| __I uint32_t | DEVICECFG |
| | Device Configuration Register, offset: 0xFC8.
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| __I uint32_t | DEVICETYPID |
| | Device Type Identifier Register, offset: 0xFCC.
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| __I uint32_t | PERIPHID4 |
| | Peripheral ID Register, offset: 0xFD0.
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| __I uint32_t | PERIPHID5 |
| | Peripheral ID Register, offset: 0xFD4.
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| __I uint32_t | PERIPHID6 |
| | Peripheral ID Register, offset: 0xFD8.
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| __I uint32_t | PERIPHID7 |
| | Peripheral ID Register, offset: 0xFDC.
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| __I uint32_t | PERIPHID0 |
| | Peripheral ID Register, offset: 0xFE0.
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| __I uint32_t | PERIPHID1 |
| | Peripheral ID Register, offset: 0xFE4.
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| __I uint32_t | PERIPHID2 |
| | Peripheral ID Register, offset: 0xFE8.
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| __I uint32_t | PERIPHID3 |
| | Peripheral ID Register, offset: 0xFEC.
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| __I uint32_t | COMPID [4] |
| | Component ID Register, array offset: 0xFF0, array step: 0x4.
|
| __IO uint32_t MASK |
| | MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10.
|
| __IO uint32_t FCT |
| | MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10.
|
| __IO uint32_t | TBCTRL |
| | MTB_DWT Trace Buffer Control Register, offset: 0x200.
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| __I uint32_t | DEVICECFG |
| | Device Configuration Register, offset: 0xFC8.
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| __I uint32_t | DEVICETYPID |
| | Device Type Identifier Register, offset: 0xFCC.
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| __I uint32_t | PERIPHID4 |
| | Peripheral ID Register, offset: 0xFD0.
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| __I uint32_t | PERIPHID5 |
| | Peripheral ID Register, offset: 0xFD4.
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| __I uint32_t | PERIPHID6 |
| | Peripheral ID Register, offset: 0xFD8.
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| __I uint32_t | PERIPHID7 |
| | Peripheral ID Register, offset: 0xFDC.
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| __I uint32_t | PERIPHID0 |
| | Peripheral ID Register, offset: 0xFE0.
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| __I uint32_t | PERIPHID1 |
| | Peripheral ID Register, offset: 0xFE4.
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| __I uint32_t | PERIPHID2 |
| | Peripheral ID Register, offset: 0xFE8.
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| __I uint32_t | PERIPHID3 |
| | Peripheral ID Register, offset: 0xFEC.
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| __I uint32_t | COMPID [4] |
| | Component ID Register, array offset: 0xFF0, array step: 0x4.
|
| __I uint32_t | LTMR64H |
| | PIT Upper Lifetime Timer Register, offset: 0xE0.
|
| __I uint32_t | LTMR64L |
| | PIT Lower Lifetime Timer Register, offset: 0xE4.
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| __I uint32_t CVAL |
| | Current Timer Value Register, array offset: 0x104, array step: 0x10.
|
| __IO uint32_t TCTRL |
| | Timer Control Register, array offset: 0x108, array step: 0x10.
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| __IO uint32_t TFLG |
| | Timer Flag Register, array offset: 0x10C, array step: 0x10.
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| __I uint32_t | TABLEMARK |
| | End of Table Marker Register, offset: 0xC.
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| __I uint32_t | SYSACCESS |
| | System Access Register, offset: 0xFCC.
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| __I uint32_t | PERIPHID4 |
| | Peripheral ID Register, offset: 0xFD0.
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| __I uint32_t | PERIPHID5 |
| | Peripheral ID Register, offset: 0xFD4.
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| __I uint32_t | PERIPHID6 |
| | Peripheral ID Register, offset: 0xFD8.
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| __I uint32_t | PERIPHID7 |
| | Peripheral ID Register, offset: 0xFDC.
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| __I uint32_t | PERIPHID0 |
| | Peripheral ID Register, offset: 0xFE0.
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| __I uint32_t | PERIPHID1 |
| | Peripheral ID Register, offset: 0xFE4.
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| __I uint32_t | PERIPHID2 |
| | Peripheral ID Register, offset: 0xFE8.
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| __I uint32_t | PERIPHID3 |
| | Peripheral ID Register, offset: 0xFEC.
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| __I uint32_t | COMPID [4] |
| | Component ID Register, array offset: 0xFF0, array step: 0x4.
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| __IO uint32_t | COPC |
| | COP Control Register, offset: 0x1100.
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| __O uint32_t | SRVCOP |
| | Service COP, offset: 0x1104.
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| __IO uint8_t | STOPCTRL |
| | Stop Control Register, offset: 0x2.
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| __IO uint8_t | BR |
| | SPI Baud Rate Register, offset: 0x1.
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| __IO uint8_t | C2 |
| | SPI Control Register 2, offset: 0x2.
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| __IO uint8_t | C1 |
| | SPI Control Register 1, offset: 0x3.
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| __IO uint8_t | ML |
| | SPI Match Register low, offset: 0x4.
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| __IO uint8_t | MH |
| | SPI match register high, offset: 0x5.
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| __IO uint8_t | DL |
| | SPI Data Register low, offset: 0x6.
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| __IO uint8_t | DH |
| | SPI data register high, offset: 0x7.
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| __IO uint8_t | CI |
| | SPI clear interrupt register, offset: 0xA.
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| __IO uint8_t | C3 |
| | SPI control register 3, offset: 0xB.
|
| __IO uint32_t | CNT |
| | Counter, offset: 0x4.
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| __IO uint32_t | MOD |
| | Modulo, offset: 0x8.
|
| __IO uint32_t CnV |
| | Channel (n) Value, array offset: 0x10, array step: 0x8.
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| __IO uint32_t | STATUS |
| | Capture and Compare Status, offset: 0x50.
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| __IO uint32_t | CONF |
| | Configuration, offset: 0x84.
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| __IO uint32_t | DATA |
| | TSI DATA Register, offset: 0x4.
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| __IO uint32_t | TSHD |
| | TSI Threshold Register, offset: 0x8.
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| __IO uint8_t | BDL |
| | UART Baud Rate Register Low, offset: 0x1.
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| __IO uint8_t | C1 |
| | UART Control Register 1, offset: 0x2.
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| __IO uint8_t | C2 |
| | UART Control Register 2, offset: 0x3.
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| __IO uint8_t | S1 |
| | UART Status Register 1, offset: 0x4.
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| __IO uint8_t | S2 |
| | UART Status Register 2, offset: 0x5.
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| __IO uint8_t | C3 |
| | UART Control Register 3, offset: 0x6.
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| __IO uint8_t | D |
| | UART Data Register, offset: 0x7.
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| __IO uint8_t | MA1 |
| | UART Match Address Registers 1, offset: 0x8.
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| __IO uint8_t | MA2 |
| | UART Match Address Registers 2, offset: 0x9.
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| __IO uint8_t | C4 |
| | UART Control Register 4, offset: 0xA.
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| __IO uint8_t | C5 |
| | UART Control Register 5, offset: 0xB.
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1.7.2