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MCM_Type Struct Reference
[MCM Peripheral Access Layer]
MCM - Register Layout Typedef. More...
#include <MK26F18.h>
Data Fields | |
| __I uint16_t | PLASC |
| Crossbar Switch (AXBS) Slave Configuration, offset: 0x8. | |
| __I uint16_t | PLAMC |
| Crossbar Switch (AXBS) Master Configuration, offset: 0xA. | |
| __IO uint32_t | CR |
| Control Register, offset: 0xC. | |
| __IO uint32_t | ISCR |
| Interrupt Status Register, offset: 0x10. | |
| __IO uint32_t | ETBCC |
| ETB Counter Control register, offset: 0x14. | |
| __IO uint32_t | ETBRL |
| ETB Reload register, offset: 0x18. | |
| __I uint32_t | ETBCNT |
| ETB Counter Value register, offset: 0x1C. | |
| __I uint32_t | FADR |
| Fault address register, offset: 0x20. | |
| __I uint32_t | FATR |
| Fault attributes register, offset: 0x24. | |
| __I uint32_t | FDR |
| Fault data register, offset: 0x28. | |
| __IO uint32_t | PID |
| Process ID register, offset: 0x30. | |
| __IO uint32_t | CPO |
| Compute Operation Control Register, offset: 0x40. | |
| __IO uint32_t | PLACR |
| Platform Control Register, offset: 0xC. | |
Detailed Description
MCM - Register Layout Typedef.
Definition at line 15978 of file MK26F18.h.
Field Documentation
| __IO uint32_t ETBCC |
| __I uint32_t ETBCNT |
| __I uint32_t FATR |
| __IO uint32_t ISCR |
Generated on Tue Jul 12 2022 15:37:38 by
1.7.2