jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

Revisions of FPGA_bus.cpp

Revision Date Message Actions
27:fe3dddcd448c 2020-07-25 Made 'hard_check_bus' routine public. File  Diff  Annotate
25:9cdeb5267a47 2020-06-28 Removed "wait_ms" from bus initialise code. Routine is deprecated. File  Diff  Annotate
23:4b391cfd4f2d 2020-06-26 "soft_bus_check" changed to use decrementing timeout counter rather than fixed delay. File  Diff  Annotate
22:c47d4177d59c 2020-06-23 Added soft bus check that does not need a hard RESET therefore retians system configuration. File  Diff  Annotate
21:6b2b7a0e2d9a 2020-06-16 Bus check routine ammended to look for low to high transition on handshake_2 File  Diff  Annotate
20:aacf2ebd93ff 2020-06-15 Added routine to test bus on initialisation. Code documented. File  Diff  Annotate
17:928b755cba80 2020-05-23 Initial test for PWM channel File  Diff  Annotate
16:d69a36a541c5 2020-05-23 Register address pointers now calculated at run-time rather than #define compile constants File  Diff  Annotate
15:6420b52d30cc 2020-05-22 FPGA unit base register pointers are now variables rather than #define constants File  Diff  Annotate
14:b56473e54f6f 2020-05-22 Removed commented out code File  Diff  Annotate
13:67382358d024 2020-05-02 merge File  Diff  Annotate
12:b9b4ff729fef 2020-05-02 fix File  Diff  Annotate
10:56a045a02047 2020-05-02 do-transaction changed to public function File  Diff  Annotate
9:6fe95fb0c7ea 2019-05-29 Added compile time configuration to disable return of 32-bit status word.; Added log data output to allow simple timing of units of code. e.g. 6 byte out and 4 byte in transaction is timed at 9.6uS. File  Diff  Annotate
8:65d1b1a7bfcc 2019-05-12 Named bits in QE configuration register File  Diff  Annotate
7:c0bef9c1f5d5 2020-04-13 Change to remove default constructor error with Arm V6 compiler. File  Diff  Annotate
6:e68defb7b775 2019-05-08 Added code to read system data from FPGA File  Diff  Annotate
5:64c677e9995c 2019-04-18 Added routines to read and measure speed from quadrature encoder signals. File  Diff  Annotate
4:e5d36eee9245 2019-04-18 Fixed errors in register address calculations in high level routines in module FPGA_bus. File  Diff  Annotate
3:cf36c2d4208f 2019-04-17 Converted "Servo_test_2" code to use higher level routines. File  Diff  Annotate
2:fd5c862b86db 2019-04-17 Fixed problem with not enabling gloobal RC subsystem flag. File  Diff  Annotate
1:b819a72b3b5d 2019-04-17 Added higher level routines to set RC channels. File  Diff  Annotate
0:9600ed6fd725 2019-02-20 Added PWM config function File  Diff  Annotate