Diff: FPGA_bus.cpp

Revision:

16:d69a36a541c5

Parent:

15:6420b52d30cc

Child:

17:928b755cba80

--- a/FPGA_bus.cpp	Fri May 22 22:53:46 2020 +0000
+++ b/FPGA_bus.cpp	Sat May 23 11:58:57 2020 +0000
@@ -148,7 +148,7 @@
     
 void FPGA_bus::set_PWM_period(uint32_t channel, float frequency)
 {
-    uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_PERIOD);
+    uint32_t register_address = ((PWM_base + (channel * NOS_PWM_REGISTERS)) + PWM_PERIOD);
     uint32_t period_value = (uint32_t)(1000000/(20 * frequency));
     do_transaction(WRITE_REGISTER_CMD, register_address, period_value, &data, &status); 
     sys_data.PWM_period_value[channel] = period_value;
@@ -157,7 +157,7 @@
 
 void FPGA_bus::set_PWM_duty(uint32_t channel, float percentage)
 {
-    uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_ON_TIME);
+    uint32_t register_address = ((PWM_base + (channel * NOS_PWM_REGISTERS)) + PWM_ON_TIME);
     uint32_t duty_value = (uint32_t)((sys_data.PWM_period_value[channel] * percentage) / 100);
     do_transaction(WRITE_REGISTER_CMD, register_address , duty_value, &data, &status);
     sys_data.PWM_duty_value[channel] = duty_value;
@@ -166,7 +166,7 @@
 
 void FPGA_bus::PWM_enable(uint32_t channel)
 {
-    uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
+    uint32_t register_address = ((PWM_base + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
     do_transaction(WRITE_REGISTER_CMD, register_address , 1, &data, &status);
  //   sys_data.PWM_duty_value[channel] = duty_value;
     global_FPGA_unit_error_flag = status;;
@@ -174,7 +174,7 @@
 
 void FPGA_bus::PWM_config(uint32_t channel, uint32_t config_value)
 {
-    uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
+    uint32_t register_address = ((PWM_base + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
     do_transaction(WRITE_REGISTER_CMD, register_address , config_value, &data, &status);
     sys_data.PWM_duty_value[channel] = config_value;
     global_FPGA_unit_error_flag = status;;
@@ -182,50 +182,50 @@
 
 void FPGA_bus::set_RC_period(void)
 {
-    do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), 1000000, &data, &status);
+    do_transaction(WRITE_REGISTER_CMD, (RC_base + RC_SERVO_PERIOD), 1000000, &data, &status);
     global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus::set_RC_period(uint32_t duty_uS)
 {
     uint32_t nos_20nS_ticks = ((duty_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
-    do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
+    do_transaction(WRITE_REGISTER_CMD, (RC_base + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
     global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus :: set_RC_pulse(uint32_t channel, uint32_t pulse_uS)
 {
     uint32_t nos_20nS_ticks = ((pulse_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
-    do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_ON_TIME + channel), nos_20nS_ticks, &data, &status);
+    do_transaction(WRITE_REGISTER_CMD, (RC_base + RC_SERVO_ON_TIME + channel), nos_20nS_ticks, &data, &status);
     global_FPGA_unit_error_flag = status;;    
 }
 
 void FPGA_bus::enable_RC_channel(uint32_t channel)
 {
-    do_transaction(READ_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), NULL, &data, &status);
+    do_transaction(READ_REGISTER_CMD, (RC_base + RC_SERVO_CONFIG), NULL, &data, &status);
     int32_t config = (data || (0x01 << channel)) + GLOBAL_RC_ENABLE;
-    do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), config, &data, &status);
+    do_transaction(WRITE_REGISTER_CMD, (RC_base + RC_SERVO_CONFIG), config, &data, &status);
     global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus::disable_RC_channel(uint32_t channel)
 {
-    do_transaction(READ_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), NULL, &data, &status);
+    do_transaction(READ_REGISTER_CMD, (RC_base + RC_SERVO_CONFIG), NULL, &data, &status);
     uint32_t config = data && ~(0x01 << channel);
-    do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), config, &data, &status);
+    do_transaction(WRITE_REGISTER_CMD, (RC_base + RC_SERVO_CONFIG), config, &data, &status);
     global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus::QE_config(uint32_t channel, uint32_t config_value)
 {
-    uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
+    uint32_t register_address = ((PWM_base + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
     do_transaction(WRITE_REGISTER_CMD, register_address , config_value, &data, &status);
     global_FPGA_unit_error_flag = status;;
 }
 
 void FPGA_bus::enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time)
 {
-    uint32_t register_base = (QE_BASE + (channel * NOS_QE_REGISTERS));
+    uint32_t register_base = (QE_base + (channel * NOS_QE_REGISTERS));
     do_transaction(WRITE_REGISTER_CMD, (register_base + QE_SIM_PHASE_TIME), phase_time, &data, &status);
     global_FPGA_unit_error_flag = status;
     if (status != NO_ERROR) {
@@ -237,7 +237,7 @@
 
 uint32_t FPGA_bus::read_speed_measure(uint32_t channel)
 {
-    uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_SPEED_BUFFER);
+    uint32_t register_address = ((QE_base + (channel * NOS_QE_REGISTERS)) + QE_SPEED_BUFFER);
     do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
     global_FPGA_unit_error_flag = status;
     return data;
@@ -245,7 +245,7 @@
 
 uint32_t FPGA_bus::read_count_measure(uint32_t channel)
 {
-    uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_COUNT_BUFFER);
+    uint32_t register_address = ((QE_base + (channel * NOS_QE_REGISTERS)) + QE_COUNT_BUFFER);
     do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
     global_FPGA_unit_error_flag = status;
     return data;