jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

FPGA_bus.cpp@10:56a045a02047, 2020-05-02 (annotated)

Committer:
jimherd
Date:
Sat May 02 16:26:32 2020 +0000
Revision:
10:56a045a02047
Parent:
9:6fe95fb0c7ea
Child:
12:b9b4ff729fef
do-transaction changed to public function

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jimherd 0:9600ed6fd725 1 /*
jimherd 0:9600ed6fd725 2 * FPGA_bus : 8-bit bi-directional bus between uP and FPGA
jimherd 0:9600ed6fd725 3 */
jimherd 0:9600ed6fd725 4 #include "mbed.h"
jimherd 0:9600ed6fd725 5 #include "FPGA_bus.h"
jimherd 0:9600ed6fd725 6
jimherd 0:9600ed6fd725 7 /** create a FPGA_bus object connecting uP to FPGA
jimherd 0:9600ed6fd725 8 *
jimherd 0:9600ed6fd725 9 * @param nos_PWM Number of PWM channels (default = 4)
jimherd 0:9600ed6fd725 10 * @param nos_QE Number of Quadrature Encoder channels (default = 4)
jimherd 0:9600ed6fd725 11 * @param nos_servo Number of RC servo channels (default = 8)
jimherd 0:9600ed6fd725 12 *
jimherd 0:9600ed6fd725 13 * Notes
jimherd 0:9600ed6fd725 14 * You can only change the defaults by recompiling the SystemVerilog code
jimherd 0:9600ed6fd725 15 * on the FPGA.
jimherd 0:9600ed6fd725 16 */
jimherd 0:9600ed6fd725 17 FPGA_bus::FPGA_bus(int nos_PWM = NOS_PWM_CHANNELS,
jimherd 0:9600ed6fd725 18 int nos_QE = NOS_QE_CHANNELS,
jimherd 0:9600ed6fd725 19 int nos_servo = NOS_RC_CHANNELS)
jimherd 0:9600ed6fd725 20
jimherd 0:9600ed6fd725 21 : async_uP_start(ASYNC_UP_START_PIN),
jimherd 0:9600ed6fd725 22 async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
jimherd 0:9600ed6fd725 23 async_uP_RW(ASYNC_UP_RW_PIN),
jimherd 0:9600ed6fd725 24 async_uP_reset(ASYNC_UP_RESET_PIN),
jimherd 0:9600ed6fd725 25 uP_ack(ASYNC_UP_ACK_PIN),
jimherd 9:6fe95fb0c7ea 26 uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
jimherd 9:6fe95fb0c7ea 27 log_pin(LOG_PIN)
jimherd 0:9600ed6fd725 28 {
jimherd 0:9600ed6fd725 29 _nos_PWM_units = nos_PWM;
jimherd 0:9600ed6fd725 30 _nos_QE_units = nos_QE;
jimherd 0:9600ed6fd725 31 _nos_servo_units = nos_servo;
jimherd 0:9600ed6fd725 32
jimherd 0:9600ed6fd725 33 async_uP_start = LOW;
jimherd 0:9600ed6fd725 34 }
jimherd 0:9600ed6fd725 35
jimherd 0:9600ed6fd725 36 FPGA_bus::FPGA_bus(void)
jimherd 0:9600ed6fd725 37 : async_uP_start(ASYNC_UP_START_PIN),
jimherd 0:9600ed6fd725 38 async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
jimherd 0:9600ed6fd725 39 async_uP_RW(ASYNC_UP_RW_PIN),
jimherd 0:9600ed6fd725 40 async_uP_reset(ASYNC_UP_RESET_PIN),
jimherd 0:9600ed6fd725 41 uP_ack(ASYNC_UP_ACK_PIN),
jimherd 9:6fe95fb0c7ea 42 uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
jimherd 9:6fe95fb0c7ea 43 log_pin(LOG_PIN)
jimherd 0:9600ed6fd725 44 {
jimherd 0:9600ed6fd725 45 _nos_PWM_units = NOS_PWM_CHANNELS;
jimherd 0:9600ed6fd725 46 _nos_QE_units = NOS_QE_CHANNELS;
jimherd 0:9600ed6fd725 47 _nos_servo_units = NOS_RC_CHANNELS;
jimherd 0:9600ed6fd725 48
jimherd 0:9600ed6fd725 49 async_uP_start = LOW;
jimherd 0:9600ed6fd725 50 }
jimherd 0:9600ed6fd725 51
jimherd 0:9600ed6fd725 52
jimherd 0:9600ed6fd725 53
jimherd 0:9600ed6fd725 54 void FPGA_bus::initialise(void)
jimherd 0:9600ed6fd725 55 {
jimherd 0:9600ed6fd725 56 // GPIOC Periph clock enable
jimherd 0:9600ed6fd725 57
jimherd 0:9600ed6fd725 58 ENABLE_GPIO_SUBSYSTEM;
jimherd 0:9600ed6fd725 59 wait_us(2);
jimherd 0:9600ed6fd725 60
jimherd 0:9600ed6fd725 61 async_uP_start = LOW;
jimherd 0:9600ed6fd725 62 async_uP_reset = HIGH;
jimherd 0:9600ed6fd725 63 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 64 async_uP_RW = LOW;
jimherd 0:9600ed6fd725 65
jimherd 0:9600ed6fd725 66 async_uP_reset = LOW; // generate low reset pulse
jimherd 0:9600ed6fd725 67 wait_us(20);
jimherd 0:9600ed6fd725 68 async_uP_reset = HIGH;
jimherd 0:9600ed6fd725 69 wait_us(20);
jimherd 1:b819a72b3b5d 70
jimherd 1:b819a72b3b5d 71 global_FPGA_unit_error_flag = NO_ERROR;
jimherd 9:6fe95fb0c7ea 72 log_pin = LOW;
jimherd 0:9600ed6fd725 73 }
jimherd 0:9600ed6fd725 74
jimherd 0:9600ed6fd725 75 void FPGA_bus::do_start(void)
jimherd 0:9600ed6fd725 76 {
jimherd 0:9600ed6fd725 77 async_uP_start = HIGH;
jimherd 0:9600ed6fd725 78 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 79 async_uP_start = LOW;
jimherd 0:9600ed6fd725 80 }
jimherd 0:9600ed6fd725 81
jimherd 0:9600ed6fd725 82 void FPGA_bus::do_end(void)
jimherd 0:9600ed6fd725 83 {
jimherd 0:9600ed6fd725 84 while (uP_ack == HIGH)
jimherd 0:9600ed6fd725 85 ;
jimherd 0:9600ed6fd725 86 async_uP_start = LOW;
jimherd 0:9600ed6fd725 87 }
jimherd 0:9600ed6fd725 88
jimherd 0:9600ed6fd725 89 void FPGA_bus::write_byte(uint32_t byte_value)
jimherd 0:9600ed6fd725 90 {
jimherd 0:9600ed6fd725 91 SET_BUS_OUTPUT;
jimherd 0:9600ed6fd725 92 OUTPUT_BYTE_TO_BUS(byte_value);
jimherd 0:9600ed6fd725 93 async_uP_RW = WRITE_BUS;
jimherd 0:9600ed6fd725 94 async_uP_handshake_1 = HIGH;
jimherd 0:9600ed6fd725 95 while (uP_handshake_2 == LOW)
jimherd 0:9600ed6fd725 96 ;
jimherd 0:9600ed6fd725 97 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 98 while (uP_handshake_2 == HIGH)
jimherd 0:9600ed6fd725 99 ;
jimherd 0:9600ed6fd725 100 }
jimherd 0:9600ed6fd725 101
jimherd 0:9600ed6fd725 102 uint32_t FPGA_bus::read_byte(void)
jimherd 0:9600ed6fd725 103 {
jimherd 0:9600ed6fd725 104 SET_BUS_INPUT;
jimherd 0:9600ed6fd725 105 async_uP_RW = READ_BUS;
jimherd 0:9600ed6fd725 106 while (uP_handshake_2 == LOW)
jimherd 0:9600ed6fd725 107 ;
jimherd 0:9600ed6fd725 108 data = INPUT_BYTE_FROM_BUS;
jimherd 0:9600ed6fd725 109 async_uP_handshake_1 = HIGH;
jimherd 0:9600ed6fd725 110 while (uP_handshake_2 == HIGH)
jimherd 0:9600ed6fd725 111 ;
jimherd 0:9600ed6fd725 112 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 113 return data;
jimherd 0:9600ed6fd725 114 }
jimherd 0:9600ed6fd725 115
jimherd 0:9600ed6fd725 116 void FPGA_bus::do_write(uint32_t command,
jimherd 0:9600ed6fd725 117 uint32_t register_address,
jimherd 0:9600ed6fd725 118 uint32_t register_data)
jimherd 0:9600ed6fd725 119 {
jimherd 0:9600ed6fd725 120 write_byte(command);
jimherd 0:9600ed6fd725 121 write_byte(register_address);
jimherd 0:9600ed6fd725 122 write_byte(register_data);
jimherd 0:9600ed6fd725 123 write_byte(register_data>>8);
jimherd 0:9600ed6fd725 124 write_byte(register_data>>16);
jimherd 0:9600ed6fd725 125 write_byte(register_data>>24);
jimherd 0:9600ed6fd725 126 }
jimherd 0:9600ed6fd725 127
jimherd 0:9600ed6fd725 128 void FPGA_bus::do_read(received_packet_t *buffer)
jimherd 0:9600ed6fd725 129 {
jimherd 0:9600ed6fd725 130 for (int i=0; i < (NOS_RECEIVED_PACKET_WORDS<<2) ; i++) {
jimherd 0:9600ed6fd725 131 buffer->byte_data[i] = (uint8_t)read_byte();
jimherd 0:9600ed6fd725 132 }
jimherd 0:9600ed6fd725 133 }
jimherd 0:9600ed6fd725 134
jimherd 0:9600ed6fd725 135 void FPGA_bus::do_transaction(uint32_t command,
jimherd 0:9600ed6fd725 136 uint32_t register_address,
jimherd 0:9600ed6fd725 137 uint32_t register_data,
jimherd 0:9600ed6fd725 138 uint32_t *data,
jimherd 0:9600ed6fd725 139 uint32_t *status)
jimherd 0:9600ed6fd725 140 {
jimherd 9:6fe95fb0c7ea 141 log_pin = HIGH;
jimherd 0:9600ed6fd725 142 do_start();
jimherd 0:9600ed6fd725 143 do_write(command, register_address, register_data);
jimherd 0:9600ed6fd725 144 do_read(&in_pkt);
jimherd 0:9600ed6fd725 145 do_end();
jimherd 9:6fe95fb0c7ea 146 log_pin = LOW;
jimherd 0:9600ed6fd725 147 *data = in_pkt.word_data[0];
jimherd 0:9600ed6fd725 148 *status = in_pkt.word_data[1];
jimherd 0:9600ed6fd725 149 }
jimherd 0:9600ed6fd725 150
jimherd 0:9600ed6fd725 151 uint32_t FPGA_bus::do_command(FPGA_packet_t cmd_packet)
jimherd 0:9600ed6fd725 152 {
jimherd 0:9600ed6fd725 153 async_uP_start = LOW;
jimherd 0:9600ed6fd725 154 return 0;
jimherd 0:9600ed6fd725 155 }
jimherd 0:9600ed6fd725 156
jimherd 1:b819a72b3b5d 157 void FPGA_bus::set_PWM_period(uint32_t channel, float frequency)
jimherd 0:9600ed6fd725 158 {
jimherd 4:e5d36eee9245 159 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_PERIOD);
jimherd 0:9600ed6fd725 160 uint32_t period_value = (uint32_t)(1000000/(20 * frequency));
jimherd 4:e5d36eee9245 161 do_transaction(WRITE_REGISTER_CMD, register_address, period_value, &data, &status);
jimherd 0:9600ed6fd725 162 sys_data.PWM_period_value[channel] = period_value;
jimherd 1:b819a72b3b5d 163 global_FPGA_unit_error_flag = status;
jimherd 0:9600ed6fd725 164 }
jimherd 0:9600ed6fd725 165
jimherd 1:b819a72b3b5d 166 void FPGA_bus::set_PWM_duty(uint32_t channel, float percentage)
jimherd 0:9600ed6fd725 167 {
jimherd 4:e5d36eee9245 168 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_ON_TIME);
jimherd 0:9600ed6fd725 169 uint32_t duty_value = (uint32_t)((sys_data.PWM_period_value[channel] * percentage) / 100);
jimherd 4:e5d36eee9245 170 do_transaction(WRITE_REGISTER_CMD, register_address , duty_value, &data, &status);
jimherd 0:9600ed6fd725 171 sys_data.PWM_duty_value[channel] = duty_value;
jimherd 1:b819a72b3b5d 172 global_FPGA_unit_error_flag = status;;
jimherd 0:9600ed6fd725 173 }
jimherd 0:9600ed6fd725 174
jimherd 1:b819a72b3b5d 175 void FPGA_bus::PWM_enable(uint32_t channel)
jimherd 0:9600ed6fd725 176 {
jimherd 4:e5d36eee9245 177 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
jimherd 4:e5d36eee9245 178 do_transaction(WRITE_REGISTER_CMD, register_address , 1, &data, &status);
jimherd 0:9600ed6fd725 179 // sys_data.PWM_duty_value[channel] = duty_value;
jimherd 1:b819a72b3b5d 180 global_FPGA_unit_error_flag = status;;
jimherd 0:9600ed6fd725 181 }
jimherd 0:9600ed6fd725 182
jimherd 1:b819a72b3b5d 183 void FPGA_bus::PWM_config(uint32_t channel, uint32_t config_value)
jimherd 0:9600ed6fd725 184 {
jimherd 4:e5d36eee9245 185 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
jimherd 4:e5d36eee9245 186 do_transaction(WRITE_REGISTER_CMD, register_address , config_value, &data, &status);
jimherd 0:9600ed6fd725 187 sys_data.PWM_duty_value[channel] = config_value;
jimherd 1:b819a72b3b5d 188 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 189 }
jimherd 1:b819a72b3b5d 190
jimherd 4:e5d36eee9245 191 void FPGA_bus::set_RC_period(void)
jimherd 1:b819a72b3b5d 192 {
jimherd 4:e5d36eee9245 193 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), 1000000, &data, &status);
jimherd 6:e68defb7b775 194 global_FPGA_unit_error_flag = status;
jimherd 1:b819a72b3b5d 195 }
jimherd 1:b819a72b3b5d 196
jimherd 4:e5d36eee9245 197 void FPGA_bus::set_RC_period(uint32_t duty_uS)
jimherd 1:b819a72b3b5d 198 {
jimherd 1:b819a72b3b5d 199 uint32_t nos_20nS_ticks = ((duty_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
jimherd 4:e5d36eee9245 200 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
jimherd 6:e68defb7b775 201 global_FPGA_unit_error_flag = status;
jimherd 1:b819a72b3b5d 202 }
jimherd 1:b819a72b3b5d 203
jimherd 1:b819a72b3b5d 204 void FPGA_bus :: set_RC_pulse(uint32_t channel, uint32_t pulse_uS)
jimherd 1:b819a72b3b5d 205 {
jimherd 1:b819a72b3b5d 206 uint32_t nos_20nS_ticks = ((pulse_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
jimherd 4:e5d36eee9245 207 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_ON_TIME + channel), nos_20nS_ticks, &data, &status);
jimherd 1:b819a72b3b5d 208 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 209 }
jimherd 1:b819a72b3b5d 210
jimherd 4:e5d36eee9245 211 void FPGA_bus::enable_RC_channel(uint32_t channel)
jimherd 1:b819a72b3b5d 212 {
jimherd 4:e5d36eee9245 213 do_transaction(READ_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), NULL, &data, &status);
jimherd 2:fd5c862b86db 214 int32_t config = (data || (0x01 << channel)) + GLOBAL_RC_ENABLE;
jimherd 4:e5d36eee9245 215 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), config, &data, &status);
jimherd 3:cf36c2d4208f 216 global_FPGA_unit_error_flag = status;
jimherd 2:fd5c862b86db 217 }
jimherd 2:fd5c862b86db 218
jimherd 4:e5d36eee9245 219 void FPGA_bus::disable_RC_channel(uint32_t channel)
jimherd 2:fd5c862b86db 220 {
jimherd 4:e5d36eee9245 221 do_transaction(READ_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), NULL, &data, &status);
jimherd 4:e5d36eee9245 222 uint32_t config = data && ~(0x01 << channel);
jimherd 4:e5d36eee9245 223 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), config, &data, &status);
jimherd 1:b819a72b3b5d 224 global_FPGA_unit_error_flag = status;
jimherd 4:e5d36eee9245 225 }
jimherd 4:e5d36eee9245 226
jimherd 9:6fe95fb0c7ea 227 void FPGA_bus::QE_config(uint32_t channel, uint32_t config_value)
jimherd 9:6fe95fb0c7ea 228 {
jimherd 9:6fe95fb0c7ea 229 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
jimherd 9:6fe95fb0c7ea 230 do_transaction(WRITE_REGISTER_CMD, register_address , config_value, &data, &status);
jimherd 9:6fe95fb0c7ea 231 global_FPGA_unit_error_flag = status;;
jimherd 9:6fe95fb0c7ea 232 }
jimherd 9:6fe95fb0c7ea 233
jimherd 9:6fe95fb0c7ea 234 void FPGA_bus::enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time)
jimherd 4:e5d36eee9245 235 {
jimherd 9:6fe95fb0c7ea 236 uint32_t register_base = (QE_BASE + (channel * NOS_QE_REGISTERS));
jimherd 9:6fe95fb0c7ea 237 do_transaction(WRITE_REGISTER_CMD, (register_base + QE_SIM_PHASE_TIME), phase_time, &data, &status);
jimherd 5:64c677e9995c 238 global_FPGA_unit_error_flag = status;
jimherd 10:56a045a02047 239 if (status != NO_ERROR) {
jimherd 10:56a045a02047 240 return;
jimherd 10:56a045a02047 241 }
jimherd 10:56a045a02047 242 do_transaction(WRITE_REGISTER_CMD, (register_base + QE_CONFIG), config_value, &data, &status);
jimherd 10:56a045a02047 243 global_FPGA_unit_error_flag = status;
jimherd 5:64c677e9995c 244 }
jimherd 5:64c677e9995c 245
jimherd 5:64c677e9995c 246 uint32_t FPGA_bus::read_speed_measure(uint32_t channel)
jimherd 5:64c677e9995c 247 {
jimherd 8:65d1b1a7bfcc 248 uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_SPEED_BUFFER);
jimherd 5:64c677e9995c 249 do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
jimherd 5:64c677e9995c 250 global_FPGA_unit_error_flag = status;
jimherd 5:64c677e9995c 251 return data;
jimherd 6:e68defb7b775 252 }
jimherd 6:e68defb7b775 253
jimherd 10:56a045a02047 254 uint32_t FPGA_bus::read_count_measure(uint32_t channel)
jimherd 10:56a045a02047 255 {
jimherd 10:56a045a02047 256 uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_COUNT_BUFFER);
jimherd 10:56a045a02047 257 do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
jimherd 10:56a045a02047 258 global_FPGA_unit_error_flag = status;
jimherd 10:56a045a02047 259 return data;
jimherd 10:56a045a02047 260 }
jimherd 10:56a045a02047 261
jimherd 6:e68defb7b775 262 uint32_t FPGA_bus::get_SYS_data(void)
jimherd 6:e68defb7b775 263 {
jimherd 6:e68defb7b775 264 do_transaction(READ_REGISTER_CMD, SYS_DATA_REG_ADDR, NULL, &data, &status);
jimherd 6:e68defb7b775 265 sys_data.major_version = (data & 0x0000000F);
jimherd 6:e68defb7b775 266 sys_data.minor_version = (data >> 4) & 0x0000000F;
jimherd 6:e68defb7b775 267 sys_data.number_of_PWM_channels = (data >> 8) & 0x0000000F;
jimherd 6:e68defb7b775 268 sys_data.number_of_QE_channels = (data >> 8) & 0x0000000F;
jimherd 6:e68defb7b775 269 sys_data.number_of_RC_channels = (data >> 8) & 0x0000000F;
jimherd 6:e68defb7b775 270
jimherd 6:e68defb7b775 271 global_FPGA_unit_error_flag = status;
jimherd 6:e68defb7b775 272 return data;
jimherd 0:9600ed6fd725 273 }