jim herd / FPGA_bus

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FPGA_bus.cpp@12:b9b4ff729fef, 2020-05-02 (annotated)

Committer:
jimherd
Date:
Sat May 02 19:07:00 2020 +0000
Revision:
12:b9b4ff729fef
Parent:
7:c0bef9c1f5d5
Parent:
10:56a045a02047
Child:
14:b56473e54f6f
fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jimherd 0:9600ed6fd725 1 /*
jimherd 0:9600ed6fd725 2 * FPGA_bus : 8-bit bi-directional bus between uP and FPGA
jimherd 0:9600ed6fd725 3 */
jimherd 0:9600ed6fd725 4 #include "mbed.h"
jimherd 0:9600ed6fd725 5 #include "FPGA_bus.h"
jimherd 0:9600ed6fd725 6
jimherd 0:9600ed6fd725 7 /** create a FPGA_bus object connecting uP to FPGA
jimherd 0:9600ed6fd725 8 *
jimherd 0:9600ed6fd725 9 * @param nos_PWM Number of PWM channels (default = 4)
jimherd 0:9600ed6fd725 10 * @param nos_QE Number of Quadrature Encoder channels (default = 4)
jimherd 0:9600ed6fd725 11 * @param nos_servo Number of RC servo channels (default = 8)
jimherd 0:9600ed6fd725 12 *
jimherd 0:9600ed6fd725 13 * Notes
jimherd 0:9600ed6fd725 14 * You can only change the defaults by recompiling the SystemVerilog code
jimherd 0:9600ed6fd725 15 * on the FPGA.
jimherd 12:b9b4ff729fef 16 <<<<<<< working copy
jimherd 7:c0bef9c1f5d5 17 */
jimherd 7:c0bef9c1f5d5 18
jimherd 7:c0bef9c1f5d5 19 /*
jimherd 12:b9b4ff729fef 20 =======
jimherd 0:9600ed6fd725 21 */
jimherd 0:9600ed6fd725 22 FPGA_bus::FPGA_bus(int nos_PWM = NOS_PWM_CHANNELS,
jimherd 0:9600ed6fd725 23 int nos_QE = NOS_QE_CHANNELS,
jimherd 0:9600ed6fd725 24 int nos_servo = NOS_RC_CHANNELS)
jimherd 0:9600ed6fd725 25
jimherd 0:9600ed6fd725 26 : async_uP_start(ASYNC_UP_START_PIN),
jimherd 0:9600ed6fd725 27 async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
jimherd 0:9600ed6fd725 28 async_uP_RW(ASYNC_UP_RW_PIN),
jimherd 0:9600ed6fd725 29 async_uP_reset(ASYNC_UP_RESET_PIN),
jimherd 0:9600ed6fd725 30 uP_ack(ASYNC_UP_ACK_PIN),
jimherd 9:6fe95fb0c7ea 31 uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
jimherd 9:6fe95fb0c7ea 32 log_pin(LOG_PIN)
jimherd 0:9600ed6fd725 33 {
jimherd 0:9600ed6fd725 34 _nos_PWM_units = nos_PWM;
jimherd 0:9600ed6fd725 35 _nos_QE_units = nos_QE;
jimherd 0:9600ed6fd725 36 _nos_servo_units = nos_servo;
jimherd 0:9600ed6fd725 37
jimherd 0:9600ed6fd725 38 async_uP_start = LOW;
jimherd 0:9600ed6fd725 39 }
jimherd 0:9600ed6fd725 40
jimherd 12:b9b4ff729fef 41 >>>>>>> merge rev
jimherd 0:9600ed6fd725 42 FPGA_bus::FPGA_bus(void)
jimherd 0:9600ed6fd725 43 : async_uP_start(ASYNC_UP_START_PIN),
jimherd 0:9600ed6fd725 44 async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
jimherd 0:9600ed6fd725 45 async_uP_RW(ASYNC_UP_RW_PIN),
jimherd 0:9600ed6fd725 46 async_uP_reset(ASYNC_UP_RESET_PIN),
jimherd 0:9600ed6fd725 47 uP_ack(ASYNC_UP_ACK_PIN),
jimherd 9:6fe95fb0c7ea 48 uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
jimherd 9:6fe95fb0c7ea 49 log_pin(LOG_PIN)
jimherd 0:9600ed6fd725 50 {
jimherd 0:9600ed6fd725 51 _nos_PWM_units = NOS_PWM_CHANNELS;
jimherd 0:9600ed6fd725 52 _nos_QE_units = NOS_QE_CHANNELS;
jimherd 0:9600ed6fd725 53 _nos_servo_units = NOS_RC_CHANNELS;
jimherd 0:9600ed6fd725 54
jimherd 0:9600ed6fd725 55 async_uP_start = LOW;
jimherd 0:9600ed6fd725 56 }
jimherd 7:c0bef9c1f5d5 57 */
jimherd 7:c0bef9c1f5d5 58 FPGA_bus::FPGA_bus(int nos_PWM /* = NOS_PWM_CHANNELS */,
jimherd 7:c0bef9c1f5d5 59 int nos_QE /* = NOS_QE_CHANNELS */,
jimherd 7:c0bef9c1f5d5 60 int nos_servo /* = NOS_RC_CHANNELS */ )
jimherd 7:c0bef9c1f5d5 61
jimherd 7:c0bef9c1f5d5 62 : async_uP_start(ASYNC_UP_START_PIN),
jimherd 7:c0bef9c1f5d5 63 async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
jimherd 7:c0bef9c1f5d5 64 async_uP_RW(ASYNC_UP_RW_PIN),
jimherd 7:c0bef9c1f5d5 65 async_uP_reset(ASYNC_UP_RESET_PIN),
jimherd 7:c0bef9c1f5d5 66 uP_ack(ASYNC_UP_ACK_PIN),
jimherd 7:c0bef9c1f5d5 67 uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
jimherd 7:c0bef9c1f5d5 68
jimherd 7:c0bef9c1f5d5 69 _nos_PWM_units(nos_PWM),
jimherd 7:c0bef9c1f5d5 70 _nos_QE_units(nos_QE),
jimherd 7:c0bef9c1f5d5 71 _nos_servo_units(nos_servo)
jimherd 7:c0bef9c1f5d5 72 {
jimherd 7:c0bef9c1f5d5 73 /* _nos_PWM_units = nos_PWM;
jimherd 7:c0bef9c1f5d5 74 _nos_QE_units = nos_QE;
jimherd 7:c0bef9c1f5d5 75 _nos_servo_units = nos_servo; */
jimherd 7:c0bef9c1f5d5 76
jimherd 7:c0bef9c1f5d5 77 async_uP_start = LOW;
jimherd 7:c0bef9c1f5d5 78 }
jimherd 0:9600ed6fd725 79
jimherd 0:9600ed6fd725 80
jimherd 0:9600ed6fd725 81 void FPGA_bus::initialise(void)
jimherd 0:9600ed6fd725 82 {
jimherd 0:9600ed6fd725 83 // GPIOC Periph clock enable
jimherd 0:9600ed6fd725 84
jimherd 0:9600ed6fd725 85 ENABLE_GPIO_SUBSYSTEM;
jimherd 0:9600ed6fd725 86 wait_us(2);
jimherd 0:9600ed6fd725 87
jimherd 0:9600ed6fd725 88 async_uP_start = LOW;
jimherd 0:9600ed6fd725 89 async_uP_reset = HIGH;
jimherd 0:9600ed6fd725 90 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 91 async_uP_RW = LOW;
jimherd 0:9600ed6fd725 92
jimherd 0:9600ed6fd725 93 async_uP_reset = LOW; // generate low reset pulse
jimherd 0:9600ed6fd725 94 wait_us(20);
jimherd 0:9600ed6fd725 95 async_uP_reset = HIGH;
jimherd 0:9600ed6fd725 96 wait_us(20);
jimherd 1:b819a72b3b5d 97
jimherd 1:b819a72b3b5d 98 global_FPGA_unit_error_flag = NO_ERROR;
jimherd 9:6fe95fb0c7ea 99 log_pin = LOW;
jimherd 0:9600ed6fd725 100 }
jimherd 0:9600ed6fd725 101
jimherd 0:9600ed6fd725 102 void FPGA_bus::do_start(void)
jimherd 0:9600ed6fd725 103 {
jimherd 0:9600ed6fd725 104 async_uP_start = HIGH;
jimherd 0:9600ed6fd725 105 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 106 async_uP_start = LOW;
jimherd 0:9600ed6fd725 107 }
jimherd 0:9600ed6fd725 108
jimherd 0:9600ed6fd725 109 void FPGA_bus::do_end(void)
jimherd 0:9600ed6fd725 110 {
jimherd 0:9600ed6fd725 111 while (uP_ack == HIGH)
jimherd 0:9600ed6fd725 112 ;
jimherd 0:9600ed6fd725 113 async_uP_start = LOW;
jimherd 0:9600ed6fd725 114 }
jimherd 0:9600ed6fd725 115
jimherd 0:9600ed6fd725 116 void FPGA_bus::write_byte(uint32_t byte_value)
jimherd 0:9600ed6fd725 117 {
jimherd 0:9600ed6fd725 118 SET_BUS_OUTPUT;
jimherd 0:9600ed6fd725 119 OUTPUT_BYTE_TO_BUS(byte_value);
jimherd 0:9600ed6fd725 120 async_uP_RW = WRITE_BUS;
jimherd 0:9600ed6fd725 121 async_uP_handshake_1 = HIGH;
jimherd 0:9600ed6fd725 122 while (uP_handshake_2 == LOW)
jimherd 0:9600ed6fd725 123 ;
jimherd 0:9600ed6fd725 124 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 125 while (uP_handshake_2 == HIGH)
jimherd 0:9600ed6fd725 126 ;
jimherd 0:9600ed6fd725 127 }
jimherd 0:9600ed6fd725 128
jimherd 0:9600ed6fd725 129 uint32_t FPGA_bus::read_byte(void)
jimherd 0:9600ed6fd725 130 {
jimherd 0:9600ed6fd725 131 SET_BUS_INPUT;
jimherd 0:9600ed6fd725 132 async_uP_RW = READ_BUS;
jimherd 0:9600ed6fd725 133 while (uP_handshake_2 == LOW)
jimherd 0:9600ed6fd725 134 ;
jimherd 0:9600ed6fd725 135 data = INPUT_BYTE_FROM_BUS;
jimherd 0:9600ed6fd725 136 async_uP_handshake_1 = HIGH;
jimherd 0:9600ed6fd725 137 while (uP_handshake_2 == HIGH)
jimherd 0:9600ed6fd725 138 ;
jimherd 0:9600ed6fd725 139 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 140 return data;
jimherd 0:9600ed6fd725 141 }
jimherd 0:9600ed6fd725 142
jimherd 0:9600ed6fd725 143 void FPGA_bus::do_write(uint32_t command,
jimherd 0:9600ed6fd725 144 uint32_t register_address,
jimherd 0:9600ed6fd725 145 uint32_t register_data)
jimherd 0:9600ed6fd725 146 {
jimherd 0:9600ed6fd725 147 write_byte(command);
jimherd 0:9600ed6fd725 148 write_byte(register_address);
jimherd 0:9600ed6fd725 149 write_byte(register_data);
jimherd 0:9600ed6fd725 150 write_byte(register_data>>8);
jimherd 0:9600ed6fd725 151 write_byte(register_data>>16);
jimherd 0:9600ed6fd725 152 write_byte(register_data>>24);
jimherd 0:9600ed6fd725 153 }
jimherd 0:9600ed6fd725 154
jimherd 0:9600ed6fd725 155 void FPGA_bus::do_read(received_packet_t *buffer)
jimherd 0:9600ed6fd725 156 {
jimherd 0:9600ed6fd725 157 for (int i=0; i < (NOS_RECEIVED_PACKET_WORDS<<2) ; i++) {
jimherd 0:9600ed6fd725 158 buffer->byte_data[i] = (uint8_t)read_byte();
jimherd 0:9600ed6fd725 159 }
jimherd 0:9600ed6fd725 160 }
jimherd 0:9600ed6fd725 161
jimherd 0:9600ed6fd725 162 void FPGA_bus::do_transaction(uint32_t command,
jimherd 0:9600ed6fd725 163 uint32_t register_address,
jimherd 0:9600ed6fd725 164 uint32_t register_data,
jimherd 0:9600ed6fd725 165 uint32_t *data,
jimherd 0:9600ed6fd725 166 uint32_t *status)
jimherd 0:9600ed6fd725 167 {
jimherd 9:6fe95fb0c7ea 168 log_pin = HIGH;
jimherd 0:9600ed6fd725 169 do_start();
jimherd 0:9600ed6fd725 170 do_write(command, register_address, register_data);
jimherd 0:9600ed6fd725 171 do_read(&in_pkt);
jimherd 0:9600ed6fd725 172 do_end();
jimherd 9:6fe95fb0c7ea 173 log_pin = LOW;
jimherd 0:9600ed6fd725 174 *data = in_pkt.word_data[0];
jimherd 0:9600ed6fd725 175 *status = in_pkt.word_data[1];
jimherd 0:9600ed6fd725 176 }
jimherd 0:9600ed6fd725 177
jimherd 0:9600ed6fd725 178 uint32_t FPGA_bus::do_command(FPGA_packet_t cmd_packet)
jimherd 0:9600ed6fd725 179 {
jimherd 0:9600ed6fd725 180 async_uP_start = LOW;
jimherd 0:9600ed6fd725 181 return 0;
jimherd 0:9600ed6fd725 182 }
jimherd 0:9600ed6fd725 183
jimherd 1:b819a72b3b5d 184 void FPGA_bus::set_PWM_period(uint32_t channel, float frequency)
jimherd 0:9600ed6fd725 185 {
jimherd 4:e5d36eee9245 186 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_PERIOD);
jimherd 0:9600ed6fd725 187 uint32_t period_value = (uint32_t)(1000000/(20 * frequency));
jimherd 4:e5d36eee9245 188 do_transaction(WRITE_REGISTER_CMD, register_address, period_value, &data, &status);
jimherd 0:9600ed6fd725 189 sys_data.PWM_period_value[channel] = period_value;
jimherd 1:b819a72b3b5d 190 global_FPGA_unit_error_flag = status;
jimherd 0:9600ed6fd725 191 }
jimherd 0:9600ed6fd725 192
jimherd 1:b819a72b3b5d 193 void FPGA_bus::set_PWM_duty(uint32_t channel, float percentage)
jimherd 0:9600ed6fd725 194 {
jimherd 4:e5d36eee9245 195 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_ON_TIME);
jimherd 0:9600ed6fd725 196 uint32_t duty_value = (uint32_t)((sys_data.PWM_period_value[channel] * percentage) / 100);
jimherd 4:e5d36eee9245 197 do_transaction(WRITE_REGISTER_CMD, register_address , duty_value, &data, &status);
jimherd 0:9600ed6fd725 198 sys_data.PWM_duty_value[channel] = duty_value;
jimherd 1:b819a72b3b5d 199 global_FPGA_unit_error_flag = status;;
jimherd 0:9600ed6fd725 200 }
jimherd 0:9600ed6fd725 201
jimherd 1:b819a72b3b5d 202 void FPGA_bus::PWM_enable(uint32_t channel)
jimherd 0:9600ed6fd725 203 {
jimherd 4:e5d36eee9245 204 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
jimherd 4:e5d36eee9245 205 do_transaction(WRITE_REGISTER_CMD, register_address , 1, &data, &status);
jimherd 0:9600ed6fd725 206 // sys_data.PWM_duty_value[channel] = duty_value;
jimherd 1:b819a72b3b5d 207 global_FPGA_unit_error_flag = status;;
jimherd 0:9600ed6fd725 208 }
jimherd 0:9600ed6fd725 209
jimherd 1:b819a72b3b5d 210 void FPGA_bus::PWM_config(uint32_t channel, uint32_t config_value)
jimherd 0:9600ed6fd725 211 {
jimherd 4:e5d36eee9245 212 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
jimherd 4:e5d36eee9245 213 do_transaction(WRITE_REGISTER_CMD, register_address , config_value, &data, &status);
jimherd 0:9600ed6fd725 214 sys_data.PWM_duty_value[channel] = config_value;
jimherd 1:b819a72b3b5d 215 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 216 }
jimherd 1:b819a72b3b5d 217
jimherd 4:e5d36eee9245 218 void FPGA_bus::set_RC_period(void)
jimherd 1:b819a72b3b5d 219 {
jimherd 4:e5d36eee9245 220 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), 1000000, &data, &status);
jimherd 6:e68defb7b775 221 global_FPGA_unit_error_flag = status;
jimherd 1:b819a72b3b5d 222 }
jimherd 1:b819a72b3b5d 223
jimherd 4:e5d36eee9245 224 void FPGA_bus::set_RC_period(uint32_t duty_uS)
jimherd 1:b819a72b3b5d 225 {
jimherd 1:b819a72b3b5d 226 uint32_t nos_20nS_ticks = ((duty_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
jimherd 4:e5d36eee9245 227 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
jimherd 6:e68defb7b775 228 global_FPGA_unit_error_flag = status;
jimherd 1:b819a72b3b5d 229 }
jimherd 1:b819a72b3b5d 230
jimherd 1:b819a72b3b5d 231 void FPGA_bus :: set_RC_pulse(uint32_t channel, uint32_t pulse_uS)
jimherd 1:b819a72b3b5d 232 {
jimherd 1:b819a72b3b5d 233 uint32_t nos_20nS_ticks = ((pulse_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
jimherd 4:e5d36eee9245 234 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_ON_TIME + channel), nos_20nS_ticks, &data, &status);
jimherd 1:b819a72b3b5d 235 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 236 }
jimherd 1:b819a72b3b5d 237
jimherd 4:e5d36eee9245 238 void FPGA_bus::enable_RC_channel(uint32_t channel)
jimherd 1:b819a72b3b5d 239 {
jimherd 4:e5d36eee9245 240 do_transaction(READ_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), NULL, &data, &status);
jimherd 2:fd5c862b86db 241 int32_t config = (data || (0x01 << channel)) + GLOBAL_RC_ENABLE;
jimherd 4:e5d36eee9245 242 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), config, &data, &status);
jimherd 3:cf36c2d4208f 243 global_FPGA_unit_error_flag = status;
jimherd 2:fd5c862b86db 244 }
jimherd 2:fd5c862b86db 245
jimherd 4:e5d36eee9245 246 void FPGA_bus::disable_RC_channel(uint32_t channel)
jimherd 2:fd5c862b86db 247 {
jimherd 4:e5d36eee9245 248 do_transaction(READ_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), NULL, &data, &status);
jimherd 4:e5d36eee9245 249 uint32_t config = data && ~(0x01 << channel);
jimherd 4:e5d36eee9245 250 do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_CONFIG), config, &data, &status);
jimherd 1:b819a72b3b5d 251 global_FPGA_unit_error_flag = status;
jimherd 4:e5d36eee9245 252 }
jimherd 4:e5d36eee9245 253
jimherd 9:6fe95fb0c7ea 254 void FPGA_bus::QE_config(uint32_t channel, uint32_t config_value)
jimherd 9:6fe95fb0c7ea 255 {
jimherd 9:6fe95fb0c7ea 256 uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
jimherd 9:6fe95fb0c7ea 257 do_transaction(WRITE_REGISTER_CMD, register_address , config_value, &data, &status);
jimherd 9:6fe95fb0c7ea 258 global_FPGA_unit_error_flag = status;;
jimherd 9:6fe95fb0c7ea 259 }
jimherd 9:6fe95fb0c7ea 260
jimherd 9:6fe95fb0c7ea 261 void FPGA_bus::enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time)
jimherd 4:e5d36eee9245 262 {
jimherd 9:6fe95fb0c7ea 263 uint32_t register_base = (QE_BASE + (channel * NOS_QE_REGISTERS));
jimherd 9:6fe95fb0c7ea 264 do_transaction(WRITE_REGISTER_CMD, (register_base + QE_SIM_PHASE_TIME), phase_time, &data, &status);
jimherd 5:64c677e9995c 265 global_FPGA_unit_error_flag = status;
jimherd 10:56a045a02047 266 if (status != NO_ERROR) {
jimherd 10:56a045a02047 267 return;
jimherd 10:56a045a02047 268 }
jimherd 10:56a045a02047 269 do_transaction(WRITE_REGISTER_CMD, (register_base + QE_CONFIG), config_value, &data, &status);
jimherd 10:56a045a02047 270 global_FPGA_unit_error_flag = status;
jimherd 5:64c677e9995c 271 }
jimherd 5:64c677e9995c 272
jimherd 5:64c677e9995c 273 uint32_t FPGA_bus::read_speed_measure(uint32_t channel)
jimherd 5:64c677e9995c 274 {
jimherd 8:65d1b1a7bfcc 275 uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_SPEED_BUFFER);
jimherd 5:64c677e9995c 276 do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
jimherd 5:64c677e9995c 277 global_FPGA_unit_error_flag = status;
jimherd 5:64c677e9995c 278 return data;
jimherd 6:e68defb7b775 279 }
jimherd 6:e68defb7b775 280
jimherd 10:56a045a02047 281 uint32_t FPGA_bus::read_count_measure(uint32_t channel)
jimherd 10:56a045a02047 282 {
jimherd 10:56a045a02047 283 uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_COUNT_BUFFER);
jimherd 10:56a045a02047 284 do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
jimherd 10:56a045a02047 285 global_FPGA_unit_error_flag = status;
jimherd 10:56a045a02047 286 return data;
jimherd 10:56a045a02047 287 }
jimherd 10:56a045a02047 288
jimherd 6:e68defb7b775 289 uint32_t FPGA_bus::get_SYS_data(void)
jimherd 6:e68defb7b775 290 {
jimherd 6:e68defb7b775 291 do_transaction(READ_REGISTER_CMD, SYS_DATA_REG_ADDR, NULL, &data, &status);
jimherd 6:e68defb7b775 292 sys_data.major_version = (data & 0x0000000F);
jimherd 6:e68defb7b775 293 sys_data.minor_version = (data >> 4) & 0x0000000F;
jimherd 6:e68defb7b775 294 sys_data.number_of_PWM_channels = (data >> 8) & 0x0000000F;
jimherd 6:e68defb7b775 295 sys_data.number_of_QE_channels = (data >> 8) & 0x0000000F;
jimherd 6:e68defb7b775 296 sys_data.number_of_RC_channels = (data >> 8) & 0x0000000F;
jimherd 6:e68defb7b775 297
jimherd 6:e68defb7b775 298 global_FPGA_unit_error_flag = status;
jimherd 6:e68defb7b775 299 return data;
jimherd 0:9600ed6fd725 300 }