jim herd / FPGA_bus

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Files at this revision

API Documentation at this revision

Revision 6:e68defb7b775, committed 2019-05-08

Comitter:
jimherd
Date:
Wed May 08 16:41:44 2019 +0000
Parent:
5:64c677e9995c
Child:
7:c0bef9c1f5d5
Child:
8:65d1b1a7bfcc
Commit message:
Added code to read system data from FPGA

Changed in this revision

FPGA_bus.cpp Show annotated file Show diff for this revision Revisions of this file
FPGA_bus.h Show annotated file Show diff for this revision Revisions of this file 
--- a/FPGA_bus.cpp	Thu Apr 18 22:59:26 2019 +0000
+++ b/FPGA_bus.cpp	Wed May 08 16:41:44 2019 +0000
@@ -191,14 +191,14 @@
 void FPGA_bus::set_RC_period(void)
 {
     do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), 1000000, &data, &status);
-    global_FPGA_unit_error_flag = status;;
+    global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus::set_RC_period(uint32_t duty_uS)
 {
     uint32_t nos_20nS_ticks = ((duty_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
     do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
-    global_FPGA_unit_error_flag = status;;
+    global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus :: set_RC_pulse(uint32_t channel, uint32_t pulse_uS)
@@ -238,4 +238,17 @@
     do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
     global_FPGA_unit_error_flag = status;
     return data;
+}
+
+uint32_t FPGA_bus::get_SYS_data(void)
+{
+    do_transaction(READ_REGISTER_CMD, SYS_DATA_REG_ADDR, NULL, &data, &status);
+    sys_data.major_version          = (data & 0x0000000F);
+    sys_data.minor_version          = (data >> 4) & 0x0000000F;
+    sys_data.number_of_PWM_channels = (data >> 8) & 0x0000000F;
+    sys_data.number_of_QE_channels  = (data >> 8) & 0x0000000F;
+    sys_data.number_of_RC_channels  = (data >> 8) & 0x0000000F;
+    
+    global_FPGA_unit_error_flag = status;
+    return data;
 }
\ No newline at end of file

--- a/FPGA_bus.h	Thu Apr 18 22:59:26 2019 +0000
+++ b/FPGA_bus.h	Wed May 08 16:41:44 2019 +0000
@@ -81,6 +81,11 @@
 enum {READ_BUS=0, WRITE_BUS=1};
 enum {LOW=0, HIGH=1};
 
+//
+// SYS_data registers
+
+enum {SYS_DATA_REG_ADDR=0};
+
 // PWM registers
 //
 enum {PWM_PERIOD=0, PWM_ON_TIME=1, PWM_CONFIG=2, PWM_STATUS=3};
@@ -130,6 +135,8 @@
      void enable_speed_measure(uint32_t channel);
      uint32_t read_speed_measure(uint32_t channel);
      
+     uint32_t get_SYS_data(void);
+     
      int32_t global_FPGA_unit_error_flag;
      
 protected:
@@ -163,8 +170,14 @@
     DigitalIn  uP_handshake_2;
     
     struct SYS_data {
-        uint32_t PWM_period_value[NOS_PWM_CHANNELS];
-        uint32_t PWM_duty_value[NOS_PWM_CHANNELS];
+        uint8_t major_version;
+        uint8_t minor_version;
+        uint8_t number_of_PWM_channels;
+        uint8_t number_of_QE_channels;
+        uint8_t number_of_RC_channels;
+        uint8_t PWM_period_value[NOS_PWM_CHANNELS];
+        uint8_t PWM_duty_value[NOS_PWM_CHANNELS];
+        uint8_t pad1;
     } sys_data;
 };