jim herd / FPGA_bus

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Diff: FPGA_bus.cpp

Revision:
15:6420b52d30cc
Parent:
14:b56473e54f6f
Child:
16:d69a36a541c5
--- a/FPGA_bus.cpp	Fri May 22 16:52:10 2020 +0000
+++ b/FPGA_bus.cpp	Fri May 22 22:53:46 2020 +0000
@@ -31,13 +31,20 @@
                     uP_ack(ASYNC_UP_ACK_PIN),
                     uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
                     log_pin(LOG_PIN)
+                    
         {
         async_uP_start   = LOW;
+        PWM_base         = 0;
+        QE_base          = 0;
+        RC_base          = 0;
 }
 
 
 void  FPGA_bus::initialise(void)
 {
+
+    update_FPGA_register_pointers();
+    
     // GPIOC Periph clock enable
     
     ENABLE_GPIO_SUBSYSTEM;
@@ -255,4 +262,11 @@
     
     global_FPGA_unit_error_flag = status;
     return data;
+}
+
+void FPGA_bus::update_FPGA_register_pointers(void) {
+    
+    PWM_base = 1;
+    QE_base  = ((NOS_PWM_REGISTERS * _nos_PWM_units) + PWM_base);
+    RC_base  = ((NOS_QE_REGISTERS * _nos_QE_units) + QE_base);   
 }
\ No newline at end of file