jim herd / FPGA_bus

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Diff: FPGA_bus.cpp

Revision:
17:928b755cba80
Parent:
16:d69a36a541c5
Child:
20:aacf2ebd93ff
--- a/FPGA_bus.cpp	Sat May 23 11:58:57 2020 +0000
+++ b/FPGA_bus.cpp	Sat May 23 23:28:13 2020 +0000
@@ -152,6 +152,7 @@
     uint32_t period_value = (uint32_t)(1000000/(20 * frequency));
     do_transaction(WRITE_REGISTER_CMD, register_address, period_value, &data, &status); 
     sys_data.PWM_period_value[channel] = period_value;
+    do_transaction(READ_REGISTER_CMD, (1 + (channel * NOS_PWM_REGISTERS)) , NULL, &data, &status);
     global_FPGA_unit_error_flag = status;
 }
 
@@ -168,7 +169,6 @@
 {
     uint32_t register_address = ((PWM_base + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
     do_transaction(WRITE_REGISTER_CMD, register_address , 1, &data, &status);
- //   sys_data.PWM_duty_value[channel] = duty_value;
     global_FPGA_unit_error_flag = status;;
 }