jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

FPGA_bus.cpp@1:b819a72b3b5d, 2019-04-17 (annotated)

Committer:
jimherd
Date:
Wed Apr 17 14:32:22 2019 +0000
Revision:
1:b819a72b3b5d
Parent:
0:9600ed6fd725
Child:
2:fd5c862b86db
Added higher level routines to set RC channels.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jimherd 0:9600ed6fd725 1 /*
jimherd 0:9600ed6fd725 2 * FPGA_bus : 8-bit bi-directional bus between uP and FPGA
jimherd 0:9600ed6fd725 3 */
jimherd 0:9600ed6fd725 4 #include "mbed.h"
jimherd 0:9600ed6fd725 5 #include "FPGA_bus.h"
jimherd 0:9600ed6fd725 6
jimherd 0:9600ed6fd725 7 /** create a FPGA_bus object connecting uP to FPGA
jimherd 0:9600ed6fd725 8 *
jimherd 0:9600ed6fd725 9 * @param nos_PWM Number of PWM channels (default = 4)
jimherd 0:9600ed6fd725 10 * @param nos_QE Number of Quadrature Encoder channels (default = 4)
jimherd 0:9600ed6fd725 11 * @param nos_servo Number of RC servo channels (default = 8)
jimherd 0:9600ed6fd725 12 *
jimherd 0:9600ed6fd725 13 * Notes
jimherd 0:9600ed6fd725 14 * You can only change the defaults by recompiling the SystemVerilog code
jimherd 0:9600ed6fd725 15 * on the FPGA.
jimherd 0:9600ed6fd725 16 */
jimherd 0:9600ed6fd725 17 FPGA_bus::FPGA_bus(int nos_PWM = NOS_PWM_CHANNELS,
jimherd 0:9600ed6fd725 18 int nos_QE = NOS_QE_CHANNELS,
jimherd 0:9600ed6fd725 19 int nos_servo = NOS_RC_CHANNELS)
jimherd 0:9600ed6fd725 20
jimherd 0:9600ed6fd725 21 : async_uP_start(ASYNC_UP_START_PIN),
jimherd 0:9600ed6fd725 22 async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
jimherd 0:9600ed6fd725 23 async_uP_RW(ASYNC_UP_RW_PIN),
jimherd 0:9600ed6fd725 24 async_uP_reset(ASYNC_UP_RESET_PIN),
jimherd 0:9600ed6fd725 25 uP_ack(ASYNC_UP_ACK_PIN),
jimherd 0:9600ed6fd725 26 uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN)
jimherd 0:9600ed6fd725 27 {
jimherd 0:9600ed6fd725 28 _nos_PWM_units = nos_PWM;
jimherd 0:9600ed6fd725 29 _nos_QE_units = nos_QE;
jimherd 0:9600ed6fd725 30 _nos_servo_units = nos_servo;
jimherd 0:9600ed6fd725 31
jimherd 0:9600ed6fd725 32 async_uP_start = LOW;
jimherd 0:9600ed6fd725 33 }
jimherd 0:9600ed6fd725 34
jimherd 0:9600ed6fd725 35 FPGA_bus::FPGA_bus(void)
jimherd 0:9600ed6fd725 36 : async_uP_start(ASYNC_UP_START_PIN),
jimherd 0:9600ed6fd725 37 async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
jimherd 0:9600ed6fd725 38 async_uP_RW(ASYNC_UP_RW_PIN),
jimherd 0:9600ed6fd725 39 async_uP_reset(ASYNC_UP_RESET_PIN),
jimherd 0:9600ed6fd725 40 uP_ack(ASYNC_UP_ACK_PIN),
jimherd 0:9600ed6fd725 41 uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN)
jimherd 0:9600ed6fd725 42 {
jimherd 0:9600ed6fd725 43 _nos_PWM_units = NOS_PWM_CHANNELS;
jimherd 0:9600ed6fd725 44 _nos_QE_units = NOS_QE_CHANNELS;
jimherd 0:9600ed6fd725 45 _nos_servo_units = NOS_RC_CHANNELS;
jimherd 0:9600ed6fd725 46
jimherd 0:9600ed6fd725 47 async_uP_start = LOW;
jimherd 0:9600ed6fd725 48 }
jimherd 0:9600ed6fd725 49
jimherd 0:9600ed6fd725 50
jimherd 0:9600ed6fd725 51
jimherd 0:9600ed6fd725 52 void FPGA_bus::initialise(void)
jimherd 0:9600ed6fd725 53 {
jimherd 0:9600ed6fd725 54 // GPIOC Periph clock enable
jimherd 0:9600ed6fd725 55
jimherd 0:9600ed6fd725 56 ENABLE_GPIO_SUBSYSTEM;
jimherd 0:9600ed6fd725 57 wait_us(2);
jimherd 0:9600ed6fd725 58
jimherd 0:9600ed6fd725 59 async_uP_start = LOW;
jimherd 0:9600ed6fd725 60 async_uP_reset = HIGH;
jimherd 0:9600ed6fd725 61 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 62 async_uP_RW = LOW;
jimherd 0:9600ed6fd725 63
jimherd 0:9600ed6fd725 64 async_uP_reset = LOW; // generate low reset pulse
jimherd 0:9600ed6fd725 65 wait_us(20);
jimherd 0:9600ed6fd725 66 async_uP_reset = HIGH;
jimherd 0:9600ed6fd725 67 wait_us(20);
jimherd 1:b819a72b3b5d 68
jimherd 1:b819a72b3b5d 69 global_FPGA_unit_error_flag = NO_ERROR;
jimherd 0:9600ed6fd725 70 }
jimherd 0:9600ed6fd725 71
jimherd 0:9600ed6fd725 72 void FPGA_bus::do_start(void)
jimherd 0:9600ed6fd725 73 {
jimherd 0:9600ed6fd725 74 async_uP_start = HIGH;
jimherd 0:9600ed6fd725 75 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 76 async_uP_start = LOW;
jimherd 0:9600ed6fd725 77 }
jimherd 0:9600ed6fd725 78
jimherd 0:9600ed6fd725 79 void FPGA_bus::do_end(void)
jimherd 0:9600ed6fd725 80 {
jimherd 0:9600ed6fd725 81 while (uP_ack == HIGH)
jimherd 0:9600ed6fd725 82 ;
jimherd 0:9600ed6fd725 83 async_uP_start = LOW;
jimherd 0:9600ed6fd725 84 }
jimherd 0:9600ed6fd725 85
jimherd 0:9600ed6fd725 86 void FPGA_bus::write_byte(uint32_t byte_value)
jimherd 0:9600ed6fd725 87 {
jimherd 0:9600ed6fd725 88 SET_BUS_OUTPUT;
jimherd 0:9600ed6fd725 89 OUTPUT_BYTE_TO_BUS(byte_value);
jimherd 0:9600ed6fd725 90 async_uP_RW = WRITE_BUS;
jimherd 0:9600ed6fd725 91 async_uP_handshake_1 = HIGH;
jimherd 0:9600ed6fd725 92 while (uP_handshake_2 == LOW)
jimherd 0:9600ed6fd725 93 ;
jimherd 0:9600ed6fd725 94 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 95 while (uP_handshake_2 == HIGH)
jimherd 0:9600ed6fd725 96 ;
jimherd 0:9600ed6fd725 97 }
jimherd 0:9600ed6fd725 98
jimherd 0:9600ed6fd725 99 uint32_t FPGA_bus::read_byte(void)
jimherd 0:9600ed6fd725 100 {
jimherd 0:9600ed6fd725 101 SET_BUS_INPUT;
jimherd 0:9600ed6fd725 102 async_uP_RW = READ_BUS;
jimherd 0:9600ed6fd725 103 while (uP_handshake_2 == LOW)
jimherd 0:9600ed6fd725 104 ;
jimherd 0:9600ed6fd725 105 data = INPUT_BYTE_FROM_BUS;
jimherd 0:9600ed6fd725 106 async_uP_handshake_1 = HIGH;
jimherd 0:9600ed6fd725 107 while (uP_handshake_2 == HIGH)
jimherd 0:9600ed6fd725 108 ;
jimherd 0:9600ed6fd725 109 async_uP_handshake_1 = LOW;
jimherd 0:9600ed6fd725 110 return data;
jimherd 0:9600ed6fd725 111 }
jimherd 0:9600ed6fd725 112
jimherd 0:9600ed6fd725 113 void FPGA_bus::do_write(uint32_t command,
jimherd 0:9600ed6fd725 114 uint32_t register_address,
jimherd 0:9600ed6fd725 115 uint32_t register_data)
jimherd 0:9600ed6fd725 116 {
jimherd 0:9600ed6fd725 117 write_byte(command);
jimherd 0:9600ed6fd725 118 write_byte(register_address);
jimherd 0:9600ed6fd725 119 write_byte(register_data);
jimherd 0:9600ed6fd725 120 write_byte(register_data>>8);
jimherd 0:9600ed6fd725 121 write_byte(register_data>>16);
jimherd 0:9600ed6fd725 122 write_byte(register_data>>24);
jimherd 0:9600ed6fd725 123 }
jimherd 0:9600ed6fd725 124
jimherd 0:9600ed6fd725 125 void FPGA_bus::do_read(received_packet_t *buffer)
jimherd 0:9600ed6fd725 126 {
jimherd 0:9600ed6fd725 127 for (int i=0; i < (NOS_RECEIVED_PACKET_WORDS<<2) ; i++) {
jimherd 0:9600ed6fd725 128 buffer->byte_data[i] = (uint8_t)read_byte();
jimherd 0:9600ed6fd725 129 }
jimherd 0:9600ed6fd725 130 }
jimherd 0:9600ed6fd725 131
jimherd 0:9600ed6fd725 132 void FPGA_bus::do_transaction(uint32_t command,
jimherd 0:9600ed6fd725 133 uint32_t register_address,
jimherd 0:9600ed6fd725 134 uint32_t register_data,
jimherd 0:9600ed6fd725 135 uint32_t *data,
jimherd 0:9600ed6fd725 136 uint32_t *status)
jimherd 0:9600ed6fd725 137 {
jimherd 0:9600ed6fd725 138 do_start();
jimherd 0:9600ed6fd725 139 // pc.printf("\n1");
jimherd 0:9600ed6fd725 140 do_write(command, register_address, register_data);
jimherd 0:9600ed6fd725 141 // pc.printf(" 2");
jimherd 0:9600ed6fd725 142 do_read(&in_pkt);
jimherd 0:9600ed6fd725 143 // pc.printf(" 3");
jimherd 0:9600ed6fd725 144 do_end();
jimherd 0:9600ed6fd725 145 // pc.printf(" 4\n");
jimherd 0:9600ed6fd725 146 *data = in_pkt.word_data[0];
jimherd 0:9600ed6fd725 147 *status = in_pkt.word_data[1];
jimherd 0:9600ed6fd725 148 // pc.printf("data = %#08X :: status = %#08X\n", in_pkt.word_data[0], in_pkt.word_data[1]);
jimherd 0:9600ed6fd725 149 }
jimherd 0:9600ed6fd725 150
jimherd 0:9600ed6fd725 151 uint32_t FPGA_bus::do_command(FPGA_packet_t cmd_packet)
jimherd 0:9600ed6fd725 152 {
jimherd 0:9600ed6fd725 153 async_uP_start = LOW;
jimherd 0:9600ed6fd725 154 return 0;
jimherd 0:9600ed6fd725 155 }
jimherd 0:9600ed6fd725 156
jimherd 1:b819a72b3b5d 157 void FPGA_bus::set_PWM_period(uint32_t channel, float frequency)
jimherd 0:9600ed6fd725 158 {
jimherd 0:9600ed6fd725 159 uint32_t period_value = (uint32_t)(1000000/(20 * frequency));
jimherd 0:9600ed6fd725 160 do_transaction(WRITE_REGISTER_CMD, (channel + PWM_PERIOD) , period_value, &data, &status);
jimherd 0:9600ed6fd725 161 sys_data.PWM_period_value[channel] = period_value;
jimherd 1:b819a72b3b5d 162 global_FPGA_unit_error_flag = status;
jimherd 0:9600ed6fd725 163 }
jimherd 0:9600ed6fd725 164
jimherd 1:b819a72b3b5d 165 void FPGA_bus::set_PWM_duty(uint32_t channel, float percentage)
jimherd 0:9600ed6fd725 166 {
jimherd 0:9600ed6fd725 167 uint32_t duty_value = (uint32_t)((sys_data.PWM_period_value[channel] * percentage) / 100);
jimherd 0:9600ed6fd725 168 do_transaction(WRITE_REGISTER_CMD, (channel + PWM_ON_TIME) , duty_value, &data, &status);
jimherd 0:9600ed6fd725 169 sys_data.PWM_duty_value[channel] = duty_value;
jimherd 1:b819a72b3b5d 170 global_FPGA_unit_error_flag = status;;
jimherd 0:9600ed6fd725 171 }
jimherd 0:9600ed6fd725 172
jimherd 1:b819a72b3b5d 173 void FPGA_bus::PWM_enable(uint32_t channel)
jimherd 0:9600ed6fd725 174 {
jimherd 0:9600ed6fd725 175 do_transaction(WRITE_REGISTER_CMD, (channel + PWM_CONFIG) , 1, &data, &status);
jimherd 0:9600ed6fd725 176 // sys_data.PWM_duty_value[channel] = duty_value;
jimherd 1:b819a72b3b5d 177 global_FPGA_unit_error_flag = status;;
jimherd 0:9600ed6fd725 178 }
jimherd 0:9600ed6fd725 179
jimherd 1:b819a72b3b5d 180 void FPGA_bus::PWM_config(uint32_t channel, uint32_t config_value)
jimherd 0:9600ed6fd725 181 {
jimherd 0:9600ed6fd725 182 do_transaction(WRITE_REGISTER_CMD, (channel + PWM_CONFIG) , config_value, &data, &status);
jimherd 0:9600ed6fd725 183 sys_data.PWM_duty_value[channel] = config_value;
jimherd 1:b819a72b3b5d 184 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 185 }
jimherd 1:b819a72b3b5d 186
jimherd 1:b819a72b3b5d 187 void FPGA_bus::set_RC_duty(void)
jimherd 1:b819a72b3b5d 188 {
jimherd 1:b819a72b3b5d 189 do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_PERIOD), 1000000, &data, &status);
jimherd 1:b819a72b3b5d 190 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 191 }
jimherd 1:b819a72b3b5d 192
jimherd 1:b819a72b3b5d 193 void FPGA_bus::set_RC_duty(uint32_t duty_uS)
jimherd 1:b819a72b3b5d 194 {
jimherd 1:b819a72b3b5d 195 uint32_t nos_20nS_ticks = ((duty_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
jimherd 1:b819a72b3b5d 196 do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
jimherd 1:b819a72b3b5d 197 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 198 }
jimherd 1:b819a72b3b5d 199
jimherd 1:b819a72b3b5d 200 void FPGA_bus :: set_RC_pulse(uint32_t channel, uint32_t pulse_uS)
jimherd 1:b819a72b3b5d 201 {
jimherd 1:b819a72b3b5d 202 uint32_t nos_20nS_ticks = ((pulse_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
jimherd 1:b819a72b3b5d 203 do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
jimherd 1:b819a72b3b5d 204 global_FPGA_unit_error_flag = status;;
jimherd 1:b819a72b3b5d 205 }
jimherd 1:b819a72b3b5d 206
jimherd 1:b819a72b3b5d 207 void FPGA_bus ::enable_RC_channel(uint32_t channel)
jimherd 1:b819a72b3b5d 208 {
jimherd 1:b819a72b3b5d 209 do_transaction(READ_REGISTER_CMD, (RC_0 + RC_SERVO_CONFIG), NULL, &data, &status);
jimherd 1:b819a72b3b5d 210 int32_t config = data || (0x01 << channel);
jimherd 1:b819a72b3b5d 211 do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_CONFIG), config, &data, &status);
jimherd 1:b819a72b3b5d 212 global_FPGA_unit_error_flag = status;
jimherd 0:9600ed6fd725 213 }