Revision 0:e9fd5575b10e, committed 2019-10-18

Comitter:

anhtran

Date:

Fri Oct 18 03:09:43 2019 +0000

Commit message:

abc

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/HttpServer_snapshot_mbed-os.lib	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1 @@
+https://developer.mbed.org/teams/Renesas/code/HttpServer_snapshot_mbed-os/#673d663a1ed7

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/file_table_lychee.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1223 @@
+
+static const char index_htm_tbl[] = {
+ 0x3C,0x53,0x43,0x52,0x49,0x50,0x54,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65
+,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x3E,0x0D
+,0x0A,0x3C,0x21,0x2D,0x2D,0x0D,0x0A,0x6C,0x6F,0x63,0x61,0x74,0x69,0x6F,0x6E,0x2E
+,0x68,0x72,0x65,0x66,0x3D,0x22,0x2F,0x77,0x65,0x62,0x5F,0x74,0x6F,0x70,0x2E,0x68
+,0x74,0x6D,0x22,0x3B,0x0D,0x0A,0x2D,0x2D,0x3E,0x0D,0x0A,0x3C,0x2F,0x53,0x43,0x52
+,0x49,0x50,0x54,0x3E,0x0D,0x0A
+};
+
+static const char camaera_js_tbl[] = {
+ 0x76,0x61,0x72,0x20,0x69,0x6D,0x61,0x67,0x65,0x4E,0x72,0x20,0x3D,0x20,0x30,0x3B
+,0x20,0x2F,0x2F,0x20,0x53,0x65,0x72,0x69,0x61,0x6C,0x20,0x6E,0x75,0x6D,0x62,0x65
+,0x72,0x20,0x6F,0x66,0x20,0x63,0x75,0x72,0x72,0x65,0x6E,0x74,0x20,0x69,0x6D,0x61
+,0x67,0x65,0x0D,0x0A,0x76,0x61,0x72,0x20,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64
+,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x41,0x72,0x72,0x61,0x79,0x28,0x29,0x3B,0x20
+,0x2F,0x2F,0x20,0x52,0x65,0x66,0x65,0x72,0x65,0x6E,0x63,0x65,0x73,0x20,0x74,0x6F
+,0x20,0x69,0x6D,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x73,0x20,0x77,0x68,0x69
+,0x63,0x68,0x20,0x68,0x61,0x76,0x65,0x20,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64
+,0x20,0x64,0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64,0x69,0x6E,0x67,0x0D,0x0A,0x0D,0x0A
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x63,0x72,0x65,0x61,0x74,0x65,0x49
+,0x6D,0x61,0x67,0x65,0x4C,0x61,0x79,0x65,0x72,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x20
+,0x20,0x76,0x61,0x72,0x20,0x69,0x6D,0x61,0x67,0x65,0x20,0x3D,0x20,0x6E,0x65,0x77
+,0x20,0x49,0x6D,0x61,0x67,0x65,0x28,0x29,0x3B,0x0D,0x0A,0x0D,0x0A,0x20,0x20,0x69
+,0x6D,0x61,0x67,0x65,0x2E,0x73,0x72,0x63,0x20,0x3D,0x20,0x22,0x63,0x61,0x6D,0x65
+,0x72,0x61,0x2F,0x22,0x20,0x2B,0x20,0x28,0x2B,0x2B,0x69,0x6D,0x61,0x67,0x65,0x4E
+,0x72,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61,0x67,0x65,0x2E,0x73,0x74,0x79
+,0x6C,0x65,0x2E,0x70,0x6F,0x73,0x69,0x74,0x69,0x6F,0x6E,0x20,0x3D,0x20,0x22,0x61
+,0x62,0x73,0x6F,0x6C,0x75,0x74,0x65,0x22,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61
+,0x67,0x65,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x7A,0x49,0x6E,0x64,0x65,0x78,0x20
+,0x3D,0x20,0x2D,0x31,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61,0x67,0x65,0x2E,0x6F
+,0x6E,0x6C,0x6F,0x61,0x64,0x20,0x3D,0x20,0x69,0x6D,0x61,0x67,0x65,0x4F,0x6E,0x6C
+,0x6F,0x61,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61,0x67,0x65,0x2E,0x6F,0x6E
+,0x65,0x72,0x72,0x6F,0x72,0x20,0x3D,0x20,0x63,0x72,0x65,0x61,0x74,0x65,0x49,0x6D
+,0x61,0x67,0x65,0x4C,0x61,0x79,0x65,0x72,0x3B,0x0D,0x0A,0x0D,0x0A,0x20,0x20,0x76
+,0x61,0x72,0x20,0x77,0x65,0x62,0x63,0x61,0x6D,0x20,0x3D,0x20,0x64,0x6F,0x63,0x75
+,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42
+,0x79,0x49,0x64,0x28,0x22,0x77,0x65,0x62,0x63,0x61,0x6D,0x22,0x29,0x3B,0x0D,0x0A
+,0x20,0x20,0x77,0x65,0x62,0x63,0x61,0x6D,0x2E,0x69,0x6E,0x73,0x65,0x72,0x74,0x42
+,0x65,0x66,0x6F,0x72,0x65,0x28,0x69,0x6D,0x61,0x67,0x65,0x2C,0x20,0x77,0x65,0x62
+,0x63,0x61,0x6D,0x2E,0x66,0x69,0x72,0x73,0x74,0x43,0x68,0x69,0x6C,0x64,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20
+,0x69,0x6D,0x61,0x67,0x65,0x4F,0x6E,0x6C,0x6F,0x61,0x64,0x28,0x29,0x20,0x7B,0x0D
+,0x0A,0x20,0x20,0x74,0x68,0x69,0x73,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x7A,0x49
+,0x6E,0x64,0x65,0x78,0x20,0x3D,0x20,0x69,0x6D,0x61,0x67,0x65,0x4E,0x72,0x3B,0x0D
+,0x0A,0x20,0x20,0x77,0x68,0x69,0x6C,0x65,0x20,0x28,0x31,0x20,0x3C,0x20,0x66,0x69
+,0x6E,0x69,0x73,0x68,0x65,0x64,0x2E,0x6C,0x65,0x6E,0x67,0x74,0x68,0x29,0x20,0x7B
+,0x0D,0x0A,0x20,0x20,0x20,0x20,0x76,0x61,0x72,0x20,0x64,0x65,0x6C,0x20,0x3D,0x20
+,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64,0x2E,0x73,0x68,0x69,0x66,0x74,0x28,0x29
+,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x64,0x65,0x6C,0x2E,0x70,0x61,0x72,0x65,0x6E
+,0x74,0x4E,0x6F,0x64,0x65,0x2E,0x72,0x65,0x6D,0x6F,0x76,0x65,0x43,0x68,0x69,0x6C
+,0x64,0x28,0x64,0x65,0x6C,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x7D,0x0D,0x0A,0x20,0x20
+,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64,0x2E,0x70,0x75,0x73,0x68,0x28,0x74,0x68
+,0x69,0x73,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x74,0x69,0x6D,0x65,0x72,0x49,0x44,0x20
+,0x3D,0x20,0x73,0x65,0x74,0x54,0x69,0x6D,0x65,0x6F,0x75,0x74,0x28,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x7B,0x20,0x63,0x72,0x65,0x61,0x74,0x65,0x49
+,0x6D,0x61,0x67,0x65,0x4C,0x61,0x79,0x65,0x72,0x28,0x29,0x20,0x7D,0x2C,0x20,0x64
+,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x46,0x31,0x2E,0x77,0x61,0x69,0x74,0x74
+,0x69,0x6D,0x65,0x2E,0x76,0x61,0x6C,0x75,0x65,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A
+};
+
+static const char camera_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x63,0x61,0x6D,0x65,0x72,0x61,0x3C,0x2F,0x74
+,0x69,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74
+,0x79,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63
+,0x72,0x69,0x70,0x74,0x22,0x20,0x73,0x72,0x63,0x3D,0x22,0x63,0x61,0x6D,0x65,0x72
+,0x61,0x2E,0x6A,0x73,0x22,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75
+,0x74,0x66,0x2D,0x38,0x22,0x3E,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D
+,0x0A,0x3C,0x73,0x74,0x79,0x6C,0x65,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65
+,0x78,0x74,0x2F,0x63,0x73,0x73,0x22,0x3E,0x0D,0x0A,0x23,0x77,0x65,0x62,0x63,0x61
+,0x6D,0x20,0x69,0x6D,0x67,0x20,0x7B,0x0D,0x0A,0x09,0x6C,0x65,0x66,0x74,0x3A,0x20
+,0x30,0x3B,0x0D,0x0A,0x09,0x72,0x69,0x67,0x68,0x74,0x3A,0x20,0x30,0x3B,0x0D,0x0A
+,0x09,0x6D,0x61,0x78,0x2D,0x77,0x69,0x64,0x74,0x68,0x3A,0x20,0x36,0x34,0x30,0x70
+,0x78,0x3B,0x20,0x0D,0x0A,0x09,0x77,0x69,0x64,0x74,0x68,0x3A,0x20,0x31,0x30,0x30
+,0x25,0x3B,0x0D,0x0A,0x09,0x68,0x65,0x69,0x67,0x68,0x74,0x3A,0x20,0x61,0x75,0x74
+,0x6F,0x3B,0x20,0x0D,0x0A,0x7D,0x0D,0x0A,0x3C,0x2F,0x73,0x74,0x79,0x6C,0x65,0x3E
+,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79
+,0x3E,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79,0x20,0x6F,0x6E,0x6C,0x6F,0x61,0x64,0x3D
+,0x22,0x63,0x72,0x65,0x61,0x74,0x65,0x49,0x6D,0x61,0x67,0x65,0x4C,0x61,0x79,0x65
+,0x72,0x28,0x29,0x3B,0x22,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x72,0x6D,0x20,0x61,0x63
+,0x74,0x69,0x6F,0x6E,0x3D,0x22,0x23,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x46
+,0x31,0x22,0x3E,0x0D,0x0A,0x57,0x61,0x69,0x74,0x20,0x74,0x69,0x6D,0x65,0x20,0x3C
+,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x72,0x61,0x6E,0x67
+,0x65,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x77,0x61,0x69,0x74,0x74,0x69,0x6D
+,0x65,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x3D,0x22,0x35,0x30,0x30,0x22,0x20,0x6D
+,0x61,0x78,0x3D,0x22,0x31,0x30,0x30,0x30,0x22,0x20,0x73,0x74,0x65,0x70,0x3D,0x22
+,0x35,0x30,0x22,0x3E,0x20,0x5B,0x6D,0x73,0x5D,0x0D,0x0A,0x3C,0x2F,0x66,0x6F,0x72
+,0x6D,0x3E,0x0D,0x0A,0x3C,0x64,0x69,0x76,0x20,0x69,0x64,0x3D,0x22,0x77,0x65,0x62
+,0x63,0x61,0x6D,0x22,0x3E,0x3C,0x6E,0x6F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x3C
+,0x69,0x6D,0x67,0x20,0x73,0x72,0x63,0x3D,0x22,0x63,0x61,0x6D,0x65,0x72,0x61,0x2F
+,0x30,0x22,0x20,0x2F,0x3E,0x3C,0x2F,0x6E,0x6F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E
+,0x3C,0x2F,0x64,0x69,0x76,0x3E,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79,0x3E,0x0D
+,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A
+};
+
+static const char mbedrpc_js_tbl[] = {
+ 0x2F,0x2F,0x20,0x6D,0x62,0x65,0x64,0x52,0x50,0x43,0x20,0x4A,0x61,0x76,0x61,0x73
+,0x63,0x72,0x69,0x70,0x74,0x20,0x49,0x6E,0x74,0x65,0x72,0x66,0x61,0x63,0x65,0x20
+,0x75,0x73,0x69,0x6E,0x67,0x20,0x48,0x54,0x54,0x50,0x0D,0x0A,0x2F,0x2F,0x20,0x73
+,0x66,0x6F,0x72,0x64,0x20,0x61,0x6E,0x64,0x20,0x4D,0x20,0x57,0x61,0x6C,0x6B,0x65
+,0x72,0x0D,0x0A,0x2F,0x2F,0x20,0x41,0x20,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69
+,0x70,0x74,0x20,0x69,0x6E,0x74,0x65,0x72,0x66,0x61,0x63,0x65,0x20,0x66,0x6F,0x72
+,0x20,0x74,0x61,0x6C,0x6B,0x69,0x6E,0x67,0x20,0x74,0x6F,0x20,0x6D,0x62,0x65,0x64
+,0x20,0x72,0x70,0x63,0x20,0x6F,0x76,0x65,0x72,0x20,0x68,0x74,0x74,0x70,0x0D,0x0A
+,0x2F,0x2F,0x0D,0x0A,0x2F,0x2F,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20
+,0x28,0x63,0x29,0x20,0x32,0x30,0x31,0x30,0x20,0x41,0x52,0x4D,0x20,0x4C,0x74,0x64
+,0x0D,0x0A,0x2F,0x2F,0x20,0x0D,0x0A,0x2F,0x2F,0x50,0x65,0x72,0x6D,0x69,0x73,0x73
+,0x69,0x6F,0x6E,0x20,0x69,0x73,0x20,0x68,0x65,0x72,0x65,0x62,0x79,0x20,0x67,0x72
+,0x61,0x6E,0x74,0x65,0x64,0x2C,0x20,0x66,0x72,0x65,0x65,0x20,0x6F,0x66,0x20,0x63
+,0x68,0x61,0x72,0x67,0x65,0x2C,0x20,0x74,0x6F,0x20,0x61,0x6E,0x79,0x20,0x70,0x65
+,0x72,0x73,0x6F,0x6E,0x20,0x6F,0x62,0x74,0x61,0x69,0x6E,0x69,0x6E,0x67,0x20,0x61
+,0x20,0x63,0x6F,0x70,0x79,0x0D,0x0A,0x2F,0x2F,0x6F,0x66,0x20,0x74,0x68,0x69,0x73
+,0x20,0x73,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x61,0x6E,0x64,0x20,0x61,0x73
+,0x73,0x6F,0x63,0x69,0x61,0x74,0x65,0x64,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E
+,0x74,0x61,0x74,0x69,0x6F,0x6E,0x20,0x66,0x69,0x6C,0x65,0x73,0x20,0x28,0x74,0x68
+,0x65,0x20,0x22,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x22,0x29,0x2C,0x20,0x74
+,0x6F,0x20,0x64,0x65,0x61,0x6C,0x0D,0x0A,0x2F,0x2F,0x69,0x6E,0x20,0x74,0x68,0x65
+,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x77,0x69,0x74,0x68,0x6F,0x75
+,0x74,0x20,0x72,0x65,0x73,0x74,0x72,0x69,0x63,0x74,0x69,0x6F,0x6E,0x2C,0x20,0x69
+,0x6E,0x63,0x6C,0x75,0x64,0x69,0x6E,0x67,0x20,0x77,0x69,0x74,0x68,0x6F,0x75,0x74
+,0x20,0x6C,0x69,0x6D,0x69,0x74,0x61,0x74,0x69,0x6F,0x6E,0x20,0x74,0x68,0x65,0x20
+,0x72,0x69,0x67,0x68,0x74,0x73,0x0D,0x0A,0x2F,0x2F,0x74,0x6F,0x20,0x75,0x73,0x65
+,0x2C,0x20,0x63,0x6F,0x70,0x79,0x2C,0x20,0x6D,0x6F,0x64,0x69,0x66,0x79,0x2C,0x20
+,0x6D,0x65,0x72,0x67,0x65,0x2C,0x20,0x70,0x75,0x62,0x6C,0x69,0x73,0x68,0x2C,0x20
+,0x64,0x69,0x73,0x74,0x72,0x69,0x62,0x75,0x74,0x65,0x2C,0x20,0x73,0x75,0x62,0x6C
+,0x69,0x63,0x65,0x6E,0x73,0x65,0x2C,0x20,0x61,0x6E,0x64,0x2F,0x6F,0x72,0x20,0x73
+,0x65,0x6C,0x6C,0x0D,0x0A,0x2F,0x2F,0x63,0x6F,0x70,0x69,0x65,0x73,0x20,0x6F,0x66
+,0x20,0x74,0x68,0x65,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x2C,0x20,0x61
+,0x6E,0x64,0x20,0x74,0x6F,0x20,0x70,0x65,0x72,0x6D,0x69,0x74,0x20,0x70,0x65,0x72
+,0x73,0x6F,0x6E,0x73,0x20,0x74,0x6F,0x20,0x77,0x68,0x6F,0x6D,0x20,0x74,0x68,0x65
+,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x69,0x73,0x0D,0x0A,0x2F,0x2F
+,0x66,0x75,0x72,0x6E,0x69,0x73,0x68,0x65,0x64,0x20,0x74,0x6F,0x20,0x64,0x6F,0x20
+,0x73,0x6F,0x2C,0x20,0x73,0x75,0x62,0x6A,0x65,0x63,0x74,0x20,0x74,0x6F,0x20,0x74
+,0x68,0x65,0x20,0x66,0x6F,0x6C,0x6C,0x6F,0x77,0x69,0x6E,0x67,0x20,0x63,0x6F,0x6E
+,0x64,0x69,0x74,0x69,0x6F,0x6E,0x73,0x3A,0x0D,0x0A,0x2F,0x2F,0x20,0x0D,0x0A,0x2F
+,0x2F,0x54,0x68,0x65,0x20,0x61,0x62,0x6F,0x76,0x65,0x20,0x63,0x6F,0x70,0x79,0x72
+,0x69,0x67,0x68,0x74,0x20,0x6E,0x6F,0x74,0x69,0x63,0x65,0x20,0x61,0x6E,0x64,0x20
+,0x74,0x68,0x69,0x73,0x20,0x70,0x65,0x72,0x6D,0x69,0x73,0x73,0x69,0x6F,0x6E,0x20
+,0x6E,0x6F,0x74,0x69,0x63,0x65,0x20,0x73,0x68,0x61,0x6C,0x6C,0x20,0x62,0x65,0x20
+,0x69,0x6E,0x63,0x6C,0x75,0x64,0x65,0x64,0x20,0x69,0x6E,0x0D,0x0A,0x2F,0x2F,0x61
+,0x6C,0x6C,0x20,0x63,0x6F,0x70,0x69,0x65,0x73,0x20,0x6F,0x72,0x20,0x73,0x75,0x62
+,0x73,0x74,0x61,0x6E,0x74,0x69,0x61,0x6C,0x20,0x70,0x6F,0x72,0x74,0x69,0x6F,0x6E
+,0x73,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72
+,0x65,0x2E,0x0D,0x0A,0x2F,0x2F,0x20,0x0D,0x0A,0x2F,0x2F,0x54,0x48,0x45,0x20,0x53
+,0x4F,0x46,0x54,0x57,0x41,0x52,0x45,0x20,0x49,0x53,0x20,0x50,0x52,0x4F,0x56,0x49
+,0x44,0x45,0x44,0x20,0x22,0x41,0x53,0x20,0x49,0x53,0x22,0x2C,0x20,0x57,0x49,0x54
+,0x48,0x4F,0x55,0x54,0x20,0x57,0x41,0x52,0x52,0x41,0x4E,0x54,0x59,0x20,0x4F,0x46
+,0x20,0x41,0x4E,0x59,0x20,0x4B,0x49,0x4E,0x44,0x2C,0x20,0x45,0x58,0x50,0x52,0x45
+,0x53,0x53,0x20,0x4F,0x52,0x0D,0x0A,0x2F,0x2F,0x49,0x4D,0x50,0x4C,0x49,0x45,0x44
+,0x2C,0x20,0x49,0x4E,0x43,0x4C,0x55,0x44,0x49,0x4E,0x47,0x20,0x42,0x55,0x54,0x20
+,0x4E,0x4F,0x54,0x20,0x4C,0x49,0x4D,0x49,0x54,0x45,0x44,0x20,0x54,0x4F,0x20,0x54
+,0x48,0x45,0x20,0x57,0x41,0x52,0x52,0x41,0x4E,0x54,0x49,0x45,0x53,0x20,0x4F,0x46
+,0x20,0x4D,0x45,0x52,0x43,0x48,0x41,0x4E,0x54,0x41,0x42,0x49,0x4C,0x49,0x54,0x59
+,0x2C,0x0D,0x0A,0x2F,0x2F,0x46,0x49,0x54,0x4E,0x45,0x53,0x53,0x20,0x46,0x4F,0x52
+,0x20,0x41,0x20,0x50,0x41,0x52,0x54,0x49,0x43,0x55,0x4C,0x41,0x52,0x20,0x50,0x55
+,0x52,0x50,0x4F,0x53,0x45,0x20,0x41,0x4E,0x44,0x20,0x4E,0x4F,0x4E,0x49,0x4E,0x46
+,0x52,0x49,0x4E,0x47,0x45,0x4D,0x45,0x4E,0x54,0x2E,0x20,0x49,0x4E,0x20,0x4E,0x4F
+,0x20,0x45,0x56,0x45,0x4E,0x54,0x20,0x53,0x48,0x41,0x4C,0x4C,0x20,0x54,0x48,0x45
+,0x0D,0x0A,0x2F,0x2F,0x41,0x55,0x54,0x48,0x4F,0x52,0x53,0x20,0x4F,0x52,0x20,0x43
+,0x4F,0x50,0x59,0x52,0x49,0x47,0x48,0x54,0x20,0x48,0x4F,0x4C,0x44,0x45,0x52,0x53
+,0x20,0x42,0x45,0x20,0x4C,0x49,0x41,0x42,0x4C,0x45,0x20,0x46,0x4F,0x52,0x20,0x41
+,0x4E,0x59,0x20,0x43,0x4C,0x41,0x49,0x4D,0x2C,0x20,0x44,0x41,0x4D,0x41,0x47,0x45
+,0x53,0x20,0x4F,0x52,0x20,0x4F,0x54,0x48,0x45,0x52,0x0D,0x0A,0x2F,0x2F,0x4C,0x49
+,0x41,0x42,0x49,0x4C,0x49,0x54,0x59,0x2C,0x20,0x57,0x48,0x45,0x54,0x48,0x45,0x52
+,0x20,0x49,0x4E,0x20,0x41,0x4E,0x20,0x41,0x43,0x54,0x49,0x4F,0x4E,0x20,0x4F,0x46
+,0x20,0x43,0x4F,0x4E,0x54,0x52,0x41,0x43,0x54,0x2C,0x20,0x54,0x4F,0x52,0x54,0x20
+,0x4F,0x52,0x20,0x4F,0x54,0x48,0x45,0x52,0x57,0x49,0x53,0x45,0x2C,0x20,0x41,0x52
+,0x49,0x53,0x49,0x4E,0x47,0x20,0x46,0x52,0x4F,0x4D,0x2C,0x0D,0x0A,0x2F,0x2F,0x4F
+,0x55,0x54,0x20,0x4F,0x46,0x20,0x4F,0x52,0x20,0x49,0x4E,0x20,0x43,0x4F,0x4E,0x4E
+,0x45,0x43,0x54,0x49,0x4F,0x4E,0x20,0x57,0x49,0x54,0x48,0x20,0x54,0x48,0x45,0x20
+,0x53,0x4F,0x46,0x54,0x57,0x41,0x52,0x45,0x20,0x4F,0x52,0x20,0x54,0x48,0x45,0x20
+,0x55,0x53,0x45,0x20,0x4F,0x52,0x20,0x4F,0x54,0x48,0x45,0x52,0x20,0x44,0x45,0x41
+,0x4C,0x49,0x4E,0x47,0x53,0x20,0x49,0x4E,0x0D,0x0A,0x2F,0x2F,0x54,0x48,0x45,0x20
+,0x53,0x4F,0x46,0x54,0x57,0x41,0x52,0x45,0x2E,0x0D,0x0A,0x0D,0x0A,0x0D,0x0A,0x2F
+,0x2F,0x54,0x72,0x61,0x6E,0x73,0x70,0x6F,0x72,0x74,0x20,0x4D,0x65,0x63,0x68,0x61
+,0x6E,0x69,0x73,0x6D,0x73,0x20,0x20,0x20,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x20,0x70,0x6F,0x73,0x74,0x28,0x75,0x72,0x6C,0x29,0x20,0x7B,0x0D
+,0x0A,0x20,0x20,0x20,0x20,0x68,0x74,0x74,0x70,0x20,0x3D,0x20,0x28,0x77,0x69,0x6E
+,0x64,0x6F,0x77,0x2E,0x58,0x4D,0x4C,0x48,0x74,0x74,0x70,0x52,0x65,0x71,0x75,0x65
+,0x73,0x74,0x29,0x20,0x3F,0x20,0x6E,0x65,0x77,0x20,0x58,0x4D,0x4C,0x48,0x74,0x74
+,0x70,0x52,0x65,0x71,0x75,0x65,0x73,0x74,0x28,0x29,0x20,0x3A,0x20,0x6E,0x65,0x77
+,0x20,0x41,0x63,0x74,0x69,0x76,0x65,0x58,0x4F,0x62,0x6A,0x65,0x63,0x74,0x28,0x22
+,0x4D,0x69,0x63,0x72,0x6F,0x73,0x6F,0x66,0x74,0x2E,0x58,0x4D,0x4C,0x48,0x54,0x54
+,0x50,0x22,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x69,0x66,0x28,0x21,0x68,0x74
+,0x74,0x70,0x29,0x20,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x66,0x61,0x6C,0x73,0x65
+,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x68,0x74,0x74,0x70,0x2E,0x6F,0x70,0x65,0x6E
+,0x28,0x22,0x47,0x45,0x54,0x22,0x2C,0x20,0x75,0x72,0x6C,0x2C,0x20,0x66,0x61,0x6C
+,0x73,0x65,0x29,0x3B,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x0D,0x0A,0x20,0x20,0x20,0x20,0x68,0x74,0x74,0x70,0x2E,0x73,0x65,0x6E,0x64
+,0x28,0x6E,0x75,0x6C,0x6C,0x29,0x3B,0x20,0x20,0x20,0x0D,0x0A,0x20,0x20,0x20,0x20
+,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x68,0x74,0x74,0x70,0x2E,0x72,0x65,0x73,0x70
+,0x6F,0x6E,0x73,0x65,0x54,0x65,0x78,0x74,0x3B,0x0D,0x0A,0x09,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x6D,0x62
+,0x65,0x64,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x2F,0x2F,0x4E,0x6F,0x20,0x61,0x63,0x74
+,0x69,0x6F,0x6E,0x20,0x6E,0x65,0x65,0x64,0x73,0x20,0x74,0x6F,0x20,0x62,0x65,0x20
+,0x74,0x61,0x6B,0x65,0x6E,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x6D,0x62,0x65,0x64
+,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x70,0x63,0x20,0x3D
+,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x6F,0x62,0x6A,0x65,0x63,0x74
+,0x2C,0x20,0x6D,0x65,0x74,0x68,0x6F,0x64,0x2C,0x20,0x61,0x72,0x67,0x75,0x6D,0x65
+,0x6E,0x74,0x73,0x29,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x2F,0x2F,0x54,0x68,0x69
+,0x73,0x20,0x73,0x68,0x6F,0x75,0x6C,0x64,0x20,0x62,0x65,0x20,0x6F,0x76,0x65,0x72
+,0x72,0x69,0x64,0x64,0x65,0x6E,0x20,0x62,0x79,0x20,0x74,0x68,0x65,0x20,0x61,0x20
+,0x74,0x72,0x61,0x6E,0x73,0x70,0x6F,0x72,0x74,0x20,0x6D,0x65,0x63,0x68,0x61,0x6E
+,0x69,0x73,0x6D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x48,0x54,0x54,0x50,0x52,0x50
+,0x43,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x20,0x3D,0x20,0x6E,0x65
+,0x77,0x20,0x6D,0x62,0x65,0x64,0x28,0x29,0x3B,0x0D,0x0A,0x48,0x54,0x54,0x50,0x52
+,0x50,0x43,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x63,0x6F,0x6E
+,0x73,0x74,0x72,0x75,0x63,0x74,0x6F,0x72,0x20,0x3D,0x20,0x48,0x54,0x54,0x50,0x52
+,0x50,0x43,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x48,0x54,0x54
+,0x50,0x52,0x50,0x43,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x2F,0x2F,0x75,0x6E,0x6C,0x69
+,0x6B,0x65,0x20,0x6F,0x74,0x68,0x65,0x72,0x20,0x6C,0x61,0x6E,0x67,0x75,0x61,0x67
+,0x65,0x73,0x20,0x74,0x68,0x69,0x73,0x20,0x64,0x6F,0x65,0x73,0x6E,0x27,0x74,0x20
+,0x6E,0x65,0x65,0x64,0x20,0x74,0x6F,0x20,0x62,0x65,0x20,0x70,0x61,0x73,0x73,0x65
+,0x64,0x20,0x61,0x6E,0x20,0x61,0x64,0x64,0x72,0x65,0x73,0x73,0x20,0x61,0x73,0x20
+,0x69,0x74,0x20,0x77,0x69,0x6C,0x6C,0x20,0x6F,0x6E,0x6C,0x79,0x20,0x62,0x65,0x20
+,0x61,0x6C,0x6C,0x6F,0x77,0x65,0x64,0x20,0x74,0x6F,0x20,0x63,0x6F,0x6D,0x6D,0x75
+,0x6E,0x69,0x63,0x61,0x74,0x65,0x20,0x77,0x69,0x74,0x68,0x20,0x69,0x74,0x73,0x65
+,0x6C,0x66,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x0D,0x0A,0x48,0x54,0x54,0x50,0x52
+,0x50,0x43,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x70,0x63
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x6F,0x62,0x6A,0x65,0x63
+,0x74,0x2C,0x20,0x6D,0x65,0x74,0x68,0x6F,0x64,0x2C,0x20,0x61,0x72,0x67,0x75,0x6D
+,0x65,0x6E,0x74,0x73,0x29,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x72,0x65,0x74
+,0x75,0x72,0x6E,0x20,0x70,0x6F,0x73,0x74,0x28,0x22,0x2F,0x72,0x70,0x63,0x2F,0x22
+,0x20,0x2B,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x20,0x2B,0x20,0x22,0x2F,0x22,0x20
+,0x2B,0x20,0x6D,0x65,0x74,0x68,0x6F,0x64,0x20,0x2B,0x20,0x22,0x2C,0x22,0x20,0x2B
+,0x20,0x61,0x72,0x67,0x75,0x6D,0x65,0x6E,0x74,0x73,0x2E,0x6A,0x6F,0x69,0x6E,0x28
+,0x22,0x2C,0x22,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x20
+,0x50,0x69,0x6E,0x20,0x4E,0x61,0x6D,0x65,0x73,0x20,0x74,0x6F,0x20,0x41,0x6C,0x6C
+,0x6F,0x77,0x20,0x70,0x69,0x6E,0x73,0x20,0x74,0x6F,0x20,0x62,0x65,0x20,0x72,0x65
+,0x66,0x66,0x65,0x72,0x65,0x64,0x20,0x74,0x6F,0x20,0x61,0x73,0x20,0x61,0x20,0x74
+,0x79,0x70,0x65,0x20,0x72,0x61,0x74,0x68,0x65,0x72,0x20,0x74,0x68,0x61,0x6E,0x20
+,0x61,0x20,0x73,0x74,0x72,0x69,0x6E,0x67,0x20,0x6F,0x72,0x20,0x6E,0x75,0x6D,0x62
+,0x65,0x72,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x70
+,0x69,0x6E,0x28,0x6E,0x61,0x6D,0x65,0x29,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73
+,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6E,0x61,0x6D,0x65,0x3B,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x4C,0x45,0x44,0x31,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20
+,0x70,0x69,0x6E,0x28,0x22,0x4C,0x45,0x44,0x31,0x22,0x29,0x3B,0x0D,0x0A,0x4C,0x45
+,0x44,0x32,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x70,0x69,0x6E,0x28,0x22,0x4C,0x45
+,0x44,0x32,0x22,0x29,0x3B,0x0D,0x0A,0x4C,0x45,0x44,0x33,0x20,0x3D,0x20,0x6E,0x65
+,0x77,0x20,0x70,0x69,0x6E,0x28,0x22,0x4C,0x45,0x44,0x33,0x22,0x29,0x3B,0x0D,0x0A
+,0x4C,0x45,0x44,0x34,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x70,0x69,0x6E,0x28,0x22
+,0x4C,0x45,0x44,0x34,0x22,0x29,0x3B,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x20,0x69,0x6E
+,0x74,0x65,0x72,0x66,0x61,0x63,0x65,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x73,0x20,0x20,0x20,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74
+,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x44,0x69
+,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62
+,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x69,0x66
+,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70,0x69,0x6E,0x20,0x21,0x3D,0x20
+,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09,0x0D,0x0A,0x09,0x09,0x2F
+,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E,0x65,0x77,0x20,0x6F,0x62
+,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62
+,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D
+,0x0A,0x09,0x2F,0x2F,0x76,0x61,0x72,0x20,0x61,0x72,0x79,0x20,0x3D,0x20,0x6E,0x65
+,0x77,0x20,0x41,0x72,0x72,0x61,0x79,0x28,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x29,0x3B,0x0D
+,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65
+,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x22,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x22,0x2C,0x20,0x22
+,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D
+,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x5D,0x29,0x3B,0x20
+,0x0D,0x0A,0x09,0x2F,0x2F,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20
+,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28
+,0x22,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x22,0x2C,0x20,0x22,0x6E
+,0x65,0x77,0x22,0x2C,0x20,0x61,0x72,0x79,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65
+,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F
+,0x20,0x61,0x6E,0x20,0x65,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A
+,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65
+,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A
+,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70
+,0x69,0x6E,0x3B,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x44,0x69
+,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79
+,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65,0x22
+,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A
+,0x0D,0x0A,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F
+,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74
+,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74,0x28,0x74,0x68,0x69
+,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73
+,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B
+,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x44,0x69,0x67,0x69,0x74,0x61,0x6C
+,0x49,0x6E,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20
+,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x49,0x6E,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D
+,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x69
+,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70,0x69,0x6E,0x20,0x21,0x3D
+,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09,0x0D,0x0A,0x09,0x09
+,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E,0x65,0x77,0x20,0x6F
+,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B
+,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x22,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x49,0x6E,0x22,0x2C,0x20
+,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x5D,0x29,0x3B
+,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x09,0x09,0x2F,0x2F
+,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65,0x78,0x69,0x73,0x74,0x69
+,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D
+,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x49,0x6E,0x2E
+,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D
+,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09
+,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74,0x28
+,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74
+,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22
+,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A
+,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x41,0x6E
+,0x61,0x6C,0x6F,0x67,0x4F,0x75,0x74,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63
+,0x74,0x69,0x6F,0x6E,0x20,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F,0x75,0x74,0x28,0x74
+,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x69,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70
+,0x69,0x6E,0x20,0x21,0x3D,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B
+,0x09,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20
+,0x6E,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F
+,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F
+,0x75,0x74,0x22,0x2C,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69
+,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x5D,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D
+,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65
+,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A
+,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74
+,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A
+,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F
+,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69
+,0x74,0x65,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61
+,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C
+,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C
+,0x6F,0x67,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E
+,0x77,0x72,0x69,0x74,0x65,0x5F,0x75,0x31,0x36,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63
+,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09
+,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74
+,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65
+,0x5F,0x75,0x31,0x36,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F,0x75,0x74
+,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A
+,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x46,0x6C,0x6F
+,0x61,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70
+,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65
+,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D
+,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x20,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49,0x6E,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49,0x6E,0x28
+,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29
+,0x20,0x7B,0x0D,0x0A,0x09,0x69,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D
+,0x70,0x69,0x6E,0x20,0x21,0x3D,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29
+,0x7B,0x09,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61
+,0x20,0x6E,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73
+,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F
+,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22,0x41,0x6E,0x61,0x6C,0x6F,0x67
+,0x49,0x6E,0x22,0x2C,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69
+,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x5D,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D
+,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65
+,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A
+,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74
+,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A
+,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49
+,0x6E,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64
+,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x46,0x6C
+,0x6F,0x61,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72
+,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D
+,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49,0x6E,0x2E,0x70,0x72,0x6F
+,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x5F,0x75,0x31,0x36,0x20
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A
+,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28
+,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64
+,0x5F,0x75,0x31,0x36,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x20,0x50,0x77,0x6D,0x4F,0x75,0x74,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x50,0x77,0x6D,0x4F,0x75,0x74,0x28,0x74,0x68
+,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20,0x7B
+,0x0D,0x0A,0x09,0x69,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70,0x69
+,0x6E,0x20,0x21,0x3D,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09
+,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E
+,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D
+,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73
+,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62
+,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22,0x50,0x77,0x6D,0x4F,0x75,0x74,0x22,0x2C
+,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E
+,0x61,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x5D,0x29
+,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x09,0x09,0x2F
+,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65,0x78,0x69,0x73,0x74
+,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F
+,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61
+,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A,0x09,0x7D,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74
+,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77,0x72,0x69
+,0x74,0x65,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74
+,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x72
+,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x46,0x6C,0x6F,0x61,0x74
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28
+,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64
+,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70
+,0x65,0x2E,0x70,0x65,0x72,0x69,0x6F,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x65,0x72,0x69,0x6F,0x64
+,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D
+,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74
+,0x79,0x70,0x65,0x2E,0x70,0x65,0x72,0x69,0x6F,0x64,0x5F,0x6D,0x73,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70
+,0x65,0x72,0x69,0x6F,0x64,0x5F,0x6D,0x73,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75
+,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75
+,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x65,0x72,0x69
+,0x6F,0x64,0x5F,0x75,0x73,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73
+,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E
+,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x65,0x72,0x69,0x6F,0x64,0x5F,0x75,0x73
+,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D
+,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74
+,0x79,0x70,0x65,0x2E,0x70,0x75,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x20,0x3D
+,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29
+,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E
+,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22
+,0x70,0x75,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x22,0x2C,0x20,0x5B,0x76,0x61
+,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D
+,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x75
+,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x6D,0x73,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x75,0x6C
+,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x6D,0x73,0x22,0x2C,0x20,0x5B,0x76,0x61
+,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D
+,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x75
+,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x75,0x73,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x75,0x6C
+,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x75,0x73,0x22,0x2C,0x20,0x5B,0x76,0x61
+,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x73,0x65,0x72,0x69,0x61
+,0x6C,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x53
+,0x65,0x72,0x69,0x61,0x6C,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C
+,0x20,0x74,0x78,0x2C,0x20,0x72,0x78,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x69,0x66,0x28
+,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x74,0x78,0x20,0x21,0x3D,0x20,0x22,0x73,0x74
+,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72
+,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63
+,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20
+,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20
+,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20
+,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22
+,0x53,0x65,0x72,0x69,0x61,0x6C,0x22,0x2C,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20
+,0x5B,0x74,0x78,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x72,0x78,0x2E,0x5F,0x6E
+,0x61,0x6D,0x65,0x5D,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B
+,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20
+,0x65,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D
+,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20
+,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x78,0x3B,0x0D,0x0A,0x09
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C
+,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x75,0x74,0x63,0x20
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65
+,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64
+,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20
+,0x22,0x70,0x75,0x74,0x63,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29
+,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C,0x2E,0x70
+,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x67,0x65,0x74,0x63,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65
+,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x67
+,0x65,0x74,0x63,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D
+,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C,0x2E,0x70,0x72,0x6F,0x74,0x6F
+,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x61,0x62,0x6C,0x65,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65
+,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72
+,0x65,0x61,0x64,0x61,0x62,0x6C,0x65,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29
+,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C,0x2E,0x70
+,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x61,0x62
+,0x6C,0x65,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61
+,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20
+,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65,0x61,0x62,0x6C,0x65,0x22,0x2C,0x20
+,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x0D,0x0A
+,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x52,0x50
+,0x43,0x56,0x61,0x72,0x69,0x61,0x62,0x6C,0x65,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62
+,0x6C,0x65,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6E,0x61
+,0x6D,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62
+,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D
+,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61
+,0x6D,0x65,0x20,0x3D,0x20,0x6E,0x61,0x6D,0x65,0x3B,0x20,0x0D,0x0A,0x7D,0x0D,0x0A
+,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62,0x6C,0x65,0x2E,0x70,0x72
+,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77
+,0x72,0x69,0x74,0x65,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62
+,0x6C,0x65,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61
+,0x64,0x5F,0x69,0x6E,0x74,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61
+,0x72,0x73,0x65,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65
+,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C
+,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62
+,0x6C,0x65,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61
+,0x64,0x5F,0x66,0x6C,0x6F,0x61,0x74,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69
+,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20
+,0x70,0x61,0x72,0x73,0x65,0x46,0x6C,0x6F,0x61,0x74,0x28,0x74,0x68,0x69,0x73,0x2E
+,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E
+,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22
+,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61
+,0x72,0x69,0x61,0x62,0x6C,0x65,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65
+,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x28,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C
+,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F
+,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x52,0x50,0x43
+,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x20,0x52,0x50,0x43,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F
+,0x6E,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6E,0x61,0x6D
+,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65
+,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x20,0x3D,0x20,0x6E,0x61,0x6D,0x65,0x3B,0x20,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x52,0x50,0x43,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x2E,0x70,0x72,0x6F
+,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x75,0x6E,0x20,0x3D,0x20,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A
+,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x2C,0x20,0x22,0x72,0x75,0x6E,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65
+,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D
+};
+
+static const char led_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x20,0x75,0x74
+,0x66,0x2D,0x38,0x22,0x3E,0x20,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x4C
+,0x45,0x44,0x20,0x54,0x6F,0x67,0x67,0x6C,0x65,0x3C,0x2F,0x74,0x69,0x74,0x6C,0x65
+,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74,0x79,0x70,0x65,0x3D
+,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74
+,0x22,0x20,0x73,0x72,0x63,0x3D,0x22,0x6D,0x62,0x65,0x64,0x52,0x50,0x43,0x2E,0x6A
+,0x73,0x22,0x20,0x6C,0x61,0x6E,0x67,0x75,0x61,0x67,0x65,0x3D,0x22,0x6A,0x61,0x76
+,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74
+,0x3D,0x22,0x75,0x74,0x66,0x2D,0x38,0x22,0x3E,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70
+,0x74,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74,0x79,0x70,0x65
+,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70
+,0x74,0x22,0x3E,0x6D,0x62,0x65,0x64,0x3D,0x6E,0x65,0x77,0x20,0x48,0x54,0x54,0x50
+,0x52,0x50,0x43,0x28,0x29,0x3B,0x6C,0x65,0x64,0x31,0x3D,0x6E,0x65,0x77,0x20,0x44
+,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x6D,0x62,0x65,0x64,0x2C,0x4C
+,0x45,0x44,0x31,0x29,0x3B,0x6C,0x65,0x64,0x32,0x3D,0x6E,0x65,0x77,0x20,0x44,0x69
+,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x6D,0x62,0x65,0x64,0x2C,0x4C,0x45
+,0x44,0x32,0x29,0x3B,0x6C,0x65,0x64,0x33,0x3D,0x6E,0x65,0x77,0x20,0x44,0x69,0x67
+,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x6D,0x62,0x65,0x64,0x2C,0x4C,0x45,0x44
+,0x33,0x29,0x3B,0x6C,0x65,0x64,0x34,0x3D,0x6E,0x65,0x77,0x20,0x44,0x69,0x67,0x69
+,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x6D,0x62,0x65,0x64,0x2C,0x4C,0x45,0x44,0x34
+,0x29,0x3B,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D,0x0A,0x3C,0x73,0x63
+,0x72,0x69,0x70,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F
+,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x3E,0x66,0x75,0x6E,0x63
+,0x74,0x69,0x6F,0x6E,0x20,0x6C,0x65,0x64,0x31,0x5F,0x74,0x6F,0x67,0x67,0x6C,0x65
+,0x28,0x29,0x7B,0x76,0x61,0x72,0x20,0x72,0x64,0x31,0x3D,0x6C,0x65,0x64,0x31,0x2E
+,0x72,0x65,0x61,0x64,0x28,0x29,0x3B,0x69,0x66,0x28,0x72,0x64,0x31,0x3D,0x3D,0x31
+,0x29,0x7B,0x6C,0x65,0x64,0x31,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x30,0x29,0x3B
+,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3D,0x27
+,0x4C,0x45,0x44,0x31,0x20,0x4F,0x66,0x66,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65
+,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49
+,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x22,0x29,0x2E,0x73,0x74
+,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F
+,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x27,0x3B,0x64,0x6F
+,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E
+,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x22
+,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23
+,0x30,0x30,0x30,0x30,0x30,0x30,0x27,0x3B,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x6C,0x65
+,0x64,0x31,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x31,0x29,0x3B,0x62,0x74,0x6E,0x5F
+,0x4C,0x45,0x44,0x31,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3D,0x27,0x4C,0x45,0x44,0x31
+,0x20,0x4F,0x6E,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65
+,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74
+,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62
+,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x3D,0x27
+,0x23,0x30,0x30,0x38,0x30,0x30,0x30,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E
+,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64
+,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x22,0x29,0x2E,0x73,0x74,0x79
+,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x66,0x66,0x66,0x66,0x66
+,0x66,0x27,0x3B,0x7D,0x7D,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20
+,0x6C,0x65,0x64,0x32,0x5F,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x7B,0x76,0x61
+,0x72,0x20,0x72,0x64,0x32,0x3D,0x6C,0x65,0x64,0x32,0x2E,0x72,0x65,0x61,0x64,0x28
+,0x29,0x3B,0x69,0x66,0x28,0x72,0x64,0x32,0x3D,0x3D,0x31,0x29,0x7B,0x6C,0x65,0x64
+,0x32,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x30,0x29,0x3B,0x62,0x74,0x6E,0x5F,0x4C
+,0x45,0x44,0x32,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3D,0x27,0x4C,0x45,0x44,0x32,0x20
+,0x4F,0x66,0x66,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65
+,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74
+,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62
+,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x3D,0x27
+,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E
+,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64
+,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x22,0x29,0x2E,0x73,0x74,0x79
+,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x30,0x30,0x30,0x30,0x30
+,0x30,0x27,0x3B,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x6C,0x65,0x64,0x32,0x2E,0x77,0x72
+,0x69,0x74,0x65,0x28,0x31,0x29,0x3B,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x2E
+,0x76,0x61,0x6C,0x75,0x65,0x3D,0x27,0x4C,0x45,0x44,0x32,0x20,0x4F,0x6E,0x27,0x3B
+,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D
+,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44
+,0x32,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B,0x67,0x72
+,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x66,0x66,0x66,0x66
+,0x30,0x30,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74
+,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E
+,0x5F,0x4C,0x45,0x44,0x32,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F
+,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x66,0x66,0x66,0x66,0x66,0x66,0x27,0x3B,0x7D,0x7D
+,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x6C,0x65,0x64,0x33,0x5F
+,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x7B,0x76,0x61,0x72,0x20,0x72,0x64,0x33
+,0x3D,0x6C,0x65,0x64,0x33,0x2E,0x72,0x65,0x61,0x64,0x28,0x29,0x3B,0x69,0x66,0x28
+,0x72,0x64,0x33,0x3D,0x3D,0x31,0x29,0x7B,0x6C,0x65,0x64,0x33,0x2E,0x77,0x72,0x69
+,0x74,0x65,0x28,0x30,0x29,0x3B,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x2E,0x76
+,0x61,0x6C,0x75,0x65,0x3D,0x27,0x4C,0x45,0x44,0x33,0x20,0x4F,0x66,0x66,0x27,0x3B
+,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D
+,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44
+,0x33,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B,0x67,0x72
+,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x63,0x30,0x63,0x30
+,0x63,0x30,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74
+,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E
+,0x5F,0x4C,0x45,0x44,0x33,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F
+,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x30,0x30,0x30,0x30,0x30,0x30,0x27,0x3B,0x7D,0x65
+,0x6C,0x73,0x65,0x7B,0x6C,0x65,0x64,0x33,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x31
+,0x29,0x3B,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x2E,0x76,0x61,0x6C,0x75,0x65
+,0x3D,0x27,0x4C,0x45,0x44,0x33,0x20,0x4F,0x6E,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D
+,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79
+,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x22,0x29,0x2E,0x73
+,0x74,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43
+,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x66,0x66,0x36,0x36,0x30,0x30,0x27,0x3B,0x64
+,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65
+,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33
+,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x27
+,0x23,0x66,0x66,0x66,0x66,0x66,0x66,0x27,0x3B,0x7D,0x7D,0x0D,0x0A,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x20,0x6C,0x65,0x64,0x34,0x5F,0x74,0x6F,0x67,0x67,0x6C
+,0x65,0x28,0x29,0x7B,0x76,0x61,0x72,0x20,0x72,0x64,0x34,0x3D,0x6C,0x65,0x64,0x34
+,0x2E,0x72,0x65,0x61,0x64,0x28,0x29,0x3B,0x69,0x66,0x28,0x72,0x64,0x34,0x3D,0x3D
+,0x31,0x29,0x7B,0x6C,0x65,0x64,0x34,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x30,0x29
+,0x3B,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x34,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3D
+,0x27,0x4C,0x45,0x44,0x34,0x20,0x4F,0x66,0x66,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D
+,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79
+,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x34,0x22,0x29,0x2E,0x73
+,0x74,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43
+,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x27,0x3B,0x64
+,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65
+,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x34
+,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x27
+,0x23,0x30,0x30,0x30,0x30,0x30,0x30,0x27,0x3B,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x6C
+,0x65,0x64,0x34,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x31,0x29,0x3B,0x62,0x74,0x6E
+,0x5F,0x4C,0x45,0x44,0x34,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3D,0x27,0x4C,0x45,0x44
+,0x34,0x20,0x4F,0x6E,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67
+,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62
+,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x34,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E
+,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x3D
+,0x27,0x23,0x66,0x66,0x30,0x30,0x30,0x30,0x27,0x3B,0x64,0x6F,0x63,0x75,0x6D,0x65
+,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49
+,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x34,0x22,0x29,0x2E,0x73,0x74
+,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x27,0x23,0x66,0x66,0x66,0x66
+,0x66,0x66,0x27,0x3B,0x7D,0x7D,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D
+,0x0A,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F,0x64
+,0x79,0x3E,0x0D,0x0A,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A
+,0x65,0x3D,0x22,0x38,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C
+,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30
+,0x22,0x3E,0x3C,0x62,0x3E,0x4C,0x45,0x44,0x20,0x54,0x6F,0x67,0x67,0x6C,0x65,0x20
+,0x53,0x77,0x69,0x74,0x63,0x68,0x3C,0x2F,0x62,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E
+,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62,0x72,0x3E,0x3C,0x62,0x72,0x3E
+,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x62
+,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20,0x49,0x44,0x3D,0x22,0x62,0x74,0x6E,0x5F,0x4C
+,0x45,0x44,0x31,0x22,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E,0x54
+,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46
+,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x3B,0x63,0x6F,0x6C
+,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x30,0x30,0x3B,0x62,0x61,0x63,0x6B,0x67
+,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x63,0x30,0x63
+,0x30,0x63,0x30,0x3B,0x57,0x49,0x44,0x54,0x48,0x3A,0x20,0x37,0x30,0x70,0x78,0x3B
+,0x20,0x48,0x45,0x49,0x47,0x48,0x54,0x3A,0x20,0x34,0x30,0x70,0x78,0x22,0x20,0x6F
+,0x6E,0x43,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x6C,0x65,0x64,0x31,0x5F,0x74,0x6F,0x67
+,0x67,0x6C,0x65,0x28,0x29,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x3D,0x22,0x4C,0x45
+,0x44,0x31,0x20,0x4F,0x66,0x66,0x22,0x3E,0x20,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65
+,0x3D,0x22,0x62,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20,0x49,0x44,0x3D,0x22,0x62,0x74
+,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x22,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46
+,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D
+,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x3B
+,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x30,0x30,0x3B,0x62,0x61
+,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23
+,0x63,0x30,0x63,0x30,0x63,0x30,0x3B,0x57,0x49,0x44,0x54,0x48,0x3A,0x20,0x37,0x30
+,0x70,0x78,0x3B,0x20,0x48,0x45,0x49,0x47,0x48,0x54,0x3A,0x20,0x34,0x30,0x70,0x78
+,0x22,0x20,0x6F,0x6E,0x43,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x6C,0x65,0x64,0x32,0x5F
+,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x3D
+,0x22,0x4C,0x45,0x44,0x32,0x20,0x4F,0x66,0x66,0x22,0x3E,0x20,0x3C,0x62,0x72,0x3E
+,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74
+,0x79,0x70,0x65,0x3D,0x22,0x62,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20,0x49,0x44,0x3D
+,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x22,0x20,0x73,0x74,0x79,0x6C,0x65
+,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61
+,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39
+,0x70,0x74,0x3B,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x30,0x30
+,0x3B,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63,0x6F,0x6C,0x6F
+,0x72,0x3A,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x3B,0x57,0x49,0x44,0x54,0x48,0x3A
+,0x20,0x37,0x30,0x70,0x78,0x3B,0x20,0x48,0x45,0x49,0x47,0x48,0x54,0x3A,0x20,0x34
+,0x30,0x70,0x78,0x22,0x20,0x6F,0x6E,0x43,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x6C,0x65
+,0x64,0x33,0x5F,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x22,0x20,0x76,0x61,0x6C
+,0x75,0x65,0x3D,0x22,0x4C,0x45,0x44,0x33,0x20,0x4F,0x66,0x66,0x22,0x3E,0x20,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75
+,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x62,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20
+,0x49,0x44,0x3D,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x34,0x22,0x20,0x73,0x74
+,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59
+,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A
+,0x45,0x3A,0x39,0x70,0x74,0x3B,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30
+,0x30,0x30,0x30,0x3B,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63
+,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x3B,0x57,0x49,0x44
+,0x54,0x48,0x3A,0x20,0x37,0x30,0x70,0x78,0x3B,0x20,0x48,0x45,0x49,0x47,0x48,0x54
+,0x3A,0x20,0x34,0x30,0x70,0x78,0x22,0x20,0x6F,0x6E,0x43,0x6C,0x69,0x63,0x6B,0x3D
+,0x22,0x6C,0x65,0x64,0x34,0x5F,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x22,0x20
+,0x76,0x61,0x6C,0x75,0x65,0x3D,0x22,0x4C,0x45,0x44,0x34,0x20,0x4F,0x66,0x66,0x22
+,0x3E,0x20,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79
+,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A
+};
+
+static const char i2c_set_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66
+,0x2D,0x38,0x22,0x3E,0x20,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x53,0x65
+,0x74,0x74,0x69,0x6E,0x67,0x20,0x62,0x79,0x20,0x49,0x32,0x43,0x3C,0x2F,0x74,0x69
+,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74,0x79
+,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72
+,0x69,0x70,0x74,0x22,0x20,0x73,0x72,0x63,0x3D,0x22,0x6D,0x62,0x65,0x64,0x52,0x50
+,0x43,0x2E,0x6A,0x73,0x22,0x20,0x6C,0x61,0x6E,0x67,0x75,0x61,0x67,0x65,0x3D,0x22
+,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x20,0x63,0x68,0x61,0x72
+,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66,0x2D,0x38,0x22,0x3E,0x3C,0x2F,0x73,0x63
+,0x72,0x69,0x70,0x74,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74
+,0x79,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63
+,0x72,0x69,0x70,0x74,0x22,0x3E,0x6D,0x62,0x65,0x64,0x3D,0x6E,0x65,0x77,0x20,0x48
+,0x54,0x54,0x50,0x52,0x50,0x43,0x28,0x29,0x3B,0x74,0x65,0x72,0x6D,0x3D,0x6E,0x65
+,0x77,0x20,0x52,0x50,0x43,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x6D,0x62
+,0x65,0x64,0x2C,0x22,0x53,0x65,0x74,0x49,0x32,0x43,0x66,0x72,0x6F,0x6D,0x57,0x65
+,0x62,0x22,0x29,0x3B,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D,0x0A,0x3C
+,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A
+,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x38
+,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x43
+,0x4F,0x4C,0x4F,0x52,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x62
+,0x3E,0x44,0x69,0x72,0x65,0x63,0x74,0x20,0x69,0x6E,0x70,0x75,0x74,0x3C,0x2F,0x62
+,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65
+,0x3D,0x22,0x74,0x65,0x78,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x64,0x69,0x72,0x5F
+,0x69,0x6E,0x22,0x3E,0x3C,0x2F,0x69,0x6E,0x70,0x75,0x74,0x3E,0x3C,0x62,0x75,0x74
+,0x74,0x6F,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D
+,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F
+,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x22,0x20,0x6F,0x6E,0x63
+,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x73,0x6E,0x64,0x5F,0x64,0x69,0x72,0x5F,0x69,0x6E
+,0x28,0x29,0x22,0x3E,0x53,0x65,0x6E,0x64,0x3C,0x2F,0x62,0x75,0x74,0x74,0x6F,0x6E
+,0x3E,0x20,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x0D,0x0A
+,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x38
+,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x43
+,0x4F,0x4C,0x4F,0x52,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x62
+,0x3E,0x46,0x69,0x6C,0x65,0x20,0x72,0x65,0x66,0x65,0x72,0x65,0x6E,0x63,0x65,0x3C
+,0x2F,0x62,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74
+,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79
+,0x70,0x65,0x3D,0x22,0x66,0x69,0x6C,0x65,0x22,0x20,0x69,0x64,0x3D,0x22,0x66,0x69
+,0x6C,0x65,0x5F,0x75,0x70,0x6C,0x6F,0x61,0x64,0x22,0x20,0x73,0x74,0x79,0x6C,0x65
+,0x3D,0x22,0x44,0x49,0x53,0x50,0x4C,0x41,0x59,0x3A,0x6E,0x6F,0x6E,0x65,0x22,0x20
+,0x6F,0x6E,0x63,0x68,0x61,0x6E,0x67,0x65,0x3D,0x22,0x74,0x78,0x74,0x5F,0x66,0x69
+,0x6C,0x65,0x6E,0x61,0x6D,0x65,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x74
+,0x68,0x69,0x73,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3B,0x22,0x20,0x61,0x63,0x63,0x65
+,0x70,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x70,0x6C,0x61,0x69,0x6E,0x22,0x3E
+,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74
+,0x65,0x78,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x74,0x78,0x74,0x5F,0x66,0x69,0x6C
+,0x65,0x6E,0x61,0x6D,0x65,0x22,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F
+,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61
+,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x22,0x20
+,0x73,0x69,0x7A,0x65,0x3D,0x22,0x32,0x35,0x22,0x20,0x44,0x49,0x53,0x41,0x42,0x4C
+,0x45,0x44,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65
+,0x3D,0x22,0x62,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20,0x69,0x64,0x3D,0x22,0x66,0x69
+,0x6C,0x65,0x5F,0x73,0x65,0x6C,0x65,0x63,0x74,0x22,0x20,0x73,0x74,0x79,0x6C,0x65
+,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61
+,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39
+,0x70,0x74,0x22,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x66,0x69,0x6C
+,0x65,0x5F,0x75,0x70,0x6C,0x6F,0x61,0x64,0x2E,0x63,0x6C,0x69,0x63,0x6B,0x28,0x29
+,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x3D,0x22,0x43,0x68,0x6F,0x6F,0x73,0x65,0x20
+,0x61,0x20,0x74,0x65,0x78,0x74,0x20,0x46,0x69,0x6C,0x65,0x22,0x3E,0x0D,0x0A,0x3C
+,0x62,0x75,0x74,0x74,0x6F,0x6E,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x73,0x75,0x62
+,0x6D,0x69,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x73,0x6E,0x64,0x62,0x6F,0x78,0x22
+,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D
+,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D
+,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x22,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63
+,0x6B,0x3D,0x22,0x73,0x6E,0x64,0x5F,0x66,0x69,0x6C,0x65,0x5F,0x72,0x65,0x66,0x28
+,0x29,0x22,0x3E,0x53,0x65,0x6E,0x64,0x3C,0x2F,0x62,0x75,0x74,0x74,0x6F,0x6E,0x3E
+,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x3C,0x70,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F
+,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61
+,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x31,0x38,0x70,0x74,0x22
+,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x43,0x4F
+,0x4C,0x4F,0x52,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x0D,0x0A,0x3C
+,0x62,0x3E,0x4C,0x4F,0x47,0x3A,0x3C,0x2F,0x62,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E
+,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22
+,0x73,0x75,0x62,0x6D,0x69,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x74,0x65,0x78,0x74
+,0x61,0x72,0x65,0x61,0x5F,0x63,0x6C,0x65,0x61,0x72,0x22,0x20,0x73,0x74,0x79,0x6C
+,0x65,0x3D,0x22,0x44,0x49,0x53,0x50,0x4C,0x41,0x59,0x3A,0x62,0x6C,0x6F,0x63,0x6B
+,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68
+,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70
+,0x74,0x3B,0x57,0x49,0x44,0x54,0x48,0x3A,0x37,0x30,0x70,0x78,0x3B,0x48,0x45,0x49
+,0x47,0x48,0x54,0x3A,0x32,0x30,0x70,0x78,0x3B,0x50,0x4F,0x53,0x49,0x54,0x49,0x4F
+,0x4E,0x3A,0x61,0x62,0x73,0x6F,0x6C,0x75,0x74,0x65,0x3B,0x4C,0x45,0x46,0x54,0x3A
+,0x38,0x70,0x78,0x22,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x43,0x6C
+,0x72,0x5F,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x22,0x20,0x76,0x61
+,0x6C,0x75,0x65,0x3D,0x22,0x43,0x6C,0x65,0x61,0x72,0x22,0x3E,0x0D,0x0A,0x3C,0x62
+,0x75,0x74,0x74,0x6F,0x6E,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x73,0x75,0x62,0x6D
+,0x69,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61
+,0x5F,0x73,0x61,0x76,0x65,0x22,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x44,0x49
+,0x53,0x50,0x4C,0x41,0x59,0x3A,0x62,0x6C,0x6F,0x63,0x6B,0x3B,0x46,0x4F,0x4E,0x54
+,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46
+,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x3B,0x57,0x49,0x44
+,0x54,0x48,0x3A,0x37,0x30,0x70,0x78,0x3B,0x48,0x45,0x49,0x47,0x48,0x54,0x3A,0x32
+,0x30,0x70,0x78,0x3B,0x50,0x4F,0x53,0x49,0x54,0x49,0x4F,0x4E,0x3A,0x61,0x62,0x73
+,0x6F,0x6C,0x75,0x74,0x65,0x3B,0x4C,0x45,0x46,0x54,0x3A,0x38,0x32,0x70,0x78,0x22
+,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x53,0x61,0x76,0x65,0x5F,0x74
+,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x22,0x3E,0x53,0x61,0x76,0x65,0x3C
+,0x2F,0x62,0x75,0x74,0x74,0x6F,0x6E,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x72,0x6D,0x20
+,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x22,0x3E
+,0x0D,0x0A,0x3C,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x20,0x69,0x64,0x3D,0x22
+,0x72,0x65,0x73,0x75,0x6C,0x74,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x74,0x65
+,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x22,0x20,0x63,0x6F,0x6C,0x73,0x3D,0x22,0x35
+,0x30,0x22,0x20,0x72,0x6F,0x77,0x73,0x3D,0x22,0x32,0x30,0x22,0x20,0x70,0x6C,0x61
+,0x63,0x65,0x68,0x6F,0x6C,0x64,0x65,0x72,0x3D,0x22,0x22,0x20,0x76,0x61,0x6C,0x75
+,0x65,0x3D,0x22,0x22,0x3E,0x3C,0x2F,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x3E
+,0x0D,0x0A,0x3C,0x2F,0x66,0x6F,0x72,0x6D,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D
+,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74
+,0x3E,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x73,0x6E,0x64,0x5F
+,0x64,0x69,0x72,0x5F,0x69,0x6E,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x76,0x61,0x72,0x20
+,0x72,0x63,0x76,0x5F,0x74,0x65,0x78,0x74,0x3B,0x0D,0x0A,0x09,0x69,0x66,0x20,0x28
+,0x28,0x64,0x69,0x72,0x5F,0x69,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x21,0x3D
+,0x20,0x6E,0x75,0x6C,0x6C,0x29,0x20,0x26,0x26,0x20,0x28,0x64,0x69,0x72,0x5F,0x69
+,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x21,0x3D,0x20,0x22,0x22,0x29,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75
+,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61
+,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B,0x53,0x45,0x4E,0x44
+,0x5D,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72
+,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x64,0x69,0x72,0x5F
+,0x69,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3B,0x0D,0x0A,0x09,0x09,0x64,0x6F,0x63
+,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74
+,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B
+,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x72,0x63,0x76
+,0x5F,0x74,0x65,0x78,0x74,0x20,0x3D,0x20,0x74,0x65,0x72,0x6D,0x2E,0x72,0x75,0x6E
+,0x28,0x64,0x69,0x72,0x5F,0x69,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x29,0x3B,0x0D
+,0x0A,0x09,0x09,0x69,0x66,0x20,0x28,0x72,0x63,0x76,0x5F,0x74,0x65,0x78,0x74,0x20
+,0x21,0x3D,0x20,0x22,0x72,0x75,0x6E,0x22,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x09
+,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72
+,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75
+,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B,0x52,0x45,0x43,0x56,0x5D,0x22,0x3B,0x0D,0x0A
+,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F
+,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76
+,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x72,0x63,0x76,0x5F,0x74,0x65,0x78,0x74
+,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F
+,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65
+,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E
+,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x7D,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A
+,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x73,0x6E,0x64,0x5F,0x66
+,0x69,0x6C,0x65,0x5F,0x72,0x65,0x66,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x76,0x61,0x72
+,0x20,0x6F,0x62,0x6A,0x20,0x3D,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22
+,0x66,0x69,0x6C,0x65,0x5F,0x75,0x70,0x6C,0x6F,0x61,0x64,0x22,0x29,0x2E,0x66,0x69
+,0x6C,0x65,0x73,0x5B,0x30,0x5D,0x3B,0x0D,0x0A,0x09,0x76,0x61,0x72,0x20,0x72,0x65
+,0x61,0x64,0x65,0x72,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x46,0x69,0x6C,0x65,0x52
+,0x65,0x61,0x64,0x65,0x72,0x28,0x29,0x3B,0x0D,0x0A,0x09,0x72,0x65,0x61,0x64,0x65
+,0x72,0x2E,0x6F,0x6E,0x6C,0x6F,0x61,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x28,0x65,0x76,0x74,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x76,0x61
+,0x72,0x20,0x73,0x74,0x72,0x20,0x3D,0x20,0x65,0x76,0x74,0x2E,0x74,0x61,0x72,0x67
+,0x65,0x74,0x2E,0x72,0x65,0x73,0x75,0x6C,0x74,0x3B,0x0D,0x0A,0x09,0x09,0x76,0x61
+,0x72,0x20,0x73,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x20,0x3D,0x20,0x73,0x74,0x72
+,0x2E,0x73,0x70,0x6C,0x69,0x74,0x28,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x29,0x3B,0x0D
+,0x0A,0x09,0x09,0x76,0x61,0x72,0x20,0x63,0x6E,0x74,0x20,0x3D,0x20,0x30,0x3B,0x0D
+,0x0A,0x09,0x09,0x76,0x61,0x72,0x20,0x72,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x20
+,0x3D,0x20,0x30,0x3B,0x0D,0x0A,0x09,0x09,0x77,0x68,0x69,0x6C,0x65,0x20,0x28,0x28
+,0x73,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x5B,0x63,0x6E,0x74,0x5D,0x20,0x21,0x3D
+,0x20,0x6E,0x75,0x6C,0x6C,0x29,0x20,0x26,0x26,0x20,0x28,0x73,0x6E,0x64,0x5F,0x64
+,0x61,0x74,0x61,0x5B,0x63,0x6E,0x74,0x5D,0x20,0x21,0x3D,0x20,0x22,0x22,0x29,0x29
+,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72
+,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B,0x53,0x45
+,0x4E,0x44,0x5D,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65
+,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74
+,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x73
+,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x5B,0x63,0x6E,0x74,0x5D,0x3B,0x0D,0x0A,0x09
+,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66
+,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61
+,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x3B,0x0D,0x0A
+,0x09,0x09,0x09,0x72,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x20,0x3D,0x20,0x74,0x65
+,0x72,0x6D,0x2E,0x72,0x75,0x6E,0x28,0x73,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x5B
+,0x63,0x6E,0x74,0x5D,0x29,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x69,0x66,0x20,0x28,0x72
+,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x20,0x21,0x3D,0x20,0x22,0x72,0x75,0x6E,0x22
+,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E
+,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F
+,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B
+,0x52,0x45,0x43,0x56,0x5D,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x09,0x64,0x6F,0x63
+,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74
+,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B
+,0x3D,0x20,0x72,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x3B,0x0D,0x0A,0x09,0x09,0x09
+,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F
+,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C
+,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x3B,0x0D,0x0A,0x09
+,0x09,0x09,0x7D,0x0D,0x0A,0x09,0x09,0x09,0x63,0x6E,0x74,0x2B,0x2B,0x3B,0x0D,0x0A
+,0x09,0x09,0x7D,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x09,0x72,0x65,0x61,0x64,0x65,0x72
+,0x2E,0x72,0x65,0x61,0x64,0x41,0x73,0x54,0x65,0x78,0x74,0x28,0x6F,0x62,0x6A,0x29
+,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x20,0x43,0x6C,0x72,0x5F,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x7B
+,0x0D,0x0A,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F
+,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76
+,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x22,0x22,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x53,0x61,0x76,0x65,0x5F,0x74
+,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x76,0x61,0x72
+,0x20,0x62,0x6C,0x6F,0x62,0x5F,0x6F,0x62,0x6A,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20
+,0x42,0x6C,0x6F,0x62,0x28,0x5B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F
+,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65
+,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x5D,0x2C,0x20,0x7B,0x74,0x79,0x70,0x65,0x3A
+,0x22,0x74,0x65,0x78,0x74,0x2F,0x70,0x6C,0x61,0x69,0x6E,0x22,0x7D,0x29,0x3B,0x0D
+,0x0A,0x09,0x3C,0x21,0x2D,0x2D,0x20,0x44,0x65,0x74,0x65,0x72,0x6D,0x69,0x6E,0x65
+,0x73,0x20,0x62,0x72,0x6F,0x77,0x73,0x65,0x72,0x20,0x2D,0x2D,0x3E,0x0D,0x0A,0x09
+,0x69,0x66,0x20,0x28,0x6E,0x61,0x76,0x69,0x67,0x61,0x74,0x6F,0x72,0x2E,0x6D,0x73
+,0x53,0x61,0x76,0x65,0x42,0x6C,0x6F,0x62,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x3C
+,0x21,0x2D,0x2D,0x20,0x49,0x45,0x20,0x2D,0x2D,0x3E,0x0D,0x0A,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x09,0x6E,0x61,0x76,0x69,0x67,0x61,0x74,0x6F,0x72,0x2E,0x6D
+,0x73,0x53,0x61,0x76,0x65,0x4F,0x72,0x4F,0x70,0x65,0x6E,0x42,0x6C,0x6F,0x62,0x28
+,0x62,0x6C,0x6F,0x62,0x5F,0x6F,0x62,0x6A,0x2C,0x20,0x27,0x63,0x6F,0x6D,0x6D,0x5F
+,0x6C,0x6F,0x67,0x2E,0x74,0x78,0x74,0x27,0x29,0x3B,0x0D,0x0A,0x09,0x7D,0x20,0x65
+,0x6C,0x73,0x65,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x3C,0x21,0x2D,0x2D,0x20,0x45,0x78
+,0x70,0x65,0x63,0x74,0x20,0x49,0x45,0x20,0x2D,0x2D,0x3E,0x0D,0x0A,0x09,0x09,0x76
+,0x61,0x72,0x20,0x61,0x20,0x3D,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x63,0x72,0x65,0x61,0x74,0x65,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x28,0x27,0x61
+,0x27,0x29,0x3B,0x0D,0x0A,0x09,0x09,0x61,0x2E,0x68,0x72,0x65,0x66,0x20,0x3D,0x20
+,0x55,0x52,0x4C,0x2E,0x63,0x72,0x65,0x61,0x74,0x65,0x4F,0x62,0x6A,0x65,0x63,0x74
+,0x55,0x52,0x4C,0x28,0x62,0x6C,0x6F,0x62,0x5F,0x6F,0x62,0x6A,0x29,0x3B,0x0D,0x0A
+,0x09,0x09,0x61,0x2E,0x73,0x65,0x74,0x41,0x74,0x74,0x72,0x69,0x62,0x75,0x74,0x65
+,0x28,0x27,0x64,0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64,0x27,0x2C,0x20,0x27,0x63,0x6F
+,0x6D,0x6D,0x5F,0x6C,0x6F,0x67,0x2E,0x74,0x78,0x74,0x27,0x29,0x3B,0x0D,0x0A,0x09
+,0x09,0x61,0x2E,0x64,0x69,0x73,0x70,0x61,0x74,0x63,0x68,0x45,0x76,0x65,0x6E,0x74
+,0x28,0x6E,0x65,0x77,0x20,0x43,0x75,0x73,0x74,0x6F,0x6D,0x45,0x76,0x65,0x6E,0x74
+,0x28,0x27,0x63,0x6C,0x69,0x63,0x6B,0x27,0x29,0x29,0x3B,0x0D,0x0A,0x09,0x7D,0x0D
+,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D
+,0x0A,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74
+,0x6D,0x6C,0x3E,0x0D,0x0A
+};
+
+static const char web_top_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66
+,0x2D,0x38,0x22,0x3E,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x54,0x6F,0x70
+,0x20,0x50,0x61,0x67,0x65,0x3C,0x2F,0x74,0x69,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C
+,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x66,0x72,0x61,0x6D,0x65,0x73,0x65
+,0x74,0x20,0x63,0x6F,0x6C,0x73,0x3D,0x22,0x32,0x30,0x25,0x2C,0x38,0x30,0x25,0x22
+,0x3E,0x0D,0x0A,0x3C,0x66,0x72,0x61,0x6D,0x65,0x20,0x73,0x72,0x63,0x3D,0x22,0x6D
+,0x65,0x6E,0x75,0x2E,0x68,0x74,0x6D,0x22,0x3E,0x0D,0x0A,0x3C,0x66,0x72,0x61,0x6D
+,0x65,0x20,0x73,0x72,0x63,0x3D,0x22,0x77,0x69,0x6E,0x64,0x6F,0x77,0x2E,0x68,0x74
+,0x6D,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65
+,0x22,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x6E,0x6F,0x66,0x72,0x61,0x6D,0x65,0x73,0x3E
+,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x70,0x3E,0x59,0x6F,0x75
+,0x20,0x63,0x61,0x6E,0x20,0x6E,0x6F,0x74,0x20,0x76,0x69,0x65,0x77,0x20,0x74,0x68
+,0x69,0x73,0x20,0x73,0x61,0x6D,0x70,0x6C,0x65,0x20,0x73,0x69,0x6E,0x63,0x65,0x20
+,0x74,0x68,0x65,0x20,0x66,0x72,0x61,0x6D,0x65,0x20,0x6F,0x66,0x20,0x75,0x6E,0x73
+,0x75,0x70,0x70,0x6F,0x72,0x74,0x65,0x64,0x20,0x62,0x72,0x6F,0x77,0x73,0x65,0x72
+,0x2E,0x3C,0x2F,0x70,0x3E,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A
+,0x3C,0x2F,0x6E,0x6F,0x66,0x72,0x61,0x6D,0x65,0x73,0x3E,0x0D,0x0A,0x3C,0x2F,0x66
+,0x72,0x61,0x6D,0x65,0x73,0x65,0x74,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C
+,0x3E,0x0D,0x0A
+};
+
+static const char menu_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66
+,0x2D,0x38,0x22,0x3E,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x47,0x52,0x2D
+,0x50,0x45,0x41,0x43,0x48,0x20,0x4D,0x65,0x6E,0x75,0x3C,0x2F,0x74,0x69,0x74,0x6C
+,0x65,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F
+,0x64,0x79,0x20,0x62,0x67,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x22,0x23,0x46,0x46,0x46
+,0x41,0x46,0x41,0x22,0x3E,0x0D,0x0A,0x3C,0x43,0x45,0x4E,0x54,0x45,0x52,0x3E,0x0D
+,0x0A,0x3C,0x50,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22
+,0x34,0x22,0x3E,0x3C,0x42,0x3E,0x4D,0x65,0x6E,0x75,0x3C,0x2F,0x42,0x3E,0x3C,0x2F
+,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x2F,0x50,0x3E,0x0D,0x0A,0x3C,0x2F,0x43,0x45,0x4E
+,0x54,0x45,0x52,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x70,0x3E,0x0D,0x0A,0x3C,0x66,0x6F
+,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61
+,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23
+,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x61,0x20,0x68,0x72,0x65,0x66,0x3D
+,0x22,0x77,0x69,0x6E,0x64,0x6F,0x77,0x2E,0x68,0x74,0x6D,0x22,0x20,0x74,0x61,0x72
+,0x67,0x65,0x74,0x3D,0x22,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65,0x22,0x3E,0x54,0x6F
+,0x70,0x20,0x50,0x61,0x67,0x65,0x3C,0x2F,0x61,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E
+,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22
+,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22
+,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C
+,0x61,0x20,0x68,0x72,0x65,0x66,0x3D,0x22,0x63,0x61,0x6D,0x65,0x72,0x61,0x2E,0x68
+,0x74,0x6D,0x22,0x20,0x74,0x61,0x72,0x67,0x65,0x74,0x3D,0x22,0x6B,0x69,0x72,0x69
+,0x6B,0x61,0x65,0x22,0x3E,0x57,0x65,0x62,0x20,0x43,0x61,0x6D,0x65,0x72,0x61,0x3C
+,0x2F,0x61,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74
+,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x66,0x6F
+,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61
+,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23
+,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x61,0x20,0x68,0x72,0x65,0x66,0x3D
+,0x22,0x69,0x32,0x63,0x5F,0x73,0x65,0x74,0x2E,0x68,0x74,0x6D,0x22,0x20,0x74,0x61
+,0x72,0x67,0x65,0x74,0x3D,0x22,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65,0x22,0x3E,0x53
+,0x65,0x74,0x74,0x69,0x6E,0x67,0x20,0x62,0x79,0x20,0x49,0x32,0x43,0x3C,0x2F,0x61
+,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x6E,0x74
+,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20
+,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30
+,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x61,0x20,0x68,0x72,0x65,0x66,0x3D,0x22,0x6C
+,0x65,0x64,0x2E,0x68,0x74,0x6D,0x22,0x20,0x74,0x61,0x72,0x67,0x65,0x74,0x3D,0x22
+,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65,0x22,0x3E,0x4C,0x45,0x44,0x20,0x4F,0x6E,0x2F
+,0x4F,0x66,0x66,0x3C,0x2F,0x61,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F
+,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64
+,0x79,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x0D,0x0A
+};
+
+static const char window_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x20,0x75,0x74
+,0x66,0x2D,0x38,0x22,0x3E,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x47,0x52
+,0x2D,0x4C,0x59,0x43,0x48,0x45,0x45,0x20,0x57,0x69,0x6E,0x64,0x6F,0x77,0x3C,0x2F
+,0x74,0x69,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D
+,0x0A,0x3C,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E
+,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x31,0x35,0x22,0x3E,0x3C,0x73,0x70,0x61
+,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23
+,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x62,0x3E,0x47,0x52,0x2D,0x4C,0x59
+,0x43,0x48,0x45,0x45,0x20,0x57,0x65,0x62,0x20,0x43,0x61,0x6D,0x65,0x72,0x61,0x20
+,0x53,0x61,0x6D,0x70,0x6C,0x65,0x3C,0x2F,0x62,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E
+,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62
+,0x72,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x54,0x68,0x69,0x73,0x20,0x73,0x61,0x6D
+,0x70,0x6C,0x65,0x20,0x70,0x72,0x6F,0x67,0x72,0x61,0x6D,0x20,0x75,0x73,0x69,0x6E
+,0x67,0x20,0x47,0x52,0x2D,0x4C,0x59,0x43,0x48,0x45,0x45,0x2E,0x3C,0x62,0x72,0x3E
+,0x0D,0x0A,0x57,0x68,0x65,0x6E,0x20,0x79,0x6F,0x75,0x20,0x70,0x72,0x65,0x73,0x73
+,0x20,0x74,0x68,0x65,0x20,0x4D,0x65,0x6E,0x75,0x20,0x6F,0x6E,0x20,0x74,0x68,0x65
+,0x20,0x6C,0x65,0x66,0x74,0x2C,0x20,0x69,0x74,0x20,0x77,0x69,0x6C,0x6C,0x20,0x62
+,0x65,0x20,0x64,0x69,0x73,0x70,0x6C,0x61,0x79,0x65,0x64,0x20,0x69,0x6E,0x20,0x74
+,0x68,0x69,0x73,0x20,0x77,0x69,0x6E,0x64,0x6F,0x77,0x2E,0x3C,0x62,0x72,0x3E,0x0D
+,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x49,0x74,0x20,0x73,0x68,0x6F,0x77,0x73,0x20
+,0x74,0x68,0x65,0x20,0x6F,0x76,0x65,0x72,0x76,0x69,0x65,0x77,0x20,0x6F,0x66,0x20
+,0x65,0x61,0x63,0x68,0x20,0x6C,0x69,0x6E,0x6B,0x20,0x62,0x65,0x6C,0x6F,0x77,0x2E
+,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x73,0x74,0x79
+,0x6C,0x65,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x63,0x73
+,0x73,0x22,0x3E,0x2E,0x74,0x61,0x62,0x6C,0x65,0x20,0x74,0x68,0x7B,0x62,0x61,0x63
+,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x65
+,0x36,0x66,0x66,0x65,0x39,0x7D,0x3C,0x2F,0x73,0x74,0x79,0x6C,0x65,0x3E,0x0D,0x0A
+,0x3C,0x74,0x61,0x62,0x6C,0x65,0x20,0x63,0x6C,0x61,0x73,0x73,0x3D,0x22,0x74,0x61
+,0x62,0x6C,0x65,0x22,0x20,0x62,0x6F,0x72,0x64,0x65,0x72,0x3D,0x31,0x3E,0x0D,0x0A
+,0x3C,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x68,0x3E,0x4C,0x69,0x6E,0x6B,0x73,0x3C
+,0x2F,0x74,0x68,0x3E,0x3C,0x74,0x68,0x3E,0x4F,0x76,0x65,0x72,0x76,0x69,0x65,0x77
+,0x3C,0x2F,0x74,0x68,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74
+,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x64,0x3E,0x54,0x6F,0x70,0x20,0x50,0x61,0x67,0x65
+,0x3C,0x2F,0x74,0x64,0x3E,0x3C,0x74,0x64,0x3E,0x49,0x74,0x20,0x77,0x69,0x6C,0x6C
+,0x20,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x74,0x6F,0x20,0x74,0x68,0x65,0x20,0x74
+,0x6F,0x70,0x20,0x70,0x61,0x67,0x65,0x2E,0x3C,0x62,0x72,0x3E,0x3C,0x2F,0x74,0x64
+,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x72,0x3E,0x0D,0x0A
+,0x3C,0x74,0x64,0x3E,0x57,0x65,0x62,0x20,0x43,0x61,0x6D,0x65,0x72,0x61,0x3C,0x2F
+,0x74,0x64,0x3E,0x3C,0x74,0x64,0x3E,0x49,0x74,0x20,0x69,0x6E,0x64,0x69,0x63,0x61
+,0x74,0x65,0x73,0x20,0x74,0x68,0x65,0x20,0x69,0x6D,0x61,0x67,0x65,0x20,0x61,0x63
+,0x71,0x75,0x69,0x72,0x65,0x64,0x20,0x62,0x79,0x20,0x74,0x68,0x65,0x20,0x63,0x61
+,0x6D,0x65,0x72,0x61,0x20,0x6F,0x6E,0x20,0x74,0x68,0x65,0x20,0x77,0x65,0x62,0x20
+,0x62,0x72,0x6F,0x77,0x73,0x65,0x72,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x49,0x74
+,0x20,0x63,0x61,0x6E,0x20,0x62,0x65,0x20,0x63,0x68,0x61,0x6E,0x67,0x65,0x64,0x20
+,0x61,0x74,0x20,0x61,0x20,0x73,0x6C,0x69,0x64,0x65,0x72,0x20,0x62,0x61,0x72,0x20
+,0x69,0x6E,0x20,0x22,0x57,0x61,0x69,0x74,0x20,0x74,0x69,0x6D,0x65,0x22,0x20,0x61
+,0x74,0x20,0x74,0x68,0x65,0x20,0x74,0x69,0x6D,0x69,0x6E,0x67,0x20,0x6F,0x66,0x20
+,0x61,0x20,0x72,0x65,0x6E,0x65,0x77,0x61,0x6C,0x20,0x6F,0x66,0x20,0x61,0x20,0x63
+,0x61,0x6D,0x65,0x72,0x61,0x20,0x70,0x69,0x63,0x74,0x75,0x72,0x65,0x2E,0x20,0x28
+,0x44,0x65,0x66,0x61,0x75,0x6C,0x74,0x73,0x20,0x61,0x72,0x65,0x20,0x35,0x30,0x30
+,0x6D,0x73,0x2E,0x29,0x3C,0x2F,0x74,0x64,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x72,0x3E
+,0x0D,0x0A,0x3C,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x64,0x3E,0x53,0x65,0x74,0x74
+,0x69,0x6E,0x67,0x20,0x62,0x79,0x20,0x49,0x32,0x43,0x3C,0x2F,0x74,0x64,0x3E,0x3C
+,0x74,0x64,0x3E,0x49,0x74,0x20,0x69,0x6E,0x64,0x69,0x63,0x61,0x74,0x65,0x73,0x20
+,0x49,0x32,0x43,0x20,0x73,0x65,0x74,0x74,0x69,0x6E,0x67,0x20,0x6F,0x6E,0x20,0x74
+,0x68,0x65,0x20,0x77,0x65,0x62,0x20,0x62,0x72,0x6F,0x77,0x73,0x65,0x72,0x2E,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x49,0x6E,0x20,0x49,0x32,0x43,0x20,0x63,0x6F,0x6D,0x6D
+,0x75,0x6E,0x69,0x63,0x61,0x74,0x69,0x6F,0x6E,0x2C,0x20,0x47,0x52,0x2D,0x4C,0x59
+,0x43,0x48,0x45,0x45,0x20,0x65,0x78,0x65,0x63,0x75,0x74,0x65,0x73,0x20,0x74,0x68
+,0x65,0x20,0x73,0x65,0x74,0x74,0x69,0x6E,0x67,0x73,0x20,0x6F,0x66,0x20,0x74,0x68
+,0x65,0x20,0x64,0x65,0x76,0x69,0x63,0x65,0x73,0x20,0x63,0x6F,0x6E,0x6E,0x65,0x63
+,0x74,0x65,0x64,0x20,0x74,0x6F,0x20,0x49,0x32,0x43,0x5F,0x53,0x43,0x41,0x20,0x74
+,0x65,0x72,0x6D,0x69,0x6E,0x61,0x6C,0x20,0x61,0x6E,0x64,0x20,0x49,0x32,0x43,0x5F
+,0x53,0x43,0x4C,0x20,0x74,0x65,0x72,0x6D,0x69,0x6E,0x61,0x6C,0x2E,0x3C,0x62,0x72
+,0x3E,0x0D,0x0A,0x4F,0x6E,0x20,0x74,0x68,0x65,0x20,0x62,0x61,0x73,0x69,0x73,0x20
+,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x63,0x6F,0x6D,0x6D,0x61,0x6E,0x64,0x2C,0x20
+,0x47,0x52,0x2D,0x4C,0x59,0x43,0x48,0x45,0x45,0x20,0x61,0x63,0x63,0x65,0x73,0x73
+,0x65,0x73,0x20,0x74,0x6F,0x20,0x72,0x65,0x67,0x69,0x73,0x74,0x65,0x72,0x73,0x20
+,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x64,0x65,0x76,0x69,0x63,0x65,0x73,0x2E,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x59,0x6F,0x75,0x20,0x63,0x61,0x6E,0x20,0x73,0x65,0x6E
+,0x64,0x20,0x74,0x68,0x65,0x20,0x63,0x6F,0x6D,0x6D,0x61,0x6E,0x64,0x20,0x6F,0x66
+,0x20,0x74,0x68,0x65,0x20,0x73,0x70,0x65,0x63,0x69,0x66,0x69,0x65,0x64,0x20,0x66
+,0x6F,0x72,0x6D,0x61,0x74,0x20,0x69,0x6E,0x20,0x6F,0x6E,0x65,0x20,0x6F,0x66,0x20
+,0x74,0x77,0x6F,0x20,0x70,0x61,0x74,0x74,0x65,0x72,0x6E,0x73,0x20,0x62,0x65,0x6C
+,0x6F,0x77,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26
+,0x6E,0x62,0x73,0x70,0x3B,0x22,0x44,0x69,0x72,0x65,0x63,0x74,0x6C,0x20,0x69,0x6E
+,0x70,0x75,0x74,0x22,0x20,0x6F,0x72,0x20,0x22,0x46,0x69,0x6C,0x65,0x20,0x72,0x65
+,0x66,0x65,0x72,0x65,0x6E,0x63,0x65,0x22,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x50
+,0x6C,0x65,0x61,0x73,0x65,0x20,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x63
+,0x6F,0x6D,0x6D,0x61,0x6E,0x64,0x20,0x61,0x6C,0x6F,0x6E,0x67,0x20,0x74,0x68,0x65
+,0x20,0x66,0x6F,0x72,0x6D,0x61,0x74,0x20,0x61,0x66,0x74,0x65,0x72,0x20,0x79,0x6F
+,0x75,0x20,0x63,0x68,0x65,0x63,0x6B,0x20,0x74,0x68,0x65,0x20,0x73,0x70,0x65,0x63
+,0x69,0x66,0x69,0x63,0x61,0x74,0x69,0x6F,0x6E,0x73,0x20,0x6F,0x66,0x20,0x65,0x61
+,0x63,0x68,0x20,0x64,0x65,0x76,0x69,0x63,0x65,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A
+,0x54,0x68,0x65,0x20,0x66,0x6F,0x72,0x6D,0x61,0x74,0x20,0x6F,0x66,0x20,0x74,0x68
+,0x65,0x20,0x63,0x6F,0x6D,0x6D,0x61,0x6E,0x64,0x20,0x69,0x73,0x3A,0x3C,0x62,0x72
+,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x4D
+,0x65,0x74,0x68,0x6F,0x64,0x3A,0x49,0x32,0x43,0x20,0x61,0x64,0x64,0x72,0x2C,0x64
+,0x61,0x74,0x61,0x20,0x6C,0x65,0x6E,0x67,0x74,0x68,0x2C,0x64,0x61,0x74,0x61,0x31
+,0x2C,0x64,0x61,0x74,0x61,0x32,0x2C,0x64,0x61,0x74,0x61,0x33,0x2C,0x2E,0x2E,0x2E
+,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x4D,0x65,0x74,0x68
+,0x6F,0x64,0x20,0x69,0x73,0x20,0x62,0x65,0x6C,0x6F,0x77,0x2E,0x3C,0x62,0x72,0x3E
+,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E
+,0x62,0x73,0x70,0x3B,0x22,0x57,0x72,0x22,0x69,0x73,0x20,0x57,0x72,0x69,0x74,0x65
+,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x26
+,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70
+,0x3B,0x22,0x52,0x64,0x22,0x20,0x69,0x73,0x20,0x52,0x65,0x61,0x64,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73
+,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x22,0x57
+,0x72,0x4E,0x6F,0x70,0x22,0x20,0x69,0x73,0x20,0x57,0x72,0x69,0x74,0x65,0x20,0x66
+,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x4E,0x6F,0x20,0x53,0x54,0x4F,0x50,0x20
+,0x63,0x6F,0x6E,0x64,0x69,0x74,0x69,0x6F,0x6E,0x29,0x3C,0x62,0x72,0x3E,0x0D,0x0A
+,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73
+,0x70,0x3B,0x22,0x52,0x64,0x4E,0x6F,0x70,0x22,0x20,0x69,0x73,0x20,0x52,0x65,0x61
+,0x64,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x4E,0x6F,0x20,0x53,0x54
+,0x4F,0x50,0x20,0x63,0x6F,0x6E,0x64,0x69,0x74,0x69,0x6F,0x6E,0x29,0x3C,0x62,0x72
+,0x3E,0x3C,0x2F,0x74,0x64,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x72,0x3E,0x0D,0x0A,0x3C
+,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x64,0x3E,0x4C,0x45,0x44,0x20,0x4F,0x6E,0x2F
+,0x4F,0x66,0x66,0x3C,0x2F,0x74,0x64,0x3E,0x3C,0x74,0x64,0x3E,0x49,0x74,0x20,0x69
+,0x6E,0x64,0x69,0x63,0x61,0x74,0x65,0x73,0x20,0x4C,0x45,0x44,0x31,0x2C,0x20,0x4C
+,0x45,0x44,0x32,0x20,0x61,0x6E,0x64,0x20,0x4C,0x45,0x44,0x33,0x20,0x6F,0x66,0x20
+,0x74,0x68,0x65,0x20,0x74,0x6F,0x67,0x67,0x6C,0x65,0x20,0x73,0x77,0x69,0x74,0x63
+,0x68,0x20,0x6F,0x6E,0x20,0x74,0x68,0x65,0x20,0x77,0x65,0x62,0x20,0x62,0x72,0x6F
+,0x77,0x73,0x65,0x72,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x45,0x61,0x63,0x68,0x20
+,0x73,0x77,0x69,0x74,0x63,0x68,0x20,0x69,0x6E,0x64,0x69,0x63,0x61,0x74,0x65,0x73
+,0x20,0x74,0x68,0x65,0x20,0x63,0x75,0x72,0x72,0x65,0x6E,0x74,0x20,0x4C,0x45,0x44
+,0x20,0x73,0x74,0x61,0x74,0x65,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x4C,0x45,0x44
+,0x20,0x4F,0x4E,0x20,0x61,0x6E,0x64,0x20,0x4F,0x46,0x46,0x20,0x73,0x77,0x69,0x74
+,0x63,0x68,0x65,0x73,0x20,0x77,0x68,0x65,0x6E,0x20,0x79,0x6F,0x75,0x20,0x70,0x72
+,0x65,0x73,0x73,0x20,0x74,0x68,0x65,0x20,0x73,0x77,0x69,0x74,0x63,0x68,0x2E,0x20
+,0x57,0x68,0x65,0x6E,0x20,0x74,0x68,0x65,0x20,0x4C,0x45,0x44,0x20,0x69,0x73,0x20
+,0x4F,0x4E,0x2C,0x20,0x74,0x68,0x65,0x20,0x63,0x6F,0x6C,0x6F,0x72,0x20,0x6F,0x66
+,0x20,0x74,0x68,0x65,0x20,0x73,0x77,0x69,0x74,0x63,0x68,0x20,0x77,0x69,0x6C,0x6C
+,0x20,0x63,0x68,0x61,0x6E,0x67,0x65,0x20,0x74,0x68,0x65,0x20,0x4C,0x45,0x44,0x20
+,0x63,0x6F,0x6C,0x6F,0x72,0x2E,0x3C,0x2F,0x74,0x64,0x3E,0x0D,0x0A,0x3C,0x2F,0x74
+,0x72,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x61,0x62,0x6C,0x65,0x3E,0x0D,0x0A,0x0D,0x0A
+,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D
+,0x6C,0x3E,0x0D,0x0A,0x0D,0x0A
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/file_table_peach.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1225 @@
+
+static const char index_htm_tbl[] = {
+ 0x3C,0x53,0x43,0x52,0x49,0x50,0x54,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65
+,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x3E,0x0D
+,0x0A,0x3C,0x21,0x2D,0x2D,0x0D,0x0A,0x6C,0x6F,0x63,0x61,0x74,0x69,0x6F,0x6E,0x2E
+,0x68,0x72,0x65,0x66,0x3D,0x22,0x2F,0x77,0x65,0x62,0x5F,0x74,0x6F,0x70,0x2E,0x68
+,0x74,0x6D,0x22,0x3B,0x0D,0x0A,0x2D,0x2D,0x3E,0x0D,0x0A,0x3C,0x2F,0x53,0x43,0x52
+,0x49,0x50,0x54,0x3E,0x0D,0x0A
+};
+
+static const char camaera_js_tbl[] = {
+ 0x76,0x61,0x72,0x20,0x69,0x6D,0x61,0x67,0x65,0x4E,0x72,0x20,0x3D,0x20,0x30,0x3B
+,0x20,0x2F,0x2F,0x20,0x53,0x65,0x72,0x69,0x61,0x6C,0x20,0x6E,0x75,0x6D,0x62,0x65
+,0x72,0x20,0x6F,0x66,0x20,0x63,0x75,0x72,0x72,0x65,0x6E,0x74,0x20,0x69,0x6D,0x61
+,0x67,0x65,0x0D,0x0A,0x76,0x61,0x72,0x20,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64
+,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x41,0x72,0x72,0x61,0x79,0x28,0x29,0x3B,0x20
+,0x2F,0x2F,0x20,0x52,0x65,0x66,0x65,0x72,0x65,0x6E,0x63,0x65,0x73,0x20,0x74,0x6F
+,0x20,0x69,0x6D,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x73,0x20,0x77,0x68,0x69
+,0x63,0x68,0x20,0x68,0x61,0x76,0x65,0x20,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64
+,0x20,0x64,0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64,0x69,0x6E,0x67,0x0D,0x0A,0x0D,0x0A
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x63,0x72,0x65,0x61,0x74,0x65,0x49
+,0x6D,0x61,0x67,0x65,0x4C,0x61,0x79,0x65,0x72,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x20
+,0x20,0x76,0x61,0x72,0x20,0x69,0x6D,0x61,0x67,0x65,0x20,0x3D,0x20,0x6E,0x65,0x77
+,0x20,0x49,0x6D,0x61,0x67,0x65,0x28,0x29,0x3B,0x0D,0x0A,0x0D,0x0A,0x20,0x20,0x69
+,0x6D,0x61,0x67,0x65,0x2E,0x73,0x72,0x63,0x20,0x3D,0x20,0x22,0x63,0x61,0x6D,0x65
+,0x72,0x61,0x2F,0x22,0x20,0x2B,0x20,0x28,0x2B,0x2B,0x69,0x6D,0x61,0x67,0x65,0x4E
+,0x72,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61,0x67,0x65,0x2E,0x73,0x74,0x79
+,0x6C,0x65,0x2E,0x70,0x6F,0x73,0x69,0x74,0x69,0x6F,0x6E,0x20,0x3D,0x20,0x22,0x61
+,0x62,0x73,0x6F,0x6C,0x75,0x74,0x65,0x22,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61
+,0x67,0x65,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x7A,0x49,0x6E,0x64,0x65,0x78,0x20
+,0x3D,0x20,0x2D,0x31,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61,0x67,0x65,0x2E,0x6F
+,0x6E,0x6C,0x6F,0x61,0x64,0x20,0x3D,0x20,0x69,0x6D,0x61,0x67,0x65,0x4F,0x6E,0x6C
+,0x6F,0x61,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x69,0x6D,0x61,0x67,0x65,0x2E,0x6F,0x6E
+,0x65,0x72,0x72,0x6F,0x72,0x20,0x3D,0x20,0x63,0x72,0x65,0x61,0x74,0x65,0x49,0x6D
+,0x61,0x67,0x65,0x4C,0x61,0x79,0x65,0x72,0x3B,0x0D,0x0A,0x0D,0x0A,0x20,0x20,0x76
+,0x61,0x72,0x20,0x77,0x65,0x62,0x63,0x61,0x6D,0x20,0x3D,0x20,0x64,0x6F,0x63,0x75
+,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42
+,0x79,0x49,0x64,0x28,0x22,0x77,0x65,0x62,0x63,0x61,0x6D,0x22,0x29,0x3B,0x0D,0x0A
+,0x20,0x20,0x77,0x65,0x62,0x63,0x61,0x6D,0x2E,0x69,0x6E,0x73,0x65,0x72,0x74,0x42
+,0x65,0x66,0x6F,0x72,0x65,0x28,0x69,0x6D,0x61,0x67,0x65,0x2C,0x20,0x77,0x65,0x62
+,0x63,0x61,0x6D,0x2E,0x66,0x69,0x72,0x73,0x74,0x43,0x68,0x69,0x6C,0x64,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20
+,0x69,0x6D,0x61,0x67,0x65,0x4F,0x6E,0x6C,0x6F,0x61,0x64,0x28,0x29,0x20,0x7B,0x0D
+,0x0A,0x20,0x20,0x74,0x68,0x69,0x73,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x7A,0x49
+,0x6E,0x64,0x65,0x78,0x20,0x3D,0x20,0x69,0x6D,0x61,0x67,0x65,0x4E,0x72,0x3B,0x0D
+,0x0A,0x20,0x20,0x77,0x68,0x69,0x6C,0x65,0x20,0x28,0x31,0x20,0x3C,0x20,0x66,0x69
+,0x6E,0x69,0x73,0x68,0x65,0x64,0x2E,0x6C,0x65,0x6E,0x67,0x74,0x68,0x29,0x20,0x7B
+,0x0D,0x0A,0x20,0x20,0x20,0x20,0x76,0x61,0x72,0x20,0x64,0x65,0x6C,0x20,0x3D,0x20
+,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64,0x2E,0x73,0x68,0x69,0x66,0x74,0x28,0x29
+,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x64,0x65,0x6C,0x2E,0x70,0x61,0x72,0x65,0x6E
+,0x74,0x4E,0x6F,0x64,0x65,0x2E,0x72,0x65,0x6D,0x6F,0x76,0x65,0x43,0x68,0x69,0x6C
+,0x64,0x28,0x64,0x65,0x6C,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x7D,0x0D,0x0A,0x20,0x20
+,0x66,0x69,0x6E,0x69,0x73,0x68,0x65,0x64,0x2E,0x70,0x75,0x73,0x68,0x28,0x74,0x68
+,0x69,0x73,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x74,0x69,0x6D,0x65,0x72,0x49,0x44,0x20
+,0x3D,0x20,0x73,0x65,0x74,0x54,0x69,0x6D,0x65,0x6F,0x75,0x74,0x28,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x7B,0x20,0x63,0x72,0x65,0x61,0x74,0x65,0x49
+,0x6D,0x61,0x67,0x65,0x4C,0x61,0x79,0x65,0x72,0x28,0x29,0x20,0x7D,0x2C,0x20,0x64
+,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x46,0x31,0x2E,0x77,0x61,0x69,0x74,0x74
+,0x69,0x6D,0x65,0x2E,0x76,0x61,0x6C,0x75,0x65,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A
+};
+
+static const char camera_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x63,0x61,0x6D,0x65,0x72,0x61,0x3C,0x2F,0x74
+,0x69,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74
+,0x79,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63
+,0x72,0x69,0x70,0x74,0x22,0x20,0x73,0x72,0x63,0x3D,0x22,0x63,0x61,0x6D,0x65,0x72
+,0x61,0x2E,0x6A,0x73,0x22,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75
+,0x74,0x66,0x2D,0x38,0x22,0x3E,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D
+,0x0A,0x3C,0x73,0x74,0x79,0x6C,0x65,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65
+,0x78,0x74,0x2F,0x63,0x73,0x73,0x22,0x3E,0x0D,0x0A,0x23,0x77,0x65,0x62,0x63,0x61
+,0x6D,0x20,0x69,0x6D,0x67,0x20,0x7B,0x0D,0x0A,0x09,0x6C,0x65,0x66,0x74,0x3A,0x20
+,0x30,0x3B,0x0D,0x0A,0x09,0x72,0x69,0x67,0x68,0x74,0x3A,0x20,0x30,0x3B,0x0D,0x0A
+,0x09,0x6D,0x61,0x78,0x2D,0x77,0x69,0x64,0x74,0x68,0x3A,0x20,0x36,0x34,0x30,0x70
+,0x78,0x3B,0x20,0x0D,0x0A,0x09,0x77,0x69,0x64,0x74,0x68,0x3A,0x20,0x31,0x30,0x30
+,0x25,0x3B,0x0D,0x0A,0x09,0x68,0x65,0x69,0x67,0x68,0x74,0x3A,0x20,0x61,0x75,0x74
+,0x6F,0x3B,0x20,0x0D,0x0A,0x7D,0x0D,0x0A,0x3C,0x2F,0x73,0x74,0x79,0x6C,0x65,0x3E
+,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79
+,0x3E,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79,0x20,0x6F,0x6E,0x6C,0x6F,0x61,0x64,0x3D
+,0x22,0x63,0x72,0x65,0x61,0x74,0x65,0x49,0x6D,0x61,0x67,0x65,0x4C,0x61,0x79,0x65
+,0x72,0x28,0x29,0x3B,0x22,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x72,0x6D,0x20,0x61,0x63
+,0x74,0x69,0x6F,0x6E,0x3D,0x22,0x23,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x46
+,0x31,0x22,0x3E,0x0D,0x0A,0x57,0x61,0x69,0x74,0x20,0x74,0x69,0x6D,0x65,0x20,0x3C
+,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x72,0x61,0x6E,0x67
+,0x65,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x77,0x61,0x69,0x74,0x74,0x69,0x6D
+,0x65,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x3D,0x22,0x35,0x30,0x30,0x22,0x20,0x6D
+,0x61,0x78,0x3D,0x22,0x31,0x30,0x30,0x30,0x22,0x20,0x73,0x74,0x65,0x70,0x3D,0x22
+,0x35,0x30,0x22,0x3E,0x20,0x5B,0x6D,0x73,0x5D,0x0D,0x0A,0x3C,0x2F,0x66,0x6F,0x72
+,0x6D,0x3E,0x0D,0x0A,0x3C,0x64,0x69,0x76,0x20,0x69,0x64,0x3D,0x22,0x77,0x65,0x62
+,0x63,0x61,0x6D,0x22,0x3E,0x3C,0x6E,0x6F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x3C
+,0x69,0x6D,0x67,0x20,0x73,0x72,0x63,0x3D,0x22,0x63,0x61,0x6D,0x65,0x72,0x61,0x2F
+,0x30,0x22,0x20,0x2F,0x3E,0x3C,0x2F,0x6E,0x6F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E
+,0x3C,0x2F,0x64,0x69,0x76,0x3E,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79,0x3E,0x0D
+,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A
+};
+
+static const char mbedrpc_js_tbl[] = {
+ 0x2F,0x2F,0x20,0x6D,0x62,0x65,0x64,0x52,0x50,0x43,0x20,0x4A,0x61,0x76,0x61,0x73
+,0x63,0x72,0x69,0x70,0x74,0x20,0x49,0x6E,0x74,0x65,0x72,0x66,0x61,0x63,0x65,0x20
+,0x75,0x73,0x69,0x6E,0x67,0x20,0x48,0x54,0x54,0x50,0x0D,0x0A,0x2F,0x2F,0x20,0x73
+,0x66,0x6F,0x72,0x64,0x20,0x61,0x6E,0x64,0x20,0x4D,0x20,0x57,0x61,0x6C,0x6B,0x65
+,0x72,0x0D,0x0A,0x2F,0x2F,0x20,0x41,0x20,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69
+,0x70,0x74,0x20,0x69,0x6E,0x74,0x65,0x72,0x66,0x61,0x63,0x65,0x20,0x66,0x6F,0x72
+,0x20,0x74,0x61,0x6C,0x6B,0x69,0x6E,0x67,0x20,0x74,0x6F,0x20,0x6D,0x62,0x65,0x64
+,0x20,0x72,0x70,0x63,0x20,0x6F,0x76,0x65,0x72,0x20,0x68,0x74,0x74,0x70,0x0D,0x0A
+,0x2F,0x2F,0x0D,0x0A,0x2F,0x2F,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20
+,0x28,0x63,0x29,0x20,0x32,0x30,0x31,0x30,0x20,0x41,0x52,0x4D,0x20,0x4C,0x74,0x64
+,0x0D,0x0A,0x2F,0x2F,0x20,0x0D,0x0A,0x2F,0x2F,0x50,0x65,0x72,0x6D,0x69,0x73,0x73
+,0x69,0x6F,0x6E,0x20,0x69,0x73,0x20,0x68,0x65,0x72,0x65,0x62,0x79,0x20,0x67,0x72
+,0x61,0x6E,0x74,0x65,0x64,0x2C,0x20,0x66,0x72,0x65,0x65,0x20,0x6F,0x66,0x20,0x63
+,0x68,0x61,0x72,0x67,0x65,0x2C,0x20,0x74,0x6F,0x20,0x61,0x6E,0x79,0x20,0x70,0x65
+,0x72,0x73,0x6F,0x6E,0x20,0x6F,0x62,0x74,0x61,0x69,0x6E,0x69,0x6E,0x67,0x20,0x61
+,0x20,0x63,0x6F,0x70,0x79,0x0D,0x0A,0x2F,0x2F,0x6F,0x66,0x20,0x74,0x68,0x69,0x73
+,0x20,0x73,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x61,0x6E,0x64,0x20,0x61,0x73
+,0x73,0x6F,0x63,0x69,0x61,0x74,0x65,0x64,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E
+,0x74,0x61,0x74,0x69,0x6F,0x6E,0x20,0x66,0x69,0x6C,0x65,0x73,0x20,0x28,0x74,0x68
+,0x65,0x20,0x22,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x22,0x29,0x2C,0x20,0x74
+,0x6F,0x20,0x64,0x65,0x61,0x6C,0x0D,0x0A,0x2F,0x2F,0x69,0x6E,0x20,0x74,0x68,0x65
+,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x77,0x69,0x74,0x68,0x6F,0x75
+,0x74,0x20,0x72,0x65,0x73,0x74,0x72,0x69,0x63,0x74,0x69,0x6F,0x6E,0x2C,0x20,0x69
+,0x6E,0x63,0x6C,0x75,0x64,0x69,0x6E,0x67,0x20,0x77,0x69,0x74,0x68,0x6F,0x75,0x74
+,0x20,0x6C,0x69,0x6D,0x69,0x74,0x61,0x74,0x69,0x6F,0x6E,0x20,0x74,0x68,0x65,0x20
+,0x72,0x69,0x67,0x68,0x74,0x73,0x0D,0x0A,0x2F,0x2F,0x74,0x6F,0x20,0x75,0x73,0x65
+,0x2C,0x20,0x63,0x6F,0x70,0x79,0x2C,0x20,0x6D,0x6F,0x64,0x69,0x66,0x79,0x2C,0x20
+,0x6D,0x65,0x72,0x67,0x65,0x2C,0x20,0x70,0x75,0x62,0x6C,0x69,0x73,0x68,0x2C,0x20
+,0x64,0x69,0x73,0x74,0x72,0x69,0x62,0x75,0x74,0x65,0x2C,0x20,0x73,0x75,0x62,0x6C
+,0x69,0x63,0x65,0x6E,0x73,0x65,0x2C,0x20,0x61,0x6E,0x64,0x2F,0x6F,0x72,0x20,0x73
+,0x65,0x6C,0x6C,0x0D,0x0A,0x2F,0x2F,0x63,0x6F,0x70,0x69,0x65,0x73,0x20,0x6F,0x66
+,0x20,0x74,0x68,0x65,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x2C,0x20,0x61
+,0x6E,0x64,0x20,0x74,0x6F,0x20,0x70,0x65,0x72,0x6D,0x69,0x74,0x20,0x70,0x65,0x72
+,0x73,0x6F,0x6E,0x73,0x20,0x74,0x6F,0x20,0x77,0x68,0x6F,0x6D,0x20,0x74,0x68,0x65
+,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72,0x65,0x20,0x69,0x73,0x0D,0x0A,0x2F,0x2F
+,0x66,0x75,0x72,0x6E,0x69,0x73,0x68,0x65,0x64,0x20,0x74,0x6F,0x20,0x64,0x6F,0x20
+,0x73,0x6F,0x2C,0x20,0x73,0x75,0x62,0x6A,0x65,0x63,0x74,0x20,0x74,0x6F,0x20,0x74
+,0x68,0x65,0x20,0x66,0x6F,0x6C,0x6C,0x6F,0x77,0x69,0x6E,0x67,0x20,0x63,0x6F,0x6E
+,0x64,0x69,0x74,0x69,0x6F,0x6E,0x73,0x3A,0x0D,0x0A,0x2F,0x2F,0x20,0x0D,0x0A,0x2F
+,0x2F,0x54,0x68,0x65,0x20,0x61,0x62,0x6F,0x76,0x65,0x20,0x63,0x6F,0x70,0x79,0x72
+,0x69,0x67,0x68,0x74,0x20,0x6E,0x6F,0x74,0x69,0x63,0x65,0x20,0x61,0x6E,0x64,0x20
+,0x74,0x68,0x69,0x73,0x20,0x70,0x65,0x72,0x6D,0x69,0x73,0x73,0x69,0x6F,0x6E,0x20
+,0x6E,0x6F,0x74,0x69,0x63,0x65,0x20,0x73,0x68,0x61,0x6C,0x6C,0x20,0x62,0x65,0x20
+,0x69,0x6E,0x63,0x6C,0x75,0x64,0x65,0x64,0x20,0x69,0x6E,0x0D,0x0A,0x2F,0x2F,0x61
+,0x6C,0x6C,0x20,0x63,0x6F,0x70,0x69,0x65,0x73,0x20,0x6F,0x72,0x20,0x73,0x75,0x62
+,0x73,0x74,0x61,0x6E,0x74,0x69,0x61,0x6C,0x20,0x70,0x6F,0x72,0x74,0x69,0x6F,0x6E
+,0x73,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x53,0x6F,0x66,0x74,0x77,0x61,0x72
+,0x65,0x2E,0x0D,0x0A,0x2F,0x2F,0x20,0x0D,0x0A,0x2F,0x2F,0x54,0x48,0x45,0x20,0x53
+,0x4F,0x46,0x54,0x57,0x41,0x52,0x45,0x20,0x49,0x53,0x20,0x50,0x52,0x4F,0x56,0x49
+,0x44,0x45,0x44,0x20,0x22,0x41,0x53,0x20,0x49,0x53,0x22,0x2C,0x20,0x57,0x49,0x54
+,0x48,0x4F,0x55,0x54,0x20,0x57,0x41,0x52,0x52,0x41,0x4E,0x54,0x59,0x20,0x4F,0x46
+,0x20,0x41,0x4E,0x59,0x20,0x4B,0x49,0x4E,0x44,0x2C,0x20,0x45,0x58,0x50,0x52,0x45
+,0x53,0x53,0x20,0x4F,0x52,0x0D,0x0A,0x2F,0x2F,0x49,0x4D,0x50,0x4C,0x49,0x45,0x44
+,0x2C,0x20,0x49,0x4E,0x43,0x4C,0x55,0x44,0x49,0x4E,0x47,0x20,0x42,0x55,0x54,0x20
+,0x4E,0x4F,0x54,0x20,0x4C,0x49,0x4D,0x49,0x54,0x45,0x44,0x20,0x54,0x4F,0x20,0x54
+,0x48,0x45,0x20,0x57,0x41,0x52,0x52,0x41,0x4E,0x54,0x49,0x45,0x53,0x20,0x4F,0x46
+,0x20,0x4D,0x45,0x52,0x43,0x48,0x41,0x4E,0x54,0x41,0x42,0x49,0x4C,0x49,0x54,0x59
+,0x2C,0x0D,0x0A,0x2F,0x2F,0x46,0x49,0x54,0x4E,0x45,0x53,0x53,0x20,0x46,0x4F,0x52
+,0x20,0x41,0x20,0x50,0x41,0x52,0x54,0x49,0x43,0x55,0x4C,0x41,0x52,0x20,0x50,0x55
+,0x52,0x50,0x4F,0x53,0x45,0x20,0x41,0x4E,0x44,0x20,0x4E,0x4F,0x4E,0x49,0x4E,0x46
+,0x52,0x49,0x4E,0x47,0x45,0x4D,0x45,0x4E,0x54,0x2E,0x20,0x49,0x4E,0x20,0x4E,0x4F
+,0x20,0x45,0x56,0x45,0x4E,0x54,0x20,0x53,0x48,0x41,0x4C,0x4C,0x20,0x54,0x48,0x45
+,0x0D,0x0A,0x2F,0x2F,0x41,0x55,0x54,0x48,0x4F,0x52,0x53,0x20,0x4F,0x52,0x20,0x43
+,0x4F,0x50,0x59,0x52,0x49,0x47,0x48,0x54,0x20,0x48,0x4F,0x4C,0x44,0x45,0x52,0x53
+,0x20,0x42,0x45,0x20,0x4C,0x49,0x41,0x42,0x4C,0x45,0x20,0x46,0x4F,0x52,0x20,0x41
+,0x4E,0x59,0x20,0x43,0x4C,0x41,0x49,0x4D,0x2C,0x20,0x44,0x41,0x4D,0x41,0x47,0x45
+,0x53,0x20,0x4F,0x52,0x20,0x4F,0x54,0x48,0x45,0x52,0x0D,0x0A,0x2F,0x2F,0x4C,0x49
+,0x41,0x42,0x49,0x4C,0x49,0x54,0x59,0x2C,0x20,0x57,0x48,0x45,0x54,0x48,0x45,0x52
+,0x20,0x49,0x4E,0x20,0x41,0x4E,0x20,0x41,0x43,0x54,0x49,0x4F,0x4E,0x20,0x4F,0x46
+,0x20,0x43,0x4F,0x4E,0x54,0x52,0x41,0x43,0x54,0x2C,0x20,0x54,0x4F,0x52,0x54,0x20
+,0x4F,0x52,0x20,0x4F,0x54,0x48,0x45,0x52,0x57,0x49,0x53,0x45,0x2C,0x20,0x41,0x52
+,0x49,0x53,0x49,0x4E,0x47,0x20,0x46,0x52,0x4F,0x4D,0x2C,0x0D,0x0A,0x2F,0x2F,0x4F
+,0x55,0x54,0x20,0x4F,0x46,0x20,0x4F,0x52,0x20,0x49,0x4E,0x20,0x43,0x4F,0x4E,0x4E
+,0x45,0x43,0x54,0x49,0x4F,0x4E,0x20,0x57,0x49,0x54,0x48,0x20,0x54,0x48,0x45,0x20
+,0x53,0x4F,0x46,0x54,0x57,0x41,0x52,0x45,0x20,0x4F,0x52,0x20,0x54,0x48,0x45,0x20
+,0x55,0x53,0x45,0x20,0x4F,0x52,0x20,0x4F,0x54,0x48,0x45,0x52,0x20,0x44,0x45,0x41
+,0x4C,0x49,0x4E,0x47,0x53,0x20,0x49,0x4E,0x0D,0x0A,0x2F,0x2F,0x54,0x48,0x45,0x20
+,0x53,0x4F,0x46,0x54,0x57,0x41,0x52,0x45,0x2E,0x0D,0x0A,0x0D,0x0A,0x0D,0x0A,0x2F
+,0x2F,0x54,0x72,0x61,0x6E,0x73,0x70,0x6F,0x72,0x74,0x20,0x4D,0x65,0x63,0x68,0x61
+,0x6E,0x69,0x73,0x6D,0x73,0x20,0x20,0x20,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x20,0x70,0x6F,0x73,0x74,0x28,0x75,0x72,0x6C,0x29,0x20,0x7B,0x0D
+,0x0A,0x20,0x20,0x20,0x20,0x68,0x74,0x74,0x70,0x20,0x3D,0x20,0x28,0x77,0x69,0x6E
+,0x64,0x6F,0x77,0x2E,0x58,0x4D,0x4C,0x48,0x74,0x74,0x70,0x52,0x65,0x71,0x75,0x65
+,0x73,0x74,0x29,0x20,0x3F,0x20,0x6E,0x65,0x77,0x20,0x58,0x4D,0x4C,0x48,0x74,0x74
+,0x70,0x52,0x65,0x71,0x75,0x65,0x73,0x74,0x28,0x29,0x20,0x3A,0x20,0x6E,0x65,0x77
+,0x20,0x41,0x63,0x74,0x69,0x76,0x65,0x58,0x4F,0x62,0x6A,0x65,0x63,0x74,0x28,0x22
+,0x4D,0x69,0x63,0x72,0x6F,0x73,0x6F,0x66,0x74,0x2E,0x58,0x4D,0x4C,0x48,0x54,0x54
+,0x50,0x22,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x69,0x66,0x28,0x21,0x68,0x74
+,0x74,0x70,0x29,0x20,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x66,0x61,0x6C,0x73,0x65
+,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x68,0x74,0x74,0x70,0x2E,0x6F,0x70,0x65,0x6E
+,0x28,0x22,0x47,0x45,0x54,0x22,0x2C,0x20,0x75,0x72,0x6C,0x2C,0x20,0x66,0x61,0x6C
+,0x73,0x65,0x29,0x3B,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x0D,0x0A,0x20,0x20,0x20,0x20,0x68,0x74,0x74,0x70,0x2E,0x73,0x65,0x6E,0x64
+,0x28,0x6E,0x75,0x6C,0x6C,0x29,0x3B,0x20,0x20,0x20,0x0D,0x0A,0x20,0x20,0x20,0x20
+,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x68,0x74,0x74,0x70,0x2E,0x72,0x65,0x73,0x70
+,0x6F,0x6E,0x73,0x65,0x54,0x65,0x78,0x74,0x3B,0x0D,0x0A,0x09,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x6D,0x62
+,0x65,0x64,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x2F,0x2F,0x4E,0x6F,0x20,0x61,0x63,0x74
+,0x69,0x6F,0x6E,0x20,0x6E,0x65,0x65,0x64,0x73,0x20,0x74,0x6F,0x20,0x62,0x65,0x20
+,0x74,0x61,0x6B,0x65,0x6E,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x6D,0x62,0x65,0x64
+,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x70,0x63,0x20,0x3D
+,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x6F,0x62,0x6A,0x65,0x63,0x74
+,0x2C,0x20,0x6D,0x65,0x74,0x68,0x6F,0x64,0x2C,0x20,0x61,0x72,0x67,0x75,0x6D,0x65
+,0x6E,0x74,0x73,0x29,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x2F,0x2F,0x54,0x68,0x69
+,0x73,0x20,0x73,0x68,0x6F,0x75,0x6C,0x64,0x20,0x62,0x65,0x20,0x6F,0x76,0x65,0x72
+,0x72,0x69,0x64,0x64,0x65,0x6E,0x20,0x62,0x79,0x20,0x74,0x68,0x65,0x20,0x61,0x20
+,0x74,0x72,0x61,0x6E,0x73,0x70,0x6F,0x72,0x74,0x20,0x6D,0x65,0x63,0x68,0x61,0x6E
+,0x69,0x73,0x6D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x48,0x54,0x54,0x50,0x52,0x50
+,0x43,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x20,0x3D,0x20,0x6E,0x65
+,0x77,0x20,0x6D,0x62,0x65,0x64,0x28,0x29,0x3B,0x0D,0x0A,0x48,0x54,0x54,0x50,0x52
+,0x50,0x43,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x63,0x6F,0x6E
+,0x73,0x74,0x72,0x75,0x63,0x74,0x6F,0x72,0x20,0x3D,0x20,0x48,0x54,0x54,0x50,0x52
+,0x50,0x43,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x48,0x54,0x54
+,0x50,0x52,0x50,0x43,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x2F,0x2F,0x75,0x6E,0x6C,0x69
+,0x6B,0x65,0x20,0x6F,0x74,0x68,0x65,0x72,0x20,0x6C,0x61,0x6E,0x67,0x75,0x61,0x67
+,0x65,0x73,0x20,0x74,0x68,0x69,0x73,0x20,0x64,0x6F,0x65,0x73,0x6E,0x27,0x74,0x20
+,0x6E,0x65,0x65,0x64,0x20,0x74,0x6F,0x20,0x62,0x65,0x20,0x70,0x61,0x73,0x73,0x65
+,0x64,0x20,0x61,0x6E,0x20,0x61,0x64,0x64,0x72,0x65,0x73,0x73,0x20,0x61,0x73,0x20
+,0x69,0x74,0x20,0x77,0x69,0x6C,0x6C,0x20,0x6F,0x6E,0x6C,0x79,0x20,0x62,0x65,0x20
+,0x61,0x6C,0x6C,0x6F,0x77,0x65,0x64,0x20,0x74,0x6F,0x20,0x63,0x6F,0x6D,0x6D,0x75
+,0x6E,0x69,0x63,0x61,0x74,0x65,0x20,0x77,0x69,0x74,0x68,0x20,0x69,0x74,0x73,0x65
+,0x6C,0x66,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x0D,0x0A,0x48,0x54,0x54,0x50,0x52
+,0x50,0x43,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x70,0x63
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x6F,0x62,0x6A,0x65,0x63
+,0x74,0x2C,0x20,0x6D,0x65,0x74,0x68,0x6F,0x64,0x2C,0x20,0x61,0x72,0x67,0x75,0x6D
+,0x65,0x6E,0x74,0x73,0x29,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x72,0x65,0x74
+,0x75,0x72,0x6E,0x20,0x70,0x6F,0x73,0x74,0x28,0x22,0x2F,0x72,0x70,0x63,0x2F,0x22
+,0x20,0x2B,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x20,0x2B,0x20,0x22,0x2F,0x22,0x20
+,0x2B,0x20,0x6D,0x65,0x74,0x68,0x6F,0x64,0x20,0x2B,0x20,0x22,0x2C,0x22,0x20,0x2B
+,0x20,0x61,0x72,0x67,0x75,0x6D,0x65,0x6E,0x74,0x73,0x2E,0x6A,0x6F,0x69,0x6E,0x28
+,0x22,0x2C,0x22,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x20
+,0x50,0x69,0x6E,0x20,0x4E,0x61,0x6D,0x65,0x73,0x20,0x74,0x6F,0x20,0x41,0x6C,0x6C
+,0x6F,0x77,0x20,0x70,0x69,0x6E,0x73,0x20,0x74,0x6F,0x20,0x62,0x65,0x20,0x72,0x65
+,0x66,0x66,0x65,0x72,0x65,0x64,0x20,0x74,0x6F,0x20,0x61,0x73,0x20,0x61,0x20,0x74
+,0x79,0x70,0x65,0x20,0x72,0x61,0x74,0x68,0x65,0x72,0x20,0x74,0x68,0x61,0x6E,0x20
+,0x61,0x20,0x73,0x74,0x72,0x69,0x6E,0x67,0x20,0x6F,0x72,0x20,0x6E,0x75,0x6D,0x62
+,0x65,0x72,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x70
+,0x69,0x6E,0x28,0x6E,0x61,0x6D,0x65,0x29,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73
+,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6E,0x61,0x6D,0x65,0x3B,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x4C,0x45,0x44,0x31,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20
+,0x70,0x69,0x6E,0x28,0x22,0x4C,0x45,0x44,0x31,0x22,0x29,0x3B,0x0D,0x0A,0x4C,0x45
+,0x44,0x32,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x70,0x69,0x6E,0x28,0x22,0x4C,0x45
+,0x44,0x32,0x22,0x29,0x3B,0x0D,0x0A,0x4C,0x45,0x44,0x33,0x20,0x3D,0x20,0x6E,0x65
+,0x77,0x20,0x70,0x69,0x6E,0x28,0x22,0x4C,0x45,0x44,0x33,0x22,0x29,0x3B,0x0D,0x0A
+,0x4C,0x45,0x44,0x34,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x70,0x69,0x6E,0x28,0x22
+,0x4C,0x45,0x44,0x34,0x22,0x29,0x3B,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x20,0x69,0x6E
+,0x74,0x65,0x72,0x66,0x61,0x63,0x65,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x73,0x20,0x20,0x20,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D,0x2D
+,0x2D,0x2D,0x2D,0x2D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74
+,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x44,0x69
+,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62
+,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x69,0x66
+,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70,0x69,0x6E,0x20,0x21,0x3D,0x20
+,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09,0x0D,0x0A,0x09,0x09,0x2F
+,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E,0x65,0x77,0x20,0x6F,0x62
+,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62
+,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D
+,0x0A,0x09,0x2F,0x2F,0x76,0x61,0x72,0x20,0x61,0x72,0x79,0x20,0x3D,0x20,0x6E,0x65
+,0x77,0x20,0x41,0x72,0x72,0x61,0x79,0x28,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x29,0x3B,0x0D
+,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65
+,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x22,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x22,0x2C,0x20,0x22
+,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D
+,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x5D,0x29,0x3B,0x20
+,0x0D,0x0A,0x09,0x2F,0x2F,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20
+,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28
+,0x22,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x22,0x2C,0x20,0x22,0x6E
+,0x65,0x77,0x22,0x2C,0x20,0x61,0x72,0x79,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65
+,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F
+,0x20,0x61,0x6E,0x20,0x65,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A
+,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65
+,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A
+,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70
+,0x69,0x6E,0x3B,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x44,0x69
+,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79
+,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65,0x22
+,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A
+,0x0D,0x0A,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F
+,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74
+,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74,0x28,0x74,0x68,0x69
+,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73
+,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B
+,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x44,0x69,0x67,0x69,0x74,0x61,0x6C
+,0x49,0x6E,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20
+,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x49,0x6E,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D
+,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x69
+,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70,0x69,0x6E,0x20,0x21,0x3D
+,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09,0x0D,0x0A,0x09,0x09
+,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E,0x65,0x77,0x20,0x6F
+,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B
+,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x22,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x49,0x6E,0x22,0x2C,0x20
+,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x5D,0x29,0x3B
+,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x09,0x09,0x2F,0x2F
+,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65,0x78,0x69,0x73,0x74,0x69
+,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D
+,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x44,0x69,0x67,0x69,0x74,0x61,0x6C,0x49,0x6E,0x2E
+,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D
+,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09
+,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74,0x28
+,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74
+,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22
+,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A
+,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x41,0x6E
+,0x61,0x6C,0x6F,0x67,0x4F,0x75,0x74,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63
+,0x74,0x69,0x6F,0x6E,0x20,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F,0x75,0x74,0x28,0x74
+,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x69,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70
+,0x69,0x6E,0x20,0x21,0x3D,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B
+,0x09,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20
+,0x6E,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F
+,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F
+,0x75,0x74,0x22,0x2C,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69
+,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x5D,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D
+,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65
+,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A
+,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74
+,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A
+,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F
+,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69
+,0x74,0x65,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61
+,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C
+,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C
+,0x6F,0x67,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E
+,0x77,0x72,0x69,0x74,0x65,0x5F,0x75,0x31,0x36,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63
+,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09
+,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74
+,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65
+,0x5F,0x75,0x31,0x36,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x4F,0x75,0x74
+,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A
+,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x46,0x6C,0x6F
+,0x61,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70
+,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65
+,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D
+,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x20,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49,0x6E,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49,0x6E,0x28
+,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29
+,0x20,0x7B,0x0D,0x0A,0x09,0x69,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D
+,0x70,0x69,0x6E,0x20,0x21,0x3D,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29
+,0x7B,0x09,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61
+,0x20,0x6E,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73
+,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F
+,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22,0x41,0x6E,0x61,0x6C,0x6F,0x67
+,0x49,0x6E,0x22,0x2C,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69
+,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61
+,0x6D,0x65,0x5D,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D
+,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65
+,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A
+,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74
+,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A
+,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49
+,0x6E,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64
+,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x46,0x6C
+,0x6F,0x61,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72
+,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D
+,0x0D,0x0A,0x0D,0x0A,0x41,0x6E,0x61,0x6C,0x6F,0x67,0x49,0x6E,0x2E,0x70,0x72,0x6F
+,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x5F,0x75,0x31,0x36,0x20
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A
+,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28
+,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64
+,0x5F,0x75,0x31,0x36,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x20,0x50,0x77,0x6D,0x4F,0x75,0x74,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x50,0x77,0x6D,0x4F,0x75,0x74,0x28,0x74,0x68
+,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6D,0x70,0x69,0x6E,0x29,0x20,0x7B
+,0x0D,0x0A,0x09,0x69,0x66,0x28,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x6D,0x70,0x69
+,0x6E,0x20,0x21,0x3D,0x20,0x22,0x73,0x74,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09
+,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E
+,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69
+,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D
+,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73
+,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62
+,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22,0x50,0x77,0x6D,0x4F,0x75,0x74,0x22,0x2C
+,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20,0x5B,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E
+,0x61,0x6D,0x65,0x2C,0x6D,0x70,0x69,0x6E,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x5D,0x29
+,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x09,0x09,0x2F
+,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20,0x65,0x78,0x69,0x73,0x74
+,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F
+,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61
+,0x6D,0x65,0x20,0x3D,0x20,0x6D,0x70,0x69,0x6E,0x3B,0x0D,0x0A,0x09,0x7D,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74
+,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77,0x72,0x69
+,0x74,0x65,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74
+,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x72
+,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65,0x46,0x6C,0x6F,0x61,0x74
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28
+,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64
+,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70
+,0x65,0x2E,0x70,0x65,0x72,0x69,0x6F,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x65,0x72,0x69,0x6F,0x64
+,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D
+,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74
+,0x79,0x70,0x65,0x2E,0x70,0x65,0x72,0x69,0x6F,0x64,0x5F,0x6D,0x73,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70
+,0x65,0x72,0x69,0x6F,0x64,0x5F,0x6D,0x73,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75
+,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75
+,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x65,0x72,0x69
+,0x6F,0x64,0x5F,0x75,0x73,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73
+,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E
+,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x65,0x72,0x69,0x6F,0x64,0x5F,0x75,0x73
+,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D
+,0x0A,0x0D,0x0A,0x50,0x77,0x6D,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74
+,0x79,0x70,0x65,0x2E,0x70,0x75,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x20,0x3D
+,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29
+,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E
+,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22
+,0x70,0x75,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x22,0x2C,0x20,0x5B,0x76,0x61
+,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D
+,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x75
+,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x6D,0x73,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x75,0x6C
+,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x6D,0x73,0x22,0x2C,0x20,0x5B,0x76,0x61
+,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x50,0x77,0x6D
+,0x4F,0x75,0x74,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x75
+,0x6C,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x75,0x73,0x20,0x3D,0x20,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D
+,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63
+,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x70,0x75,0x6C
+,0x73,0x65,0x77,0x69,0x64,0x74,0x68,0x5F,0x75,0x73,0x22,0x2C,0x20,0x5B,0x76,0x61
+,0x6C,0x75,0x65,0x5D,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F,0x2F,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x73,0x65,0x72,0x69,0x61
+,0x6C,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x53
+,0x65,0x72,0x69,0x61,0x6C,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C
+,0x20,0x74,0x78,0x2C,0x20,0x72,0x78,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x69,0x66,0x28
+,0x74,0x79,0x70,0x65,0x6F,0x66,0x20,0x74,0x78,0x20,0x21,0x3D,0x20,0x22,0x73,0x74
+,0x72,0x69,0x6E,0x67,0x22,0x29,0x7B,0x09,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x63,0x72
+,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x6E,0x65,0x77,0x20,0x6F,0x62,0x6A,0x65,0x63
+,0x74,0x0D,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20
+,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x20,0x20
+,0x20,0x20,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20
+,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x22
+,0x53,0x65,0x72,0x69,0x61,0x6C,0x22,0x2C,0x20,0x22,0x6E,0x65,0x77,0x22,0x2C,0x20
+,0x5B,0x74,0x78,0x2E,0x5F,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x72,0x78,0x2E,0x5F,0x6E
+,0x61,0x6D,0x65,0x5D,0x29,0x3B,0x20,0x0D,0x0A,0x09,0x7D,0x65,0x6C,0x73,0x65,0x7B
+,0x0D,0x0A,0x09,0x09,0x2F,0x2F,0x54,0x69,0x65,0x20,0x74,0x6F,0x20,0x61,0x6E,0x20
+,0x65,0x78,0x69,0x73,0x74,0x69,0x6E,0x67,0x20,0x6F,0x62,0x6A,0x65,0x63,0x74,0x0D
+,0x0A,0x09,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x20,0x3D,0x20
+,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A,0x09,0x09,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x20,0x3D,0x20,0x74,0x78,0x3B,0x0D,0x0A,0x09
+,0x7D,0x0D,0x0A,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C
+,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x70,0x75,0x74,0x63,0x20
+,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65
+,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64
+,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20
+,0x22,0x70,0x75,0x74,0x63,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29
+,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C,0x2E,0x70
+,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x67,0x65,0x74,0x63,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65
+,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x67
+,0x65,0x74,0x63,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D
+,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C,0x2E,0x70,0x72,0x6F,0x74,0x6F
+,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61,0x64,0x61,0x62,0x6C,0x65,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61,0x72,0x73,0x65
+,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72
+,0x65,0x61,0x64,0x61,0x62,0x6C,0x65,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29
+,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x53,0x65,0x72,0x69,0x61,0x6C,0x2E,0x70
+,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x61,0x62
+,0x6C,0x65,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61
+,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20
+,0x70,0x61,0x72,0x73,0x65,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x2C,0x20,0x22,0x77,0x72,0x69,0x74,0x65,0x61,0x62,0x6C,0x65,0x22,0x2C,0x20
+,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x0D,0x0A
+,0x2F,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x52,0x50
+,0x43,0x56,0x61,0x72,0x69,0x61,0x62,0x6C,0x65,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75
+,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62
+,0x6C,0x65,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6E,0x61
+,0x6D,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62
+,0x65,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D
+,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61
+,0x6D,0x65,0x20,0x3D,0x20,0x6E,0x61,0x6D,0x65,0x3B,0x20,0x0D,0x0A,0x7D,0x0D,0x0A
+,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62,0x6C,0x65,0x2E,0x70,0x72
+,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x77,0x72,0x69,0x74,0x65,0x20,0x3D,0x20
+,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72
+,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x77
+,0x72,0x69,0x74,0x65,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65,0x5D,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62
+,0x6C,0x65,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61
+,0x64,0x5F,0x69,0x6E,0x74,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x70,0x61
+,0x72,0x73,0x65,0x49,0x6E,0x74,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65
+,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C
+,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B
+,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61,0x72,0x69,0x61,0x62
+,0x6C,0x65,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x65,0x61
+,0x64,0x5F,0x66,0x6C,0x6F,0x61,0x74,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69
+,0x6F,0x6E,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20
+,0x70,0x61,0x72,0x73,0x65,0x46,0x6C,0x6F,0x61,0x74,0x28,0x74,0x68,0x69,0x73,0x2E
+,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E
+,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C,0x20,0x5B,0x22,0x22
+,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x52,0x50,0x43,0x56,0x61
+,0x72,0x69,0x61,0x62,0x6C,0x65,0x2E,0x70,0x72,0x6F,0x74,0x6F,0x74,0x79,0x70,0x65
+,0x2E,0x72,0x65,0x61,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x28,0x74
+,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68
+,0x69,0x73,0x2E,0x6E,0x61,0x6D,0x65,0x2C,0x20,0x22,0x72,0x65,0x61,0x64,0x22,0x2C
+,0x20,0x5B,0x22,0x22,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x2F
+,0x2F,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x20,0x52,0x50,0x43
+,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A
+,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x20,0x52,0x50,0x43,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F
+,0x6E,0x28,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x2C,0x20,0x6E,0x61,0x6D
+,0x65,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D,0x62,0x65
+,0x64,0x20,0x3D,0x20,0x74,0x68,0x69,0x73,0x5F,0x6D,0x62,0x65,0x64,0x3B,0x0D,0x0A
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x20,0x3D,0x20,0x6E,0x61,0x6D,0x65,0x3B,0x20,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x52,0x50,0x43,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x2E,0x70,0x72,0x6F
+,0x74,0x6F,0x74,0x79,0x70,0x65,0x2E,0x72,0x75,0x6E,0x20,0x3D,0x20,0x66,0x75,0x6E
+,0x63,0x74,0x69,0x6F,0x6E,0x28,0x76,0x61,0x6C,0x75,0x65,0x29,0x20,0x7B,0x0D,0x0A
+,0x09,0x72,0x65,0x74,0x75,0x72,0x6E,0x20,0x28,0x74,0x68,0x69,0x73,0x2E,0x5F,0x6D
+,0x62,0x65,0x64,0x2E,0x72,0x70,0x63,0x28,0x74,0x68,0x69,0x73,0x2E,0x6E,0x61,0x6D
+,0x65,0x2C,0x20,0x22,0x72,0x75,0x6E,0x22,0x2C,0x20,0x5B,0x76,0x61,0x6C,0x75,0x65
+,0x5D,0x29,0x29,0x3B,0x0D,0x0A,0x7D
+};
+
+static const char led_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x20,0x75,0x74
+,0x66,0x2D,0x38,0x22,0x3E,0x20,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x4C
+,0x45,0x44,0x20,0x54,0x6F,0x67,0x67,0x6C,0x65,0x3C,0x2F,0x74,0x69,0x74,0x6C,0x65
+,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74,0x79,0x70,0x65,0x3D
+,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74
+,0x22,0x20,0x73,0x72,0x63,0x3D,0x22,0x6D,0x62,0x65,0x64,0x52,0x50,0x43,0x2E,0x6A
+,0x73,0x22,0x20,0x6C,0x61,0x6E,0x67,0x75,0x61,0x67,0x65,0x3D,0x22,0x6A,0x61,0x76
+,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74
+,0x3D,0x22,0x75,0x74,0x66,0x2D,0x38,0x22,0x3E,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70
+,0x74,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74,0x79,0x70,0x65
+,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70
+,0x74,0x22,0x3E,0x6D,0x62,0x65,0x64,0x3D,0x6E,0x65,0x77,0x20,0x48,0x54,0x54,0x50
+,0x52,0x50,0x43,0x28,0x29,0x3B,0x6C,0x65,0x64,0x31,0x3D,0x6E,0x65,0x77,0x20,0x44
+,0x69,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x6D,0x62,0x65,0x64,0x2C,0x4C
+,0x45,0x44,0x31,0x29,0x3B,0x6C,0x65,0x64,0x32,0x3D,0x6E,0x65,0x77,0x20,0x44,0x69
+,0x67,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x6D,0x62,0x65,0x64,0x2C,0x4C,0x45
+,0x44,0x32,0x29,0x3B,0x6C,0x65,0x64,0x33,0x3D,0x6E,0x65,0x77,0x20,0x44,0x69,0x67
+,0x69,0x74,0x61,0x6C,0x4F,0x75,0x74,0x28,0x6D,0x62,0x65,0x64,0x2C,0x4C,0x45,0x44
+,0x33,0x29,0x3B,0x0D,0x0A,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D,0x0A
+,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65
+,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x3E,0x0D
+,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x6C,0x65,0x64,0x31,0x5F,0x74
+,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x76,0x61,0x72,0x20,0x72,0x64,0x31,0x20,0x3D,0x20,0x6C,0x65,0x64
+,0x31,0x2E,0x72,0x65,0x61,0x64,0x28,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x69,0x66,0x20,0x28,0x72,0x64,0x31,0x20,0x3D,0x3D,0x20,0x31,0x29
+,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x6C,0x65,0x64,0x31,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x30
+,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x2E,0x76,0x61,0x6C
+,0x75,0x65,0x20,0x3D,0x20,0x27,0x4C,0x45,0x44,0x31,0x20,0x4F,0x66,0x66,0x27,0x3B
+,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C
+,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C
+,0x45,0x44,0x31,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B
+,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27,0x23
+,0x63,0x30,0x63,0x30,0x63,0x30,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65
+,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49
+,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x22,0x29,0x2E,0x73,0x74
+,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27,0x23,0x30,0x30
+,0x30,0x30,0x30,0x30,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x6C,0x65,0x64,0x31,0x2E,0x77,0x72,0x69
+,0x74,0x65,0x28,0x31,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31
+,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x27,0x4C,0x45,0x44,0x31,0x20,0x4F
+,0x6E,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65
+,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74
+,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62
+,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x20,0x3D
+,0x20,0x27,0x23,0x66,0x66,0x30,0x30,0x30,0x30,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63
+,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74
+,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x31,0x22,0x29
+,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27
+,0x23,0x66,0x66,0x66,0x66,0x66,0x66,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F
+,0x6E,0x20,0x6C,0x65,0x64,0x32,0x5F,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x20
+,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x76,0x61,0x72,0x20,0x72
+,0x64,0x32,0x20,0x3D,0x20,0x6C,0x65,0x64,0x32,0x2E,0x72,0x65,0x61,0x64,0x28,0x29
+,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x69,0x66,0x20,0x28,0x72
+,0x64,0x32,0x20,0x3D,0x3D,0x20,0x31,0x29,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x6C,0x65,0x64,0x32
+,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x30,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x62,0x74,0x6E,0x5F
+,0x4C,0x45,0x44,0x32,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x27,0x4C,0x45
+,0x44,0x32,0x20,0x4F,0x66,0x66,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65
+,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49
+,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x22,0x29,0x2E,0x73,0x74
+,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F
+,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x27,0x3B
+,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C
+,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C
+,0x45,0x44,0x32,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F
+,0x72,0x20,0x3D,0x20,0x27,0x23,0x30,0x30,0x30,0x30,0x30,0x30,0x27,0x3B,0x0D,0x0A
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D,0x0A
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x6C,0x65,0x64,0x32,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x31,0x29,0x3B,0x0D,0x0A
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D
+,0x20,0x27,0x4C,0x45,0x44,0x32,0x20,0x4F,0x6E,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63
+,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74
+,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x22,0x29
+,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E
+,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27,0x23,0x30,0x30,0x38,0x30,0x30
+,0x30,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65
+,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74
+,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63
+,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27,0x23,0x66,0x66,0x66,0x66,0x66,0x66,0x27
+,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x7D,0x0D,0x0A,0x7D,0x0D
+,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x6C,0x65,0x64,0x33,0x5F,0x74
+,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x76,0x61,0x72,0x20,0x72,0x64,0x33,0x20,0x3D,0x20,0x6C,0x65,0x64
+,0x33,0x2E,0x72,0x65,0x61,0x64,0x28,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x69,0x66,0x20,0x28,0x72,0x64,0x33,0x20,0x3D,0x3D,0x20,0x31,0x29
+,0x20,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x6C,0x65,0x64,0x33,0x2E,0x77,0x72,0x69,0x74,0x65,0x28,0x30
+,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x2E,0x76,0x61,0x6C
+,0x75,0x65,0x20,0x3D,0x20,0x27,0x4C,0x45,0x44,0x33,0x20,0x4F,0x66,0x66,0x27,0x3B
+,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C
+,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C
+,0x45,0x44,0x33,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62,0x61,0x63,0x6B
+,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27,0x23
+,0x63,0x30,0x63,0x30,0x63,0x30,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65
+,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49
+,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x22,0x29,0x2E,0x73,0x74
+,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27,0x23,0x30,0x30
+,0x30,0x30,0x30,0x30,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x7D,0x65,0x6C,0x73,0x65,0x7B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x6C,0x65,0x64,0x33,0x2E,0x77,0x72,0x69
+,0x74,0x65,0x28,0x31,0x29,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33
+,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x27,0x4C,0x45,0x44,0x33,0x20,0x4F
+,0x6E,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65
+,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74
+,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x22,0x29,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x62
+,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x43,0x6F,0x6C,0x6F,0x72,0x20,0x3D
+,0x20,0x27,0x23,0x30,0x30,0x30,0x30,0x63,0x63,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x64,0x6F,0x63
+,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74
+,0x42,0x79,0x49,0x64,0x28,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x22,0x29
+,0x2E,0x73,0x74,0x79,0x6C,0x65,0x2E,0x63,0x6F,0x6C,0x6F,0x72,0x20,0x3D,0x20,0x27
+,0x23,0x66,0x66,0x66,0x66,0x66,0x66,0x27,0x3B,0x0D,0x0A,0x20,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70
+,0x74,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F
+,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69
+,0x7A,0x65,0x3D,0x22,0x38,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79
+,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x38
+,0x30,0x22,0x3E,0x3C,0x62,0x3E,0x4C,0x45,0x44,0x20,0x54,0x6F,0x67,0x67,0x6C,0x65
+,0x20,0x53,0x77,0x69,0x74,0x63,0x68,0x3C,0x2F,0x62,0x3E,0x3C,0x2F,0x73,0x70,0x61
+,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62,0x72,0x3E,0x3C,0x62,0x72
+,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22
+,0x62,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20,0x49,0x44,0x3D,0x22,0x62,0x74,0x6E,0x5F
+,0x4C,0x45,0x44,0x31,0x22,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E
+,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B
+,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x3B,0x63,0x6F
+,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x30,0x30,0x3B,0x62,0x61,0x63,0x6B
+,0x67,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x63,0x30
+,0x63,0x30,0x63,0x30,0x3B,0x57,0x49,0x44,0x54,0x48,0x3A,0x20,0x37,0x30,0x70,0x78
+,0x3B,0x20,0x48,0x45,0x49,0x47,0x48,0x54,0x3A,0x20,0x34,0x30,0x70,0x78,0x22,0x20
+,0x6F,0x6E,0x43,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x6C,0x65,0x64,0x31,0x5F,0x74,0x6F
+,0x67,0x67,0x6C,0x65,0x28,0x29,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20
+,0x22,0x4C,0x45,0x44,0x31,0x20,0x4F,0x66,0x66,0x22,0x3E,0x20,0x3C,0x62,0x72,0x3E
+,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74
+,0x79,0x70,0x65,0x3D,0x22,0x62,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20,0x49,0x44,0x3D
+,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x32,0x22,0x20,0x73,0x74,0x79,0x6C,0x65
+,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61
+,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39
+,0x70,0x74,0x3B,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x30,0x30
+,0x3B,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63,0x6F,0x6C,0x6F
+,0x72,0x3A,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x3B,0x57,0x49,0x44,0x54,0x48,0x3A
+,0x20,0x37,0x30,0x70,0x78,0x3B,0x20,0x48,0x45,0x49,0x47,0x48,0x54,0x3A,0x20,0x34
+,0x30,0x70,0x78,0x22,0x20,0x6F,0x6E,0x43,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x6C,0x65
+,0x64,0x32,0x5F,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29,0x22,0x20,0x76,0x61,0x6C
+,0x75,0x65,0x20,0x3D,0x20,0x22,0x4C,0x45,0x44,0x32,0x20,0x4F,0x66,0x66,0x22,0x3E
+,0x20,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E
+,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x62,0x75,0x74,0x74,0x6F,0x6E
+,0x22,0x20,0x49,0x44,0x3D,0x22,0x62,0x74,0x6E,0x5F,0x4C,0x45,0x44,0x33,0x22,0x20
+,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49
+,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53
+,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x3B,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30
+,0x30,0x30,0x30,0x30,0x30,0x3B,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64
+,0x2D,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x63,0x30,0x63,0x30,0x63,0x30,0x3B,0x57
+,0x49,0x44,0x54,0x48,0x3A,0x20,0x37,0x30,0x70,0x78,0x3B,0x20,0x48,0x45,0x49,0x47
+,0x48,0x54,0x3A,0x20,0x34,0x30,0x70,0x78,0x22,0x20,0x6F,0x6E,0x43,0x6C,0x69,0x63
+,0x6B,0x3D,0x22,0x6C,0x65,0x64,0x33,0x5F,0x74,0x6F,0x67,0x67,0x6C,0x65,0x28,0x29
+,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x22,0x4C,0x45,0x44,0x33,0x20
+,0x4F,0x66,0x66,0x22,0x3E,0x20,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x2F
+,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A
+};
+
+static const char i2c_set_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66
+,0x2D,0x38,0x22,0x3E,0x20,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x53,0x65
+,0x74,0x74,0x69,0x6E,0x67,0x20,0x62,0x79,0x20,0x49,0x32,0x43,0x3C,0x2F,0x74,0x69
+,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74,0x79
+,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63,0x72
+,0x69,0x70,0x74,0x22,0x20,0x73,0x72,0x63,0x3D,0x22,0x6D,0x62,0x65,0x64,0x52,0x50
+,0x43,0x2E,0x6A,0x73,0x22,0x20,0x6C,0x61,0x6E,0x67,0x75,0x61,0x67,0x65,0x3D,0x22
+,0x6A,0x61,0x76,0x61,0x73,0x63,0x72,0x69,0x70,0x74,0x22,0x20,0x63,0x68,0x61,0x72
+,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66,0x2D,0x38,0x22,0x3E,0x3C,0x2F,0x73,0x63
+,0x72,0x69,0x70,0x74,0x3E,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74,0x20,0x74
+,0x79,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x6A,0x61,0x76,0x61,0x73,0x63
+,0x72,0x69,0x70,0x74,0x22,0x3E,0x6D,0x62,0x65,0x64,0x3D,0x6E,0x65,0x77,0x20,0x48
+,0x54,0x54,0x50,0x52,0x50,0x43,0x28,0x29,0x3B,0x74,0x65,0x72,0x6D,0x3D,0x6E,0x65
+,0x77,0x20,0x52,0x50,0x43,0x46,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28,0x6D,0x62
+,0x65,0x64,0x2C,0x22,0x53,0x65,0x74,0x49,0x32,0x43,0x66,0x72,0x6F,0x6D,0x57,0x65
+,0x62,0x22,0x29,0x3B,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D,0x0A,0x3C
+,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A
+,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x38
+,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x43
+,0x4F,0x4C,0x4F,0x52,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x62
+,0x3E,0x44,0x69,0x72,0x65,0x63,0x74,0x20,0x69,0x6E,0x70,0x75,0x74,0x3C,0x2F,0x62
+,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65
+,0x3D,0x22,0x74,0x65,0x78,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x64,0x69,0x72,0x5F
+,0x69,0x6E,0x22,0x3E,0x3C,0x2F,0x69,0x6E,0x70,0x75,0x74,0x3E,0x3C,0x62,0x75,0x74
+,0x74,0x6F,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D
+,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F
+,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x22,0x20,0x6F,0x6E,0x63
+,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x73,0x6E,0x64,0x5F,0x64,0x69,0x72,0x5F,0x69,0x6E
+,0x28,0x29,0x22,0x3E,0x53,0x65,0x6E,0x64,0x3C,0x2F,0x62,0x75,0x74,0x74,0x6F,0x6E
+,0x3E,0x20,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x0D,0x0A
+,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x38
+,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x43
+,0x4F,0x4C,0x4F,0x52,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x62
+,0x3E,0x46,0x69,0x6C,0x65,0x20,0x72,0x65,0x66,0x65,0x72,0x65,0x6E,0x63,0x65,0x3C
+,0x2F,0x62,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74
+,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79
+,0x70,0x65,0x3D,0x22,0x66,0x69,0x6C,0x65,0x22,0x20,0x69,0x64,0x3D,0x22,0x66,0x69
+,0x6C,0x65,0x5F,0x75,0x70,0x6C,0x6F,0x61,0x64,0x22,0x20,0x73,0x74,0x79,0x6C,0x65
+,0x3D,0x22,0x44,0x49,0x53,0x50,0x4C,0x41,0x59,0x3A,0x6E,0x6F,0x6E,0x65,0x22,0x20
+,0x6F,0x6E,0x63,0x68,0x61,0x6E,0x67,0x65,0x3D,0x22,0x74,0x78,0x74,0x5F,0x66,0x69
+,0x6C,0x65,0x6E,0x61,0x6D,0x65,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x74
+,0x68,0x69,0x73,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3B,0x22,0x20,0x61,0x63,0x63,0x65
+,0x70,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x70,0x6C,0x61,0x69,0x6E,0x22,0x3E
+,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x74
+,0x65,0x78,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x74,0x78,0x74,0x5F,0x66,0x69,0x6C
+,0x65,0x6E,0x61,0x6D,0x65,0x22,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F
+,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61
+,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x22,0x20
+,0x73,0x69,0x7A,0x65,0x3D,0x22,0x32,0x35,0x22,0x20,0x44,0x49,0x53,0x41,0x42,0x4C
+,0x45,0x44,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65
+,0x3D,0x22,0x62,0x75,0x74,0x74,0x6F,0x6E,0x22,0x20,0x69,0x64,0x3D,0x22,0x66,0x69
+,0x6C,0x65,0x5F,0x73,0x65,0x6C,0x65,0x63,0x74,0x22,0x20,0x73,0x74,0x79,0x6C,0x65
+,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61
+,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39
+,0x70,0x74,0x22,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x66,0x69,0x6C
+,0x65,0x5F,0x75,0x70,0x6C,0x6F,0x61,0x64,0x2E,0x63,0x6C,0x69,0x63,0x6B,0x28,0x29
+,0x22,0x20,0x76,0x61,0x6C,0x75,0x65,0x3D,0x22,0x43,0x68,0x6F,0x6F,0x73,0x65,0x20
+,0x61,0x20,0x74,0x65,0x78,0x74,0x20,0x46,0x69,0x6C,0x65,0x22,0x3E,0x0D,0x0A,0x3C
+,0x62,0x75,0x74,0x74,0x6F,0x6E,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x73,0x75,0x62
+,0x6D,0x69,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x73,0x6E,0x64,0x62,0x6F,0x78,0x22
+,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D
+,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D
+,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x22,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63
+,0x6B,0x3D,0x22,0x73,0x6E,0x64,0x5F,0x66,0x69,0x6C,0x65,0x5F,0x72,0x65,0x66,0x28
+,0x29,0x22,0x3E,0x53,0x65,0x6E,0x64,0x3C,0x2F,0x62,0x75,0x74,0x74,0x6F,0x6E,0x3E
+,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x3C,0x70,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x46,0x4F
+,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61
+,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x31,0x38,0x70,0x74,0x22
+,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x43,0x4F
+,0x4C,0x4F,0x52,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x0D,0x0A,0x3C
+,0x62,0x3E,0x4C,0x4F,0x47,0x3A,0x3C,0x2F,0x62,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E
+,0x3E,0x0D,0x0A,0x3C,0x69,0x6E,0x70,0x75,0x74,0x20,0x74,0x79,0x70,0x65,0x3D,0x22
+,0x73,0x75,0x62,0x6D,0x69,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x74,0x65,0x78,0x74
+,0x61,0x72,0x65,0x61,0x5F,0x63,0x6C,0x65,0x61,0x72,0x22,0x20,0x73,0x74,0x79,0x6C
+,0x65,0x3D,0x22,0x44,0x49,0x53,0x50,0x4C,0x41,0x59,0x3A,0x62,0x6C,0x6F,0x63,0x6B
+,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68
+,0x6F,0x6D,0x61,0x3B,0x46,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70
+,0x74,0x3B,0x57,0x49,0x44,0x54,0x48,0x3A,0x37,0x30,0x70,0x78,0x3B,0x48,0x45,0x49
+,0x47,0x48,0x54,0x3A,0x32,0x30,0x70,0x78,0x3B,0x50,0x4F,0x53,0x49,0x54,0x49,0x4F
+,0x4E,0x3A,0x61,0x62,0x73,0x6F,0x6C,0x75,0x74,0x65,0x3B,0x4C,0x45,0x46,0x54,0x3A
+,0x38,0x70,0x78,0x22,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x43,0x6C
+,0x72,0x5F,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x22,0x20,0x76,0x61
+,0x6C,0x75,0x65,0x3D,0x22,0x43,0x6C,0x65,0x61,0x72,0x22,0x3E,0x0D,0x0A,0x3C,0x62
+,0x75,0x74,0x74,0x6F,0x6E,0x20,0x74,0x79,0x70,0x65,0x3D,0x22,0x73,0x75,0x62,0x6D
+,0x69,0x74,0x22,0x20,0x69,0x64,0x3D,0x22,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61
+,0x5F,0x73,0x61,0x76,0x65,0x22,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x44,0x49
+,0x53,0x50,0x4C,0x41,0x59,0x3A,0x62,0x6C,0x6F,0x63,0x6B,0x3B,0x46,0x4F,0x4E,0x54
+,0x2D,0x46,0x41,0x4D,0x49,0x4C,0x59,0x3A,0x54,0x61,0x68,0x6F,0x6D,0x61,0x3B,0x46
+,0x4F,0x4E,0x54,0x2D,0x53,0x49,0x5A,0x45,0x3A,0x39,0x70,0x74,0x3B,0x57,0x49,0x44
+,0x54,0x48,0x3A,0x37,0x30,0x70,0x78,0x3B,0x48,0x45,0x49,0x47,0x48,0x54,0x3A,0x32
+,0x30,0x70,0x78,0x3B,0x50,0x4F,0x53,0x49,0x54,0x49,0x4F,0x4E,0x3A,0x61,0x62,0x73
+,0x6F,0x6C,0x75,0x74,0x65,0x3B,0x4C,0x45,0x46,0x54,0x3A,0x38,0x32,0x70,0x78,0x22
+,0x20,0x6F,0x6E,0x63,0x6C,0x69,0x63,0x6B,0x3D,0x22,0x53,0x61,0x76,0x65,0x5F,0x74
+,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x22,0x3E,0x53,0x61,0x76,0x65,0x3C
+,0x2F,0x62,0x75,0x74,0x74,0x6F,0x6E,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x72,0x6D,0x20
+,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x22,0x3E
+,0x0D,0x0A,0x3C,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x20,0x69,0x64,0x3D,0x22
+,0x72,0x65,0x73,0x75,0x6C,0x74,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x74,0x65
+,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x22,0x20,0x63,0x6F,0x6C,0x73,0x3D,0x22,0x35
+,0x30,0x22,0x20,0x72,0x6F,0x77,0x73,0x3D,0x22,0x32,0x30,0x22,0x20,0x70,0x6C,0x61
+,0x63,0x65,0x68,0x6F,0x6C,0x64,0x65,0x72,0x3D,0x22,0x22,0x20,0x76,0x61,0x6C,0x75
+,0x65,0x3D,0x22,0x22,0x3E,0x3C,0x2F,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x3E
+,0x0D,0x0A,0x3C,0x2F,0x66,0x6F,0x72,0x6D,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D
+,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x73,0x63,0x72,0x69,0x70,0x74
+,0x3E,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x73,0x6E,0x64,0x5F
+,0x64,0x69,0x72,0x5F,0x69,0x6E,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x76,0x61,0x72,0x20
+,0x72,0x63,0x76,0x5F,0x74,0x65,0x78,0x74,0x3B,0x0D,0x0A,0x09,0x69,0x66,0x20,0x28
+,0x28,0x64,0x69,0x72,0x5F,0x69,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x21,0x3D
+,0x20,0x6E,0x75,0x6C,0x6C,0x29,0x20,0x26,0x26,0x20,0x28,0x64,0x69,0x72,0x5F,0x69
+,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x21,0x3D,0x20,0x22,0x22,0x29,0x29,0x20
+,0x7B,0x0D,0x0A,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75
+,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61
+,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B,0x53,0x45,0x4E,0x44
+,0x5D,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72
+,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x64,0x69,0x72,0x5F
+,0x69,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x3B,0x0D,0x0A,0x09,0x09,0x64,0x6F,0x63
+,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74
+,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B
+,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x72,0x63,0x76
+,0x5F,0x74,0x65,0x78,0x74,0x20,0x3D,0x20,0x74,0x65,0x72,0x6D,0x2E,0x72,0x75,0x6E
+,0x28,0x64,0x69,0x72,0x5F,0x69,0x6E,0x2E,0x76,0x61,0x6C,0x75,0x65,0x29,0x3B,0x0D
+,0x0A,0x09,0x09,0x69,0x66,0x20,0x28,0x72,0x63,0x76,0x5F,0x74,0x65,0x78,0x74,0x20
+,0x21,0x3D,0x20,0x22,0x72,0x75,0x6E,0x22,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x09
+,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72
+,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75
+,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B,0x52,0x45,0x43,0x56,0x5D,0x22,0x3B,0x0D,0x0A
+,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F
+,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76
+,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x72,0x63,0x76,0x5F,0x74,0x65,0x78,0x74
+,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F
+,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65
+,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E
+,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x7D,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x7D,0x0D,0x0A
+,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x73,0x6E,0x64,0x5F,0x66
+,0x69,0x6C,0x65,0x5F,0x72,0x65,0x66,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x76,0x61,0x72
+,0x20,0x6F,0x62,0x6A,0x20,0x3D,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x67,0x65,0x74,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x42,0x79,0x49,0x64,0x28,0x22
+,0x66,0x69,0x6C,0x65,0x5F,0x75,0x70,0x6C,0x6F,0x61,0x64,0x22,0x29,0x2E,0x66,0x69
+,0x6C,0x65,0x73,0x5B,0x30,0x5D,0x3B,0x0D,0x0A,0x09,0x76,0x61,0x72,0x20,0x72,0x65
+,0x61,0x64,0x65,0x72,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20,0x46,0x69,0x6C,0x65,0x52
+,0x65,0x61,0x64,0x65,0x72,0x28,0x29,0x3B,0x0D,0x0A,0x09,0x72,0x65,0x61,0x64,0x65
+,0x72,0x2E,0x6F,0x6E,0x6C,0x6F,0x61,0x64,0x20,0x3D,0x20,0x66,0x75,0x6E,0x63,0x74
+,0x69,0x6F,0x6E,0x28,0x65,0x76,0x74,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x76,0x61
+,0x72,0x20,0x73,0x74,0x72,0x20,0x3D,0x20,0x65,0x76,0x74,0x2E,0x74,0x61,0x72,0x67
+,0x65,0x74,0x2E,0x72,0x65,0x73,0x75,0x6C,0x74,0x3B,0x0D,0x0A,0x09,0x09,0x76,0x61
+,0x72,0x20,0x73,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x20,0x3D,0x20,0x73,0x74,0x72
+,0x2E,0x73,0x70,0x6C,0x69,0x74,0x28,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x29,0x3B,0x0D
+,0x0A,0x09,0x09,0x76,0x61,0x72,0x20,0x63,0x6E,0x74,0x20,0x3D,0x20,0x30,0x3B,0x0D
+,0x0A,0x09,0x09,0x76,0x61,0x72,0x20,0x72,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x20
+,0x3D,0x20,0x30,0x3B,0x0D,0x0A,0x09,0x09,0x77,0x68,0x69,0x6C,0x65,0x20,0x28,0x28
+,0x73,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x5B,0x63,0x6E,0x74,0x5D,0x20,0x21,0x3D
+,0x20,0x6E,0x75,0x6C,0x6C,0x29,0x20,0x26,0x26,0x20,0x28,0x73,0x6E,0x64,0x5F,0x64
+,0x61,0x74,0x61,0x5B,0x63,0x6E,0x74,0x5D,0x20,0x21,0x3D,0x20,0x22,0x22,0x29,0x29
+,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72
+,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B,0x53,0x45
+,0x4E,0x44,0x5D,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65
+,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74
+,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x73
+,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x5B,0x63,0x6E,0x74,0x5D,0x3B,0x0D,0x0A,0x09
+,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66
+,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61
+,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x3B,0x0D,0x0A
+,0x09,0x09,0x09,0x72,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x20,0x3D,0x20,0x74,0x65
+,0x72,0x6D,0x2E,0x72,0x75,0x6E,0x28,0x73,0x6E,0x64,0x5F,0x64,0x61,0x74,0x61,0x5B
+,0x63,0x6E,0x74,0x5D,0x29,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x69,0x66,0x20,0x28,0x72
+,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x20,0x21,0x3D,0x20,0x22,0x72,0x75,0x6E,0x22
+,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x09,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E
+,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F
+,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5B
+,0x52,0x45,0x43,0x56,0x5D,0x22,0x3B,0x0D,0x0A,0x09,0x09,0x09,0x09,0x64,0x6F,0x63
+,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74
+,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x20,0x2B
+,0x3D,0x20,0x72,0x63,0x76,0x5F,0x64,0x61,0x74,0x61,0x3B,0x0D,0x0A,0x09,0x09,0x09
+,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F,0x66,0x6F
+,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76,0x61,0x6C
+,0x75,0x65,0x20,0x2B,0x3D,0x20,0x22,0x5C,0x72,0x5C,0x6E,0x22,0x3B,0x0D,0x0A,0x09
+,0x09,0x09,0x7D,0x0D,0x0A,0x09,0x09,0x09,0x63,0x6E,0x74,0x2B,0x2B,0x3B,0x0D,0x0A
+,0x09,0x09,0x7D,0x0D,0x0A,0x09,0x7D,0x0D,0x0A,0x09,0x72,0x65,0x61,0x64,0x65,0x72
+,0x2E,0x72,0x65,0x61,0x64,0x41,0x73,0x54,0x65,0x78,0x74,0x28,0x6F,0x62,0x6A,0x29
+,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E
+,0x20,0x43,0x6C,0x72,0x5F,0x74,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x7B
+,0x0D,0x0A,0x09,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F,0x75,0x74,0x5F
+,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65,0x61,0x2E,0x76
+,0x61,0x6C,0x75,0x65,0x20,0x3D,0x20,0x22,0x22,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A,0x0D
+,0x0A,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x20,0x53,0x61,0x76,0x65,0x5F,0x74
+,0x65,0x78,0x74,0x61,0x72,0x65,0x61,0x28,0x29,0x7B,0x0D,0x0A,0x09,0x76,0x61,0x72
+,0x20,0x62,0x6C,0x6F,0x62,0x5F,0x6F,0x62,0x6A,0x20,0x3D,0x20,0x6E,0x65,0x77,0x20
+,0x42,0x6C,0x6F,0x62,0x28,0x5B,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E,0x6F
+,0x75,0x74,0x5F,0x66,0x6F,0x72,0x6D,0x2E,0x74,0x65,0x78,0x74,0x5F,0x61,0x72,0x65
+,0x61,0x2E,0x76,0x61,0x6C,0x75,0x65,0x5D,0x2C,0x20,0x7B,0x74,0x79,0x70,0x65,0x3A
+,0x22,0x74,0x65,0x78,0x74,0x2F,0x70,0x6C,0x61,0x69,0x6E,0x22,0x7D,0x29,0x3B,0x0D
+,0x0A,0x09,0x3C,0x21,0x2D,0x2D,0x20,0x44,0x65,0x74,0x65,0x72,0x6D,0x69,0x6E,0x65
+,0x73,0x20,0x62,0x72,0x6F,0x77,0x73,0x65,0x72,0x20,0x2D,0x2D,0x3E,0x0D,0x0A,0x09
+,0x69,0x66,0x20,0x28,0x6E,0x61,0x76,0x69,0x67,0x61,0x74,0x6F,0x72,0x2E,0x6D,0x73
+,0x53,0x61,0x76,0x65,0x42,0x6C,0x6F,0x62,0x29,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x3C
+,0x21,0x2D,0x2D,0x20,0x49,0x45,0x20,0x2D,0x2D,0x3E,0x0D,0x0A,0x20,0x20,0x20,0x20
+,0x20,0x20,0x20,0x20,0x09,0x6E,0x61,0x76,0x69,0x67,0x61,0x74,0x6F,0x72,0x2E,0x6D
+,0x73,0x53,0x61,0x76,0x65,0x4F,0x72,0x4F,0x70,0x65,0x6E,0x42,0x6C,0x6F,0x62,0x28
+,0x62,0x6C,0x6F,0x62,0x5F,0x6F,0x62,0x6A,0x2C,0x20,0x27,0x63,0x6F,0x6D,0x6D,0x5F
+,0x6C,0x6F,0x67,0x2E,0x74,0x78,0x74,0x27,0x29,0x3B,0x0D,0x0A,0x09,0x7D,0x20,0x65
+,0x6C,0x73,0x65,0x20,0x7B,0x0D,0x0A,0x09,0x09,0x3C,0x21,0x2D,0x2D,0x20,0x45,0x78
+,0x70,0x65,0x63,0x74,0x20,0x49,0x45,0x20,0x2D,0x2D,0x3E,0x0D,0x0A,0x09,0x09,0x76
+,0x61,0x72,0x20,0x61,0x20,0x3D,0x20,0x64,0x6F,0x63,0x75,0x6D,0x65,0x6E,0x74,0x2E
+,0x63,0x72,0x65,0x61,0x74,0x65,0x45,0x6C,0x65,0x6D,0x65,0x6E,0x74,0x28,0x27,0x61
+,0x27,0x29,0x3B,0x0D,0x0A,0x09,0x09,0x61,0x2E,0x68,0x72,0x65,0x66,0x20,0x3D,0x20
+,0x55,0x52,0x4C,0x2E,0x63,0x72,0x65,0x61,0x74,0x65,0x4F,0x62,0x6A,0x65,0x63,0x74
+,0x55,0x52,0x4C,0x28,0x62,0x6C,0x6F,0x62,0x5F,0x6F,0x62,0x6A,0x29,0x3B,0x0D,0x0A
+,0x09,0x09,0x61,0x2E,0x73,0x65,0x74,0x41,0x74,0x74,0x72,0x69,0x62,0x75,0x74,0x65
+,0x28,0x27,0x64,0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64,0x27,0x2C,0x20,0x27,0x63,0x6F
+,0x6D,0x6D,0x5F,0x6C,0x6F,0x67,0x2E,0x74,0x78,0x74,0x27,0x29,0x3B,0x0D,0x0A,0x09
+,0x09,0x61,0x2E,0x64,0x69,0x73,0x70,0x61,0x74,0x63,0x68,0x45,0x76,0x65,0x6E,0x74
+,0x28,0x6E,0x65,0x77,0x20,0x43,0x75,0x73,0x74,0x6F,0x6D,0x45,0x76,0x65,0x6E,0x74
+,0x28,0x27,0x63,0x6C,0x69,0x63,0x6B,0x27,0x29,0x29,0x3B,0x0D,0x0A,0x09,0x7D,0x0D
+,0x0A,0x7D,0x0D,0x0A,0x0D,0x0A,0x3C,0x2F,0x73,0x63,0x72,0x69,0x70,0x74,0x3E,0x0D
+,0x0A,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74
+,0x6D,0x6C,0x3E,0x0D,0x0A
+};
+
+static const char web_top_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66
+,0x2D,0x38,0x22,0x3E,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x54,0x6F,0x70
+,0x20,0x50,0x61,0x67,0x65,0x3C,0x2F,0x74,0x69,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C
+,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x66,0x72,0x61,0x6D,0x65,0x73,0x65
+,0x74,0x20,0x63,0x6F,0x6C,0x73,0x3D,0x22,0x32,0x30,0x25,0x2C,0x38,0x30,0x25,0x22
+,0x3E,0x0D,0x0A,0x3C,0x66,0x72,0x61,0x6D,0x65,0x20,0x73,0x72,0x63,0x3D,0x22,0x6D
+,0x65,0x6E,0x75,0x2E,0x68,0x74,0x6D,0x22,0x3E,0x0D,0x0A,0x3C,0x66,0x72,0x61,0x6D
+,0x65,0x20,0x73,0x72,0x63,0x3D,0x22,0x77,0x69,0x6E,0x64,0x6F,0x77,0x2E,0x68,0x74
+,0x6D,0x22,0x20,0x6E,0x61,0x6D,0x65,0x3D,0x22,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65
+,0x22,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x6E,0x6F,0x66,0x72,0x61,0x6D,0x65,0x73,0x3E
+,0x0D,0x0A,0x3C,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x70,0x3E,0x59,0x6F,0x75
+,0x20,0x63,0x61,0x6E,0x20,0x6E,0x6F,0x74,0x20,0x76,0x69,0x65,0x77,0x20,0x74,0x68
+,0x69,0x73,0x20,0x73,0x61,0x6D,0x70,0x6C,0x65,0x20,0x73,0x69,0x6E,0x63,0x65,0x20
+,0x74,0x68,0x65,0x20,0x66,0x72,0x61,0x6D,0x65,0x20,0x6F,0x66,0x20,0x75,0x6E,0x73
+,0x75,0x70,0x70,0x6F,0x72,0x74,0x65,0x64,0x20,0x62,0x72,0x6F,0x77,0x73,0x65,0x72
+,0x2E,0x3C,0x2F,0x70,0x3E,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A
+,0x3C,0x2F,0x6E,0x6F,0x66,0x72,0x61,0x6D,0x65,0x73,0x3E,0x0D,0x0A,0x3C,0x2F,0x66
+,0x72,0x61,0x6D,0x65,0x73,0x65,0x74,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C
+,0x3E,0x0D,0x0A
+};
+
+static const char menu_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66
+,0x2D,0x38,0x22,0x3E,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x47,0x52,0x2D
+,0x50,0x45,0x41,0x43,0x48,0x20,0x4D,0x65,0x6E,0x75,0x3C,0x2F,0x74,0x69,0x74,0x6C
+,0x65,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C,0x62,0x6F
+,0x64,0x79,0x20,0x62,0x67,0x63,0x6F,0x6C,0x6F,0x72,0x3D,0x22,0x23,0x46,0x46,0x46
+,0x41,0x46,0x41,0x22,0x3E,0x0D,0x0A,0x3C,0x43,0x45,0x4E,0x54,0x45,0x52,0x3E,0x0D
+,0x0A,0x3C,0x50,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22
+,0x34,0x22,0x3E,0x3C,0x42,0x3E,0x4D,0x65,0x6E,0x75,0x3C,0x2F,0x42,0x3E,0x3C,0x2F
+,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x2F,0x50,0x3E,0x0D,0x0A,0x3C,0x2F,0x43,0x45,0x4E
+,0x54,0x45,0x52,0x3E,0x0D,0x0A,0x0D,0x0A,0x3C,0x70,0x3E,0x0D,0x0A,0x3C,0x66,0x6F
+,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61
+,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23
+,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x61,0x20,0x68,0x72,0x65,0x66,0x3D
+,0x22,0x77,0x69,0x6E,0x64,0x6F,0x77,0x2E,0x68,0x74,0x6D,0x22,0x20,0x74,0x61,0x72
+,0x67,0x65,0x74,0x3D,0x22,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65,0x22,0x3E,0x54,0x6F
+,0x70,0x20,0x50,0x61,0x67,0x65,0x3C,0x2F,0x61,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E
+,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22
+,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22
+,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C
+,0x61,0x20,0x68,0x72,0x65,0x66,0x3D,0x22,0x63,0x61,0x6D,0x65,0x72,0x61,0x2E,0x68
+,0x74,0x6D,0x22,0x20,0x74,0x61,0x72,0x67,0x65,0x74,0x3D,0x22,0x6B,0x69,0x72,0x69
+,0x6B,0x61,0x65,0x22,0x3E,0x57,0x65,0x62,0x20,0x43,0x61,0x6D,0x65,0x72,0x61,0x3C
+,0x2F,0x61,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74
+,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x66,0x6F
+,0x6E,0x74,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61
+,0x6E,0x20,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23
+,0x30,0x30,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x61,0x20,0x68,0x72,0x65,0x66,0x3D
+,0x22,0x69,0x32,0x63,0x5F,0x73,0x65,0x74,0x2E,0x68,0x74,0x6D,0x22,0x20,0x74,0x61
+,0x72,0x67,0x65,0x74,0x3D,0x22,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65,0x22,0x3E,0x53
+,0x65,0x74,0x74,0x69,0x6E,0x67,0x20,0x62,0x79,0x20,0x49,0x32,0x43,0x3C,0x2F,0x61
+,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x66,0x6F,0x6E,0x74
+,0x20,0x73,0x69,0x7A,0x65,0x3D,0x22,0x34,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20
+,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30
+,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x61,0x20,0x68,0x72,0x65,0x66,0x3D,0x22,0x6C
+,0x65,0x64,0x2E,0x68,0x74,0x6D,0x22,0x20,0x74,0x61,0x72,0x67,0x65,0x74,0x3D,0x22
+,0x6B,0x69,0x72,0x69,0x6B,0x61,0x65,0x22,0x3E,0x4C,0x45,0x44,0x20,0x4F,0x6E,0x2F
+,0x4F,0x66,0x66,0x3C,0x2F,0x61,0x3E,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F
+,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64
+,0x79,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x0D,0x0A
+};
+
+static const char window_htm_tbl[] = {
+ 0x3C,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x3C,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A
+,0x3C,0x6D,0x65,0x74,0x61,0x20,0x68,0x74,0x74,0x70,0x2D,0x65,0x71,0x75,0x69,0x76
+,0x3D,0x22,0x43,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x2D,0x54,0x79,0x70,0x65,0x22,0x20
+,0x63,0x6F,0x6E,0x74,0x65,0x6E,0x74,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x68,0x74
+,0x6D,0x6C,0x3B,0x20,0x63,0x68,0x61,0x72,0x73,0x65,0x74,0x3D,0x22,0x75,0x74,0x66
+,0x2D,0x38,0x22,0x3E,0x0D,0x0A,0x3C,0x74,0x69,0x74,0x6C,0x65,0x3E,0x47,0x52,0x2D
+,0x50,0x45,0x41,0x43,0x48,0x20,0x57,0x69,0x6E,0x64,0x6F,0x77,0x3C,0x2F,0x74,0x69
+,0x74,0x6C,0x65,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x65,0x61,0x64,0x3E,0x0D,0x0A,0x3C
+,0x62,0x6F,0x64,0x79,0x3E,0x0D,0x0A,0x3C,0x70,0x3E,0x3C,0x66,0x6F,0x6E,0x74,0x20
+,0x73,0x69,0x7A,0x65,0x3D,0x22,0x31,0x35,0x22,0x3E,0x3C,0x73,0x70,0x61,0x6E,0x20
+,0x73,0x74,0x79,0x6C,0x65,0x3D,0x22,0x63,0x6F,0x6C,0x6F,0x72,0x3A,0x23,0x30,0x30
+,0x30,0x30,0x38,0x30,0x22,0x3E,0x3C,0x62,0x3E,0x47,0x52,0x2D,0x50,0x45,0x41,0x43
+,0x48,0x20,0x41,0x75,0x64,0x69,0x6F,0x2F,0x43,0x61,0x6D,0x65,0x72,0x61,0x20,0x53
+,0x68,0x69,0x65,0x6C,0x64,0x20,0x53,0x61,0x6D,0x70,0x6C,0x65,0x3C,0x2F,0x62,0x3E
+,0x3C,0x2F,0x73,0x70,0x61,0x6E,0x3E,0x3C,0x2F,0x66,0x6F,0x6E,0x74,0x3E,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x54,0x68
+,0x69,0x73,0x20,0x73,0x61,0x6D,0x70,0x6C,0x65,0x20,0x70,0x72,0x6F,0x67,0x72,0x61
+,0x6D,0x20,0x75,0x73,0x69,0x6E,0x67,0x20,0x47,0x52,0x2D,0x50,0x45,0x41,0x43,0x48
+,0x20,0x61,0x6E,0x64,0x20,0x41,0x75,0x64,0x69,0x6F,0x2F,0x43,0x61,0x6D,0x65,0x72
+,0x61,0x20,0x53,0x68,0x69,0x65,0x6C,0x64,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x57
+,0x68,0x65,0x6E,0x20,0x79,0x6F,0x75,0x20,0x70,0x72,0x65,0x73,0x73,0x20,0x74,0x68
+,0x65,0x20,0x4D,0x65,0x6E,0x75,0x20,0x6F,0x6E,0x20,0x74,0x68,0x65,0x20,0x6C,0x65
+,0x66,0x74,0x2C,0x20,0x69,0x74,0x20,0x77,0x69,0x6C,0x6C,0x20,0x62,0x65,0x20,0x64
+,0x69,0x73,0x70,0x6C,0x61,0x79,0x65,0x64,0x20,0x69,0x6E,0x20,0x74,0x68,0x69,0x73
+,0x20,0x77,0x69,0x6E,0x64,0x6F,0x77,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x49,0x74,0x20,0x73,0x68,0x6F,0x77,0x73,0x20,0x74,0x68,0x65
+,0x20,0x6F,0x76,0x65,0x72,0x76,0x69,0x65,0x77,0x20,0x6F,0x66,0x20,0x65,0x61,0x63
+,0x68,0x20,0x6C,0x69,0x6E,0x6B,0x20,0x62,0x65,0x6C,0x6F,0x77,0x2E,0x3C,0x62,0x72
+,0x3E,0x0D,0x0A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x73,0x74,0x79,0x6C,0x65,0x20
+,0x74,0x79,0x70,0x65,0x3D,0x22,0x74,0x65,0x78,0x74,0x2F,0x63,0x73,0x73,0x22,0x3E
+,0x0D,0x0A,0x2E,0x74,0x61,0x62,0x6C,0x65,0x20,0x74,0x68,0x20,0x7B,0x0D,0x0A,0x20
+,0x20,0x62,0x61,0x63,0x6B,0x67,0x72,0x6F,0x75,0x6E,0x64,0x2D,0x63,0x6F,0x6C,0x6F
+,0x72,0x3A,0x20,0x23,0x65,0x36,0x66,0x66,0x65,0x39,0x3B,0x0D,0x0A,0x7D,0x0D,0x0A
+,0x3C,0x2F,0x73,0x74,0x79,0x6C,0x65,0x3E,0x0D,0x0A,0x3C,0x74,0x61,0x62,0x6C,0x65
+,0x20,0x63,0x6C,0x61,0x73,0x73,0x3D,0x22,0x74,0x61,0x62,0x6C,0x65,0x22,0x20,0x62
+,0x6F,0x72,0x64,0x65,0x72,0x3D,0x31,0x3E,0x0D,0x0A,0x3C,0x74,0x72,0x3E,0x0D,0x0A
+,0x3C,0x74,0x68,0x3E,0x4C,0x69,0x6E,0x6B,0x73,0x3C,0x2F,0x74,0x68,0x3E,0x3C,0x74
+,0x68,0x3E,0x4F,0x76,0x65,0x72,0x76,0x69,0x65,0x77,0x3C,0x2F,0x74,0x68,0x3E,0x0D
+,0x0A,0x3C,0x2F,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74
+,0x64,0x3E,0x54,0x6F,0x70,0x20,0x50,0x61,0x67,0x65,0x3C,0x2F,0x74,0x64,0x3E,0x3C
+,0x74,0x64,0x3E,0x49,0x74,0x20,0x77,0x69,0x6C,0x6C,0x20,0x72,0x65,0x74,0x75,0x72
+,0x6E,0x20,0x74,0x6F,0x20,0x74,0x68,0x65,0x20,0x74,0x6F,0x70,0x20,0x70,0x61,0x67
+,0x65,0x2E,0x3C,0x62,0x72,0x3E,0x3C,0x2F,0x74,0x64,0x3E,0x0D,0x0A,0x3C,0x2F,0x74
+,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x64,0x3E,0x57,0x65
+,0x62,0x20,0x43,0x61,0x6D,0x65,0x72,0x61,0x3C,0x2F,0x74,0x64,0x3E,0x3C,0x74,0x64
+,0x3E,0x49,0x74,0x20,0x69,0x6E,0x64,0x69,0x63,0x61,0x74,0x65,0x73,0x20,0x74,0x68
+,0x65,0x20,0x69,0x6D,0x61,0x67,0x65,0x20,0x61,0x63,0x71,0x75,0x69,0x72,0x65,0x64
+,0x20,0x62,0x79,0x20,0x74,0x68,0x65,0x20,0x63,0x61,0x6D,0x65,0x72,0x61,0x20,0x6F
+,0x6E,0x20,0x74,0x68,0x65,0x20,0x77,0x65,0x62,0x20,0x62,0x72,0x6F,0x77,0x73,0x65
+,0x72,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x49,0x74,0x20,0x63,0x61,0x6E,0x20,0x62
+,0x65,0x20,0x63,0x68,0x61,0x6E,0x67,0x65,0x64,0x20,0x61,0x74,0x20,0x61,0x20,0x73
+,0x6C,0x69,0x64,0x65,0x72,0x20,0x62,0x61,0x72,0x20,0x69,0x6E,0x20,0x22,0x57,0x61
+,0x69,0x74,0x20,0x74,0x69,0x6D,0x65,0x22,0x20,0x61,0x74,0x20,0x74,0x68,0x65,0x20
+,0x74,0x69,0x6D,0x69,0x6E,0x67,0x20,0x6F,0x66,0x20,0x61,0x20,0x72,0x65,0x6E,0x65
+,0x77,0x61,0x6C,0x20,0x6F,0x66,0x20,0x61,0x20,0x63,0x61,0x6D,0x65,0x72,0x61,0x20
+,0x70,0x69,0x63,0x74,0x75,0x72,0x65,0x2E,0x20,0x28,0x44,0x65,0x66,0x61,0x75,0x6C
+,0x74,0x73,0x20,0x61,0x72,0x65,0x20,0x35,0x30,0x30,0x6D,0x73,0x2E,0x29,0x3C,0x2F
+,0x74,0x64,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x72,0x3E
+,0x0D,0x0A,0x3C,0x74,0x64,0x3E,0x53,0x65,0x74,0x74,0x69,0x6E,0x67,0x20,0x62,0x79
+,0x20,0x49,0x32,0x43,0x3C,0x2F,0x74,0x64,0x3E,0x3C,0x74,0x64,0x3E,0x49,0x74,0x20
+,0x69,0x6E,0x64,0x69,0x63,0x61,0x74,0x65,0x73,0x20,0x49,0x32,0x43,0x20,0x73,0x65
+,0x74,0x74,0x69,0x6E,0x67,0x20,0x6F,0x6E,0x20,0x74,0x68,0x65,0x20,0x77,0x65,0x62
+,0x20,0x62,0x72,0x6F,0x77,0x73,0x65,0x72,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x49
+,0x6E,0x20,0x49,0x32,0x43,0x20,0x63,0x6F,0x6D,0x6D,0x75,0x6E,0x69,0x63,0x61,0x74
+,0x69,0x6F,0x6E,0x2C,0x20,0x47,0x52,0x2D,0x50,0x45,0x41,0x43,0x48,0x20,0x65,0x78
+,0x65,0x63,0x75,0x74,0x65,0x73,0x20,0x74,0x68,0x65,0x20,0x73,0x65,0x74,0x74,0x69
+,0x6E,0x67,0x73,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x64,0x65,0x76,0x69,0x63
+,0x65,0x73,0x20,0x63,0x6F,0x6E,0x6E,0x65,0x63,0x74,0x65,0x64,0x20,0x74,0x6F,0x20
+,0x49,0x32,0x43,0x5F,0x53,0x43,0x41,0x20,0x74,0x65,0x72,0x6D,0x69,0x6E,0x61,0x6C
+,0x20,0x61,0x6E,0x64,0x20,0x49,0x32,0x43,0x5F,0x53,0x43,0x4C,0x20,0x74,0x65,0x72
+,0x6D,0x69,0x6E,0x61,0x6C,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x4F,0x6E,0x20,0x74
+,0x68,0x65,0x20,0x62,0x61,0x73,0x69,0x73,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20
+,0x63,0x6F,0x6D,0x6D,0x61,0x6E,0x64,0x2C,0x20,0x47,0x52,0x2D,0x50,0x45,0x41,0x43
+,0x48,0x20,0x61,0x63,0x63,0x65,0x73,0x73,0x65,0x73,0x20,0x74,0x6F,0x20,0x72,0x65
+,0x67,0x69,0x73,0x74,0x65,0x72,0x73,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x64
+,0x65,0x76,0x69,0x63,0x65,0x73,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x59,0x6F,0x75
+,0x20,0x63,0x61,0x6E,0x20,0x73,0x65,0x6E,0x64,0x20,0x74,0x68,0x65,0x20,0x63,0x6F
+,0x6D,0x6D,0x61,0x6E,0x64,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x70,0x65
+,0x63,0x69,0x66,0x69,0x65,0x64,0x20,0x66,0x6F,0x72,0x6D,0x61,0x74,0x20,0x69,0x6E
+,0x20,0x6F,0x6E,0x65,0x20,0x6F,0x66,0x20,0x74,0x77,0x6F,0x20,0x70,0x61,0x74,0x74
+,0x65,0x72,0x6E,0x73,0x20,0x62,0x65,0x6C,0x6F,0x77,0x2E,0x3C,0x62,0x72,0x3E,0x0D
+,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x22,0x44,0x69
+,0x72,0x65,0x63,0x74,0x6C,0x20,0x69,0x6E,0x70,0x75,0x74,0x22,0x20,0x6F,0x72,0x20
+,0x22,0x46,0x69,0x6C,0x65,0x20,0x72,0x65,0x66,0x65,0x72,0x65,0x6E,0x63,0x65,0x22
+,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x50,0x6C,0x65,0x61,0x73,0x65,0x20,0x63,0x72
+,0x65,0x61,0x74,0x65,0x20,0x61,0x20,0x63,0x6F,0x6D,0x6D,0x61,0x6E,0x64,0x20,0x61
+,0x6C,0x6F,0x6E,0x67,0x20,0x74,0x68,0x65,0x20,0x66,0x6F,0x72,0x6D,0x61,0x74,0x20
+,0x61,0x66,0x74,0x65,0x72,0x20,0x79,0x6F,0x75,0x20,0x63,0x68,0x65,0x63,0x6B,0x20
+,0x74,0x68,0x65,0x20,0x73,0x70,0x65,0x63,0x69,0x66,0x69,0x63,0x61,0x74,0x69,0x6F
+,0x6E,0x73,0x20,0x6F,0x66,0x20,0x65,0x61,0x63,0x68,0x20,0x64,0x65,0x76,0x69,0x63
+,0x65,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x54,0x68,0x65,0x20,0x66,0x6F,0x72,0x6D
+,0x61,0x74,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x63,0x6F,0x6D,0x6D,0x61,0x6E
+,0x64,0x20,0x69,0x73,0x3A,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70
+,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x4D,0x65,0x74,0x68,0x6F,0x64,0x3A,0x49,0x32
+,0x43,0x20,0x61,0x64,0x64,0x72,0x2C,0x64,0x61,0x74,0x61,0x20,0x6C,0x65,0x6E,0x67
+,0x74,0x68,0x2C,0x64,0x61,0x74,0x61,0x31,0x2C,0x64,0x61,0x74,0x61,0x32,0x2C,0x64
+,0x61,0x74,0x61,0x33,0x2C,0x2E,0x2E,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x4D,0x65,0x74,0x68,0x6F,0x64,0x20,0x69,0x73,0x20,0x62,0x65
+,0x6C,0x6F,0x77,0x2E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B
+,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x22,0x57,0x72,0x22
+,0x69,0x73,0x20,0x57,0x72,0x69,0x74,0x65,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F
+,0x6E,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62
+,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x22,0x52,0x64,0x22,0x20,0x69,0x73
+,0x20,0x52,0x65,0x61,0x64,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x3C,0x62
+,0x72,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B
+,0x26,0x6E,0x62,0x73,0x70,0x3B,0x22,0x57,0x72,0x4E,0x6F,0x70,0x22,0x20,0x69,0x73
+,0x20,0x57,0x72,0x69,0x74,0x65,0x20,0x66,0x75,0x6E,0x63,0x74,0x69,0x6F,0x6E,0x28
+,0x4E,0x6F,0x20,0x53,0x54,0x4F,0x50,0x20,0x63,0x6F,0x6E,0x64,0x69,0x74,0x69,0x6F
+,0x6E,0x29,0x3C,0x62,0x72,0x3E,0x0D,0x0A,0x26,0x6E,0x62,0x73,0x70,0x3B,0x26,0x6E
+,0x62,0x73,0x70,0x3B,0x26,0x6E,0x62,0x73,0x70,0x3B,0x22,0x52,0x64,0x4E,0x6F,0x70
+,0x22,0x20,0x69,0x73,0x20,0x52,0x65,0x61,0x64,0x20,0x66,0x75,0x6E,0x63,0x74,0x69
+,0x6F,0x6E,0x28,0x4E,0x6F,0x20,0x53,0x54,0x4F,0x50,0x20,0x63,0x6F,0x6E,0x64,0x69
+,0x74,0x69,0x6F,0x6E,0x29,0x3C,0x62,0x72,0x3E,0x3C,0x2F,0x74,0x64,0x3E,0x0D,0x0A
+,0x3C,0x2F,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x74,0x64
+,0x3E,0x4C,0x45,0x44,0x20,0x4F,0x6E,0x2F,0x4F,0x66,0x66,0x3C,0x2F,0x74,0x64,0x3E
+,0x3C,0x74,0x64,0x3E,0x49,0x74,0x20,0x69,0x6E,0x64,0x69,0x63,0x61,0x74,0x65,0x73
+,0x20,0x4C,0x45,0x44,0x31,0x2C,0x20,0x4C,0x45,0x44,0x32,0x20,0x61,0x6E,0x64,0x20
+,0x4C,0x45,0x44,0x33,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x74,0x6F,0x67,0x67
+,0x6C,0x65,0x20,0x73,0x77,0x69,0x74,0x63,0x68,0x20,0x6F,0x6E,0x20,0x74,0x68,0x65
+,0x20,0x77,0x65,0x62,0x20,0x62,0x72,0x6F,0x77,0x73,0x65,0x72,0x2E,0x3C,0x62,0x72
+,0x3E,0x0D,0x0A,0x45,0x61,0x63,0x68,0x20,0x73,0x77,0x69,0x74,0x63,0x68,0x20,0x69
+,0x6E,0x64,0x69,0x63,0x61,0x74,0x65,0x73,0x20,0x74,0x68,0x65,0x20,0x63,0x75,0x72
+,0x72,0x65,0x6E,0x74,0x20,0x4C,0x45,0x44,0x20,0x73,0x74,0x61,0x74,0x65,0x2E,0x3C
+,0x62,0x72,0x3E,0x0D,0x0A,0x4C,0x45,0x44,0x20,0x4F,0x4E,0x20,0x61,0x6E,0x64,0x20
+,0x4F,0x46,0x46,0x20,0x73,0x77,0x69,0x74,0x63,0x68,0x65,0x73,0x20,0x77,0x68,0x65
+,0x6E,0x20,0x79,0x6F,0x75,0x20,0x70,0x72,0x65,0x73,0x73,0x20,0x74,0x68,0x65,0x20
+,0x73,0x77,0x69,0x74,0x63,0x68,0x2E,0x20,0x57,0x68,0x65,0x6E,0x20,0x74,0x68,0x65
+,0x20,0x4C,0x45,0x44,0x20,0x69,0x73,0x20,0x4F,0x4E,0x2C,0x20,0x74,0x68,0x65,0x20
+,0x63,0x6F,0x6C,0x6F,0x72,0x20,0x6F,0x66,0x20,0x74,0x68,0x65,0x20,0x73,0x77,0x69
+,0x74,0x63,0x68,0x20,0x77,0x69,0x6C,0x6C,0x20,0x63,0x68,0x61,0x6E,0x67,0x65,0x20
+,0x74,0x68,0x65,0x20,0x4C,0x45,0x44,0x20,0x63,0x6F,0x6C,0x6F,0x72,0x2E,0x3C,0x2F
+,0x74,0x64,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x72,0x3E,0x0D,0x0A,0x3C,0x2F,0x74,0x61
+,0x62,0x6C,0x65,0x3E,0x0D,0x0A,0x0D,0x0A,0x0D,0x0A,0x3C,0x2F,0x62,0x6F,0x64,0x79
+,0x3E,0x0D,0x0A,0x3C,0x2F,0x68,0x74,0x6D,0x6C,0x3E,0x0D,0x0A,0x0D,0x0A
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/i2c_setting.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,245 @@
+/*
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#include "mbed.h"
+#include "i2c_setting.h"
+
+#define REG_REQ_BUF_SIZE        (7)
+#define DATA_MAX_SIZE           (32)
+#define ARG_MAX_NUM             (DATA_MAX_SIZE + 3)      // Reqest, I2C addr, len, data1, data2, data3, ...
+#define ARG_MAX_SIZE            (2)                      // upper bit + lower bit
+#define NULL_SIZE               (1)
+#define CODE_NULL               (0x00)
+#define NUM_STR_TO_HEX          (0x30)
+#define BIG_STR_TO_HEX          (0x37)
+#define SMA_STR_TO_HEX          (0x57)
+#define MASK_HEX10              (0x10)
+
+#define OFS_REQ                 (0)
+#define OFS_I2C_ADDR            (1)
+#define OFS_DATA_SIZE           (2)
+#define OFS_DATA                (3)
+
+#define STR_WR                  "Wr:"
+#define STR_RD                  "Rd:"
+#define STR_WR_NO_P             "WrNoP:"
+#define STR_RD_NO_P             "RdNoP:"
+
+#define REQ_NONE                (0)
+#define REQ_WR                  (1)
+#define REQ_RD                  (2)
+#define REQ_WR_NO_P             (3)
+#define REQ_RD_NO_P             (4)
+
+I2C i2c(I2C_SDA, I2C_SCL);
+
+static char hex_to_char_tbl[] = {
+    '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+    'A', 'B', 'C', 'D', 'E', 'F'
+};
+
+static int str_to_hex(char * psrcbuf, char * pdestbuf, int cnt) {
+    int retval = false;
+    int32_t tmp_hex;
+
+    if ((psrcbuf != NULL) && (pdestbuf != NULL)) {
+        retval = true;
+        if ((((int32_t)*psrcbuf) >= '0') && (((int32_t)*psrcbuf) <= '9')) {
+            tmp_hex = NUM_STR_TO_HEX;
+        } else if ((((int32_t)*psrcbuf) >= 'A') && (((int32_t)*psrcbuf) <= 'F')) {
+            tmp_hex = BIG_STR_TO_HEX;
+        } else if ((((int32_t)*psrcbuf) >= 'a') && (((int32_t)*psrcbuf) <= 'f')) {
+            tmp_hex = SMA_STR_TO_HEX;
+        } else {
+            retval = false;
+        }
+        if (retval == true) {
+            *pdestbuf += ((int32_t)*psrcbuf) - tmp_hex;
+            if (cnt == 0) {
+                *pdestbuf *= MASK_HEX10;
+            }
+        }
+    }
+
+    return retval;
+}
+
+static void char_to_16char(char * pdestbuf, char * psrcbuf, int length) {
+    if ((pdestbuf != NULL) && (psrcbuf != NULL)) {
+        while (1) {
+            *pdestbuf = hex_to_char_tbl[((int32_t)*psrcbuf) / MASK_HEX10];
+            pdestbuf++;
+            *pdestbuf = hex_to_char_tbl[((int32_t)*psrcbuf) % MASK_HEX10];
+            pdestbuf++;
+
+            psrcbuf++;
+            length--;
+            if (length != 0) {
+                *pdestbuf = ',';
+                pdestbuf++;
+            } else {
+                break;
+            }
+        }
+        *pdestbuf = CODE_NULL;
+    }
+}
+
+static int analysis_cmd(char * buf, char * p_reg_arg_buf) {
+    int  arg_cnt = 0;
+    int  byte_cnt = 0;
+    int  retval;
+    char * psrcbuf = buf;
+    int  ret;
+
+    if (strncmp(psrcbuf, STR_WR, sizeof(STR_WR) - 1) == 0) {
+        ret = REQ_WR;
+        psrcbuf += sizeof(STR_WR) - 1;
+    } else if (strncmp(psrcbuf, STR_RD, sizeof(STR_RD) - 1) == 0) {
+        ret = REQ_RD;
+        psrcbuf += sizeof(STR_RD) - 1;
+    } else if (strncmp(psrcbuf, STR_WR_NO_P, sizeof(STR_WR_NO_P) - 1) == 0) {
+        ret = REQ_WR_NO_P;
+        psrcbuf += sizeof(STR_WR_NO_P) - 1;
+    } else if (strncmp(psrcbuf, STR_RD_NO_P, sizeof(STR_RD_NO_P) - 1) == 0) {
+        ret = REQ_RD_NO_P;
+        psrcbuf += sizeof(STR_RD_NO_P) - 1;
+    } else {
+        ret = REQ_NONE;
+    }
+
+    if (ret != REQ_NONE) {
+        /* get argument(Reqest, I2C addr, len, data1, data2, data3, ...) */
+        p_reg_arg_buf[arg_cnt] = ret;
+        arg_cnt++;
+        byte_cnt = 0;
+        while (((int32_t)*psrcbuf) != CODE_NULL) {
+            retval = str_to_hex(psrcbuf, &p_reg_arg_buf[arg_cnt], byte_cnt);
+            if (retval != false) {
+                byte_cnt++;
+                if (byte_cnt >= ARG_MAX_SIZE) {
+                    if ((arg_cnt + 1) >= ARG_MAX_NUM) {
+                        ret = REQ_NONE;
+                        break;
+                    } else {
+                        arg_cnt++;
+                        byte_cnt = 0;
+                    }
+                }
+            }
+            psrcbuf++;
+        }
+    }
+
+    return ret;
+}
+
+static void execute_cmd(char * buf, char * p_reg_arg_buf) {
+    int ret;
+    size_t len;
+    int stop = 0;
+
+    /* check request */
+    if ((p_reg_arg_buf[OFS_REQ] == REQ_WR_NO_P) || (p_reg_arg_buf[OFS_REQ] == REQ_RD_NO_P)) {
+        stop = 1;
+    }
+
+    switch (p_reg_arg_buf[OFS_REQ]) {
+        case REQ_WR:
+        case REQ_WR_NO_P:
+            ret = i2c.write(p_reg_arg_buf[OFS_I2C_ADDR], &p_reg_arg_buf[OFS_DATA], p_reg_arg_buf[OFS_DATA_SIZE], stop);
+            if (ret == 0) {
+                sprintf(buf, "OK");
+            }
+        break;
+        case REQ_RD:
+        case REQ_RD_NO_P:
+            ret = i2c.read(p_reg_arg_buf[OFS_I2C_ADDR], &p_reg_arg_buf[OFS_DATA], p_reg_arg_buf[OFS_DATA_SIZE], stop);
+            if (ret == 0) {
+                sprintf(buf, "OK ");
+                len = strlen(buf);
+                char_to_16char(&buf[len], &p_reg_arg_buf[OFS_DATA], p_reg_arg_buf[OFS_DATA_SIZE]);
+            }
+        break;
+        default:
+        case REQ_NONE:
+            ret = -1;
+        break;
+    }
+    if (ret != 0) {
+        sprintf(buf, "NG");
+    }
+}
+
+bool i2c_setting_exe(char * buf) {
+    int reg_arg_cnt;
+    char reg_arg_buf[ARG_MAX_NUM] = {0};
+
+    /* analysis command */
+    reg_arg_cnt = analysis_cmd(buf, reg_arg_buf);
+    if (reg_arg_cnt != REQ_NONE) {
+        /* check length */
+        if (reg_arg_buf[OFS_DATA_SIZE] >= DATA_MAX_SIZE) {
+            reg_arg_buf[OFS_DATA_SIZE] = DATA_MAX_SIZE;
+        }
+        /* execute command */
+        execute_cmd(buf, reg_arg_buf);
+        return true;
+    }
+
+    return false;
+}
+
+#if(0) /* Please enable this line when performing the setting from the Terminal side. */
+Serial terminal(USBTX, USBRX);
+static char recv_term_buffer[I2C_SETTING_STR_BUF_SIZE];
+
+void SetI2CfromTerm(void const *argument) {
+    int32_t term_buf_offset = 0;
+    char recv_data;
+
+    while (1) {
+        recv_data = terminal.getc();
+        /* echo back */
+        printf("%c", recv_data);
+        switch ((int32_t)recv_data) {
+            case 0x0A :
+                recv_term_buffer[term_buf_offset] = CODE_NULL;
+                term_buf_offset = 0;
+                /* command analysis and execute */
+                if (i2c_setting_exe(recv_term_buffer) != false) {
+                    terminal.puts(recv_term_buffer);
+                }
+            break;
+            case 0x0D :
+                /* Do Nothing */
+            break;
+            default :
+                /* check data_buffer size  */
+                if (term_buf_offset < I2C_SETTING_STR_BUF_SIZE) {
+                    recv_term_buffer[term_buf_offset] = recv_data;
+                    term_buf_offset++;
+                }
+            break;
+        }
+    }
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/i2c_setting.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,28 @@
+/*
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#ifndef I2C_SETTING_H
+#define I2C_SETTING_H
+
+#define I2C_SETTING_STR_BUF_SIZE   (150)
+
+extern bool i2c_setting_exe(char * buf);
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,422 @@
+#include "mbed.h"
+#include "EasyAttach_CameraAndLCD.h"
+#include "dcache-control.h"
+#include "JPEG_Converter.h"
+#include "HTTPServer.h"
+#include "mbed_rpc.h"
+#include "FATFileSystem.h"
+#include "RomRamBlockDevice.h"
+#include "SDBlockDevice_GRBoard.h"
+#if defined(TARGET_RZ_A1H)
+#include "file_table_peach.h"         //Binary data of web pages
+#elif defined(TARGET_GR_LYCHEE)
+#include "file_table_lychee.h"        //Binary data of web pages
+#endif
+#include "i2c_setting.h"
+
+/**** User Selection *********/
+/** Network setting **/
+#define USE_DHCP               (1)                 /* Select  0(static configuration) or 1(use DHCP) */
+#if (USE_DHCP == 0)
+  #define IP_ADDRESS           ("192.168.0.2")     /* IP address      */
+  #define SUBNET_MASK          ("255.255.255.0")   /* Subnet mask     */
+  #define DEFAULT_GATEWAY      ("192.168.0.3")     /* Default gateway */
+#endif
+#define NETWORK_TYPE           (2)                 /* Select  0(Ethernet), 1(reserved), 2(ESP32 STA) ,3(ESP32 AP) */
+#if (NETWORK_TYPE >= 2)
+  #define SCAN_NETWORK         (1)                 /* Select  0(Use WLAN_SSID, WLAN_PSK, WLAN_SECURITY) or 1(To select a network using the terminal.) */
+  #define WLAN_SSID            ("SSIDofYourAP")    /* SSID */
+  #define WLAN_PSK             ("PSKofYourAP")     /* PSK(Pre-Shared Key) */
+  #define WLAN_SECURITY        NSAPI_SECURITY_WPA_WPA2 /* NSAPI_SECURITY_NONE, NSAPI_SECURITY_WEP, NSAPI_SECURITY_WPA, NSAPI_SECURITY_WPA2 or NSAPI_SECURITY_WPA_WPA2 */
+#endif
+/** JPEG out setting **/
+#define JPEG_ENCODE_QUALITY    (75)                /* JPEG encode quality (min:1, max:75 (Considering the size of JpegBuffer, about 75 is the upper limit.)) */
+#define VFIELD_INT_SKIP_CNT    (0)                 /* A guide for GR-LYCHEE.  0:60fps, 1:30fps, 2:20fps, 3:15fps, 4:12fps, 5:10fps */
+/*****************************/
+
+#if (NETWORK_TYPE == 0)
+  #include "EthernetInterface.h"
+  EthernetInterface network;
+#elif (NETWORK_TYPE == 2)
+  #include "ESP32Interface.h"
+  ESP32Interface network;
+#elif (NETWORK_TYPE == 3)
+  #include "ESP32InterfaceAP.h"
+  ESP32InterfaceAP network;
+#else
+  #error NETWORK_TYPE error
+#endif /* NETWORK_TYPE */
+
+/* Video input and LCD layer 0 output */
+#define VIDEO_FORMAT           (DisplayBase::VIDEO_FORMAT_YCBCR422)
+#define GRAPHICS_FORMAT        (DisplayBase::GRAPHICS_FORMAT_YCBCR422)
+#define WR_RD_WRSWA            (DisplayBase::WR_RD_WRSWA_32_16BIT)
+#define DATA_SIZE_PER_PIC      (2u)
+
+/*! Frame buffer stride: Frame buffer stride should be set to a multiple of 32 or 128
+    in accordance with the frame buffer burst transfer mode. */
+#define VIDEO_PIXEL_HW         (320u)  /* QVGA */
+#define VIDEO_PIXEL_VW         (240u)  /* QVGA */
+
+#define FRAME_BUFFER_STRIDE    (((VIDEO_PIXEL_HW * DATA_SIZE_PER_PIC) + 31u) & ~31u)
+#define FRAME_BUFFER_HEIGHT    (VIDEO_PIXEL_VW)
+
+DisplayBase Display;
+
+#if defined(__ICCARM__)
+#pragma data_alignment=32
+static uint8_t user_frame_buffer0[FRAME_BUFFER_STRIDE * FRAME_BUFFER_HEIGHT]@ ".mirrorram";
+#else
+static uint8_t user_frame_buffer0[FRAME_BUFFER_STRIDE * FRAME_BUFFER_HEIGHT]__attribute((section("NC_BSS"),aligned(32)));
+#endif
+
+FATFileSystem fs("storage");
+RomRamBlockDevice romram_bd(512000, 512);
+SDBlockDevice_GRBoard sd;
+Serial pc(USBTX, USBRX);
+Thread sdConnectTask;
+
+#if defined(__ICCARM__)
+#pragma data_alignment=32
+static uint8_t JpegBuffer[2][1024 * 64];
+#else
+static uint8_t JpegBuffer[2][1024 * 64]__attribute((aligned(32)));
+#endif
+static size_t jcu_encode_size[2];
+static int image_change = 0;
+JPEG_Converter Jcu;
+static int jcu_buf_index_write = 0;
+static int jcu_buf_index_write_done = 0;
+static int jcu_buf_index_read = 0;
+static int jcu_encoding = 0;
+static int Vfield_Int_Cnt = 0;
+static char i2c_setting_str_buf[I2C_SETTING_STR_BUF_SIZE];
+
+static void JcuEncodeCallBackFunc(JPEG_Converter::jpeg_conv_error_t err_code) {
+    if (err_code == JPEG_Converter::JPEG_CONV_OK) {
+        jcu_buf_index_write_done = jcu_buf_index_write;
+        image_change = 1;
+    }
+    jcu_encoding = 0;
+}
+
+static int snapshot_req(const char ** pp_data) {
+    int encode_size;
+
+    while ((jcu_encoding == 1) || (image_change == 0)) {
+        ThisThread::sleep_for(1);
+    }
+    jcu_buf_index_read = jcu_buf_index_write_done;
+    image_change = 0;
+
+    *pp_data = (const char *)JpegBuffer[jcu_buf_index_read];
+    encode_size = (int)jcu_encode_size[jcu_buf_index_read];
+
+    return encode_size;
+}
+
+static void IntCallbackFunc_Vfield(DisplayBase::int_type_t int_type) {
+    if (Vfield_Int_Cnt < VFIELD_INT_SKIP_CNT) {
+        Vfield_Int_Cnt++;
+        return;
+    }
+    Vfield_Int_Cnt = 0;
+
+    //Interrupt callback function
+    if (jcu_encoding == 0) {
+        JPEG_Converter::bitmap_buff_info_t bitmap_buff_info;
+        JPEG_Converter::encode_options_t   encode_options;
+
+        bitmap_buff_info.width              = VIDEO_PIXEL_HW;
+        bitmap_buff_info.height             = VIDEO_PIXEL_VW;
+        bitmap_buff_info.format             = JPEG_Converter::WR_RD_YCbCr422;
+        bitmap_buff_info.buffer_address     = (void *)user_frame_buffer0;
+
+        encode_options.encode_buff_size     = sizeof(JpegBuffer[0]);
+        encode_options.p_EncodeCallBackFunc = &JcuEncodeCallBackFunc;
+        encode_options.input_swapsetting    = JPEG_Converter::WR_RD_WRSWA_32_16_8BIT;
+
+        jcu_encoding = 1;
+        if (jcu_buf_index_read == jcu_buf_index_write) {
+            jcu_buf_index_write ^= 1;  // toggle
+        }
+        jcu_encode_size[jcu_buf_index_write] = 0;
+        dcache_invalid(JpegBuffer[jcu_buf_index_write], sizeof(JpegBuffer[0]));
+        if (Jcu.encode(&bitmap_buff_info, JpegBuffer[jcu_buf_index_write],
+            &jcu_encode_size[jcu_buf_index_write], &encode_options) != JPEG_Converter::JPEG_CONV_OK) {
+            jcu_encode_size[jcu_buf_index_write] = 0;
+            jcu_encoding = 0;
+        }
+    }
+}
+
+static void Start_Video_Camera(void) {
+    // Video capture setting (progressive form fixed)
+    Display.Video_Write_Setting(
+        DisplayBase::VIDEO_INPUT_CHANNEL_0,
+        DisplayBase::COL_SYS_NTSC_358,
+        (void *)user_frame_buffer0,
+        FRAME_BUFFER_STRIDE,
+        VIDEO_FORMAT,
+        WR_RD_WRSWA,
+        VIDEO_PIXEL_VW,
+        VIDEO_PIXEL_HW
+    );
+    EasyAttach_CameraStart(Display, DisplayBase::VIDEO_INPUT_CHANNEL_0);
+}
+
+static void TerminalWrite(Arguments* arg, Reply* r) {
+    if ((arg != NULL) && (r != NULL)) {
+        for (int i = 0; i < arg->argc; i++) {
+            if (arg->argv[i] != NULL) {
+                printf("%s", arg->argv[i]);
+            }
+        }
+        printf("\n");
+        r->putData<const char*>("ok");
+    }
+}
+
+static void mount_romramfs(void) {
+    FILE * fp;
+
+    romram_bd.SetRomAddr(0x18000000, 0x1FFFFFFF);
+    fs.format(&romram_bd, 512);
+    fs.mount(&romram_bd);
+
+    //index.htm
+    fp = fopen("/storage/index.htm", "w");
+    fwrite(index_htm_tbl, sizeof(char), sizeof(index_htm_tbl), fp);
+    fclose(fp);
+
+    //camera.js
+    fp = fopen("/storage/camera.js", "w");
+    fwrite(camaera_js_tbl, sizeof(char), sizeof(camaera_js_tbl), fp);
+    fclose(fp);
+
+    //camera.htm
+    fp = fopen("/storage/camera.htm", "w");
+    fwrite(camera_htm_tbl, sizeof(char), sizeof(camera_htm_tbl), fp);
+    fclose(fp);
+
+    //mbedrpc.js
+    fp = fopen("/storage/mbedrpc.js", "w");
+    fwrite(mbedrpc_js_tbl, sizeof(char), sizeof(mbedrpc_js_tbl), fp);
+    fclose(fp);
+
+    //led.htm
+    fp = fopen("/storage/led.htm", "w");
+    fwrite(led_htm_tbl, sizeof(char), sizeof(led_htm_tbl), fp);
+    fclose(fp);
+
+    //i2c_set.htm
+    fp = fopen("/storage/i2c_set.htm", "w");
+    fwrite(i2c_set_htm_tbl, sizeof(char), sizeof(i2c_set_htm_tbl), fp);
+    fclose(fp);
+
+    //web_top.htm
+    fp = fopen("/storage/web_top.htm", "w");
+    fwrite(web_top_htm_tbl, sizeof(char), sizeof(web_top_htm_tbl), fp);
+    fclose(fp);
+
+    //menu.htm
+    fp = fopen("/storage/menu.htm", "w");
+    fwrite(menu_htm_tbl, sizeof(char), sizeof(menu_htm_tbl), fp);
+    fclose(fp);
+
+    //window.htm
+    fp = fopen("/storage/window.htm", "w");
+    fwrite(window_htm_tbl, sizeof(char), sizeof(window_htm_tbl), fp);
+    fclose(fp);
+}
+
+static void SetI2CfromWeb(Arguments* arg, Reply* r) {
+    int result = 0;
+
+    if (arg != NULL) {
+        if (arg->argc >= 2) {
+            if ((arg->argv[0] != NULL) && (arg->argv[1] != NULL)) {
+                sprintf(i2c_setting_str_buf, "%s,%s", arg->argv[0], arg->argv[1]);
+                result = 1;
+            }
+        } else if (arg->argc == 1) {
+            if (arg->argv[0] != NULL) {
+                sprintf(i2c_setting_str_buf, "%s", arg->argv[0]);
+                result = 1;
+            }
+        } else {
+            /* Do nothing */
+        }
+        /* command analysis and execute */
+        if (result != 0) {
+            if (i2c_setting_exe(i2c_setting_str_buf) != false) {
+                r->putData<const char*>(i2c_setting_str_buf);
+            }
+        }
+    }
+}
+
+#if (SCAN_NETWORK == 1) && (NETWORK_TYPE != 3)
+static const char *sec2str(nsapi_security_t sec) {
+    switch (sec) {
+        case NSAPI_SECURITY_NONE:
+            return "None";
+        case NSAPI_SECURITY_WEP:
+            return "WEP";
+        case NSAPI_SECURITY_WPA:
+            return "WPA";
+        case NSAPI_SECURITY_WPA2:
+            return "WPA2";
+        case NSAPI_SECURITY_WPA_WPA2:
+            return "WPA/WPA2";
+        case NSAPI_SECURITY_UNKNOWN:
+        default:
+            return "Unknown";
+    }
+}
+
+static bool scan_network(WiFiInterface *wifi) {
+    WiFiAccessPoint *ap;
+    bool ret = false;
+    int i;
+    int count = 10;    /* Limit number of network arbitrary to 10 */
+
+    printf("Scan:\r\n");
+    ap = new WiFiAccessPoint[count];
+    if (ap == NULL) {
+        printf("memory error\r\n");
+        return 0;
+    }
+    count = wifi->scan(ap, count);
+    for (i = 0; i < count; i++) {
+        printf("No.%d Network: %s secured: %s BSSID: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx RSSI: %hhd Ch: %hhd\r\n",
+               i, ap[i].get_ssid(), sec2str(ap[i].get_security()),
+               ap[i].get_bssid()[0], ap[i].get_bssid()[1], ap[i].get_bssid()[2], ap[i].get_bssid()[3],
+               ap[i].get_bssid()[4], ap[i].get_bssid()[5], ap[i].get_rssi(), ap[i].get_channel());
+    }
+    printf("%d networks available.\r\n", count);
+
+    if (count > 0) {
+        char c;
+        char pass[64];
+        int select_no;
+        bool loop_break = false;;
+
+        printf("\nPlease enter the number of the network you want to connect.\r\n");
+        printf("Enter key:[0]-[%d], (If inputting the other key, it's scanned again.)\r\n", count - 1);
+        c = (uint8_t)pc.getc();
+        select_no = c - 0x30;
+        if ((select_no >= 0) && (select_no < count)) {
+            printf("[%s] is selected.\r\n", ap[select_no].get_ssid());
+            printf("Please enter the PSK.\r\n");
+            i = 0;
+            while (loop_break == false) {
+                c = (uint8_t)pc.getc();
+                switch (c) {
+                    case 0x0D:
+                        pass[i] = '\0';
+                        pc.puts("\r\n");
+                        loop_break = true;
+                        break;
+                    case 0x08:
+                        if (i > 0) {
+                            pc.puts("\b \b");
+                            i--;
+                        }
+                        break;
+                    case 0x0A:
+                        break;
+                    default:
+                        if ((i + 1) < sizeof(pass)) {
+                            pass[i] = c;
+                            i++;
+                            pc.putc(c);
+                        }
+                        break;
+                }
+            }
+            wifi->set_credentials(ap[select_no].get_ssid(), pass, ap[select_no].get_security());
+            ret = true;
+        }
+    }
+
+    delete[] ap;
+
+    return ret;
+}
+#endif
+
+static void sd_connect_task(void) {
+    int storage_type = 0;
+
+    while (1) {
+        if (storage_type == 0) {
+            if (sd.connect()) {
+                fs.unmount();
+                fs.mount(&sd);
+                storage_type = 1;
+                printf("SDBlockDevice\r\n");
+            }
+        } else {
+            if (sd.connected() == false) {
+                fs.unmount();
+                fs.mount(&romram_bd);
+                storage_type = 0;
+                printf("RomRamBlockDevice\r\n");
+            }
+        }
+        ThisThread::sleep_for(250);
+    }
+}
+
+int main(void) {
+    printf("********* PROGRAM START ***********\r\n");
+
+    mount_romramfs();   //RomRamFileSystem Mount
+
+    sdConnectTask.start(&sd_connect_task);
+
+    EasyAttach_Init(Display);
+    Jcu.SetQuality(JPEG_ENCODE_QUALITY);
+    // Interrupt callback function setting (Field end signal for recording function in scaler 0)
+    Display.Graphics_Irq_Handler_Set(DisplayBase::INT_TYPE_S0_VFIELD, 0, IntCallbackFunc_Vfield);
+    Start_Video_Camera();
+
+    RPC::add_rpc_class<RpcDigitalOut>();
+    RPCFunction rpcFunc(TerminalWrite, "TerminalWrite");
+    RPCFunction rpcSetI2C(SetI2CfromWeb, "SetI2CfromWeb");
+
+    printf("Network Setting up...\r\n");
+#if (USE_DHCP == 0)
+    network.set_dhcp(false);
+    if (network.set_network(IP_ADDRESS, SUBNET_MASK, DEFAULT_GATEWAY) != 0) { //for Static IP Address (IPAddress, NetMasks, Gateway)
+        printf("Network Set Network Error \r\n");
+    }
+#endif
+
+#if (NETWORK_TYPE >= 2)
+#if (SCAN_NETWORK == 1) && (NETWORK_TYPE != 3)
+    while (!scan_network(&network));
+#else
+    network.set_credentials(WLAN_SSID, WLAN_PSK, WLAN_SECURITY);
+#endif
+#endif
+
+    printf("\r\nConnecting...\r\n");
+    if (network.connect() != 0) {
+        printf("Network Connect Error \r\n");
+        return -1;
+    }
+    printf("MAC Address is %s\r\n", network.get_mac_address());
+    printf("IP Address is %s\r\n", network.get_ip_address());
+    printf("NetMask is %s\r\n", network.get_netmask());
+    printf("Gateway Address is %s\r\n", network.get_gateway());
+    printf("Network Setup OK\r\n");
+
+    SnapshotHandler::attach_req(&snapshot_req);
+    HTTPServerAddHandler<SnapshotHandler>("/camera"); //Camera
+    FSHandler::mount("/storage", "/");
+    HTTPServerAddHandler<FSHandler>("/");
+    HTTPServerAddHandler<RPCHandler>("/rpc");
+    HTTPServerStart(&network, 80);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs.lib	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1 @@
+https://github.com/d-kato/mbed-gr-libs/#96f9b419a3e413195479068c4b279509baa61dae

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/AlarmTimer/AlarmTimer.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,48 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/**************************************************************************//**
+* @file          AlarmTimer.h
+* @brief         AlarmTimer API
+******************************************************************************/
+
+#ifndef ALARM_TIMER_H
+#define ALARM_TIMER_H
+
+#include "mbed.h"
+
+/** A class to communicate a AlarmTimer
+ *
+ */
+class AlarmTimer {
+public:
+
+    /** Set alarm interrupt
+     *
+     * @param seconds Alarm time
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    static bool set(time_t seconds);
+
+    /** Attach a function to call when an alarm interrupt occurs
+     *
+     * @param func pointer to the function to be called
+     */
+    static void attach(Callback<void()> func);
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/AlarmTimer/TARGET_RZ_A1XX/AlarmTimer.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,112 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+
+#include "AlarmTimer.h"
+#include "rza_io_regrw.h"
+
+static Callback<void()> event;
+static bool init_end = false;
+
+#define RTC_IRQ_NUM    ARM_IRQn
+
+static void int_alarm(void) {
+    RTC.RSECAR &= ~0x80;
+    RTC.RMINAR &= ~0x80;
+    RTC.RHRAR  &= ~0x80;
+    RTC.RDAYAR &= ~0x80;
+    RTC.RMONAR &= ~0x80;
+    RTC.RCR3   &= ~0x80;
+    RTC.RCR1   &= ~0x01; // AF = 0
+    if (event) {
+        event.call();
+    }
+}
+
+static void set_alarm_int(void) {
+    if (init_end != false) {
+        return;
+    }
+    GIC_DisableIRQ(RTC_IRQ_NUM);
+    InterruptHandlerRegister(RTC_IRQ_NUM, &int_alarm);
+    GIC_SetPriority(RTC_IRQ_NUM, 5);
+    GIC_SetConfiguration(RTC_IRQ_NUM, 1);
+    GIC_EnableIRQ(RTC_IRQ_NUM);
+    init_end = true;
+}
+
+static uint8_t hex8_to_dec(uint8_t hex_val) {
+    uint32_t calc_data;
+
+    calc_data  = hex_val / 10 * 0x10;
+    calc_data += hex_val % 10;
+
+    if (calc_data > 0x99) {
+        calc_data = 0;
+    }
+
+    return (uint8_t)calc_data;
+}
+
+static uint16_t hex16_to_dec(uint16_t hex_val) {
+    uint32_t calc_data;
+
+    calc_data  =   hex_val / 1000       * 0x1000;
+    calc_data += ((hex_val / 100) % 10) * 0x100;
+    calc_data += ((hex_val / 10)  % 10) * 0x10;
+    calc_data +=   hex_val        % 10;
+
+    if (calc_data > 0x9999) {
+        calc_data = 0;
+    }
+    return (uint16_t)calc_data;
+}
+
+void AlarmTimer::attach(Callback<void()> func) {
+    event = func;
+}
+
+bool AlarmTimer::set(time_t seconds) {
+    if ((RTC.RCR2 & 0x01) == 0) {
+        return false;
+    }
+
+    struct tm *t = localtime(&seconds);
+
+    RTC.RCR1 &= ~0x08u;   // AIE = 0
+    for (int i = 0; (i < 1000) && ((RTC.RCR1 & 0x08) != 0); i++) {
+        ;
+    }
+    RTC.RCR1 &= ~0x01u;   // AF = 0
+
+    set_alarm_int();
+
+    RTC.RSECAR = 0x80 + hex8_to_dec(t->tm_sec);
+    RTC.RMINAR = 0x80 + hex8_to_dec(t->tm_min);
+    RTC.RHRAR  = 0x80 + hex8_to_dec(t->tm_hour);
+    RTC.RDAYAR = 0x80 + hex8_to_dec(t->tm_mday);
+    RTC.RMONAR = 0x80 + hex8_to_dec(t->tm_mon + 1);
+    RTC.RYRAR  = hex16_to_dec(t->tm_year + 1900);
+    RTC.RCR3   = 0x80;
+
+    RTC.RCR1 &= ~0x01u;   // AF = 0
+    RTC.RCR1 |= 0x08u;    // AIE = 1
+
+    return true;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/AlarmTimer/TARGET_RZ_A2XX/AlarmTimer.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,85 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+
+#include "AlarmTimer.h"
+#include "rza_io_regrw.h"
+
+static Callback<void()> event;
+static bool init_end = false;
+
+#define RTC_IRQ_NUM    ARM_S_IRQn
+
+static void int_alarm(void) {
+    RTC_BCNT1.BCNT0AER.BYTE = 0x00;
+    RTC_BCNT1.BCNT1AER.BYTE = 0x00;
+    RTC_BCNT1.BCNT2AER.WORD = 0x0000;
+    RTC_BCNT1.BCNT3AER.BYTE = 0x00;
+    RTC_BCNT1.RSR.BIT.AF    = 0;
+    if (event) {
+        event.call();
+    }
+}
+
+static void set_alarm_int(void) {
+    if (init_end != false) {
+        return;
+    }
+    GIC_DisableIRQ(RTC_IRQ_NUM);
+    InterruptHandlerRegister(RTC_IRQ_NUM, &int_alarm);
+    GIC_SetPriority(RTC_IRQ_NUM, 5);
+    GIC_SetConfiguration(RTC_IRQ_NUM, 1);
+    GIC_EnableIRQ(RTC_IRQ_NUM);
+    init_end = true;
+}
+
+void AlarmTimer::attach(Callback<void()> func) {
+    event = func;
+}
+
+bool AlarmTimer::set(time_t seconds) {
+    if (RTC_BCNT1.RCR2.BIT.START == 0) {
+        return false;
+    }
+
+    RTC_BCNT1.RCR1.BIT.AIE = 0;
+    for (int i = 0; (i < 1000) && (RTC_BCNT1.RCR1.BIT.AIE != 0); i++) {
+        ;
+    }
+    RTC_BCNT1.RSR.BIT.AF = 0;
+
+    set_alarm_int();
+
+    RTC_BCNT1.BCNT0AR.BYTE = (uint8_t)(seconds >>  0);
+    RTC_BCNT1.BCNT1AR.BYTE = (uint8_t)(seconds >>  8);
+    RTC_BCNT1.BCNT2AR.BYTE = (uint8_t)(seconds >> 16);
+    RTC_BCNT1.BCNT3AR.BYTE = (uint8_t)(seconds >> 24);
+
+    RTC_BCNT1.BCNT0AER.BYTE = 0xFF;
+    RTC_BCNT1.BCNT1AER.BYTE = 0xFF;
+    RTC_BCNT1.BCNT2AER.WORD = 0x00FF;
+    RTC_BCNT1.BCNT3AER.BYTE = 0xFF;
+
+    wait_ms(4);
+
+    RTC_BCNT1.RSR.BIT.AF = 0;
+    RTC_BCNT1.RCR1.BIT.AIE = 1;
+
+    return true;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/AsciiFont/AsciiFont.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,119 @@
+/* Copyright (c) 2016 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed.h"
+#include "AsciiFont.h"
+#include "ascii.h"
+
+AsciiFont::AsciiFont(uint8_t * p_buf, int width, int height, int stride, int byte_per_pixel, uint32_t const colour) : 
+    p_text_field(p_buf), max_width(width), max_height(height), buf_stride(stride), pixel_num(byte_per_pixel), background_colour(colour) {
+    
+}
+
+void AsciiFont::Erase() {
+    Erase(background_colour, 0, 0, max_width, max_height);
+}
+
+void AsciiFont::Erase(uint32_t const colour) {
+    Erase(colour, 0, 0, max_width, max_height);
+}
+
+void AsciiFont::Erase(uint32_t const colour, int x, int y, int width, int height) {
+    int idx_base;
+    int wk_idx, i, j ,k;
+
+    background_colour = colour;
+    if ((x + width) > max_width) {
+        width = max_width - x;
+    }
+    if ((y + height) > max_height) {
+        height = max_height - y;
+    }
+    idx_base = (x * pixel_num) + (buf_stride * y);
+    for (i = 0; i < height; i++) {
+        wk_idx = idx_base + (buf_stride * i);
+        for (j = 0; j < width; j++) {
+            for (k = (pixel_num - 1); k >= 0; k--) {
+                p_text_field[wk_idx++] = (uint8_t)(background_colour >> (8 * k));
+            }
+        }
+    }
+}
+
+int AsciiFont::DrawStr(const char * str, int x, int y, uint32_t const colour, int font_size, uint16_t const max_char_num) {
+    int char_num = 0;
+
+    if ((str == NULL) || (font_size <= 0)) {
+        return 0;
+    }
+    while ((*str != '\0') && (char_num < max_char_num)) {
+        if (DrawChar(*str, x, y, colour, font_size) == false) {
+            break;
+        }
+        str++;
+        x += CHAR_PIX_WIDTH * font_size;
+        char_num++;
+    }
+    return char_num;
+}
+
+bool AsciiFont::DrawChar(char c, int x, int y, uint32_t const colour, int font_size) {
+    int idx_base;
+    int idx_y = 0;
+    int wk_idx, i, j ,k, fw, fh;
+    char * p_pattern;
+    uint8_t mask = 0x80;
+    uint32_t wk_colour;
+
+    if (font_size <= 0) {
+        return false;
+    }
+    if ((x + (CHAR_PIX_WIDTH * font_size)) > max_width) {
+        return false;
+    }
+    if ((y + (CHAR_PIX_HEIGHT * font_size)) > max_height) {
+        return false;
+    }
+
+    if ((c >= 0x20) && (c <= 0x7e)) {
+        p_pattern = (char *)&g_ascii_table[c - 0x20][0];
+    } else {
+        p_pattern = (char *)&g_ascii_table[10][0]; /* '*' */
+    }
+    idx_base = (x * pixel_num) + (buf_stride * y);
+
+    /* Drawing */
+    for (i = 0; i < CHAR_PIX_HEIGHT; i++) {
+        for (fh = 0; fh < font_size; fh++) {
+            wk_idx = idx_base + (buf_stride * idx_y);
+            for (j = 0; j < CHAR_PIX_WIDTH; j++) {
+                if (p_pattern[j] & mask) {
+                    wk_colour = colour;
+                } else {
+                    wk_colour = background_colour;
+                }
+                for (fw = 0; fw < font_size; fw++) {
+                    for (k = (pixel_num - 1); k >= 0; k--) {
+                        p_text_field[wk_idx++] = (uint8_t)(wk_colour >> (8 * k));
+                    }
+                }
+            }
+            idx_y++;
+        }
+        mask = (uint8_t)(mask >> 1);
+    }
+    return true;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/AsciiFont/AsciiFont.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,147 @@
+/* Copyright (c) 2016 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**************************************************************************//**
+* @file          AsciiFont.h
+* @brief         AsciiFont API
+******************************************************************************/
+
+#ifndef ASCII_FONT_H
+#define ASCII_FONT_H
+
+#include "mbed.h"
+
+/** Draw the character of the ASCII code.
+ *
+ * Example
+ * @code
+ * #include "mbed.h"
+ * #include "AsciiFont.h"
+ * 
+ * #define WIDTH           (12)
+ * #define HEIGHT          (16)
+ * #define BYTE_PER_PIXEL  (1u)
+ * #define STRIDE          (((WIDTH * BYTE_PER_PIXEL) + 7u) & ~7u) //multiple of 8
+ * 
+ * uint8_t text_field[STRIDE * HEIGHT];
+ * 
+ * //for debug
+ * void print_text_field() {
+ *     int idx = 0;
+ * 
+ *     for (int i = 0; i < HEIGHT; i++) {
+ *         for (int j = 0; j < STRIDE; j++) {
+ *             printf("%02x", text_field[idx++]);
+ *         }
+ *         printf("\r\n");
+ *     }
+ *     printf("\r\n");
+ * }
+ * 
+ * int main() {
+ *     AsciiFont ascii_font(text_field, WIDTH, HEIGHT, STRIDE, BYTE_PER_PIXEL);
+ * 
+ *     ascii_font.Erase(0xcc);
+ *     ascii_font.DrawStr("AB", 0, 0, 0x11, 1);
+ *     ascii_font.DrawChar('C', AsciiFont::CHAR_PIX_WIDTH,
+ *                         AsciiFont::CHAR_PIX_HEIGHT, 0x22, 1);
+ *     print_text_field(); //debug print
+ * 
+ *     ascii_font.Erase();
+ *     ascii_font.DrawStr("D", 0, 0, 0xef, 2);
+ *     print_text_field(); //debug print
+ * 
+ *     ascii_font.Erase(0x11, 6, 0, 6, 8);
+ *     print_text_field(); //debug print
+ * }
+ * @endcode
+ */
+
+class AsciiFont {
+public:
+
+    /** Constructor: Initializes AsciiFont.
+     *
+     * @param p_buf Text field address
+     * @param width Text field width
+     * @param height Text field height
+     * @param stride Buffer stride
+     * @param colour Background color
+     * @param byte_per_pixel Byte per pixel
+     */
+    AsciiFont(uint8_t * p_buf, int width, int height, int stride, int byte_per_pixel, uint32_t const colour = 0);
+
+    /** Erase text field
+     *
+     */
+    void Erase();
+
+    /** Erase text field
+     *
+     * @param colour Background color
+     */
+    void Erase(uint32_t const colour);
+
+    /** Erase text field
+     *
+     * @param colour Background color
+     * @param x Erase start position of x coordinate
+     * @param y Erase start position of y coordinate
+     * @param width Erase field width
+     * @param height Erase field height
+     */
+    void Erase(uint32_t const colour, int x, int y, int width, int height);
+
+    /** Draw a string
+     *
+     * @param str String
+     * @param x Drawing start position of x coordinate
+     * @param y Drawing start position of y coordinate
+     * @param color Font color
+     * @param font_size Font size (>=1)
+     * @param max_char_num The maximum number of characters
+     * @return The drawn number of characters
+     */
+    int DrawStr(const char * str, int x, int y, uint32_t const colour, int font_size = 1, uint16_t const max_char_num = 0xffff);
+
+    /** Draw a character
+     *
+     * @param x Drawing start position of x coordinate
+     * @param y Drawing start position of y coordinate
+     * @param color Font color
+     * @param font_size Font size (>=1)
+     * @return true if successfull
+     */
+    bool DrawChar(char c, int x, int y, uint32_t const colour, int font_size = 1);
+
+    /** The pixel width of a character. (font_size=1)
+     *
+     */
+    static const int CHAR_PIX_WIDTH  = 6;
+
+    /** The pixel height of a character. (font_size=1)
+     *
+     */
+    static const int CHAR_PIX_HEIGHT = 8;
+
+private:
+    uint8_t * p_text_field;
+    int max_width;
+    int max_height;
+    int buf_stride;
+    int pixel_num;
+    uint32_t background_colour;
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/AsciiFont/ascii.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,149 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name     : ascii.c
+* Device(s)     : RZ/A1H (R7S721001)
+* Tool-Chain    : GNUARM-NONEv14.02-EABI
+* H/W Platform  : RSK+RZA1H CPU Board
+* Description   : Defines ascii font table
+*******************************************************************************/
+/*******************************************************************************
+* History       : DD.MM.YYYY Version Description
+*               : 21.10.2014 1.00
+*******************************************************************************/
+
+/*******************************************************************************
+* User Includes (Project Level Includes)
+*******************************************************************************/
+/* ASCII header */
+#include "ascii.h"
+
+/*******************************************************************************
+* Global Tables
+*******************************************************************************/
+/* Bytes after this pre-processor are 1-byte aligned */
+#pragma pack(1)
+
+const char g_ascii_table[][6] =
+{
+  { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},      /* ' '*/
+  { 0x00, 0x00, 0x79, 0x00, 0x00, 0x00},      /* ! */
+  { 0x00, 0x70, 0x00, 0x70, 0x00, 0x00},      /* " */
+  { 0x22, 0x7F, 0x22, 0x7F, 0x22, 0x00},      /* # */
+  { 0x12, 0x2A, 0x7F, 0x2A, 0x24, 0x00},      /* $ */
+  { 0x62, 0x64, 0x08, 0x13, 0x23, 0x00},      /* % */
+  { 0x36, 0x49, 0x55, 0x22, 0x05, 0x00},      /* & */
+  { 0x00, 0x00, 0x60, 0x00, 0x00, 0x00},      /* ' */
+  { 0x00, 0x1C, 0x22, 0x41, 0x00, 0x00},      /* ( */
+  { 0x00, 0x41, 0x22, 0x1C, 0x00, 0x00},      /* ) */
+  { 0x24, 0x18, 0x7E, 0x18, 0x24, 0x00},      /* * */
+  { 0x08, 0x08, 0x3E, 0x08, 0x08, 0x00},      /* + */
+  { 0x00, 0x05, 0x06, 0x00, 0x00, 0x00},      /* , */
+  { 0x08, 0x08, 0x08, 0x08, 0x08, 0x00},      /* - */
+  { 0x00, 0x03, 0x03, 0x00, 0x00, 0x00},      /* . */
+  { 0x02, 0x04, 0x08, 0x10, 0x20, 0x00},      /* / */
+  { 0x3E, 0x45, 0x49, 0x51, 0x3E, 0x00},      /* 0 */
+  { 0x00, 0x21, 0x7F, 0x01, 0x00, 0x00},      /* 1 */
+  { 0x21, 0x43, 0x45, 0x49, 0x71, 0x00},      /* 2 */
+  { 0x42, 0x41, 0x51, 0x69, 0x46, 0x00},      /* 3 */
+  { 0x0C, 0x14, 0x24, 0x7F, 0x04, 0x00},      /* 4 */
+  { 0x72, 0x51, 0x51, 0x51, 0x4E, 0x00},      /* 5 */
+  { 0x1E, 0x29, 0x49, 0x49, 0x06, 0x00},      /* 6 */
+  { 0x40, 0x47, 0x48, 0x50, 0x60, 0x00},      /* 7 */
+  { 0x36, 0x49, 0x49, 0x49, 0x36, 0x00},      /* 8 */
+  { 0x30, 0x49, 0x49, 0x4A, 0x3C, 0x00},      /* 9 */
+  { 0x00, 0x66, 0x66, 0x00, 0x00, 0x00},      /* : */
+  { 0x00, 0x35, 0x36, 0x00, 0x00, 0x00},      /* ; */
+  { 0x08, 0x14, 0x22, 0x41, 0x00, 0x00},      /* < */
+  { 0x14, 0x14, 0x14, 0x14, 0x14, 0x00},      /* = */
+  { 0x00, 0x41, 0x22, 0x14, 0x08, 0x00},      /* > */
+  { 0x20, 0x40, 0x45, 0x48, 0x30, 0x00},      /* ? */
+  { 0x38, 0x45, 0x5D, 0x59, 0x3E, 0x00},      /* @ */
+  { 0x1F, 0x24, 0x44, 0x24, 0x1F, 0x00},      /* A */
+  { 0x7F, 0x49, 0x49, 0x49, 0x36, 0x00},      /* B */
+  { 0x3E, 0x41, 0x41, 0x41, 0x22, 0x00},      /* C */
+  { 0x7F, 0x41, 0x41, 0x22, 0x1C, 0x00},      /* D */
+  { 0x7F, 0x49, 0x49, 0x49, 0x41, 0x00},      /* E */
+  { 0x7F, 0x48, 0x48, 0x48, 0x40, 0x00},      /* F */
+  { 0x3E, 0x41, 0x49, 0x49, 0x2F, 0x00},      /* G */
+  { 0x7F, 0x08, 0x08, 0x08, 0x7F, 0x00},      /* H */
+  { 0x00, 0x41, 0x7F, 0x41, 0x00, 0x00},      /* I */
+  { 0x02, 0x01, 0x41, 0x7E, 0x40, 0x00},      /* J */
+  { 0x7F, 0x08, 0x14, 0x22, 0x41, 0x00},      /* K */
+  { 0x7F, 0x01, 0x01, 0x01, 0x01, 0x00},      /* L */
+  { 0x7F, 0x20, 0x18, 0x20, 0x7F, 0x00},      /* M */
+  { 0x7F, 0x10, 0x08, 0x04, 0x7F, 0x00},      /* N */
+  { 0x3E, 0x41, 0x41, 0x41, 0x3E, 0x00},      /* O */
+  { 0x7F, 0x48, 0x48, 0x48, 0x30, 0x00},      /* P */
+  { 0x3E, 0x41, 0x45, 0x42, 0x3D, 0x00},      /* Q */
+  { 0x7F, 0x48, 0x4C, 0x4A, 0x31, 0x00},      /* R */
+  { 0x32, 0x49, 0x49, 0x49, 0x26, 0x00},      /* S */
+  { 0x40, 0x40, 0x7F, 0x40, 0x40, 0x00},      /* T */
+  { 0x7E, 0x01, 0x01, 0x01, 0x7E, 0x00},      /* U */
+  { 0x7C, 0x02, 0x01, 0x02, 0x7C, 0x00},      /* V */
+  { 0x7E, 0x01, 0x0E, 0x01, 0x7E, 0x00},      /* W */
+  { 0x63, 0x14, 0x08, 0x14, 0x63, 0x00},      /* X */
+  { 0x70, 0x08, 0x07, 0x08, 0x70, 0x00},      /* Y */
+  { 0x43, 0x45, 0x49, 0x51, 0x61, 0x00},      /* Z */
+  { 0x00, 0x7F, 0x41, 0x00, 0x00, 0x00},      /* [ */
+  { 0x20, 0x10, 0x08, 0x04, 0x02, 0x00},      /* "\" */
+  { 0x00, 0x00, 0x41, 0x7F, 0x00, 0x00},      /* ] */
+  { 0x00, 0x20, 0x40, 0x20, 0x00, 0x00},      /* ^ */
+  { 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},      /* _ */
+  { 0x00, 0x40, 0x20, 0x00, 0x00, 0x00},      /* ' */
+  { 0x02, 0x15, 0x15, 0x0F, 0x01, 0x00},      /* a */
+  { 0x00, 0x7F, 0x11, 0x11, 0x0E, 0x00},      /* b */
+  { 0x00, 0x0E, 0x11, 0x11, 0x11, 0x00},      /* c */
+  { 0x0E, 0x11, 0x11, 0x7F, 0x00, 0x00},      /* d */
+  { 0x0E, 0x15, 0x15, 0x15, 0x0C, 0x00},      /* e */
+  { 0x00, 0x10, 0x3F, 0x50, 0x50, 0x00},      /* f */
+  { 0x08, 0x15, 0x15, 0x15, 0x1E, 0x00},      /* g */
+  { 0x00, 0x7F, 0x10, 0x10, 0x0F, 0x00},      /* h */
+  { 0x00, 0x11, 0x5F, 0x01, 0x00, 0x00},      /* i */
+  { 0x02, 0x01, 0x01, 0x5E, 0x00, 0x00},      /* j */
+  { 0x00, 0x7F, 0x04, 0x0A, 0x11, 0x00},      /* k */
+  { 0x00, 0x41, 0x7F, 0x01, 0x00, 0x00},      /* l */
+  { 0x1F, 0x10, 0x0F, 0x10, 0x0F, 0x00},      /* m */
+  { 0x00, 0x1F, 0x10, 0x10, 0x0F, 0x00},      /* n */
+  { 0x0E, 0x11, 0x11, 0x11, 0x0E, 0x00},      /* 0 */
+  { 0x1F, 0x14, 0x14, 0x14, 0x08, 0x00},      /* p */
+  { 0x08, 0x14, 0x14, 0x14, 0x1F, 0x00},      /* q */
+  { 0x00, 0x1F, 0x08, 0x10, 0x10, 0x00},      /* r */
+  { 0x09, 0x15, 0x15, 0x15, 0x12, 0x00},      /* s */
+  { 0x00, 0x10, 0x7E, 0x11, 0x01, 0x00},      /* t */
+  { 0x00, 0x1E, 0x01, 0x01, 0x1F, 0x00},      /* u */
+  { 0x1C, 0x02, 0x01, 0x02, 0x1C, 0x00},      /* v */
+  { 0x1E, 0x01, 0x06, 0x01, 0x1E, 0x00},      /* w */
+  { 0x11, 0x0A, 0x04, 0x0A, 0x11, 0x00},      /* x */
+  { 0x18, 0x05, 0x05, 0x1E, 0x00, 0x00},      /* y */
+  { 0x11, 0x13, 0x15, 0x19, 0x11, 0x00},      /* z */
+  { 0x00, 0x08, 0x36, 0x41, 0x00, 0x00},      /* { */
+  { 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00},      /* | */
+  { 0x00, 0x41, 0x36, 0x08, 0x00, 0x00},      /* } */
+  { 0x00, 0x20, 0x40, 0x20, 0x40, 0x00}       /* ~ */
+  };
+
+/* Bytes after this pre-processor are 4-byte aligned */
+#pragma pack(4)
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/AsciiFont/ascii.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,49 @@
+/******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name     : ascii.h
+* Device(s)     : RZ/A1H (R7S721001)
+* Tool-Chain    : GNUARM-NONEv14.02-EABI
+* H/W Platform  : RSK+RZA1H CPU Board
+* Description  : This Header file contains the Macro Definitions & prototypes
+*                for the functions used in lcd.c
+*******************************************************************************/
+/*******************************************************************************
+* History       : DD.MM.YYYY Version Description
+*               : 21.10.2014 1.00
+*******************************************************************************/
+
+/* Multiple inclusion prevention macro */
+#ifndef ASCII_H
+#define ASCII_H
+
+/******************************************************************************
+Macro Definitions
+******************************************************************************/
+extern const char g_ascii_table[][6];
+
+/* ASCII_H */
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/DeepStandby/DeepStandby.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,78 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/**************************************************************************//**
+* @file          DeepStandby.h
+* @brief         DeepStandby API
+******************************************************************************/
+
+#ifndef DEEP_STANDBY_H
+#define DEEP_STANDBY_H
+
+#include "mbed.h"
+
+/** A class to communicate a DeepStandby
+ *
+ */
+class DeepStandby {
+public:
+
+    typedef struct {
+        bool button0;       /*!< Works with GR_LYCHEE, RZ_A2M_EVB and SEMB1402. */
+        bool button1;       /*!< Works with GR_LYCHEE, RZ_A2M_EVB and RZ_A2M_SBEV. */
+        bool rtc;           /*!< Works with RZ_A1, GR_LYCHEE, RZ_A2M_EVB, RZ_A2M_SBEV and SEMB1402. */
+    } cancel_src_simple_t;
+
+    /** Set deep standby mode
+     *
+     * @param src     Factors that cancel deep standby.
+     */
+    static void SetDeepStandbySimple(cancel_src_simple_t *src);
+
+    /** Get deep standby cancel source
+     *
+     * @param src     Factor that canceled deep standby.
+     * @return        true : Deep standby canceled.  false : Reset start.
+     */
+    static bool GetCancelSourceSimple(cancel_src_simple_t *src);
+
+
+
+    typedef struct {
+        uint8_t  rramkp;    /*!< Value of RRAMKP register */
+        uint16_t dsssr;     /*!< Value of DSSSR register */
+        uint16_t dsesr;     /*!< Value of DSESR register */
+        uint16_t usbdsssr;  /*!< Value of USBDSSSR register (Used only with RZ/A2M) */
+    } cancel_src_direct_t;
+
+    /** Set deep standby mode
+     *
+     * @param src     Factors that cancel deep standby.
+     */
+    static void SetDeepStandbyDirect(cancel_src_direct_t *src);
+
+    /** Get deep standby cancel source
+     *
+     * @param dsfr    Value of DSFR register
+     * @param usbdsfr Value of USBDSFR register
+     * @return        true : Deep standby canceled.  false : Reset start.
+     */
+    static bool GetCancelSourceDirect(uint16_t *dsfr, uint8_t *usbdsfr);
+
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/DeepStandby/TARGET_RZ_A1XX/DeepStandby.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,188 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+
+#include "DeepStandby.h"
+#include "cpg_iobitmask.h"
+
+#if defined(TARGET_RZ_A1H)
+#define CANCEL_SRC_BIT_BUTTON0  (0)       // Not supported (P6_0)
+#define CANCEL_SRC_BIT_BUTTON1  (0)       // Not supported
+#elif defined(TARGET_GR_LYCHEE)
+#define CANCEL_SRC_BIT_BUTTON0  (1 << 9)  // P7_2
+#define CANCEL_SRC_BIT_BUTTON1  (1 << 4)  // P7_3
+#else
+#warning "This board is not supported."
+#define CANCEL_SRC_BIT_BUTTON0  (0)       // Not supported
+#define CANCEL_SRC_BIT_BUTTON1  (0)       // Not supported
+#endif
+#define CANCEL_SRC_BIT_RTC      (1 << 6)  // RTCAR
+
+void DeepStandby::SetDeepStandbySimple(cancel_src_simple_t *src)
+{
+    cancel_src_direct_t src_direct;
+
+    if (src == NULL) {
+        return;
+    }
+
+    src_direct.rramkp   = 0x0E;    // RRAMKP1, RRAMKP2, RRAMKP3
+    src_direct.dsssr    = 0x0000;
+    src_direct.dsesr    = 0x0000;
+    src_direct.usbdsssr = 0x0000;
+
+    if (src->button0) {
+        src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON0;
+    }
+    if (src->button1) {
+        src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON1;
+    }
+    if (src->rtc) {
+        src_direct.dsssr |= CANCEL_SRC_BIT_RTC;
+    }
+
+    SetDeepStandbyDirect(&src_direct);
+}
+
+
+void DeepStandby::SetDeepStandbyDirect(cancel_src_direct_t *src)
+{
+    volatile uint32_t dummy_32;
+    volatile uint16_t dummy_16;
+    volatile uint8_t dummy_8;
+
+    if (src == NULL) {
+        return;
+    }
+
+    // 1. Set the standby_mode_en bit of the power control register in the PL310 to 1.
+    L2C.REG15_POWER_CTRL = 0x00000001uL;
+    dummy_32 = L2C.REG15_POWER_CTRL;
+
+    // 2. Set the RRAMKP3 to RRAMKP0 bits in RRAMKP for the corresponding on-chip data-retention RAM area
+    //    that must be retained. Transfer the programs to be retained to the specified areas of the on-chip
+    //    data-retention RAM.
+    CPG.RRAMKP = src->rramkp;
+    dummy_8 = CPG.RRAMKP;
+
+    // 3. Set the RAMBOOT and EBUSKEEPE bits in DSCTR to specify the activation method for returning from
+    //    deep standby mode and to select whether the external memory control pin status is retained or not.
+    CPG.DSCTR = 0;                 // Activation Method : External memory
+    dummy_8 = CPG.DSCTR;
+
+    // 4. When canceling deep standby mode by an interrupt, set the corresponding bit in DSSSR to select
+    //    the pin or source to cancel deep standby mode. In this case, specify the input signal detection
+    //    mode for the selected pin with the corresponding bit in DSESR.
+    CPG.DSSSR = src->dsssr;
+    dummy_16 = CPG.DSSSR;
+    CPG.DSESR = src->dsesr;
+    dummy_16 = CPG.DSESR;
+
+    // 5. Execute read and write of an arbitrary but the same address for each page in the on-chip data-
+    //    retention RAM area. When this is not executed, data last written may not be written to the on-chip
+    //    data-retention RAM. If there is a write to the on-chip data-retention RAM after this time, execute
+    //    this processing after the last write to the on-chip dataretention RAM.
+    L1C_CleanInvalidateDCacheAll();  // Clean and invalidate the whole data cache.
+
+    // On-Chip Data Retention RAM   Page 1 of bank 0
+    dummy_32 = *((uint32_t *)0x20004000);  // Read
+    *((uint32_t *)0x20004000) = dummy_32;  // Write
+
+    // On-Chip Data Retention RAM   Page 2 of bank 0
+    dummy_32 = *((uint32_t *)0x20008000);  // Read
+    *((uint32_t *)0x20008000) = dummy_32;  // Write
+
+    // On-Chip Data Retention RAM   Page 3 of bank 0
+    dummy_32 = *((uint32_t *)0x20010000);  // Read
+    *((uint32_t *)0x20010000) = dummy_32;  // Write
+
+    L1C_CleanDCacheAll();  // Clean the whole data cache.
+
+    // 6. Set the STBY and DEEP bits in the STBCR1 register to 1, and then read this register.
+    CPG.STBCR1 = CPG_STBCR1_DEEP | CPG_STBCR1_STBY; // deep standby mode
+    dummy_8 = CPG.STBCR1;
+
+    // 7. Clear the flag in the DSFR register.
+    dummy_16 = CPG.DSFR;
+    CPG.DSFR = 0;
+    dummy_16 = CPG.DSFR;
+
+    // 8. Set the CPU interface control register (ICCICR) of the interrupt controller to 0 so that the CPU
+    //    is not notified of interrupts other than NMIs. Then, read the ICCICR register.
+    INTC.ICCICR = 0;
+    dummy_32 = INTC.ICCICR;
+
+    // Compiler warning measures
+    (void)dummy_32;
+    (void)dummy_16;
+    (void)dummy_8;
+
+    // Execute the WFI instruction
+    while (1) {
+        __WFI();
+    }
+}
+
+bool DeepStandby::GetCancelSourceSimple(cancel_src_simple_t *src)
+{
+    volatile uint16_t dsfr = CPG.DSFR;
+
+    if (dsfr == 0x0000) {
+        return false;
+    }
+
+    if (src != NULL) {
+        if (dsfr & CANCEL_SRC_BIT_BUTTON0) {
+            src->button0 = true;
+        } else {
+            src->button0 = false;
+        }
+        if (dsfr & CANCEL_SRC_BIT_BUTTON1) {
+            src->button1 = true;
+        } else {
+            src->button1 = false;
+        }
+        if (dsfr & CANCEL_SRC_BIT_RTC) {
+            src->rtc = true;
+        } else {
+            src->rtc = false;
+        }
+    }
+
+    return true;
+}
+
+bool DeepStandby::GetCancelSourceDirect(uint16_t *dsfr, uint8_t *usbdsfr)
+{
+    volatile uint16_t wk_dsfr = CPG.DSFR;
+
+    if (wk_dsfr == 0x0000) {
+        return false;
+    }
+
+    if (dsfr != NULL) {
+        *dsfr = wk_dsfr;
+    }
+
+    if (usbdsfr != NULL) {
+        *usbdsfr = 0x00;
+    }
+
+    return true;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/DeepStandby/TARGET_RZ_A2XX/DeepStandby.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,205 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+
+#include "DeepStandby.h"
+
+#if defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF)
+#define CANCEL_SRC_BIT_BUTTON0  (1 << 11) // PJ_1
+#define CANCEL_SRC_BIT_BUTTON1  (1 << 8)  // NMI
+#elif defined(TARGET_RZ_A2M_SBEV)
+#define CANCEL_SRC_BIT_BUTTON0  (0)       // Not supported (PC_5)
+#define CANCEL_SRC_BIT_BUTTON1  (1 << 8)  // NMI
+#elif defined(TARGET_SEMB1402)
+#define CANCEL_SRC_BIT_BUTTON0  (1 << 3)  // PE_1
+#define CANCEL_SRC_BIT_BUTTON1  (0)       // Not supported (PE_0)
+#else
+#warning "This board is not supported."
+#define CANCEL_SRC_BIT_BUTTON0  (0)       // Not supported
+#define CANCEL_SRC_BIT_BUTTON1  (0)       // Not supported
+#endif
+#define CANCEL_SRC_BIT_RTC      (1 << 7)  // RTCAR1
+
+void DeepStandby::SetDeepStandbySimple(cancel_src_simple_t *src)
+{
+    cancel_src_direct_t src_direct;
+
+    if (src == NULL) {
+        return;
+    }
+
+    src_direct.rramkp   = 0x0E;    // RRAMKP1, RRAMKP2, RRAMKP3
+    src_direct.dsssr    = 0x0000;
+    src_direct.dsesr    = 0x0000;
+    src_direct.usbdsssr = 0x0000;
+
+    if (src->button0) {
+        src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON0;
+    }
+    if (src->button1) {
+        src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON1;
+    }
+    if (src->rtc) {
+        src_direct.dsssr |= CANCEL_SRC_BIT_RTC;
+    }
+
+    SetDeepStandbyDirect(&src_direct);
+}
+
+void DeepStandby::SetDeepStandbyDirect(cancel_src_direct_t *src)
+{
+    volatile uint32_t dummy_32;
+    volatile uint16_t dummy_16;
+    volatile uint8_t dummy_8;
+
+    if (src == NULL) {
+        return;
+    }
+
+    // 1. Set the standby_mode_en bit of the power control register in the PL310 to 1.
+    pl310.REG15_POWER_CTRL.BIT.standby_mode_en = 1;
+    dummy_32 = pl310.REG15_POWER_CTRL.LONG;
+
+    // 2. Set the RRAMKP3 to RRAMKP0 bits in RRAMKP for the corresponding on-chip data-retention RAM area
+    //    that must be retained. Transfer the programs to be retained to the specified areas of the on-chip
+    //    data-retention RAM.
+    PMG.RRAMKP.BYTE = src->rramkp;
+    dummy_8 = PMG.RRAMKP.BYTE;
+
+    // 3. Set the RAMBOOT and EBUSKEEPE bits in DSCTR to specify the activation method for returning from
+    //    deep standby mode and to select whether the external memory control pin status is retained or not.
+
+    // Activation Method : External memory
+    PMG.DSCTR.BIT.RAMBOOT   = 0;
+    PMG.DSCTR.BIT.EBUSKEEPE = 0;
+    dummy_8 = PMG.DSCTR.BYTE;
+
+    // 4. When canceling deep standby mode by an interrupt, set the corresponding bit in DSSSR to select
+    //    the pin or source to cancel deep standby mode. In this case, specify the input signal detection
+    //    mode for the selected pin with the corresponding bit in DSESR.
+    PMG.DSSSR.WORD = src->dsssr;
+    dummy_16 = PMG.DSSSR.WORD;
+
+    PMG.DSESR.WORD = src->dsesr;
+    dummy_16 = PMG.DSESR.WORD;
+
+    PMG.USBDSSSR.BYTE = src->usbdsssr;
+    dummy_8 = PMG.USBDSSSR.BYTE;
+    PMG.DSCNT.BIT.CNTD = 0;
+    dummy_16 = PMG.DSCNT.WORD;
+
+    // 5. Execute read and write of an arbitrary but the same address for each page in the on-chip data-
+    //    retention RAM area. When this is not executed, data last written may not be written to the on-chip
+    //    data-retention RAM. If there is a write to the on-chip data-retention RAM after this time, execute
+    //    this processing after the last write to the on-chip dataretention RAM.
+    L1C_CleanInvalidateDCacheAll();  // Clean and invalidate the whole data cache.
+
+    // On-Chip Data Retention RAM   Page 1
+    dummy_32 = *((uint32_t *)0x80004000);  // Read
+    *((uint32_t *)0x80004000) = dummy_32;  // Write
+
+    // On-Chip Data Retention RAM   Page 2
+    dummy_32 = *((uint32_t *)0x80008000);  // Read
+    *((uint32_t *)0x80008000) = dummy_32;  // Write
+
+    // On-Chip Data Retention RAM   Page 3
+    dummy_32 = *((uint32_t *)0x80010000);  // Read
+    *((uint32_t *)0x80010000) = dummy_32;  // Write
+
+    L1C_CleanDCacheAll();  // Clean the whole data cache.
+
+    // 6. Set the STBY and DEEP bits in the STBCR1 register to 1, and then read this register.
+
+    // deep standby mode
+    CPG.STBCR1.BIT.DEEP = 1;
+    CPG.STBCR1.BIT.STBY = 1;
+    dummy_8 = CPG.STBCR1.BYTE;
+
+    // 7. Clear the flag in the DSFR register.
+    dummy_16 = PMG.DSFR.WORD;
+    PMG.DSFR.WORD = 0;
+    dummy_16 = PMG.DSFR.WORD;
+    dummy_8 = PMG.USBDSFR.BYTE;
+    PMG.USBDSFR.BYTE = 0;
+    dummy_8 = PMG.USBDSFR.BYTE;
+
+    // 8. Set the CPU interface control register (GICC_CTLR) of the interrupt controller to 0 so that the CPU
+    //    is not notified of interrupts other than NMIs. Then, read the GICC_CTLR register.
+    INTC.GICC_CTLR.LONG = 0;
+    dummy_32 = INTC.GICC_CTLR.LONG;
+
+    // Compiler warning measures
+    (void)dummy_32;
+    (void)dummy_16;
+    (void)dummy_8;
+
+    // Execute the WFI instruction
+    while (1) {
+        __WFI();
+    }
+}
+
+bool DeepStandby::GetCancelSourceSimple(cancel_src_simple_t *src)
+{
+    volatile uint16_t dsfr = PMG.DSFR.WORD;
+
+    if (dsfr == 0x0000) {
+        return false;
+    }
+
+    if (src != NULL) {
+        if (dsfr & CANCEL_SRC_BIT_BUTTON0) {
+            src->button0 = true;
+        } else {
+            src->button0 = false;
+        }
+        if (dsfr & CANCEL_SRC_BIT_BUTTON1) {
+            src->button1 = true;
+        } else {
+            src->button1 = false;
+        }
+        if (dsfr & CANCEL_SRC_BIT_RTC) {
+            src->rtc = true;
+        } else {
+            src->rtc = false;
+        }
+    }
+
+    return true;
+}
+
+bool DeepStandby::GetCancelSourceDirect(uint16_t *dsfr, uint8_t *usbdsfr)
+{
+    volatile uint16_t wk_dsfr = PMG.DSFR.WORD;
+    volatile uint8_t wk_usbdsfr = PMG.USBDSFR.BYTE;
+
+    if ((wk_dsfr == 0x0000) && (wk_usbdsfr == 0x00)) {
+        return false;
+    }
+
+    if (dsfr != NULL) {
+        *dsfr = wk_dsfr;
+    }
+
+    if (usbdsfr != NULL) {
+        *usbdsfr = wk_usbdsfr;
+    }
+
+    return true;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/DisplayApp/DisplayApp.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,246 @@
+/* Copyright (c) 2016 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed.h"
+#include "DisplayApp.h"
+
+void DisplayApp::display_app_process() {
+    int data;
+    int pos_x_wk;
+    int pos_wk;
+
+    PcApp.connect();
+
+    while (!PcApp.configured()) {
+        ThisThread::sleep_for(100);
+    }
+
+    while (1) {
+        if (PcApp.readable()) {
+            data = PcApp.getc();
+            if (data == '{') {
+                pos_seq = POS_SEQ_START;
+            } else if (data == 'X') {
+                if (pos_seq == POS_SEQ_START) {
+                    pos_seq = POS_SEQ_X;
+                } else {
+                    pos_seq = POS_SEQ_INIT;
+                }
+            } else if (data == 'Y') {
+                if (pos_seq == POS_SEQ_C) {
+                    pos_seq = POS_SEQ_Y;
+                } else {
+                    pos_seq = POS_SEQ_INIT;
+                }
+            } else if (data == '=') {
+                if (pos_seq == POS_SEQ_X) {
+                    pos_seq = POS_SEQ_X_POS;
+                    pos_wk = 0;
+                } else if (pos_seq == POS_SEQ_Y) {
+                    pos_seq = POS_SEQ_Y_POS;
+                    pos_wk = 0;
+                } else {
+                    pos_seq = POS_SEQ_INIT;
+                }
+            } else if (data == '-') {
+                if (pos_seq == POS_SEQ_X_POS) {
+                    pos_seq = POS_SEQ_X_M;
+                } else if (pos_seq == POS_SEQ_Y_POS) {
+                    pos_seq = POS_SEQ_Y_M;
+                } else {
+                    pos_seq = POS_SEQ_INIT;
+                }
+            } else if ((data >= '0') && (data <= '9')) {
+                if ((pos_seq == POS_SEQ_X_POS) || (pos_seq == POS_SEQ_Y_POS)) {
+                    pos_wk = (pos_wk * 10) + (data - '0');
+                } else if ((pos_seq == POS_SEQ_X_M) && (data == '1')) {
+                    pos_wk = -1;
+                } else if ((pos_seq == POS_SEQ_Y_M) && (data == '1')) {
+                    pos_wk = -1;
+                } else {
+                    pos_seq = POS_SEQ_INIT;
+                }
+            } else if (data == ',') {
+                if ((pos_seq == POS_SEQ_X_POS) || (pos_seq == POS_SEQ_X_M)) {
+                    pos_x_wk = pos_wk;
+                    pos_seq = POS_SEQ_C;
+                } else {
+                    pos_seq = POS_SEQ_INIT;
+                }
+            } else if (data == '}') {
+                if ((pos_seq == POS_SEQ_Y_POS) || (pos_seq == POS_SEQ_Y_M)) {
+                    pos_seq = POS_SEQ_END;
+                    if ((pos_x != pos_x_wk) || (pos_y != pos_wk)) {
+                        pos_x = pos_x_wk;
+                        pos_y = pos_wk;
+                        if (event) {
+                            event.call();
+                        }
+                    }
+                } else {
+                    pos_seq = POS_SEQ_INIT;
+                }
+            } else {
+                pos_seq = POS_SEQ_INIT;
+            }
+        } else {
+            ThisThread::sleep_for(10);
+        }
+    }
+}
+
+DisplayApp::DisplayApp(osPriority tsk_pri, uint32_t stack_size) : 
+  PcApp(false), displayThread(tsk_pri, stack_size) {
+    displayThread.start(callback(this, &DisplayApp::display_app_process));
+}
+
+void DisplayApp::SendHeader(uint32_t size) {
+    uint8_t headder_data[12] = {0xFF,0xFF,0xAA,0x55,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
+
+    headder_data[8]  = (uint8_t)((uint32_t)size >> 0);
+    headder_data[9]  = (uint8_t)((uint32_t)size >> 8);
+    headder_data[10] = (uint8_t)((uint32_t)size >> 16);
+    headder_data[11] = (uint8_t)((uint32_t)size >> 24);
+    PcApp.send((uint8_t *)headder_data, sizeof(headder_data));
+}
+
+void DisplayApp::SendData(uint8_t * buf, uint32_t size) {
+    PcApp.send(buf, size);
+}
+
+int DisplayApp::SendRgb888(uint8_t * buf, uint32_t pic_width, uint32_t pic_height) {
+    uint32_t offset_size = 54;
+    uint32_t buf_stride = (((pic_width * 4u) + 31u) & ~31u);
+    uint32_t pic_size = buf_stride * pic_height;
+    uint32_t total_size = pic_size + offset_size;
+    uint8_t wk_bitmap_buf[54];
+    int wk_idx = 0;
+
+    if (!PcApp.configured()) {
+        return 0;
+    }
+    SendHeader(total_size);
+
+    /* BITMAPFILEHEADER */
+    wk_bitmap_buf[wk_idx++] = 'B';
+    wk_bitmap_buf[wk_idx++] = 'M';
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(total_size >> 0);   /* bfSize */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(total_size >> 8);   /* bfSize */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(total_size >> 16);  /* bfSize */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(total_size >> 24);  /* bfSize */
+    wk_bitmap_buf[wk_idx++] = 0;  /* bfReserved1 */
+    wk_bitmap_buf[wk_idx++] = 0;  /* bfReserved1 */
+    wk_bitmap_buf[wk_idx++] = 0;  /* bfReserved2 */
+    wk_bitmap_buf[wk_idx++] = 0;  /* bfReserved2 */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(offset_size >> 0);   /* bfOffBits */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(offset_size >> 8);   /* bfOffBits */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(offset_size >> 16);  /* bfOffBits */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(offset_size >> 24);  /* bfOffBits */
+
+    /* BITMAPINFOHEADER */
+    wk_bitmap_buf[wk_idx++] = 40; /* biSize */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biSize */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biSize */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biSize */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_width >> 0);    /* biWidth */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_width >> 8);    /* biWidth */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_width >> 16);   /* biWidth */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_width >> 24);   /* biWidth */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)((-(long)pic_height) >> 0);   /* biHeight */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)((-(long)pic_height) >> 8);   /* biHeight */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)((-(long)pic_height) >> 16);  /* biHeight */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)((-(long)pic_height) >> 24);  /* biHeight */
+    wk_bitmap_buf[wk_idx++] = 1;  /* biPlanes */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biPlanes */
+    wk_bitmap_buf[wk_idx++] = 32; /* biBitCount */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biBitCount */
+
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCopmression */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCopmression */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCopmression */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCopmression */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_size >> 0);   /* biSizeImage */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_size >> 8);   /* biSizeImage */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_size >> 16);  /* biSizeImage */
+    wk_bitmap_buf[wk_idx++] = (uint8_t)(pic_size >> 24);  /* biSizeImage */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biXPixPerMeter */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biXPixPerMeter */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biXPixPerMeter */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biXPixPerMeter */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biYPixPerMeter */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biYPixPerMeter */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biYPixPerMeter */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biYPixPerMeter */
+
+    wk_bitmap_buf[wk_idx++] = 0;  /* biClrUsed */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biClrUsed */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biClrUsed */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biClrUsed */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCirImportant */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCirImportant */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCirImportant */
+    wk_bitmap_buf[wk_idx++] = 0;  /* biCirImportant */
+    PcApp.send(wk_bitmap_buf, wk_idx);
+
+    SendData(buf, pic_size);
+    wk_idx += pic_size;
+
+    return wk_idx;
+};
+
+void DisplayApp::SetCallback(Callback<void()> func) {
+    event = func;
+}
+
+int DisplayApp::SendJpeg(uint8_t * buf, uint32_t size) {
+    if (!PcApp.configured()) {
+        return 0;
+    }
+    SendHeader(size);
+    SendData(buf, size);
+
+    return size;
+}
+
+int DisplayApp::GetMaxTouchNum(void) {
+    return 1;
+}
+
+int DisplayApp::GetCoordinates(int touch_buff_num, touch_pos_t * p_touch) {
+    touch_pos_t * wk_touch;
+    int count = 0;
+    int x = pos_x;
+    int y = pos_y;
+
+    if (touch_buff_num > 0) {
+        count = 0;
+        wk_touch        = &p_touch[0];
+        wk_touch->valid = false;
+        wk_touch->x     = 0;
+        wk_touch->y     = 0;
+        if (x >= 0) {
+            count = 1;
+            wk_touch->valid = true;
+            wk_touch->x = (uint32_t)x;
+        }
+        if (y >= 0) {
+            count = 1;
+            wk_touch->valid = true;
+            wk_touch->y = (uint32_t)y;
+        }
+    }
+
+    return count;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/DisplayApp/DisplayApp.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,132 @@
+/* Copyright (c) 2016 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**************************************************************************//**
+* @file          DisplayApp.h
+* @brief         DisplayApp API
+******************************************************************************/
+
+#ifndef DISPLAY_APP_H
+#define DISPLAY_APP_H
+
+#include "mbed.h"
+#include "rtos.h"
+#include "USBSerial.h"
+
+/** A class to communicate a DisplayApp
+ *
+ */
+class DisplayApp {
+public:
+    /** Touch position structure */
+    typedef struct {
+        uint32_t x;      /**< The position of the x-coordinate. */
+        uint32_t y;      /**< The position of the y-coordinate. */
+        bool     valid;  /**< Whether a valid data.. */
+    } touch_pos_t;
+
+    /** Constructor: Initializes DisplayApp.
+     *
+     * @param   tsk_pri        Priority of the thread function. (default: osPriorityNormal).
+     * @param   init_pri       Priority of before the USB is connected. (default: osPriorityLow).
+     * @param   stack_size     stack size (in bytes) requirements for the thread function. (default: 2048).
+     */
+    DisplayApp(osPriority tsk_pri = osPriorityNormal, uint32_t stack_size = 2048);
+
+    /** Send RGB888 data
+     *
+     * @param buf data buffer address
+     * @param pic_width picture width
+     * @param pic_height picture height
+     * @return send data size
+     */
+    int SendRgb888(uint8_t * buf, uint32_t pic_width, uint32_t pic_height);
+
+    /** Send JPEG data
+     *
+     * @param buf data buffer address
+     * @param size data size
+     * @return send data size
+     */
+    int SendJpeg(uint8_t * buf, uint32_t size);
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     * @param func A pointer to a void function, or 0 to set as none
+     */
+    void SetCallback(Callback<void()> func);
+
+    /** Attach a function to call when touch panel int
+     *
+     * @param obj pointer to the object to call the member function on
+     * @param method pointer to the member function to be called
+     */
+    template<typename T>
+    void SetCallback(T* obj, void (T::*method)()) {
+        // Underlying call thread safe
+        SetCallback(callback(obj, method));
+    }
+
+    /** Attach a member function to call when touch panel int
+     *
+     * @param obj pointer to the object to call the member function on
+     * @param method pointer to the member function to be called
+     */
+    template<typename T>
+    void SetCallback(T* obj, void (*method)(T*)) {
+        // Underlying call thread safe
+        SetCallback(callback(obj, method));
+    }
+    /** Get the maximum number of simultaneous touches 
+     * 
+     * @return The maximum number of simultaneous touches.
+     */
+    int GetMaxTouchNum(void);
+
+   /** Get the coordinates
+     *
+     * @param touch_buff_num The number of structure p_touch.
+     * @param p_touch Touch position information.
+     * @return The number of touch points.
+     */
+    int GetCoordinates(int touch_buff_num, touch_pos_t * p_touch);
+
+private:
+    typedef enum {
+        POS_SEQ_INIT,
+        POS_SEQ_START,
+        POS_SEQ_X,
+        POS_SEQ_X_POS,
+        POS_SEQ_X_M,
+        POS_SEQ_C,
+        POS_SEQ_Y,
+        POS_SEQ_Y_POS,
+        POS_SEQ_Y_M,
+        POS_SEQ_END,
+    } pos_seq_t;
+
+    USBSerial PcApp;
+    Thread displayThread;
+    pos_seq_t pos_seq;
+    int pos_x;
+    int pos_y;
+    Callback<void()> event;
+
+    void touch_int_callback(void);
+    void display_app_process();
+    void SendHeader(uint32_t size);
+    void SendData(uint8_t * buf, uint32_t size);
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyAttach_CameraAndLCD/EasyAttach_CameraAndLCD.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,305 @@
+/* Copyright (c) 2017 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed.h"
+#include "rtos.h"
+#include "EasyAttach_CameraAndLCD.h"
+
+#if MBED_CONF_APP_LCD
+#if ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x0000)    /* GR-PEACH LVDS */
+static DigitalOut lcd_cntrst(P8_15);
+#elif ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x1000)  /* GR-LYCHEE */
+static PwmOut lcd_cntrst(P3_12);
+#elif (MBED_CONF_APP_LCD_TYPE == RZ_A2M_EVB_RSK_TFT) /* RZ/A2M */
+static PwmOut lcd_cntrst(P7_6);
+#endif
+#define MAX_BACKLIGHT_VOL       (33.0f)
+#ifndef TYPICAL_BACKLIGHT_VOL
+  #define TYPICAL_BACKLIGHT_VOL (33.0f)
+#endif
+static float voltage_adjust = (TYPICAL_BACKLIGHT_VOL / MAX_BACKLIGHT_VOL);
+#endif
+
+static const DisplayBase::lcd_config_t * lcd_port_init(DisplayBase& Display) {
+#if MBED_CONF_APP_LCD
+ #if ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x0000)   /* GR-PEACH LVDS */
+    PinName lvds_pin[8] = {
+        /* data pin */
+        P5_7, P5_6, P5_5, P5_4, P5_3, P5_2, P5_1, P5_0
+    };
+    Display.Graphics_Lvds_Port_Init(lvds_pin, 8);
+
+    DigitalOut lcd_pwon(P7_15);
+    DigitalOut lcd_blon(P8_1);
+    lcd_pwon = 0;
+    lcd_blon = 0;
+    ThisThread::sleep_for(100);
+    lcd_pwon = 1;
+    lcd_blon = 1;
+ #elif ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x0100) /* GR-PEACH RGB */
+    PinName lcd_pin[28] = {
+        /* data pin */
+        P11_15, P11_14, P11_13, P11_12, P5_7, P5_6, P5_5, P5_4, P5_3, P5_2, P5_1, P5_0,
+        P4_7, P4_6, P4_5, P4_4, P10_12, P10_13, P10_14, P10_15, P3_15, P3_14, P3_13,
+        P3_12, P3_11, P3_10, P3_9, P3_8
+    };
+    Display.Graphics_Lcd_Port_Init(lcd_pin, 28);
+ #elif ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x1000) /* GR-LYCHEE */
+    PinName lcd_pin[28] = {
+        /* data pin */
+        P6_15, P6_14, P6_13, P6_12, P6_11, P6_10, P6_9, P6_8, P6_7, P6_6, P6_5, P6_4,
+        P6_3, P6_2, P6_1, P6_0, P3_7, P3_6, P3_5, P3_4, P3_3, P3_2, P3_1, P3_0, P5_2,
+        P5_1, P5_0, P7_4, 
+    };
+    Display.Graphics_Lcd_Port_Init(lcd_pin, 28);
+
+    DigitalOut lcd_pwon(P5_12);
+    lcd_pwon = 0;
+    lcd_cntrst.period_us(500);
+    ThisThread::sleep_for(100);
+    lcd_pwon = 1;
+ #elif ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x2000) /* RZ/A2M LVDS */
+    PinName lvds_pin[8] = {
+        /* data pin */
+        P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7
+    };
+    Display.Graphics_Lvds_Port_Init(lvds_pin, 8);
+ #elif ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x2100) /* RZ/A2M RGB */
+    PinName lcd_pin[28] = {
+        /* data pin */
+        PB_5, PB_4, PB_3, PB_2, PB_1, PB_0, PA_7, PA_6, PA_5, PA_4, PA_3, PA_2, PA_1, PA_0,
+        P8_0, PF_0, PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PH_2, PF_7, PC_3, PC_4, P7_7, PJ_6
+    };
+    Display.Graphics_Lcd_Port_Init(lcd_pin, 28);
+  #if MBED_CONF_APP_LCD_TYPE == RZ_A2M_DVI_STICK
+    const char send_cmd[3] = {0x08u, 0xbfu, 0x70u};
+   #if defined(TARGET_RZ_A2M_SBEV) || defined(TARGET_SEMB1402)
+    I2C mI2c_(PD_5, PD_4);
+   #else
+    I2C mI2c_(I2C_SDA, I2C_SCL);
+   #endif
+    mI2c_.write(0x78, send_cmd, 3);
+  #elif MBED_CONF_APP_LCD_TYPE == RZ_A2M_EVB_RSK_TFT
+    lcd_cntrst.period_us(500);
+  #endif
+ #endif
+    return &LcdCfgTbl_LCD_shield;
+#else
+    return NULL;
+#endif
+}
+
+static DisplayBase::graphics_error_t camera_init(DisplayBase& Display, uint16_t cap_width, uint16_t cap_height) {
+#if MBED_CONF_APP_CAMERA
+ #if MBED_CONF_APP_CAMERA_TYPE == CAMERA_CVBS
+    DisplayBase::graphics_error_t error;
+    error = Display.Graphics_Video_init(DisplayBase::INPUT_SEL_VDEC, NULL);
+    if( error != DisplayBase::GRAPHICS_OK ) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        return error;
+    }
+
+    return DisplayBase::GRAPHICS_OK;
+ #else
+    DisplayBase::graphics_error_t error;
+    DisplayBase::video_input_sel_t video_input_sel;
+
+  #if CAMERA_MODULE == MODULE_MIPI
+    // do nothing
+  #elif defined(TARGET_RZ_A1H)
+    PinName cmos_camera_pin[11] = {
+        /* data pin */
+        P2_7, P2_6, P2_5, P2_4, P2_3, P2_2, P2_1, P2_0,
+        /* control pin */
+        P10_0,      /* DV0_CLK   */
+        P1_0,       /* DV0_Vsync */
+        P1_1        /* DV0_Hsync */
+    };
+   #if MBED_CONF_APP_SHIELD_TYPE == SHIELD_AUDIO_CAMERA
+    DigitalOut pwdn(P3_12);
+    pwdn = 0;
+    ThisThread::sleep_for(1 + 1);
+   #elif MBED_CONF_APP_SHIELD_TYPE == SHIELD_WIRELESS_CAMERA
+    DigitalOut pwdn(P3_15);
+    DigitalOut rstb(P3_14);
+    pwdn = 0;
+    rstb = 0;
+    ThisThread::sleep_for(10 + 1);
+    rstb = 1;
+    ThisThread::sleep_for(1 + 1);
+   #endif
+  #elif defined(TARGET_GR_LYCHEE)
+    PinName cmos_camera_pin[11] = {
+        /* data pin */
+        P1_0, P1_1, P1_2, P1_3, P1_8, P1_9, P1_10, P1_11,
+        /* control pin */
+        P7_8,       /* DV0_CLK   */
+        P7_9,       /* DV0_Vsync */
+        P7_10       /* DV0_Hsync */
+    };
+    DigitalOut pwdn(P7_11);
+    DigitalOut rstb(P2_3);
+
+    pwdn = 0;
+    rstb = 0;
+    ThisThread::sleep_for(10 + 1);
+    rstb = 1;
+    ThisThread::sleep_for(1 + 1);
+  #elif defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF) || defined(TARGET_RZ_A2M_SBEV) || defined(TARGET_SEMB1402)
+    PinName cmos_camera_pin[11] = {
+        /* data pin */
+        PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PH_0, PH_1,
+        /* control pin */
+        P6_1,       /* VIO_CLK   */
+        P6_2,       /* VIO_VD */
+        P6_3        /* VIO_HD */
+    };
+    DigitalOut camera_stby(PE_0);
+    camera_stby = 0;
+    ThisThread::sleep_for(1 + 1);
+  #endif
+
+    /* camera input port setting */
+  #if CAMERA_MODULE == MODULE_VDC
+    video_input_sel = DisplayBase::INPUT_SEL_EXT;
+    error = Display.Graphics_Dvinput_Port_Init(cmos_camera_pin, 11);
+  #elif CAMERA_MODULE == MODULE_CEU
+    video_input_sel = DisplayBase::INPUT_SEL_CEU;
+    error = Display.Graphics_Ceu_Port_Init(cmos_camera_pin, 11);
+  #else
+    video_input_sel = DisplayBase::INPUT_SEL_MIPI;
+    error = DisplayBase::GRAPHICS_OK;
+  #endif
+    if( error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        return error;
+    }
+
+  #if MBED_CONF_APP_CAMERA_TYPE == CAMERA_MT9V111
+    MT9V111_config camera_cfg;
+  #elif MBED_CONF_APP_CAMERA_TYPE == CAMERA_OV7725
+    OV7725_config camera_cfg;
+  #elif MBED_CONF_APP_CAMERA_TYPE == CAMERA_OV5642
+    OV5642_config camera_cfg;
+  #elif MBED_CONF_APP_CAMERA_TYPE == CAMERA_RASPBERRY_PI
+    RaspberryPi_config camera_cfg;
+  #else
+    #error "No camera chosen. Please add 'config.camera-type.value' to your mbed_app.json (see README.md for more information)."
+  #endif
+
+  #if CAMERA_MODULE == MODULE_MIPI
+    DisplayBase::video_mipi_param_t mipi_config;
+    DisplayBase::video_vin_setup_t  vin_setup;
+
+    camera_cfg.Initialise();
+    camera_cfg.SetMipiConfig(&mipi_config);
+    camera_cfg.SetVinSetup(&vin_setup);
+    error = Display.Graphics_Video_init(video_input_sel, &mipi_config, &vin_setup);
+  #else
+    DisplayBase::video_ext_in_config_t ext_in_config;
+
+    camera_cfg.Initialise();
+    camera_cfg.SetExtInConfig(&ext_in_config);
+    if (cap_width != 0) {
+        ext_in_config.cap_width  = cap_width;                             /* Capture width */
+    }
+    if (cap_height != 0) {
+        ext_in_config.cap_height = cap_height;                            /* Capture heigh */
+    }
+
+    error = Display.Graphics_Video_init(video_input_sel, &ext_in_config);
+  #endif
+    if( error != DisplayBase::GRAPHICS_OK ) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        return error;
+    }
+
+    return DisplayBase::GRAPHICS_OK;
+ #endif
+#else
+    return DisplayBase::GRAPHICS_OK;
+#endif
+}
+
+DisplayBase::graphics_error_t EasyAttach_Init(DisplayBase& Display, uint16_t cap_width, uint16_t cap_height) {
+    DisplayBase::graphics_error_t error;
+    const DisplayBase::lcd_config_t * lcd_config = lcd_port_init(Display);
+
+    error = Display.Graphics_init(lcd_config);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        return error;
+    }
+    return camera_init(Display, cap_width, cap_height);
+}
+
+void EasyAttach_SetTypicalBacklightVol(float typ_vol) {
+#if MBED_CONF_APP_LCD
+    if (typ_vol > MAX_BACKLIGHT_VOL) {
+        voltage_adjust = 1.0f;
+    } else {
+        voltage_adjust = (typ_vol / MAX_BACKLIGHT_VOL);
+    }
+#endif
+}
+
+void EasyAttach_LcdBacklight(bool type) {
+#if MBED_CONF_APP_LCD
+    if (type) {
+        EasyAttach_LcdBacklight(1.0f);
+    } else {
+        EasyAttach_LcdBacklight(0.0f);
+    }
+#endif
+}
+
+void EasyAttach_LcdBacklight(float value) {
+#if MBED_CONF_APP_LCD
+#if ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x0000) || ((MBED_CONF_APP_LCD_TYPE & 0xFF00) == 0x1000) || (MBED_CONF_APP_LCD_TYPE == RZ_A2M_EVB_RSK_TFT)
+    lcd_cntrst = (value * voltage_adjust);
+#endif
+#endif
+}
+
+DisplayBase::graphics_error_t EasyAttach_CameraStart(DisplayBase& Display, DisplayBase::video_input_channel_t channel) {
+#if MBED_CONF_APP_CAMERA
+    DisplayBase::graphics_error_t error;
+
+    /* Video write process start */
+    error = Display.Video_Start(channel);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        return error;
+    }
+
+  #if CAMERA_MODULE == MODULE_VDC
+    /* Video write process stop */
+    error = Display.Video_Stop(channel);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        return error;
+    }
+
+    /* Video write process start */
+    error = Display.Video_Start(channel);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        return error;
+    }
+  #endif
+#endif
+
+    return DisplayBase::GRAPHICS_OK;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyAttach_CameraAndLCD/EasyAttach_CameraAndLCD.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,162 @@
+/* Copyright (c) 2017 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef EASY_ATTACH_CAMERA_AND_LCD_H
+#define EASY_ATTACH_CAMERA_AND_LCD_H
+
+#include "DisplayBace.h"
+
+// camera
+#if MBED_CONF_APP_CAMERA
+  // camera-type
+  #define CAMERA_CVBS                 0x0001
+  #define CAMERA_MT9V111              0x0002
+  #define CAMERA_OV7725               0x0003
+  #define CAMERA_OV5642               0x0004
+  #define CAMERA_WIRELESS_CAMERA      0x0083
+  #define CAMERA_RASPBERRY_PI         0x2000
+
+  // shield-type
+  #define SHIELD_AUDIO_CAMERA         1
+  #define SHIELD_WIRELESS_CAMERA      2
+
+  // camera module
+  #define MODULE_VDC                  0
+  #define MODULE_CEU                  1
+  #define MODULE_MIPI                 2
+
+  #ifndef MBED_CONF_APP_SHIELD_TYPE
+    #if defined(TARGET_RZ_A1H)
+      #if (MBED_CONF_APP_CAMERA_TYPE == CAMERA_WIRELESS_CAMERA)
+        #define MBED_CONF_APP_SHIELD_TYPE  SHIELD_WIRELESS_CAMERA
+        #undef  MBED_CONF_APP_CAMERA_TYPE
+        #define MBED_CONF_APP_CAMERA_TYPE  CAMERA_OV7725
+      #else
+        #define MBED_CONF_APP_SHIELD_TYPE  SHIELD_AUDIO_CAMERA
+      #endif
+    #endif
+  #endif
+
+  #ifndef MBED_CONF_APP_CAMERA_TYPE
+    #if defined(TARGET_GR_LYCHEE)
+      #define MBED_CONF_APP_CAMERA_TYPE    CAMERA_OV7725
+    #elif defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF) || defined(TARGET_RZ_A2M_SBEV) || defined(TARGET_SEMB1402)
+      #define MBED_CONF_APP_CAMERA_TYPE    CAMERA_RASPBERRY_PI
+    #else
+      #define MBED_CONF_APP_CAMERA_TYPE    CAMERA_MT9V111
+    #endif
+  #endif
+
+  #if (MBED_CONF_APP_CAMERA_TYPE == CAMERA_CVBS) && defined(TARGET_GR_LYCHEE)
+    #error "MBED_CONF_APP_CAMERA_TYPE is not supported in this target."
+  #endif
+
+  #if ((MBED_CONF_APP_CAMERA_TYPE & 0x2000) != 0)
+    #define CAMERA_MODULE             MODULE_MIPI
+  #elif defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF) || defined(TARGET_RZ_A2M_SBEV) || defined(TARGET_SEMB1402)
+    #define CAMERA_MODULE             MODULE_CEU
+  #else
+    #define CAMERA_MODULE             MODULE_VDC
+  #endif
+
+  #if MBED_CONF_APP_CAMERA_TYPE == CAMERA_MT9V111
+    #include "MT9V111_config.h"
+  #elif MBED_CONF_APP_CAMERA_TYPE == CAMERA_OV7725
+    #include "OV7725_config.h"
+  #elif MBED_CONF_APP_CAMERA_TYPE == CAMERA_OV5642
+    #include "OV5642_config.h"
+  #elif MBED_CONF_APP_CAMERA_TYPE == CAMERA_RASPBERRY_PI
+    #include "RaspberryPi_config.h"
+  #endif
+#endif
+
+// lcd
+#if MBED_CONF_APP_LCD
+  // lcd-type
+  #define GR_PEACH_4_3INCH_SHIELD     0x0000
+  #define GR_PEACH_7_1INCH_SHIELD     0x0001
+  #define GR_PEACH_RSK_TFT            0x0002
+  #define GR_PEACH_DISPLAY_SHIELD     0x0100
+  #define GR_LYCHEE_TF043HV001A0      0x1000
+  #define GR_LYCHEE_ATM0430D25        0x1001
+  #define GR_LYCHEE_FG040346DSSWBG03  0x1002
+  #define RZ_A2M_LVDS_TO_HDMI         0x2000
+  #define RZ_A2M_EVB_RSK_TFT          0x2100
+  #define RZ_A2M_DVI_STICK            0x2101
+
+  #define GR_LYCHEE_LCD               GR_LYCHEE_TF043HV001A0
+
+  #ifndef MBED_CONF_APP_LCD_TYPE
+    #if defined(TARGET_RZ_A1H)
+      #define MBED_CONF_APP_LCD_TYPE    GR_PEACH_4_3INCH_SHIELD
+    #elif defined(TARGET_GR_LYCHEE)
+      #define MBED_CONF_APP_LCD_TYPE    GR_LYCHEE_LCD
+    #elif defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF)
+      #define MBED_CONF_APP_LCD_TYPE    RZ_A2M_DVI_STICK
+    #elif defined(TARGET_RZ_A2M_SBEV) || defined(TARGET_SEMB1402)
+      #define MBED_CONF_APP_LCD_TYPE    RZ_A2M_LVDS_TO_HDMI
+    #endif
+  #endif
+
+  #if defined(TARGET_RZ_A1H) && ((MBED_CONF_APP_LCD_TYPE & 0xF000) != 0x0000)
+    #error "MBED_CONF_APP_LCD_TYPE is not supported in this target."
+  #endif
+  #if defined(TARGET_GR_LYCHEE) && ((MBED_CONF_APP_LCD_TYPE & 0xF000) != 0x1000)
+    #error "MBED_CONF_APP_LCD_TYPE is not supported in this target."
+  #endif
+
+  #if MBED_CONF_APP_LCD_TYPE == GR_PEACH_4_3INCH_SHIELD
+    #include "LCD_shield_config_4_3inch.h"
+  #elif MBED_CONF_APP_LCD_TYPE == GR_PEACH_7_1INCH_SHIELD
+    #include "LCD_shield_config_7_1inch.h"
+  #elif MBED_CONF_APP_LCD_TYPE == GR_PEACH_RSK_TFT
+    #include "LCD_shield_config_RSK_TFT.h"
+  #elif MBED_CONF_APP_LCD_TYPE == GR_PEACH_DISPLAY_SHIELD
+    #include "Display_shield_config.h"
+  #elif MBED_CONF_APP_LCD_TYPE == GR_LYCHEE_TF043HV001A0
+    #include "LCD_config_TF043HV001A0.h"
+  #elif MBED_CONF_APP_LCD_TYPE == GR_LYCHEE_ATM0430D25
+    #include "LCD_config_ATM0430D25.h"
+  #elif MBED_CONF_APP_LCD_TYPE == GR_LYCHEE_FG040346DSSWBG03
+    #include "LCD_config_FG040346DSSWBG03.h"
+  #elif MBED_CONF_APP_LCD_TYPE == RZ_A2M_LVDS_TO_HDMI
+    #include "LCD_config_lvds_to_hdmi.h"
+  #elif MBED_CONF_APP_LCD_TYPE == RZ_A2M_EVB_RSK_TFT
+    #include "LCD_config_RSK_TFT.h"
+  #elif MBED_CONF_APP_LCD_TYPE == RZ_A2M_DVI_STICK
+    #include "LCD_config_DVI_Stick.h"
+  #else
+    #error "No lcd chosen. Please add 'config.lcd-type.value' to your mbed_app.json (see README.md for more information)."
+  #endif
+#endif
+
+extern DisplayBase::graphics_error_t EasyAttach_Init(
+    DisplayBase& Display,
+    uint16_t cap_width = 0,
+    uint16_t cap_height = 0
+);
+
+extern DisplayBase::graphics_error_t EasyAttach_CameraStart(
+    DisplayBase& Display,
+    DisplayBase::video_input_channel_t channel = DisplayBase::VIDEO_INPUT_CHANNEL_0
+);
+
+extern void EasyAttach_SetTypicalBacklightVol(float typ_vol);
+
+extern void EasyAttach_LcdBacklight(bool type = true);
+
+extern void EasyAttach_LcdBacklight(float value);
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyAttach_CameraAndLCD/README.md	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,104 @@
+# Easy Attach Camera And LCD - Easily add all supported Camera and LCD to your mbed OS project
+
+Just declare the desired camera and LCD in your `mbed_app.json` file, and call `EasyAttach_Init()` from your application.
+
+## Enable camera and LCD
+
+Add the following to your ``mbed_app.json`` file:
+
+```json
+{
+    "config": {
+        "camera":{
+            "help": "0:disable 1:enable",
+            "value": "1"
+        },
+        "lcd":{
+            "help": "0:disable 1:enable",
+            "value": "1"
+        }
+    }
+}
+```
+
+## Specifying Camera and LCD
+
+Add the following to your ``mbed_app.json`` file:
+
+```json
+{
+    "config": {
+        "camera":{
+            "help": "0:disable 1:enable",
+            "value": "1"
+        },
+        "camera-type":{
+            "help": "Please see EasyAttach_CameraAndLCD/README.md",
+            "value": "CAMERA_CVBS"
+        },
+        "lcd":{
+            "help": "0:disable 1:enable",
+            "value": "1"
+        },
+        "lcd-type":{
+            "help": "Please see EasyAttach_CameraAndLCD/README.md",
+            "value": "GR_PEACH_4_3INCH_SHIELD"
+        }
+    }
+}
+```
+
+| camera-type "value"        | Description                        |
+|:---------------------------|:-----------------------------------|
+| CAMERA_CVBS                | GR-PEACH NTSC signal               |
+| CAMERA_MT9V111             | GR-PEACH MT9V111                   |
+| CAMERA_OV7725              | GR-LYHCEE included camera          |
+| CAMERA_OV5642              | GR-PEACH OV5642                    |
+| CAMERA_WIRELESS_CAMERA     | GR-PEACH Wireless/Camera shield (OV7725) |
+| CAMERA_RASPBERRY_PI        | RZ/A2M Raspberry Pi camera         |
+
+| lcd-type "value"           | Description                        |
+|:---------------------------|:-----------------------------------|
+| GR_PEACH_4_3INCH_SHIELD    | GR-PEACH 4.3 inch LCD shield       |
+| GR_PEACH_7_1INCH_SHIELD    | GR-PEACH 7.1 inch LCD shield       |
+| GR_PEACH_RSK_TFT           | GR-PEACH RSK board LCD             |
+| GR_PEACH_DISPLAY_SHIELD    | GR-PEACH Display Shield            |
+| GR_LYCHEE_TF043HV001A0     | GR-LYHCEE TF043HV001A0             |
+| GR_LYCHEE_ATM0430D25       | GR-LYHCEE ATM0430D25               |
+| GR_LYCHEE_FG040346DSSWBG03 | GR-LYHCEE FG040346DSSWBG03         |
+| GR_LYCHEE_LCD              | GR-LYHCEE TF043HV001A0 (For compatibility) |
+| RZ_A2M_LVDS_TO_HDMI        | RZ/A2M LVDS To HDMI Board          |
+| RZ_A2M_EVB_RSK_TFT         | RZ/A2M RSK TFT APP BOARD           |
+| RZ_A2M_DVI_STICK           | RZ/A2M Display Output Board        |
+
+If camera-type and lcd-type are not specified, the following are specified.
+* ``GR-PEACH``    camera:CAMERA_MT9V111, LCD:GR_PEACH_4_3INCH_SHIELD  
+* ``GR-LYCHEE``   camera:CAMERA_OV7725,  LCD:GR_LYCHEE_LCD  
+* ``RZ/A2M Evaluation Board Kit`` camera:CAMERA_RASPBERRY_PI, LCD:RZ_A2M_DVI_STICK
+* ``SBEV-RZ/A2M`` camera:CAMERA_RASPBERRY_PI, LCD:RZ_A2M_LVDS_TO_HDMI
+* ``SEMB1402``    camera:CAMERA_RASPBERRY_PI, LCD:RZ_A2M_LVDS_TO_HDMI
+
+
+## Using Easy Connect Camera from your application
+
+Easy Connect Camera has just one function:
+
+```cpp
+#include "EasyAttach_CameraAndLCD.h"
+
+int main(void) {
+    DisplayBase Display;
+
+    EasyAttach_Init(Display);
+
+    // Required processing of your program
+
+    EasyAttach_CameraStart(Display, DisplayBase::VIDEO_INPUT_CHANNEL_0);
+
+    // Required processing of your program
+
+    EasyAttach_LcdBacklight(true);
+
+    // Rest of your program
+}
+```

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyPlayback/EasyPlayback.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,277 @@
+/* mbed EasyPlayback Library
+ * Copyright (C) 2017 dkato
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "dcache-control.h"
+#include "EasyPlayback.h"
+
+EasyPlayback::EasyPlayback(audio_type_t type, PinName pin1, PinName pin2) : 
+     _buff_index(0), _type(type), _skip(false), _pause(false), _init_end(false)
+{
+    _audio_buff_size = 0;
+    _audio_write_buff_num = 0;
+    _audio_ssif = NULL;
+    _audio_pwm = NULL;
+#if (R_BSP_SPDIF_ENABLE == 1)
+    _audio_spdif = NULL;
+#endif
+    _audio_soundless = NULL;
+    _heap_buf = NULL;
+    _audio_buf = NULL;
+    if (_type == AUDIO_TPYE_SSIF) {
+        _audio_buff_size = 4096;
+        _audio_write_buff_num = 8;
+        _audio_ssif = new AUDIO_GRBoard(0x80, (_audio_write_buff_num - 1), 0);
+        _audio = _audio_ssif;
+    } else if (_type == AUDIO_TPYE_PWM) {
+        _audio_buff_size = 4096;
+        _audio_write_buff_num = 8;
+        _audio_pwm = new PwmOutSpeaker(pin1, pin2);
+        _audio = _audio_pwm;
+    } else if (_type == AUDIO_TPYE_SPDIF) {
+#if (R_BSP_SPDIF_ENABLE == 1)
+        _audio_buff_size = (192 * 2 * 10);
+        _audio_write_buff_num = 8;
+        _audio_spdif = new SPDIF_GRBoard(0x80, (_audio_write_buff_num - 1), 0);
+        _audio = _audio_spdif;
+#else
+        MBED_ASSERT(false);
+#endif
+    } else if (_type == AUDIO_TPYE_SOUNDLESS) {
+        _audio_buff_size = (4410 * 2);
+        _audio_write_buff_num = 0;
+        _audio_soundless = new SoundlessSpeaker();
+        _audio = _audio_soundless;
+    } else if (_type == AUDIO_TPYE_NULL) {
+        _audio_buff_size = 4096;
+        _audio_write_buff_num = 0;
+        _audio_null = new NullSpeaker();
+        _audio = _audio_null;
+    } else {
+        MBED_ASSERT(false);
+    }
+    if ((_audio_buff_size != 0) && (_audio_write_buff_num != 0)) {
+        _heap_buf = new uint8_t[_audio_buff_size * _audio_write_buff_num + 31];
+        _audio_buf = (uint8_t *)(((uint32_t)_heap_buf + 31ul) & ~31ul);
+    }
+}
+
+EasyPlayback::~EasyPlayback()
+{
+    if (_audio_ssif != NULL) {
+        delete _audio_ssif;
+    }
+    if (_audio_pwm != NULL) {
+        delete _audio_pwm;
+    }
+#if (R_BSP_SPDIF_ENABLE == 1)
+    if (_audio_spdif != NULL) {
+        delete _audio_spdif;
+    }
+#endif
+    if (_audio_soundless != NULL) {
+        delete _audio_soundless;
+    }
+    if (_heap_buf != NULL) {
+        delete [] _heap_buf;
+    }
+}
+
+bool EasyPlayback::get_tag(const char* filename, char* p_title, char* p_artist, char* p_album, uint16_t tag_size)
+{
+    FILE * fp = NULL;
+    EasyDecoder * decoder;
+    bool ret = false;
+
+    decoder = create_decoer_class(filename);
+    if (decoder == NULL) {
+        return false;
+    }
+
+    fp = fopen(filename, "r");
+    if (fp == NULL) {
+        // do nothing
+    } else if (decoder->AnalyzeHeder(p_title, p_artist, p_album, tag_size, fp) != false) {
+        ret = true;
+    }
+    delete decoder;
+    if (fp != NULL) {
+        fclose(fp);
+    }
+
+    return ret;
+}
+
+bool EasyPlayback::play(const char* filename)
+{
+    const rbsp_data_conf_t audio_write_async_ctl = {NULL, NULL};
+    size_t audio_data_size;
+    FILE * fp = NULL;
+    uint8_t * p_buf;
+    uint32_t read_size;
+    uint32_t i;
+    EasyDecoder * decoder;
+    bool ret = false;
+    uint32_t padding_size;
+
+    decoder = create_decoer_class(filename);
+    if (decoder == NULL) {
+        return false;
+    }
+
+    if (!_init_end) {
+        _audio->power();
+        _audio->outputVolume(1.0, 1.0);
+        _init_end = true;
+    }
+
+     _skip = false;
+    fp = fopen(filename, "r");
+    if (fp == NULL) {
+        // do nothing
+    } else if (decoder->AnalyzeHeder(NULL, NULL, NULL, 0, fp) == false) {
+        // do nothing
+    } else if  ((decoder->GetChannel() != 2)
+            || (_audio->format(decoder->GetBlockSize()) == false)
+            || (_audio->frequency(decoder->GetSamplingRate()) == false)) {
+        // do nothing
+    } else {
+        if ((_type == AUDIO_TPYE_SPDIF) && (decoder->GetBlockSize() == 16)) {
+            padding_size = 2;
+            read_size = _audio_buff_size / 2;
+        } else if ((decoder->GetBlockSize() == 20) || (decoder->GetBlockSize() == 24)) {
+            padding_size = 1;
+            read_size = _audio_buff_size * 3 / 4;
+        } else {
+            padding_size = 0;
+            read_size = _audio_buff_size;
+        }
+        setvbuf(fp, NULL, _IONBF, 0); // unbuffered
+
+        while (true) {
+            while ((_pause) && (!_skip)) {
+                ThisThread::sleep_for(100);
+            }
+            if (_skip) {
+                break;
+            }
+            if (_audio_buf == NULL) {
+                audio_data_size = decoder->GetNextData(NULL, read_size);
+                if (audio_data_size > 0) {
+                    if (padding_size != 0) {
+                        _audio->write(NULL, _audio_buff_size, &audio_write_async_ctl);
+                    } else {
+                        _audio->write(NULL, audio_data_size, &audio_write_async_ctl);
+                    }
+                } else {
+                    break;
+                }
+            } else {
+                p_buf = &_audio_buf[_audio_buff_size * _buff_index];
+                audio_data_size = decoder->GetNextData(p_buf, read_size);
+                if (audio_data_size > 0) {
+                    if (padding_size != 0) {
+                        int idx_w = _audio_buff_size - 1;
+                        int idx_r = read_size - 1;
+                        uint32_t block_byte = (decoder->GetBlockSize() + 7) / 8;
+
+                        // fill the shortfall with 0
+                        for (i = audio_data_size; i < read_size; i++) {
+                            p_buf[i] = 0;
+                        }
+
+                        while (idx_w >= 0) {
+                            // padding
+                            for (i = 0; i < padding_size; i++) {
+                                p_buf[idx_w--] = 0x00;
+                            }
+                            for (i = 0; i < block_byte; i++) {
+                                p_buf[idx_w--] = p_buf[idx_r--];
+                            }
+                        }
+                        dcache_clean(p_buf, _audio_buff_size);
+                        _audio->write(p_buf, _audio_buff_size, &audio_write_async_ctl);
+                    } else {
+                        dcache_clean(p_buf, audio_data_size);
+                        _audio->write(p_buf, audio_data_size, &audio_write_async_ctl);
+                    }
+                    if ((_buff_index + 1) < _audio_write_buff_num) {
+                        _buff_index++;
+                    } else {
+                        _buff_index = 0;
+                    }
+                } else {
+                    break;
+                }
+            }
+        }
+        ThisThread::sleep_for(500);
+        ret = true;
+    }
+    delete decoder;
+    if (fp != NULL) {
+        fclose(fp);
+    }
+
+    return ret;
+}
+
+bool EasyPlayback::is_paused(void)
+{
+    return _pause;
+}
+
+void EasyPlayback::pause()
+{
+    _pause = !_pause;
+}
+
+void EasyPlayback::pause(bool type)
+{
+    _pause = type;
+}
+
+void EasyPlayback::skip(void)
+{
+    _skip = true;
+}
+
+bool EasyPlayback::outputVolume(float VolumeOut)
+{
+    if (!_init_end) {
+        _audio->power();
+        _init_end = true;
+    }
+    return _audio->outputVolume(VolumeOut, VolumeOut);
+}
+
+EasyDecoder * EasyPlayback::create_decoer_class(const char* filename)
+{
+    std::map<std::string, EasyDecoder*(*)()>::iterator itr;
+    char *extension = strstr((char *)filename, ".");
+
+    if (extension == NULL) {
+        return NULL;
+    }
+
+    itr = m_lpDecoders.find(extension);
+    if (itr == m_lpDecoders.end()) {
+        return NULL;
+    }
+
+    return (*itr).second();
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyPlayback/EasyPlayback.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,79 @@
+/* mbed EasyPlayback Library
+ * Copyright (C) 2017 dkato
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __EASY_PLAYBACK_H__
+#define __EASY_PLAYBACK_H__
+
+#include <string>
+#include <map>
+#include "EasyDecoder.h"
+#include "AUDIO_GRBoard.h"
+#include "PwmOutSpeaker.h"
+#include "SPDIF_GRBoard.h"
+#include "SoundlessSpeaker.h"
+#include "NullSpeaker.h"
+#include "FATFileSystem.h"
+
+class EasyPlayback
+{
+public:
+    typedef enum {
+        AUDIO_TPYE_SSIF,
+        AUDIO_TPYE_PWM,
+        AUDIO_TPYE_SPDIF,
+        AUDIO_TPYE_SOUNDLESS,
+        AUDIO_TPYE_NULL
+    } audio_type_t;
+
+    EasyPlayback(audio_type_t type = AUDIO_TPYE_SSIF, PinName pin1 = NC, PinName pin2 = NC);
+    ~EasyPlayback();
+    bool get_tag(const char* filename, char* p_title, char* p_artist, char* p_album, uint16_t tag_size);
+    bool play(const char* filename);
+    bool is_paused(void);
+    void pause(void);
+    void pause(bool type);
+    void skip(void);
+    bool outputVolume(float VolumeOut);
+
+    template<typename T>
+    void add_decoder(const string& extension) {
+        m_lpDecoders[extension] = &T::inst;
+    }
+
+private:
+    AUDIO_GRBoard * _audio_ssif;
+    PwmOutSpeaker * _audio_pwm;
+#if (R_BSP_SPDIF_ENABLE == 1)
+    SPDIF_GRBoard * _audio_spdif;
+#endif
+    SoundlessSpeaker * _audio_soundless;
+    NullSpeaker * _audio_null;
+    AUDIO_RBSP * _audio;
+    int _buff_index;
+    audio_type_t _type;
+    bool _skip;
+    bool _pause;
+    bool _init_end;
+    uint32_t _audio_write_buff_num;
+    uint32_t _audio_buff_size;
+    uint8_t *_heap_buf;
+    uint8_t *_audio_buf;
+    std::map<std::string, EasyDecoder*(*)()> m_lpDecoders;
+
+    EasyDecoder * create_decoer_class(const char* filename);
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyPlayback/decoder/EasyDec_Mov.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,193 @@
+/* mbed EasyDec_Mov Library
+ * Copyright (C) 2018 dkato
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "EasyDec_Mov.h"
+
+#define FourConstant(a, b, c, d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
+
+#ifndef htonl
+#   define htonl(x) __REV(x)
+#endif
+#ifndef ntohl
+#   define ntohl(x) __REV(x)
+#endif
+
+uint8_t * EasyDec_Mov::_videoBuf = NULL;
+uint32_t EasyDec_Mov::_videoBufSize = 0;
+Callback<void()> EasyDec_Mov::_function = NULL;
+
+void EasyDec_Mov::attach(Callback<void()> func, uint8_t * video_buf, uint32_t video_buf_size) {
+    _function = func;
+    _videoBuf = video_buf;
+    _videoBufSize = video_buf_size;
+}
+
+bool EasyDec_Mov::AnalyzeHeder(char* p_title, char* p_artist, char* p_album, uint16_t tag_size, FILE* fp) {
+    Buffer buf;
+
+    if (fp == NULL) {
+        return false;
+    }
+    if (p_title != NULL) {
+        p_title[0] = '\0';
+    }
+    if (p_artist != NULL) {
+        p_artist[0] = '\0';
+    }
+    if (p_album != NULL) {
+        p_album[0] = '\0';
+    }
+
+    mov_fp = fp;
+    availableCount = bufSize;
+
+    frameSizesP = frameSizes;
+    audioSizesP = audioSizes;
+
+    search(htonl(FourConstant('s', 't', 's', 'z')));
+    fseek(mov_fp, 8, SEEK_CUR);
+    fread(&buf, sizeof(Buffer), 1, mov_fp);
+    numOfFrames = htonl(buf.value);
+    stszAddress = ftell(mov_fp);
+    fread(&buf, sizeof(Buffer), 1, mov_fp);
+
+    search(htonl(FourConstant('s', 't', 'c', 'o')));
+    fseek(mov_fp, 4, SEEK_CUR);
+    fread(&buf, sizeof(Buffer), 1, mov_fp);
+    if (numOfFrames != htonl(buf.value)) {
+        return false;
+    }
+    fread(&buf, sizeof(Buffer), 1, mov_fp);
+    stcoAddress = ftell(mov_fp);
+    lastFrameAddress = htonl(buf.value);
+
+    fillCaches();
+
+    _video_flg = true;
+
+    return true;
+}
+
+size_t EasyDec_Mov::GetNextData(void *buf, size_t len) {
+    size_t ret;
+    uint32_t rest_size = 0;
+    uint32_t aSize = *audioSizesP;
+
+    if (numOfFrames <= 0) {
+        return 0;
+    }
+
+    if (_video_flg) {
+        _video_flg = false;
+        if ((_videoBuf == NULL) || (*frameSizesP > _videoBufSize)) {
+            fseek(mov_fp, *frameSizesP, SEEK_CUR);
+        } else {
+            fread(_videoBuf, 1, *frameSizesP, mov_fp);
+            if (_function) {
+                _function();
+            }
+        }
+        frameSizesP++;
+    }
+
+    if ((int)aSize < 0) {
+        ret = 0;
+    } else {
+        if (aSize > len) {
+            rest_size = aSize - len;
+            *audioSizesP = rest_size;
+            aSize = len;
+        }
+        if (buf == NULL) {
+            fseek(mov_fp, aSize, SEEK_CUR);
+            ret = aSize;
+        } else {
+            ret = (uint32_t)fread(buf, 1, aSize, mov_fp);
+        }
+    }
+    if (rest_size == 0) {
+        _video_flg = true;
+        audioSizesP++;
+        if (--availableCount == 0) {
+            fillCaches();
+        }
+        numOfFrames--;
+    }
+
+    return ret;
+}
+
+uint16_t EasyDec_Mov::GetChannel() {
+    return 2;
+}
+
+uint16_t EasyDec_Mov::GetBlockSize() {
+    return 16;
+}
+
+uint32_t EasyDec_Mov::GetSamplingRate() {
+    return 44100;
+}
+
+void EasyDec_Mov::search(uint32_t pattern) {
+    Buffer buf;
+    uint8_t first = pattern & 0xFF;
+    buf.value = 0;
+    while (true) {
+        size_t size = fread(buf.array, sizeof(int8_t), 1, mov_fp);
+        if (size == 0) {
+            return;
+        }
+        if (buf.array[0] == first) {
+            fread(&buf.array[1], sizeof(int8_t), 3, mov_fp);
+            if (buf.value == pattern) {
+                break;
+            }
+        }
+    }
+}
+
+void EasyDec_Mov::fillCaches() {
+    Buffer buf[bufSize];
+    Buffer *bufP = buf;
+    uint32_t lastFrame = lastFrameAddress;
+
+    fseek(mov_fp, stszAddress, SEEK_SET);
+    fread(frameSizes, sizeof(uint32_t), bufSize, mov_fp);
+    stszAddress += sizeof(uint32_t) * bufSize;
+
+    fseek(mov_fp, stcoAddress, SEEK_SET);
+    stcoAddress += sizeof(uint32_t) * bufSize;
+    fread(buf, sizeof(Buffer), bufSize, mov_fp);
+    availableCount = bufSize;
+    frameSizesP = frameSizes;
+    audioSizesP = audioSizes;
+    do {
+        uint32_t frameAddress = htonl(bufP->value);
+        *frameSizesP = htonl(*frameSizesP);
+        *audioSizesP++ = frameAddress - lastFrameAddress - *frameSizesP;
+        lastFrameAddress = frameAddress;
+        ++frameSizesP;
+        ++bufP;
+    } while (--availableCount);
+
+    fseek(mov_fp, lastFrame, SEEK_SET);
+    availableCount = bufSize;
+    frameSizesP = frameSizes;
+    audioSizesP = audioSizes;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyPlayback/decoder/EasyDec_Mov.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,106 @@
+/* mbed EasyDec_Mov Library
+ * Copyright (C) 2018 dkato
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**************************************************************************//**
+* @file          EasyDec_Mov.h
+* @brief         mov
+******************************************************************************/
+#ifndef __EASY_DEC_MOV_H__
+#define __EASY_DEC_MOV_H__
+
+#include "EasyDecoder.h"
+
+/** A class to communicate a EasyDec_Mov
+ *
+ */
+class EasyDec_Mov : public EasyDecoder {
+public:
+
+    static inline EasyDecoder* inst() { return new EasyDec_Mov; }
+
+    /** Attach a function to be called when acquiring an image
+     *
+     * @param func pointer to the function to be called
+     * @param video_buf video buffer address
+     * @param video_buf_size video buffer size
+     */
+    static void attach(Callback<void()> func, uint8_t * video_buf, uint32_t video_buf_size);
+
+    /** analyze header
+     *
+     * @param p_title title tag buffer
+     * @param p_artist artist tag buffer
+     * @param p_album album tag buffer
+     * @param tag_size tag buffer size
+     * @param fp file pointer
+     * @return true = success, false = failure
+     */
+    virtual bool AnalyzeHeder(char* p_title, char* p_artist, char* p_album, uint16_t tag_size, FILE* fp);
+
+    /** get next data
+     *
+     * @param buf data buffer address
+     * @param len data buffer length
+     * @return get data size
+     */
+    virtual size_t GetNextData(void *buf, size_t len);
+
+    /** get channel
+     *
+     * @return channel
+     */
+    virtual uint16_t GetChannel();
+
+    /** get block size
+     *
+     * @return block size
+     */
+    virtual uint16_t GetBlockSize();
+
+    /** get sampling rate
+     *
+     * @return sampling rate
+     */
+    virtual uint32_t GetSamplingRate();
+
+private:
+    union __attribute__((packed)) Buffer {
+        uint8_t  array[4];
+        uint32_t value;
+    };
+    static uint8_t * _videoBuf;
+    static uint32_t _videoBufSize;
+    static Callback<void()> _function;  /**< Callback. */
+
+    static const int bufSize = 32;
+    uint32_t frameSizes[bufSize];
+    uint32_t audioSizes[bufSize];
+    FILE * mov_fp;
+    uint32_t numOfFrames;
+    uint32_t *frameSizesP;
+    uint32_t *audioSizesP;
+    uint32_t stszAddress;
+    uint32_t stcoAddress;
+    uint32_t lastFrameAddress;
+    int availableCount;
+    bool _video_flg;
+
+    void search(uint32_t pattern);
+    void fillCaches();
+};
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyPlayback/decoder/EasyDec_WavCnv2ch.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,215 @@
+/* mbed EasyDec_WavCnv2ch Library
+ * Copyright (C) 2017 dkato
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "EasyDec_WavCnv2ch.h"
+
+bool EasyDec_WavCnv2ch::AnalyzeHeder(char* p_title, char* p_artist, char* p_album, uint16_t tag_size, FILE* fp) {
+    bool result = false;
+    size_t read_size;
+    uint8_t wk_read_buff[36];
+    char *data;
+    uint32_t chunk_size;
+    uint32_t sub_chunk_size;
+    uint32_t list_index_max;
+    bool list_ok = false;
+    uint32_t read_index = 0;
+    uint32_t data_index = 0;
+    uint16_t wk_len;
+
+    if (fp == NULL) {
+        return false;
+    }
+    music_data_size  = 0;
+    music_data_index = 0;
+    wav_fp = fp;
+    if (p_title != NULL) {
+        p_title[0] = '\0';
+    }
+    if (p_artist != NULL) {
+        p_artist[0] = '\0';
+    }
+    if (p_album != NULL) {
+        p_album[0] = '\0';
+    }
+
+    read_size = fread(&wk_read_buff[0], sizeof(char), 36, wav_fp);
+    if (read_size < 36) {
+        // do nothing
+    } else if (memcmp(&wk_read_buff[0], "RIFF", 4) != 0) {
+        // do nothing
+    } else if (memcmp(&wk_read_buff[8], "WAVE", 4) != 0) {
+        // do nothing
+    } else if (memcmp(&wk_read_buff[12], "fmt ", 4) != 0) {
+        // do nothing
+    } else {
+        read_index += 36;
+        channel = ((uint32_t)wk_read_buff[22] << 0) + ((uint32_t)wk_read_buff[23] << 8);
+        sampling_rate = ((uint32_t)wk_read_buff[24] << 0)
+                      + ((uint32_t)wk_read_buff[25] << 8)
+                      + ((uint32_t)wk_read_buff[26] << 16)
+                      + ((uint32_t)wk_read_buff[27] << 24);
+        block_size = ((uint32_t)wk_read_buff[34] << 0) + ((uint32_t)wk_read_buff[35] << 8);
+        while (1) {
+            read_size = fread(&wk_read_buff[0], sizeof(char), 8, wav_fp);
+            read_index += 8;
+            if (read_size < 8) {
+                break;
+            } else {
+                chunk_size = ((uint32_t)wk_read_buff[4] << 0)
+                           + ((uint32_t)wk_read_buff[5] << 8)
+                           + ((uint32_t)wk_read_buff[6] << 16)
+                           + ((uint32_t)wk_read_buff[7] << 24);
+                if (memcmp(&wk_read_buff[0], "data", 4) == 0) {
+                    result = true;
+                    music_data_size = chunk_size;
+                    if (list_ok == true) {
+                        break;
+                    } else {
+                        data_index = read_index;
+                        fseek(wav_fp, chunk_size, SEEK_CUR);
+                        read_index += chunk_size;
+                    }
+                } else if (memcmp(&wk_read_buff[0], "LIST", 4) == 0) {
+                    list_ok = true;
+                    list_index_max = read_index + chunk_size;
+                    read_size = fread(&wk_read_buff[0], sizeof(char), 4, wav_fp);
+                    read_index += 4;
+                    while (read_index < list_index_max) {
+                        read_size = fread(&wk_read_buff[0], sizeof(char), 8, wav_fp);
+                        read_index += 8;
+                        if (read_size < 8) {
+                            break;
+                        } else if (memcmp(&wk_read_buff[0], "INAM", 4) == 0) {
+                            data = p_title;
+                        } else if (memcmp(&wk_read_buff[0], "IART", 4) == 0) {
+                            data = p_artist;
+                        } else if (memcmp(&wk_read_buff[0], "IPRD", 4) == 0) {
+                            data = p_album;
+                        } else {
+                            data = NULL;
+                        }
+                        sub_chunk_size = ((uint32_t)wk_read_buff[4] << 0)
+                                       + ((uint32_t)wk_read_buff[5] << 8)
+                                       + ((uint32_t)wk_read_buff[6] << 16)
+                                       + ((uint32_t)wk_read_buff[7] << 24);
+                        if ((data != NULL) && (tag_size != 0)) {
+                            if (sub_chunk_size > (uint32_t)(tag_size - 1)) {
+                                wk_len = (tag_size - 1);
+                            } else {
+                                wk_len = sub_chunk_size;
+                            }
+                            read_size = fread(data, sizeof(char), wk_len, wav_fp);
+                            data[wk_len] = '\0';
+                        }
+                        if ((sub_chunk_size & 0x00000001) != 0) {
+                            sub_chunk_size += 1;
+                        }
+                        read_index += sub_chunk_size;
+                        fseek(wav_fp, read_index, SEEK_SET);
+                    }
+                    if (data_index != 0) {
+                        break;
+                    } else {
+                        fseek(wav_fp, list_index_max, SEEK_SET);
+                    }
+                } else {
+                    fseek(wav_fp, chunk_size, SEEK_CUR);
+                    read_index += chunk_size;
+                }
+            }
+        }
+
+        if (data_index != 0) {
+            fseek(wav_fp, data_index, SEEK_SET);
+        }
+    }
+
+    return result;
+}
+
+size_t EasyDec_WavCnv2ch::GetNextData(void *buf, size_t len) {
+    size_t ret_size;
+    size_t read_max = len;
+
+    if (block_size < 8) {
+        return -1;
+    }
+
+    if ((channel == 1) && (len != 0)) {
+        read_max /= 2;
+    }
+
+    if ((music_data_index + read_max) > music_data_size) {
+        read_max = music_data_size - music_data_index;
+    }
+
+    if (read_max <= 0) {
+        return 0;
+    }
+
+    music_data_index += read_max;
+
+    if (buf == NULL) {
+        fseek(wav_fp, read_max, SEEK_CUR);
+        ret_size = read_max;
+        if ((channel == 1) && (ret_size > 0)) {
+            ret_size *= 2;
+        }
+    } else {
+        ret_size = fread(buf, sizeof(char), read_max, wav_fp);
+
+        if ((channel == 1) && (ret_size > 0)) {
+            int block_byte;
+            int idx_w = len - 1;
+            int idx_r = ret_size - 1;
+            int idx_r_last;
+            int j;
+
+            block_byte = (block_size + 7) / 8;
+            while (idx_w >= 0) {
+                idx_r_last = idx_r;
+                for (j = 0; j < block_byte; j++) {
+                    ((uint8_t*)buf)[idx_w--] = ((uint8_t*)buf)[idx_r--];
+                }
+                idx_r = idx_r_last;
+                for (j = 0; j < block_byte; j++) {
+                    ((uint8_t*)buf)[idx_w--] = ((uint8_t*)buf)[idx_r--];
+                }
+            }
+            ret_size *= 2;
+        }
+    }
+
+    return ret_size;
+}
+
+uint16_t EasyDec_WavCnv2ch::GetChannel() {
+    if (channel == 1) {
+        return 2;
+    } else {
+        return channel;
+    }
+}
+
+uint16_t EasyDec_WavCnv2ch::GetBlockSize() {
+    return block_size;
+}
+
+uint32_t EasyDec_WavCnv2ch::GetSamplingRate() {
+    return sampling_rate;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyPlayback/decoder/EasyDec_WavCnv2ch.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,80 @@
+/* mbed EasyDec_WavCnv2ch Library
+ * Copyright (C) 2017 dkato
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**************************************************************************//**
+* @file          EasyDec_WavCnv2ch.h
+* @brief         wav
+******************************************************************************/
+#ifndef __EASY_DEC_WAV_CNV_2CH_H__
+#define __EASY_DEC_WAV_CNV_2CH_H__
+
+#include "EasyDecoder.h"
+
+/** A class to communicate a EasyDec_WavCnv2ch
+ *
+ */
+class EasyDec_WavCnv2ch : public EasyDecoder {
+public:
+
+    static inline EasyDecoder* inst() { return new EasyDec_WavCnv2ch; }
+
+    /** analyze header
+     *
+     * @param p_title title tag buffer
+     * @param p_artist artist tag buffer
+     * @param p_album album tag buffer
+     * @param tag_size tag buffer size
+     * @param fp file pointer
+     * @return true = success, false = failure
+     */
+    virtual bool AnalyzeHeder(char* p_title, char* p_artist, char* p_album, uint16_t tag_size, FILE* fp);
+
+    /** get next data
+     *
+     * @param buf data buffer address
+     * @param len data buffer length
+     * @return get data size
+     */
+    virtual size_t GetNextData(void *buf, size_t len);
+
+    /** get channel
+     *
+     * @return channel
+     */
+    virtual uint16_t GetChannel();
+
+    /** get block size
+     *
+     * @return block size
+     */
+    virtual uint16_t GetBlockSize();
+
+    /** get sampling rate
+     *
+     * @return sampling rate
+     */
+    virtual uint32_t GetSamplingRate();
+
+private:
+    FILE * wav_fp;
+    uint32_t music_data_size;
+    uint32_t music_data_index;
+    uint16_t channel;
+    uint16_t block_size;
+    uint32_t sampling_rate;
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/EasyPlayback/decoder/EasyDecoder.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,66 @@
+/* mbed EasyDecoder Library
+ * Copyright (C) 2017 dkato
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __EASY_DECODER_H__
+#define __EASY_DECODER_H__
+
+#include "mbed.h"
+
+class EasyDecoder {
+public:
+
+    virtual ~EasyDecoder(){}
+
+    /** analyze header
+     *
+     * @param p_title title tag buffer
+     * @param p_artist artist tag buffer
+     * @param p_album album tag buffer
+     * @param tag_size tag buffer size
+     * @param fp file pointer
+     * @return true = success, false = failure
+     */
+    virtual bool AnalyzeHeder(char* p_title, char* p_artist, char* p_album, uint16_t tag_size, FILE* fp) = 0;
+
+    /** get next data
+     *
+     * @param buf data buffer address
+     * @param len data buffer length
+     * @return get data size
+     */
+    virtual size_t GetNextData(void *buf, size_t len) = 0;
+
+    /** get channel
+     *
+     * @return channel
+     */
+    virtual uint16_t GetChannel() = 0;
+
+    /** get block size
+     *
+     * @return block size
+     */
+    virtual uint16_t GetBlockSize() = 0;
+
+    /** get sampling rate
+     *
+     * @return sampling rate
+     */
+    virtual uint32_t GetSamplingRate() = 0;
+
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/DisplayBace.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,634 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+ * @file         DisplayBase.h
+ * @brief        Display driver wrapper class for GR-PEACH
+******************************************************************************/
+
+#ifndef MBED_DISPLAYBASE_H
+#define MBED_DISPLAYBASE_H
+
+#include "pinmap.h"
+
+/*! @class DisplayBase
+ *  @brief Display driver wrapper class for GR-PEACH
+ */
+class DisplayBase
+{
+
+public:
+    /*! @enum video_input_channel_t
+        @brief Video input channel select
+     */
+    typedef enum {
+        VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */
+        VIDEO_INPUT_CHANNEL_1      /*!< Video input channel 1 */
+    } video_input_channel_t;
+
+    /*! @enum video_adc_vinsel_t
+        @brief Input pin control
+     */
+    typedef enum {
+        VIDEO_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input            */
+        VIDEO_ADC_VINSEL_VIN2      /*!< VIN2 input            */
+    } video_adc_vinsel_t;
+
+    /*! @enum graphics_layer_t
+        @brief Graphics layer select
+     */
+    typedef enum {
+        GRAPHICS_LAYER_0 = 0,           /*!< Graphics layer 0         */
+        GRAPHICS_LAYER_1,               /*!< Graphics layer 1         */
+        GRAPHICS_LAYER_2,               /*!< Graphics layer 2         */
+        GRAPHICS_LAYER_3                /*!< Graphics layer 3         */
+    } graphics_layer_t;
+
+    /*! @enum graphics_error_t
+        @brief Error codes
+     */
+    typedef enum {
+        GRAPHICS_OK = 0,                   /*!< Normal termination       */
+        GRAPHICS_VDC5_ERR = -1,            /*!< VDC5 driver error        */
+        GRAPHICS_FORMA_ERR = -2,           /*!< Not support format       */
+        GRAPHICS_LAYER_ERR = -3,           /*!< Invalid layer ID error   */
+        GRAPHICS_CHANNLE_ERR = -4,         /*!< Invalid channel error */
+        GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */
+        GRAPHICS_VIDEO_PAL_SIZE_ERR = -6,  /*!< Video Write size(vw) error */
+        GRAPHICS_PARAM_RANGE_ERR = -7      /*!< Parameter range error */
+    } graphics_error_t;
+
+    /*! @enum graphics_format_t
+        @brief Graphics layer read format selects
+    */
+    typedef enum {
+        GRAPHICS_FORMAT_YCBCR422 = 0,      /*!< YCbCr422 (2byte / px)  */
+        GRAPHICS_FORMAT_RGB565,            /*!< RGB565   (2byte / px)  */
+        GRAPHICS_FORMAT_RGB888,            /*!< RGB888   (4byte / px)  */
+        GRAPHICS_FORMAT_ARGB8888,          /*!< ARGB8888 (4byte / px)  */
+        GRAPHICS_FORMAT_ARGB4444,          /*!< ARGB4444 (2byte / px)  */
+        GRAPHICS_FORMAT_CLUT8,             /*!< CLUT8    (1byte / px)  */
+        GRAPHICS_FORMAT_CLUT4,             /*!< CLUT4    (0.5byte / px)  */
+        GRAPHICS_FORMAT_CLUT1              /*!< CLUT1    (0.125byte / px)  */
+    } graphics_format_t;
+
+    /*! @enum video_format_t
+        @brief Video writing format selects
+     */
+    typedef enum {
+        VIDEO_FORMAT_YCBCR422 = 0,      /*!< YCbCr422 (2byte / px)    */
+        VIDEO_FORMAT_RGB565,            /*!< RGB565   (2byte / px)    */
+        VIDEO_FORMAT_RGB888,            /*!< RGB888   (4byte / px)    */
+        VIDEO_FORMAT_RAW8               /*!< RAW8     (1byte / px)    */
+    } video_format_t;
+
+    /*! @enum wr_rd_swa_t
+        @brief Frame buffer swap setting
+     */
+    typedef enum {
+        WR_RD_WRSWA_NON = 0,           /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+        WR_RD_WRSWA_8BIT,              /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+        WR_RD_WRSWA_16BIT,             /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+        WR_RD_WRSWA_16_8BIT,           /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+        WR_RD_WRSWA_32BIT,             /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+        WR_RD_WRSWA_32_8BIT,           /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+        WR_RD_WRSWA_32_16BIT,          /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+        WR_RD_WRSWA_32_16_8BIT,        /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    } wr_rd_swa_t;
+
+    /*! @enum lcd_tcon_pin_t
+        @brief LCD tcon output pin selects
+     */
+    typedef enum {
+        LCD_TCON_PIN_NON = -1,          /*!< Not using output         */
+        LCD_TCON_PIN_0,                 /*!< LCD_TCON0                */
+        LCD_TCON_PIN_1,                 /*!< LCD_TCON1                */
+        LCD_TCON_PIN_2,                 /*!< LCD_TCON2                */
+        LCD_TCON_PIN_3,                 /*!< LCD_TCON3                */
+        LCD_TCON_PIN_4,                 /*!< LCD_TCON4                */
+    } lcd_tcon_pin_t;
+
+    /*! @enum lcd_outformat_t
+        @brief LCD output format selects
+     */
+    typedef enum {
+        LCD_OUTFORMAT_RGB888 = 0,       /*!< RGB888 or LVDS           */
+        LCD_OUTFORMAT_RGB666,           /*!< RGB666                   */
+        LCD_OUTFORMAT_RGB565            /*!< RGB565                   */
+    } lcd_outformat_t;
+
+    /*! @enum edge_t
+        @brief Edge of a signal
+     */
+    typedef enum {
+        EDGE_RISING    = 0,             /*!< Rising edge              */
+        EDGE_FALLING   = 1              /*!< Falling edge             */
+    } edge_t;
+
+    /*! @enum lcd_type_t
+        @brief LCD type
+     */
+    typedef enum {
+        LCD_TYPE_LVDS = 0,              /*!< LVDS control                */
+        LCD_TYPE_PARALLEL_RGB           /*!< RGB parallel signal control */
+    } lcd_type_t;
+
+    /*! @enum sig_pol_t
+        @brief Polarity of a signal
+     */
+    typedef enum {
+        SIG_POL_NOT_INVERTED = 0,       /*!< Not inverted             */
+        SIG_POL_INVERTED                /*!< Inverted                 */
+    } sig_pol_t;
+
+    /*! @enum int_type_t
+        @brief Interrupt type
+     */
+    typedef enum {
+        INT_TYPE_S0_VI_VSYNC = 0,      /*!< Vsync signal input to scaler 0 */
+        INT_TYPE_S0_LO_VSYNC,          /*!< Vsync signal output from scaler 0 */
+        INT_TYPE_S0_VSYNCERR,          /*!< Missing Vsync signal for scaler 0 */
+        INT_TYPE_VLINE,                /*!< Specified line signal for panel output in graphics 3 */
+        INT_TYPE_S0_VFIELD,            /*!< Field end signal for recording function in scaler 0 */
+        INT_TYPE_IV1_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 0 */
+        INT_TYPE_IV3_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 0 */
+        INT_TYPE_IV5_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 2 */
+        INT_TYPE_IV6_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 3 */
+        INT_TYPE_S0_WLINE,             /*!< Write specification line signal input to scaling-down control block in scaler 0 */
+        INT_TYPE_S1_VI_VSYNC,          /*!< Vsync signal input to scaler 1 */
+        INT_TYPE_S1_LO_VSYNC,          /*!< Vsync signal output from scaler 1 */
+        INT_TYPE_S1_VSYNCERR,          /*!< Missing Vsync signal for scaler 1 */
+        INT_TYPE_S1_VFIELD,            /*!< Field end signal for recording function in scaler 1 */
+        INT_TYPE_IV2_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 1 */
+        INT_TYPE_IV4_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 1 */
+        INT_TYPE_S1_WLINE,             /*!< Write specification line signal input to scaling-down control block in scaler 1 */
+        INT_TYPE_OIR_VI_VSYNC,         /*!< Vsync signal input to output image generator */
+        INT_TYPE_OIR_LO_VSYNC,         /*!< Vsync signal output from output image generator */
+        INT_TYPE_OIR_VLINE,            /*!< Specified line signal for panel output in output image generator */
+        INT_TYPE_OIR_VFIELD,           /*!< Field end signal for recording function in output image generator */
+        INT_TYPE_IV7_VBUFERR,          /*!< Frame buffer write overflow signal for output image generator */
+        INT_TYPE_IV8_VBUFERR,          /*!< Frame buffer read underflow signal for graphics (OIR) */
+        INT_TYPE_NUM                   /*!< The number of VDC5 interrupt types */
+    } int_type_t;
+
+    /*! @enum graphics_video_col_sys_t
+        @brief Video color system
+     */
+    typedef enum {
+        COL_SYS_NTSC_358       = 0,        /*!< NTSC-3.58 */
+        COL_SYS_NTSC_443       = 1,        /*!< NTSC-4.43 */
+        COL_SYS_PAL_443        = 2,        /*!< PAL-4.43 */
+        COL_SYS_PAL_M          = 3,        /*!< PAL-M */
+        COL_SYS_PAL_N          = 4,        /*!< PAL-N */
+        COL_SYS_SECAM          = 5,        /*!< SECAM */
+        COL_SYS_NTSC_443_60    = 6,        /*!< NTSC-4.43 (60Hz) */
+        COL_SYS_PAL_60         = 7,        /*!< PAL-60 */
+    } graphics_video_col_sys_t;
+
+    /*! @enum video_input_sel_t
+        @brief External Input select
+     */
+    typedef enum {
+        INPUT_SEL_VDEC     = 0,            /*!< Video decoder output signals */
+        INPUT_SEL_EXT      = 1,            /*!< Signals supplied via the external input pins */
+        INPUT_SEL_CEU      = 2,            /*!< Signals supplied via the CEU input pins */
+        INPUT_SEL_MIPI     = 3             /*!< Signals supplied via the MIPI input pins */
+    } video_input_sel_t;
+
+    /*! @enum video_extin_format_t
+       @brief External input format select
+    */
+    typedef enum {
+        VIDEO_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 Not support */
+        VIDEO_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+        VIDEO_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+        VIDEO_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+        VIDEO_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+        VIDEO_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+        VIDEO_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 Not support */
+    } video_extin_format_t;
+
+    /*! @enum onoff_t
+        @brief On/off
+     */
+    typedef enum {
+        OFF    = 0,            /*!< Off */
+        ON     = 1             /*!< On */
+    } onoff_t;
+
+    /*! @enum extin_input_line_t
+        @brief Number of lines for BT.656 external input
+     */
+    typedef enum {
+        EXTIN_LINE_525     = 0,    /*!< 525 lines */
+        EXTIN_LINE_625     = 1     /*!< 625 lines */
+    } extin_input_line_t;
+
+    /*! @enum extin_h_pos_t
+        @brief Y/Cb/Y/Cr data string start timing
+     */
+    typedef enum {
+        EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+        EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+        EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+        EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+        EXTIN_H_POS_NUM
+    } extin_h_pos_t;
+
+    /*! @struct rect_t
+        @brief The relative position within the graphics display area
+     */
+    typedef struct {
+        unsigned short vs;          /*!< Vertical start pos       */
+        unsigned short vw;          /*!< Vertical width (height)  */
+        unsigned short hs;          /*!< Horizontal start pos     */
+        unsigned short hw;          /*!< Horizontal width         */
+    } rect_t;
+
+    /*! @struct clut_t
+        @brief CLUT setup parameter
+     */
+    typedef struct {
+        uint32_t            color_num;  /*!< The number of colors in CLUT */
+        const uint32_t    * clut;       /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
+    } clut_t;
+
+    /*! @struct lcd_config_t
+        @brief LCD configuration
+     */
+    typedef struct {
+        lcd_type_t      lcd_type;               /*!< LVDS or Pararel RGB                      */
+        double          intputClock;            /*!< P1  clk [MHz] ex. 66.67f                 */
+        double          outputClock;            /*!< LCD clk [MHz] ex. 33.33f                 */
+
+        lcd_outformat_t lcd_outformat;          /*!< Output format select */
+        edge_t          lcd_edge;               /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+        unsigned short  h_toatal_period;        /*!< Free-running Hsync period                */
+        unsigned short  v_toatal_period;        /*!< Free-running Vsync period                */
+        unsigned short  h_disp_widht;           /*!< LCD display area size, horizontal width  */
+        unsigned short  v_disp_widht;           /*!< LCD display area size, vertical width    */
+        unsigned short  h_back_porch;           /*!< LCD display horizontal back porch period */
+        unsigned short  v_back_porch;           /*!< LCD display vertical back porch period   */
+
+        lcd_tcon_pin_t  h_sync_port;            /*!< TCONn or Not use(-1)                     */
+        sig_pol_t       h_sync_port_polarity;   /*!< Polarity inversion control of signal     */
+        unsigned short  h_sync_width;           /*!< Hsync width                              */
+
+        lcd_tcon_pin_t  v_sync_port;            /*!< TCONn or Not use(-1)                     */
+        sig_pol_t       v_sync_port_polarity;   /*!< Polarity inversion control of signal     */
+        unsigned short  v_sync_width;           /*!< Vsync width  */
+
+        lcd_tcon_pin_t  de_port;                /*!< TCONn or Not use(-1)                     */
+        sig_pol_t       de_port_polarity;       /*!< Polarity inversion control of signal     */
+    } lcd_config_t;
+
+    /*! @struct video_ext_in_config_t
+        @brief Digital Video Input configuration
+     */
+    typedef struct {
+        video_extin_format_t     inp_format;    /*!< External Input Format Select                                */
+        edge_t                   inp_pxd_edge;  /*!< Clock Edge Select for Capturing External Input Video Image  */
+        edge_t                   inp_vs_edge;   /*!< Clock Edge Select for Capturing External Input Vsync Signal */
+        edge_t                   inp_hs_edge;   /*!< Clock Edge Select for Capturing External Input Hsync Signal */
+        onoff_t                  inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control               */
+        onoff_t                  inp_swap_on;   /*!< External Input Bit Endian Change On/Off Control             */
+        sig_pol_t                inp_vs_inv;    /*!< External Input Vsync Signal DV_VSYNC Inversion Control      */
+        sig_pol_t                inp_hs_inv;    /*!< External Input Hsync Signal DV_HSYNC Inversion Control      */
+        extin_input_line_t       inp_f525_625;  /*!< Number of lines for BT.656 external input */
+        extin_h_pos_t            inp_h_pos;     /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+        unsigned short           cap_vs_pos;    /*!< Capture start position from Vsync */
+        unsigned short           cap_hs_pos;    /*!< Capture start position form Hsync */
+        unsigned short           cap_width;     /*!< Capture width  */
+        unsigned short           cap_height;    /*!< Capture height should be a multiple of 4.*/
+    } video_ext_in_config_t;
+
+    /* mipi phy timing struct */
+    typedef struct {
+        uint16_t mipi_ths_prepare;  /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0 state) */
+        uint16_t mipi_ths_settle;   /*!< Setting of the period in which a transition to the HS state is ignored after the TTHS_PREPARE period begins */
+        uint16_t mipi_tclk_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0) */
+        uint16_t mipi_tclk_settle;  /*!< Setting of the period in which a transition to the HS state is ignored after the TCLK_PREPARE period begins */
+        uint16_t mipi_tclk_miss;    /*!< Setting of the period in which the absence of the clock is detected, and the HS-RX is disabled */
+        uint16_t mipi_t_init_slave; /*!< Minimum duration of the INIT state */
+    } video_mipi_phy_timing_t;
+
+    /* mipi parameter struct */
+    typedef struct {
+        uint8_t  mipi_lanenum;                 /*!< Mipi Lane Num */
+        uint8_t  mipi_vc;                      /*!< Mipi Virtual Channel */
+        uint8_t  mipi_interlace;               /*!< Interlace or Progressive */
+        uint8_t  mipi_laneswap;                /*!< Mipi Lane Swap Setting */
+        uint16_t mipi_frametop;                /*!< (for Interlace)Top Field Packet ID */
+        uint16_t mipi_outputrate;              /*!< Mipi Data Send Speed(Mbit per sec) */
+        video_mipi_phy_timing_t mipi_phy_timing;  /*!< Mipi D-PHY timing settings */
+    } video_mipi_param_t;
+
+    /*! Vin parameter Struct */
+    typedef struct {
+        uint16_t vin_preclip_starty;    /*!< Pre Area Clip Start Line */
+        uint16_t vin_preclip_endy;      /*!< Pre Area Clip End Line */
+        uint16_t vin_preclip_startx;    /*!< Pre Area Clip Start Column */
+        uint16_t vin_preclip_endx;      /*!< Pre Area Clip End Column */
+    } video_vin_preclip_t;
+
+    typedef struct {
+        uint8_t  vin_scaleon;           /*!< Scaling On or OFF */
+        uint8_t  vin_interpolation;     /*!< Scaling Interpolation */
+        uint16_t vin_scale_h;           /*!< Horizontal multiple */
+        uint16_t vin_scale_v;           /*!< vertical multiple */
+    } video_vin_scale_t;
+
+    typedef struct {
+        uint16_t vin_afterclip_size_x;  /*!< After Area Clip horizontal size */
+        uint16_t vin_afterclip_size_y;  /*!< After Area Clip vertical size */
+    } video_vin_afterclip_t;
+
+    /*! YCbCr422 input data alignment */
+    typedef enum
+    {
+        VIN_Y_UPPER = 0,  /*!< Upper bit is Y, lower bit is CbCr */
+        VIN_CB_UPPER,     /*!< Upper bit is CbCr, lower bit is Y */
+    } video_vin_input_align_t;
+
+    /*! Output data byte swap mode */
+    typedef enum
+    {
+        VIN_SWAP_OFF = 0,   /*!< Not swap */
+        VIN_SWAP_ON,        /*!< Swap */
+    } video_vin_output_swap_t;
+
+    typedef struct {
+        video_vin_preclip_t   vin_preclip;     /*!< Pre Area Clip Parameter */
+        video_vin_scale_t     vin_scale;       /*!< Scale Parameter */
+        video_vin_afterclip_t vin_afterclip;   /*!< After Area Clip Parameter */
+        uint8_t         vin_yuv_clip;       /*!< YUV Range Clip Parameter */
+        uint8_t         vin_lut;            /*!< LUT Conversion On or OFF */
+        uint8_t         vin_inputformat;    /*!< Input Image Format */
+        uint8_t         vin_outputformat;   /*!< Output Image Format */
+        uint8_t         vin_outputendian;   /*!< Output Data Endian*/
+        uint8_t         vin_dither;         /*!< (for RGB565 or ARGB1555)Output Data Dithering On or Off */
+        uint8_t         vin_interlace;      /*!< (for Interlace input)Capture Method */
+        uint8_t         vin_alpha_val8;     /*!< (for ARGB8888)Alpha Value */
+        uint8_t         vin_alpha_val1;     /*!< (for ARGB1555)Alpha Value */
+        uint16_t        vin_stride;         /*!< Stride (byte) */
+        uint32_t        vin_ycoffset;       /*!< (for YC separate output)Address Offset Value */
+        video_vin_input_align_t  vin_input_align;  /*!< YCbCr422 input data alignment */
+        video_vin_output_swap_t  vin_output_swap;  /*!< Output data byte swap mode */
+    } video_vin_setup_t;
+
+    /** Constructor method of display base object
+     */
+    DisplayBase( void );
+
+    /** Graphics initialization processing<br>
+     *  If not using display, set NULL in parameter.
+     *  @param[in]    lcd_config          : LCD configuration
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_init( const lcd_config_t * lcd_config );
+
+    /** Graphics Video initialization processing<br>
+     *  If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
+     *  @param[in]    video_input_sel     : Input select
+     *  @param[in]    video_ext_in_config : Video configuration
+     *  @retval       error code
+     */
+    graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config );
+
+    /** Graphics Video initialization processing<br>
+     *  @param[in]    video_input_sel     : Input select
+     *  @param[in]    video_mipi_config   : MIPI configuration
+     *  @param[in]    video_vin_setup     : MIPI configuration
+     *  @retval       error code
+     */
+    graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_mipi_param_t * video_mipi_config, video_vin_setup_t * video_vin_setup );
+
+    /** LCD output port initialization processing
+     *  @param[in]    pin                 : Pin assign for LCD output
+     *  @param[in]    pin_count           : Total number of pin assign
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count );
+
+    /** LVDS output port initialization processing
+     *  @param[in]    pin                 : Pin assign for LVDS output
+     *  @param[in]    pin_count           : Total number of pin assign
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count );
+
+    /** Digital video input port initialization processing
+     *  @param[in]    pin                 : Pin assign for digital video input port
+     *  @param[in]    pin_count           : Total number of pin assign
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count );
+
+    /** CEU input port initialization processing
+     *  @param[in]    pin                 : Pin assign for CEU input port
+     *  @param[in]    pin_count           : Total number of pin assign
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Ceu_Port_Init( PinName *pin, unsigned int pin_count );
+
+    /**  Interrupt callback setup
+     *  This function performs the following processing:
+     *  - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br>
+     *  - Registers the specified interrupt callback function.<br>
+     *  - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br>
+     *  @param[in]    Graphics_Irq_Handler_Set : VDC5 interrupt type
+     *  @param[in]    num                      : Interrupt line number
+     *  @param[in]    callback                 : Interrupt callback function pointer
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t)  );
+
+    /** Start the graphics surface read process
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Start( graphics_layer_t layer_id );
+
+    /** Stop the graphics surface read process
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Stop( graphics_layer_t layer_id );
+
+    /** Start the video surface write process
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Start ( video_input_channel_t video_input_channel );
+
+    /** Stop the video surface write process
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Stop ( video_input_channel_t video_input_channel );
+
+    /** Graphics surface read process setting
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @param[in]    fb_stride           : Line offset address of the frame buffer[byte]  <br />
+     *      Frame buffer stride should be set to a multiple of 32 or 128
+     *      in accordance with the frame buffer burst transfer mode.
+     *  @param[in]    gr_format           : Format of the frame buffer read signal <br />
+     *      - GRAPHICS_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+     *      - GRAPHICS_FORMAT_RGB565   : RGB565 (2byte/px)
+     *      - GRAPHICS_FORMAT_RGB888   : RGB888 (4byte/px)
+     *      - GRAPHICS_FORMAT_ARGB8888 : ARGB8888 (4byte/px)
+     *      - GRAPHICS_FORMAT_CLUT8    : CLUT8 (1byte/px)
+     *      - GRAPHICS_FORMAT_CLUT4    : CLUT4 (0.5byte/px)
+     *      - GRAPHICS_FORMAT_CLUT1    : CLUT1 (0,12byte/px)
+     *  @param[in]    wr_rd_swa : frame buffer swap setting <br />
+     *      -    WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+     *      -    WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+     *      -    WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+     *      -    WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+     *      -    WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+     *      -    WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+     *      -    WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+     *      -    WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+     *  @param[in]    gr_rect             : Graphics display area
+     *  @param[in]    gr_clut             : CLUT setup parameter
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Read_Setting (
+        graphics_layer_t    layer_id,
+        void              * framebuff,
+        unsigned int        fb_stride,
+        graphics_format_t   gr_format,
+        wr_rd_swa_t         wr_rd_swa,
+        rect_t            * gr_rect,
+        clut_t            * gr_clut = 0 );
+
+    /** Graphics surface read buffer change process
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Read_Change (
+        graphics_layer_t    layer_id,
+        void             *  framebuff);
+
+    /** Video surface write process setting
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *                If using digital input, this parameter is not referenced. <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @param[in]    col_sys             : Analog video signal color system <br />
+     *                If using digital input, this parameter is not referenced. <br />
+     *      - COL_SYS_NTSC_358    : NTSC-3.58
+     *      - COL_SYS_NTSC_443    : NTSC-4.43
+     *      - COL_SYS_PAL_443     : PAL-4.43
+     *      - COL_SYS_PAL_M       : PAL-M
+     *      - COL_SYS_PAL_N       : PAL-N
+     *      - COL_SYS_SECAM       : SECAM
+     *      - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz)
+     *      - COL_SYS_PAL_60      : PAL-60
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @param[in]    fb_stride           : Line offset address of the frame buffer[byte]  <br />
+     *      Frame buffer stride should be set to a multiple of 32 or 128
+     *      in accordance with the frame buffer burst transfer mode.
+     *  @param[in]    video_format        : Frame buffer video-signal writing format <br />
+     *      - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+     *      - VIDEO_FORMAT_RGB565   : RGB565 (2byte/px)
+     *      - VIDEO_FORMAT_RGB888   : RGB888 (4byte/px)
+     *  @param[in]    wr_rd_swa : frame buffer swap setting  <br />
+     *      -    WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+     *      -    WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+     *      -    WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+     *      -    WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+     *      -    WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+     *      -    WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+     *      -    WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+     *      -    WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+     *  @param[in]    video_write_buff_vw : Output height[px] <br />
+     *      - NTSC format : Max height is 480[px]
+     *      - PAL format  : Max height is 520[px]
+     *  @param[in]    video_write_buff_hw : Output width[px] <br />
+     *      - Max width : 800[px]
+     *  @param[in]    video_adc_vinsel : Input pin control <br />
+     *      - VIDEO_ADC_VINSEL_VIN1 : VIN1 input
+     *      - VIDEO_ADC_VINSEL_VIN2 : VIN2 input
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Write_Setting (
+        video_input_channel_t       video_input_channel,
+        graphics_video_col_sys_t    col_sys,
+        void                      * framebuff,
+        unsigned int                fb_stride,
+        video_format_t              video_format,
+        wr_rd_swa_t                 wr_rd_swa,
+        unsigned short              video_write_buff_vw,
+        unsigned short              video_write_buff_hw,
+        video_adc_vinsel_t          video_adc_vinsel = VIDEO_ADC_VINSEL_VIN1 );
+
+    /** Video surface write buffer change process
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @param[in]    fb_stride           : Line offset address of the frame buffer <br />
+     *      Frame buffer stride should be set to a multiple of 32 or 128
+     *      in accordance with the frame buffer burst transfer mode.
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Write_Change (
+        video_input_channel_t    video_input_channel,
+        void                   * framebuff,
+        uint32_t                 fb_stride );
+
+protected:
+    lcd_config_t          _lcd_config;
+    video_input_sel_t     _video_input_sel;
+    video_ext_in_config_t _video_ext_in_config;
+#if defined(TARGET_RZ_A2XX)
+    video_mipi_param_t    _video_mipi_config;
+    video_vin_setup_t     _video_vin_setup;
+#endif
+};
+
+
+#endif /* MBED_DISPLAYBASE_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/DisplayBase.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,531 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+#include <string.h>
+#include "DisplayBace.h"
+#include "gr_board_vdc5.h"
+
+/**************************************************************************//**
+ * @brief       Constructor of the DisplayBase class
+ * @param[in]   None
+ * @retval      None
+******************************************************************************/
+DisplayBase::DisplayBase( void )
+{
+    /* Lcd setting (default) */
+    _lcd_config.lcd_type             = LCD_TYPE_PARALLEL_RGB;       /* LVDS or Pararel RGB                      */
+    _lcd_config.intputClock          = 66.67f;                      /* P1  clk [MHz] ex. 66.67                  */
+    _lcd_config.outputClock          = 40.00f;                      /* LCD clk [MHz] ex. 33.33                  */
+
+    _lcd_config.lcd_outformat        = LCD_OUTFORMAT_RGB888;        /* Output format select */
+    _lcd_config.lcd_edge             = EDGE_FALLING;                /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+    _lcd_config.h_toatal_period      = (800u + 40u + 128u+ 88u);    /* Free-running Hsync period                */
+    _lcd_config.v_toatal_period      = (600u + 1u + 4u + 23u);      /* Free-running Vsync period                */
+    _lcd_config.h_disp_widht         = 800u;                        /* LCD display area size, horizontal width  */
+    _lcd_config.v_disp_widht         = 600u;                        /* LCD display area size, vertical width    */
+    _lcd_config.h_back_porch         = (128u+ 88u);                 /* LCD display horizontal back porch period */
+    _lcd_config.v_back_porch         = (4u + 23u);                  /* LCD display vertical back porch period   */
+
+    _lcd_config.h_sync_port          = LCD_TCON_PIN_0;              /* TCONn or Not use(-1)                     */
+    _lcd_config.h_sync_port_polarity = SIG_POL_NOT_INVERTED;        /* Polarity inversion control of signal     */
+    _lcd_config.h_sync_width         = 128u;                        /* Hsync width                              */
+
+    _lcd_config.v_sync_port          = LCD_TCON_PIN_1;              /* TCONn or Not use(-1)                     */
+    _lcd_config.v_sync_port_polarity = SIG_POL_NOT_INVERTED;        /* Polarity inversion control of signal     */
+    _lcd_config.v_sync_width         = 4u;                          /* Vsync width                              */
+
+    _lcd_config.de_port              = LCD_TCON_PIN_NON;            /* TCONn or Not use(-1)                     */
+    _lcd_config.de_port_polarity     = SIG_POL_NOT_INVERTED;        /* Polarity inversion control of signal     */
+
+    /* Digital video input setting (default) */
+    _video_input_sel                    = INPUT_SEL_VDEC;           /* Video decoder output signals */
+    _video_ext_in_config.inp_format     = VIDEO_EXTIN_FORMAT_BT601;
+    _video_ext_in_config.inp_pxd_edge   = EDGE_RISING;              /* Clock edge select for capturing data          */
+    _video_ext_in_config.inp_vs_edge    = EDGE_RISING;              /* Clock edge select for capturing Vsync signals */
+    _video_ext_in_config.inp_hs_edge    = EDGE_RISING;              /* Clock edge select for capturing Hsync signals */
+    _video_ext_in_config.inp_endian_on  = OFF;                      /* External input bit endian change on/off       */
+    _video_ext_in_config.inp_swap_on    = OFF;                      /* External input B/R signal swap on/off         */
+    _video_ext_in_config.inp_vs_inv     = SIG_POL_NOT_INVERTED;     /* External input DV_VSYNC inversion control     */
+    _video_ext_in_config.inp_hs_inv     = SIG_POL_INVERTED;         /* External input DV_HSYNC inversion control     */
+    _video_ext_in_config.inp_f525_625   = EXTIN_LINE_525;           /* Number of lines for BT.656 external input     */
+    _video_ext_in_config.inp_h_pos      = EXTIN_H_POS_CRYCBY;       /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    _video_ext_in_config.cap_vs_pos     = 6u;                       /* Capture start position from Vsync             */
+    _video_ext_in_config.cap_hs_pos     = 302u;                     /* Capture start position form Hsync             */
+    _video_ext_in_config.cap_width      = 640u;                     /* Capture width                                 */
+    _video_ext_in_config.cap_height     = 468u;                     /* Capture height should be a multiple of 4      */
+
+#if defined(TARGET_RZ_A2XX)
+    /* mipi */
+    _video_mipi_config.mipi_lanenum    = 2;
+    _video_mipi_config.mipi_vc         = 0;
+    _video_mipi_config.mipi_interlace  = 0;
+    _video_mipi_config.mipi_laneswap   = 0; /* Progressive */
+    _video_mipi_config.mipi_frametop   = 0;
+    _video_mipi_config.mipi_outputrate = 80;
+
+    _video_mipi_config.mipi_phy_timing.mipi_ths_prepare  = 0x00000012u;
+    _video_mipi_config.mipi_phy_timing.mipi_ths_settle   = 0x00000019u;
+    _video_mipi_config.mipi_phy_timing.mipi_tclk_prepare = 0x0000000Fu;
+    _video_mipi_config.mipi_phy_timing.mipi_tclk_settle  = 0x0000001Eu;
+    _video_mipi_config.mipi_phy_timing.mipi_tclk_miss    = 0x00000008u;
+    _video_mipi_config.mipi_phy_timing.mipi_t_init_slave = 0x0000338Fu;
+
+    memset(&_video_vin_setup, 0, sizeof(_video_vin_setup));
+#endif
+} /* End of constructor method () */
+
+/**************************************************************************//**
+ * @brief       Graphics initialization processing
+ * @param[in]   lcd_config                : LCD configuration
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_init( const lcd_config_t * lcd_config )
+{
+    if( lcd_config != NULL ) {
+        _lcd_config.lcd_type             = lcd_config->lcd_type;            /* LVDS or Pararel RGB                      */
+        _lcd_config.intputClock          = lcd_config->intputClock;         /* P1  clk [MHz] ex. 66.67                  */
+        _lcd_config.outputClock          = lcd_config->outputClock;         /* LCD clk [MHz] ex. 33.33                  */
+
+        _lcd_config.lcd_outformat        = lcd_config->lcd_outformat;       /* Output format select */
+        _lcd_config.lcd_edge             = lcd_config->lcd_edge;            /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+        _lcd_config.h_toatal_period      = lcd_config->h_toatal_period;     /* Free-running Hsync period                */
+        _lcd_config.v_toatal_period      = lcd_config->v_toatal_period;     /* Free-running Vsync period                */
+        _lcd_config.h_disp_widht         = lcd_config->h_disp_widht;        /* LCD display area size, horizontal width  */
+        _lcd_config.v_disp_widht         = lcd_config->v_disp_widht;        /* LCD display area size, vertical width    */
+        _lcd_config.h_back_porch         = lcd_config->h_back_porch;        /* LCD display horizontal back porch period */
+        _lcd_config.v_back_porch         = lcd_config->v_back_porch;        /* LCD display vertical back porch period   */
+
+        _lcd_config.h_sync_port          = lcd_config->h_sync_port;         /* TCONn or Not use(-1)                     */
+        _lcd_config.h_sync_port_polarity = lcd_config->h_sync_port_polarity;/* Polarity inversion control of signal     */
+        _lcd_config.h_sync_width         = lcd_config->h_sync_width;        /* Hsync width                              */
+
+        _lcd_config.v_sync_port          = lcd_config->v_sync_port;         /* TCONn or Not use(-1)                     */
+        _lcd_config.v_sync_port_polarity = lcd_config->v_sync_port_polarity;/* Polarity inversion control of signal     */
+        _lcd_config.v_sync_width         = lcd_config->v_sync_width;        /* Vsync width  */
+
+        _lcd_config.de_port              = lcd_config->de_port;             /* TCONn or Not use(-1)                     */
+        _lcd_config.de_port_polarity     = lcd_config->de_port_polarity;    /* Polarity inversion control of signal     */
+    }
+
+    return (graphics_error_t)DRV_Graphics_Init( (drv_lcd_config_t *)&_lcd_config );
+} /* End of method Graphics_init() */
+
+/**************************************************************************//**
+ * @brief       Graphics Video initialization processing
+ * @param[in]   video_input_sel                : Input select
+ * @param[in]   video_ext_in_config            : Digtal video input configuration
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config )
+{
+    graphics_error_t error;
+
+    if ((video_input_sel == INPUT_SEL_EXT)
+     || (video_input_sel == INPUT_SEL_CEU)) {
+        _video_input_sel = video_input_sel;
+
+        if (video_ext_in_config != NULL) {
+            /* Signals supplied via the external input pins        */
+            /* if using Video decoder output signals, not using value. */
+            _video_ext_in_config.inp_format    = video_ext_in_config->inp_format;
+            _video_ext_in_config.inp_pxd_edge  = video_ext_in_config->inp_pxd_edge;
+            _video_ext_in_config.inp_vs_edge   = video_ext_in_config->inp_vs_edge;
+            _video_ext_in_config.inp_hs_edge   = video_ext_in_config->inp_hs_edge;
+            _video_ext_in_config.inp_endian_on = video_ext_in_config->inp_endian_on;
+            _video_ext_in_config.inp_swap_on   = video_ext_in_config->inp_swap_on;
+            _video_ext_in_config.inp_vs_inv    = video_ext_in_config->inp_vs_inv;
+            _video_ext_in_config.inp_hs_inv    = video_ext_in_config->inp_hs_inv;
+            _video_ext_in_config.inp_f525_625  = video_ext_in_config->inp_f525_625;
+            _video_ext_in_config.inp_h_pos     = video_ext_in_config->inp_h_pos;
+            _video_ext_in_config.cap_vs_pos    = video_ext_in_config->cap_vs_pos;
+            _video_ext_in_config.cap_hs_pos    = video_ext_in_config->cap_hs_pos;
+            _video_ext_in_config.cap_width     = video_ext_in_config->cap_width;
+            _video_ext_in_config.cap_height    = video_ext_in_config->cap_height;
+        }
+        error = (graphics_error_t)DRV_Graphics_Video_init( (drv_video_input_sel_t)video_input_sel,
+                (drv_video_ext_in_config_t *)&_video_ext_in_config );
+    } else {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+
+    return error;
+} /* End of method Graphics_Video_init() */
+
+/**************************************************************************//**
+ * @brief       Graphics Video initialization processing
+ * @param[in]   video_input_sel                : Input select
+ * @param[in]   video_mipi_config              : MIPI configuration
+ * @param[in]   video_vin_setup                : MIPI configuration
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Video_init( video_input_sel_t video_input_sel, video_mipi_param_t * video_mipi_config, video_vin_setup_t * video_vin_setup )
+{
+    graphics_error_t error = GRAPHICS_VDC5_ERR;
+
+#if defined(TARGET_RZ_A2XX)
+    if (video_input_sel == INPUT_SEL_MIPI) {
+        _video_input_sel = video_input_sel;
+
+        if (video_mipi_config != NULL) {
+            memcpy(&_video_mipi_config, video_mipi_config, sizeof(_video_mipi_config));
+        }
+        if (video_vin_setup != NULL) {
+            memcpy(&_video_vin_setup, video_vin_setup, sizeof(_video_vin_setup));
+        }
+        error = (graphics_error_t)DRV_Graphics_Video_init( (drv_video_input_sel_t)video_input_sel,
+                (drv_video_ext_in_config_t *)&_video_ext_in_config );
+    } else {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+#endif
+
+    return error;
+} /* End of method Graphics_Video_init() */
+
+/**************************************************************************//**
+ * @brief       LCD I/O initialization processing
+ * @param[in]   pin                       : Pointer of the pin assignment
+ * @param[in]   pin_count                 : Total number of the pin assignment
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count )
+{
+    return (graphics_error_t)DRV_Graphics_Lcd_Port_Init( pin, pin_count );
+} /* End of method Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       LVDS I/O port initialization processing
+ * @param[in]   pin                       : Pointer of the pin assignment
+ * @param[in]   pin_count                 : Total number of the pin assignment
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count )
+{
+    return (graphics_error_t)DRV_Graphics_Lvds_Port_Init( pin, pin_count );
+} /* End of method Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Digital video input I/O port initialization processing
+ * @param[in]   pin                       : Pointer of the pin assignment
+ * @param[in]   pin_count                 : Total number of the pin assignment
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count )
+{
+    return (graphics_error_t)DRV_Graphics_Dvinput_Port_Init( pin, pin_count );
+} /* End of method Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       CEU input I/O port initialization processing
+ * @param[in]   pin                       : Pointer of the pin assignment
+ * @param[in]   pin_count                 : Total number of the pin assignment
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Ceu_Port_Init( PinName *pin, unsigned int pin_count )
+{
+    return (graphics_error_t)DRV_Graphics_CEU_Port_Init( pin, pin_count );
+} /* End of method Graphics_Ceu_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       IRQ interrupt handler setting
+ * @param[in]   irq                       : VDC5 interrupt type
+ * @param[in]   num                       : Interrupt line number
+ * @param[in]   * callback                : Interrupt callback function pointer
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Irq_Handler_Set( int_type_t irq, unsigned short num, void (* callback)(int_type_t)  )
+{
+    return (graphics_error_t)DRV_Graphics_Irq_Handler_Set( (vdc5_int_type_t)irq, num, (void (*)(vdc5_int_type_t))callback );
+} /* End of method Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read start processing
+ * @param[in]   layer_id                  : Graphics layer ID
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Start( graphics_layer_t layer_id )
+{
+    return (graphics_error_t)DRV_Graphics_Start( (drv_graphics_layer_t)layer_id );
+} /* End of method Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read stop processing
+ * @param[in]   layer_id                  : Graphics layer ID
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Stop( graphics_layer_t layer_id )
+{
+    return (graphics_error_t)DRV_Graphics_Stop( (drv_graphics_layer_t)layer_id );
+} /* End of method Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief       Video surface write start processing
+ * @param[in]   video_input_channel        : Video input channel
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Start( video_input_channel_t video_input_channel )
+{
+    graphics_error_t error = GRAPHICS_OK;
+
+    /*  Digital video inputs : supporting video_input_channel 0 only. */
+    if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+
+    if( error == GRAPHICS_OK ) {
+        error = (graphics_error_t)DRV_Video_Start( (drv_video_input_channel_t)video_input_channel );
+    }
+    return error;
+} /* End of method Video_Start() */
+
+/**************************************************************************//**
+ * @brief       Video surface write stop processing
+ * @param[in]   video_input_channel        : Video input channel
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Stop( video_input_channel_t video_input_channel )
+{
+    graphics_error_t error = GRAPHICS_OK;
+
+    /*  Digital video inputs : supporting video_input_channel 0 only. */
+    if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+
+    if( error == GRAPHICS_OK ) {
+        error = (graphics_error_t)DRV_Video_Stop(
+                    (drv_video_input_channel_t)video_input_channel );
+    }
+    return error;
+} /* End of method Video_Stop() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process setting
+ *
+ *              Description:<br>
+ *              This function supports the following 4 image format.
+ *                  YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in]   layer_id                   : Graphics layer ID
+ * @param[in]   framebuff                  : Base address of the frame buffer
+ * @param[in]   fb_stride                  : Line offset address of the frame buffer
+ * @param[in]   gr_format                  : Format of the frame buffer read signal
+ * @param[in]   wr_rd_swa                  : frame buffer swap setting
+ *      - WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+ *      - WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ *      - WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ *      - WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ *      - WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ *      - WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ *      - WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ *      - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in]   gr_rect                    : Graphics display area
+ * @param[in]   gr_clut                    : CLUT setup parameter
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Read_Setting(
+    graphics_layer_t    layer_id,
+    void              * framebuff,
+    unsigned int        fb_stride,
+    graphics_format_t   gr_format,
+    wr_rd_swa_t         wr_rd_swa,
+    rect_t            * gr_rect,
+    clut_t            * gr_clut )
+{
+    rect_t rect;
+
+    rect.hs = gr_rect->hs + _lcd_config.h_back_porch;
+    rect.vs = gr_rect->vs + _lcd_config.v_back_porch;
+    rect.hw = gr_rect->hw;
+    rect.vw = gr_rect->vw;
+
+    return (graphics_error_t)DRV_Graphics_Read_Setting(
+               (drv_graphics_layer_t)layer_id,
+               framebuff,
+               fb_stride,
+               (drv_graphics_format_t)gr_format,
+               (drv_wr_rd_swa_t)wr_rd_swa,
+               (drv_rect_t *)&rect,
+               (drv_clut_t *)gr_clut);
+} /* End of method Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process changing
+ *
+ *              Description:<br>
+ *              This function is used to swap buffers.
+ *
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Read_Change ( graphics_layer_t layer_id, void *  framebuff)
+{
+    return (graphics_error_t)DRV_Graphics_Read_Change(
+               (drv_graphics_layer_t)layer_id, framebuff );
+} /* End of method Graphics_Read_Change() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting
+ *              This function set the video write process. Input form is weave
+ *              (progressive) mode fixed.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   video_input_ch          : Video input channel
+ * @param[in]   col_sys                 : Analog video signal color system
+ * @param[in]   adc_vinsel              : Video input pin
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ *      - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+ *      - VIDEO_FORMAT_RGB565   : RGB565 (2byte/px)
+ *      - VIDEO_FORMAT_RGB888   : RGB888 (4byte/px)
+ * @param[in]   wr_rd_swa               : frame buffer swap setting
+ *      - WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+ *      - WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ *      - WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ *      - WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ *      - WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ *      - WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ *      - WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ *      - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in]   video_write_size_vw [px]: output v width
+ * @param[in]   video_write_size_hw [px]: output h width
+ * @param[in]   video_adc_vinsel        : Input pin control
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Write_Setting(
+    video_input_channel_t       video_input_channel,
+    graphics_video_col_sys_t    col_sys,
+    void                      * framebuff,
+    unsigned int                fb_stride,
+    video_format_t              video_format,
+    wr_rd_swa_t                 wr_rd_swa,
+    unsigned short              write_buff_vw,
+    unsigned short              write_buff_hw,
+    video_adc_vinsel_t          video_adc_vinsel )
+
+{
+    graphics_error_t error = GRAPHICS_OK;
+
+    if( _video_input_sel == INPUT_SEL_VDEC ) {
+        if( col_sys == COL_SYS_NTSC_358 || col_sys == COL_SYS_NTSC_443 || col_sys == COL_SYS_NTSC_443_60 ) {
+            if( (write_buff_vw / 2u) > 240u ) {
+                error = GRAPHICS_VIDEO_NTSC_SIZE_ERR;
+            }
+        } else {
+            if( (write_buff_vw / 2u) > 280u ) {
+                error = GRAPHICS_VIDEO_PAL_SIZE_ERR;
+            }
+        }
+
+        if( write_buff_hw > 800u ) {
+            error = GRAPHICS_PARAM_RANGE_ERR;
+        }
+        if( error == GRAPHICS_OK ) {
+            error = (graphics_error_t)DRV_Video_Write_Setting(
+                        (drv_video_input_channel_t)video_input_channel,
+                        (drv_graphics_video_col_sys_t)col_sys,
+                        framebuff,
+                        fb_stride,
+                        (drv_video_format_t)video_format,
+                        (drv_wr_rd_swa_t)wr_rd_swa,
+                        write_buff_vw,
+                        write_buff_hw,
+                        (drv_video_adc_vinsel_t)video_adc_vinsel);
+        }
+    } else if( _video_input_sel == INPUT_SEL_EXT ) {
+        rect_t cap_area;
+
+        cap_area.hs = _video_ext_in_config.cap_hs_pos * 2;
+        cap_area.hw = _video_ext_in_config.cap_width  * 2;
+        cap_area.vs = _video_ext_in_config.cap_vs_pos;
+        cap_area.vw = _video_ext_in_config.cap_height;
+
+        error = (graphics_error_t) DRV_Video_Write_Setting_Digital(
+                    framebuff,
+                    fb_stride,
+                    (drv_video_format_t)video_format,
+                    (drv_wr_rd_swa_t)wr_rd_swa,
+                    write_buff_vw,
+                    write_buff_hw,
+                    (drv_rect_t *)&cap_area );
+    } else if( _video_input_sel == INPUT_SEL_CEU ) {
+        error = (graphics_error_t) DRV_Video_Write_Setting_Ceu(
+                    framebuff,
+                    fb_stride,
+                    (drv_video_format_t)video_format,
+                    (drv_wr_rd_swa_t)wr_rd_swa,
+                    write_buff_vw,
+                    write_buff_hw,
+                    (drv_video_ext_in_config_t *)&_video_ext_in_config);
+#if defined(TARGET_RZ_A2XX)
+    } else if( _video_input_sel == INPUT_SEL_MIPI ) {
+        error = (graphics_error_t) DRV_Video_Write_Setting_Mipi(
+                    framebuff,
+                    fb_stride,
+                    (drv_video_format_t)video_format,
+                    (drv_wr_rd_swa_t)wr_rd_swa,
+                    write_buff_vw,
+                    write_buff_hw,
+                    (drv_mipi_param_t *)&_video_mipi_config,
+                    (drv_vin_setup_t *)&_video_vin_setup);
+#endif
+    } else {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+    return error;
+} /* End of method Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface write process changing
+ *              This function is used to swap buffers of the weave write processing.
+ * @param[in]   video_input_ch          : Video input channle
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Write_Change (
+    video_input_channel_t video_input_channel, void * framebuff, uint32_t fb_stride )
+{
+    return (graphics_error_t)DRV_Video_Write_Change(
+               (drv_video_input_channel_t)video_input_channel, framebuff, fb_stride );
+} /* End of method Video_Write_Change() */
+
+/* End of file */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/gr_board_vdc5.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,448 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         gr_board_vdc5.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Graphics driver wrapper function definitions in C
+******************************************************************************/
+
+#ifndef GR_BOARD_VDC5_H
+#define GR_BOARD_VDC5_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+#if defined(TARGET_RZ_A1XX)
+#include    "r_vdc5.h"
+#else
+#include    "r_vdc.h"
+#define vdc5_irq_handler      vdc_irq_handler
+#define vdc5_int_type_t       vdc_int_type_t
+#endif
+#include    "pinmap.h"
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define VSYNC_1_2_FH_TIMING    (858u)   /* Vsync signal 1/2fH phase timing */
+#define VSYNC_1_4_FH_TIMING    (429u)   /* Vsync signal 1/4fH phase timing */
+#define DEFAULT_INPUT_CLOCK    (66.67)  /* P1 clock VDC5 */
+#define DEFAULT_OUTPUT_CLOCK   (66.67)  /* LVDS output clock */
+
+#define     IMGCAP_SIZE_NTSC_HS         (122u)
+#define     IMGCAP_SIZE_NTSC_HW         (720u)
+#define     IMGCAP_SIZE_NTSC_VS         (16u)
+#define     IMGCAP_SIZE_NTSC_VW         (240u)
+
+#define     IMGCAP_SIZE_PAL_HS          (132u)
+#define     IMGCAP_SIZE_PAL_HW          (720u)
+#define     IMGCAP_SIZE_PAL_VS          (19u)
+#define     IMGCAP_SIZE_PAL_VW          (280u)
+
+typedef void (*vdc5_irq_handler)(uint32_t int_sense);
+
+/* video channel select */
+typedef enum {
+    DRV_VIDEO_INPUT_CHANNEL_0 = 0,      /* video input channel 0    */
+    DRV_VIDEO_INPUT_CHANNEL_1           /* video input channel 1    */
+} drv_video_input_channel_t;
+
+/* input pin control */
+typedef enum {
+    DRV_VIDEO_ADC_VINSEL_VIN1 = 0,      /* VIN1 input               */
+    DRV_VIDEO_ADC_VINSEL_VIN2           /* VIN2 input               */
+} drv_video_adc_vinsel_t;
+
+/* graphics layer select */
+typedef enum {
+    DRV_GRAPHICS_LAYER_0 = 0,           /* graphics layer 0         */
+    DRV_GRAPHICS_LAYER_1,               /* graphics layer 1         */
+    DRV_GRAPHICS_LAYER_2,               /* graphics layer 2         */
+    DRV_GRAPHICS_LAYER_3                /* graphics layer 3         */
+} drv_graphics_layer_t;
+
+/* error codes */
+typedef enum {
+    DRV_GRAPHICS_OK = 0,                /* Normal termination       */
+    DRV_GRAPHICS_VDC5_ERR = -1,         /* VDC5 error               */
+    DRV_GRAPHICS_FORMAT_ERR = -2,       /* Not support format       */
+    DRV_GRAPHICS_LAYER_ERR = -3,        /* Invalid layer ID error   */
+    DRV_GRAPHICS_CHANNEL_ERR = -4,      /* Invalid channel error    */
+    DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write           */
+    DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6,  /* Video Write           */
+    DRV_GRAPHICS_PARAM_RANGE_ERR = -7   /* Parameter range error    */
+} drv_graphics_error_t;
+
+/* graphics layer format select */
+typedef enum {
+    DRV_GRAPHICS_FORMAT_YCBCR422 = 0,   /* YCbCr422                 */
+    DRV_GRAPHICS_FORMAT_RGB565,         /* RGB565                   */
+    DRV_GRAPHICS_FORMAT_RGB888,         /* RGB888                   */
+    DRV_GRAPHICS_FORMAT_ARGB8888,       /* ARGB8888                 */
+    DRV_GRAPHICS_FORMAT_ARGB4444,       /* ARGB4444                 */
+    DRV_GRAPHICS_FORMAT_CLUT8,          /* CLUT8                    */
+    DRV_GRAPHICS_FORMAT_CLUT4,          /* CLUT4                    */
+    DRV_GRAPHICS_FORMAT_CLUT1           /* CLUT1                    */
+} drv_graphics_format_t;
+
+/* video writing format select */
+typedef enum {
+    DRV_VIDEO_FORMAT_YCBCR422 = 0,      /* YCbCr422                 */
+    DRV_VIDEO_FORMAT_RGB565,            /* RGB565                   */
+    DRV_VIDEO_FORMAT_RGB888,            /* RGB888                   */
+    DRV_VIDEO_FORMAT_RAW8               /* RAW8                   */
+} drv_video_format_t;
+
+
+/* lcd tcon output pin select */
+typedef enum {
+    DRV_LCD_TCON_PIN_NON = -1,          /* Not using output         */
+    DRV_LCD_TCON_PIN_0,                 /* LCD_TCON0                */
+    DRV_LCD_TCON_PIN_1,                 /* LCD_TCON1                */
+    DRV_LCD_TCON_PIN_2                  /* LCD_TCON2                */
+} drv_lcd_tcon_pin_t;
+
+/* lcd output format select */
+typedef enum {
+    DRV_LCD_OUTFORMAT_RGB888 = 0,       /* RGB888 or LVDS           */
+    DRV_LCD_OUTFORMAT_RGB666,           /* RGB666                   */
+    DRV_LCD_OUTFORMAT_RGB565            /* RGB565                   */
+} drv_lcd_outformat_t;
+
+/* frame buffer swap setting */
+typedef enum {
+    DRV_WR_RD_WRSWA_NON = 0,           /* Not swapped: 1-2-3-4-5-6-7-8 */
+    DRV_WR_RD_WRSWA_8BIT,              /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+    DRV_WR_RD_WRSWA_16BIT,             /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+    DRV_WR_RD_WRSWA_16_8BIT,           /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+    DRV_WR_RD_WRSWA_32BIT,             /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+    DRV_WR_RD_WRSWA_32_8BIT,           /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+    DRV_WR_RD_WRSWA_32_16BIT,          /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+    DRV_WR_RD_WRSWA_32_16_8BIT,        /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+} drv_wr_rd_swa_t;
+
+/* edge of a signal */
+typedef enum {
+    DRV_EDGE_RISING    = 0,             /* Rising edge              */
+    DRV_EDGE_FALLING   = 1              /* Falling edge             */
+} drv_edge_t;
+
+/* lcd type */
+typedef enum {
+    DRV_LCD_TYPE_LVDS = 0,              /* LVDS signal control      */
+    DRV_LCD_TYPE_PARALLEL_RGB           /* RGB parallel signal control */
+} drv_lcd_type_t;
+
+/* Polarity of a signal */
+typedef enum {
+    DRV_SIG_POL_NOT_INVERTED = 0,       /* Not inverted             */
+    DRV_SIG_POL_INVERTED                /* Inverted                 */
+} drv_sig_pol_t;
+
+/* Video color system */
+typedef enum {
+    DRV_COL_SYS_NTSC_358       = 0,        /* NTSC-3.58 */
+    DVV_COL_SYS_NTSC_443       = 1,        /* NTSC-4.43 */
+    DRV_COL_SYS_PAL_443        = 2,        /* PAL-4.43 */
+    DRV_COL_SYS_PAL_M          = 3,        /* PAL-M */
+    DRV_COL_SYS_PAL_N          = 4,        /* PAL-N */
+    DRV_COL_SYS_SECAM          = 5,        /* SECAM */
+    DRV_COL_SYS_NTSC_443_60    = 6,        /* NTSC-4.43 (60Hz) */
+    DRV_COL_SYS_PAL_60         = 7,        /* PAL-60 */
+} drv_graphics_video_col_sys_t;
+
+/* External Input select */
+typedef enum {
+    DRV_INPUT_SEL_VDEC     = 0,            /*!< Video decoder output signals */
+    DRV_INPUT_SEL_EXT      = 1,            /*!< Signals supplied via the external input pins */
+    DRV_INPUT_SEL_CEU      = 2,            /*!< Signals supplied via the CEU input pins */
+    DRV_INPUT_SEL_MIPI     = 3             /*!< Signals supplied via the MIPI input pins */
+} drv_video_input_sel_t;
+
+/* External input format select  */
+typedef enum {
+    DRV_VIDEO_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 Not support */
+    DRV_VIDEO_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+    DRV_VIDEO_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+    DRV_VIDEO_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+    DRV_VIDEO_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+    DRV_VIDEO_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+    DRV_VIDEO_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 Not support */
+} drv_video_extin_format_t;
+
+/* On/off */
+typedef enum {
+    DRV_OFF    = 0,                      /*!< Off */
+    DRV_ON     = 1                       /*!< On */
+} drv_onoff_t;
+
+/* Number of lines for BT.656 external input  */
+typedef enum {
+    DRV_EXTIN_LINE_525     = 0,    /*!< 525 lines */
+    DRV_EXTIN_LINE_625     = 1     /*!< 625 lines */
+} drv_extin_input_line_t;
+
+/* Y/Cb/Y/Cr data string start timing */
+typedef enum {
+    DRV_EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+    DRV_EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+    DRV_EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+    DRV_EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+} drv_extin_h_pos_t;
+
+/* The relative position within the graphics display area */
+typedef struct {
+    uint16_t   vs;                  /* Vertical start pos       */
+    uint16_t   vw;                  /* Vertical width (height)  */
+    uint16_t   hs;                  /* Horizontal start pos     */
+    uint16_t   hw;                  /* Horizontal width         */
+} drv_rect_t;
+
+/*! CLUT setup parameter */
+typedef struct {
+    uint32_t            color_num;  /*!< The number of colors in CLUT */
+    const uint32_t    * clut;       /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
+} drv_clut_t;
+
+/* lcd configuration  */
+typedef struct {
+    drv_lcd_type_t      lcd_type;               /* LVDS or Pararel RGB                      */
+    double              intputClock;            /* P1  clk [MHz] ex. 66.67                  */
+    double              outputClock;            /* LCD clk [MHz] ex. 33.33                  */
+
+    drv_lcd_outformat_t lcd_outformat;          /* Output format select */
+    drv_edge_t          lcd_edge;               /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+    uint16_t            h_toatal_period;        /* Free-running Hsync period                */
+    uint16_t            v_toatal_period;        /* Free-running Vsync period                */
+    uint16_t            h_disp_widht;           /* LCD display area size, horizontal width  */
+    uint16_t            v_disp_widht;           /* LCD display area size, vertical width    */
+    uint16_t            h_back_porch;           /* LCD display horizontal back porch period */
+    uint16_t            v_back_porch;           /* LCD display vertical back porch period   */
+
+    drv_lcd_tcon_pin_t  h_sync_port;            /* TCONn or Not use(-1)                     */
+    drv_sig_pol_t       h_sync_port_polarity;   /* Polarity inversion control of signal     */
+    uint16_t            h_sync_width;           /* Hsync width                              */
+
+    drv_lcd_tcon_pin_t  v_sync_port;            /* TCONn or Not use(-1)                     */
+    drv_sig_pol_t       v_sync_port_polarity;   /* Polarity inversion control of signal     */
+    uint16_t            v_sync_width;           /* Vsync width  */
+
+    drv_lcd_tcon_pin_t  de_port;                /* TCONn or Not use(-1)                     */
+    drv_sig_pol_t       de_port_polarity;       /* Polarity inversion control of signal     */
+
+} drv_lcd_config_t;
+
+/* Digital video input configuration  */
+typedef struct {
+    drv_video_extin_format_t     inp_format;    /*!< External Input Format Select                                */
+    drv_edge_t                   inp_pxd_edge;  /*!< Clock Edge Select for Capturing External Input Video Image  */
+    drv_edge_t                   inp_vs_edge;   /*!< Clock Edge Select for Capturing External Input Vsync Signal */
+    drv_edge_t                   inp_hs_edge;   /*!< Clock Edge Select for Capturing External Input Hsync Signal */
+    drv_onoff_t                  inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control               */
+    drv_onoff_t                  inp_swap_on;   /*!< External Input Bit Endian Change On/Off Control             */
+    drv_sig_pol_t                inp_vs_inv;    /*!< External Input Vsync Signal DV_VSYNC Inversion Control      */
+    drv_sig_pol_t                inp_hs_inv;    /*!< External Input Hsync Signal DV_HSYNC Inversion Control      */
+    drv_extin_input_line_t       inp_f525_625;  /*!< Number of lines for BT.656 external input */
+    drv_extin_h_pos_t            inp_h_pos;     /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+    unsigned short               cap_vs_pos;    /*!< Capture start position from Vsync */
+    unsigned short               cap_hs_pos;    /*!< Capture start position form Hsync */
+    unsigned short               cap_width;     /*!< Capture width  */
+    unsigned short               cap_height;    /*!< Capture height should be a multiple of 4.*/
+} drv_video_ext_in_config_t;
+
+/* mipi phy timing struct */
+typedef struct
+{
+    uint16_t mipi_ths_prepare;  /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0 state) */
+    uint16_t mipi_ths_settle;   /*!< Setting of the period in which a transition to the HS state is ignored after the TTHS_PREPARE period begins */
+    uint16_t mipi_tclk_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0) */
+    uint16_t mipi_tclk_settle;  /*!< Setting of the period in which a transition to the HS state is ignored after the TCLK_PREPARE period begins */
+    uint16_t mipi_tclk_miss;    /*!< Setting of the period in which the absence of the clock is detected, and the HS-RX is disabled */
+    uint16_t mipi_t_init_slave; /*!< Minimum duration of the INIT state */
+} drv_mipi_phy_timing_t;
+
+/* mipi parameter struct */
+typedef struct
+{
+    uint8_t  mipi_lanenum;                 /*!< Mipi Lane Num */
+    uint8_t  mipi_vc;                      /*!< Mipi Virtual Channel */
+    uint8_t  mipi_interlace;               /*!< Interlace or Progressive */
+    uint8_t  mipi_laneswap;                /*!< Mipi Lane Swap Setting */
+    uint16_t mipi_frametop;                /*!< (for Interlace)Top Field Packet ID */
+    uint16_t mipi_outputrate;              /*!< Mipi Data Send Speed(Mbit per sec) */
+    drv_mipi_phy_timing_t mipi_phy_timing;  /*!< Mipi D-PHY timing settings */
+} drv_mipi_param_t;
+
+/*! Vin parameter Struct */
+typedef struct
+{
+    uint16_t vin_preclip_starty;    /*!< Pre Area Clip Start Line */
+    uint16_t vin_preclip_endy;      /*!< Pre Area Clip End Line */
+    uint16_t vin_preclip_startx;    /*!< Pre Area Clip Start Column */
+    uint16_t vin_preclip_endx;      /*!< Pre Area Clip End Column */
+} drv_vin_preclip_t;
+
+typedef struct
+{
+    uint8_t  vin_scaleon;           /*!< Scaling On or OFF */
+    uint8_t  vin_interpolation;     /*!< Scaling Interpolation */
+    uint16_t vin_scale_h;           /*!< Horizontal multiple */
+    uint16_t vin_scale_v;           /*!< vertical multiple */
+} drv_vin_scale_t;
+
+typedef struct
+{
+    uint16_t vin_afterclip_size_x;  /*!< After Area Clip horizontal size */
+    uint16_t vin_afterclip_size_y;  /*!< After Area Clip vertical size */
+} drv_vin_afterclip_t;
+
+/*! YCbCr422 input data alignment */
+typedef enum
+{
+    __VIN_Y_UPPER = 0,  /*!< Upper bit is Y, lower bit is CbCr */
+    __VIN_CB_UPPER,     /*!< Upper bit is CbCr, lower bit is Y */
+} drv_vin_input_align_t;
+
+/*! Output data byte swap mode */
+typedef enum
+{
+    __VIN_SWAP_OFF = 0,   /*!< Not swap */
+    __VIN_SWAP_ON,        /*!< Swap */
+} drv_vin_output_swap_t;
+
+typedef struct
+{
+    drv_vin_preclip_t   vin_preclip;     /*!< Pre Area Clip Parameter */
+    drv_vin_scale_t     vin_scale;       /*!< Scale Parameter */
+    drv_vin_afterclip_t vin_afterclip;   /*!< After Area Clip Parameter */
+    uint8_t         vin_yuv_clip;       /*!< YUV Range Clip Parameter */
+    uint8_t         vin_lut;            /*!< LUT Conversion On or OFF */
+    uint8_t         vin_inputformat;    /*!< Input Image Format */
+    uint8_t         vin_outputformat;   /*!< Output Image Format */
+    uint8_t         vin_outputendian;   /*!< Output Data Endian*/
+    uint8_t         vin_dither;         /*!< (for RGB565 or ARGB1555)Output Data Dithering On or Off */
+    uint8_t         vin_interlace;      /*!< (for Interlace input)Capture Method */
+    uint8_t         vin_alpha_val8;     /*!< (for ARGB8888)Alpha Value */
+    uint8_t         vin_alpha_val1;     /*!< (for ARGB1555)Alpha Value */
+    uint16_t        vin_stride;         /*!< Stride (byte) */
+    uint32_t        vin_ycoffset;       /*!< (for YC separate output)Address Offset Value */
+    drv_vin_input_align_t  vin_input_align;  /*!< YCbCr422 input data alignment */
+    drv_vin_output_swap_t  vin_output_swap;  /*!< Output data byte swap mode */
+} drv_vin_setup_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config );
+drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config );
+
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count );
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count );
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count );
+drv_graphics_error_t DRV_Graphics_CEU_Port_Init( PinName *pin, uint32_t pin_count );
+
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t irq, uint16_t num, void (* callback)(vdc5_int_type_t)  );
+
+drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id );
+drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id );
+drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch );
+drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch );
+
+drv_graphics_error_t DRV_Graphics_Read_Setting (
+    drv_graphics_layer_t    layer_id,
+    void                  * framebuff,
+    uint32_t                fb_stride,
+    drv_graphics_format_t   gr_format,
+    drv_wr_rd_swa_t         wr_rd_swa,
+    drv_rect_t            * gr_rect,
+    drv_clut_t            * gr_clut );
+
+drv_graphics_error_t DRV_Graphics_Read_Change (
+    drv_graphics_layer_t    layer_id,
+    void                 *  framebuff);
+
+drv_graphics_error_t DRV_Video_Write_Setting (
+    drv_video_input_channel_t       video_input_ch,
+    drv_graphics_video_col_sys_t    col_sys,
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_adc_vinsel_t          video_adc_vinsel );
+
+drv_graphics_error_t DRV_Video_Write_Setting_Digital (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_rect_t                    * cap_area );
+
+drv_graphics_error_t DRV_Video_Write_Setting_Ceu (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_ext_in_config_t     * drv_video_ext_in_config);
+
+drv_graphics_error_t DRV_Video_Write_Setting_Mipi (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_mipi_param_t              * mipi_data,
+    drv_vin_setup_t               * vin_setup);
+
+drv_graphics_error_t DRV_Video_Write_Change (
+    drv_video_input_channel_t    video_input_ch,
+    void                       * framebuff,
+    uint32_t                     fb_stride );
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* GR_BOARD_VDC5_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/common/lcd_panel/lcd_analog_rgb_ch0.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,175 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb_ch0.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+#if     (LCD_VDC5_CH0_PANEL==1)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Port 11 */
+#define LCD_PORT11_5TH (0xE0FFu)
+/* Port 10 */
+#define LCD_PORT10_5TH (0xFFFFu)
+
+#define FH_1_2_CYCLE   (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup (VDC5 channel 0)
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0 (void)
+{
+    volatile uint32_t   dummy_read;
+    uint32_t            reg_data;
+
+    /*  Analog RGB D-sub15 (RGB888)
+                        : LCD0_CLK              ... P11_15, 5th alternative function
+            HSYNC       : LCD0_TCON0            ... P11_14, 5th alternative function
+            VSYNC       : LCD0_TCON1            ... P11_13, 5th alternative function
+        LCD0_DATA
+            R[7:0]      : LCD0_DATA[23:16]      ... P10_0 ~ P10_7, 5th alternative function
+            G[7:0]      : LCD0_DATA[15:8]       ... P10_8 ~ P10_15, 5th alternative function
+            B[7:0]      : LCD0_DATA[7:0]        ... P11_0 ~ P11_7, 5th alternative function
+    */
+    /* Port 11 */
+    reg_data        = (uint32_t)GPIO.PMC11 & (uint32_t)~LCD_PORT11_5TH;
+    GPIO.PMC11      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC11;
+    dummy_read      = reg_data;
+    /* PFCAE11, PFCE11, PFC11 ... 5th alternative function
+       PIPC11, PMC11
+       b15:b13  : P11_15 ~ P11_13
+       b7:b0    : P11_7 ~ P11_0 */
+    reg_data        = (uint32_t)GPIO.PFCAE11 | (uint32_t)LCD_PORT11_5TH;
+    GPIO.PFCAE11    = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE11 & (uint32_t)~LCD_PORT11_5TH;
+    GPIO.PFCE11     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC11 & (uint32_t)~LCD_PORT11_5TH;
+    GPIO.PFC11      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PIPC11 | (uint32_t)LCD_PORT11_5TH;
+    GPIO.PIPC11     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC11 | (uint32_t)LCD_PORT11_5TH;
+    GPIO.PMC11      = (uint16_t)reg_data;
+
+    /* Port 10 */
+    reg_data        = (uint32_t)GPIO.PMC10 & (uint32_t)~LCD_PORT10_5TH;
+    GPIO.PMC10      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC10;
+    dummy_read      = reg_data;
+#if(1) /* mbed */
+    (void)dummy_read; /* unused */
+#endif
+    /* PFCAE10, PFCE10, PFC10 ... 5th alternative function
+       PIPC10, PMC10
+       b15:b0   : P10_15 ~ P10_0 */
+    reg_data        = (uint32_t)GPIO.PFCAE10 | (uint32_t)LCD_PORT10_5TH;
+    GPIO.PFCAE10    = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE10 & (uint32_t)~LCD_PORT10_5TH;
+    GPIO.PFCE10     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC10 & (uint32_t)~LCD_PORT10_5TH;
+    GPIO.PFC10      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PIPC10 | (uint32_t)LCD_PORT10_5TH;
+    GPIO.PIPC10     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC10 | (uint32_t)LCD_PORT10_5TH;
+    GPIO.PMC10      = (uint16_t)reg_data;
+}   /* End of function GRAPHICS_SetLcdPanel_Ch0() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing (VDC5 channel 0)
+ * @param[out]  outctrl     : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch0 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* Analog RGB D-sub15 (RGB888), SVGA signal 800x600 */
+    /* TCON timing setting, VS */
+    static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS = {
+        (uint16_t)(LCD_CH0_S_VSYNC * FH_1_2_CYCLE),   /* Signal pulse start position */
+        (uint16_t)(LCD_CH0_W_VSYNC * FH_1_2_CYCLE),   /* Pulse width */
+        VDC5_LCD_TCON_POLMD_NORMAL,
+        VDC5_LCD_TCON_REFSEL_HSYNC,
+        LCD_CH0_POL_VSYNC,                  /* Polarity inversion control of signal */
+        VDC5_LCD_TCON_PIN_1,                /* Output pin for LCD driving signal */
+        LCD_CH0_OUT_EDGE                    /* Output phase control of signal */
+    };
+    /* TCON timing setting, HS */
+    static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS = {
+        (uint16_t)LCD_CH0_S_HSYNC,          /* Signal pulse start position */
+        (uint16_t)LCD_CH0_W_HSYNC,          /* Pulse width */
+        VDC5_LCD_TCON_POLMD_NORMAL,
+        VDC5_LCD_TCON_REFSEL_HSYNC,         /* Signal operating reference select */
+        LCD_CH0_POL_HSYNC,                  /* Polarity inversion control of signal */
+        VDC5_LCD_TCON_PIN_0,                /* Output pin for LCD driving signal */
+        LCD_CH0_OUT_EDGE                    /* Output phase control of signal */
+    };
+
+    if (outctrl != NULL) {
+        outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = &lcd_tcon_timing_VS;  /* STVA/VS: Vsync */
+        outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;                 /* STVB/VE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS;  /* STH/SP/HS: Hsync */
+        outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;                 /* STB/LP/HE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;                 /* CPV/GCK: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;                 /* POLA: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;                 /* POLB: Not used */
+        outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;                 /* DE: Not used */
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings_Ch0() */
+
+#endif  /* LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_ANALOG_RGB */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/common/lcd_panel/lcd_analog_rgb_ch1.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,241 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb_ch1.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 1 function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+#if     (LCD_VDC5_CH1_PANEL==1)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Port 4 */
+#define LCD_PORT4_2ND (0x5400u)
+/* Port 9 */
+#define LCD_PORT9_1ST (0x00FCu)
+/* Port 5 */
+#define LCD_PORT5_7TH (0x0600u)
+#define LCD_PORT5_2ND (0x00FFu)
+/* Port 2 */
+#define LCD_PORT2_7TH (0xF000u)
+#define LCD_PORT2_6TH (0x0F00u)
+
+#define FH_1_2_CYCLE   (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup (VDC5 channel 1)
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch1 (void)
+{
+    volatile uint32_t   dummy_read;
+    uint32_t            reg_data;
+
+    /*  Analog RGB D-sub15 (RGB888)
+            VSYNC       : LCD1_TCON1            ... P4_14, 2nd alternative function
+                        : LCD1_CLK              ... P4_12, 2nd alternative function
+            HSYNC       : LCD1_TCON5            ... P4_10, 2nd alternative function
+        LCD1_DATA
+            R[7:0]      : LCD1_DATA[23:18]      ... P9_7 ~ P9_2, 1st alternative function
+                        :          [17:16]      ... P5_10 ~ P5_9, 7th alternative function
+            G[7:0]      : LCD1_DATA[15:12]      ... P2_15 ~ P2_12, 7th alternative function
+                        :          [11:8]       ... P2_11 ~ P2_8, 6th alternative function
+            B[7:0]      : LCD1_DATA[7:0]        ... P5_7 ~ P5_0, 2nd alternative function
+    */
+    /* Port 4 */
+    reg_data        = (uint32_t)GPIO.PMC4 & (uint32_t)~LCD_PORT4_2ND;
+    GPIO.PMC4       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC4;
+    dummy_read      = reg_data;
+    /* PFCAE4, PFCE4, PFC4 ... 2nd alternative function
+       PIPC4, PMC4
+       b14      : P4_14
+       b12      : P4_12
+       b10      : P4_10 */
+    reg_data        = (uint32_t)GPIO.PFCAE4 & (uint32_t)~LCD_PORT4_2ND;
+    GPIO.PFCAE4     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE4 & (uint32_t)~LCD_PORT4_2ND;
+    GPIO.PFCE4      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC4 | (uint32_t)LCD_PORT4_2ND;
+    GPIO.PFC4       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PIPC4 | (uint32_t)LCD_PORT4_2ND;
+    GPIO.PIPC4      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC4 | (uint32_t)LCD_PORT4_2ND;
+    GPIO.PMC4       = (uint16_t)reg_data;
+
+    /* Port 9 */
+    reg_data        = (uint32_t)GPIO.PMC9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PMC9       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC9;
+    dummy_read      = reg_data;
+    /* PFCAE9, PFCE9, PFC9 ... 1st alternative function
+       PIPC9, PMC9
+       b7:b2    : P9_7 ~ P9_2 */
+    reg_data        = (uint32_t)GPIO.PFCAE9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PFCAE9     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PFCE9      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PFC9       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PIPC9 | (uint32_t)LCD_PORT9_1ST;
+    GPIO.PIPC9      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC9 | (uint32_t)LCD_PORT9_1ST;
+    GPIO.PMC9       = (uint16_t)reg_data;
+
+    /* Port 5 */
+    reg_data        = (uint32_t)GPIO.PMC5 & (uint32_t)~(LCD_PORT5_7TH|LCD_PORT5_2ND);
+    GPIO.PMC5       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC5;
+    dummy_read      = reg_data;
+    /* PFCAE5, PFCE5, PFC5 ... 7th alternative function
+       b10:b9   : P5_10 ~ P5_9 */
+    reg_data        = (uint32_t)GPIO.PFCAE5 | (uint32_t)LCD_PORT5_7TH;
+    GPIO.PFCAE5     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE5 | (uint32_t)LCD_PORT5_7TH;
+    GPIO.PFCE5      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC5 & (uint32_t)~LCD_PORT5_7TH;
+    GPIO.PFC5       = (uint16_t)reg_data;
+    /* PFCAE5, PFCE5, PFC5 ... 2nd alternative function
+       b7:b0    : P5_7 ~ P5_0 */
+    reg_data        = (uint32_t)GPIO.PFCAE5 & (uint32_t)~LCD_PORT5_2ND;
+    GPIO.PFCAE5     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE5 & (uint32_t)~LCD_PORT5_2ND;
+    GPIO.PFCE5      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC5 | (uint32_t)LCD_PORT5_2ND;
+    GPIO.PFC5       = (uint16_t)reg_data;
+    /* PIPC5, PMC5
+       b10:b9   : P5_10 ~ P5_9
+       b7:b0    : P5_7 ~ P5_0 */
+    reg_data        = (uint32_t)GPIO.PIPC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
+    GPIO.PIPC5      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
+    GPIO.PMC5       = (uint16_t)reg_data;
+
+    /* Port 2 */
+    reg_data        = (uint32_t)GPIO.PMC2 & (uint32_t)~(LCD_PORT2_7TH|LCD_PORT2_6TH);
+    GPIO.PMC2       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC2;
+    dummy_read      = reg_data;
+#if(1) /* mbed */
+    (void)dummy_read; /* unused */
+#endif
+    /* PFCAE2, PFCE2, PFC2 ... 7th alternative function
+       b15:b12  : P2_15 ~ P2_12 */
+    reg_data        = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_7TH;
+    GPIO.PFCAE2     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE2 | (uint32_t)LCD_PORT2_7TH;
+    GPIO.PFCE2      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC2 & (uint32_t)~LCD_PORT2_7TH;
+    GPIO.PFC2       = (uint16_t)reg_data;
+    /* PFCAE2, PFCE2, PFC2 ... 6th alternative function
+       b11:b8   : P2_11 ~ P2_8 */
+    reg_data        = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_6TH;
+    GPIO.PFCAE2     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE2 & (uint32_t)~LCD_PORT2_6TH;
+    GPIO.PFCE2      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC2 | (uint32_t)LCD_PORT2_6TH;
+    GPIO.PFC2       = (uint16_t)reg_data;
+    /* PIPC2, PMC2
+       b15:b8   : P2_15 ~ P2_8 */
+    reg_data        = (uint32_t)GPIO.PIPC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
+    GPIO.PIPC2      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
+    GPIO.PMC2       = (uint16_t)reg_data;
+}   /* End of function GRAPHICS_SetLcdPanel_Ch1() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing (VDC5 channel 1)
+ * @param[out]  outctrl     : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch1 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* Analog RGB D-sub15 (RGB888), SVGA signal 800x600 */
+    /* TCON timing setting, VS */
+    static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS = {
+        (uint16_t)(LCD_CH1_S_VSYNC * FH_1_2_CYCLE),   /* Signal pulse start position */
+        (uint16_t)(LCD_CH1_W_VSYNC * FH_1_2_CYCLE),   /* Pulse width */
+        VDC5_LCD_TCON_POLMD_NORMAL,
+        VDC5_LCD_TCON_REFSEL_HSYNC,
+        LCD_CH1_POL_VSYNC,                  /* Polarity inversion control of signal */
+        VDC5_LCD_TCON_PIN_1,                /* Output pin for LCD driving signal */
+        LCD_CH1_OUT_EDGE                    /* Output phase control of signal */
+    };
+    /* TCON timing setting, HS */
+    static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS = {
+        (uint16_t)LCD_CH1_S_HSYNC,          /* Signal pulse start position */
+        (uint16_t)LCD_CH1_W_HSYNC,          /* Pulse width */
+        VDC5_LCD_TCON_POLMD_NORMAL,
+        VDC5_LCD_TCON_REFSEL_HSYNC,         /* Signal operating reference select */
+        LCD_CH1_POL_HSYNC,                  /* Polarity inversion control of signal */
+        VDC5_LCD_TCON_PIN_5,                /* Output pin for LCD driving signal */
+        LCD_CH1_OUT_EDGE                    /* Output phase control of signal */
+    };
+
+    if (outctrl != NULL) {
+        outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = &lcd_tcon_timing_VS;  /* STVA/VS: Vsync */
+        outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;                 /* STVB/VE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS;  /* STH/SP/HS: Hsync */
+        outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;                 /* STB/LP/HE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;                 /* CPV/GCK: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;                 /* POLA: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;                 /* POLB: Not used */
+        outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;                 /* DE: Not used */
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings_Ch1() */
+
+#endif  /* LCD_VDC5_CH1_PANEL==LCD_CH1_PANEL_ANALOG_RGB */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/common/lcd_panel/lcd_gr_peach_ch0.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,99 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_gr_peach_ch0.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+#if     (LCD_VDC5_CH0_PANEL==2)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup (VDC5 channel 0)
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0 (void)
+{
+
+    /* Not Support */
+
+}   /* End of function GRAPHICS_SetLcdPanel_Ch0() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing (VDC5 channel 0)
+ * @param[out]  outctrl     : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch0 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* Not Support */
+
+    if (outctrl != NULL) {
+        outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = NULL;                 /* STVA/VS: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;                 /* STVB/VE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL;                 /* STH/SP/HS: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;                 /* STB/LP/HE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;                 /* CPV/GCK: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;                 /* POLA: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;                 /* POLB: Not used */
+        outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;                 /* DE: Not used */
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings_Ch0() */
+
+#endif  /* LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_GR_PEACH */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/common/lcd_settings.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,114 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_settings.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver LCD panel settings sample
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define LVDSPLL_TST (16u)     /* LVDSPLL_TST (LVDS PLL internal parameters) */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup
+ * @param[in]   channel
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel (const vdc5_channel_t channel)
+{
+    if (channel == VDC5_CHANNEL_0)    {
+        GRAPHICS_SetLcdPanel_Ch0();
+    } else {
+        GRAPHICS_SetLcdPanel_Ch1();
+    }
+}   /* End of function GRAPHICS_SetLcdPanel() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing
+ * @param[in]   channel
+ * @param[out]  outctrl         : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings (const vdc5_channel_t channel, const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* LCD TCON timing setting */
+    if (channel == VDC5_CHANNEL_0) {
+        GRAPHICS_SetLcdTconSettings_Ch0(outctrl);
+    } else {
+        GRAPHICS_SetLcdTconSettings_Ch1(outctrl);
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings() */
+
+/**************************************************************************//**
+ * @brief       LVDS-related parameter acquisition processing
+ * @param[in]   channel
+ * @retval      Address of the area containing the LVDS-related parameters
+******************************************************************************/
+vdc5_lvds_t * GRAPHICS_GetLvdsParam (const vdc5_channel_t channel)
+{
+    static vdc5_lvds_t  lvds_param;
+    vdc5_lvds_t       * p_lvds;
+
+    p_lvds = (vdc5_lvds_t *)&lvds_param;
+
+    if (channel == VDC5_CHANNEL_0) {
+        p_lvds = NULL;
+    } else {
+        p_lvds = NULL;
+    }
+    return p_lvds;
+}   /* End of function GRAPHICS_GetLvdsParam() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/include/r_vdc5.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,957 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver API definitions
+******************************************************************************/
+
+#ifndef R_VDC5_H
+#define R_VDC5_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5_user.h"
+
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_GAM_GAIN_ADJ_NUM       (32u)   /*!< The number of the gamma correction gain coefficient */
+#define     VDC5_GAM_START_TH_NUM       (31u)   /*!< The number of the gamma correction start threshold */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDC5 driver */
+typedef enum {
+    VDC5_OK = 0,                /*!< Normal termination */
+    VDC5_ERR_PARAM_CHANNEL,     /*!< Invalid channel error (parameter error): An illegal channel is specified. */
+    VDC5_ERR_PARAM_LAYER_ID,    /*!< Invalid layer ID error (parameter error): An illegal layer ID is specified. */
+    VDC5_ERR_PARAM_NULL,        /*!< NULL specification error (parameter error):
+                                     NULL is specified for a required parameter. */
+    VDC5_ERR_PARAM_BIT_WIDTH,   /*!< Bit width error (parameter error):
+                                     A value exceeding the possible bit width is specified. */
+    VDC5_ERR_PARAM_UNDEFINED,   /*!< Undefined parameter error (parameter error):
+                                     A value that is not defined in the specification is specified. */
+    VDC5_ERR_PARAM_EXCEED_RANGE,/*!< Out-of-value-range error (parameter error):
+                                     The specified parameter value is beyond the value range defined
+                                     in the specification. */
+    VDC5_ERR_PARAM_CONDITION,   /*!< Unauthorized condition error (parameter error):
+                                     A parameter is specified under conditions that are not authorized
+                                     by the specification. */
+    VDC5_ERR_IF_CONDITION,      /*!< Interface condition error (interface error):
+                                     An API function is called under unauthorized conditions. */
+    VDC5_ERR_RESOURCE_CLK,      /*!< Clock resource error (resource error): No panel clock is set up. */
+    VDC5_ERR_RESOURCE_VSYNC,    /*!< Vsync signal resource error (resource error): No Vsync signal is set up. */
+    VDC5_ERR_RESOURCE_INPUT,    /*!< Input signal resource error (resource error): No video image input is set up. */
+    VDC5_ERR_RESOURCE_OUTPUT,   /*!< Output resource error (resource error): No display output is set up. */
+    VDC5_ERR_RESOURCE_LVDS_CLK, /*!< LVDS clock resource error (resource error):
+                                     An attempt is made to use the LVDS clock without setting it up,
+                                     or the LVDS clock is specified when it is already set up. */
+    VDC5_ERR_RESOURCE_LAYER,    /*!< Layer resource error (resource error):
+                                     The specified layer is under unavailable conditions. */
+    VDC5_ERR_NUM                /*!< The number of error codes */
+} vdc5_error_t;
+
+/*! VDC5 channels */
+typedef enum {
+    VDC5_CHANNEL_0 = 0,         /*!< Channel 0 */
+    VDC5_CHANNEL_1,             /*!< Channel 1 */
+    VDC5_CHANNEL_NUM            /*!< The number of channels */
+} vdc5_channel_t;
+
+/*! On/off */
+typedef enum {
+    VDC5_OFF    = 0,            /*!< Off */
+    VDC5_ON     = 1             /*!< On */
+} vdc5_onoff_t;
+/*! Edge of a signal */
+typedef enum {
+    VDC5_EDGE_RISING    = 0,    /*!< Rising edge */
+    VDC5_EDGE_FALLING   = 1     /*!< Falling edge */
+} vdc5_edge_t;
+/*! Polarity of a signal */
+typedef enum {
+    VDC5_SIG_POL_NOT_INVERTED   = 0,    /*!< Not inverted */
+    VDC5_SIG_POL_INVERTED       = 1     /*!< Inverted */
+} vdc5_sig_pol_t;
+
+/*! Scaling type ID */
+typedef enum {
+    VDC5_SC_TYPE_SC0 = 0,               /*!< Scaler 0 */
+    VDC5_SC_TYPE_SC1,                   /*!< Scaler 1 */
+    VDC5_SC_TYPE_OIR,                   /*!< Output image generator (OIR) */
+    VDC5_SC_TYPE_NUM                    /*!< The number of scaler types */
+} vdc5_scaling_type_t;
+/*! Graphics type ID */
+typedef enum {
+    VDC5_GR_TYPE_GR0 = 0,               /*!< Graphics 0 */
+    VDC5_GR_TYPE_GR1,                   /*!< Graphics 1 */
+    VDC5_GR_TYPE_GR2,                   /*!< Graphics 2 */
+    VDC5_GR_TYPE_GR3,                   /*!< Graphics 3 */
+    VDC5_GR_TYPE_VIN,                   /*!< VIN synthesizer */
+    VDC5_GR_TYPE_OIR,                   /*!< Output image generator (OIR) */
+    VDC5_GR_TYPE_NUM                    /*!< The number of graphics types */
+} vdc5_graphics_type_t;
+/*! Layer ID */
+typedef enum {
+    VDC5_LAYER_ID_ALL       = -1,                                       /*!< All layers */
+    VDC5_LAYER_ID_0_WR      = (VDC5_SC_TYPE_SC0 + 0),                   /*!< Write process for layer 0 */
+    VDC5_LAYER_ID_1_WR      = (VDC5_SC_TYPE_SC1 + 0),                   /*!< Write process for layer 1 */
+    VDC5_LAYER_ID_OIR_WR    = (VDC5_SC_TYPE_OIR + 0),                   /*!< Write process for layer OIR */
+    VDC5_LAYER_ID_0_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR0),    /*!< Read process for layer 0 */
+    VDC5_LAYER_ID_1_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR1),    /*!< Read process for layer 1 */
+    VDC5_LAYER_ID_2_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR2),    /*!< Read process for layer 2 */
+    VDC5_LAYER_ID_3_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR3),    /*!< Read process for layer 3 */
+    VDC5_LAYER_ID_VIN_RD    = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_VIN),    /*!< VIN synthesizer */
+    VDC5_LAYER_ID_OIR_RD    = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_OIR),    /*!< Read process for layer OIR */
+    VDC5_LAYER_ID_NUM       = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_NUM)     /*!< The number of layer IDs */
+} vdc5_layer_id_t;
+/*! The horizontal/vertical timing of the VDC5 signals */
+typedef struct {
+    uint16_t    vs;                 /*!< Vertical signal start position from the reference signal */
+    uint16_t    vw;                 /*!< Vertical signal width (height) */
+    uint16_t    hs;                 /*!< Horizontal signal start position from the reference signal */
+    uint16_t    hw;                 /*!< Horizontal signal width */
+} vdc5_period_rect_t;
+/*! The relative position within the graphics display area */
+typedef struct {
+    uint16_t   vs_rel;              /*!< Vertical start position */
+    uint16_t   vw_rel;              /*!< Vertical width (height) */
+    uint16_t   hs_rel;              /*!< Horizontal start position */
+    uint16_t   hw_rel;              /*!< Horizontal width */
+} vdc5_pd_disp_rect_t;
+
+/***********************    For R_VDC5_Initialize       ***********************/
+/*! Panel clock select */
+typedef enum {
+    VDC5_PANEL_ICKSEL_IMG = 0,      /*!< Divided video image clock (VIDEO_X1) */
+    VDC5_PANEL_ICKSEL_IMG_DV,       /*!< Divided video image clock (DV_CLK) */
+    VDC5_PANEL_ICKSEL_EXT_0,        /*!< Divided external clock (LCD0_EXTCLK) */
+    VDC5_PANEL_ICKSEL_EXT_1,        /*!< Divided external clock (LCD1_EXTCLK) */
+    VDC5_PANEL_ICKSEL_PERI,         /*!< Divided peripheral clock 1 */
+    VDC5_PANEL_ICKSEL_LVDS,         /*!< LVDS PLL clock */
+    VDC5_PANEL_ICKSEL_LVDS_DIV7,    /*!< LVDS PLL clock divided by 7 */
+    VDC5_PANEL_ICKSEL_NUM           /*!< The number of panel clock select settings */
+} vdc5_panel_clksel_t;
+/*! Clock frequency division ratio */
+typedef enum {
+    VDC5_PANEL_CLKDIV_1_1 = 0,      /*!< Division Ratio 1/1 */
+    VDC5_PANEL_CLKDIV_1_2,          /*!< Division Ratio 1/2 */
+    VDC5_PANEL_CLKDIV_1_3,          /*!< Division Ratio 1/3 */
+    VDC5_PANEL_CLKDIV_1_4,          /*!< Division Ratio 1/4 */
+    VDC5_PANEL_CLKDIV_1_5,          /*!< Division Ratio 1/5 */
+    VDC5_PANEL_CLKDIV_1_6,          /*!< Division Ratio 1/6 */
+    VDC5_PANEL_CLKDIV_1_7,          /*!< Division Ratio 1/7 */
+    VDC5_PANEL_CLKDIV_1_8,          /*!< Division Ratio 1/8 */
+    VDC5_PANEL_CLKDIV_1_9,          /*!< Division Ratio 1/9 */
+    VDC5_PANEL_CLKDIV_1_12,         /*!< Division Ratio 1/12 */
+    VDC5_PANEL_CLKDIV_1_16,         /*!< Division Ratio 1/16 */
+    VDC5_PANEL_CLKDIV_1_24,         /*!< Division Ratio 1/24 */
+    VDC5_PANEL_CLKDIV_1_32,         /*!< Division Ratio 1/32 */
+    VDC5_PANEL_CLKDIV_NUM           /*!< The number of division ratio settings */
+} vdc5_panel_clk_dcdr_t;
+/*! The clock input to frequency divider 1 */
+typedef enum {
+    VDC5_LVDS_INCLK_SEL_IMG = 0,    /*!< Video image clock (VIDEO_X1) */
+    VDC5_LVDS_INCLK_SEL_DV_0,       /*!< Video image clock (DV0_CLK) */
+    VDC5_LVDS_INCLK_SEL_DV_1,       /*!< Video image clock (DV1_CLK) */
+    VDC5_LVDS_INCLK_SEL_EXT_0,      /*!< External clock (LCD0_EXTCLK) */
+    VDC5_LVDS_INCLK_SEL_EXT_1,      /*!< External clock (LCD1_EXTCLK) */
+    VDC5_LVDS_INCLK_SEL_PERI,       /*!< Peripheral clock 1 */
+    VDC5_LVDS_INCLK_SEL_NUM
+} vdc5_lvds_in_clk_sel_t;
+/*! The frequency dividing value (NIDIV or NODIV) */
+typedef enum {
+    VDC5_LVDS_NDIV_1 = 0,           /*!< Div 1 */
+    VDC5_LVDS_NDIV_2,               /*!< Div 2 */
+    VDC5_LVDS_NDIV_4,               /*!< Div 4 */
+    VDC5_LVDS_NDIV_NUM
+} vdc5_lvds_ndiv_t;
+/*! The frequency dividing value (NOD) for the output frequency */
+typedef enum {
+    VDC5_LVDS_PLL_NOD_1 = 0,        /*!< Div 1 */
+    VDC5_LVDS_PLL_NOD_2,            /*!< Div 2 */
+    VDC5_LVDS_PLL_NOD_4,            /*!< Div 4 */
+    VDC5_LVDS_PLL_NOD_8,            /*!< Div 8 */
+    VDC5_LVDS_PLL_NOD_NUM
+} vdc5_lvds_pll_nod_t;
+/*! LVDS parameter */
+typedef struct {
+    vdc5_lvds_in_clk_sel_t  lvds_in_clk_sel;/*!< The clock input to frequency divider 1 */
+    vdc5_lvds_ndiv_t        lvds_idiv_set;  /*!< The frequency dividing value (NIDIV) for frequency divider 1 */
+    uint16_t                lvdspll_tst;    /*!< Internal parameter setting for LVDS PLL */
+    vdc5_lvds_ndiv_t        lvds_odiv_set;  /*!< The frequency dividing value (NODIV) for frequency divider 2 */
+    vdc5_channel_t          lvds_vdc_sel;   /*!< A channel in VDC5 whose data is to be output through the LVDS */
+    uint16_t                lvdspll_fd;     /*!< The frequency dividing value (NFD) for the feedback frequency */
+    uint16_t                lvdspll_rd;     /*!< The frequency dividing value (NRD) for the input frequency */
+    vdc5_lvds_pll_nod_t     lvdspll_od;     /*!< The frequency dividing value (NOD) for the output frequency */
+} vdc5_lvds_t;
+/*! Initialization parameter */
+typedef struct {
+    vdc5_panel_clksel_t     panel_icksel;   /*!< Panel clock select */
+    vdc5_panel_clk_dcdr_t   panel_dcdr;     /*!< Clock frequency division ratio */
+    const vdc5_lvds_t     * lvds;           /*!< LVDS-related parameter */
+} vdc5_init_t;
+
+/***********************    For R_VDC5_VideoInput       ***********************/
+/*! Input select */
+typedef enum {
+    VDC5_INPUT_SEL_VDEC     = 0,    /*!< Video decoder output signals */
+    VDC5_INPUT_SEL_EXT      = 1     /*!< Signals supplied via the external input pins */
+} vdc5_input_sel_t;
+/*! Sync signal delay adjustment parameter */
+typedef struct {
+    uint16_t    inp_vs_dly_l;       /*!< Number of lines for delaying Vsync signal and field differentiation signal */
+    uint16_t    inp_fld_dly;        /*!< Field differentiation signal delay amount */
+    uint16_t    inp_vs_dly;         /*!< Vsync signal delay amount */
+    uint16_t    inp_hs_dly;         /*!< Hsync signal delay amount */
+} vdc5_sync_delay_t;
+/*! External input format select */
+typedef enum {
+    VDC5_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 */
+    VDC5_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+    VDC5_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+    VDC5_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+    VDC5_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+    VDC5_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+    VDC5_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 */
+    VDC5_EXTIN_FORMAT_NUM
+} vdc5_extin_format_t;
+/*! Reference select for external input BT.656 Hsync signal */
+typedef enum {
+    VDC5_EXTIN_REF_H_EAV    = 0,    /*!< EAV */
+    VDC5_EXTIN_REF_H_SAV    = 1     /*!< SAV */
+} vdc5_extin_ref_hsync_t;
+/*! Number of lines for BT.656 external input */
+typedef enum {
+    VDC5_EXTIN_LINE_525     = 0,    /*!< 525 lines */
+    VDC5_EXTIN_LINE_625     = 1     /*!< 625 lines */
+} vdc5_extin_input_line_t;
+/*! Y/Cb/Y/Cr data string start timing */
+typedef enum {
+    VDC5_EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+    VDC5_EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+    VDC5_EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+    VDC5_EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+    VDC5_EXTIN_H_POS_NUM
+} vdc5_extin_h_pos_t;
+/*! External input signal parameter */
+typedef struct {
+    vdc5_extin_format_t     inp_format;     /*!< External input format select */
+    vdc5_edge_t             inp_pxd_edge;   /*!< Clock edge select for capturing external input video image signals */
+    vdc5_edge_t             inp_vs_edge;    /*!< Clock edge select for capturing external input Vsync signals */
+    vdc5_edge_t             inp_hs_edge;    /*!< Clock edge select for capturing external input Hsync signals */
+    vdc5_onoff_t            inp_endian_on;  /*!< External input bit endian change on/off control */
+    vdc5_onoff_t            inp_swap_on;    /*!< External input B/R signal swap on/off control */
+    vdc5_sig_pol_t          inp_vs_inv;     /*!< External input Vsync signal DV_VSYNC inversion control */
+    vdc5_sig_pol_t          inp_hs_inv;     /*!< External input Hsync signal DV_HSYNC inversion control */
+    vdc5_extin_ref_hsync_t  inp_h_edge_sel; /*!< Reference select for external input BT.656 Hsync signal */
+    vdc5_extin_input_line_t inp_f525_625;   /*!< Number of lines for BT.656 external input */
+    vdc5_extin_h_pos_t      inp_h_pos;      /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+} vdc5_ext_in_sig_t;
+/*! Video input setup parameter */
+typedef struct {
+    vdc5_input_sel_t            inp_sel;    /*!< Input select */
+    uint16_t                    inp_fh50;   /*!< Vsync signal 1/2fH phase timing */
+    uint16_t                    inp_fh25;   /*!< Vsync signal 1/4fH phase timing */
+    const vdc5_sync_delay_t   * dly;        /*!< Sync signal delay adjustment parameter */
+    const vdc5_ext_in_sig_t   * ext_sig;    /*!< External input signal parameter */
+} vdc5_input_t;
+
+/***********************    For R_VDC5_SyncControl      ***********************/
+/*! Horizontal/vertical sync signal output and full-screen enable signal select */
+typedef enum {
+    VDC5_RES_VS_IN_SEL_SC0  = 0,    /*!< Sync signal output and full-screen enable signal from scaler 0 */
+    VDC5_RES_VS_IN_SEL_SC1  = 1     /*!< Sync signal output and full-screen enable signal from scaler 1 */
+} vdc5_res_vs_in_sel_t;
+/*! Vsync signal compensation parameter */
+typedef struct {
+    uint16_t        res_vmask;              /*!< Repeated Vsync signal masking period */
+    uint16_t        res_vlack;              /*!< Missing-Sync compensating pulse output wait time */
+} vdc5_vsync_cpmpe_t;
+/*! Sync signal control parameter */
+typedef struct {
+    vdc5_onoff_t                res_vs_sel;     /*!< Vsync signal output select (free-running Vsync on/off control) */
+    vdc5_res_vs_in_sel_t        res_vs_in_sel;  /*!< Horizontal/vertical sync signal output
+                                                     and full-screen enable signal select */
+    uint16_t                    res_fv;         /*!< Free-running Vsync period setting */
+    uint16_t                    res_fh;         /*!< Hsync period setting */
+    uint16_t                    res_vsdly;      /*!< Vsync signal delay control */
+    vdc5_period_rect_t          res_f;          /*!< Full-screen enable signal */
+    const vdc5_vsync_cpmpe_t  * vsync_cpmpe;    /*!< Vsync signal compensation parameter */
+} vdc5_sync_ctrl_t;
+
+/***********************    For R_VDC5_DisplayOutput    ***********************/
+/*! POLA/POLB signal generation mode select */
+typedef enum {
+    VDC5_LCD_TCON_POLMD_NORMAL = 0,         /*!< Normal mode */
+    VDC5_LCD_TCON_POLMD_1X1REV,             /*!< 1x1 reverse mode */
+    VDC5_LCD_TCON_POLMD_1X2REV,             /*!< 1x2 reverse mode */
+    VDC5_LCD_TCON_POLMD_2X2REV,             /*!< 2x2 reverse mode */
+    VDC5_LCD_TCON_POLMD_NUM
+} vdc5_lcd_tcon_polmode_t;
+/*! Signal operating reference select */
+typedef enum {
+    VDC5_LCD_TCON_REFSEL_HSYNC      = 0,    /*!< Hsync signal reference */
+    VDC5_LCD_TCON_REFSEL_OFFSET_H   = 1     /*!< Offset Hsync signal reference */
+} vdc5_lcd_tcon_refsel_t;
+/*! LCD TCON output pin select */
+typedef enum {
+    VDC5_LCD_TCON_PIN_NON = -1,             /*!< Nothing output */
+    VDC5_LCD_TCON_PIN_0,                    /*!< LCD_TCON0 */
+    VDC5_LCD_TCON_PIN_1,                    /*!< LCD_TCON1 */
+    VDC5_LCD_TCON_PIN_2,                    /*!< LCD_TCON2 */
+    VDC5_LCD_TCON_PIN_3,                    /*!< LCD_TCON3 */
+    VDC5_LCD_TCON_PIN_4,                    /*!< LCD_TCON4 */
+    VDC5_LCD_TCON_PIN_5,                    /*!< LCD_TCON5 */
+    VDC5_LCD_TCON_PIN_6,                    /*!< LCD_TCON6 */
+    VDC5_LCD_TCON_PIN_NUM
+} vdc5_lcd_tcon_pin_t;
+/*! LCD TCON timing signal parameter */
+typedef struct {
+    uint16_t                tcon_hsvs;      /*!< Signal pulse start position */
+    uint16_t                tcon_hwvw;      /*!< Pulse width */
+    vdc5_lcd_tcon_polmode_t tcon_md;        /*!< POLA/POLB signal generation mode select */
+    vdc5_lcd_tcon_refsel_t  tcon_hs_sel;    /*!< Signal operating reference select */
+    vdc5_sig_pol_t          tcon_inv;       /*!< Polarity inversion control of signal */
+    vdc5_lcd_tcon_pin_t     tcon_pin;       /*!< LCD TCON output pin select */
+    vdc5_edge_t             outcnt_edge;    /*!< Output phase control of signal */
+} vdc5_lcd_tcon_timing_t;
+/*! Timing signals for driving the LCD panel */
+typedef enum {
+    VDC5_LCD_TCONSIG_STVA_VS = 0,           /*!< STVA/VS */
+    VDC5_LCD_TCONSIG_STVB_VE,               /*!< STVB/VE */
+    VDC5_LCD_TCONSIG_STH_SP_HS,             /*!< STH/SP/HS */
+    VDC5_LCD_TCONSIG_STB_LP_HE,             /*!< STB/LP/HE */
+    VDC5_LCD_TCONSIG_CPV_GCK,               /*!< CPV/GCK */
+    VDC5_LCD_TCONSIG_POLA,                  /*!< POLA */
+    VDC5_LCD_TCONSIG_POLB,                  /*!< POLB */
+    VDC5_LCD_TCONSIG_DE,                    /*!< DE */
+    VDC5_LCD_TCONSIG_NUM
+} vdc5_lcd_tcon_sigsel_t;
+/*! Output format select */
+typedef enum {
+    VDC5_LCD_OUTFORMAT_RGB888 = 0,          /*!< RGB888 */
+    VDC5_LCD_OUTFORMAT_RGB666,              /*!< RGB666 */
+    VDC5_LCD_OUTFORMAT_RGB565,              /*!< RGB565 */
+    VDC5_LCD_OUTFORMAT_SERIAL_RGB,          /*!< Serial RGB */
+    VDC5_LCD_OUTFORMAT_NUM
+} vdc5_lcd_outformat_t;
+/*! Clock frequency control */
+typedef enum {
+    VDC5_LCD_PARALLEL_CLKFRQ_1 = 0,         /*!< 100% speed (parallel RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_3,               /*!< Triple speed (serial RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_4,               /*!< Quadruple speed (serial RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_NUM
+} vdc5_lcd_clkfreqsel_t;
+/*! Scan direction select */
+typedef enum {
+    VDC5_LCD_SERIAL_SCAN_FORWARD   = 0,     /*!< Forward scan */
+    VDC5_LCD_SERIAL_SCAN_REVERSE   = 1      /*!< Reverse scan */
+} vdc5_lcd_scan_t;
+/*! Clock phase adjustment for serial RGB output */
+typedef enum {
+    VDC5_LCD_SERIAL_CLKPHASE_0 = 0,         /*!< 0[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_1,             /*!< 1[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_2,             /*!< 2[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_3,             /*!< 3[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_NUM
+} vdc5_lcd_clkphase_t;
+/*! Display output configuration parameter */
+typedef struct {
+    uint16_t                        tcon_half;                      /*!< 1/2fH timing */
+    uint16_t                        tcon_offset;                    /*!< Offset Hsync signal timing */
+    const vdc5_lcd_tcon_timing_t  * outctrl[VDC5_LCD_TCONSIG_NUM];  /*!< LCD TCON timing signal parameter */
+    vdc5_edge_t                     outcnt_lcd_edge;                /*!< Output phase control of LCD_DATA23
+                                                                         to LCD_DATA0 pin */
+    vdc5_onoff_t                    out_endian_on;                  /*!< Bit endian change on/off control */
+    vdc5_onoff_t                    out_swap_on;                    /*!< B/R signal swap on/off control */
+    vdc5_lcd_outformat_t            out_format;                     /*!< Output format select */
+    vdc5_lcd_clkfreqsel_t           out_frq_sel;                    /*!< Clock frequency control */
+    vdc5_lcd_scan_t                 out_dir_sel;                    /*!< Scan direction select */
+    vdc5_lcd_clkphase_t             out_phase;                      /*!< Clock phase adjustment
+                                                                         for serial RGB output */
+    uint32_t                        bg_color;                       /*!< Background color in 24-bit RGB color format */
+} vdc5_output_t;
+
+/***********************    For R_VDC5_CallbackISR      ***********************/
+/*! VDC5 interrupt type */
+typedef enum {
+    VDC5_INT_TYPE_S0_VI_VSYNC = 0,      /*!< Vsync signal input to scaler 0 */
+    VDC5_INT_TYPE_S0_LO_VSYNC,          /*!< Vsync signal output from scaler 0 */
+    VDC5_INT_TYPE_S0_VSYNCERR,          /*!< Missing Vsync signal for scaler 0 */
+    VDC5_INT_TYPE_VLINE,                /*!< Specified line signal for panel output in graphics 3 */
+    VDC5_INT_TYPE_S0_VFIELD,            /*!< Field end signal for recording function in scaler 0 */
+    VDC5_INT_TYPE_IV1_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 0 */
+    VDC5_INT_TYPE_IV3_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 0 */
+    VDC5_INT_TYPE_IV5_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 2 */
+    VDC5_INT_TYPE_IV6_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 3 */
+    VDC5_INT_TYPE_S0_WLINE,             /*!< Write specification line signal input to scaling-down control block
+                                            in scaler 0 */
+    VDC5_INT_TYPE_S1_VI_VSYNC,          /*!< Vsync signal input to scaler 1 */
+    VDC5_INT_TYPE_S1_LO_VSYNC,          /*!< Vsync signal output from scaler 1 */
+    VDC5_INT_TYPE_S1_VSYNCERR,          /*!< Missing Vsync signal for scaler 1 */
+    VDC5_INT_TYPE_S1_VFIELD,            /*!< Field end signal for recording function in scaler 1 */
+    VDC5_INT_TYPE_IV2_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 1 */
+    VDC5_INT_TYPE_IV4_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 1 */
+    VDC5_INT_TYPE_S1_WLINE,             /*!< Write specification line signal input to scaling-down control block
+                                            in scaler 1 */
+    VDC5_INT_TYPE_OIR_VI_VSYNC,         /*!< Vsync signal input to output image generator */
+    VDC5_INT_TYPE_OIR_LO_VSYNC,         /*!< Vsync signal output from output image generator */
+    VDC5_INT_TYPE_OIR_VLINE,            /*!< Specified line signal for panel output in output image generator */
+    VDC5_INT_TYPE_OIR_VFIELD,           /*!< Field end signal for recording function in output image generator */
+    VDC5_INT_TYPE_IV7_VBUFERR,          /*!< Frame buffer write overflow signal for output image generator */
+    VDC5_INT_TYPE_IV8_VBUFERR,          /*!< Frame buffer read underflow signal for graphics (OIR) */
+    VDC5_INT_TYPE_NUM                   /*!< The number of VDC5 interrupt types */
+} vdc5_int_type_t;
+/*! Interrupt callback setup parameter */
+typedef struct {
+    vdc5_int_type_t     type;                       /*!< VDC5 interrupt type */
+    void             (* callback)(vdc5_int_type_t); /*!< Interrupt callback function pointer */
+    uint16_t            line_num;                   /*!< Line interrupt set */
+} vdc5_int_t;
+
+/***********************    For R_VDC5_WriteDataControl ***********************/
+/*! Frame buffer writing mode for image processing */
+typedef enum {
+    VDC5_WR_MD_NORMAL = 0,                  /*!< Normal */
+    VDC5_WR_MD_MIRROR,                      /*!< Horizontal mirroring */
+    VDC5_WR_MD_ROT_90DEG,                   /*!< 90 degree rotation */
+    VDC5_WR_MD_ROT_180DEG,                  /*!< 180 degree rotation */
+    VDC5_WR_MD_ROT_270DEG,                  /*!< 270 degree rotation */
+    VDC5_WR_MD_NUM
+} vdc5_wr_md_t;
+/*! Scaling-down and rotation parameter */
+typedef struct {
+    vdc5_period_rect_t  res;                /*!< Image area to be captured */
+    vdc5_onoff_t        res_pfil_sel;       /*!< Prefilter mode select for brightness signals (on/off) */
+    uint16_t            res_out_vw;         /*!< Number of valid lines in vertical direction
+                                                 output by scaling-down control block */
+    uint16_t            res_out_hw;         /*!< Number of valid horizontal pixels
+                                                 output by scaling-down control block */
+    vdc5_onoff_t        adj_sel;            /*!< Handling for lack of last-input line (on/off) */
+    vdc5_wr_md_t        res_ds_wr_md;       /*!< Frame buffer writing mode for image processing */
+} vdc5_scalingdown_rot_t;
+/*! Frame buffer swap setting */
+typedef enum {
+    VDC5_WR_RD_WRSWA_NON = 0,           /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+    VDC5_WR_RD_WRSWA_8BIT,              /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+    VDC5_WR_RD_WRSWA_16BIT,             /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+    VDC5_WR_RD_WRSWA_16_8BIT,           /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+    VDC5_WR_RD_WRSWA_32BIT,             /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+    VDC5_WR_RD_WRSWA_32_8BIT,           /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+    VDC5_WR_RD_WRSWA_32_16BIT,          /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+    VDC5_WR_RD_WRSWA_32_16_8BIT,        /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    VDC5_WR_RD_WRSWA_NUM
+} vdc5_wr_rd_swa_t;
+/*! Frame buffer video-signal writing format */
+typedef enum {
+    VDC5_RES_MD_YCBCR422 = 0,               /*!< YCbCr422 */
+    VDC5_RES_MD_RGB565,                     /*!< RGB565 */
+    VDC5_RES_MD_RGB888,                     /*!< RGB888 */
+    VDC5_RES_MD_YCBCR444,                   /*!< YCbCr444 */
+    VDC5_RES_MD_NUM
+} vdc5_res_md_t;
+/*! Transfer burst length */
+typedef enum {
+    VDC5_BST_MD_32BYTE = 0,                 /*!< 32-byte transfer (4 bursts) */
+    VDC5_BST_MD_128BYTE                     /*!< 128-byte transfer (16 bursts) */
+} vdc5_bst_md_t;
+/*! Field operating mode select */
+typedef enum {
+    VDC5_RES_INTER_PROGRESSIVE  = 0,        /*!< Progressive */
+    VDC5_RES_INTER_INTERLACE    = 1         /*!< Interlace */
+} vdc5_res_inter_t;
+/*! Writing rate */
+typedef enum {
+    VDC5_RES_FS_RATE_PER1 = 0,              /* 1/1 an input signal */
+    VDC5_RES_FS_RATE_PER2,                  /* 1/2 an input signal */
+    VDC5_RES_FS_RATE_PER4,                  /* 1/4 an input signal */
+    VDC5_RES_FS_RATE_PER8,                  /* 1/8 an input signal */
+    VDC5_RES_FS_RATE_NUM
+} vdc5_res_fs_rate_t;
+/*! Write field select */
+typedef enum {
+    VDC5_RES_FLD_SEL_TOP    = 0,            /*!< Top field */
+    VDC5_RES_FLD_SEL_BOTTOM = 1             /*!< Bottom field */
+} vdc5_res_fld_sel_t;
+/*! Data write control parameter */
+typedef struct {
+    vdc5_scalingdown_rot_t  scalingdown_rot;/*!< Scaling-down and rotation parameter */
+    vdc5_wr_rd_swa_t        res_wrswa;      /*!< Swap setting in frame buffer writing */
+    vdc5_res_md_t           res_md;         /*!< Frame buffer video-signal writing format */
+    vdc5_bst_md_t           res_bst_md;     /*!< Transfer burst length for frame buffer writing */
+    vdc5_res_inter_t        res_inter;      /*!< Field operating mode select */
+    vdc5_res_fs_rate_t      res_fs_rate;    /*!< Writing rate */
+    vdc5_res_fld_sel_t      res_fld_sel;    /*!< Write field select */
+    vdc5_onoff_t            res_dth_on;     /*!< Dither correction on/off */
+    void                  * base;           /*!< Frame buffer base address */
+    uint32_t                ln_off;         /*!< Frame buffer line offset address [byte] */
+    uint32_t                flm_num;        /*!< Number of frames of buffer to be written to (res_flm_num + 1) */
+    uint32_t                flm_off;        /*!< Frame buffer frame offset address [byte] */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+} vdc5_write_t;
+
+/***********************  For R_VDC5_ChangeWriteProcess ***********************/
+/*! Data write change parameter */
+typedef struct {
+    vdc5_scalingdown_rot_t  scalingdown_rot;/*!< Scaling-down and rotation parameter */
+} vdc5_write_chg_t;
+
+/***********************  For R_VDC5_ReadDataControl    ***********************/
+/*! Line offset address direction of the frame buffer */
+typedef enum {
+    VDC5_GR_LN_OFF_DIR_INC = 0,             /*!< Increments the address by the line offset address */
+    VDC5_GR_LN_OFF_DIR_DEC                  /*!< Decrements the address by the line offset address */
+} vdc5_gr_ln_off_dir_t;
+/*! Frame buffer address setting signal */
+typedef enum {
+    VDC5_GR_FLM_SEL_SCALE_DOWN = 0,         /*!< Links to scaling-down process */
+    VDC5_GR_FLM_SEL_FLM_NUM,                /*!< Selects frame 0 (graphics display) */
+    VDC5_GR_FLM_SEL_DISTORTION,             /*!< Links to distortion correction */
+    VDC5_GR_FLM_SEL_POINTER_BUFF,           /*!< Links to pointer buffer */
+    VDC5_GR_FLM_SEL_NUM
+} vdc5_gr_flm_sel_t;
+/*! Size of the frame buffer to be read */
+typedef struct {
+    uint16_t                in_vw;          /*!< Number of lines in a frame */
+    uint16_t                in_hw;          /*!< Width of the horizontal valid period */
+} vdc5_width_read_fb_t;
+/*! Format of the frame buffer read signal */
+typedef enum {
+    VDC5_GR_FORMAT_RGB565 = 0,              /*!< RGB565 */
+    VDC5_GR_FORMAT_RGB888,                  /*!< RGB888 */
+    VDC5_GR_FORMAT_ARGB1555,                /*!< ARGB1555 */
+    VDC5_GR_FORMAT_ARGB4444,                /*!< ARGB4444 */
+    VDC5_GR_FORMAT_ARGB8888,                /*!< ARGB8888 */
+    VDC5_GR_FORMAT_CLUT8,                   /*!< CLUT8 */
+    VDC5_GR_FORMAT_CLUT4,                   /*!< CLUT4 */
+    VDC5_GR_FORMAT_CLUT1,                   /*!< CLUT1 */
+    VDC5_GR_FORMAT_YCBCR422,                /*!< YCbCr422: This setting is prohibited for the graphics 2 and 3 */
+    VDC5_GR_FORMAT_YCBCR444,                /*!< YCbCr444: This setting is prohibited for the graphics 2 and 3 */
+    VDC5_GR_FORMAT_RGBA5551,                /*!< RGBA5551 */
+    VDC5_GR_FORMAT_RGBA8888,                /*!< RGBA8888 */
+    VDC5_GR_FORMAT_NUM                      /*!< The number of signal formats */
+} vdc5_gr_format_t;
+/*! Swapping of data read from buffer in the YCbCr422 format */
+typedef enum {
+    VDC5_GR_YCCSWAP_CBY0CRY1 = 0,
+    VDC5_GR_YCCSWAP_Y0CBY1CR,
+    VDC5_GR_YCCSWAP_CRY0CBY1,
+    VDC5_GR_YCCSWAP_Y0CRY1CB,
+    VDC5_GR_YCCSWAP_Y1CRY0CB,
+    VDC5_GR_YCCSWAP_CRY1CBY0,
+    VDC5_GR_YCCSWAP_Y1CBY0CR,
+    VDC5_GR_YCCSWAP_CBY1CRY0,
+    VDC5_GR_YCCSWAP_NUM
+} vdc5_gr_ycc_swap_t;
+/*! Data read control parameter */
+typedef struct {
+    vdc5_gr_ln_off_dir_t            gr_ln_off_dir;  /*!< Line offset address direction of the frame buffer */
+    vdc5_gr_flm_sel_t               gr_flm_sel;     /*!< Frame buffer address setting signal */
+    vdc5_onoff_t                    gr_imr_flm_inv; /*!< Frame buffer number for distortion correction */
+    vdc5_bst_md_t                   gr_bst_md;      /*!< Frame buffer burst transfer mode */
+    void                          * gr_base;        /*!< Frame buffer base address */
+    uint32_t                        gr_ln_off;      /*!< Frame buffer line offset address */
+    const vdc5_width_read_fb_t    * width_read_fb;  /*!< Size of the frame buffer to be read */
+    vdc5_onoff_t                    adj_sel;        /*!< Folding handling (on/off) */
+    vdc5_gr_format_t                gr_format;      /*!< Format of the frame buffer read signal */
+    vdc5_gr_ycc_swap_t              gr_ycc_swap;    /*!< Swapping of data read from buffer
+                                                         in the YCbCr422 format */
+    vdc5_wr_rd_swa_t                gr_rdswa;       /*!< Swap setting in frame buffer reading */
+    vdc5_period_rect_t              gr_grc;         /*!< Graphics display area */
+} vdc5_read_t;
+
+/******************************* For R_VDC5_ChangeReadProcess       *******************************/
+/*! The type of graphics display modes */
+typedef enum {
+    VDC5_DISPSEL_IGNORED    = -1,       /*!< Ignored */
+    VDC5_DISPSEL_BACK       = 0,        /*!< Background color display */
+    VDC5_DISPSEL_LOWER      = 1,        /*!< Lower-layer graphics display */
+    VDC5_DISPSEL_CURRENT    = 2,        /*!< Current graphics display */
+    VDC5_DISPSEL_BLEND      = 3,        /*!< Blended display of lower-layer graphics and current graphics */
+    VDC5_DISPSEL_NUM        = 4         /*!< The number of graphics display modes */
+} vdc5_gr_disp_sel_t;
+/*! Data read change parameter */
+typedef struct {
+    void                          * gr_base;        /*!< Frame buffer base address */
+    const vdc5_width_read_fb_t    * width_read_fb;  /*!< Size of the frame buffer to be read */
+    const vdc5_period_rect_t      * gr_grc;         /*!< Graphics display area */
+    const vdc5_gr_disp_sel_t      * gr_disp_sel;    /*!< Graphics display mode */
+} vdc5_read_chg_t;
+
+/******************************* For R_VDC5_StartProcess            *******************************/
+/*! Data write/read start parameter */
+typedef struct {
+    const vdc5_gr_disp_sel_t      * gr_disp_sel;    /*!< Graphics display mode */
+} vdc5_start_t;
+
+/******************************* For R_VDC5_VideoNoiseReduction     *******************************/
+/*! TAP select */
+typedef enum {
+    VDC5_NR_TAPSEL_1 = 0,           /*!< Adjacent pixel */
+    VDC5_NR_TAPSEL_2,               /*!< 2 adjacent pixels */
+    VDC5_NR_TAPSEL_3,               /*!< 3 adjacent pixels */
+    VDC5_NR_TAPSEL_4,               /*!< 4 adjacent pixels */
+    VDC5_NR_TAPSEL_NUM
+} vdc5_nr_tap_t;
+/*! Noise reduction gain adjustment */
+typedef enum {
+    VDC5_NR_GAIN_1_2 = 0,           /*!< 1/2 */
+    VDC5_NR_GAIN_1_4,               /*!< 1/4 */
+    VDC5_NR_GAIN_1_8,               /*!< 1/8 */
+    VDC5_NR_GAIN_1_16,              /*!< 1/16 */
+    VDC5_NR_GAIN_NUM
+} vdc5_nr_gain_t;
+/*! Noise reduction parameter */
+typedef struct {
+    vdc5_nr_tap_t   nr1d_tap;       /*!< TAP select */
+    uint32_t        nr1d_th;        /*!< Maximum value of coring (absolute value) */
+    vdc5_nr_gain_t  nr1d_gain;      /*!< Noise reduction gain adjustment */
+} vdc5_nr_param_t;
+/*! Noise reduction setup parameter */
+typedef struct {
+    vdc5_nr_param_t     y;          /*!< Y/G signal noise reduction parameter */
+    vdc5_nr_param_t     cb;         /*!< Cb/B signal noise reduction parameter */
+    vdc5_nr_param_t     cr;         /*!< Cr/R signal noise reduction parameter */
+} vdc5_noise_reduction_t;
+
+/******************************* For R_VDC5_ImageColorMatrix        *******************************/
+/*! Color matrix module */
+typedef enum {
+    VDC5_COLORMTX_IMGCNT = 0,           /*!< Input Controller (input video signal) */
+    VDC5_COLORMTX_ADJ_0,                /*!< Image quality improver 0 (scaler 0 output) */
+    VDC5_COLORMTX_ADJ_1,                /*!< Image quality improver 1 (scaler 1 output) */
+    VDC5_COLORMTX_NUM
+} vdc5_colormtx_module_t;
+/*! Operating mode */
+typedef enum {
+    VDC5_COLORMTX_GBR_GBR = 0,          /*!< GBR to GBR */
+    VDC5_COLORMTX_GBR_YCBCR,            /*!< GBR to YCbCr */
+    VDC5_COLORMTX_YCBCR_GBR,            /*!< YCbCr to GBR */
+    VDC5_COLORMTX_YCBCR_YCBCR,          /*!< YCbCr to YCbCr */
+    VDC5_COLORMTX_MODE_NUM              /*!< The number of operating modes */
+} vdc5_colormtx_mode_t;
+/*! Color matrix offset (DC) adjustment */
+typedef enum {
+    VDC5_COLORMTX_OFFST_YG = 0,         /*!< YG */
+    VDC5_COLORMTX_OFFST_B,              /*!< B */
+    VDC5_COLORMTX_OFFST_R,              /*!< R */
+    VDC5_COLORMTX_OFFST_NUM             /*!< The number of the color matrix DC offset values */
+} vdc5_colormtx_offset_t;
+/*! Color matrix signal gain adjustment */
+typedef enum {
+    VDC5_COLORMTX_GAIN_GG = 0,          /*!< GG */
+    VDC5_COLORMTX_GAIN_GB,              /*!< GB */
+    VDC5_COLORMTX_GAIN_GR,              /*!< GR */
+    VDC5_COLORMTX_GAIN_BG,              /*!< BG */
+    VDC5_COLORMTX_GAIN_BB,              /*!< BB */
+    VDC5_COLORMTX_GAIN_BR,              /*!< BR */
+    VDC5_COLORMTX_GAIN_RG,              /*!< RG */
+    VDC5_COLORMTX_GAIN_RB,              /*!< RB */
+    VDC5_COLORMTX_GAIN_RR,              /*!< RR */
+    VDC5_COLORMTX_GAIN_NUM              /*!< The number of the color matrix gain values */
+} vdc5_colormtx_gain_t;
+/*! Color matrix setup parameter */
+typedef struct {
+    vdc5_colormtx_module_t  module;                         /*!< Color matrix module */
+    vdc5_colormtx_mode_t    mtx_mode;                       /*!< Operating mode */
+    uint16_t                offset[VDC5_COLORMTX_OFFST_NUM];/*!< Offset (DC) adjustment of Y/G, B, and R signal */
+    uint16_t                gain[VDC5_COLORMTX_GAIN_NUM];   /*!< GG, GB, GR, BG, BB, BR, RG, RB, and RR signal
+                                                                 gain adjustment */
+} vdc5_color_matrix_t;
+
+/******************************* For R_VDC5_ImageEnhancement        *******************************/
+/*! Image quality improver ID */
+typedef enum {
+    VDC5_IMG_IMPRV_0 = 0,           /*!< Image quality improver 0 */
+    VDC5_IMG_IMPRV_1,               /*!< Image quality improver 1 */
+    VDC5_IMG_IMPRV_NUM              /*!< The number of image quality improvers */
+} vdc5_imgimprv_id_t;
+
+/*! Sharpness band */
+typedef enum {
+    VDC5_IMGENH_SHARP_H1 = 0,       /*!< H1: Adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_H2,           /*!< H2: Second adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_H3,           /*!< H3: Third adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_NUM           /*!< The number of horizontal sharpness bands */
+} vdc5_img_enh_sh_t;
+/*! Sharpness control parameter */
+typedef struct {
+    uint8_t     shp_clip_o;         /*!< Sharpness correction value clipping (on the overshoot side) */
+    uint8_t     shp_clip_u;         /*!< Sharpness correction value clipping (on the undershoot side) */
+    uint8_t     shp_gain_o;         /*!< Sharpness edge amplitude value gain (on the overshoot side) */
+    uint8_t     shp_gain_u;         /*!< Sharpness edge amplitude value gain (on the undershoot side) */
+    uint8_t     shp_core;           /*!< Active sharpness range */
+} vdc5_sharpness_ctrl_t;
+/*! Sharpness setup parameter */
+typedef struct {
+    vdc5_onoff_t            shp_h2_lpf_sel;                     /*!< LPF selection for folding prevention
+                                                                     before H2 edge detection */
+    vdc5_sharpness_ctrl_t   hrz_sharp[VDC5_IMGENH_SHARP_NUM];   /*!< Sharpness control parameter (H1, H2, and H3) */
+} vdc5_enhance_sharp_t;
+/*! LTI band */
+typedef enum {
+    VDC5_IMGENH_LTI1 = 0,           /*!< H2: Second adjacent pixel used as reference */
+    VDC5_IMGENH_LTI2,               /*!< H4: Fourth adjacent pixel used as reference */
+    VDC5_IMGENH_LTI_NUM             /*!< The number of horizontal LTI bands */
+} vdc5_img_enh_lti_t;
+/*! Median filter reference pixel select */
+typedef enum {
+    VDC5_LTI_MDFIL_SEL_ADJ2 = 0,    /*!< Second adjacent pixel selected as reference */
+    VDC5_LTI_MDFIL_SEL_ADJ1         /*!< Adjacent pixel selected as reference */
+} vdc5_lti_mdfil_sel_t;
+/*! LTI control parameter */
+typedef struct {
+    uint8_t     lti_inc_zero;       /*!< Median filter LTI correction threshold */
+    uint8_t     lti_gain;           /*!< LTI edge amplitude value gain */
+    uint8_t     lti_core;           /*!< LTI coring (maximum core value of 255) */
+} vdc5_lti_ctrl_t;
+/*! Luminance Transient Improvement setup parameter */
+typedef struct {
+    vdc5_onoff_t            lti_h2_lpf_sel;             /*!< LPF selection for folding prevention
+                                                             before H2 edge detection */
+    vdc5_lti_mdfil_sel_t    lti_h4_median_tap_sel;      /*!< Median filter reference pixel select */
+    vdc5_lti_ctrl_t         lti[VDC5_IMGENH_LTI_NUM];   /*!< LTI control parameter (H2 and H4) */
+} vdc5_enhance_lti_t;
+
+/******************************* For R_VDC5_ImageBlackStretch       *******************************/
+/*! Black stretch setup parameter */
+typedef struct {
+    uint16_t    bkstr_st;           /*!< Black stretch start point */
+    uint16_t    bkstr_d;            /*!< Black stretch depth */
+    uint16_t    bkstr_t1;           /*!< Black stretch time constant (T1) */
+    uint16_t    bkstr_t2;           /*!< Black stretch time constant (T2) */
+} vdc5_black_t;
+
+/******************************* For R_VDC5_AlphaBlending           *******************************/
+/*! Alpha signal of the ARGB1555/ARGB5551 format */
+typedef struct {
+    uint8_t     gr_a0;                  /*!< Alpha signal when alpha is set to '0' */
+    uint8_t     gr_a1;                  /*!< Alpha signal when alpha is set to '1' */
+} vdc5_alpha_argb1555_t;
+/*! Alpha blending in one-pixel units */
+typedef struct {
+    vdc5_onoff_t    gr_acalc_md;        /*!< Premultiplication processing at alpha blending
+                                             in one-pixel units (on/off) */
+} vdc5_alpha_pixel_t;
+/*! Alpha blending setup parameter */
+typedef struct {
+    const vdc5_alpha_argb1555_t   * alpha_1bit; /*!< Alpha signal of the ARGB1555/ARGB5551 format */
+    const vdc5_alpha_pixel_t      * alpha_pixel;/*!< Premultiplication processing at alpha blending in one-pixel */
+} vdc5_alpha_blending_t;
+
+/******************************* For R_VDC5_AlphaBlendingRect       *******************************/
+/*! Parameter for alpha blending in a rectangular area */
+typedef struct {
+    int16_t         gr_arc_coef;        /*!< Alpha coefficient for alpha blending in a rectangular area
+                                             (-255 to 255) */
+    uint8_t         gr_arc_rate;        /*!< Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+    uint8_t         gr_arc_def;         /*!< Initial alpha value for alpha blending in a rectangular area */
+    vdc5_onoff_t    gr_arc_mul;         /*!< Multiplication processing with current alpha at alpha blending
+                                             in a rectangular area (on/off) */
+} vdc5_alpha_rect_t;
+/*! Selection of lower-layer plane in scaler */
+typedef struct {
+    vdc5_onoff_t    gr_vin_scl_und_sel; /*!< Selection of lower-layer plane in scaler
+                                             - VDC5_OFF: Selects graphics 0 as lower-layer graphics
+                                                         and graphics 1 as current graphics
+                                             - VDC5_ON: Selects graphics 1 as lower-layer graphics
+                                                        and graphics 0 as current graphics */
+} vdc5_scl_und_sel_t;
+/*! Setup parameter for alpha blending in a rectangular area */
+typedef struct {
+    const vdc5_pd_disp_rect_t * gr_arc;     /*!< Rectangular area subjected to alpha blending */
+    const vdc5_alpha_rect_t   * alpha_rect; /*!< Parameter for alpha blending in a rectangular area */
+    const vdc5_scl_und_sel_t  * scl_und_sel;/*!< Selection of lower-layer plane in scaler */
+} vdc5_alpha_blending_rect_t;
+
+/******************************* For R_VDC5_Chromakey               *******************************/
+/*! Chroma-key setup parameter */
+typedef struct {
+    uint32_t    ck_color;       /*!< RGB/CLUT signal for RGB/CLUT-index chroma-key processing */
+    uint32_t    rep_color;      /*!< Replaced ARGB signal after RGB/CLUT-index chroma-key processing */
+    uint8_t     rep_alpha;      /*!< Replaced alpha signal after RGB-index chroma-key processing (in 8 bits) */
+} vdc5_chromakey_t;
+
+/******************************* For R_VDC5_CLUT                    *******************************/
+/*! CLUT setup parameter */
+typedef struct {
+    uint32_t            color_num;  /*!< The number of colors in CLUT */
+    const uint32_t    * clut;       /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
+} vdc5_clut_t;
+
+/******************************* For R_VDC5_DisplayCalibration      *******************************/
+/*! Correction circuit sequence control */
+typedef enum {
+    VDC5_CALIBR_ROUTE_BCG = 0,          /*!< Brightness -> contrast -> gamma correction */
+    VDC5_CALIBR_ROUTE_GBC               /*!< Gamma correction -> brightness -> contrast */
+} vdc5_calibr_route_t;
+/*! Brightness (DC) adjustment parameter */
+typedef struct {
+    uint16_t    pbrt_g;                 /*!< Brightness (DC) adjustment of G signal */
+    uint16_t    pbrt_b;                 /*!< Brightness (DC) adjustment of B signal */
+    uint16_t    pbrt_r;                 /*!< Brightness (DC) adjustment of R signal */
+} vdc5_calibr_bright_t;
+/*! Contrast (gain) adjustment parameter */
+typedef struct {
+    uint8_t     cont_g;                 /*!< Contrast (gain) adjustment of G signal */
+    uint8_t     cont_b;                 /*!< Contrast (gain) adjustment of B signal */
+    uint8_t     cont_r;                 /*!< Contrast (gain) adjustment of R signal */
+} vdc5_calibr_contrast_t;
+/*! Panel dither operation mode */
+typedef enum {
+    VDC5_PDTH_MD_TRU = 0,               /*!< Truncate */
+    VDC5_PDTH_MD_RDOF,                  /*!< Round-off */
+    VDC5_PDTH_MD_2X2,                   /*!< 2 x 2 pattern dither */
+    VDC5_PDTH_MD_RAND,                  /*!< Random pattern dither */
+    VDC5_PDTH_MD_NUM
+} vdc5_panel_dither_md_t;
+/*! Panel dithering parameter */
+typedef struct {
+    vdc5_panel_dither_md_t  pdth_sel;   /*!< Panel dither operation mode */
+    uint8_t                 pdth_pa;    /*!< Pattern value (A) of 2x2 pattern dither */
+    uint8_t                 pdth_pb;    /*!< Pattern value (B) of 2x2 pattern dither */
+    uint8_t                 pdth_pc;    /*!< Pattern value (C) of 2x2 pattern dither */
+    uint8_t                 pdth_pd;    /*!< Pattern value (D) of 2x2 pattern dither */
+} vdc5_calibr_dither_t;
+/*! Display calibration parameter */
+typedef struct {
+    vdc5_calibr_route_t             route;          /*!< Correction circuit sequence control */
+    const vdc5_calibr_bright_t    * bright;         /*!< Brightness (DC) adjustment parameter */
+    const vdc5_calibr_contrast_t  * contrast;       /*!< Contrast (gain) adjustment parameter */
+    const vdc5_calibr_dither_t    * panel_dither;   /*!< Panel dithering parameter */
+} vdc5_disp_calibration_t;
+
+/******************************* For R_VDC5_GammaCorrection         *******************************/
+/*! Gamma correction setup parameter */
+typedef struct {
+    const uint16_t    * gam_g_gain;     /*!< Gain adjustment of area 0 to 31 of G signal */
+    const uint8_t     * gam_g_th;       /*!< Start threshold of area 1 to 31 of G signal */
+    const uint16_t    * gam_b_gain;     /*!< Gain adjustment of area 0 to 31 of B signal */
+    const uint8_t     * gam_b_th;       /*!< Start threshold of area 1 to 31 of B signal */
+    const uint16_t    * gam_r_gain;     /*!< Gain adjustment of area 0 to 31 of R signal */
+    const uint8_t     * gam_r_th;       /*!< Start threshold of area 1 to 31 of R signal */
+} vdc5_gamma_correction_t;
+
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdc5_error_t R_VDC5_Initialize(
+    const vdc5_channel_t        ch,
+    const vdc5_init_t   * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num);
+vdc5_error_t R_VDC5_Terminate(const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdc5_error_t R_VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
+vdc5_error_t R_VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+vdc5_error_t R_VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
+vdc5_error_t R_VDC5_CallbackISR(const vdc5_channel_t ch, const vdc5_int_t * const param);
+vdc5_error_t R_VDC5_WriteDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param);
+vdc5_error_t R_VDC5_ChangeWriteProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t   * const param);
+vdc5_error_t R_VDC5_ReadDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_read_t   * const param);
+vdc5_error_t R_VDC5_ChangeReadProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param);
+vdc5_error_t R_VDC5_StartProcess(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param);
+vdc5_error_t R_VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_VideoNoiseReduction(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param);
+vdc5_error_t R_VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+vdc5_error_t R_VDC5_ImageEnhancement(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area);
+vdc5_error_t R_VDC5_ImageBlackStretch(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param);
+vdc5_error_t R_VDC5_AlphaBlending(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param);
+vdc5_error_t R_VDC5_AlphaBlendingRect(
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param);
+vdc5_error_t R_VDC5_Chromakey(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param);
+vdc5_error_t R_VDC5_CLUT(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param);
+vdc5_error_t R_VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+vdc5_error_t R_VDC5_GammaCorrection(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param);
+
+void (*R_VDC5_GetISR(const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense);
+
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_VDC5_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/include/r_vdc5_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,103 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_user.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver user-defined header
+******************************************************************************/
+
+#ifndef R_VDC5_USER_H
+#define R_VDC5_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Compilation switch to enable parameter check functions<br>
+    If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_VDC5_CHECK_PARAMETERS
+
+
+/*! GBR to YCbCr conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - Y  =  0.299 * R + 0.587 * G + 0.114 * B
+ *  - Cb = -0.169 * R - 0.331 * G + 0.500 * B
+ *  - Cr =  0.500 * R - 0.419 * G - 0.081 * B
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum {
+    VDC5_COLORCONV_Y_R  = (77u),
+    VDC5_COLORCONV_Y_G  = (150u),
+    VDC5_COLORCONV_Y_B  = (29u),
+    VDC5_COLORCONV_CB_R = (2005u),
+    VDC5_COLORCONV_CB_G = (1963u),
+    VDC5_COLORCONV_CB_B = (128u),
+    VDC5_COLORCONV_CR_R = (128u),
+    VDC5_COLORCONV_CR_G = (1941u),
+    VDC5_COLORCONV_CR_B = (2027u)
+} vdc5_colcnv_rgb_ycbcr_t;
+
+/*! YCbCr to GBR conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - G = 1.0 * Y - 0.344 * Cb - 0.714 * Cr
+ *  - B = 1.0 * Y + 1.772 * Cb +   0.0 * Cr
+ *  - R = 1.0 * Y +   0.0 * Cb + 1.402 * Cr
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum {
+    VDC5_COLORCONV_G_Y  = (256u),
+    VDC5_COLORCONV_G_CB = (1960u),
+    VDC5_COLORCONV_G_CR = (1865u),
+    VDC5_COLORCONV_B_Y  = (256u),
+    VDC5_COLORCONV_B_CB = (454u),
+    VDC5_COLORCONV_B_CR = (0u),
+    VDC5_COLORCONV_R_Y  = (256u),
+    VDC5_COLORCONV_R_CB = (0u),
+    VDC5_COLORCONV_R_CR = (359u)
+} vdc5_colcnv_ycbcr_rgb_t;
+
+/*! Color matrix DC offset typical value */
+#define     VDC5_COLORCONV_DC_OFFSET        (128u)
+/*! Color matrix coefficient value that represents one times */
+#define     VDC5_COLORCONV_1TIMES_GAIN      (256u)
+
+/*! 1usec wait cycle for LVDS PLL */
+#define     VDC5_LVDS_PLL_WAIT_CYCLE        (38u)
+/*! 200usec wait counter for LVDS PLL */
+#define     VDC5_LVDS_PLL_WAIT_200USEC      (13400u)
+
+
+#endif  /* R_VDC5_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1224 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+#include    "r_vdc5_shared_param.h"
+#include    "r_vdc5_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_scaling_type_t ConvertRwProcId2SclId(const vdc5_layer_id_t layer_id);
+static vdc5_graphics_type_t ConvertRwProcId2GrId(const vdc5_layer_id_t layer_id);
+
+
+/**************************************************************************//**
+ * @brief       VDC5 driver initialization
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Initializes the VDC5 driver's internal variables.
+ *              - Calls the user-defined function specified in init_func.
+ *              - Sets up and enables the VDC5's panel clock.
+ *              - Sets up and enables the LVDS only if LVDS is used.
+ *              - Disables all the VDC5 interrupts.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Initialization parameter
+ * @param[in]   init_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Initialize (
+    const vdc5_channel_t        ch,
+    const vdc5_init_t   * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_InitializeCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmInit(ch);
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+            /* The LVDS PLL clock has been already set. */
+            if (param->lvds != NULL) {
+                ret = VDC5_ERR_RESOURCE_LVDS_CLK;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetInitParam(ch, param);
+
+        /* Callback function */
+        if (init_func != 0) {
+            init_func(user_num);
+        }
+
+        VDC5_Initialize(ch, param);
+
+        /* Disable all VDC5 interrupts */
+        VDC5_Int_Disable(ch);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_VALID);
+        if (param->lvds != NULL) {
+            VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LVDS_CLK, VDC5_RESOURCE_ST_VALID);
+        }
+    }
+    return ret;
+}   /* End of function R_VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief       VDC5 driver termination
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Disables all the VDC5 interrupts.
+ *              - Disables the VDC5 panel clock.
+ *              - Disables the LVDS if one is used and becomes unnecessary as the result of calling this function.
+ *              - Calls the user-defined function specified in quit_func.
+ * @param[in]   ch                      : Channel
+ * @param[in]   quit_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Terminate (const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    vdc5_error_t    ret;
+    vdc5_onoff_t    lvds_ref;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_TerminateCheckPrm(ch);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetTerminate(ch);
+
+        /* Disable all VDC5 interrupts */
+        VDC5_Int_Disable(ch);
+
+        VDC5_Terminate(ch);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_INVALID);
+
+        lvds_ref = VDC5_ShrdPrmGetLvdsClkRef();
+        if (lvds_ref == VDC5_OFF) {     /* LVDS PLL clock is not referred. */
+            VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LVDS_CLK, VDC5_RESOURCE_ST_INVALID);
+        }
+
+        /* Callback function */
+        if (quit_func != 0) {
+            quit_func(user_num);
+        }
+    }
+    return ret;
+}   /* End of function R_VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Video input setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Selects the video input.
+ *              - Sets up the phase timing of the input signals.
+ *              - Performs delay control on the sync signal for the video inputs.
+ *              - Sets up the parameters for the external input video signals only when they are used.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_error_t ret;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_VideoInputCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetInputParam(ch, param);
+
+        /* Setting VDC5 registers */
+        VDC5_VideoInput(ch, param);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_VIDEO_IN, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Sync control setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Selects the vertical sync signal.
+ *              - Sets up the period of the sync signal.
+ *              - Sets up the delay of the vertical sync signal.
+ *              - Sets up the full-screen enable signal.
+ *              - Sets up the compensation for the vertical sync signal.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_SyncControlCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        }
+    }
+    if (ret == VDC5_OK) {
+        if (param->res_vs_sel == VDC5_OFF) {
+            /* External input Vsync signal is selected. */
+            if (param->res_vs_in_sel == VDC5_RES_VS_IN_SEL_SC0) {
+                /* Scaler 0 */
+                rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+            } else {
+                /* Scaler 1 */
+                rsrc_state = VDC5_ShrdPrmGetResource(
+                                 ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+                                 VDC5_RESOURCE_VIDEO_IN);
+            }
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetSyncParam(ch, param);
+
+        /* Setting VDC5 registers */
+        VDC5_SyncControl(ch, param);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_VSYNC, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Display output setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the timing signals for driving the LCD panel.
+ *              - Sets up the phase, data sequence, and format of the LCD panel output data.
+ *              - Sets up the background color.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_DisplayOutputCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        } else {
+            rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VSYNC);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetOutputParam(ch, param);
+
+        /* Setting VDC5 registers */
+        VDC5_DisplayOutput(ch, param);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LCD_PANEL, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CallbackISR (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_CallbackISRCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        } else {
+            rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VSYNC);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_Int_SetInterrupt(ch, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_CallbackISR() */
+
+/**************************************************************************//**
+ * @brief       Data write control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the input image area to be captured.
+ *              - Makes input image scale-down/rotation control settings (layers 0 and 1 only).
+ *              - Makes frame buffer write control settings.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_WR
+ *                                        - VDC5_LAYER_ID_1_WR
+ *                                        - VDC5_LAYER_ID_OIR_WR
+ * @param[in]   param                   : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_WriteDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_scaling_type_t     scaling_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    scaling_id = ConvertRwProcId2SclId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_WriteDataControlCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is already used. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            if (layer_id == VDC5_LAYER_ID_0_WR) {
+                /* Layer 0 */
+                rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+            } else if (layer_id == VDC5_LAYER_ID_1_WR) {
+                /* Layer 1 */
+                rsrc_state = VDC5_ShrdPrmGetResource(
+                                 ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+                                 VDC5_RESOURCE_VIDEO_IN);
+            } else {
+                /* Layer OIR */
+                rsrc_state = VDC5_RESOURCE_ST_VALID;
+            }
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetWriteParam(ch, scaling_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_WriteDataControl(ch, scaling_id, param);
+
+        VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data write change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the input image area to be captured.
+ *              - Makes changes with respect to scaling-down/rotation control of the input image (layers 0 and 1 only).
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_WR
+ *                                        - VDC5_LAYER_ID_1_WR
+ *                                        - VDC5_LAYER_ID_OIR_WR
+ * @param[in]   param                   : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeWriteProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_scaling_type_t     scaling_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    scaling_id = ConvertRwProcId2SclId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChangeWriteProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetChgWriteParam(ch, scaling_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ChangeWriteProcess(ch, scaling_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Data read control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the display area for graphics images.
+ *              - Makes image scale-up control settings (layers 0 and 1 only).
+ *              - Makes frame buffer read control settings.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   param                   : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReadDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ReadDataControlCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is already used. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetReadParam(ch, graphics_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ReadDataControl(ch, graphics_id, param);
+
+        VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control) (layers 0 and 1 only).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   param                   : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeReadProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChangeReadProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetChgReadParam(ch, graphics_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ChangeReadProcess(ch, graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read start processing
+ *
+ *              Description:<br>
+ *              This function performs layer start processing. If the layer ID specified in layer_id
+ *              is VDC5_LAYER_ID_ALL, the function starts all the layers that are in the stopped state
+ *              and also enabled. If the layer ID is not VDC5_LAYER_ID_ALL, the function starts only
+ *              the specified layer.<br>
+ *              When performing start processing for write, the function starts a write to the frame buffer.
+ *              When performing start processing for read, the function starts a read from the frame buffer
+ *              and sets the graphics display mode to the specified values for each layer.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StartProcess (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_StartProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL) {
+            rsrc_state = VDC5_ShrdPrmGetRwProcReady(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_StartProcess(ch, layer_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read stop processing
+ *
+ *              Description:<br>
+ *              This function performs layer stop processing. If the layer ID specified in layer_id is
+ *              VDC5_LAYER_ID_ALL, the function stops all the layers that are enabled and running.
+ *              If the layer ID is not VDC5_LAYER_ID_ALL, the function stops only the specified layer.<br>
+ *              When performing stop processing for write, the function stops the write to the frame buffer.
+ *              When performing stop processing for read, the function stops the read from the frame buffer
+ *              and resets the graphics display mode to the initial values for each of the layers.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_StopProcessCheckPrm(ch, layer_id);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL) {
+            rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_StopProcess(ch, layer_id);
+    }
+    return ret;
+}   /* End of function R_VDC5_StopSurface() */
+
+/**************************************************************************//**
+ * @brief       Data write/read control release processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Disables the specified layer.
+ *              - Initializes the cascaded connection settings (layer 1 read processing only).
+ *              - Initializes the VIN synthesizer settings (layer 0 and 1 read processing only).
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ReleaseDataControlCheckPrm(ch, layer_id);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL) {
+            rsrc_state = VDC5_ShrdPrmGetRwProcReady(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ReleaseDataControl(ch, layer_id);
+
+        VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_INVALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief       Noise reduction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off noise reduction processing.
+ *              - Sets up the noise reduction parameters for the Y/G, Cb/B, and Cr/R signals.
+ * @param[in]   ch                      : Channel
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoNoiseReduction (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_VideoNoiseReductCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_INPUT;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_VideoNoiseReduction(ch, nr1d_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Color matrix setup
+ *
+ *              Description:<br>
+ *              This function sets up the specified color matrix.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageColorMatrixCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (param->module == VDC5_COLORMTX_IMGCNT) {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_WR);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                rsrc_state = VDC5_ShrdPrmGetLayerResource(
+                                 ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+                                 VDC5_LAYER_ID_1_WR);
+            }
+        } else if (param->module == VDC5_COLORMTX_ADJ_0) {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+        } else {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_RD);
+        }
+
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ImageColorMatrix(ch, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Image enhancement processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off sharpness processing.
+ *              - Sets up the sharpness parameter.
+ *              - Turns on and off LTI processing.
+ *              - Sets up the LTI parameter.
+ *              - Sets up the enhancer-enabled area to be subjected to sharpness and LTI processing.
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageEnhancement (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_color_space_t      color_space;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageEnhancementCheckPrm(ch, imgimprv_id, sharp_param, enh_area);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(
+                         ch,
+                         ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_LAYER_ID_0_RD : VDC5_LAYER_ID_1_RD));
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(
+                              ch,
+                              ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_GR_TYPE_GR0 : VDC5_GR_TYPE_GR1));
+            if (color_space == VDC5_COLOR_SPACE_GBR) {
+                /* The image quality improver does not act on RGB signals. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ImageEnhancement(ch, imgimprv_id, shp_h_on, sharp_param, lti_h_on, lti_param, enh_area);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Black stretch setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off black stretch processing.
+ *              - Sets up the black stretch parameters.
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageBlackStretch (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_color_space_t      color_space;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageBlackStretchCheckPrm(ch, imgimprv_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(
+                         ch,
+                         ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_LAYER_ID_0_RD : VDC5_LAYER_ID_1_RD));
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(
+                              ch,
+                              ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_GR_TYPE_GR0 : VDC5_GR_TYPE_GR1));
+            if (color_space == VDC5_COLOR_SPACE_GBR) {
+                /* The image quality improver does not act on RGB signals. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ImageBlackStretch(ch, imgimprv_id, bkstr_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the alpha value of the ARGB1555/RGBA5551 formats.
+ *              - Make settings for premultiplication processing at alpha blending in one-pixel.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlending (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_AlphaBlendingCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_AlphaBlending(ch, graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Rectangle alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off alpha blending in a rectangular area.
+ *              - Sets up the rectangular area subjected to alpha blending.
+ *              - Sets up the alpha value for alpha blending in a rectangular area.
+ *              - Makes fade-in/-out settings to be applied to rectangle alpha blending.
+ *              - Allocates graphics 0 and 1 to the lower-layer/current graphics in the VIN synthesizer.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_VIN_RD
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlendingRect (
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_color_space_t      color_space;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_AlphaBlendingRectCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        if (layer_id != VDC5_LAYER_ID_VIN_RD) {
+            /* Resource checks */
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            } else {
+                /* Condition checks */
+                color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+                if (color_space == VDC5_COLOR_SPACE_YCBCR) {
+                    /* Alpha blending cannot be used
+                       when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+                    ret = VDC5_ERR_IF_CONDITION;
+                }
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_AlphaBlendingRect(ch, graphics_id, gr_arc_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_AlphaBlendingRect() */
+
+/**************************************************************************//**
+ * @brief       Chroma-key setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off the chroma-key processing.
+ *              - Sets up the color signals to be subject to chroma-key processing and
+ *                the color signals after replacement.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Chromakey (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_color_space_t      color_space;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChromakeyCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+            if (color_space == VDC5_COLOR_SPACE_YCBCR) {
+                /* Chroma-key processing cannot be used
+                   when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_Chromakey(ch, graphics_id, gr_ck_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       CLUT setup
+ *
+ *              Description:<br>
+ *              This function sets up CLUT for the specified layer.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CLUT (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_CLUTCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_CLUT(ch, graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_SetCLUT() */
+
+/**************************************************************************//**
+ * @brief       Display calibration processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up panel brightness adjustment.
+ *              - Sets up contrast adjustment.
+ *              - Sets up panel dithering.
+ *              - Makes control settings for the correction circuit sequence.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_DisplayCalibrationCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_DisplayCalibration(ch, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Gamma correction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off gamma correction processing.
+ *              - Sets up the gamma correction gain adjustment values for the G/B/R signals.
+ *              - Sets up the gamma correction start threshold values for the G/B/R signals.
+ * @param[in]   ch                      : Channel
+ * @param[in]   gam_on                  : Gamma correction ON/OFF setting
+ * @param[in]   param                   : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_GammaCorrection (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_GammaCorrectionCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_GammaCorrection(ch, gam_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Convert read/write process ID into scaling type ID
+ *
+ * @param[in]   layer_id              : Layer ID
+ * @retval      Scaling type ID
+ *****************************************************************************/
+static vdc5_scaling_type_t ConvertRwProcId2SclId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_scaling_type_t scaling_id;
+
+    switch (layer_id) {
+        case VDC5_LAYER_ID_0_WR:                /* Layer 0, write process */
+            scaling_id = VDC5_SC_TYPE_SC0;      /* Scaler 0 */
+            break;
+        case VDC5_LAYER_ID_1_WR:                /* Layer 1, write process */
+            scaling_id = VDC5_SC_TYPE_SC1;      /* Scaler 1 */
+            break;
+        case VDC5_LAYER_ID_OIR_WR:              /* Layer OIR, write process */
+            scaling_id = VDC5_SC_TYPE_OIR;      /* OIR */
+            break;
+        default:                                /* Error */
+            scaling_id = VDC5_SC_TYPE_NUM;
+            break;
+    }
+    return scaling_id;
+}   /* End of function ConvertRwProcId2SclId() */
+
+/**************************************************************************//**
+ * @brief       Convert read/write process ID into graphics type ID
+ *
+ * @param[in]   layer_id              : Layer ID
+ * @retval      Graphics type ID
+ *****************************************************************************/
+static vdc5_graphics_type_t ConvertRwProcId2GrId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_graphics_type_t graphics_id;
+
+    switch (layer_id) {
+        case VDC5_LAYER_ID_0_RD:                /* Layer 0, read process */
+            graphics_id = VDC5_GR_TYPE_GR0;     /* Graphics 0 */
+            break;
+        case VDC5_LAYER_ID_1_RD:                /* Layer 1, read process */
+            graphics_id = VDC5_GR_TYPE_GR1;     /* Graphics 1 */
+            break;
+        case VDC5_LAYER_ID_2_RD:                /* Layer 2, read process */
+            graphics_id = VDC5_GR_TYPE_GR2;     /* Graphics 2 */
+            break;
+        case VDC5_LAYER_ID_3_RD:                /* Layer 3, read process */
+            graphics_id = VDC5_GR_TYPE_GR3;     /* Graphics 3 */
+            break;
+        case VDC5_LAYER_ID_VIN_RD:              /* Layer VIN, read process */
+            graphics_id = VDC5_GR_TYPE_VIN;     /* VIN */
+            break;
+        case VDC5_LAYER_ID_OIR_RD:              /* Layer OIR, read process */
+            graphics_id = VDC5_GR_TYPE_OIR;     /* OIR */
+            break;
+        default:                                /* Error */
+            graphics_id = VDC5_GR_TYPE_NUM;
+            break;
+    }
+    return graphics_id;
+}   /* End of function ConvertRwProcId2GrId() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_check_parameter.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1952 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_check_parameter.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_shared_param.h"
+#include    "r_vdc5_check_parameter.h"
+
+
+#ifdef      R_VDC5_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDC5_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDC5_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDC5_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDC5_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDC5_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDC5_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDC5_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDC5_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDC5_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDC5_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDC5_CPARA_RANGE_0X00007FFF (0x00007FFFu)
+#define VDC5_CPARA_RANGE_0X0000FFFF (0x0000FFFFu)
+#define VDC5_CPARA_RANGE_0X007FFFFF (0x007FFFFFu)
+#define VDC5_CPARA_RANGE_0X00FFFFFF (0x00FFFFFFu)
+/* Valid range for signal delay amount */
+#define VDC5_CPARA_INP_FLD_DLY_MAX (254u)
+#define VDC5_CPARA_INP_VS_DLY_MAX  (254u)
+#define VDC5_CPARA_INP_HS_DLY_MAX  (254u)
+/* Valid range for NFS */
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_56 (56u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_24 (24u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_28 (28u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_31 (31u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_37 (37u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_39 (39u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_46 (46u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_47 (47u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_55 (55u)
+/* Valid range for HS + HW */
+#define VDC5_CPARA_HS_HW_MAX       (2015u)
+/* Valid range for HS */
+#define VDC5_CPARA_HS_MIN          (16u)
+/* Valid range for VS + VW */
+#define VDC5_CPARA_VS_VW_MAX       (2039u)
+/* Valid range for VS */
+#define VDC5_CPARA_VS_MIN          (4u)
+/* The max number of CLUT data values */
+#define VDC5_CPARA_CLUT8_NUM       (256u)
+#define VDC5_CPARA_CLUT4_NUM       (16u)
+#define VDC5_CPARA_CLUT1_NUM       (2u)
+/* Valid range for the alpha coefficient */
+#define VDC5_CPARA_GR_ARC_COEF_MIN (-255)
+#define VDC5_CPARA_GR_ARC_COEF_MAX (255)
+/* Valid range for HS of enhancer area */
+#define VDC5_CPARA_ENH_HS_LIMIT    (4u)
+/* Valid range for VS of enhancer area */
+#define VDC5_CPARA_ENH_VS_LIMIT    (2u)
+
+#define VDC5_BKSTR_T2_PROHIBITED    (31u)
+
+#define VDC5_MULTIPLE_4_MASK        (0x00000003u)
+#define VDC5_MULTIPLE_32_MASK       (0x0000001Fu)
+#define VDC5_MULTIPLE_128_MASK      (0x0000007Fu)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_error_t CheckChannel(const vdc5_channel_t ch);
+static vdc5_error_t CheckLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckGraphicsTypeLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckRect(const vdc5_period_rect_t * const rect);
+static vdc5_error_t CheckTcon_Vertical(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_Horizontal(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_HorizontalPol(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_DataEnable(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckGammaCrct_GainAdjustment(const uint16_t * gam_gain);
+
+
+/**************************************************************************//**
+ * @brief       Checks on initialization parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Initialization parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_InitializeCheckPrm (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+    vdc5_error_t            error;
+    const vdc5_lvds_t     * lvds_tmp;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_input_sel_t        inp_sel_tmp;
+    vdc5_channel_t          lvds_vdc_sel_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Panel clock select */
+    if (param->panel_icksel >= VDC5_PANEL_ICKSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS) && (param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+        /* Clock frequency division ratio */
+        if (param->panel_dcdr >= VDC5_PANEL_CLKDIV_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+    rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+        inp_sel_tmp = VDC5_ShrdPrmGetInputSelect(ch);
+        if (((inp_sel_tmp == VDC5_INPUT_SEL_VDEC) && (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV)) ||
+                ((inp_sel_tmp == VDC5_INPUT_SEL_EXT) && (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG))) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+
+    /* LVDS-related parameter */
+    lvds_tmp = param->lvds;
+    if (lvds_tmp == NULL) {
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The LVDS PLL clock has not been set yet. */
+            if ((param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+                error = VDC5_ERR_PARAM_NULL;
+                goto END;
+            }
+        } else {
+            if (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7) {
+                lvds_vdc_sel_tmp = VDC5_ShrdPrmGetLvdsCh();
+                if (ch != lvds_vdc_sel_tmp) {
+                    /* Channel mismatch error */
+                    error = VDC5_ERR_PARAM_CONDITION;
+                    goto END;
+                }
+            }
+        }
+    } else {
+        /* The clock input to frequency divider 1 */
+        if (lvds_tmp->lvds_in_clk_sel >= VDC5_LVDS_INCLK_SEL_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* The frequency dividing value (NIDIV and NODIV) for frequency divider 1 and 2 */
+        if ((lvds_tmp->lvds_idiv_set >= VDC5_LVDS_NDIV_NUM) || (lvds_tmp->lvds_odiv_set >= VDC5_LVDS_NDIV_NUM)) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* Internal parameter setting for LVDS PLL */
+        if (((uint32_t)lvds_tmp->lvdspll_tst & (uint32_t)~VDC5_CPARA_RANGE_0X0000003F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* A channel in VDC5 whose data is to be output through the LVDS */
+        if (lvds_tmp->lvds_vdc_sel >= VDC5_CHANNEL_NUM) {
+            error = VDC5_ERR_PARAM_CHANNEL;
+            goto END;
+        }
+        if (param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS_DIV7) {
+            /* When using the clock output from the LVDS PLL as the clock for the LVDS output interface,
+               both channel number should match. */
+            if (ch != lvds_tmp->lvds_vdc_sel) {
+                /* Channel mismatch error */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+        /* The frequency dividing value (NFD) for the feedback frequency */
+        if (((uint32_t)lvds_tmp->lvdspll_fd & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_56) {
+            if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_24) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_28) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_31)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_37) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_39)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_46) ||
+                    ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_47) ||
+                    ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_55)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+        /* The frequency dividing value (NRD) for the input frequency */
+        if (((uint32_t)lvds_tmp->lvdspll_rd & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* The frequency dividing value (NOD) for the output frequency */
+        if (lvds_tmp->lvdspll_od >= VDC5_LVDS_PLL_NOD_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_InitializeCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_Terminate
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_TerminateCheckPrm (const vdc5_channel_t ch)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_TerminateCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on video input setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoInputCheckPrm (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_error_t                error;
+    const vdc5_sync_delay_t   * dly_tmp;
+    const vdc5_ext_in_sig_t   * ext_sig_tmp;
+    vdc5_panel_clksel_t         panel_clksel;
+    vdc5_resource_state_t       rsrc_state;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+        panel_clksel = VDC5_ShrdPrmGetPanelClkSel(ch);
+        if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+            /* Video decoder output signals */
+            if (panel_clksel == VDC5_PANEL_ICKSEL_IMG_DV) {
+                /* Video image clock, DV_CLK */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        } else {
+            /* Signals supplied via the external input pins */
+            if (panel_clksel == VDC5_PANEL_ICKSEL_IMG) {
+                /* Video image clock, VIDEO_X1 */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+
+    /* Vsync signal 1/2fH phase timing */
+    if (((uint32_t)param->inp_fh50 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal 1/4fH phase timing */
+    if (((uint32_t)param->inp_fh25 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL) {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        if (((uint32_t)dly_tmp->inp_vs_dly_l & (uint32_t)~VDC5_CPARA_RANGE_0X00000007) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Field differentiation signal delay amount */
+        if (((uint32_t)dly_tmp->inp_fld_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_fld_dly > (uint32_t)VDC5_CPARA_INP_FLD_DLY_MAX) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Vsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_vs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_vs_dly > (uint32_t)VDC5_CPARA_INP_VS_DLY_MAX) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Hsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_hs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_hs_dly > (uint32_t)VDC5_CPARA_INP_HS_DLY_MAX) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp == NULL) {
+        if (param->inp_sel != VDC5_INPUT_SEL_VDEC) {
+            error = VDC5_ERR_PARAM_NULL;
+            goto END;
+        }
+    } else {
+        /* External input format select */
+        if (ext_sig_tmp->inp_format >= VDC5_EXTIN_FORMAT_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+        if (ext_sig_tmp->inp_h_pos >= VDC5_EXTIN_H_POS_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if ((ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_YCRYCB) || (ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_CRYCBY)) {
+            if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR422) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_VideoInputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sync control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Sync control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_SyncControlCheckPrm (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    if (param->res_vs_sel != VDC5_OFF) {
+        /* Free-running Vsync period setting */
+        if (((uint32_t)param->res_fv & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Hsync period setting */
+    if (((uint32_t)param->res_fh & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal delay control */
+    if (((uint32_t)param->res_vsdly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Full-screen enable control */
+    error = CheckRect(&param->res_f);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_SyncControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display output configuration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayOutputCheckPrm (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_error_t                    error;
+    uint32_t                        tcon_sig_index;
+    static vdc5_error_t    (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+        const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing) = {
+        &CheckTcon_Vertical,        /* STVA/VS */
+        &CheckTcon_Vertical,        /* STVB/VE */
+        &CheckTcon_Horizontal,      /* STH/HS */
+        &CheckTcon_Horizontal,      /* STB/HE */
+        &CheckTcon_Horizontal,      /* CPV/GCK */
+        &CheckTcon_HorizontalPol,   /* POLA */
+        &CheckTcon_HorizontalPol,   /* POLB */
+        &CheckTcon_DataEnable       /* DE */
+    };
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* 1/2fH timing */
+    if (((uint32_t)param->tcon_half & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Offset Hsync signal timing */
+    if (((uint32_t)param->tcon_offset & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* LCD TCON timing setting */
+    for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++) {
+        if (param->outctrl[tcon_sig_index] != NULL) {
+            error = tcon_function_tbl[tcon_sig_index](param->outctrl[tcon_sig_index]);
+            if (error != VDC5_OK) {
+                goto END;
+            }
+        }
+    }
+
+    /* LCD output format select */
+    if (param->out_format >= VDC5_LCD_OUTFORMAT_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB) {
+        /* Clock frequency control */
+        if (param->out_frq_sel >= VDC5_LCD_SERIAL_CLKFRQ_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC5_LCD_PARALLEL_CLKFRQ_1) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+        /* Clock phase adjustment */
+        if (param->out_phase >= VDC5_LCD_SERIAL_CLKPHASE_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC5_LCD_SERIAL_CLKFRQ_3) {
+            if (param->out_phase == VDC5_LCD_SERIAL_CLKPHASE_3) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+    /* Background color in 24-bit RGB color format */
+    if ((param->bg_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_DisplayOutputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on interrupt callback setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CallbackISRCheckPrm (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* VDC5 interrupt type */
+    if (param->type >= VDC5_INT_TYPE_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Interrupt callback function pointer */
+    if (param->callback != 0) {
+        if ((param->type == VDC5_INT_TYPE_VLINE) ||
+                (param->type == VDC5_INT_TYPE_S0_WLINE) ||
+                (param->type == VDC5_INT_TYPE_S1_WLINE) ||
+                (param->type == VDC5_INT_TYPE_OIR_VLINE)) {
+            /* Line interrupt set */
+            if (((uint32_t)param->line_num & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_CallbackISRCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_WriteDataControlCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_0_WR) && (layer_id != VDC5_LAYER_ID_1_WR) && (layer_id != VDC5_LAYER_ID_OIR_WR)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode for image processing */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Swap setting in frame buffer writing */
+    if (param->res_wrswa >= VDC5_WR_RD_WRSWA_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer video-signal writing format */
+    if (param->res_md >= VDC5_RES_MD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Writing rate */
+    if (param->res_fs_rate >= VDC5_RES_FS_RATE_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer base address */
+    if (param->base == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Frame buffer line offset address [byte] */
+    if ((param->ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->res_bst_md == VDC5_BST_MD_32BYTE) {
+        /* 32-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else {
+        /* 128-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    if ((param->flm_num & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u) {
+        if ((param->flm_off & (uint32_t)~VDC5_CPARA_RANGE_0X007FFFFF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (param->res_bst_md == VDC5_BST_MD_32BYTE) {
+            /* 32-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        } else {
+            /* 128-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_WriteDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeWriteProcessCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t  * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_0_WR) && (layer_id != VDC5_LAYER_ID_1_WR) && (layer_id != VDC5_LAYER_ID_OIR_WR)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChangeWriteProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReadDataControlCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_error_t            error;
+    void                  * btm_base_tmp;
+    vdc5_resource_state_t   rsrc_state;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Frame buffer address setting signal */
+    if (param->gr_flm_sel >= VDC5_GR_FLM_SEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    btm_base_tmp    = NULL;
+    rsrc_state      = VDC5_RESOURCE_ST_INVALID;
+    switch (graphics_id) {
+        case VDC5_GR_TYPE_GR0:
+            btm_base_tmp    = VDC5_ShrdPrmGetFrBuffBtm(ch, VDC5_SC_TYPE_SC0);
+            rsrc_state      = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_WR);
+            break;
+        case VDC5_GR_TYPE_GR1:
+            if (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION) {
+                /* IMR-LS2 is implemented in scaler 0 only. */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            btm_base_tmp    = VDC5_ShrdPrmGetFrBuffBtm(ch, VDC5_SC_TYPE_SC1);
+            rsrc_state      = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_WR);
+            break;
+        /* The following two cases are intentionally combined. */
+        case VDC5_GR_TYPE_GR2:
+        case VDC5_GR_TYPE_GR3:
+            if (param->gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            break;
+        case VDC5_GR_TYPE_OIR:
+            if (param->gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            if ((ch != VDC5_CHANNEL_0) && (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION)) {
+                /* IMR-LSD is implemented in channel 0 only. */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            break;
+        default:
+            /* DO NOTHING */
+            break;
+    }
+    if ((btm_base_tmp != NULL) && (rsrc_state != VDC5_RESOURCE_ST_INVALID)) {
+        /* btm_base_tmp is valid only when rsrc_state is valid. */
+        if (param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Frame buffer base address */
+    if (param->gr_base == NULL) {
+        if (param->gr_flm_sel != VDC5_GR_FLM_SEL_POINTER_BUFF) {
+            error = VDC5_ERR_PARAM_NULL;
+            goto END;
+        }
+    }
+    /* Frame buffer line offset address */
+    if ((param->gr_ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->gr_bst_md == VDC5_BST_MD_32BYTE) {
+        /* 32-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else {
+        /* 128-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    if (param->width_read_fb != NULL) {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Format of the frame buffer read signal */
+    if (param->gr_format >= VDC5_GR_FORMAT_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444)) {
+        /* YCbCr422 and YCbCr444 are supported for the graphics 0 and 1. */
+        if ((graphics_id != VDC5_GR_TYPE_GR0) && (graphics_id != VDC5_GR_TYPE_GR1)) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    if (param->gr_format == VDC5_GR_FORMAT_YCBCR422) {
+        /* Swapping of data read from buffer in the YCbCr422 format */
+        if (param->gr_ycc_swap >= VDC5_GR_YCCSWAP_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+    /* Swap setting in frame buffer reading */
+    if (param->gr_rdswa >= VDC5_WR_RD_WRSWA_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Graphics display area */
+    error = CheckRect(&param->gr_grc);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ReadDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeReadProcessCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Width of the image read from frame buffer */
+    if (param->width_read_fb != NULL) {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Graphics display area */
+    if (param->gr_grc != NULL) {
+        error = CheckRect(param->gr_grc);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+    }
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL) {
+        if ((*(param->gr_disp_sel) < VDC5_DISPSEL_IGNORED) || (*(param->gr_disp_sel) >= VDC5_DISPSEL_NUM)) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChangeReadProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write/read start parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StartProcessCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param)
+{
+    vdc5_error_t                error;
+    uint32_t                    graphics_types;
+    const vdc5_gr_disp_sel_t  * gr_disp_sel_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    gr_disp_sel_tmp = param->gr_disp_sel;
+    if (gr_disp_sel_tmp == NULL) {
+        error = VDC5_OK;
+        goto END;
+    }
+    /* Graphics display mode */
+    if (layer_id == VDC5_LAYER_ID_ALL) {
+        for (graphics_types = 0; graphics_types < VDC5_GR_TYPE_NUM; graphics_types++) {
+            if ((gr_disp_sel_tmp[graphics_types] < VDC5_DISPSEL_IGNORED) ||
+                    (gr_disp_sel_tmp[graphics_types] >= VDC5_DISPSEL_NUM)) {
+                error = VDC5_ERR_PARAM_UNDEFINED;
+                goto END;
+            }
+        }
+    } else {
+        if ((*gr_disp_sel_tmp < VDC5_DISPSEL_IGNORED) || (*gr_disp_sel_tmp >= VDC5_DISPSEL_NUM)) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_StartProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_StopProcess
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StopProcessCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_StopProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_ReleaseDataControl
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReleaseDataControlCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ReleaseDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on noise reduction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoNoiseReductCheckPrm (const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param)
+{
+    vdc5_error_t            error;
+    const vdc5_nr_param_t * nr_param;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_OK;
+        goto END;
+    }
+
+    /* Y/G signal noise reduction parameter */
+    nr_param = &param->y;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cb/B signal noise reduction parameter */
+    nr_param = &param->cb;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cr/R signal noise reduction parameter */
+    nr_param = &param->cr;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_VideoNoiseReductCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on color matrix setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageColorMatrixCheckPrm (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    vdc5_error_t    error;
+    int32_t         colormtx_index;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Color matrix module */
+    if (param->module >= VDC5_COLORMTX_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Operating mode */
+    if (param->mtx_mode >= VDC5_COLORMTX_MODE_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->module != VDC5_COLORMTX_IMGCNT) {
+        if ((param->mtx_mode == VDC5_COLORMTX_GBR_YCBCR) || (param->mtx_mode == VDC5_COLORMTX_YCBCR_YCBCR)) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Offset (DC) adjustment of Y/G, B, and R signal */
+    for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_OFFST_NUM; colormtx_index++) {
+        if (((uint32_t)param->offset[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_GAIN_NUM; colormtx_index++) {
+        if (((uint32_t)param->gain[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageColorMatrixCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sharpness setup parameter and enhancer-enabled area setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   sharp_param : Sharpness setup parameter
+ * @param[in]   enh_area    : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageEnhancementCheckPrm (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC5_IMG_IMPRV_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Sharpness parameter */
+    if (sharp_param != NULL) {
+        /* Sharpness control parameter (H1, H2, and H3) */
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Enhancer area */
+    if (enh_area != NULL) {
+        /* Vertical start position */
+        if (((uint32_t)enh_area->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->vs < (uint32_t)VDC5_CPARA_ENH_VS_LIMIT) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Height (vertical width) */
+        if (((uint32_t)enh_area->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Horizontal start position */
+        if (((uint32_t)enh_area->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->hs < (uint32_t)VDC5_CPARA_ENH_HS_LIMIT) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Horizontal width */
+        if (((uint32_t)enh_area->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageEnhancementCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on black stretch setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   param       : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageBlackStretchCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_black_t  * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC5_IMG_IMPRV_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    if (param != NULL) {
+        /* Black stretch start point */
+        if (((uint32_t)param->bkstr_st & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch depth */
+        if (((uint32_t)param->bkstr_d & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T1) */
+        if (((uint32_t)param->bkstr_t1 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T2) */
+        if (((uint32_t)param->bkstr_t2 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->bkstr_t2 == VDC5_BKSTR_T2_PROHIBITED) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageBlackStretchCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on alpha blending setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingCheckPrm (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_1_RD) && (layer_id != VDC5_LAYER_ID_2_RD) && (layer_id != VDC5_LAYER_ID_3_RD)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_AlphaBlendingCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on setup parameter for alpha blending in a rectangular area
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingRectCheckPrm (
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_1_RD) &&
+            (layer_id != VDC5_LAYER_ID_2_RD) &&
+            (layer_id != VDC5_LAYER_ID_3_RD) &&
+            (layer_id != VDC5_LAYER_ID_VIN_RD)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param != NULL) {
+        /* Rectangular area subjected to alpha blending */
+        if (param->gr_arc != NULL) {
+            /* Vertical start position */
+            if (((uint32_t)param->gr_arc->vs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Height (vertical width) */
+            if (((uint32_t)param->gr_arc->vw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal start position */
+            if (((uint32_t)param->gr_arc->hs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal width */
+            if (((uint32_t)param->gr_arc->hw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+        /* Alpha Blending in a rectangular area */
+        if (param->alpha_rect != NULL) {
+            /* Frame rate for alpha blending in a rectangular area */
+            if ((param->alpha_rect->gr_arc_coef < (int16_t)VDC5_CPARA_GR_ARC_COEF_MIN) || (param->alpha_rect->gr_arc_coef > (int16_t)VDC5_CPARA_GR_ARC_COEF_MAX)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_AlphaBlendingRectCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma-key setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChromakeyCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_error_t        error;
+    vdc5_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param != NULL) {
+        gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+        switch (gr_format_tmp) {
+            /* The following four cases are intentionally combined,
+              since the four types of graphics format are represented as 16 bit unsigned integer. */
+            case VDC5_GR_FORMAT_RGB565:
+            case VDC5_GR_FORMAT_ARGB1555:
+            case VDC5_GR_FORMAT_ARGB4444:
+            case VDC5_GR_FORMAT_RGBA5551:
+                if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u) ||
+                        ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u)) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_RGB888:
+                if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u) ||
+                        ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u)) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_CLUT8:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_CLUT4:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_CLUT1:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00000001) != 0u) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            default:
+                /* DO NOTHING */
+                break;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChromakeyCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on CLUT setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CLUTCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_clut_t   * const param)
+{
+    vdc5_error_t        error;
+    vdc5_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* The number of colors in CLUT */
+    if (param->color_num == 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+    if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1) {
+        /* CLUT1 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT1_NUM) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else if (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) {
+        /* CLUT4 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT4_NUM) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else {
+        /* CLUT8 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT8_NUM) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* Address of the area storing the CLUT data (in ARGB8888 format) */
+    if (param->clut == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_CLUTCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display calibration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayCalibrationCheckPrm (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_calibr_bright_t    * bright_tmp;
+    const vdc5_calibr_dither_t    * panel_dither_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL) {
+        /* Brightness (DC) adjustment of G signal */
+        if (((uint32_t)bright_tmp->pbrt_g & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of B signal */
+        if (((uint32_t)bright_tmp->pbrt_b & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of R signal */
+        if (((uint32_t)bright_tmp->pbrt_r & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL) {
+        /* Panel dither operation mode */
+        if (panel_dither_tmp->pdth_sel >= VDC5_PDTH_MD_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2) {
+            /* Pattern value (A)-(D) of 2x2 pattern dither */
+            if (((uint32_t)panel_dither_tmp->pdth_pa & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pb & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pc & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pd & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_DisplayCalibrationCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on gamma correction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_GammaCorrectionCheckPrm (const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param != NULL) {
+        /* Gain adjustment of area 0 to 31 of G signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_g_gain);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of B signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_b_gain);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of R signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_r_gain);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_GammaCorrectionCheckPrm() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Checks on VDC5 channel
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckChannel (const vdc5_channel_t ch)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if (ch >= VDC5_CHANNEL_NUM) {
+        error = VDC5_ERR_PARAM_CHANNEL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckChannel() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckLayerId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if ((layer_id < VDC5_LAYER_ID_ALL) || (layer_id >= VDC5_LAYER_ID_NUM)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+    if (layer_id == VDC5_LAYER_ID_VIN_RD) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID related to graphics
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckGraphicsTypeLayerId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if ((layer_id < VDC5_LAYER_ID_0_RD) || (layer_id > VDC5_LAYER_ID_OIR_RD)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+    if (layer_id == VDC5_LAYER_ID_VIN_RD) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckGraphicsTypeLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on horizontal/vertical timing of the VDC5 signals
+ * @param[in]   rect            : Horizontal/vertical timing of the VDC5 signals
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckRect (const vdc5_period_rect_t * const rect)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Vertical start position */
+    if (((uint32_t)rect->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->vs < (uint32_t)VDC5_CPARA_VS_MIN) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Height (vertical width) */
+    if (((uint32_t)rect->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->vs + (uint32_t)rect->vw) > (uint32_t)VDC5_CPARA_VS_VW_MAX) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+
+    /* Horizontal start position */
+    if (((uint32_t)rect->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->hs < (uint32_t)VDC5_CPARA_HS_MIN) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Horizontal width */
+    if (((uint32_t)rect->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->hs + (uint32_t)rect->hw) > (uint32_t)VDC5_CPARA_HS_HW_MAX) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckRect() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Horizontal (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Horizontal() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal (POLA/POLB)
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_HorizontalPol (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* POLA/POLB signal generation mode select */
+    if (lcd_tcon_timing->tcon_md >= VDC5_LCD_TCON_POLMD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_HorizontalPol() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for vertical panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Vertical (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Vertical() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for DE timing signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_DataEnable (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_DataEnable() */
+
+/**************************************************************************//**
+ * @brief       Checks on gain adjustment of area 0 to 31 of G/B/R signal
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31 of G/B/R signal
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckGammaCrct_GainAdjustment (const uint16_t * gam_gain)
+{
+    uint32_t        gain_index;
+    vdc5_error_t    error;
+
+    error = VDC5_OK;
+
+    if (gam_gain != NULL) {
+        for (gain_index = 0; gain_index < VDC5_GAM_GAIN_ADJ_NUM; gain_index++) {
+            if (((uint32_t)*gam_gain & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            gam_gain++;
+        }
+    }
+END:
+    return error;
+}   /* End of function CheckGammaCrct_GainAdjustment() */
+
+#endif      /* R_VDC5_CHECK_PARAMETERS */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_check_parameter.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,122 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_check_parameter.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver parameter check definitions
+******************************************************************************/
+
+#ifndef R_VDC5_CHECK_PARAMETER_H
+#define R_VDC5_CHECK_PARAMETER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+#ifdef      R_VDC5_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdc5_error_t VDC5_InitializeCheckPrm(const vdc5_channel_t ch, const vdc5_init_t * const param);
+vdc5_error_t VDC5_TerminateCheckPrm(const vdc5_channel_t ch);
+vdc5_error_t VDC5_VideoInputCheckPrm(const vdc5_channel_t ch, const vdc5_input_t * const param);
+vdc5_error_t VDC5_SyncControlCheckPrm(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+vdc5_error_t VDC5_DisplayOutputCheckPrm(const vdc5_channel_t ch, const vdc5_output_t * const param);
+vdc5_error_t VDC5_CallbackISRCheckPrm(const vdc5_channel_t ch, const vdc5_int_t * const param);
+vdc5_error_t VDC5_WriteDataControlCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param);
+vdc5_error_t VDC5_ChangeWriteProcessCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t  * const param);
+vdc5_error_t VDC5_ReadDataControlCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param);
+vdc5_error_t VDC5_ChangeReadProcessCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param);
+vdc5_error_t VDC5_StartProcessCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param);
+vdc5_error_t VDC5_StopProcessCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t VDC5_ReleaseDataControlCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t VDC5_VideoNoiseReductCheckPrm(const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param);
+vdc5_error_t VDC5_ImageColorMatrixCheckPrm(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+vdc5_error_t VDC5_ImageEnhancementCheckPrm(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_period_rect_t    * const enh_area);
+vdc5_error_t VDC5_ImageBlackStretchCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_black_t  * const param);
+vdc5_error_t VDC5_AlphaBlendingCheckPrm(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param);
+vdc5_error_t VDC5_AlphaBlendingRectCheckPrm(
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_alpha_blending_rect_t    * const param);
+vdc5_error_t VDC5_ChromakeyCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_chromakey_t  * const param);
+vdc5_error_t VDC5_CLUTCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_clut_t   * const param);
+vdc5_error_t VDC5_DisplayCalibrationCheckPrm(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+vdc5_error_t VDC5_GammaCorrectionCheckPrm(const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param);
+
+
+#endif      /* R_VDC5_CHECK_PARAMETERS */
+
+#endif  /* R_VDC5_CHECK_PARAMETER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_interrupt.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1671 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_interrupt.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver interrupt related processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     UNUSED_PARAM(param)             (void)(param)
+
+#define VDC5_INT_BIT_S0_VI_VSYNC    ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_LO_VSYNC    ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_S0_VSYNCERR    ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_VLINE          ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_S0_VFIELD      ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_IV1_VBUFERR    ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV3_VBUFERR    ((uint32_t)0x01000000u)
+#define VDC5_INT_BIT_IV5_VBUFERR    ((uint32_t)0x10000000u)
+#define VDC5_INT_BIT_IV6_VBUFERR    ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_WLINE       ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_S1_VI_VSYNC    ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_S1_LO_VSYNC    ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_S1_VSYNCERR    ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_S1_VFIELD      ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV2_VBUFERR    ((uint32_t)0x01000000u)
+#define VDC5_INT_BIT_IV4_VBUFERR    ((uint32_t)0x10000000u)
+#define VDC5_INT_BIT_S1_WLINE       ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_OIR_VI_VSYNC   ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_OIR_LO_VSYNC   ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_OIR_VLINE      ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_OIR_VFIELD     ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_IV7_VBUFERR    ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV8_VBUFERR    ((uint32_t)0x01000000u)
+
+#define VDC5_GR_UPDATE_P_VEN_BIT    ((uint32_t)0x00000010u)
+#define VDC5_SCL0_UPDATE_VEN_A_BIT  ((uint32_t)0x00000001u)
+
+/* Valid bit range */
+#define VDC5_INT_RANGE_0X000007FF   (0x000007FFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv2_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv4_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv7_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv8_vbuferr_ISR(const uint32_t int_sense);
+
+static void VDC5_Ch1_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv2_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv4_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv7_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv8_vbuferr_ISR(const uint32_t int_sense);
+
+/*! List of the callback function pointers */
+static void (*vdc5_int_callback[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(vdc5_int_type_t int_type);
+
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ * @param[in]   ch                              : Channel
+ * @param[in]   type                            : VDC5 interrupt type
+ * @retval      VDC5 Interrupt service routine
+ *****************************************************************************/
+void (*R_VDC5_GetISR (const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense)
+{
+    static void (* const isr_table[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(const uint32_t int_sense) = {
+        {
+            &VDC5_Ch0_s0_vi_vsync_ISR,
+            &VDC5_Ch0_s0_lo_vsync_ISR,
+            &VDC5_Ch0_s0_vsyncerr_ISR,
+            &VDC5_Ch0_vline_ISR,
+            &VDC5_Ch0_s0_vfield_ISR,
+            &VDC5_Ch0_iv1_vbuferr_ISR,
+            &VDC5_Ch0_iv3_vbuferr_ISR,
+            &VDC5_Ch0_iv5_vbuferr_ISR,
+            &VDC5_Ch0_iv6_vbuferr_ISR,
+            &VDC5_Ch0_s0_wline_ISR,
+            &VDC5_Ch0_s1_vi_vsync_ISR,
+            &VDC5_Ch0_s1_lo_vsync_ISR,
+            &VDC5_Ch0_s1_vsyncerr_ISR,
+            &VDC5_Ch0_s1_vfield_ISR,
+            &VDC5_Ch0_iv2_vbuferr_ISR,
+            &VDC5_Ch0_iv4_vbuferr_ISR,
+            &VDC5_Ch0_s1_wline_ISR,
+            &VDC5_Ch0_oir_vi_vsync_ISR,
+            &VDC5_Ch0_oir_lo_vsync_ISR,
+            &VDC5_Ch0_oir_vline_ISR,
+            &VDC5_Ch0_oir_vfield_ISR,
+            &VDC5_Ch0_iv7_vbuferr_ISR,
+            &VDC5_Ch0_iv8_vbuferr_ISR
+        },
+        {
+            &VDC5_Ch1_s0_vi_vsync_ISR,
+            &VDC5_Ch1_s0_lo_vsync_ISR,
+            &VDC5_Ch1_s0_vsyncerr_ISR,
+            &VDC5_Ch1_vline_ISR,
+            &VDC5_Ch1_s0_vfield_ISR,
+            &VDC5_Ch1_iv1_vbuferr_ISR,
+            &VDC5_Ch1_iv3_vbuferr_ISR,
+            &VDC5_Ch1_iv5_vbuferr_ISR,
+            &VDC5_Ch1_iv6_vbuferr_ISR,
+            &VDC5_Ch1_s0_wline_ISR,
+            &VDC5_Ch1_s1_vi_vsync_ISR,
+            &VDC5_Ch1_s1_lo_vsync_ISR,
+            &VDC5_Ch1_s1_vsyncerr_ISR,
+            &VDC5_Ch1_s1_vfield_ISR,
+            &VDC5_Ch1_iv2_vbuferr_ISR,
+            &VDC5_Ch1_iv4_vbuferr_ISR,
+            &VDC5_Ch1_s1_wline_ISR,
+            &VDC5_Ch1_oir_vi_vsync_ISR,
+            &VDC5_Ch1_oir_lo_vsync_ISR,
+            &VDC5_Ch1_oir_vline_ISR,
+            &VDC5_Ch1_oir_vfield_ISR,
+            &VDC5_Ch1_iv7_vbuferr_ISR,
+            &VDC5_Ch1_iv8_vbuferr_ISR
+        }
+    };
+    void (* isr_function)(const uint32_t int_sense);
+
+    isr_function = isr_table[ch][type];
+
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    /* Channel and interrupt type */
+    if ((ch >= VDC5_CHANNEL_NUM) || (type >= VDC5_INT_TYPE_NUM)) {
+        isr_function = 0;
+    }
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+
+    return isr_function;
+}   /* End of function R_VDC5_GetISR() */
+
+/**************************************************************************//**
+ * @brief       Disables all VDC5 interrupts
+ * @param[in]   ch                      : Channel
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Int_Disable (const vdc5_channel_t ch)
+{
+    const vdc5_regaddr_system_ctrl_t  * system_ctrl;
+    int32_t                             int_type;
+
+    system_ctrl = &vdc5_regaddr_system_ctrl[ch];
+
+    for (int_type = 0; int_type < VDC5_INT_TYPE_NUM; int_type++) {
+        vdc5_int_callback[ch][int_type] = 0;
+    }
+    /* Interrupt output off */
+    *(system_ctrl->syscnt_int4) = 0u;
+    *(system_ctrl->syscnt_int5) = 0u;
+    *(system_ctrl->syscnt_int6) = 0u;
+
+}   /* End of function VDC5_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief       Enables/disables the specified VDC5 interrupt
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Int_SetInterrupt (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    volatile uint32_t     * int_clhd_reg;
+    volatile uint32_t     * int_onoff_reg;
+    volatile uint32_t     * linenum_reg;
+    volatile uint16_t     * linenum16_reg;
+    volatile uint32_t     * linenum_update_reg;
+    uint32_t                mask_bit;
+    uint32_t                reg_data;
+    static const uint32_t   interrupt_bit_table[VDC5_INT_TYPE_NUM] = {
+        VDC5_INT_BIT_S0_VI_VSYNC,
+        VDC5_INT_BIT_S0_LO_VSYNC,
+        VDC5_INT_BIT_S0_VSYNCERR,
+        VDC5_INT_BIT_VLINE,
+        VDC5_INT_BIT_S0_VFIELD,
+        VDC5_INT_BIT_IV1_VBUFERR,
+        VDC5_INT_BIT_IV3_VBUFERR,
+        VDC5_INT_BIT_IV5_VBUFERR,
+        VDC5_INT_BIT_IV6_VBUFERR,
+        VDC5_INT_BIT_S0_WLINE,
+        VDC5_INT_BIT_S1_VI_VSYNC,
+        VDC5_INT_BIT_S1_LO_VSYNC,
+        VDC5_INT_BIT_S1_VSYNCERR,
+        VDC5_INT_BIT_S1_VFIELD,
+        VDC5_INT_BIT_IV2_VBUFERR,
+        VDC5_INT_BIT_IV4_VBUFERR,
+        VDC5_INT_BIT_S1_WLINE,
+        VDC5_INT_BIT_OIR_VI_VSYNC,
+        VDC5_INT_BIT_OIR_LO_VSYNC,
+        VDC5_INT_BIT_OIR_VLINE,
+        VDC5_INT_BIT_OIR_VFIELD,
+        VDC5_INT_BIT_IV7_VBUFERR,
+        VDC5_INT_BIT_IV8_VBUFERR
+    };
+
+    if (param->type < VDC5_INT_TYPE_IV6_VBUFERR) {
+        /* INT0: VDC5_INT_TYPE_S0_VI_VSYNC ~ INT7: VDC5_INT_TYPE_IV5_VBUFERR */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl[ch].syscnt_int1;
+        int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int4;
+    } else if (param->type < VDC5_INT_TYPE_S1_WLINE) {
+        /* INT8: VDC5_INT_TYPE_IV6_VBUFERR ~ INT15: VDC5_INT_TYPE_IV4_VBUFERR */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl[ch].syscnt_int2;
+        int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int5;
+    } else {
+        /* INT16: VDC5_INT_TYPE_S1_WLINE ~ INT22: VDC5_INT_TYPE_IV8_VBUFERR */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl[ch].syscnt_int3;
+        int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int6;
+    }
+    mask_bit = interrupt_bit_table[param->type];
+
+    /* Interrupt callback function pointer */
+    vdc5_int_callback[ch][param->type] = param->callback;
+
+    if (param->callback != 0) {
+        /* ON */
+        if ((*int_onoff_reg & mask_bit) == 0u) {
+            /* OFF to ON */
+            *int_onoff_reg |= mask_bit;
+            reg_data        = *int_onoff_reg;
+            *int_clhd_reg   = reg_data;
+        }
+
+        if (param->type == VDC5_INT_TYPE_VLINE) {
+            /* Specified line signal for panel output in graphics 3 */
+            linenum_reg         = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_clut;
+            linenum_update_reg  = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+            *linenum_reg        &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
+            *linenum_reg        |= (uint32_t)param->line_num;
+            *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
+        } else if (param->type == VDC5_INT_TYPE_S0_WLINE) {
+            /* Write specification line signal input to scaling-down control block in scaler 0 */
+            linenum16_reg       = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_int;
+            linenum_update_reg  = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
+            *linenum16_reg       = param->line_num;
+            *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
+        } else if (param->type == VDC5_INT_TYPE_S1_WLINE) {
+            /* Write specification line signal input to scaling-down control block in scaler 1 */
+            linenum16_reg       = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_int;
+            linenum_update_reg  = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
+            *linenum16_reg       = param->line_num;
+            *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
+        } else if (param->type == VDC5_INT_TYPE_OIR_VLINE) {
+            /* Specified line signal for panel output in output image generator */
+            linenum_reg         = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_clut;
+            linenum_update_reg  = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+            *linenum_reg        &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
+            *linenum_reg        |= (uint32_t)param->line_num;
+            *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
+        } else {
+            /* Do nothing */
+        }
+    } else {
+        /* OFF */
+        *int_onoff_reg &= (uint32_t)~mask_bit;
+        reg_data        = *int_onoff_reg;
+        *int_clhd_reg   = reg_data;
+    }
+
+}   /* End of function VDC5_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV1_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV3_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV5_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV6_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV2_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv2_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv2_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV4_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv4_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv4_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV7_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv7_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv7_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV8_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv8_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv8_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV1_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV3_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV5_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV6_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV2_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv2_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv2_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV4_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv4_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv4_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV7_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv7_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv7_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV8_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv8_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv8_vbuferr_ISR() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_register.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,3790 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+#include    "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     INITIAL_SCALING_PHASE          ((uint32_t)2048u)
+#define     SCALING_RATIO_SAME_SIZE        (4096u)
+/* Vsync signal delay control for OIR */
+#define     OIR_VSYNC_DELAY                 ((uint32_t)1u)
+
+#define     LVDS_LPHYACC_VALUE              ((uint32_t)0x0001u)
+
+/* Panel clock frequency division ratio */
+#define     VDC5_REG_CLKDIV_1_1            (1u)
+#define     VDC5_REG_CLKDIV_1_2            (2u)
+#define     VDC5_REG_CLKDIV_1_3            (3u)
+#define     VDC5_REG_CLKDIV_1_4            (4u)
+#define     VDC5_REG_CLKDIV_1_5            (5u)
+#define     VDC5_REG_CLKDIV_1_6            (6u)
+#define     VDC5_REG_CLKDIV_1_7            (7u)
+#define     VDC5_REG_CLKDIV_1_8            (8u)
+#define     VDC5_REG_CLKDIV_1_9            (9u)
+#define     VDC5_REG_CLKDIV_1_12           (12u)
+#define     VDC5_REG_CLKDIV_1_16           (16u)
+#define     VDC5_REG_CLKDIV_1_24           (24u)
+#define     VDC5_REG_CLKDIV_1_32           (32u)
+/* Panel clock select */
+#define     VDC5_REG_ICKSEL_IMG            (0x0000u)
+#define     VDC5_REG_ICKSEL_IMG_DV         (0x0000u)
+#define     VDC5_REG_ICKSEL_EXT_0          (0x1000u)
+#define     VDC5_REG_ICKSEL_EXT_1          (0x2000u)
+#define     VDC5_REG_ICKSEL_PERI           (0x3000u)
+#define     VDC5_REG_ICKSEL_LVDS           (0x0400u)
+#define     VDC5_REG_ICKSEL_LVDS_DIV7      (0x0800u)
+/* Output pin edge select */
+#define     VDC5_REG_TCON0_EDGE            (0x0040u)
+#define     VDC5_REG_TCON1_EDGE            (0x0020u)
+#define     VDC5_REG_TCON2_EDGE            (0x0010u)
+#define     VDC5_REG_TCON3_EDGE            (0x0008u)
+#define     VDC5_REG_TCON4_EDGE            (0x0004u)
+#define     VDC5_REG_TCON5_EDGE            (0x0002u)
+#define     VDC5_REG_TCON6_EDGE            (0x0001u)
+/* Panel dither output format select */
+#define     VDC5_REG_PATH_FORMAT_RGB888    (0x00000000u)
+#define     VDC5_REG_PATH_FORMAT_RGB666    (0x00010000u)
+#define     VDC5_REG_PATH_FORMAT_RGB565    (0x00020000u)
+#define     VDC5_REG_PATH_FORMAT_NON       (0x00000000u)
+/* Calculate scaling ratio use value */
+#define     VDC5_REG_FLOAT_1_0 (1.0f)
+#define     VDC5_REG_FLOAT_0_5 (0.5f)
+/* bits per pixel */
+#define     VDC5_REG_BIT_PER_PIXEL_RGB565    (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGB888    (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB1555  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB4444  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB8888  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT8     (8u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT4     (4u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT1     (1u)
+#define     VDC5_REG_BIT_PER_PIXEL_YCBCR422  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_YCBCR444  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGBA5551  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGBA8888  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_VALUE_8   (8u)
+/* Convert the color data from 4 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_17      (17u)
+/* Convert the color data from 5 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_263     (263u)
+#define     VDC5_REG_EXTENSION_VALUE_32      (32u)
+/* Convert the color data from 6 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_259     (259u)
+#define     VDC5_REG_EXTENSION_VALUE_64      (64u)
+/* Round off */
+#define     VDC5_REG_ROUND_OFF_VALUE_1       (1u)
+#define     VDC5_REG_ROUND_OFF_VALUE_2       (2u)
+/* Color mask data */
+#define     VDC5_REG_ALPHA_8BIT              (0xFF000000u)
+#define     VDC5_REG_RGB_24BIT_MASK          (0x00FFFFFFu)
+#define     VDC5_REG_COLOR_8BIT_MASK         (0x000000FFu)
+#define     VDC5_REG_COLOR_6BIT_MASK         (0x0000003Fu)
+#define     VDC5_REG_COLOR_5BIT_MASK         (0x0000001Fu)
+#define     VDC5_REG_COLOR_4BIT_MASK         (0x0000000Fu)
+#define     VDC5_REG_ARGB8888_GB_MASK        (0x00FFFF00u)
+
+/* RGB565 bits mask data */
+#define     VDC5_REG_RGB565_R_MASK           (0x0000F800u)
+#define     VDC5_REG_RGB565_G_MASK           (0x000007E0u)
+#define     VDC5_REG_RGB565_B_MASK           (0x0000001Fu)
+/* ARGB4444 bits mask data */
+#define     VDC5_REG_ARGB4444_R_MASK         (0x00000F00u)
+#define     VDC5_REG_ARGB4444_G_MASK         (0x000000F0u)
+#define     VDC5_REG_ARGB4444_B_MASK         (0x0000000Fu)
+/* ARGB1555 bits mask data */
+#define     VDC5_REG_ARGB1555_R_MASK         (0x00007C00u)
+#define     VDC5_REG_ARGB1555_G_MASK         (0x000003E0u)
+#define     VDC5_REG_ARGB1555_B_MASK         (0x0000001Fu)
+/* RGBA5551 bits mask data */
+#define     VDC5_REG_RGBA5551_R_MASK         (0x0000F800u)
+#define     VDC5_REG_RGBA5551_G_MASK         (0x000007C0u)
+#define     VDC5_REG_RGBA5551_B_MASK         (0x0000003Eu)
+
+/* bit pattern */
+#define     VDC5_REG_BIT31          (0x80000000u)
+#define     VDC5_REG_BIT29          (0x20000000u)
+#define     VDC5_REG_BIT28          (0x10000000u)
+#define     VDC5_REG_BIT24          (0x01000000u)
+#define     VDC5_REG_BIT20          (0x00100000u)
+#define     VDC5_REG_BIT16          (0x00010000u)
+#define     VDC5_REG_BIT15          (0x00008000u)
+#define     VDC5_REG_BIT14          (0x00004000u)
+#define     VDC5_REG_BIT13          (0x00002000u)
+#define     VDC5_REG_BIT12          (0x00001000u)
+#define     VDC5_REG_BIT8           (0x00000100u)
+#define     VDC5_REG_BIT4           (0x00000010u)
+#define     VDC5_REG_BIT2           (0x00000004u)
+#define     VDC5_REG_BIT1           (0x00000002u)
+#define     VDC5_REG_BIT0           (0x00000001u)
+
+/* shift value */
+#define     VDC5_REG_SHIFT_28       (28u)
+#define     VDC5_REG_SHIFT_24       (24u)
+#define     VDC5_REG_SHIFT_20       (20u)
+#define     VDC5_REG_SHIFT_16       (16u)
+#define     VDC5_REG_SHIFT_13       (13u)
+#define     VDC5_REG_SHIFT_12       (12u)
+#define     VDC5_REG_SHIFT_11       (11u)
+#define     VDC5_REG_SHIFT_10       (10u)
+#define     VDC5_REG_SHIFT_8        (8u)
+#define     VDC5_REG_SHIFT_6        (6u)
+#define     VDC5_REG_SHIFT_5        (5u)
+#define     VDC5_REG_SHIFT_4        (4u)
+#define     VDC5_REG_SHIFT_2        (2u)
+#define     VDC5_REG_SHIFT_1        (1u)
+
+/* register set value */
+#define VDC5_REG_BIT_0XFFFF0000     (0xFFFF0000u) /* scaler_0->scl0_frc2                     */
+/* scaler_1->scl0_frc2                     */
+/* register mask value */
+#define VDC5_REG_MASK_0XF7FF1C3F    (0xF7FF1C3Fu) /* mask img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X0000D000    (0x0000D000u) /* mask img_synthesizer->gr_ab1            */
+#define VDC5_REG_MASK_0X01FF00FF    (0x01FF00FFu) /* mask img_synthesizer->gr_ab6            */
+#define VDC5_REG_MASK_0X0000007F    (0x0000007Fu) /* mask output_ctrl->out_clk_phase         */
+#define VDC5_REG_MASK_0X11003313    (0x11003313u) /* mask output_ctrl->out_set               */
+#define VDC5_REG_MASK_0X00030000    (0x00030000u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X0007000D    (0x0007000Du) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00000300    (0x00000300u) /* mask scaler->scl1_wr5                   */
+#define VDC5_REG_MASK_0X0703FF02    (0x0703FF02u) /* mask regaddr_lvds->lclkselr             */
+#define VDC5_REG_MASK_0X07FF1F30    (0x07FF1F30u) /* mask regaddr_lvds->lpllsetr             */
+#define VDC5_REG_MASK_0X00010301    (0x00010301u) /* mask img_synthesizer->gr_flm1           */
+#define VDC5_REG_MASK_0X7FFF03FF    (0x7FFF03FFu) /* mask img_synthesizer->gr_flm3           */
+#define VDC5_REG_MASK_0X0000E000    (0x0000E000u) /* mask img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X00007F33    (0x00007F33u) /* mask input_ctrl->imgcnt_nr_cnt0         */
+#define VDC5_REG_MASK_0X00FF0000    (0x00FF0000u) /* mask img_synthesizer->gr_ab7            */
+#define VDC5_REG_MASK_0X00300000    (0x00300000u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X00003333    (0x00003333u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X00007111    (0x00007111u) /* mask input_ctrl->inp_sel_cnt            */
+#define VDC5_REG_MASK_0X11110113    (0x11110113u) /* mask input_ctrl->inp_ext_sync_cnt       */
+#define VDC5_REG_MASK_0X000007FF    (0x000007FFu) /* mask img_synthesizer->gr_flm5           */
+#define VDC5_REG_MASK_0X0000FFFF    (0x0000FFFFu) /* mask scaler->scl0_ds4                   */
+/*      caler->scl0_us5                    */
+#define VDC5_REG_MASK_0X00000011    (0x00000011u) /* mask scaler->scl0_ds1                   */
+/*      scaler->scl0_us1                   */
+#define VDC5_REG_MASK_0X00000070    (0x00000070u) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00000080    (0x00000080u) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00003110    (0x00003110u) /* mask output_ctrl->tcon_tim_pola2        */
+/*      output_ctrl->tcon_tim_polb2        */
+#define VDC5_REG_MASK_0X000000FF    (0x000000FFu) /* mask scaler_0->scl0_frc5                */
+/*      scaler_1->scl0_frc5                */
+#define VDC5_REG_MASK_0X0000003F    (0x0000003Fu) /* mask img_synthesizer->gr_flm6           */
+/*      img_qlty_imp->adj_enh_shp1         */
+#define VDC5_REG_MASK_0XFF000000    (0xFF000000u) /* mask img_synthesizer->gr_ab10           */
+/*      img_synthesizer->gr_ab11           */
+#define VDC5_REG_MASK_0X00000110    (0x00000110u) /* mask output_ctrl->tcon_tim_sth2         */
+/*      output_ctrl->tcon_tim_stb2         */
+/*      output_ctrl->tcon_tim_cpv2         */
+#define VDC5_REG_MASK_0X00000007    (0x00000007u) /* mask *(output_pin_regaddr[tcon_pin])    */
+/*      img_synthesizer->gr_flm2           */
+/*      img_synthesizer->gr_flm2           */
+#define VDC5_REG_MASK_0X07FF0000    (0x07FF0000u) /* mask scaler_0->scl0_frc4                */
+/*      scaler_1->scl0_frc4                */
+/*      img_synthesizer->gr_flm5           */
+/*      img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X0FFF0FFF    (0x0FFF0FFFu) /* mask                                    */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+#define VDC5_REG_MASK_0X00000003    (0x00000003u) /* mask img_synthesizer->gr_ab1            */
+/*      regaddr_lvds->lphyacc              */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void SetVideoExternalInput(
+    const vdc5_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc5_regaddr_input_ctrl_t * const input_ctrl);
+static void SetInitialConnection(const vdc5_channel_t ch);
+static void SetGrapicsBackgroundColor(const vdc5_channel_t ch);
+static void SetScalerBackgroundColor(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space);
+static void SetLcdTcon_STVA_VS(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STVB_VE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STH_HS(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STB_HE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_CPV_GCK(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLA(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLB(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_DE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetScalingDown(
+    const vdc5_scalingdown_rot_t    * const scldw_rot,
+    const vdc5_res_inter_t                  res_inter,
+    const vdc5_regaddr_scaler_t     * const scaler);
+static void SetScalingUp(
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_onoff_t                  adj_sel,
+    const vdc5_onoff_t                  ip_conversion,
+    const vdc5_wr_md_t                  res_ds_wr_md,
+    const vdc5_gr_ln_off_dir_t          ln_off_dir,
+    const vdc5_regaddr_scaler_t * const scaler);
+static uint32_t CalcScalingRatio(
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc5_onoff_t  adj_sel,
+    const vdc5_onoff_t  round_up);
+static void SetInputCntrlColorMtx(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+static vdc5_onoff_t ConfirmGraphicsEnlargement(
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc);
+static void SetScalerGraphics(
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_onoff_t                  gr_enlarge);
+static uint32_t DisplayStartPixelSetting(const uint32_t gr_base, const vdc5_gr_format_t gr_format);
+static vdc5_onoff_t SetCascade(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge);
+static void SetupGraphicsVIN(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge);
+static void ChangeGraphicsVIN(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge);
+static void SetImgQaImproverColorMtx(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space);
+
+static void SetRwProcAbility_Write_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Write_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Write_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_2(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_3(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRegUpdateRwEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+
+static void SetGraphicsDisplayMode(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_gr_disp_sel_t    * const gr_disp_sel);
+static void SetColorMatrix(
+    const vdc5_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc5_regaddr_color_matrix_t   * const color_matrix);
+static void SetImageEnhancementSharpness(
+    const vdc5_onoff_t                          shp_h_on,
+    const vdc5_enhance_sharp_t          * const sharp_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetImageEnhancementLti(
+    const vdc5_onoff_t                          lti_h_on,
+    const vdc5_enhance_lti_t            * const lti_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetAlphaRectArea(
+    const vdc5_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc5_regaddr_img_synthesizer_t    * const img_synthesizer);
+static void SetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
+static uint32_t ColorConversion(const vdc5_gr_format_t gr_format, const uint32_t input_color);
+static uint32_t ColorConversionFrom4to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom5to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom6to8(const uint32_t color_value);
+static uint32_t ColorConversionIntoAgbr(const uint32_t color_value);
+static void Set_Clut(const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut);
+static void Set_StartThreshold_Gamma(const uint8_t * gam_th, volatile uint32_t * const * const gam_area);
+static void Set_GainAdjustment_Gamma(const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut);
+static void Wait_200_usec(void);
+
+/*! Color matrix offset (DC) adjustment (YG, B, and R) */
+static const uint16_t colormtx_offset_adj[VDC5_COLORMTX_OFFST_NUM] = {
+    (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET
+};
+/*! Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+static const uint16_t colormtx_gain_adj[VDC5_COLORMTX_MODE_NUM][VDC5_COLORMTX_GAIN_NUM] = {
+    {   /* GBR to GBR */
+        (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+    },
+    {   /* GBR to YCbCr */
+        (uint16_t)VDC5_COLORCONV_Y_G,  (uint16_t)VDC5_COLORCONV_Y_B,  (uint16_t)VDC5_COLORCONV_Y_R,
+        (uint16_t)VDC5_COLORCONV_CB_G, (uint16_t)VDC5_COLORCONV_CB_B, (uint16_t)VDC5_COLORCONV_CB_R,
+        (uint16_t)VDC5_COLORCONV_CR_G, (uint16_t)VDC5_COLORCONV_CR_B, (uint16_t)VDC5_COLORCONV_CR_R
+    },
+    {   /* YCbCr to GBR */
+        (uint16_t)VDC5_COLORCONV_G_Y, (uint16_t)VDC5_COLORCONV_G_CB, (uint16_t)VDC5_COLORCONV_G_CR,
+        (uint16_t)VDC5_COLORCONV_B_Y, (uint16_t)VDC5_COLORCONV_B_CB, (uint16_t)VDC5_COLORCONV_B_CR,
+        (uint16_t)VDC5_COLORCONV_R_Y, (uint16_t)VDC5_COLORCONV_R_CB, (uint16_t)VDC5_COLORCONV_R_CR
+    },
+    {   /* YCbCr to YCbCr */
+        (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+    }
+};
+
+static void (* const rw_proc_function_tbl[VDC5_LAYER_ID_NUM])(const vdc5_channel_t ch, const vdc5_onoff_t ability) = {
+    &SetRwProcAbility_Write_0,          /* Write scaler 0 */
+    &SetRwProcAbility_Write_1,          /* Write scaler 1 */
+    &SetRwProcAbility_Write_OIR,        /* Write OIR */
+    &SetRwProcAbility_Read_0,           /* Read graphics 0 */
+    &SetRwProcAbility_Read_1,           /* Read graphics 1 */
+    &SetRwProcAbility_Read_2,           /* Read graphics 2 */
+    &SetRwProcAbility_Read_3,           /* Read graphics 3 */
+    0,                                  /* Read VIN */
+    &SetRwProcAbility_Read_OIR          /* Read OIR */
+};
+
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Initialize (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+    const vdc5_lvds_t         * lvds_tmp;
+    const vdc5_regaddr_lvds_t * regaddr_lvds;
+    volatile uint32_t           counter;
+    uint16_t                    syscnt_panel_clk_tmp;
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    volatile uint32_t         * inp_sel_cnt_reg;
+    static const uint16_t       panel_dcdr_tbl[VDC5_PANEL_CLKDIV_NUM] = {
+        /* Panel clock frequency division ratio */
+        (uint16_t)VDC5_REG_CLKDIV_1_1, (uint16_t)VDC5_REG_CLKDIV_1_2,  (uint16_t)VDC5_REG_CLKDIV_1_3,  (uint16_t)VDC5_REG_CLKDIV_1_4,
+        (uint16_t)VDC5_REG_CLKDIV_1_5, (uint16_t)VDC5_REG_CLKDIV_1_6,  (uint16_t)VDC5_REG_CLKDIV_1_7,  (uint16_t)VDC5_REG_CLKDIV_1_8,
+        (uint16_t)VDC5_REG_CLKDIV_1_9, (uint16_t)VDC5_REG_CLKDIV_1_12, (uint16_t)VDC5_REG_CLKDIV_1_16, (uint16_t)VDC5_REG_CLKDIV_1_24,
+        (uint16_t)VDC5_REG_CLKDIV_1_32
+    };
+    static const uint16_t       panel_icksel_tbl[VDC5_PANEL_ICKSEL_NUM] = {
+        /* Panel clock select */
+        (uint16_t)VDC5_REG_ICKSEL_IMG,  (uint16_t)VDC5_REG_ICKSEL_IMG_DV, (uint16_t)VDC5_REG_ICKSEL_EXT_0, (uint16_t)VDC5_REG_ICKSEL_EXT_1,
+        (uint16_t)VDC5_REG_ICKSEL_PERI, (uint16_t)VDC5_REG_ICKSEL_LVDS,   (uint16_t)VDC5_REG_ICKSEL_LVDS_DIV7
+    };
+
+    syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+    /* LVDS */
+    lvds_tmp = param->lvds;
+    if (lvds_tmp != NULL) {
+        regaddr_lvds = &vdc5_regaddr_lvds;
+
+        /* Output from the LVDS PLL is disabled. */
+        *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
+        /* Controls power-down for the LVDS PLL: Power-down state */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
+        for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+            /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+        }
+
+        /* LPHYACC */
+        *(regaddr_lvds->lphyacc) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(regaddr_lvds->lphyacc) |= LVDS_LPHYACC_VALUE;
+        /* LCLKSELR: LVDS clock select register */
+        *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_MASK_0X0703FF02;
+        /* The clock input to frequency divider 1 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_in_clk_sel << VDC5_REG_SHIFT_24;
+        /* The frequency dividing value (NIDIV) for frequency divider 1 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_idiv_set << VDC5_REG_SHIFT_16;
+        /* Internal parameter setting for LVDS PLL */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvdspll_tst << VDC5_REG_SHIFT_10;
+        /* The frequency dividing value (NODIV) for frequency divider 2 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_odiv_set << VDC5_REG_SHIFT_8;
+        if (lvds_tmp->lvds_vdc_sel != VDC5_CHANNEL_0) {
+            /* A channel in VDC5 whose data is to be output through the LVDS */
+            *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT1;
+        }
+
+        /* LPLLSETR: LVDS PLL setting register */
+        *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_MASK_0X07FF1F30;
+        /* The frequency dividing value (NFD) for the feedback frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_fd << VDC5_REG_SHIFT_16;
+        /* The frequency dividing value (NRD) for the input frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_rd << VDC5_REG_SHIFT_8;
+        /* The frequency dividing value (NOD) for the output frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_od << VDC5_REG_SHIFT_4;
+
+        for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+            /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+        }
+        /* Controls power-down for the LVDS PLL: Normal operation */
+        *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_BIT0;
+
+        /* Wait for 200 usec. */
+        Wait_200_usec();
+
+        /* Output from the LVDS PLL is enabled. */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT4;
+    }
+
+    inp_sel_cnt_reg = vdc5_regaddr_input_ctrl[ch].inp_sel_cnt;
+    /* Input select */
+    if (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV) {
+        *inp_sel_cnt_reg |= (uint32_t)VDC5_REG_BIT20;
+    } else {
+        *inp_sel_cnt_reg &= (uint32_t)~VDC5_REG_BIT20;
+    }
+    syscnt_panel_clk_tmp    = panel_dcdr_tbl[param->panel_dcdr];
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp |
+                                         (uint32_t)panel_icksel_tbl[param->panel_icksel]);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+    /* Enable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp | VDC5_REG_BIT8);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+}   /* End of function VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for termination
+ * @param[in]   ch                      : Channel
+ * @retval      None
+******************************************************************************/
+void VDC5_Terminate (const vdc5_channel_t ch)
+{
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    uint16_t                    syscnt_panel_clk_tmp;
+    vdc5_resource_state_t       rsrc_state;
+    vdc5_onoff_t                lvds_ref;
+    const vdc5_regaddr_lvds_t * regaddr_lvds;
+    volatile uint32_t           counter;
+
+    syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+    rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {       /* LVDS PLL clock is set. */
+        lvds_ref = VDC5_ShrdPrmGetLvdsClkRef();
+        if (lvds_ref == VDC5_OFF) {     /* LVDS PLL clock is not referred. */
+            regaddr_lvds = &vdc5_regaddr_lvds;
+
+            /* Output from the LVDS PLL is disabled. */
+            *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
+            /* Controls power-down for the LVDS PLL: Power-down state */
+            *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
+            for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+                /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+            }
+        }
+    }
+}   /* End of function VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for video input
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    const vdc5_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc5_sync_delay_t           * dly_tmp;
+    const vdc5_ext_in_sig_t           * ext_sig_tmp;
+
+    input_ctrl = &vdc5_regaddr_input_ctrl[ch];
+
+    /* Input select */
+    if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+        *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_BIT20;
+    } else {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT20;
+    }
+    /* Vsync signal 1/2fH and 1/4fH phase timing */
+    *(input_ctrl->inp_vsync_ph_adj)  = (uint32_t)param->inp_fh50 << VDC5_REG_SHIFT_16;
+    *(input_ctrl->inp_vsync_ph_adj) |= (uint32_t)param->inp_fh25;
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL) {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        *(input_ctrl->inp_dly_adj)  = (uint32_t)dly_tmp->inp_vs_dly_l << VDC5_REG_SHIFT_24;
+        /* Field differentiation signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_fld_dly << VDC5_REG_SHIFT_16;
+        /* Vsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_vs_dly << VDC5_REG_SHIFT_8;
+        /* Hsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_hs_dly;
+    }
+
+    /* Horizontal noise reduction operating mode, Y/Cb/Cr mode */
+    *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT20;
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp != NULL) {
+        /* Setting external input video signal */
+        SetVideoExternalInput(ext_sig_tmp, input_ctrl);
+
+        /* Horizontal noise reduction operating mode, G/B/R mode */
+        if ((ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+                (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+                (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB565)) {
+            *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT20;
+        }
+    }
+
+    /* Register update control register (INP_UPDATE)
+       b4       INP_EXT_UPDATE
+       b0       INP_IMG_UPDATE */
+    *(input_ctrl->inp_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+}   /* End of function VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for sync control
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync signal control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler_0;
+    const vdc5_regaddr_scaler_t   * scaler_1;
+    const vdc5_regaddr_scaler_t   * scaler_oir;
+    uint32_t                        full_scr;
+
+    scaler_0    = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+    scaler_1    = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+    scaler_oir  = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+
+    if (param->vsync_cpmpe != NULL) {
+        /* Frequent Vsync signal masking period */
+        *(scaler_0->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
+        *(scaler_1->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
+        /* Missing-Sync compensating pulse output wait time */
+        *(scaler_0->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
+        *(scaler_1->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
+        /* Frequent Vsync signal masking and missing Vsync signal compensation */
+        *(scaler_0->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
+    } else {
+        /* Frequent Vsync signal masking and missing Vsync signal compensation are disabled, if unnecessary. */
+        *(scaler_0->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
+        *(scaler_1->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
+    }
+    /* In OIR, frequent Vsync signal masking and missing Vsync signal compensation are set to off. */
+    *(scaler_oir->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+    *(scaler_oir->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+
+    /* Hsync period setting and free-running Vsync period initialization */
+    *(scaler_0->scl0_frc4)      = (uint32_t)param->res_fh;
+    *(scaler_1->scl0_frc4)      = (uint32_t)param->res_fh;
+    *(scaler_oir->scl0_frc4)    = (uint32_t)param->res_fh;
+    /* Vsync signal output select (free-running Vsync on/off control) */
+    if (param->res_vs_sel == VDC5_OFF) {
+        *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+    } else {
+        *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(scaler_0->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
+        *(scaler_1->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(scaler_1->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
+    }
+    /* In OIR, external input Vsync signal is selected automatically. */
+    *(scaler_oir->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+
+    /* Sync signal output and full-screen enable signal select: Scaler 0 */
+    *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+    *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+
+    /* Vsync signal delay control */
+    *(scaler_0->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+    *(scaler_0->scl0_frc5) |= (uint32_t)param->res_vsdly;
+    *(scaler_1->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+    *(scaler_1->scl0_frc5) |= (uint32_t)param->res_vsdly;
+    *(scaler_oir->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+    *(scaler_oir->scl0_frc5) |= OIR_VSYNC_DELAY;
+
+    /* Full-screen enable signal */
+    full_scr  = (uint32_t)param->res_f.vs << VDC5_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.vw;
+
+    *(scaler_0->scl0_frc6)   = full_scr;
+    *(scaler_1->scl0_frc6)   = full_scr;
+    *(scaler_oir->scl0_frc6) = full_scr;
+
+    full_scr  = (uint32_t)param->res_f.hs << VDC5_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.hw;
+
+    *(scaler_0->scl0_frc7)   = full_scr;
+    *(scaler_1->scl0_frc7)   = full_scr;
+    *(scaler_oir->scl0_frc7) = full_scr;
+
+    /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+       b8       SCL0_UPDATE
+       b4       SCL0_VEN_B */
+    *(scaler_0->scl0_update)   |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    *(scaler_1->scl0_update)   |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    *(scaler_oir->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+    SetInitialConnection(ch);
+
+    VDC5_ShrdPrmSetUndSel(ch, VDC5_OFF);
+}   /* End of function VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display output
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    const vdc5_regaddr_output_ctrl_t      * output_ctrl;
+    volatile uint32_t                     * output_pin_regaddr[VDC5_LCD_TCON_PIN_NUM];
+    uint32_t                                tcon_sig_index;
+    const vdc5_lcd_tcon_timing_t  * const * lcd_tcon_timing;
+    static void                    (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+        const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+        const vdc5_regaddr_output_ctrl_t    * const output_ctrl) = {
+        &SetLcdTcon_STVA_VS,    /* STVA/VS */
+        &SetLcdTcon_STVB_VE,    /* STVB/VE */
+        &SetLcdTcon_STH_HS,     /* STH_HS */
+        &SetLcdTcon_STB_HE,     /* STB_HE */
+        &SetLcdTcon_CPV_GCK,    /* CPV_GCK */
+        &SetLcdTcon_POLA,       /* POLA */
+        &SetLcdTcon_POLB,       /* POLB */
+        &SetLcdTcon_DE          /* DE */
+    };
+    const uint32_t                      output_pin_edge[VDC5_LCD_TCON_PIN_NUM] = {
+        VDC5_REG_TCON0_EDGE, VDC5_REG_TCON1_EDGE, VDC5_REG_TCON2_EDGE, VDC5_REG_TCON3_EDGE,
+        VDC5_REG_TCON4_EDGE, VDC5_REG_TCON5_EDGE, VDC5_REG_TCON6_EDGE
+    };
+    vdc5_lcd_tcon_pin_t                 tcon_pin_tmp;
+    const vdc5_gr_disp_sel_t            gr_disp_sel_tbl[VDC5_GR_TYPE_NUM] = {
+        /* Graphics display mode for initialization */
+        VDC5_DISPSEL_BACK,              /* Graphics 0 */
+        VDC5_DISPSEL_LOWER,             /* Graphics 1 */
+        VDC5_DISPSEL_LOWER,             /* Graphics 2 */
+        VDC5_DISPSEL_LOWER,             /* Graphics 3 */
+        VDC5_DISPSEL_IGNORED,           /* VIN */
+        VDC5_DISPSEL_BACK               /* OIR */
+    };
+    const uint32_t                      dither_format[VDC5_LCD_OUTFORMAT_NUM] = {
+        /* Panel dither output format select */
+        VDC5_REG_PATH_FORMAT_RGB888, VDC5_REG_PATH_FORMAT_RGB666,
+        VDC5_REG_PATH_FORMAT_RGB565, VDC5_REG_PATH_FORMAT_NON
+    };
+
+    output_ctrl = &vdc5_regaddr_output_ctrl[ch];
+
+    /* 1/2fH timing */
+    *(output_ctrl->tcon_tim)  = (uint32_t)param->tcon_half << VDC5_REG_SHIFT_16;
+    /* Offset Hsync signal timing */
+    *(output_ctrl->tcon_tim) |= (uint32_t)param->tcon_offset;
+
+    /* Create output pin register address table */
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_0] = output_ctrl->tcon_tim_stva2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_1] = output_ctrl->tcon_tim_stvb2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_2] = output_ctrl->tcon_tim_sth2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_3] = output_ctrl->tcon_tim_stb2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_4] = output_ctrl->tcon_tim_cpv2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_5] = output_ctrl->tcon_tim_pola2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_6] = output_ctrl->tcon_tim_polb2;
+
+    /* Clear output phase control of LCT_TCON0~6 pin */
+    *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_MASK_0X0000007F;
+    /* LCD TCON */
+    lcd_tcon_timing = param->outctrl;
+    for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++) {
+        if (*lcd_tcon_timing != NULL) {
+            /* Setting LCD TCON */
+            tcon_function_tbl[tcon_sig_index](*lcd_tcon_timing, output_ctrl);
+
+            tcon_pin_tmp = (*lcd_tcon_timing)->tcon_pin;
+            if (tcon_pin_tmp != VDC5_LCD_TCON_PIN_NON) {
+                /* LCD TCON output pin select */
+                *(output_pin_regaddr[tcon_pin_tmp]) &= (uint32_t)~VDC5_REG_MASK_0X00000007;
+                *(output_pin_regaddr[tcon_pin_tmp]) |= tcon_sig_index;
+                /* Output phase control of LCT_TCON pin */
+                if ((*lcd_tcon_timing)->outcnt_edge != VDC5_EDGE_RISING) {
+                    *(output_ctrl->out_clk_phase) |= output_pin_edge[tcon_pin_tmp];
+                }
+            }
+        }
+        lcd_tcon_timing++;
+    }
+
+    *(output_ctrl->out_set) &= (uint32_t)~VDC5_REG_MASK_0X11003313;
+    /* Bit endian change ON/OFF control */
+    if (param->out_endian_on != VDC5_OFF) {
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT28;
+    }
+    /* B/R signal swap ON/OFF control */
+    if (param->out_swap_on != VDC5_OFF) {
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT24;
+    }
+    /* Output format select */
+    *(output_ctrl->out_set) |= (uint32_t)param->out_format << VDC5_REG_SHIFT_12;
+
+    /* Panel dither output format select */
+    *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00030000;
+    *(output_ctrl->out_pdtha) |= dither_format[param->out_format];
+
+    if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB) {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_frq_sel << VDC5_REG_SHIFT_8;
+        /* Scan direction select */
+        if (param->out_dir_sel != VDC5_LCD_SERIAL_SCAN_FORWARD) {
+            *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT4;
+        }
+        /* Clock phase adjustment */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_phase;
+    } else {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_LCD_PARALLEL_CLKFRQ_1 << VDC5_REG_SHIFT_8;
+    }
+
+    /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+    if (param->outcnt_lcd_edge == VDC5_EDGE_RISING) {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT8;
+    } else {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT8;
+    }
+
+    /* Set background color */
+    SetGrapicsBackgroundColor(ch);
+    /* Initialize graphics display mode */
+    SetGraphicsDisplayMode(ch, VDC5_LAYER_ID_ALL, gr_disp_sel_tbl);
+
+    /* TCON register update control register (TCON_UPDATE)
+       b0       TCON_VEN */
+    *(output_ctrl->tcon_update) |= (uint32_t)VDC5_REG_BIT0;
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write control processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_WriteDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    const vdc5_scalingdown_rot_t  * scldw_rot;
+
+    scaler      = &vdc5_regaddr_scaler[ch][scaling_id];
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X0007000D;
+    /* Swap setting in frame buffer writing */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_wrswa << VDC5_REG_SHIFT_16;
+    /* Frame buffer video-signal writing format */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_md << VDC5_REG_SHIFT_2;
+    /* Transfer burst length for frame buffer writing */
+    if (param->res_bst_md != VDC5_BST_MD_32BYTE) {
+        *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    /* Frame buffer base address */
+    *(scaler->scl1_wr2) = (uint32_t)param->base;
+    /* Frame buffer line offset address[byte] */
+    *(scaler->scl1_wr3) = param->ln_off << VDC5_REG_SHIFT_16;
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    *(scaler->scl1_wr3) |= param->flm_num;
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u) {
+        *(scaler->scl1_wr4) = param->flm_off;
+    }
+
+    /* Writing rate */
+    *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_MASK_0X00000300;
+    *(scaler->scl1_wr5) |= (uint32_t)param->res_fs_rate << VDC5_REG_SHIFT_8;
+
+    /* Dither correction on/off */
+    if (param->res_dth_on == VDC5_OFF) {
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT4;
+    } else {
+        *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Bit Reduction */
+    if (param->res_md == VDC5_RES_MD_RGB565) {
+        /* On */
+        *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT0;
+    } else {
+        /* Off */
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        /* Vertical and horizontal width after scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
+
+        /* Vertical scaling-down and horizontal scaling-down : OFF */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
+
+        /* Field operating mode select is fixed to progressive */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
+    } else {
+        /* Scaler 0 or 1 */
+        /* Field determination signal delay control */
+        if (param->flm_num == 0u) {
+            /* Frame buffer: One plane */
+            *(scaler->scl0_frc5) &= (uint32_t)~VDC5_REG_BIT8;
+        } else {
+            /* Frame buffer: Two planes or more */
+            *(scaler->scl0_frc5) |= (uint32_t)VDC5_REG_BIT8;
+        }
+
+        /* Horizontal prefilter */
+        if (scldw_rot->res_pfil_sel == VDC5_OFF) {
+            *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+        } else {
+            *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+        }
+        /* Number of valid lines in vertical direction output by scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+        /* Number of valid horizontal pixels output by scaling-down control block */
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+        /* Scaling-down */
+        SetScalingDown(scldw_rot, param->res_inter, scaler);
+
+        /* Frame buffer writing mode for image processing */
+        *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+        *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+        /* Field operating mode select */
+        if (param->res_inter == VDC5_RES_INTER_PROGRESSIVE) {
+            /* Progressive */
+            *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
+        } else {
+            /* Interlace */
+            *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT12;
+        }
+        /* Write field select */
+        if (param->res_fld_sel == VDC5_RES_FLD_SEL_TOP) {
+            /* Top field */
+            *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT4;
+        } else {
+            /* Bottom field */
+            *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT4;
+        }
+
+        /* Frame buffer for bottom */
+        if (param->btm_base != NULL) {
+            /* SC_RES_TB_ADD_MOD */
+            *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_MASK_0X00000080;
+
+            /* Frame buffer base address */
+            *(scaler->scl1_wr8) = (uint32_t)param->btm_base;
+            /* Frame buffer line offset address[byte] */
+            *(scaler->scl1_wr9)  = param->ln_off << VDC5_REG_SHIFT_16;
+            /* Number of frames of buffer to be written to (defined by res_flm_num + 1) */
+            *(scaler->scl1_wr9) |= param->flm_num;
+            /* Frame buffer frame offset address */
+            if (param->flm_num != 0u) {
+                *(scaler->scl1_wr10) = param->flm_off;
+            }
+        } else {
+            /* SC_RES_TB_ADD_MOD */
+            *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000080;
+        }
+    }
+
+    /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+    /* Register update control register (SC0/SC1/OIR_SCL1_UPDATE)
+       b16      SCL1_UPDATE_A
+       b4       SCL1_VEN_B
+       b0       SCL1_VEN_A */
+    *(scaler->scl1_update)   |= (uint32_t)(VDC5_REG_BIT16 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+    if (scaling_id != VDC5_SC_TYPE_OIR) {
+        SetInputCntrlColorMtx(ch, scaling_id);
+    }
+}   /* End of function VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write change processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ChangeWriteProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    const vdc5_scalingdown_rot_t  * scldw_rot;
+    vdc5_res_inter_t                res_inter_tmp;
+
+    scaler      = &vdc5_regaddr_scaler[ch][scaling_id];
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        /* Vertical and horizontal width after scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
+    } else {
+        /* Scaler 0 or 1 */
+        /* Horizontal prefilter */
+        if (scldw_rot->res_pfil_sel == VDC5_OFF) {
+            *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+        } else {
+            *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+        }
+        /* Number of valid lines in vertical direction output by scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+        /* Number of valid horizontal pixels output by scaling-down control block */
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+        /* Progressive or interlace */
+        res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
+        /* Scaling-down */
+        SetScalingDown(scldw_rot, res_inter_tmp, scaler);
+
+        /* Frame buffer writing mode for image processing */
+        *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+        *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+        /* Register update control register (SC0/SC1)
+           b4       SCL1_VEN_B
+           b0       SCL1_VEN_A */
+        *(scaler->scl1_update)   |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+    }
+
+    /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+}   /* End of function VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read control processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ReadDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_qlty_imp_t     * img_qlty_imp;
+    vdc5_width_read_fb_t                  * w_read_fb;
+    vdc5_onoff_t                            graphics_enlargement;
+    vdc5_color_space_t                      color_space;
+    vdc5_resource_state_t                   rsrc_state;
+    uint32_t                                reg_data;
+
+    w_read_fb = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, param->gr_flm_sel, w_read_fb, &param->gr_grc);
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+            (graphics_id == VDC5_GR_TYPE_GR1) ||
+            (graphics_id == VDC5_GR_TYPE_OIR)) {
+        SetScalerGraphics(ch, graphics_id, w_read_fb, &param->gr_grc, param->gr_flm_sel, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_MASK_0X00010301;
+    /* Line offset address direction of the frame buffer */
+    if (param->gr_ln_off_dir != VDC5_GR_LN_OFF_DIR_INC) {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Frame buffer address setting signal */
+    *(img_synthesizer->gr_flm1) |= (uint32_t)param->gr_flm_sel << VDC5_REG_SHIFT_8;
+    /* Frame buffer burst transfer mode */
+    if (param->gr_bst_md != VDC5_BST_MD_32BYTE) {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT0;
+    }
+    /* Sets the frame buffer number for distortion correction */
+    if (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION) {
+        if (param->gr_imr_flm_inv == VDC5_OFF) {
+            *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_BIT4;
+        } else {
+            *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT4;
+        }
+    }
+
+    /* Frame buffer base address */
+    *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+    /* Frame buffer line offset address[byte] */
+    *(img_synthesizer->gr_flm3) &= (uint32_t)~VDC5_REG_MASK_0X7FFF03FF;
+    *(img_synthesizer->gr_flm3) |= param->gr_ln_off << VDC5_REG_SHIFT_16;
+
+    /* The number of lines when reading the addresses repeatedly */
+    *(img_synthesizer->gr_flm5) = (uint32_t)VDC5_REG_MASK_0X000007FF;
+    /* Number of lines in a frame */
+    *(img_synthesizer->gr_flm5) |= ((uint32_t)w_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+
+    *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0XF7FF1C3F;
+    /* Format of the frame buffer read signal */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_format << VDC5_REG_SHIFT_28;
+    /* Width of the horizontal valid period */
+    *(img_synthesizer->gr_flm6) |= ((uint32_t)w_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+    /* Swap setting in frame buffer reading */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_rdswa << VDC5_REG_SHIFT_10;
+
+    if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM)) {
+        /* Sets the amount of data to be skipped through */
+        *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, param->gr_format);
+    }
+
+    /* Graphics display mode */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+    if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+            (graphics_id == VDC5_GR_TYPE_OIR)) {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+    } else {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+    }
+
+    /* Graphics display area */
+    *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc.vs << VDC5_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc.vw;
+    *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc.hs << VDC5_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc.hw;
+
+    /* Initialize alpha blending in a rectangular area */
+    if ((graphics_id == VDC5_GR_TYPE_GR1) ||
+            (graphics_id == VDC5_GR_TYPE_GR2) ||
+            (graphics_id == VDC5_GR_TYPE_GR3)) {
+        /* Turns off alpha blending in a rectangular area */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X0000D000;
+        /* The valid image area for alpha blending in a rectangular area */
+        reg_data                   = *(img_synthesizer->gr_ab2);
+        *(img_synthesizer->gr_ab4) = reg_data;
+        reg_data                   = *(img_synthesizer->gr_ab3);
+        *(img_synthesizer->gr_ab5) = reg_data;
+        /* Disable fade-in and fade-out */
+        *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+        /* Set the initial alpha value to '255' */
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+    }
+    /* Turns off  chroma-key processing */
+    *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+        /* Alpha value is set to 255. */
+        *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+    }
+    if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+        /* Swapping of data read from buffer in the YCbCr422 format */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000E000;
+        if (param->gr_format == VDC5_GR_FORMAT_YCBCR422) {
+            *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_ycc_swap << VDC5_REG_SHIFT_13;
+            /* The interpolation mode for YCC422 to YCbCr444 conversion is fixed to average interpolation */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_REG_BIT8;
+        } else {
+            /* If the format of the frame buffer read signal is not YCbCr422,
+               initialize the swapping of data read from buffer in the YCbCr422 format. */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_GR_YCCSWAP_CBY0CRY1 << VDC5_REG_SHIFT_13;
+        }
+
+        SetupGraphicsVIN(ch, graphics_id, param->gr_flm_sel, graphics_enlargement);
+
+        color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+
+        SetScalerBackgroundColor(ch, graphics_id, color_space);
+        SetImgQaImproverColorMtx(ch, graphics_id, color_space);
+
+        if (graphics_id == VDC5_GR_TYPE_GR0) {
+            img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_0];
+        } else {
+            img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_1];
+        }
+        /* Operating mode */
+        if (color_space == VDC5_COLOR_SPACE_GBR) {
+            *(img_qlty_imp->adj_enh_tim1) &= (uint32_t)~VDC5_REG_BIT4;
+        } else {
+            *(img_qlty_imp->adj_enh_tim1) |= (uint32_t)VDC5_REG_BIT4;
+        }
+        /* Register update control register (ADJx_UPDATE)
+           b0       ADJx_VEN */
+        *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_RD);
+    if ((graphics_id == VDC5_GR_TYPE_GR0) && (rsrc_state == VDC5_RESOURCE_ST_INVALID)) {
+        /* Graphics 0 is specified when graphics 1 is not used. */
+        SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b8       GRx_UPDATE
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+}   /* End of function VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read change processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ChangeReadProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    vdc5_gr_flm_sel_t                       gr_flm_sel_tmp;
+    vdc5_period_rect_t                    * gr_grc_tmp;
+    vdc5_width_read_fb_t                  * w_read_fb;
+    vdc5_onoff_t                            graphics_enlargement;
+    vdc5_gr_format_t                        gr_format_tmp;
+
+    gr_flm_sel_tmp  = VDC5_ShrdPrmGetSelFbAddrSig(ch, graphics_id);
+    gr_grc_tmp      = VDC5_ShrdPrmGetDisplayArea(ch, graphics_id);
+    w_read_fb       = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, gr_flm_sel_tmp, w_read_fb, gr_grc_tmp);
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+            (graphics_id == VDC5_GR_TYPE_GR1) ||
+            (graphics_id == VDC5_GR_TYPE_OIR)) {
+        SetScalerGraphics(ch, graphics_id, w_read_fb, gr_grc_tmp, gr_flm_sel_tmp, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    /* Frame buffer base address */
+    if (param->gr_base != NULL) {
+        *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+        if ((gr_flm_sel_tmp == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel_tmp == VDC5_GR_FLM_SEL_FLM_NUM)) {
+            gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+            /* Sets the amount of data to be skipped through */
+            *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+            *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, gr_format_tmp);
+        }
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL) {
+        /* Number of lines in a frame */
+        *(img_synthesizer->gr_flm5) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm5) |= ((uint32_t)param->width_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+        /* Width of the horizontal valid period */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm6) |= ((uint32_t)param->width_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+    }
+
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL) {
+        if (*(param->gr_disp_sel) != VDC5_DISPSEL_IGNORED) {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*(param->gr_disp_sel);
+        }
+    }
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL) {
+        *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc->vs << VDC5_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc->vw;
+        *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc->hs << VDC5_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc->hw;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+        ChangeGraphicsVIN(ch, graphics_id, gr_flm_sel_tmp, graphics_enlargement);
+    }
+}   /* End of function VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read start processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_StartProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param)
+{
+    uint32_t                    layer_id_num;
+    vdc5_resource_state_t       resource_state;
+    vdc5_resource_state_t       oir_resrc_st_before;
+    vdc5_resource_state_t       oir_resrc_st_after;
+    const vdc5_regaddr_scaler_t * scaler;
+
+    if (param->gr_disp_sel != NULL) {
+        /* Set graphics display mode */
+        SetGraphicsDisplayMode(ch, layer_id, param->gr_disp_sel);
+    }
+
+    oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        rw_proc_function_tbl[layer_id](ch, VDC5_ON);
+    } else {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+            resource_state = VDC5_ShrdPrmGetRwProcReady(ch, (vdc5_layer_id_t)layer_id_num);
+            if (resource_state != VDC5_RESOURCE_ST_INVALID) {
+                rw_proc_function_tbl[layer_id_num](ch, VDC5_ON);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(ch, layer_id);
+
+    oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    /* OIR */
+    if ((oir_resrc_st_before == VDC5_RESOURCE_ST_INVALID) &&
+            (oir_resrc_st_after != VDC5_RESOURCE_ST_INVALID)) {
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+        *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT16;
+        /* Register update control register (OIR_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+    }
+}   /* End of function VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read stop processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+void VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    uint32_t                    layer_id_num;
+    vdc5_resource_state_t       resource_state;
+    vdc5_resource_state_t       oir_resrc_st_before;
+    vdc5_resource_state_t       oir_resrc_st_after;
+    const vdc5_regaddr_scaler_t * scaler;
+
+    oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        rw_proc_function_tbl[layer_id](ch, VDC5_OFF);
+    } else {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+            resource_state = VDC5_ShrdPrmGetRwProcEnabled(ch, (vdc5_layer_id_t)layer_id_num);
+            if (resource_state != VDC5_RESOURCE_ST_INVALID) {
+                rw_proc_function_tbl[layer_id_num](ch, VDC5_OFF);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(ch, layer_id);
+
+    oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    /* OIR */
+    if ((oir_resrc_st_before != VDC5_RESOURCE_ST_INVALID) &&
+            (oir_resrc_st_after == VDC5_RESOURCE_ST_INVALID)) {
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+        *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT16;
+        /* Register update control register (OIR_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+    }
+}   /* End of function VDC5_StopProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read control release processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+void VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    const vdc5_regaddr_scaler_t           * scaler;
+    vdc5_resource_state_t                   resource_state;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+
+    resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_1_RD);
+    if ((layer_id == VDC5_LAYER_ID_1_RD) ||
+            ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
+        SetInitialConnection(ch);
+
+        /* Use Vsync and enable signal output from scaler 0 */
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+        *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+        /* Register update control register (SC0_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+        *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+        /* Register update control register (SC1_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+
+        /* Initialize the color matrix in the image quality improver (scaler 1 output) */
+        SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
+    }
+
+    resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_0_RD);
+    if ((layer_id == VDC5_LAYER_ID_0_RD) ||
+            ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
+        img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+        /* Turns off alpha blending in a rectangular area */
+        *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+        /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
+        *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+        /* Graphics display mode in VIN */
+        *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+        /* Disable fade-in and fade-out */
+        *(img_synthesizer_vin->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+        /* Set the initial alpha value to '255' */
+        *(img_synthesizer_vin->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+
+        /* Graphics register update control register (GR_VIN_UPDATE)
+           b8       GR_VIN_UPDATE
+           b4       GR_VIN_P_VEN */
+        *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    }
+}   /* End of function VDC5_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for noise reduction
+ * @param[in]   ch                      : Channel
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_VideoNoiseReduction (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param)
+{
+    const vdc5_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc5_nr_param_t             * nr_param;
+
+    input_ctrl = &vdc5_regaddr_input_ctrl[ch];
+
+    if (param != NULL) {
+        /* Y/G signal noise reduction parameter */
+        nr_param = &param->y;
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_MASK_0X00007F33;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt0) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_gain;
+
+        /* Cb/B signal noise reduction parameter */
+        nr_param = &param->cb;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1)  = nr_param->nr1d_th << VDC5_REG_SHIFT_24;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_20;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain << VDC5_REG_SHIFT_16;
+
+        /* Cr/R signal noise reduction parameter */
+        nr_param = &param->cr;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain;
+    }
+
+    if (nr1d_on == VDC5_OFF) {
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT16;
+    } else {
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT16;
+    }
+
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for color matrix
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    SetColorMatrix(param->mtx_mode, param->offset, param->gain, &vdc5_regaddr_color_matrix[ch][param->module]);
+}   /* End of function VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for image enhancement processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageEnhancement (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
+
+    /* Sharpness */
+    SetImageEnhancementSharpness(shp_h_on, sharp_param, img_qlty_imp);
+
+    /* LTI */
+    SetImageEnhancementLti(lti_h_on, lti_param, img_qlty_imp);
+
+    /* Enhancer area */
+    if (enh_area != NULL) {
+        *(img_qlty_imp->adj_enh_tim2)  = (uint32_t)enh_area->vs << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim2) |= (uint32_t)enh_area->vw;
+        *(img_qlty_imp->adj_enh_tim3)  = (uint32_t)enh_area->hs << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim3) |= (uint32_t)enh_area->hw;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for black stretch
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageBlackStretch (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param)
+{
+    const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
+
+    if (param != NULL) {
+        /* Black stretch start point */
+        *(img_qlty_imp->adj_bkstr_set)  = (uint32_t)((uint32_t)param->bkstr_st << VDC5_REG_SHIFT_20);
+        /* Black stretch depth */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_d << VDC5_REG_SHIFT_16);
+        /* Black stretch time constant (T1) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_t1 << VDC5_REG_SHIFT_8);
+        /* Black stretch time constant (T2) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)param->bkstr_t2;
+    }
+
+    if (bkstr_on == VDC5_OFF) {
+        *(img_qlty_imp->adj_bkstr_set) &= (uint32_t)~VDC5_REG_BIT24;
+    } else {
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)VDC5_REG_BIT24;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for alpha blending
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_AlphaBlending (
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    /* Alpha signal of the ARGB1555/ARGB5551 format */
+    if (param->alpha_1bit != NULL) {
+        *(img_synthesizer->gr_ab10) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab10) |= (uint32_t)param->alpha_1bit->gr_a0 << VDC5_REG_SHIFT_24;
+        *(img_synthesizer->gr_ab11) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)param->alpha_1bit->gr_a1 << VDC5_REG_SHIFT_24;
+    }
+
+    /* Premultiplication processing at alpha blending in one-pixel */
+    if (param->alpha_pixel != NULL) {
+        if (param->alpha_pixel->gr_acalc_md == VDC5_OFF) {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT14;
+        } else {
+            *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT14;
+        }
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for rectangle alpha blending
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      None
+******************************************************************************/
+void VDC5_AlphaBlendingRect (
+    const vdc5_channel_t                        ch,
+    const vdc5_graphics_type_t                  graphics_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_alpha_rect_t               * alpha_rect_tmp;
+    uint32_t                                arc_coef;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    /* Alpha blending on/off control in a rectangular area */
+    if (gr_arc_on == VDC5_OFF) {
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+    } else {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT12;
+    }
+
+    if (param != NULL) {
+        /* Selection of lower-layer plane in scaler */
+        if (param->scl_und_sel != NULL) {
+            SetUndSel(ch, param->scl_und_sel->gr_vin_scl_und_sel);
+        }
+        /* Rectangular area subjected to alpha blending */
+        SetAlphaRectArea(param->gr_arc, img_synthesizer);
+
+        /* Alpha blending in a rectangular area */
+        alpha_rect_tmp = param->alpha_rect;
+        if (alpha_rect_tmp != NULL) {
+            if (graphics_id != VDC5_GR_TYPE_VIN) {
+                /* Multiplication processing with current alpha at alpha blending in a rectangular area (on/off) */
+                if (alpha_rect_tmp->gr_arc_mul == VDC5_OFF) {
+                    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT15;
+                } else {
+                    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT15;
+                }
+            }
+            /* Alpha coefficient for alpha blending in a rectangular area (-255 to 255) */
+            if (alpha_rect_tmp->gr_arc_coef < 0) {
+                arc_coef = (uint32_t)(alpha_rect_tmp->gr_arc_coef * (-1));  /* Conversion into absolute value */
+                /* Subtraction of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)VDC5_REG_BIT24;
+            } else {
+                arc_coef = (uint32_t)alpha_rect_tmp->gr_arc_coef;
+                /* Addition of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)0x00000000u;
+            }
+            *(img_synthesizer->gr_ab6) |= arc_coef << VDC5_REG_SHIFT_16;
+            /* Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+            *(img_synthesizer->gr_ab6) |= (uint32_t)alpha_rect_tmp->gr_arc_rate;
+            /* Initial alpha value for alpha blending in a rectangular area */
+            *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_MASK_0X00FF0000;
+            *(img_synthesizer->gr_ab7) |= (uint32_t)alpha_rect_tmp->gr_arc_def << VDC5_REG_SHIFT_16;
+        }
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma-key
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_Chromakey (
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_gr_format_t                        gr_format_tmp;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    if (param != NULL) {
+        gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+        if ((gr_format_tmp == VDC5_GR_FORMAT_CLUT1) ||
+                (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) ||
+                (gr_format_tmp == VDC5_GR_FORMAT_CLUT8)) {
+            *(img_synthesizer->gr_ab8)  = (uint32_t)(param->ck_color << VDC5_REG_SHIFT_24);
+            *(img_synthesizer->gr_ab9)  = ColorConversionIntoAgbr(param->rep_color & VDC5_REG_RGB_24BIT_MASK);
+        } else {
+            /* Color conversion from gr_format_tmp into RGB888 format */
+            *(img_synthesizer->gr_ab8)  = ColorConversion(gr_format_tmp, param->ck_color);
+            *(img_synthesizer->gr_ab9)  = ColorConversion(gr_format_tmp, param->rep_color);
+        }
+        if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+            /* Alpha value is set to 255. */
+            *(img_synthesizer->gr_ab9) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+        } else {
+            *(img_synthesizer->gr_ab9) |= (uint32_t)param->rep_alpha << VDC5_REG_SHIFT_24;
+        }
+    }
+
+    if (gr_ck_on == VDC5_OFF) {
+        *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+    } else {
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for CLUT
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_CLUT (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param)
+{
+    vdc5_gr_format_t                        gr_format_tmp;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+    if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1) {
+        if (param->color_num == ((uint32_t)1u)) {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+                /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+            }
+        } else {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            *(img_synthesizer->gr_ab11) = ColorConversionIntoAgbr(param->clut[1]);
+            if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+                /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+                *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+            }
+        }
+    } else {    /* CLUT4 or CLUT8 */
+        Set_Clut(param, vdc5_regaddr_clut[ch][graphics_id]);
+
+        /* CLUT table control register (GRx_CLUT)
+           b16      GRx_CLT_SEL - CLUT table select signal - XOR, flip signal */
+        *(img_synthesizer->gr_clut) ^= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_CLUT() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display calibration
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    const vdc5_calibr_bright_t        * bright_tmp;
+    const vdc5_calibr_contrast_t      * contrast_tmp;
+    const vdc5_calibr_dither_t        * panel_dither_tmp;
+    const vdc5_regaddr_output_ctrl_t  * output_ctrl;
+
+    output_ctrl = &vdc5_regaddr_output_ctrl[ch];
+
+    /* Correction circuit sequence control */
+    if (param->route == VDC5_CALIBR_ROUTE_BCG) {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT12;
+    } else {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT12;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL) {
+        *(output_ctrl->out_bright1)  = (uint32_t)bright_tmp->pbrt_g;
+        *(output_ctrl->out_bright2)  = (uint32_t)bright_tmp->pbrt_b << VDC5_REG_SHIFT_16;
+        *(output_ctrl->out_bright2) |= (uint32_t)bright_tmp->pbrt_r;
+    }
+
+    /* Contrast (gain) adjustment */
+    contrast_tmp = param->contrast;
+    if (contrast_tmp != NULL) {
+        *(output_ctrl->out_contrast)  = (uint32_t)contrast_tmp->cont_g << VDC5_REG_SHIFT_16;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_b << VDC5_REG_SHIFT_8;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_r;
+    }
+
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL) {
+        *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00300000;
+        *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_sel << VDC5_REG_SHIFT_20;
+        if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2) {
+            *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00003333;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pa << VDC5_REG_SHIFT_12;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pb << VDC5_REG_SHIFT_8;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pc << VDC5_REG_SHIFT_4;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pd;
+        }
+    }
+
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for gamma correction
+ * @param[in]   ch          : Channel
+ * @param[in]   gam_on      : Gamma correction ON/OFF setting
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_GammaCorrection (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param)
+{
+    const vdc5_regaddr_gamma_t  * gamma;
+
+    gamma = &vdc5_regaddr_gamma[ch];
+
+    /* Gamma correction on/off control */
+    *(gamma->gam_sw) = (gam_on == VDC5_OFF) ? 0x0000u : 0x0001u;
+
+    if (param != NULL) {
+        /* Start threshold of area 1 to 31 of G signal */
+        Set_StartThreshold_Gamma(param->gam_g_th, gamma->gam_g_area);
+        /* Gain adjustment of area 0 to 31 of G signal */
+        Set_GainAdjustment_Gamma(param->gam_g_gain, gamma->gam_g_lut);
+        /* Register update control register G (GAM_G_UPDATE)
+           b0       GAM_G_VEN */
+        *(gamma->gam_g_update) |= (uint32_t)VDC5_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of B signal */
+        Set_StartThreshold_Gamma(param->gam_b_th, gamma->gam_b_area);
+        /* Gain adjustment of area 0 to 31 of B signal */
+        Set_GainAdjustment_Gamma(param->gam_b_gain, gamma->gam_b_lut);
+        /* Register update control register B (GAM_B_UPDATE)
+           b0       GAM_B_VEN */
+        *(gamma->gam_b_update) |= (uint32_t)VDC5_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of R signal */
+        Set_StartThreshold_Gamma(param->gam_r_th, gamma->gam_r_area);
+        /* Gain adjustment of area 0 to 31 of R signal */
+        Set_GainAdjustment_Gamma(param->gam_r_gain, gamma->gam_r_lut);
+        /* Register update control register R (GAM_R_UPDATE)
+           b0       GAM_R_VEN */
+        *(gamma->gam_r_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+}   /* End of function VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Sets external input video signal
+ * @param[in]   ext_sig_tmp             : External input signal parameter
+ * @param[in]   input_ctrl              : Input controller registers
+ * @retval      None
+******************************************************************************/
+static void SetVideoExternalInput (
+    const vdc5_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc5_regaddr_input_ctrl_t * const input_ctrl)
+{
+    *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_MASK_0X00007111;
+    /* External input format select */
+    if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR444) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_EXTIN_FORMAT_RGB888 << VDC5_REG_SHIFT_12;
+    } else {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)ext_sig_tmp->inp_format << VDC5_REG_SHIFT_12;
+    }
+    /* Clock edge select for capturing external input video image signals */
+    if (ext_sig_tmp->inp_pxd_edge != VDC5_EDGE_RISING) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Clock edge select for capturing external input Vsync signals */
+    if (ext_sig_tmp->inp_vs_edge != VDC5_EDGE_RISING) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Clock edge select for capturing external input Hsync signals */
+    if (ext_sig_tmp->inp_hs_edge != VDC5_EDGE_RISING) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    *(input_ctrl->inp_ext_sync_cnt) &= (uint32_t)~VDC5_REG_MASK_0X11110113;
+    /* External input bit endian change on/off control */
+    if (ext_sig_tmp->inp_endian_on != VDC5_OFF) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT28;
+    }
+    /* External input B/R signal swap on/off control */
+    if (ext_sig_tmp->inp_swap_on != VDC5_OFF) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT24;
+    }
+    /* External input Vsync signal DV_VSYNC inversion control */
+    if (ext_sig_tmp->inp_vs_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT20;
+    }
+    /* External input Hsync signal DV_HSYNC inversion control */
+    if (ext_sig_tmp->inp_hs_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Reference select for external input BT.656 Hsync signal */
+    if (ext_sig_tmp->inp_h_edge_sel != VDC5_EXTIN_REF_H_EAV) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Number of lines for BT.656 external input */
+    if (ext_sig_tmp->inp_f525_625 != VDC5_EXTIN_LINE_525) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)ext_sig_tmp->inp_h_pos;
+}   /* End of function SetVideoExternalInput() */
+
+/**************************************************************************//**
+ * @brief       Initializes cascaded connection
+ * @param[in]   ch                      : Channel
+ * @retval      None
+******************************************************************************/
+static void SetInitialConnection (const vdc5_channel_t ch)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+
+    /* Cascade ON */
+    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
+    /* Graphics register update control register (GR1_UPDATE)
+       b8       GR1_UPDATE */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
+
+    VDC5_ShrdPrmSetCascade(ch, VDC5_ON);
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+    /* Turns off alpha blending in a rectangular area */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+    /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
+    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+    /* Graphics display mode in VIN */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+    /* Disable fade-in and fade-out */
+    *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+    /* Set the initial alpha value to '255' */
+    *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+    /* Graphics register update control register (GR_VIN_UPDATE)
+       b8       GR_VIN_UPDATE
+       b4       GR_VIN_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+}   /* End of function SetInitialConnection() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for graphics
+ * @param[in]   ch                  : Channel
+ * @retval      None
+******************************************************************************/
+static void SetGrapicsBackgroundColor (const vdc5_channel_t ch)
+{
+    uint32_t                bg_color_tmp;
+    uint32_t                bg_color_conv;
+    volatile uint32_t     * bg_color_reg;
+    volatile uint32_t     * update_reg;
+    vdc5_graphics_type_t    gr_type_index;
+
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp = VDC5_ShrdPrmGetBgColor(ch, VDC5_COLOR_SPACE_GBR);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+    /* GR2, GR3, VIN, OIR */
+    for (gr_type_index = VDC5_GR_TYPE_GR2; gr_type_index < VDC5_GR_TYPE_NUM; gr_type_index++) {
+        /* Background color in GBR format (GRx_BASE) */
+        bg_color_reg    = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_base;
+        *bg_color_reg   = bg_color_conv;
+        /* Graphics register update control register (GRx_UPDATE)
+           b4       GRx_P_VEN */
+        update_reg      = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_update;
+        *update_reg    |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* For OIR */
+    /* Background color in RGB format (OIR_SCL0_OVR1) */
+    bg_color_reg    = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_ovr1;
+    *bg_color_reg   = bg_color_tmp;
+    /* Register update control register (OIR_SCL0_UPDATE)
+       b4       SCL0_VEN_B */
+    update_reg      = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_update;
+    *update_reg    |= (uint32_t)VDC5_REG_BIT4;
+}   /* End of function SetGrapicsBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for scaler 0, scaler 1, graphics 0, and graphics 1
+ *
+ *              Description:<br>
+ *              This function should be called only when graphics 0 or graphics 1 is selected.
+ * @param[in]   ch                  : Channel
+ * @param[in]   graphics_id         : Graphics type ID
+ * @param[in]   color_space         : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetScalerBackgroundColor (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space)
+{
+    volatile uint32_t * scl0_update_reg;
+    volatile uint32_t * scl0_ovr1_reg;
+    volatile uint32_t * gr_base_reg;
+    volatile uint32_t * gr_update_reg;
+    uint32_t            bg_color_tmp;
+    uint32_t            bg_color_conv;
+
+    if (graphics_id == VDC5_GR_TYPE_GR0) {
+        scl0_ovr1_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_ovr1;
+        scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
+        gr_base_reg     = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_base;
+        gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+    } else {
+        /* graphics_id == VDC5_GR_TYPE_GR1 */
+        scl0_ovr1_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_ovr1;
+        scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
+        gr_base_reg     = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_base;
+        gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+    }
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp    = VDC5_ShrdPrmGetBgColor(ch, color_space);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+    /* Background color in RGB format or CrYCb format */
+    *scl0_ovr1_reg      = bg_color_tmp;
+    /* Register update control register
+       b4       SCL0_VEN_B */
+    *scl0_update_reg   |= (uint32_t)VDC5_REG_BIT4;
+
+    /* Background color in GBR format or YCbCr format */
+    *gr_base_reg        = bg_color_conv;
+    /* Graphics register update control register
+       b4       GRx_P_VEN */
+    *gr_update_reg     |= (uint32_t)VDC5_REG_BIT4;
+}   /* End of function SetScalerBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVA/VS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVA_VS (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stva1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stva1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_stva2) &= (uint32_t)~VDC5_REG_BIT4;
+    } else {
+        *(output_ctrl->tcon_tim_stva2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVA_VS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVB/VE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVB_VE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stvb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stvb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_stvb2) &= (uint32_t)~VDC5_REG_BIT4;
+    } else {
+        *(output_ctrl->tcon_tim_stvb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVB_VE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STH/HS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STH_HS (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_sth1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_sth1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_sth2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STH_HS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STB/HE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STB_HE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_stb2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STB_HE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - CPV/GCK
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_CPV_GCK (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_cpv1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_cpv1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_cpv2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_CPV_GCK() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLA
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLA (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_pola1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_pola1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_pola2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_pola2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLA() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLB
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLB (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_polb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_polb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_polb2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_polb2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLB() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - DE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_DE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Polarity inversion control of signal */
+    *(output_ctrl->tcon_tim_de) = (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) ? (uint32_t)0u : (uint32_t)1u;
+
+}   /* End of function SetLcdTcon_DE() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-down
+ * @param[in]   scldw_rot               : Scaling-down and rotation parameter
+ * @param[in]   res_inter               : Field operating mode select
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingDown (
+    const vdc5_scalingdown_rot_t    * const scldw_rot,
+    const vdc5_res_inter_t                  res_inter,
+    const vdc5_regaddr_scaler_t     * const scaler)
+{
+    uint32_t    vw_before_scld;    /* Vertical width before scaling-down */
+    uint32_t    hw_before_scld;    /* Horizontal width before scaling-down */
+    uint32_t    vw_after_scld;     /* Vertical width after scaling-down */
+    uint32_t    hw_after_scld;     /* Horizontal width after scaling-down */
+    uint32_t    scaling_ratio;
+
+    vw_before_scld = (uint32_t)scldw_rot->res.vw;
+    hw_before_scld = (uint32_t)scldw_rot->res.hw;
+
+    vw_after_scld = (uint32_t)scldw_rot->res_out_vw;
+    hw_after_scld = (uint32_t)scldw_rot->res_out_hw;
+
+    /* Vertical scaling-down: ON, vertical scaling-up: OFF */
+    *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT4;
+    *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+    if (vw_before_scld > vw_after_scld) {
+        scaling_ratio = CalcScalingRatio(vw_before_scld, vw_after_scld, scldw_rot->adj_sel, VDC5_OFF);
+
+        *(scaler->scl0_ds6) = scaling_ratio;
+    } else {
+        *(scaler->scl0_ds6) = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    }
+
+    /* Horizontal scaling-down */
+    if (hw_before_scld > hw_after_scld) {
+        /* ON */
+        *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(hw_before_scld, hw_after_scld, VDC5_ON, VDC5_ON);
+
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_ds4) |= scaling_ratio;
+    } else {
+        /* OFF */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    if (res_inter != VDC5_RES_INTER_PROGRESSIVE) {
+        /* Top */
+        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+    }
+
+}   /* End of function SetScalingDown() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-up
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   adj_sel                 : Folding handling (on/off)
+ * @param[in]   ip_conversion           : IP conversion on/off
+ * @param[in]   res_ds_wr_md            : Frame buffer writing mode for image processing
+ * @param[in]   ln_off_dir              : Line offset address direction of the frame buffer
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingUp (
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_onoff_t                  adj_sel,
+    const vdc5_onoff_t                  ip_conversion,
+    const vdc5_wr_md_t                  res_ds_wr_md,
+    const vdc5_gr_ln_off_dir_t          ln_off_dir,
+    const vdc5_regaddr_scaler_t * const scaler)
+{
+    uint32_t            w_before_scl;       /* Width before scaling-up */
+    uint32_t            w_after_scl;        /* Width after scaling-up */
+    uint32_t            scaling_ratio;
+    vdc5_onoff_t        vscl_up;            /* Vertical scaling-up */
+
+    vscl_up = VDC5_OFF;
+
+    /* Vertical scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_vw;
+    w_after_scl     = (uint32_t)gr_grc->vw;
+    if (w_before_scl < w_after_scl) {
+        /* Vertical scaling-down: OFF, vertical scaling-up: ON */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT4;
+        *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT4;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+        *(scaler->scl0_ds6) = scaling_ratio;
+
+        vscl_up = VDC5_ON;
+    } else {
+        /* Vertical scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+    }
+
+    /* Horizontal scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_hw;
+    w_after_scl     = (uint32_t)gr_grc->hw;
+    if (w_before_scl < w_after_scl) {
+        /* Horizontal scaling-up: ON */
+        *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+
+        *(scaler->scl0_us5) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_us5) |= scaling_ratio;
+    } else {
+        /* Horizontal scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    if (ip_conversion == VDC5_OFF) {
+        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    } else {
+        if (vscl_up != VDC5_OFF) {
+            switch (res_ds_wr_md) {
+                case VDC5_WR_MD_ROT_90DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    /* US_HB */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE;
+                    break;
+                case VDC5_WR_MD_ROT_180DEG:
+                    if (ln_off_dir == VDC5_GR_LN_OFF_DIR_INC) {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                    break;
+                case VDC5_WR_MD_ROT_270DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    /* US_HT */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+                    break;
+                default:    /* Normal or horizontal mirroring */
+                    if (ln_off_dir == VDC5_GR_LN_OFF_DIR_DEC) {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                    break;
+            }
+        }
+    }
+}   /* End of function SetScalingUp() */
+
+/**************************************************************************//**
+ * @brief       Calculates scaling ratio
+ *
+ *              Description:<br>
+ *              In this function, the overflow in calculation is not considered.
+ *              before_scl and after_scl are 11bit width, so the overflow does not occur.
+ * @param[in]   before_scl              : Size before scaling
+ * @param[in]   after_scl               : Size after scaling
+ * @param[in]   adj_sel                 : Handling for lack of last-input pixel/line, or folding handling
+ * @param[in]   round_up                : Round-up on/off
+ * @retval      Scaling ratio
+******************************************************************************/
+static uint32_t CalcScalingRatio (
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc5_onoff_t  adj_sel,
+    const vdc5_onoff_t  round_up)
+{
+    float32_t   ratio;
+    float32_t   sigma;
+    int32_t     ratio_int;
+    uint32_t    scaling_ratio;
+
+    /* When parameter checking is not performed,
+       following checks are necessary to avoid a division by zero exception and a negative number. */
+    if ((after_scl == 0u) || (after_scl == 1u)) {
+        scaling_ratio = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    } else {
+        /* ratio = before_scl * 4096.0 / after_scl */
+        ratio  = (float32_t)before_scl * (float32_t)SCALING_RATIO_SAME_SIZE;
+        ratio /= (float32_t)after_scl;
+
+        if (adj_sel != VDC5_OFF) {
+            sigma  = ratio * ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+            sigma -= ((float32_t)before_scl - (float32_t)VDC5_REG_FLOAT_1_0) * (float32_t)SCALING_RATIO_SAME_SIZE;
+            sigma /= ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+            ratio -= sigma;
+        }
+
+        if (round_up == VDC5_OFF) {
+            /* Round off */
+            ratio    += (float32_t)VDC5_REG_FLOAT_0_5;
+            ratio_int = (int32_t)ratio;
+        } else {
+            /* Round up */
+            ratio_int = (int32_t)ratio;
+            if ((float32_t)ratio_int < ratio) {
+                ratio_int++;
+            }
+        }
+        scaling_ratio = (uint32_t)ratio_int;
+    }
+    return scaling_ratio;
+}   /* End of function CalcScalingRatio() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the input controller
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      None
+******************************************************************************/
+static void SetInputCntrlColorMtx (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    vdc5_channel_t          channel;
+    vdc5_color_space_t      color_space_input;
+    vdc5_color_space_t      color_space_fb;
+    vdc5_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    if (scaling_id == VDC5_SC_TYPE_SC0) {
+        channel = ch;
+    } else {
+        channel = (ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0;
+    }
+    color_space_input   = VDC5_ShrdPrmGetColorSpace(channel);
+    color_space_fb      = VDC5_ShrdPrmGetColorSpaceFbWr(ch, scaling_id);
+    /* Color matrix operating mode */
+    if (color_space_input == VDC5_COLOR_SPACE_GBR) {
+        if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
+            /* GBR to GBR */
+            mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+        } else {
+            /* GBR to YCbCr */
+            mtx_mode_tmp = VDC5_COLORMTX_GBR_YCBCR;
+        }
+    } else {
+        if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
+            /* YCbCr to GBR */
+            mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+        } else {
+            /* YCbCr to YCbCr */
+            mtx_mode_tmp = VDC5_COLORMTX_YCBCR_YCBCR;
+        }
+    }
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[channel][VDC5_COLORMTX_IMGCNT]);
+
+}   /* End of function SetInputCntrlColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Confirms whether the graphics enlargement will occur or not
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @retval      Graphics enlargement on/off
+******************************************************************************/
+static vdc5_onoff_t ConfirmGraphicsEnlargement (
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc)
+{
+    vdc5_onoff_t graphics_enlargement;
+
+    graphics_enlargement = VDC5_OFF;
+    if (gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) {
+        if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+            if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) ||
+                    ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
+                graphics_enlargement = VDC5_ON;
+            }
+        }
+    } else {
+        if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) || ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
+            graphics_enlargement = VDC5_ON;
+        }
+    }
+    return graphics_enlargement;
+}   /* End of function ConfirmGraphicsEnlargement() */
+
+/**************************************************************************//**
+ * @brief       Sets scaler for graphics
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void SetScalerGraphics (
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_onoff_t                  gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_scaler_t           * scaler;
+    vdc5_scaling_type_t                     scaling_id;
+    vdc5_res_inter_t                        res_inter_tmp;
+    vdc5_wr_md_t                            res_ds_wr_md_tmp;
+    vdc5_onoff_t                            adj_sel_tmp;
+    vdc5_onoff_t                            ip_conversion;
+    uint32_t                                reg_data;
+    vdc5_gr_ln_off_dir_t                    ln_off_dir;
+
+    if (graphics_id == VDC5_GR_TYPE_GR0) {
+        /* Scaler 0 */
+        scaling_id = VDC5_SC_TYPE_SC0;
+    } else if (graphics_id == VDC5_GR_TYPE_GR1) {
+        /* Scaler 1 */
+        scaling_id = VDC5_SC_TYPE_SC1;
+    } else {
+        /* OIR */
+        scaling_id = VDC5_SC_TYPE_OIR;
+    }
+
+    scaler = &vdc5_regaddr_scaler[ch][scaling_id];
+
+    if ((gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) && (gr_enlarge == VDC5_OFF)) {
+        /* Normal graphics display */
+        /* Sync signals from the graphics processing block */
+        *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
+
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b4       SCL0_VEN_B */
+        *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT4);
+    } else {
+        /* Video image or graphics enlargement */
+        if (graphics_id == VDC5_GR_TYPE_OIR) {
+            /* Turn the vertical scaling-up and the horizontal scaling-up off */
+            *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
+            /* Sync signals from the graphics processing block */
+            *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
+        } else {
+            /* Sync signals from the scaling-up control block */
+            *(scaler->scl0_us8) &= (uint32_t)~VDC5_REG_BIT4;
+
+            /* Graphics display area */
+            *(scaler->scl0_us2)  = (uint32_t)gr_grc->vs << VDC5_REG_SHIFT_16;
+            *(scaler->scl0_us2) |= (uint32_t)gr_grc->vw;
+            *(scaler->scl0_us3)  = (uint32_t)gr_grc->hs << VDC5_REG_SHIFT_16;
+            *(scaler->scl0_us3) |= (uint32_t)gr_grc->hw;
+
+            *(scaler->scl0_us4)  = (uint32_t)w_read_fb->in_vw << VDC5_REG_SHIFT_16;
+            *(scaler->scl0_us4) |= (uint32_t)w_read_fb->in_hw;
+
+            res_ds_wr_md_tmp    = VDC5_ShrdPrmGetWritingMode(ch, scaling_id);
+            adj_sel_tmp         = VDC5_ShrdPrmGetMeasureFolding(ch, graphics_id);
+            ip_conversion       = VDC5_OFF;
+            if ((gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF)) {
+                res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
+                if (res_inter_tmp != VDC5_RES_INTER_PROGRESSIVE) {
+                    ip_conversion = VDC5_ON;
+                }
+            }
+
+            ln_off_dir = VDC5_ShrdPrmGetLineOfsAddrDir(ch, graphics_id);
+            /* Scaling-up */
+            SetScalingUp(w_read_fb, gr_grc, adj_sel_tmp, ip_conversion, res_ds_wr_md_tmp, ln_off_dir, scaler);
+        }
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b8       SCL0_UPDATE
+           b4       SCL0_VEN_B
+           b0       SCL0_VEN_A */
+        *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+    }
+
+    if (gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) {
+        img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+        /* Frame buffer frame offset address */
+        reg_data                    = *(scaler->scl1_wr4);
+        *(img_synthesizer->gr_flm4) = reg_data;
+
+        /* Graphics register update control register (GRx_UPDATE)
+           b0       GRx_IBUS_VEN */
+        *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+}   /* End of function SetScalerGraphics() */
+
+/**************************************************************************//**
+ * @brief       Gets the amount of data to be skipped through
+ * @param[in]   gr_base                 : Frame buffer base address
+ * @param[in]   gr_format               : Graphics format
+ * @retval      The amount of data to be skipped through
+******************************************************************************/
+static uint32_t DisplayStartPixelSetting (const uint32_t gr_base, const vdc5_gr_format_t gr_format)
+{
+    uint32_t                gr_sta_pos;
+    static const uint32_t   bits_per_pixel[VDC5_GR_FORMAT_NUM] = {
+        VDC5_REG_BIT_PER_PIXEL_RGB565,         /* RGB565 */
+        VDC5_REG_BIT_PER_PIXEL_RGB888,         /* RGB888 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB1555,       /* ARGB1555 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB4444,       /* ARGB4444 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB8888,       /* ARGB8888 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT8,          /* CLUT8 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT4,          /* CLUT4 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT1,          /* CLUT1 */
+        VDC5_REG_BIT_PER_PIXEL_YCBCR422,       /* YCbCr422: In the YCbCr422 format, 32 bits are used for two pixels. */
+        VDC5_REG_BIT_PER_PIXEL_YCBCR444,       /* YCbCr444 */
+        VDC5_REG_BIT_PER_PIXEL_RGBA5551,       /* RGBA5551 */
+        VDC5_REG_BIT_PER_PIXEL_RGBA8888        /* RGBA8888 */
+    };
+
+    gr_sta_pos  = gr_base & (uint32_t)VDC5_REG_MASK_0X00000007;
+    gr_sta_pos *= (uint32_t)VDC5_REG_BIT_PER_PIXEL_VALUE_8;
+    gr_sta_pos /= bits_per_pixel[gr_format];
+    gr_sta_pos &= (uint32_t)VDC5_REG_MASK_0X0000003F;
+
+    return gr_sta_pos;
+}   /* End of function DisplayStartPixelSetting() */
+
+/**************************************************************************//**
+ * @brief       Sets cascaded connection
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      Cascade ON/OFF
+******************************************************************************/
+static vdc5_onoff_t SetCascade (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_scaler_t           * scaler_0;
+    const vdc5_regaddr_scaler_t           * scaler_1;
+    vdc5_res_vs_in_sel_t                    res_vs_in_sel_tmp;
+    vdc5_onoff_t                            cascade;
+
+    cascade = VDC5_ShrdPrmGetCascade(ch);
+    /* Cascade */
+    if (graphics_id == VDC5_GR_TYPE_GR1) {
+        img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+        scaler_0        = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+        scaler_1        = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+
+        if ((gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) || (gr_enlarge != VDC5_OFF)) {
+            /* Video image or graphics enlargement */
+            /* Cascade OFF */
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT28;
+
+            cascade = VDC5_OFF;
+            /* Get sync signal output and full-screen enable signal select */
+            res_vs_in_sel_tmp = VDC5_ShrdPrmGetVsInSel(ch);
+            if (res_vs_in_sel_tmp == VDC5_RES_VS_IN_SEL_SC0) {
+                /* Use Vsync and enable signal output from scaler 0 */
+                *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+                *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+            } else {
+                /* Use Vsync and enable signal output from scaler 1 */
+                *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+                *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+            }
+        } else {
+            /* Cascade ON */
+            *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
+
+            cascade = VDC5_ON;
+            /* Use Vsync and enable signal output from scaler 0 */
+            *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+        }
+        VDC5_ShrdPrmSetCascade(ch, cascade);
+
+        /* Register update control register (SC0_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler_0->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+        /* Register update control register (SC1_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler_1->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+        /* Graphics register update control register (GR1_UPDATE)
+           b8       GR1_UPDATE */
+        *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    return cascade;
+}   /* End of function SetCascade() */
+
+/**************************************************************************//**
+ * @brief       Sets VIN synthesizer
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void SetupGraphicsVIN (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+    vdc5_onoff_t                            cascade;
+    vdc5_resource_state_t                   rsrc_state;
+    vdc5_onoff_t                            und_sel;
+    uint32_t                                reg_data;
+
+    /* Cascade */
+    cascade     = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
+
+    /* Display area for VIN */
+    rsrc_state  = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+    if ((cascade == VDC5_OFF) &&
+            ((rsrc_state != VDC5_RESOURCE_ST_INVALID) || (graphics_id == VDC5_GR_TYPE_GR0))) {
+        /* Cascade connection OFF and graphics 0 is used */
+        img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+        und_sel = VDC5_ShrdPrmGetUndSel(ch);
+        if (und_sel == VDC5_OFF) {
+            /* Graphics 1 is allocated to the upper-layer. */
+            *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+            img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+        } else {
+            /* Graphics 0 is allocated to the upper-layer. */
+            *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+            img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+        }
+        /* Graphics display mode in VIN */
+        *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
+        /* Copy the graphics display area in the upper-layer to the VIN display area. */
+        reg_data                        = *(img_synthesizer->gr_ab2);
+        *(img_synthesizer_vin->gr_ab2)  = reg_data;
+        reg_data                        = *(img_synthesizer->gr_ab3);
+        *(img_synthesizer_vin->gr_ab3)  = reg_data;
+        /* The valid image area for alpha blending in a rectangular area */
+        reg_data                        = *(img_synthesizer_vin->gr_ab2);
+        *(img_synthesizer_vin->gr_ab4)  = reg_data;
+        reg_data                        = *(img_synthesizer_vin->gr_ab3);
+        *(img_synthesizer_vin->gr_ab5)  = reg_data;
+
+        /* Graphics register update control register (GR_VIN_UPDATE)
+           b8       GR_VIN_UPDATE
+           b4       GR_VIN_P_VEN */
+        *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    }
+}   /* End of function SetupGraphicsVIN() */
+
+/**************************************************************************//**
+ * @brief       Changes VIN synthesizer settings
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void ChangeGraphicsVIN (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+    vdc5_onoff_t                            cascade;
+    vdc5_onoff_t                            cascade_prev;
+    vdc5_resource_state_t                   rsrc_state;
+    vdc5_onoff_t                            und_sel;
+    uint32_t                                reg_data;
+
+    /* Cascade */
+    cascade_prev    = VDC5_ShrdPrmGetCascade(ch);
+    cascade         = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
+
+    /* Display area for VIN */
+    rsrc_state  = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+        /* Graphics 0 is used */
+        img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+        if (cascade == VDC5_OFF) {
+            /* Cascade connection is OFF */
+            und_sel = VDC5_ShrdPrmGetUndSel(ch);
+            if (und_sel == VDC5_OFF) {
+                /* Graphics 1 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+            } else {
+                /* Graphics 0 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+            }
+            /* Graphics display mode in VIN */
+            *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
+            /* Copy the graphics display area in the upper-layer to the VIN display area. */
+            reg_data                        = *(img_synthesizer->gr_ab2);
+            *(img_synthesizer_vin->gr_ab2)  = reg_data;
+            reg_data                        = *(img_synthesizer->gr_ab3);
+            *(img_synthesizer_vin->gr_ab3)  = reg_data;
+        } else {
+            /* Cascade connection is ON */
+            if (cascade_prev == VDC5_OFF) {
+                /* Cascade connection was turned on in this function. */
+                /* Selection of lower-layer plane in scaler is set to 1. */
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+                /* Graphics display mode in VIN */
+                *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+            }
+        }
+        /* Graphics register update control register (GR_VIN_UPDATE)
+           b8       GR_VIN_UPDATE
+           b4       GR_VIN_P_VEN */
+        *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    }
+}   /* End of function ChangeGraphicsVIN() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the image quality improver
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   color_space             : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetImgQaImproverColorMtx (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space)
+{
+    vdc5_colormtx_module_t  module_tmp;
+    vdc5_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    /* Color matrix operating mode */
+    if (color_space == VDC5_COLOR_SPACE_GBR) {
+        mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+    } else {
+        mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+    }
+    /* Color matrix module */
+    module_tmp = (graphics_id == VDC5_GR_TYPE_GR0) ? VDC5_COLORMTX_ADJ_0 : VDC5_COLORMTX_ADJ_1;
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[ch][module_tmp]);
+
+}   /* End of function SetImgQaImproverColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for scaler 0
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    volatile uint32_t               dummy_read;
+    uint32_t                        reg_data;
+
+    /* SC0/GR0 writing */
+    scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+
+    if (ability == VDC5_OFF) {
+        /* SC0 frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_WR);
+    } else {
+        /* SC0 frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+        /* Reset and reset cancellation of the pointer buffer with dummy read */
+        *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+        *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+#if(1) /* mbed */
+        (void)dummy_read; /* unused */
+#endif
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for scaler 1
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    volatile uint32_t               dummy_read;
+    uint32_t                        reg_data;
+
+    /* SC1/GR1 writing */
+    scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+
+    if (ability == VDC5_OFF) {
+        /* SC1 frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_WR);
+    } else {
+        /* SC1 frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+        /* Reset and reset cancellation of the pointer buffer with dummy read */
+        *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+        *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+#if(1) /* mbed */
+        (void)dummy_read; /* unused */
+#endif
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_1() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for OIR
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_scaler_t * scaler;
+
+    /* OIR writing */
+    scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+
+    if (ability == VDC5_OFF) {
+        /* OIR frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_WR);
+    } else {
+        /* OIR frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_OIR() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 0
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* SC0/GR0 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+
+    if (ability == VDC5_OFF) {
+        /* GR0 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_RD);
+    } else {
+        /* GR0 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 1
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* SC1/GR1 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+
+    if (ability == VDC5_OFF) {
+        /* GR1 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_RD);
+    } else {
+        /* GR1 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_1() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 2
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_2 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR2 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2];
+
+    if (ability == VDC5_OFF) {
+        /* GR2 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_2_RD);
+    } else {
+        /* GR2 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_2_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_2() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 3
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_3 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR3 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3];
+
+    if (ability == VDC5_OFF) {
+        /* GR3 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_3_RD);
+    } else {
+        /* GR3 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_3_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_3() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for OIR
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* OIR reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR];
+
+    if (ability == VDC5_OFF) {
+        /* OIR frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_RD);
+    } else {
+        /* OIR frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_OIR() */
+
+/**************************************************************************//**
+ * @brief       Sets register update control register to update the frame buffer
+ *              read and write enable settings.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+static void SetRegUpdateRwEnable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    volatile uint32_t * scl1_update_reg;
+    volatile uint32_t * gr_update_reg;
+
+    switch (layer_id) {
+        case VDC5_LAYER_ID_0_WR:        /* Layer 0, write process */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_1_WR:        /* Layer 1, write process */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_OIR_WR:      /* Layer OIR, write process */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_0_RD:        /* Layer 0, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_1_RD:        /* Layer 1, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_2_RD:        /* Layer 2, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_3_RD:        /* Layer 3, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_OIR_RD:      /* Layer OIR, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+
+        case VDC5_LAYER_ID_ALL:         /* All */
+            /* Register update control register (SCx_SCL1_UPDATE)
+               b20      SCL1_UPDATE_B
+               b4       SCL1_VEN_B
+               b0       SCL1_VEN_A */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            /* Register update control register (OIR_SCL1_UPDATE)
+               b4       SCL1_VEN_B
+               b0       SCL1_VEN_A */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN
+               b0       GRx_IBUS_VEN */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+
+        default:
+            /* DO NOTHING */
+            break;
+    }
+}   /* End of function SetRegUpdateRwEnable() */
+
+/**************************************************************************//**
+ * @brief       Sets graphics display mode
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   gr_disp_sel             : Graphics display mode
+ * @retval      None
+******************************************************************************/
+static void SetGraphicsDisplayMode (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_gr_disp_sel_t    * const gr_disp_sel)
+{
+    uint32_t                                graphics_id;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    if (layer_id == VDC5_LAYER_ID_ALL) {
+        for (graphics_id = 0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++) {
+            if ((graphics_id != VDC5_GR_TYPE_VIN) && (gr_disp_sel[graphics_id] != VDC5_DISPSEL_IGNORED)) {
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+                *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+                *(img_synthesizer->gr_ab1) |= (uint32_t)gr_disp_sel[graphics_id];
+                /* Graphics register update control register (GRx_UPDATE)
+                   b4       GRx_P_VEN */
+                *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+            }
+        }
+    } else if ((layer_id >= VDC5_LAYER_ID_0_RD) && (layer_id <= VDC5_LAYER_ID_OIR_RD)) {
+        if (*gr_disp_sel != VDC5_DISPSEL_IGNORED) {
+            graphics_id = (uint32_t)(layer_id - VDC5_SC_TYPE_NUM);
+
+            img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*gr_disp_sel;
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN */
+            *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+        }
+    } else {
+        /* Do nothing */
+    }
+}   /* End of function SetGraphicsDisplayMode() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix
+ * @param[in]   mtx_mode                : Operating mode
+ * @param[in]   offset                  : Offset (DC) adjustment of Y/G, B, and R signal
+ * @param[in]   gain                    : GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment
+ * @param[in]   color_matrix            : Color matrix registers
+ * @retval      None
+******************************************************************************/
+static void SetColorMatrix (
+    const vdc5_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc5_regaddr_color_matrix_t   * const color_matrix)
+{
+    /* Operating mode */
+    *(color_matrix->mtx_mode) = (uint32_t)mtx_mode;
+
+    /* Offset (DC) adjustment of Y/G, B, and R signal and
+       GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    *(color_matrix->mtx_yg_adj0)    = (uint32_t)offset[VDC5_COLORMTX_OFFST_YG] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj0)   |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GG];
+    *(color_matrix->mtx_yg_adj1)    = (uint32_t)gain[VDC5_COLORMTX_GAIN_GB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj1)   |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GR];
+    *(color_matrix->mtx_cbb_adj0)   = (uint32_t)offset[VDC5_COLORMTX_OFFST_B] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj0)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BG];
+    *(color_matrix->mtx_cbb_adj1)   = (uint32_t)gain[VDC5_COLORMTX_GAIN_BB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj1)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BR];
+    *(color_matrix->mtx_crr_adj0)   = (uint32_t)offset[VDC5_COLORMTX_OFFST_R] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj0)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RG];
+    *(color_matrix->mtx_crr_adj1)   = (uint32_t)gain[VDC5_COLORMTX_GAIN_RB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj1)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RR];
+
+    /* Register update control register (IMGCNT_UPDATE/ADJx_UPDATE)
+       b0       IMGCNT_VEN/ADJx_VEN */
+    *(color_matrix->mtx_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function SetColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets sharpness
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness ON/OFF setting
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementSharpness (
+    const vdc5_onoff_t                          shp_h_on,
+    const vdc5_enhance_sharp_t          * const sharp_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc5_sharpness_ctrl_t * sharpness_ctrl;
+
+    if (sharp_param != NULL) {
+        /* H1, adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp2)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H2, second adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (sharp_param->shp_h2_lpf_sel == VDC5_OFF) {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)0x00000000u;
+        } else {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)VDC5_REG_BIT16;
+        }
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp3) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp4)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H3, third adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp5) = (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp6)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+    }
+
+    if (shp_h_on == VDC5_OFF) {
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_BIT16;
+    } else {
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)VDC5_REG_BIT16;
+    }
+}   /* End of function SetImageEnhancementSharpness() */
+
+/**************************************************************************//**
+ * @brief       Sets LTI
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementLti (
+    const vdc5_onoff_t                          lti_h_on,
+    const vdc5_enhance_lti_t            * const lti_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc5_lti_ctrl_t * lti_ctrl;
+
+    if (lti_param != NULL) {
+        /* H2, second adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI1];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (lti_param->lti_h2_lpf_sel == VDC5_OFF) {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)0x00000000u;
+        } else {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)VDC5_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)lti_ctrl->lti_core;
+
+        /* H4, fourth adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI2];
+        /* Median filter reference pixel select */
+        if (lti_param->lti_h4_median_tap_sel == VDC5_LTI_MDFIL_SEL_ADJ2) {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)0x00000000u;
+        } else {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)VDC5_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)lti_ctrl->lti_core;
+    }
+
+    if (lti_h_on == VDC5_OFF) {
+        *(img_qlty_imp->adj_enh_lti1) &= (uint32_t)~VDC5_REG_BIT31;
+    } else {
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)VDC5_REG_BIT31;
+    }
+}   /* End of function SetImageEnhancementLti() */
+
+/**************************************************************************//**
+ * @brief       Sets alpha blending area of a rectangle
+ * @param[in]   pd_disp_rect        : Rectangular area for alpha blending
+ * @param[in]   img_synthesizer     : Image synthesizer registers
+ * @retval      None
+******************************************************************************/
+static void SetAlphaRectArea (
+    const vdc5_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc5_regaddr_img_synthesizer_t    * const img_synthesizer)
+{
+    uint32_t v_start;
+    uint32_t h_start;
+
+    if (pd_disp_rect != NULL) {
+        v_start = *(img_synthesizer->gr_ab2) >> VDC5_REG_SHIFT_16;
+        h_start = *(img_synthesizer->gr_ab3) >> VDC5_REG_SHIFT_16;
+
+        v_start += (uint32_t)pd_disp_rect->vs_rel;
+        h_start += (uint32_t)pd_disp_rect->hs_rel;
+        /* If the start position exceeds the maximum bit width, the value should be saturated. */
+        if ((v_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
+            v_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+        }
+        if ((h_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
+            h_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+        }
+
+        *(img_synthesizer->gr_ab4) = (v_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->vw_rel;
+        *(img_synthesizer->gr_ab5) = (h_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->hw_rel;
+    }
+}   /* End of function SetAlphaRectArea() */
+
+/**************************************************************************//**
+ * @brief       Sets upper-layer and lower-layer plane in scaler
+ * @param[in]   ch                      : Channel
+ * @param[in]   und_sel                 : Selection of lower-layer plane in scaler
+ * @retval      None
+ *****************************************************************************/
+static void SetUndSel (const vdc5_channel_t ch, const vdc5_onoff_t und_sel)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+    vdc5_onoff_t                            current_und_sel;
+    vdc5_onoff_t                            cascade;
+    vdc5_resource_state_t                   rsrc_state;
+    uint32_t                                reg_data;
+
+    current_und_sel = VDC5_ShrdPrmGetUndSel(ch);
+    if (und_sel != current_und_sel) {
+        VDC5_ShrdPrmSetUndSel(ch, und_sel);
+
+        cascade     = VDC5_ShrdPrmGetCascade(ch);
+        rsrc_state  = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+        if ((cascade == VDC5_OFF) && (rsrc_state != VDC5_RESOURCE_ST_INVALID)) {
+            /* Cascade connection OFF and graphics 0 is used */
+            img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+            if (und_sel == VDC5_OFF) {
+                /* Graphics 1 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+            } else {
+                /* Graphics 0 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+            }
+            /* Copy the graphics display area in the upper-layer to the VIN display area. */
+            reg_data                        = *(img_synthesizer->gr_ab2);
+            *(img_synthesizer_vin->gr_ab2)  = reg_data;
+            reg_data                        = *(img_synthesizer->gr_ab3);
+            *(img_synthesizer_vin->gr_ab3)  = reg_data;
+
+            /* Graphics register update control register (GR_VIN_UPDATE)
+               b8       GR_VIN_UPDATE
+               b4       GR_VIN_P_VEN */
+            *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+        }
+    }
+}   /* End of function SetUndSel() */
+
+/**************************************************************************//**
+ * @brief       Converts the color format from gr_format format into 24-bit RGB888 format
+ * @param[in]   gr_format           : Color format
+ * @param[in]   input_color         : Color data
+ * @retval      RGB888 color data
+******************************************************************************/
+static uint32_t ColorConversion (const vdc5_gr_format_t gr_format, const uint32_t input_color)
+{
+    uint32_t red;
+    uint32_t green;
+    uint32_t blue;
+    uint32_t conv_color;
+
+    conv_color = 0;
+    switch (gr_format) {
+        case VDC5_GR_FORMAT_RGB565:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGB565_R_MASK) >> VDC5_REG_SHIFT_11));
+            green = ColorConversionFrom6to8((uint32_t)((input_color & VDC5_REG_RGB565_G_MASK) >> VDC5_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_RGB565_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_RGB888:
+            conv_color = ColorConversionIntoAgbr(input_color);
+            break;
+        case VDC5_GR_FORMAT_ARGB1555:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_R_MASK) >> VDC5_REG_SHIFT_10));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_G_MASK) >> VDC5_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_ARGB1555_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_ARGB4444:
+            red   = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_R_MASK) >> VDC5_REG_SHIFT_8));
+            green = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_G_MASK) >> VDC5_REG_SHIFT_4));
+            blue  = ColorConversionFrom4to8((uint32_t)(input_color & VDC5_REG_ARGB4444_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_ARGB8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)(input_color & VDC5_REG_RGB_24BIT_MASK));
+            break;
+        case VDC5_GR_FORMAT_RGBA5551:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_R_MASK) >> VDC5_REG_SHIFT_11));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_G_MASK) >> VDC5_REG_SHIFT_6));
+            blue  = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_B_MASK) >> VDC5_REG_SHIFT_1));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_RGBA8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)((input_color >> VDC5_REG_SHIFT_8) & VDC5_REG_RGB_24BIT_MASK));
+            break;
+        default:
+            /* DO NOTHING */
+            break;
+    }
+    return conv_color;
+}   /* End of function ColorConversion() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 4 bits value into 8 bits value
+ * @param[in]   color_value         : 4-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom4to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_4BIT_MASK;
+    color *= (uint32_t)VDC5_REG_EXTENSION_VALUE_17;
+
+    return color;
+}   /* End of function ColorConversionFrom4to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 5 bits value into 8 bits value
+ * @param[in]   color_value         : 5-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom5to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_5BIT_MASK;
+    color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_263 * VDC5_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_32;
+    /* Round off */
+    color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom5to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 6 bits value into 8 bits value
+ * @param[in]   color_value         : 6-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom6to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_6BIT_MASK;
+    color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_259 * VDC5_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_64;
+    /* Round off */
+    color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom6to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from ARGB8888 format into AGBR8888 format
+ * @param[in]   color_value         : ARGB8888 color data
+ * @retval      AGBR8888 color data
+******************************************************************************/
+static uint32_t ColorConversionIntoAgbr (const uint32_t color_value)
+{
+    uint32_t color_bgr;
+    uint32_t color_dat;
+
+    /* Green and blue */
+    color_bgr   = (uint32_t)(color_value << VDC5_REG_SHIFT_8);
+    color_bgr  &= (uint32_t)VDC5_REG_ARGB8888_GB_MASK;
+    /* Alpha */
+    color_dat   = (uint32_t)(color_value & VDC5_REG_ALPHA_8BIT);
+    color_bgr  |= color_dat;
+    /* Red */
+    color_dat   = (uint32_t)((color_value >> VDC5_REG_SHIFT_16) & VDC5_REG_COLOR_8BIT_MASK);
+    color_bgr  |= color_dat;
+
+    return color_bgr;
+}   /* End of function ColorConversionIntoAgbr() */
+
+/**************************************************************************//**
+ * @brief       Sets color lookup table (CLUT)
+ * @param[in]   param               : CLUT parameter
+ * @param[out]  regaddr_clut        : CLUT register top address
+ * @retval      None
+******************************************************************************/
+static void Set_Clut (const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut)
+{
+    uint32_t            data_len;
+    const uint32_t    * clut_tmp;
+
+    clut_tmp = param->clut;
+    for (data_len = 0; data_len < param->color_num; data_len++) {
+        *regaddr_clut = *clut_tmp;
+        regaddr_clut++;
+        clut_tmp++;
+    }
+}   /* End of function Set_Clut() */
+
+/**************************************************************************//**
+ * @brief       Sets start threshold for gamma correction
+ * @param[in]   gam_th          : Start threshold of area 1 to 31
+ * @param[out]  gam_area        : Gamma correction registers for start threshold
+ * @retval      None
+******************************************************************************/
+static void Set_StartThreshold_Gamma (const uint8_t * gam_th, volatile uint32_t * const * const gam_area)
+{
+    uint32_t reg_index;
+
+    if (gam_th != NULL) {
+        *(gam_area[0])  = (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th;
+        gam_th++;
+
+        for (reg_index = 1; reg_index < VDC5_GAM_AREA_REG_NUM; reg_index++) {
+            *(gam_area[reg_index])  = (uint32_t)*gam_th << VDC5_REG_SHIFT_24;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th;
+            gam_th++;
+        }
+    }
+}   /* End of function Set_StartThreshold_Gamma() */
+
+/**************************************************************************//**
+ * @brief       Sets gain adjustment for gamma correction
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31
+ * @param[out]  gam_lut         : Gamma correction registers for gain adjustment
+ * @retval      None
+******************************************************************************/
+static void Set_GainAdjustment_Gamma (const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut)
+{
+    uint32_t reg_index;
+
+    if (gam_gain != NULL) {
+        for (reg_index = 0; reg_index < VDC5_GAM_LUT_REG_NUM; reg_index++) {
+            *(gam_lut[reg_index])  = (uint32_t)*gam_gain << VDC5_REG_SHIFT_16;
+            gam_gain++;
+            *(gam_lut[reg_index]) |= (uint32_t)*gam_gain;
+            gam_gain++;
+        }
+    }
+}   /* End of function Set_GainAdjustment_Gamma() */
+
+/**************************************************************************//**
+ * @brief       Waits for 200 usec
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void Wait_200_usec (void)
+{
+    volatile uint32_t   counter;
+
+    for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_200USEC; counter++) {
+        /* Wait for 200 usec. */
+    }
+}   /* End of function Wait_200_usec() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_register.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,318 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDC5_REGISTER_H
+#define R_VDC5_REGISTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_GAM_LUT_REG_NUM    (16u)   /*!< The number of table setting register in gamma correction block */
+#define     VDC5_GAM_AREA_REG_NUM   (8u)    /*!< The number of area setting register in gamma correction block */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDC5 input controller register address list */
+typedef struct {
+    volatile uint32_t * inp_update;
+    volatile uint32_t * inp_sel_cnt;
+    volatile uint32_t * inp_ext_sync_cnt;
+    volatile uint32_t * inp_vsync_ph_adj;
+    volatile uint32_t * inp_dly_adj;
+    volatile uint32_t * imgcnt_update;
+    volatile uint32_t * imgcnt_nr_cnt0;
+    volatile uint32_t * imgcnt_nr_cnt1;
+} vdc5_regaddr_input_ctrl_t;
+
+/*! VDC5 scaler register address list */
+typedef struct {
+    volatile uint32_t * scl0_update;
+    volatile uint32_t * scl0_frc1;
+    volatile uint32_t * scl0_frc2;
+    volatile uint32_t * scl0_frc3;
+    volatile uint32_t * scl0_frc4;
+    volatile uint32_t * scl0_frc5;
+    volatile uint32_t * scl0_frc6;
+    volatile uint32_t * scl0_frc7;
+    volatile uint32_t * scl0_frc9;
+    volatile uint16_t * scl0_mon0;
+    volatile uint16_t * scl0_int;
+    volatile uint32_t * scl0_ds1;
+    volatile uint32_t * scl0_ds2;
+    volatile uint32_t * scl0_ds3;
+    volatile uint32_t * scl0_ds4;
+    volatile uint32_t * scl0_ds5;
+    volatile uint32_t * scl0_ds6;
+    volatile uint32_t * scl0_ds7;
+    volatile uint32_t * scl0_us1;
+    volatile uint32_t * scl0_us2;
+    volatile uint32_t * scl0_us3;
+    volatile uint32_t * scl0_us4;
+    volatile uint32_t * scl0_us5;
+    volatile uint32_t * scl0_us6;
+    volatile uint32_t * scl0_us7;
+    volatile uint32_t * scl0_us8;
+    volatile uint32_t * scl0_ovr1;
+    volatile uint32_t * scl1_update;
+    volatile uint32_t * scl1_wr1;
+    volatile uint32_t * scl1_wr2;
+    volatile uint32_t * scl1_wr3;
+    volatile uint32_t * scl1_wr4;
+    volatile uint32_t * scl1_wr5;
+    volatile uint32_t * scl1_wr6;
+    volatile uint32_t * scl1_wr7;
+    volatile uint32_t * scl1_wr8;
+    volatile uint32_t * scl1_wr9;
+    volatile uint32_t * scl1_wr10;
+    volatile uint32_t * scl1_wr11;
+    volatile uint32_t * scl1_mon1;
+    volatile uint32_t * scl1_pbuf0;
+    volatile uint32_t * scl1_pbuf1;
+    volatile uint32_t * scl1_pbuf2;
+    volatile uint32_t * scl1_pbuf3;
+    volatile uint32_t * scl1_pbuf_fld;
+    volatile uint32_t * scl1_pbuf_cnt;
+} vdc5_regaddr_scaler_t;
+
+/*! VDC5 image quality improver register address list */
+typedef struct {
+    volatile uint32_t * adj_update;
+    volatile uint32_t * adj_bkstr_set;
+    volatile uint32_t * adj_enh_tim1;
+    volatile uint32_t * adj_enh_tim2;
+    volatile uint32_t * adj_enh_tim3;
+    volatile uint32_t * adj_enh_shp1;
+    volatile uint32_t * adj_enh_shp2;
+    volatile uint32_t * adj_enh_shp3;
+    volatile uint32_t * adj_enh_shp4;
+    volatile uint32_t * adj_enh_shp5;
+    volatile uint32_t * adj_enh_shp6;
+    volatile uint32_t * adj_enh_lti1;
+    volatile uint32_t * adj_enh_lti2;
+} vdc5_regaddr_img_qlty_imp_t;
+
+/*! VDC5 color matrix register address list */
+typedef struct {
+    volatile uint32_t * mtx_update;
+    volatile uint32_t * mtx_mode;
+    volatile uint32_t * mtx_yg_adj0;
+    volatile uint32_t * mtx_yg_adj1;
+    volatile uint32_t * mtx_cbb_adj0;
+    volatile uint32_t * mtx_cbb_adj1;
+    volatile uint32_t * mtx_crr_adj0;
+    volatile uint32_t * mtx_crr_adj1;
+} vdc5_regaddr_color_matrix_t;
+
+/*! VDC5 image synthesizer register address list */
+typedef struct {
+    volatile uint32_t * gr_update;
+    volatile uint32_t * gr_flm_rd;
+    volatile uint32_t * gr_flm1;
+    volatile uint32_t * gr_flm2;
+    volatile uint32_t * gr_flm3;
+    volatile uint32_t * gr_flm4;
+    volatile uint32_t * gr_flm5;
+    volatile uint32_t * gr_flm6;
+    volatile uint32_t * gr_ab1;
+    volatile uint32_t * gr_ab2;
+    volatile uint32_t * gr_ab3;
+    volatile uint32_t * gr_ab4;
+    volatile uint32_t * gr_ab5;
+    volatile uint32_t * gr_ab6;
+    volatile uint32_t * gr_ab7;
+    volatile uint32_t * gr_ab8;
+    volatile uint32_t * gr_ab9;
+    volatile uint32_t * gr_ab10;
+    volatile uint32_t * gr_ab11;
+    volatile uint32_t * gr_base;
+    volatile uint32_t * gr_clut;
+    volatile uint32_t * gr_mon;
+} vdc5_regaddr_img_synthesizer_t;
+
+/*! VDC5 gamma correction register address list */
+typedef struct {
+    volatile uint32_t * gam_sw;
+    volatile uint32_t * gam_g_update;
+    volatile uint32_t * gam_g_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_g_area[VDC5_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_b_update;
+    volatile uint32_t * gam_b_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_b_area[VDC5_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_r_update;
+    volatile uint32_t * gam_r_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_r_area[VDC5_GAM_AREA_REG_NUM];
+} vdc5_regaddr_gamma_t;
+
+/*! VDC5 output controller register address list */
+typedef struct {
+    volatile uint32_t * tcon_update;
+    volatile uint32_t * tcon_tim;
+    volatile uint32_t * tcon_tim_stva1;
+    volatile uint32_t * tcon_tim_stva2;
+    volatile uint32_t * tcon_tim_stvb1;
+    volatile uint32_t * tcon_tim_stvb2;
+    volatile uint32_t * tcon_tim_sth1;
+    volatile uint32_t * tcon_tim_sth2;
+    volatile uint32_t * tcon_tim_stb1;
+    volatile uint32_t * tcon_tim_stb2;
+    volatile uint32_t * tcon_tim_cpv1;
+    volatile uint32_t * tcon_tim_cpv2;
+    volatile uint32_t * tcon_tim_pola1;
+    volatile uint32_t * tcon_tim_pola2;
+    volatile uint32_t * tcon_tim_polb1;
+    volatile uint32_t * tcon_tim_polb2;
+    volatile uint32_t * tcon_tim_de;
+    volatile uint32_t * out_update;
+    volatile uint32_t * out_set;
+    volatile uint32_t * out_bright1;
+    volatile uint32_t * out_bright2;
+    volatile uint32_t * out_contrast;
+    volatile uint32_t * out_pdtha;
+    volatile uint32_t * out_clk_phase;
+} vdc5_regaddr_output_ctrl_t;
+
+/*! VDC5 system controller register address list */
+typedef struct {
+    volatile uint32_t * syscnt_int1;
+    volatile uint32_t * syscnt_int2;
+    volatile uint32_t * syscnt_int3;
+    volatile uint32_t * syscnt_int4;
+    volatile uint32_t * syscnt_int5;
+    volatile uint32_t * syscnt_int6;
+    volatile uint16_t * syscnt_panel_clk;
+    volatile uint16_t * syscnt_clut;
+} vdc5_regaddr_system_ctrl_t;
+
+/*! LVDS register address list */
+typedef struct {
+    volatile uint32_t * lvds_update;
+    volatile uint32_t * lvdsfcl;
+    volatile uint32_t * lclkselr;
+    volatile uint32_t * lpllsetr;
+    volatile uint32_t * lphyacc;
+} vdc5_regaddr_lvds_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdc5_regaddr_input_ctrl_t      vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_scaler_t          vdc5_regaddr_scaler[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM];
+extern const vdc5_regaddr_img_qlty_imp_t    vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM][VDC5_IMG_IMPRV_NUM];
+extern const vdc5_regaddr_color_matrix_t    vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM][VDC5_COLORMTX_NUM];
+extern const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+extern uint32_t                     * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+extern const vdc5_regaddr_output_ctrl_t     vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_gamma_t           vdc5_regaddr_gamma[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_system_ctrl_t     vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_lvds_t            vdc5_regaddr_lvds;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_Initialize(const vdc5_channel_t ch, const vdc5_init_t * const param);
+void VDC5_Terminate(const vdc5_channel_t ch);
+void VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
+void VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+void VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
+void VDC5_WriteDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param);
+void VDC5_ChangeWriteProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param);
+void VDC5_ReadDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param);
+void VDC5_ChangeReadProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param);
+void VDC5_StartProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param);
+void VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_VideoNoiseReduction(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param);
+void VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+void VDC5_ImageEnhancement(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area);
+void VDC5_ImageBlackStretch(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param);
+void VDC5_AlphaBlending(
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_alpha_blending_t * const param);
+void VDC5_AlphaBlendingRect(
+    const vdc5_channel_t                        ch,
+    const vdc5_graphics_type_t                  graphics_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param);
+void VDC5_Chromakey(
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param);
+void VDC5_CLUT(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param);
+void VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+void VDC5_GammaCorrection(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param);
+
+void VDC5_Int_Disable(const vdc5_channel_t ch);
+void VDC5_Int_SetInterrupt(const vdc5_channel_t ch, const vdc5_int_t * const param);
+
+
+#endif  /* R_VDC5_REGISTER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_register_address.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1105 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register_address.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_CH0_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF6000u)
+#define     VDC5_CH0_GR1_CLUT_TBL           (*(uint32_t*)0xFCFF6400u)
+#define     VDC5_CH0_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF6800u)
+#define     VDC5_CH0_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF6C00u)
+#define     VDC5_CH0_GR_OIR_CLUT_TBL        (*(uint32_t*)0xFCFF7000u)
+#define     VDC5_CH1_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF8000u)
+#define     VDC5_CH1_GR1_CLUT_TBL           (*(uint32_t*)0xFCFF8400u)
+#define     VDC5_CH1_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF8800u)
+#define     VDC5_CH1_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF8C00u)
+#define     VDC5_CH1_GR_OIR_CLUT_TBL        (*(uint32_t*)0xFCFF9000u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDC5 input controller register address list */
+const vdc5_regaddr_input_ctrl_t vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.INP_UPDATE,
+        &VDC50.INP_SEL_CNT,
+        &VDC50.INP_EXT_SYNC_CNT,
+        &VDC50.INP_VSYNC_PH_ADJ,
+        &VDC50.INP_DLY_ADJ,
+        &VDC50.IMGCNT_UPDATE,
+        &VDC50.IMGCNT_NR_CNT0,
+        &VDC50.IMGCNT_NR_CNT1
+    },
+    {   /* Channel 1 */
+        &VDC51.INP_UPDATE,
+        &VDC51.INP_SEL_CNT,
+        &VDC51.INP_EXT_SYNC_CNT,
+        &VDC51.INP_VSYNC_PH_ADJ,
+        &VDC51.INP_DLY_ADJ,
+        &VDC51.IMGCNT_UPDATE,
+        &VDC51.IMGCNT_NR_CNT0,
+        &VDC51.IMGCNT_NR_CNT1
+    }
+};
+
+/* VDC5 scaler register address list */
+const vdc5_regaddr_scaler_t vdc5_regaddr_scaler[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM] = {
+    {   /* Channel 0 */
+        {   /* SC0 */
+            &VDC50.SC0_SCL0_UPDATE,
+            &VDC50.SC0_SCL0_FRC1,
+            &VDC50.SC0_SCL0_FRC2,
+            &VDC50.SC0_SCL0_FRC3,
+            &VDC50.SC0_SCL0_FRC4,
+            &VDC50.SC0_SCL0_FRC5,
+            &VDC50.SC0_SCL0_FRC6,
+            &VDC50.SC0_SCL0_FRC7,
+            &VDC50.SC0_SCL0_FRC9,
+            &VDC50.SC0_SCL0_MON0,
+            &VDC50.SC0_SCL0_INT,
+            &VDC50.SC0_SCL0_DS1,
+            &VDC50.SC0_SCL0_DS2,
+            &VDC50.SC0_SCL0_DS3,
+            &VDC50.SC0_SCL0_DS4,
+            &VDC50.SC0_SCL0_DS5,
+            &VDC50.SC0_SCL0_DS6,
+            &VDC50.SC0_SCL0_DS7,
+            &VDC50.SC0_SCL0_US1,
+            &VDC50.SC0_SCL0_US2,
+            &VDC50.SC0_SCL0_US3,
+            &VDC50.SC0_SCL0_US4,
+            &VDC50.SC0_SCL0_US5,
+            &VDC50.SC0_SCL0_US6,
+            &VDC50.SC0_SCL0_US7,
+            &VDC50.SC0_SCL0_US8,
+            &VDC50.SC0_SCL0_OVR1,
+            &VDC50.SC0_SCL1_UPDATE,
+            &VDC50.SC0_SCL1_WR1,
+            &VDC50.SC0_SCL1_WR2,
+            &VDC50.SC0_SCL1_WR3,
+            &VDC50.SC0_SCL1_WR4,
+            &VDC50.SC0_SCL1_WR5,
+            &VDC50.SC0_SCL1_WR6,
+            &VDC50.SC0_SCL1_WR7,
+            &VDC50.SC0_SCL1_WR8,
+            &VDC50.SC0_SCL1_WR9,
+            &VDC50.SC0_SCL1_WR10,
+            &VDC50.SC0_SCL1_WR11,
+            &VDC50.SC0_SCL1_MON1,
+            &VDC50.SC0_SCL1_PBUF0,
+            &VDC50.SC0_SCL1_PBUF1,
+            &VDC50.SC0_SCL1_PBUF2,
+            &VDC50.SC0_SCL1_PBUF3,
+            &VDC50.SC0_SCL1_PBUF_FLD,
+            &VDC50.SC0_SCL1_PBUF_CNT
+        },
+        {   /* SC1 */
+            &VDC50.SC1_SCL0_UPDATE,
+            &VDC50.SC1_SCL0_FRC1,
+            &VDC50.SC1_SCL0_FRC2,
+            &VDC50.SC1_SCL0_FRC3,
+            &VDC50.SC1_SCL0_FRC4,
+            &VDC50.SC1_SCL0_FRC5,
+            &VDC50.SC1_SCL0_FRC6,
+            &VDC50.SC1_SCL0_FRC7,
+            &VDC50.SC1_SCL0_FRC9,
+            &VDC50.SC1_SCL0_MON0,
+            &VDC50.SC1_SCL0_INT,
+            &VDC50.SC1_SCL0_DS1,
+            &VDC50.SC1_SCL0_DS2,
+            &VDC50.SC1_SCL0_DS3,
+            &VDC50.SC1_SCL0_DS4,
+            &VDC50.SC1_SCL0_DS5,
+            &VDC50.SC1_SCL0_DS6,
+            &VDC50.SC1_SCL0_DS7,
+            &VDC50.SC1_SCL0_US1,
+            &VDC50.SC1_SCL0_US2,
+            &VDC50.SC1_SCL0_US3,
+            &VDC50.SC1_SCL0_US4,
+            &VDC50.SC1_SCL0_US5,
+            &VDC50.SC1_SCL0_US6,
+            &VDC50.SC1_SCL0_US7,
+            &VDC50.SC1_SCL0_US8,
+            &VDC50.SC1_SCL0_OVR1,
+            &VDC50.SC1_SCL1_UPDATE,
+            &VDC50.SC1_SCL1_WR1,
+            &VDC50.SC1_SCL1_WR2,
+            &VDC50.SC1_SCL1_WR3,
+            &VDC50.SC1_SCL1_WR4,
+            &VDC50.SC1_SCL1_WR5,
+            &VDC50.SC1_SCL1_WR6,
+            &VDC50.SC1_SCL1_WR7,
+            &VDC50.SC1_SCL1_WR8,
+            &VDC50.SC1_SCL1_WR9,
+            &VDC50.SC1_SCL1_WR10,
+            &VDC50.SC1_SCL1_WR11,
+            &VDC50.SC1_SCL1_MON1,
+            &VDC50.SC1_SCL1_PBUF0,
+            &VDC50.SC1_SCL1_PBUF1,
+            &VDC50.SC1_SCL1_PBUF2,
+            &VDC50.SC1_SCL1_PBUF3,
+            &VDC50.SC1_SCL1_PBUF_FLD,
+            &VDC50.SC1_SCL1_PBUF_CNT
+        },
+        {   /* OIR */
+            &VDC50.OIR_SCL0_UPDATE,
+            &VDC50.OIR_SCL0_FRC1,
+            &VDC50.OIR_SCL0_FRC2,
+            &VDC50.OIR_SCL0_FRC3,
+            &VDC50.OIR_SCL0_FRC4,
+            &VDC50.OIR_SCL0_FRC5,
+            &VDC50.OIR_SCL0_FRC6,
+            &VDC50.OIR_SCL0_FRC7,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.OIR_SCL0_DS1,
+            &VDC50.OIR_SCL0_DS2,
+            &VDC50.OIR_SCL0_DS3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.OIR_SCL0_DS7,
+            &VDC50.OIR_SCL0_US1,
+            &VDC50.OIR_SCL0_US2,
+            &VDC50.OIR_SCL0_US3,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.OIR_SCL0_US8,
+            &VDC50.OIR_SCL0_OVR1,
+            &VDC50.OIR_SCL1_UPDATE,
+            &VDC50.OIR_SCL1_WR1,
+            &VDC50.OIR_SCL1_WR2,
+            &VDC50.OIR_SCL1_WR3,
+            &VDC50.OIR_SCL1_WR4,
+            &VDC50.OIR_SCL1_WR5,
+            &VDC50.OIR_SCL1_WR6,
+            &VDC50.OIR_SCL1_WR7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL
+        }
+    },
+    {   /* Channel 1 */
+        {   /* SC0 */
+            &VDC51.SC0_SCL0_UPDATE,
+            &VDC51.SC0_SCL0_FRC1,
+            &VDC51.SC0_SCL0_FRC2,
+            &VDC51.SC0_SCL0_FRC3,
+            &VDC51.SC0_SCL0_FRC4,
+            &VDC51.SC0_SCL0_FRC5,
+            &VDC51.SC0_SCL0_FRC6,
+            &VDC51.SC0_SCL0_FRC7,
+            &VDC51.SC0_SCL0_FRC9,
+            &VDC51.SC0_SCL0_MON0,
+            &VDC51.SC0_SCL0_INT,
+            &VDC51.SC0_SCL0_DS1,
+            &VDC51.SC0_SCL0_DS2,
+            &VDC51.SC0_SCL0_DS3,
+            &VDC51.SC0_SCL0_DS4,
+            &VDC51.SC0_SCL0_DS5,
+            &VDC51.SC0_SCL0_DS6,
+            &VDC51.SC0_SCL0_DS7,
+            &VDC51.SC0_SCL0_US1,
+            &VDC51.SC0_SCL0_US2,
+            &VDC51.SC0_SCL0_US3,
+            &VDC51.SC0_SCL0_US4,
+            &VDC51.SC0_SCL0_US5,
+            &VDC51.SC0_SCL0_US6,
+            &VDC51.SC0_SCL0_US7,
+            &VDC51.SC0_SCL0_US8,
+            &VDC51.SC0_SCL0_OVR1,
+            &VDC51.SC0_SCL1_UPDATE,
+            &VDC51.SC0_SCL1_WR1,
+            &VDC51.SC0_SCL1_WR2,
+            &VDC51.SC0_SCL1_WR3,
+            &VDC51.SC0_SCL1_WR4,
+            &VDC51.SC0_SCL1_WR5,
+            &VDC51.SC0_SCL1_WR6,
+            &VDC51.SC0_SCL1_WR7,
+            &VDC51.SC0_SCL1_WR8,
+            &VDC51.SC0_SCL1_WR9,
+            &VDC51.SC0_SCL1_WR10,
+            &VDC51.SC0_SCL1_WR11,
+            &VDC51.SC0_SCL1_MON1,
+            &VDC51.SC0_SCL1_PBUF0,
+            &VDC51.SC0_SCL1_PBUF1,
+            &VDC51.SC0_SCL1_PBUF2,
+            &VDC51.SC0_SCL1_PBUF3,
+            &VDC51.SC0_SCL1_PBUF_FLD,
+            &VDC51.SC0_SCL1_PBUF_CNT
+        },
+        {   /* SC1 */
+            &VDC51.SC1_SCL0_UPDATE,
+            &VDC51.SC1_SCL0_FRC1,
+            &VDC51.SC1_SCL0_FRC2,
+            &VDC51.SC1_SCL0_FRC3,
+            &VDC51.SC1_SCL0_FRC4,
+            &VDC51.SC1_SCL0_FRC5,
+            &VDC51.SC1_SCL0_FRC6,
+            &VDC51.SC1_SCL0_FRC7,
+            &VDC51.SC1_SCL0_FRC9,
+            &VDC51.SC1_SCL0_MON0,
+            &VDC51.SC1_SCL0_INT,
+            &VDC51.SC1_SCL0_DS1,
+            &VDC51.SC1_SCL0_DS2,
+            &VDC51.SC1_SCL0_DS3,
+            &VDC51.SC1_SCL0_DS4,
+            &VDC51.SC1_SCL0_DS5,
+            &VDC51.SC1_SCL0_DS6,
+            &VDC51.SC1_SCL0_DS7,
+            &VDC51.SC1_SCL0_US1,
+            &VDC51.SC1_SCL0_US2,
+            &VDC51.SC1_SCL0_US3,
+            &VDC51.SC1_SCL0_US4,
+            &VDC51.SC1_SCL0_US5,
+            &VDC51.SC1_SCL0_US6,
+            &VDC51.SC1_SCL0_US7,
+            &VDC51.SC1_SCL0_US8,
+            &VDC51.SC1_SCL0_OVR1,
+            &VDC51.SC1_SCL1_UPDATE,
+            &VDC51.SC1_SCL1_WR1,
+            &VDC51.SC1_SCL1_WR2,
+            &VDC51.SC1_SCL1_WR3,
+            &VDC51.SC1_SCL1_WR4,
+            &VDC51.SC1_SCL1_WR5,
+            &VDC51.SC1_SCL1_WR6,
+            &VDC51.SC1_SCL1_WR7,
+            &VDC51.SC1_SCL1_WR8,
+            &VDC51.SC1_SCL1_WR9,
+            &VDC51.SC1_SCL1_WR10,
+            &VDC51.SC1_SCL1_WR11,
+            &VDC51.SC1_SCL1_MON1,
+            &VDC51.SC1_SCL1_PBUF0,
+            &VDC51.SC1_SCL1_PBUF1,
+            &VDC51.SC1_SCL1_PBUF2,
+            &VDC51.SC1_SCL1_PBUF3,
+            &VDC51.SC1_SCL1_PBUF_FLD,
+            &VDC51.SC1_SCL1_PBUF_CNT
+        },
+        {   /* OIR */
+            &VDC51.OIR_SCL0_UPDATE,
+            &VDC51.OIR_SCL0_FRC1,
+            &VDC51.OIR_SCL0_FRC2,
+            &VDC51.OIR_SCL0_FRC3,
+            &VDC51.OIR_SCL0_FRC4,
+            &VDC51.OIR_SCL0_FRC5,
+            &VDC51.OIR_SCL0_FRC6,
+            &VDC51.OIR_SCL0_FRC7,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.OIR_SCL0_DS1,
+            &VDC51.OIR_SCL0_DS2,
+            &VDC51.OIR_SCL0_DS3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.OIR_SCL0_DS7,
+            &VDC51.OIR_SCL0_US1,
+            &VDC51.OIR_SCL0_US2,
+            &VDC51.OIR_SCL0_US3,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.OIR_SCL0_US8,
+            &VDC51.OIR_SCL0_OVR1,
+            &VDC51.OIR_SCL1_UPDATE,
+            &VDC51.OIR_SCL1_WR1,
+            &VDC51.OIR_SCL1_WR2,
+            &VDC51.OIR_SCL1_WR3,
+            &VDC51.OIR_SCL1_WR4,
+            &VDC51.OIR_SCL1_WR5,
+            &VDC51.OIR_SCL1_WR6,
+            &VDC51.OIR_SCL1_WR7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL
+        }
+    }
+};
+
+/* VDC5 image quality improver register address list */
+const vdc5_regaddr_img_qlty_imp_t vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM][VDC5_IMG_IMPRV_NUM] = {
+    {   /* Channel 0 */
+        {   /* SC0 */
+            &VDC50.ADJ0_UPDATE,
+            &VDC50.ADJ0_BKSTR_SET,
+            &VDC50.ADJ0_ENH_TIM1,
+            &VDC50.ADJ0_ENH_TIM2,
+            &VDC50.ADJ0_ENH_TIM3,
+            &VDC50.ADJ0_ENH_SHP1,
+            &VDC50.ADJ0_ENH_SHP2,
+            &VDC50.ADJ0_ENH_SHP3,
+            &VDC50.ADJ0_ENH_SHP4,
+            &VDC50.ADJ0_ENH_SHP5,
+            &VDC50.ADJ0_ENH_SHP6,
+            &VDC50.ADJ0_ENH_LTI1,
+            &VDC50.ADJ0_ENH_LTI2
+        },
+        {   /* SC1 */
+            &VDC50.ADJ1_UPDATE,
+            &VDC50.ADJ1_BKSTR_SET,
+            &VDC50.ADJ1_ENH_TIM1,
+            &VDC50.ADJ1_ENH_TIM2,
+            &VDC50.ADJ1_ENH_TIM3,
+            &VDC50.ADJ1_ENH_SHP1,
+            &VDC50.ADJ1_ENH_SHP2,
+            &VDC50.ADJ1_ENH_SHP3,
+            &VDC50.ADJ1_ENH_SHP4,
+            &VDC50.ADJ1_ENH_SHP5,
+            &VDC50.ADJ1_ENH_SHP6,
+            &VDC50.ADJ1_ENH_LTI1,
+            &VDC50.ADJ1_ENH_LTI2
+        }
+    },
+    {   /* Channel 1 */
+        {   /* SC0 */
+            &VDC51.ADJ0_UPDATE,
+            &VDC51.ADJ0_BKSTR_SET,
+            &VDC51.ADJ0_ENH_TIM1,
+            &VDC51.ADJ0_ENH_TIM2,
+            &VDC51.ADJ0_ENH_TIM3,
+            &VDC51.ADJ0_ENH_SHP1,
+            &VDC51.ADJ0_ENH_SHP2,
+            &VDC51.ADJ0_ENH_SHP3,
+            &VDC51.ADJ0_ENH_SHP4,
+            &VDC51.ADJ0_ENH_SHP5,
+            &VDC51.ADJ0_ENH_SHP6,
+            &VDC51.ADJ0_ENH_LTI1,
+            &VDC51.ADJ0_ENH_LTI2
+        },
+        {   /* SC1 */
+            &VDC51.ADJ1_UPDATE,
+            &VDC51.ADJ1_BKSTR_SET,
+            &VDC51.ADJ1_ENH_TIM1,
+            &VDC51.ADJ1_ENH_TIM2,
+            &VDC51.ADJ1_ENH_TIM3,
+            &VDC51.ADJ1_ENH_SHP1,
+            &VDC51.ADJ1_ENH_SHP2,
+            &VDC51.ADJ1_ENH_SHP3,
+            &VDC51.ADJ1_ENH_SHP4,
+            &VDC51.ADJ1_ENH_SHP5,
+            &VDC51.ADJ1_ENH_SHP6,
+            &VDC51.ADJ1_ENH_LTI1,
+            &VDC51.ADJ1_ENH_LTI2
+        }
+    }
+};
+
+/* VDC5 color matrix register address list */
+const vdc5_regaddr_color_matrix_t vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM][VDC5_COLORMTX_NUM] = {
+    {   /* Channel 0 */
+        {   /* Input Controller */
+            &VDC50.IMGCNT_UPDATE,
+            &VDC50.IMGCNT_MTX_MODE,
+            &VDC50.IMGCNT_MTX_YG_ADJ0,
+            &VDC50.IMGCNT_MTX_YG_ADJ1,
+            &VDC50.IMGCNT_MTX_CBB_ADJ0,
+            &VDC50.IMGCNT_MTX_CBB_ADJ1,
+            &VDC50.IMGCNT_MTX_CRR_ADJ0,
+            &VDC50.IMGCNT_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 0 */
+            &VDC50.ADJ0_UPDATE,
+            &VDC50.ADJ0_MTX_MODE,
+            &VDC50.ADJ0_MTX_YG_ADJ0,
+            &VDC50.ADJ0_MTX_YG_ADJ1,
+            &VDC50.ADJ0_MTX_CBB_ADJ0,
+            &VDC50.ADJ0_MTX_CBB_ADJ1,
+            &VDC50.ADJ0_MTX_CRR_ADJ0,
+            &VDC50.ADJ0_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 1 */
+            &VDC50.ADJ1_UPDATE,
+            &VDC50.ADJ1_MTX_MODE,
+            &VDC50.ADJ1_MTX_YG_ADJ0,
+            &VDC50.ADJ1_MTX_YG_ADJ1,
+            &VDC50.ADJ1_MTX_CBB_ADJ0,
+            &VDC50.ADJ1_MTX_CBB_ADJ1,
+            &VDC50.ADJ1_MTX_CRR_ADJ0,
+            &VDC50.ADJ1_MTX_CRR_ADJ1
+        }
+    },
+    {   /* Channel 1 */
+        {   /* Input Controller */
+            &VDC51.IMGCNT_UPDATE,
+            &VDC51.IMGCNT_MTX_MODE,
+            &VDC51.IMGCNT_MTX_YG_ADJ0,
+            &VDC51.IMGCNT_MTX_YG_ADJ1,
+            &VDC51.IMGCNT_MTX_CBB_ADJ0,
+            &VDC51.IMGCNT_MTX_CBB_ADJ1,
+            &VDC51.IMGCNT_MTX_CRR_ADJ0,
+            &VDC51.IMGCNT_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 0 */
+            &VDC51.ADJ0_UPDATE,
+            &VDC51.ADJ0_MTX_MODE,
+            &VDC51.ADJ0_MTX_YG_ADJ0,
+            &VDC51.ADJ0_MTX_YG_ADJ1,
+            &VDC51.ADJ0_MTX_CBB_ADJ0,
+            &VDC51.ADJ0_MTX_CBB_ADJ1,
+            &VDC51.ADJ0_MTX_CRR_ADJ0,
+            &VDC51.ADJ0_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 1 */
+            &VDC51.ADJ1_UPDATE,
+            &VDC51.ADJ1_MTX_MODE,
+            &VDC51.ADJ1_MTX_YG_ADJ0,
+            &VDC51.ADJ1_MTX_YG_ADJ1,
+            &VDC51.ADJ1_MTX_CBB_ADJ0,
+            &VDC51.ADJ1_MTX_CBB_ADJ1,
+            &VDC51.ADJ1_MTX_CRR_ADJ0,
+            &VDC51.ADJ1_MTX_CRR_ADJ1
+        }
+    }
+};
+
+/* VDC5 image synthesizer register address list */
+const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM] = {
+    {   /* Channel 0 */
+        {   /* GR0 */
+            &VDC50.GR0_UPDATE,
+            &VDC50.GR0_FLM_RD,
+            &VDC50.GR0_FLM1,
+            &VDC50.GR0_FLM2,
+            &VDC50.GR0_FLM3,
+            &VDC50.GR0_FLM4,
+            &VDC50.GR0_FLM5,
+            &VDC50.GR0_FLM6,
+            &VDC50.GR0_AB1,
+            &VDC50.GR0_AB2,
+            &VDC50.GR0_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR0_AB7,
+            &VDC50.GR0_AB8,
+            &VDC50.GR0_AB9,
+            &VDC50.GR0_AB10,
+            &VDC50.GR0_AB11,
+            &VDC50.GR0_BASE,
+            &VDC50.GR0_CLUT,
+            NULL
+        },
+        {   /* GR1 */
+            &VDC50.GR1_UPDATE,
+            &VDC50.GR1_FLM_RD,
+            &VDC50.GR1_FLM1,
+            &VDC50.GR1_FLM2,
+            &VDC50.GR1_FLM3,
+            &VDC50.GR1_FLM4,
+            &VDC50.GR1_FLM5,
+            &VDC50.GR1_FLM6,
+            &VDC50.GR1_AB1,
+            &VDC50.GR1_AB2,
+            &VDC50.GR1_AB3,
+            &VDC50.GR1_AB4,
+            &VDC50.GR1_AB5,
+            &VDC50.GR1_AB6,
+            &VDC50.GR1_AB7,
+            &VDC50.GR1_AB8,
+            &VDC50.GR1_AB9,
+            &VDC50.GR1_AB10,
+            &VDC50.GR1_AB11,
+            &VDC50.GR1_BASE,
+            &VDC50.GR1_CLUT,
+            &VDC50.GR1_MON
+        },
+        {   /* GR2 */
+            &VDC50.GR2_UPDATE,
+            &VDC50.GR2_FLM_RD,
+            &VDC50.GR2_FLM1,
+            &VDC50.GR2_FLM2,
+            &VDC50.GR2_FLM3,
+            &VDC50.GR2_FLM4,
+            &VDC50.GR2_FLM5,
+            &VDC50.GR2_FLM6,
+            &VDC50.GR2_AB1,
+            &VDC50.GR2_AB2,
+            &VDC50.GR2_AB3,
+            &VDC50.GR2_AB4,
+            &VDC50.GR2_AB5,
+            &VDC50.GR2_AB6,
+            &VDC50.GR2_AB7,
+            &VDC50.GR2_AB8,
+            &VDC50.GR2_AB9,
+            &VDC50.GR2_AB10,
+            &VDC50.GR2_AB11,
+            &VDC50.GR2_BASE,
+            &VDC50.GR2_CLUT,
+            &VDC50.GR2_MON
+        },
+        {   /* GR3 */
+            &VDC50.GR3_UPDATE,
+            &VDC50.GR3_FLM_RD,
+            &VDC50.GR3_FLM1,
+            &VDC50.GR3_FLM2,
+            &VDC50.GR3_FLM3,
+            &VDC50.GR3_FLM4,
+            &VDC50.GR3_FLM5,
+            &VDC50.GR3_FLM6,
+            &VDC50.GR3_AB1,
+            &VDC50.GR3_AB2,
+            &VDC50.GR3_AB3,
+            &VDC50.GR3_AB4,
+            &VDC50.GR3_AB5,
+            &VDC50.GR3_AB6,
+            &VDC50.GR3_AB7,
+            &VDC50.GR3_AB8,
+            &VDC50.GR3_AB9,
+            &VDC50.GR3_AB10,
+            &VDC50.GR3_AB11,
+            &VDC50.GR3_BASE,
+            &VDC50.GR3_CLUT_INT,
+            &VDC50.GR3_MON
+        },
+        {   /* VIN */
+            &VDC50.GR_VIN_UPDATE,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR_VIN_AB1,
+            &VDC50.GR_VIN_AB2,
+            &VDC50.GR_VIN_AB3,
+            &VDC50.GR_VIN_AB4,
+            &VDC50.GR_VIN_AB5,
+            &VDC50.GR_VIN_AB6,
+            &VDC50.GR_VIN_AB7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR_VIN_BASE,
+            NULL,
+            &VDC50.GR_VIN_MON
+        },
+        {   /* OIR */
+            &VDC50.GR_OIR_UPDATE,
+            &VDC50.GR_OIR_FLM_RD,
+            &VDC50.GR_OIR_FLM1,
+            &VDC50.GR_OIR_FLM2,
+            &VDC50.GR_OIR_FLM3,
+            &VDC50.GR_OIR_FLM4,
+            &VDC50.GR_OIR_FLM5,
+            &VDC50.GR_OIR_FLM6,
+            &VDC50.GR_OIR_AB1,
+            &VDC50.GR_OIR_AB2,
+            &VDC50.GR_OIR_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR_OIR_AB7,
+            &VDC50.GR_OIR_AB8,
+            &VDC50.GR_OIR_AB9,
+            &VDC50.GR_OIR_AB10,
+            &VDC50.GR_OIR_AB11,
+            &VDC50.GR_OIR_BASE,
+            &VDC50.GR_OIR_CLUT,
+            &VDC50.GR_OIR_MON
+        }
+    },
+    {   /* Channel 1 */
+        {   /* GR0 */
+            &VDC51.GR0_UPDATE,
+            &VDC51.GR0_FLM_RD,
+            &VDC51.GR0_FLM1,
+            &VDC51.GR0_FLM2,
+            &VDC51.GR0_FLM3,
+            &VDC51.GR0_FLM4,
+            &VDC51.GR0_FLM5,
+            &VDC51.GR0_FLM6,
+            &VDC51.GR0_AB1,
+            &VDC51.GR0_AB2,
+            &VDC51.GR0_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR0_AB7,
+            &VDC51.GR0_AB8,
+            &VDC51.GR0_AB9,
+            &VDC51.GR0_AB10,
+            &VDC51.GR0_AB11,
+            &VDC51.GR0_BASE,
+            &VDC51.GR0_CLUT,
+            NULL
+        },
+        {   /* GR1 */
+            &VDC51.GR1_UPDATE,
+            &VDC51.GR1_FLM_RD,
+            &VDC51.GR1_FLM1,
+            &VDC51.GR1_FLM2,
+            &VDC51.GR1_FLM3,
+            &VDC51.GR1_FLM4,
+            &VDC51.GR1_FLM5,
+            &VDC51.GR1_FLM6,
+            &VDC51.GR1_AB1,
+            &VDC51.GR1_AB2,
+            &VDC51.GR1_AB3,
+            &VDC51.GR1_AB4,
+            &VDC51.GR1_AB5,
+            &VDC51.GR1_AB6,
+            &VDC51.GR1_AB7,
+            &VDC51.GR1_AB8,
+            &VDC51.GR1_AB9,
+            &VDC51.GR1_AB10,
+            &VDC51.GR1_AB11,
+            &VDC51.GR1_BASE,
+            &VDC51.GR1_CLUT,
+            &VDC51.GR1_MON
+        },
+        {   /* GR2 */
+            &VDC51.GR2_UPDATE,
+            &VDC51.GR2_FLM_RD,
+            &VDC51.GR2_FLM1,
+            &VDC51.GR2_FLM2,
+            &VDC51.GR2_FLM3,
+            &VDC51.GR2_FLM4,
+            &VDC51.GR2_FLM5,
+            &VDC51.GR2_FLM6,
+            &VDC51.GR2_AB1,
+            &VDC51.GR2_AB2,
+            &VDC51.GR2_AB3,
+            &VDC51.GR2_AB4,
+            &VDC51.GR2_AB5,
+            &VDC51.GR2_AB6,
+            &VDC51.GR2_AB7,
+            &VDC51.GR2_AB8,
+            &VDC51.GR2_AB9,
+            &VDC51.GR2_AB10,
+            &VDC51.GR2_AB11,
+            &VDC51.GR2_BASE,
+            &VDC51.GR2_CLUT,
+            &VDC51.GR2_MON
+        },
+        {   /* GR3 */
+            &VDC51.GR3_UPDATE,
+            &VDC51.GR3_FLM_RD,
+            &VDC51.GR3_FLM1,
+            &VDC51.GR3_FLM2,
+            &VDC51.GR3_FLM3,
+            &VDC51.GR3_FLM4,
+            &VDC51.GR3_FLM5,
+            &VDC51.GR3_FLM6,
+            &VDC51.GR3_AB1,
+            &VDC51.GR3_AB2,
+            &VDC51.GR3_AB3,
+            &VDC51.GR3_AB4,
+            &VDC51.GR3_AB5,
+            &VDC51.GR3_AB6,
+            &VDC51.GR3_AB7,
+            &VDC51.GR3_AB8,
+            &VDC51.GR3_AB9,
+            &VDC51.GR3_AB10,
+            &VDC51.GR3_AB11,
+            &VDC51.GR3_BASE,
+            &VDC51.GR3_CLUT_INT,
+            &VDC51.GR3_MON
+        },
+        {   /* VIN */
+            &VDC51.GR_VIN_UPDATE,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR_VIN_AB1,
+            &VDC51.GR_VIN_AB2,
+            &VDC51.GR_VIN_AB3,
+            &VDC51.GR_VIN_AB4,
+            &VDC51.GR_VIN_AB5,
+            &VDC51.GR_VIN_AB6,
+            &VDC51.GR_VIN_AB7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR_VIN_BASE,
+            NULL,
+            &VDC51.GR_VIN_MON
+        },
+        {   /* OIR */
+            &VDC51.GR_OIR_UPDATE,
+            &VDC51.GR_OIR_FLM_RD,
+            &VDC51.GR_OIR_FLM1,
+            &VDC51.GR_OIR_FLM2,
+            &VDC51.GR_OIR_FLM3,
+            &VDC51.GR_OIR_FLM4,
+            &VDC51.GR_OIR_FLM5,
+            &VDC51.GR_OIR_FLM6,
+            &VDC51.GR_OIR_AB1,
+            &VDC51.GR_OIR_AB2,
+            &VDC51.GR_OIR_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR_OIR_AB7,
+            &VDC51.GR_OIR_AB8,
+            &VDC51.GR_OIR_AB9,
+            &VDC51.GR_OIR_AB10,
+            &VDC51.GR_OIR_AB11,
+            &VDC51.GR_OIR_BASE,
+            &VDC51.GR_OIR_CLUT,
+            &VDC51.GR_OIR_MON
+        }
+    }
+};
+
+/* VDC5 CLUT register address list */
+uint32_t * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM] = {
+    {   /* Channel 0 */
+        &VDC5_CH0_GR0_CLUT_TBL,
+        &VDC5_CH0_GR1_CLUT_TBL,
+        &VDC5_CH0_GR2_CLUT_TBL,
+        &VDC5_CH0_GR3_CLUT_TBL,
+        NULL,
+        &VDC5_CH0_GR_OIR_CLUT_TBL
+    },
+    {   /* Channel 1 */
+        &VDC5_CH1_GR0_CLUT_TBL,
+        &VDC5_CH1_GR1_CLUT_TBL,
+        &VDC5_CH1_GR2_CLUT_TBL,
+        &VDC5_CH1_GR3_CLUT_TBL,
+        NULL,
+        &VDC5_CH1_GR_OIR_CLUT_TBL
+    }
+};
+
+/* VDC5 output controller register address list */
+const vdc5_regaddr_output_ctrl_t vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.TCON_UPDATE,
+        &VDC50.TCON_TIM,
+        &VDC50.TCON_TIM_STVA1,
+        &VDC50.TCON_TIM_STVA2,
+        &VDC50.TCON_TIM_STVB1,
+        &VDC50.TCON_TIM_STVB2,
+        &VDC50.TCON_TIM_STH1,
+        &VDC50.TCON_TIM_STH2,
+        &VDC50.TCON_TIM_STB1,
+        &VDC50.TCON_TIM_STB2,
+        &VDC50.TCON_TIM_CPV1,
+        &VDC50.TCON_TIM_CPV2,
+        &VDC50.TCON_TIM_POLA1,
+        &VDC50.TCON_TIM_POLA2,
+        &VDC50.TCON_TIM_POLB1,
+        &VDC50.TCON_TIM_POLB2,
+        &VDC50.TCON_TIM_DE,
+        &VDC50.OUT_UPDATE,
+        &VDC50.OUT_SET,
+        &VDC50.OUT_BRIGHT1,
+        &VDC50.OUT_BRIGHT2,
+        &VDC50.OUT_CONTRAST,
+        &VDC50.OUT_PDTHA,
+        &VDC50.OUT_CLK_PHASE
+    },
+    {   /* Channel 1 */
+        &VDC51.TCON_UPDATE,
+        &VDC51.TCON_TIM,
+        &VDC51.TCON_TIM_STVA1,
+        &VDC51.TCON_TIM_STVA2,
+        &VDC51.TCON_TIM_STVB1,
+        &VDC51.TCON_TIM_STVB2,
+        &VDC51.TCON_TIM_STH1,
+        &VDC51.TCON_TIM_STH2,
+        &VDC51.TCON_TIM_STB1,
+        &VDC51.TCON_TIM_STB2,
+        &VDC51.TCON_TIM_CPV1,
+        &VDC51.TCON_TIM_CPV2,
+        &VDC51.TCON_TIM_POLA1,
+        &VDC51.TCON_TIM_POLA2,
+        &VDC51.TCON_TIM_POLB1,
+        &VDC51.TCON_TIM_POLB2,
+        &VDC51.TCON_TIM_DE,
+        &VDC51.OUT_UPDATE,
+        &VDC51.OUT_SET,
+        &VDC51.OUT_BRIGHT1,
+        &VDC51.OUT_BRIGHT2,
+        &VDC51.OUT_CONTRAST,
+        &VDC51.OUT_PDTHA,
+        &VDC51.OUT_CLK_PHASE
+    }
+};
+
+/* VDC5 gamma correction register address list */
+const vdc5_regaddr_gamma_t vdc5_regaddr_gamma[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.GAM_SW,
+        &VDC50.GAM_G_UPDATE,
+        {
+            &VDC50.GAM_G_LUT1,
+            &VDC50.GAM_G_LUT2,
+            &VDC50.GAM_G_LUT3,
+            &VDC50.GAM_G_LUT4,
+            &VDC50.GAM_G_LUT5,
+            &VDC50.GAM_G_LUT6,
+            &VDC50.GAM_G_LUT7,
+            &VDC50.GAM_G_LUT8,
+            &VDC50.GAM_G_LUT9,
+            &VDC50.GAM_G_LUT10,
+            &VDC50.GAM_G_LUT11,
+            &VDC50.GAM_G_LUT12,
+            &VDC50.GAM_G_LUT13,
+            &VDC50.GAM_G_LUT14,
+            &VDC50.GAM_G_LUT15,
+            &VDC50.GAM_G_LUT16
+        },
+        {
+            &VDC50.GAM_G_AREA1,
+            &VDC50.GAM_G_AREA2,
+            &VDC50.GAM_G_AREA3,
+            &VDC50.GAM_G_AREA4,
+            &VDC50.GAM_G_AREA5,
+            &VDC50.GAM_G_AREA6,
+            &VDC50.GAM_G_AREA7,
+            &VDC50.GAM_G_AREA8
+        },
+        &VDC50.GAM_B_UPDATE,
+        {
+            &VDC50.GAM_B_LUT1,
+            &VDC50.GAM_B_LUT2,
+            &VDC50.GAM_B_LUT3,
+            &VDC50.GAM_B_LUT4,
+            &VDC50.GAM_B_LUT5,
+            &VDC50.GAM_B_LUT6,
+            &VDC50.GAM_B_LUT7,
+            &VDC50.GAM_B_LUT8,
+            &VDC50.GAM_B_LUT9,
+            &VDC50.GAM_B_LUT10,
+            &VDC50.GAM_B_LUT11,
+            &VDC50.GAM_B_LUT12,
+            &VDC50.GAM_B_LUT13,
+            &VDC50.GAM_B_LUT14,
+            &VDC50.GAM_B_LUT15,
+            &VDC50.GAM_B_LUT16
+        },
+        {
+            &VDC50.GAM_B_AREA1,
+            &VDC50.GAM_B_AREA2,
+            &VDC50.GAM_B_AREA3,
+            &VDC50.GAM_B_AREA4,
+            &VDC50.GAM_B_AREA5,
+            &VDC50.GAM_B_AREA6,
+            &VDC50.GAM_B_AREA7,
+            &VDC50.GAM_B_AREA8
+        },
+        &VDC50.GAM_R_UPDATE,
+        {
+            &VDC50.GAM_R_LUT1,
+            &VDC50.GAM_R_LUT2,
+            &VDC50.GAM_R_LUT3,
+            &VDC50.GAM_R_LUT4,
+            &VDC50.GAM_R_LUT5,
+            &VDC50.GAM_R_LUT6,
+            &VDC50.GAM_R_LUT7,
+            &VDC50.GAM_R_LUT8,
+            &VDC50.GAM_R_LUT9,
+            &VDC50.GAM_R_LUT10,
+            &VDC50.GAM_R_LUT11,
+            &VDC50.GAM_R_LUT12,
+            &VDC50.GAM_R_LUT13,
+            &VDC50.GAM_R_LUT14,
+            &VDC50.GAM_R_LUT15,
+            &VDC50.GAM_R_LUT16
+        },
+        {
+            &VDC50.GAM_R_AREA1,
+            &VDC50.GAM_R_AREA2,
+            &VDC50.GAM_R_AREA3,
+            &VDC50.GAM_R_AREA4,
+            &VDC50.GAM_R_AREA5,
+            &VDC50.GAM_R_AREA6,
+            &VDC50.GAM_R_AREA7,
+            &VDC50.GAM_R_AREA8
+        }
+    },
+    {   /* Channel 1 */
+        &VDC51.GAM_SW,
+        &VDC51.GAM_G_UPDATE,
+        {
+            &VDC51.GAM_G_LUT1,
+            &VDC51.GAM_G_LUT2,
+            &VDC51.GAM_G_LUT3,
+            &VDC51.GAM_G_LUT4,
+            &VDC51.GAM_G_LUT5,
+            &VDC51.GAM_G_LUT6,
+            &VDC51.GAM_G_LUT7,
+            &VDC51.GAM_G_LUT8,
+            &VDC51.GAM_G_LUT9,
+            &VDC51.GAM_G_LUT10,
+            &VDC51.GAM_G_LUT11,
+            &VDC51.GAM_G_LUT12,
+            &VDC51.GAM_G_LUT13,
+            &VDC51.GAM_G_LUT14,
+            &VDC51.GAM_G_LUT15,
+            &VDC51.GAM_G_LUT16
+        },
+        {
+            &VDC51.GAM_G_AREA1,
+            &VDC51.GAM_G_AREA2,
+            &VDC51.GAM_G_AREA3,
+            &VDC51.GAM_G_AREA4,
+            &VDC51.GAM_G_AREA5,
+            &VDC51.GAM_G_AREA6,
+            &VDC51.GAM_G_AREA7,
+            &VDC51.GAM_G_AREA8
+        },
+        &VDC51.GAM_B_UPDATE,
+        {
+            &VDC51.GAM_B_LUT1,
+            &VDC51.GAM_B_LUT2,
+            &VDC51.GAM_B_LUT3,
+            &VDC51.GAM_B_LUT4,
+            &VDC51.GAM_B_LUT5,
+            &VDC51.GAM_B_LUT6,
+            &VDC51.GAM_B_LUT7,
+            &VDC51.GAM_B_LUT8,
+            &VDC51.GAM_B_LUT9,
+            &VDC51.GAM_B_LUT10,
+            &VDC51.GAM_B_LUT11,
+            &VDC51.GAM_B_LUT12,
+            &VDC51.GAM_B_LUT13,
+            &VDC51.GAM_B_LUT14,
+            &VDC51.GAM_B_LUT15,
+            &VDC51.GAM_B_LUT16
+        },
+        {
+            &VDC51.GAM_B_AREA1,
+            &VDC51.GAM_B_AREA2,
+            &VDC51.GAM_B_AREA3,
+            &VDC51.GAM_B_AREA4,
+            &VDC51.GAM_B_AREA5,
+            &VDC51.GAM_B_AREA6,
+            &VDC51.GAM_B_AREA7,
+            &VDC51.GAM_B_AREA8
+        },
+        &VDC51.GAM_R_UPDATE,
+        {
+            &VDC51.GAM_R_LUT1,
+            &VDC51.GAM_R_LUT2,
+            &VDC51.GAM_R_LUT3,
+            &VDC51.GAM_R_LUT4,
+            &VDC51.GAM_R_LUT5,
+            &VDC51.GAM_R_LUT6,
+            &VDC51.GAM_R_LUT7,
+            &VDC51.GAM_R_LUT8,
+            &VDC51.GAM_R_LUT9,
+            &VDC51.GAM_R_LUT10,
+            &VDC51.GAM_R_LUT11,
+            &VDC51.GAM_R_LUT12,
+            &VDC51.GAM_R_LUT13,
+            &VDC51.GAM_R_LUT14,
+            &VDC51.GAM_R_LUT15,
+            &VDC51.GAM_R_LUT16
+        },
+        {
+            &VDC51.GAM_R_AREA1,
+            &VDC51.GAM_R_AREA2,
+            &VDC51.GAM_R_AREA3,
+            &VDC51.GAM_R_AREA4,
+            &VDC51.GAM_R_AREA5,
+            &VDC51.GAM_R_AREA6,
+            &VDC51.GAM_R_AREA7,
+            &VDC51.GAM_R_AREA8
+        }
+    }
+};
+
+/* VDC5 system controller register address list */
+const vdc5_regaddr_system_ctrl_t vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.SYSCNT_INT1,
+        &VDC50.SYSCNT_INT2,
+        &VDC50.SYSCNT_INT3,
+        &VDC50.SYSCNT_INT4,
+        &VDC50.SYSCNT_INT5,
+        &VDC50.SYSCNT_INT6,
+        &VDC50.SYSCNT_PANEL_CLK,
+        &VDC50.SYSCNT_CLUT
+    },
+    {   /* Channel 1 */
+        &VDC51.SYSCNT_INT1,
+        &VDC51.SYSCNT_INT2,
+        &VDC51.SYSCNT_INT3,
+        &VDC51.SYSCNT_INT4,
+        &VDC51.SYSCNT_INT5,
+        &VDC51.SYSCNT_INT6,
+        &VDC51.SYSCNT_PANEL_CLK,
+        &VDC51.SYSCNT_CLUT
+    }
+};
+
+/* LVDS register address list */
+const vdc5_regaddr_lvds_t vdc5_regaddr_lvds = {
+    &LVDS.LVDS_UPDATE,
+    &LVDS.LVDSFCL,
+    &LVDS.LCLKSELR,
+    &LVDS.LPLLSETR,
+    &LVDS.LPHYACC
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_shared_param.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1029 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_shared_param.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver shared parameter processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Two to the power of eleven */
+#define     TWO_POWER_ELEVEN                (2048)
+
+#define     VDC5_SPARA_DIV_2                (2)
+#define     VDC5_SPARA_DIV_256              (256)
+
+/* Color Conversion Value */
+#define     VDC5_SPARA_COLOR_CONV_RANGE     (255)
+#define     VDC5_SPARA_COLOR_CONV_OFFSET    (128)
+
+/* Color mask data */
+#define     VDC5_SPARA_COLOR_8BIT_MASK      (0x000000FFu)
+
+/* shift value */
+#define     VDC5_SPARA_SHIFT_16             (16u)
+#define     VDC5_SPARA_SHIFT_8              (8u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct {
+    vdc5_panel_clksel_t     panel_icksel;   /*!< Panel clock select */
+    vdc5_onoff_t            lvds_ref;       /*!< Reference to the LVDS PLL clock */
+    vdc5_color_space_t      color_sp_in;    /*!< Color space of the input video image signal */
+    vdc5_input_sel_t        inp_sel;        /*!< Input select */
+    vdc5_res_vs_in_sel_t    res_vs_in_sel;  /*!< Horizontal/vertical sync signal output and
+                                                 full-screen enable signal select */
+    vdc5_onoff_t            cascade;        /*!< Cascaded connection */
+    vdc5_onoff_t            und_sel;        /*!< Selection of lower-layer plane in scaler */
+    uint32_t                bg_color_rgb;   /*!< Background color in 24-bit RGB color format */
+    uint32_t                bg_color_crycb; /*!< Background color in 24-bit CrYCb format */
+} vdc5_shared_param_common_t;
+
+typedef struct {
+    vdc5_wr_md_t            res_ds_wr_md;   /*!< Frame buffer writing mode for image processing */
+    vdc5_res_inter_t        res_inter;      /*!< Field operating mode select */
+    vdc5_color_space_t      color_sp_fb_wr; /*!< Color space of the frame buffer writing format */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+    vdc5_width_read_fb_t    width_wr_fb;    /*!< Size of the image output by scaling-down control block */
+} vdc5_shared_param_scaling_t;
+
+typedef struct {
+    vdc5_gr_ln_off_dir_t    gr_ln_off_dir;      /*!< Line offset address direction of the frame buffer */
+    vdc5_gr_flm_sel_t       gr_flm_sel;         /*!< Frame buffer address setting signal */
+    vdc5_gr_format_t        gr_format;          /*!< Format of the frame buffer read signal */
+    vdc5_color_space_t      color_sp_fb_rd;     /*!< Color space of the frame buffer reading format */
+    vdc5_onoff_t            adj_sel;            /*!< Folding handling (on/off) */
+    vdc5_period_rect_t      gr_grc;             /*!< Graphics display area */
+    vdc5_width_read_fb_t    width_read_fb;      /*!< Size of the frame buffer to be read */
+} vdc5_shared_param_graphics_t;
+
+typedef struct {
+    vdc5_resource_state_t   rsrc_panel_clock;
+    vdc5_resource_state_t   rsrc_video_input;
+    vdc5_resource_state_t   rsrc_vsync_signal;
+    vdc5_resource_state_t   rsrc_lcd_panel;
+} vdc5_shared_param_resource_t;
+
+/*! Read/write process state */
+typedef enum {
+    VDC5_RW_PROC_STATE_DISABLE   = 0,
+    VDC5_RW_PROC_STATE_ENABLE    = 1
+} vdc5_rw_proc_state_t;
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer(const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type);
+static uint32_t SumProduct(
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset);
+
+static vdc5_shared_param_common_t   param_common[VDC5_CHANNEL_NUM];
+static vdc5_shared_param_scaling_t  param_scaling[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM];
+static vdc5_shared_param_graphics_t param_graphics[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+/*! A channel in VDC5 whose data is to be output through the LVDS */
+static vdc5_channel_t               lvds_vdc_sel_ch;
+
+static vdc5_resource_state_t        layer_resource[VDC5_CHANNEL_NUM][VDC5_LAYER_ID_NUM];
+static vdc5_rw_proc_state_t         rw_proc_state[VDC5_CHANNEL_NUM][VDC5_LAYER_ID_NUM];
+
+static vdc5_onoff_t video_input_flag[VDC5_CHANNEL_NUM] = {VDC5_OFF, VDC5_OFF};
+
+
+/**************************************************************************//**
+ * @brief       Initializes variables of the VDC5 driver
+ * @param[in]   ch                      : Channel
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmInit (const vdc5_channel_t ch)
+{
+    int32_t                         layer_id_num;
+    vdc5_shared_param_common_t    * shared_param_common;
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+    vdc5_scaling_type_t             scaling_id;
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+    vdc5_graphics_type_t            graphics_id;
+
+    for (layer_id_num = 0; layer_id_num < VDC5_LAYER_ID_NUM; layer_id_num++) {
+        layer_resource[ch][layer_id_num] = VDC5_RESOURCE_ST_INVALID;
+        rw_proc_state[ch][layer_id_num]  = VDC5_RW_PROC_STATE_DISABLE;
+    }
+
+    shared_param_common = &param_common[ch];
+
+    shared_param_common->panel_icksel   = VDC5_PANEL_ICKSEL_PERI;   /* Panel clock select */
+    shared_param_common->lvds_ref       = VDC5_OFF;                 /* Reference to the LVDS PLL clock */
+    shared_param_common->res_vs_in_sel  = VDC5_RES_VS_IN_SEL_SC0;   /* Horizontal/vertical sync signal output and
+                                                                       full-screen enable signal select */
+    shared_param_common->cascade        = VDC5_ON;                  /* Cascaded connection */
+    shared_param_common->und_sel        = VDC5_OFF;                 /* Selection of lower-layer plane in scaler */
+    shared_param_common->bg_color_rgb   = (uint32_t)0u;             /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_crycb = (uint32_t)0u;             /* Background color in 24-bit CrYCb format */
+
+    if (video_input_flag[ch] == VDC5_OFF) {
+        shared_param_common->color_sp_in    = VDC5_COLOR_SPACE_GBR; /* Color space of the input video image signal */
+        shared_param_common->inp_sel        = VDC5_INPUT_SEL_VDEC;  /* Input select */
+    }
+
+    for (scaling_id = VDC5_SC_TYPE_SC0; scaling_id < VDC5_SC_TYPE_NUM; scaling_id++) {
+        shared_param_scaling = &param_scaling[ch][scaling_id];
+
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md      = VDC5_WR_MD_NORMAL;
+        shared_param_scaling->res_inter         = VDC5_RES_INTER_PROGRESSIVE;   /* Field operating mode select */
+        /* Color space of the frame buffer writing format */
+        shared_param_scaling->color_sp_fb_wr    = VDC5_COLOR_SPACE_GBR;
+        /* Frame buffer base address for bottom */
+        shared_param_scaling->btm_base          = NULL;
+        /* Size of the image output by scaling-down control block */
+        shared_param_scaling->width_wr_fb.in_vw = (uint16_t)0;
+        shared_param_scaling->width_wr_fb.in_hw = (uint16_t)0;
+    }
+
+    for (graphics_id = VDC5_GR_TYPE_GR0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++) {
+        shared_param_graphics = &param_graphics[ch][graphics_id];
+
+        /* Line offset address direction of the frame buffer */
+        shared_param_graphics->gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC;
+        /* Frame buffer address setting signal */
+        shared_param_graphics->gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM;
+        /* Format of the frame buffer read signal */
+        shared_param_graphics->gr_format = VDC5_GR_FORMAT_RGB565;
+        /* Color space of the frame buffer reading format */
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+        /* Folding handling (on/off) */
+        shared_param_graphics->adj_sel = VDC5_OFF;
+        /* Graphics display area */
+        shared_param_graphics->gr_grc.vs = (uint16_t)0;
+        shared_param_graphics->gr_grc.vw = (uint16_t)0;
+        shared_param_graphics->gr_grc.hs = (uint16_t)0;
+        shared_param_graphics->gr_grc.hw = (uint16_t)0;
+        /* Size of the frame buffer to be read */
+        shared_param_graphics->width_read_fb.in_vw = (uint16_t)0;
+        shared_param_graphics->width_read_fb.in_hw = (uint16_t)0;
+    }
+    /* A channel in VDC5 whose data is to be output through the LVDS */
+    lvds_vdc_sel_ch = VDC5_CHANNEL_NUM;     /* Initialized with invalid channel */
+}   /* End of function VDC5_ShrdPrmInit() */
+
+/**************************************************************************//**
+ * @brief       Sets the initialization parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetInitParam (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common[ch];
+
+    /* Panel clock select */
+    shared_param_common->panel_icksel = param->panel_icksel;
+    /* Reference to the LVDS PLL clock */
+    if ((param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+        shared_param_common->lvds_ref = VDC5_ON;
+    }
+    if (param->lvds != NULL) {
+        /* A channel in VDC5 whose data is to be output through the LVDS */
+        lvds_vdc_sel_ch = param->lvds->lvds_vdc_sel;
+    }
+}   /* End of function VDC5_ShrdPrmSetInitParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the termination parameter
+ * @param[in]   ch                      : Channel
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetTerminate (const vdc5_channel_t ch)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common[ch];
+
+    /* Reference to the LVDS PLL clock */
+    shared_param_common->lvds_ref = VDC5_OFF;
+}   /* End of function VDC5_ShrdPrmSetTerminate() */
+
+/**************************************************************************//**
+ * @brief       Sets the video input setup parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetInputParam (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    video_input_flag[ch] = VDC5_ON;
+
+    shared_param_common = &param_common[ch];
+
+    /* Color space */
+    if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+        /* Video decoder output signals */
+        shared_param_common->color_sp_in = VDC5_COLOR_SPACE_YCBCR;
+    } else {
+        /* Signals supplied via the external input pins */
+        if ((param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+                (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+                (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB565)) {
+            shared_param_common->color_sp_in = VDC5_COLOR_SPACE_GBR;
+        } else {
+            shared_param_common->color_sp_in = VDC5_COLOR_SPACE_YCBCR;
+        }
+    }
+    /* Input select */
+    shared_param_common->inp_sel = param->inp_sel;
+}   /* End of function VDC5_ShrdPrmSetInputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the sync control parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetSyncParam (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common[ch];
+
+    shared_param_common->res_vs_in_sel = param->res_vs_in_sel;
+}   /* End of function VDC5_ShrdPrmSetSyncParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the display output configuration parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetOutputParam (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+    int32_t                         red;
+    int32_t                         green;
+    int32_t                         blue;
+    uint32_t                        y_val;
+    uint32_t                        cb_val;
+    uint32_t                        cr_val;
+
+    shared_param_common = &param_common[ch];
+
+    /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_rgb = param->bg_color;
+
+    red     = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_16) & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    green   = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_8)  & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    blue    = (int32_t)( param->bg_color                         & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    /* Y */
+    y_val = SumProduct(
+                red,
+                green,
+                blue,
+                (int32_t)VDC5_COLORCONV_Y_R,
+                (int32_t)VDC5_COLORCONV_Y_G,
+                (int32_t)VDC5_COLORCONV_Y_B,
+                0);
+    /* Cb */
+    cb_val = SumProduct(
+                 red,
+                 green,
+                 blue,
+                 (int32_t)VDC5_COLORCONV_CB_R,
+                 (int32_t)VDC5_COLORCONV_CB_G,
+                 (int32_t)VDC5_COLORCONV_CB_B,
+                 (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+    /* Cr */
+    cr_val = SumProduct(
+                 red,
+                 green,
+                 blue,
+                 (int32_t)VDC5_COLORCONV_CR_R,
+                 (int32_t)VDC5_COLORCONV_CR_G,
+                 (int32_t)VDC5_COLORCONV_CR_B,
+                 (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+    /* Background color in 24-bit CrYCb format */
+    shared_param_common->bg_color_crycb = (uint32_t)((cr_val << VDC5_SPARA_SHIFT_16) | (y_val << VDC5_SPARA_SHIFT_8) | cb_val);
+}   /* End of function VDC5_ShrdPrmSetOutputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write control parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetWriteParam (
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling[ch][scaling_id];
+
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md = VDC5_WR_MD_NORMAL;
+        /* Field operating mode select */
+        shared_param_scaling->res_inter = VDC5_RES_INTER_PROGRESSIVE;
+    } else {
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+        /* Field operating mode select */
+        shared_param_scaling->res_inter = param->res_inter;
+    }
+
+    /* Color space of the frame buffer */
+    if ((param->res_md == VDC5_RES_MD_YCBCR422) || (param->res_md == VDC5_RES_MD_YCBCR444)) {
+        shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_YCBCR;
+    } else {
+        shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_GBR;
+    }
+
+    /* Frame buffer base address for bottom */
+    shared_param_scaling->btm_base = param->btm_base;
+    /* Size of the image output by scaling-down control block */
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res.vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res.hw;
+    } else {
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+    }
+}   /* End of function VDC5_ShrdPrmSetWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write change parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgWriteParam (
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param)
+{
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling[ch][scaling_id];
+
+    if (scaling_id != VDC5_SC_TYPE_OIR) {
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+    }
+
+    /* Size of the image output by scaling-down control block */
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res.vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res.hw;
+    } else {
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+    }
+}   /* End of function VDC5_ShrdPrmSetChgWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read control parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetReadParam (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[ch][graphics_id];
+
+    /* Line offset address direction of the frame buffer */
+    shared_param_graphics->gr_ln_off_dir = param->gr_ln_off_dir;
+
+    /* Frame buffer address setting signal */
+    shared_param_graphics->gr_flm_sel = param->gr_flm_sel;
+
+    /* Format of the frame buffer read signal */
+    shared_param_graphics->gr_format = param->gr_format;
+
+    /* Color space of the frame buffer */
+    if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444)) {
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_YCBCR;
+    } else {
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+    }
+
+    /* Folding handling (on/off) */
+    shared_param_graphics->adj_sel = param->adj_sel;
+
+    /* Graphics display area */
+    shared_param_graphics->gr_grc = param->gr_grc;
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL) {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    } else {
+        /* If not specified, ... */
+        if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+            /* The size of the frame buffer to be read is assumed that it is the same as
+               the width of the graphics display area. */
+            shared_param_graphics->width_read_fb.in_vw = param->gr_grc.vw;
+            shared_param_graphics->width_read_fb.in_hw = param->gr_grc.hw;
+        } else {
+            /* The size of the image output by scaling-down control block is used for the size of the frame buffer
+               to be read when a frame buffer address setting signal links to the video image signals. */
+            if (graphics_id == VDC5_GR_TYPE_GR0) {
+                /* Scaler 0 */
+                shared_param_graphics->width_read_fb = param_scaling[ch][VDC5_SC_TYPE_SC0].width_wr_fb;
+            } else { /* Scaler 1 */
+                shared_param_graphics->width_read_fb = param_scaling[ch][VDC5_SC_TYPE_SC1].width_wr_fb;
+            }
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetReadParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read change parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgReadParam (
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[ch][graphics_id];
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL) {
+        shared_param_graphics->gr_grc = *(param->gr_grc);
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL) {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    }
+}   /* End of function VDC5_ShrdPrmSetChgReadParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the cascaded connection
+ * @param[in]   ch                      : Channel
+ * @param[in]   cascade                 : Cascaded connection
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetCascade (const vdc5_channel_t ch, const vdc5_onoff_t cascade)
+{
+    param_common[ch].cascade = cascade;
+}   /* End of function VDC5_ShrdPrmSetCascade() */
+
+/**************************************************************************//**
+ * @brief       Sets the selection of lower-layer plane in scaler
+ * @param[in]   ch                      : Channel
+ * @param[in]   und_sel                 : Selection of lower-layer plane in scaler
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetUndSel (const vdc5_channel_t ch, const vdc5_onoff_t und_sel)
+{
+    param_common[ch].und_sel = und_sel;
+}   /* End of function VDC5_ShrdPrmSetUndSel() */
+
+/**************************************************************************//**
+ * @brief       Gets the panel clock select
+ * @param[in]   ch                      : Channel
+ * @retval      Panel clock select
+ *****************************************************************************/
+vdc5_panel_clksel_t VDC5_ShrdPrmGetPanelClkSel (const vdc5_channel_t ch)
+{
+    return param_common[ch].panel_icksel;
+}   /* End of function VDC5_ShrdPrmGetPanelClkSel() */
+
+/**************************************************************************//**
+ * @brief       Gets the reference to the LVDS PLL clock
+ * @param[in]   void
+ * @retval      Reference to the LVDS PLL clock
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetLvdsClkRef (void)
+{
+    vdc5_onoff_t onoff;
+
+    if ((param_common[VDC5_CHANNEL_0].lvds_ref == VDC5_OFF) && (param_common[VDC5_CHANNEL_1].lvds_ref == VDC5_OFF)) {
+        onoff = VDC5_OFF;
+    } else {
+        onoff = VDC5_ON;
+    }
+    return onoff;
+}   /* End of function VDC5_ShrdPrmGetLvdsClkRef() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the input video image signal
+ * @param[in]   ch                      : Channel
+ * @retval      Color space of the input video image signal
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace (const vdc5_channel_t ch)
+{
+    return param_common[ch].color_sp_in;
+}   /* End of function VDC5_ShrdPrmGetColorSpace() */
+
+/**************************************************************************//**
+ * @brief       Gets the input select
+ * @param[in]   ch                      : Channel
+ * @retval      Input select
+ *****************************************************************************/
+vdc5_input_sel_t VDC5_ShrdPrmGetInputSelect (const vdc5_channel_t ch)
+{
+    return param_common[ch].inp_sel;
+}   /* End of function VDC5_ShrdPrmGetInputSelect() */
+
+/**************************************************************************//**
+ * @brief       Gets the sync signal output and full-screen enable signal select
+ * @param[in]   ch                      : Channel
+ * @retval      Horizontal/vertical sync signal output and full-screen enable signal select
+ *              - VDC5_RES_VS_IN_SEL_SC0: Sync signal output and full-screen enable signal from scaler 0
+ *              - VDC5_RES_VS_IN_SEL_SC1: Sync signal output and full-screen enable signal from scaler 1
+ *****************************************************************************/
+vdc5_res_vs_in_sel_t VDC5_ShrdPrmGetVsInSel (const vdc5_channel_t ch)
+{
+    return param_common[ch].res_vs_in_sel;
+}   /* End of function VDC5_ShrdPrmGetVsInSel() */
+
+/**************************************************************************//**
+ * @brief       Gets the cascaded connection
+ * @param[in]   ch                      : Channel
+ * @retval      Cascaded connection (on/off)
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetCascade (const vdc5_channel_t ch)
+{
+    return param_common[ch].cascade;
+}   /* End of function VDC5_ShrdPrmGetCascade() */
+
+/**************************************************************************//**
+ * @brief       Gets the selection of lower-layer plane in scaler
+ * @param[in]   ch                      : Channel
+ * @retval      Selection of lower-layer plane in scaler
+ *              - VDC5_OFF: Selects graphics 0 as lower-layer graphics and graphics 1 as current graphics
+ *              - VDC5_ON: Selects graphics 1 as lower-layer graphics and graphics 0 as current graphics
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetUndSel (const vdc5_channel_t ch)
+{
+    return param_common[ch].und_sel;
+}   /* End of function VDC5_ShrdPrmGetUndSel() */
+
+/**************************************************************************//**
+ * @brief       Get the background color
+ * @param[in]   ch                      : Channel
+ * @param[in]   color_space             : Color space
+ * @retval      Background color in 24-bit RGB color format or CrYCb format
+ *****************************************************************************/
+uint32_t VDC5_ShrdPrmGetBgColor (const vdc5_channel_t ch, const vdc5_color_space_t color_space)
+{
+    return (color_space == VDC5_COLOR_SPACE_GBR) ? param_common[ch].bg_color_rgb : param_common[ch].bg_color_crycb;
+}   /* End of function VDC5_ShrdPrmGetBgColor() */
+
+/**************************************************************************//**
+ * @brief       Get the frame buffer writing mode for image processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Frame buffer writing mode for image processing
+ *****************************************************************************/
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].res_ds_wr_md;
+}   /* End of function VDC5_ShrdPrmGetWritingMode() */
+
+/**************************************************************************//**
+ * @brief       Gets the field operating mode select
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Field operating mode select
+ *****************************************************************************/
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].res_inter;
+}   /* End of function VDC5_ShrdPrmGetInterlace() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer writing format
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Color space of the frame buffer writing format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].color_sp_fb_wr;
+}   /* End of function VDC5_ShrdPrmGetColorSpaceFbWr() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer base address for bottom
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Frame buffer base address for bottom
+ *****************************************************************************/
+void * VDC5_ShrdPrmGetFrBuffBtm (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].btm_base;
+}   /* End of function VDC5_ShrdPrmGetFrBuffBtm() */
+
+/**************************************************************************//**
+ * @brief       Gets the line offset address direction of the frame buffer
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Line offset address direction of the frame buffer
+ *****************************************************************************/
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].gr_ln_off_dir;
+}   /* End of function VDC5_ShrdPrmGetLineOfsAddrDir() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer address setting signal
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Frame buffer address setting signal
+ *****************************************************************************/
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].gr_flm_sel;
+}   /* End of function VDC5_ShrdPrmGetSelFbAddrSig() */
+
+/**************************************************************************//**
+ * @brief       Gets the format of the frame buffer read signal
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Format of the frame buffer read signal
+ *****************************************************************************/
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].gr_format;
+}   /* End of function VDC5_ShrdPrmGetGraphicsFormat() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer reading format
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Color space of the frame buffer reading format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].color_sp_fb_rd;
+}   /* End of function VDC5_ShrdPrmGetColorSpaceFbRd() */
+
+/**************************************************************************//**
+ * @brief       Gets the folding handling
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Folding handling (on/off)
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].adj_sel;
+}   /* End of function VDC5_ShrdPrmGetMeasureFolding() */
+
+/**************************************************************************//**
+ * @brief       Gets the graphics display area
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Graphics display area
+ *****************************************************************************/
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return &param_graphics[ch][graphics_id].gr_grc;
+}   /* End of function VDC5_ShrdPrmGetDisplayArea() */
+
+/**************************************************************************//**
+ * @brief       Gets the size of the frame buffer to be read
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Size of the frame buffer to be read
+ *****************************************************************************/
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id)
+{
+    return &param_graphics[ch][graphics_id].width_read_fb;
+}   /* End of function VDC5_ShrdPrmGetFrBuffWidth_Rd() */
+
+/**************************************************************************//**
+ * @brief       Gets the VDC5 channel whose data is to be output through the LVDS
+ * @param[in]   void
+ * @retval      A channel in VDC5 whose data is to be output through the LVDS
+ *****************************************************************************/
+vdc5_channel_t VDC5_ShrdPrmGetLvdsCh (void)
+{
+    /* This value is valid only when LVDS PLL clock resource (VDC5_RESOURCE_LVDS_CLK) is valid. */
+    return lvds_vdc_sel_ch;
+}   /* End of function VDC5_ShrdPrmGetLvdsCh() */
+
+/**************************************************************************//**
+ * @brief       Updates the resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   rsrc_type               : Resource type
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetResource (
+    const vdc5_channel_t        ch,
+    const vdc5_resource_type_t  rsrc_type,
+    const vdc5_resource_state_t rsrc_state)
+{
+    vdc5_resource_state_t * resource_state;
+
+    resource_state = GetResourceStatePointer(ch, rsrc_type);
+    if (resource_state != NULL) {
+        *resource_state = rsrc_state;
+    }
+}   /* End of function VDC5_ShrdPrmSetResource() */
+
+/**************************************************************************//**
+ * @brief       Updates the layer resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetLayerResource (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_resource_state_t rsrc_state)
+{
+    uint32_t layer_id_num;
+
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        layer_resource[ch][layer_id] = rsrc_state;
+    } else {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+            if (rw_proc_state[ch][layer_id_num] == VDC5_RW_PROC_STATE_DISABLE) {
+                layer_resource[ch][layer_id_num] = rsrc_state;
+            }
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetResource (const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type)
+{
+    vdc5_resource_state_t * resource_state;
+    vdc5_resource_state_t   rsrc_state;
+
+    rsrc_state = VDC5_RESOURCE_ST_INVALID;
+
+    resource_state = GetResourceStatePointer(ch, rsrc_type);
+    if (resource_state != NULL) {
+        rsrc_state = *resource_state;
+    }
+    return rsrc_state;
+}   /* End of function VDC5_ShrdPrmGetResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the layer resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Layer resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    return layer_resource[ch][layer_id];
+}   /* End of function VDC5_ShrdPrmGetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing enabled
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcEnable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        if (layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) {
+            rw_proc_state[ch][layer_id] = VDC5_RW_PROC_STATE_ENABLE;
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetRwProcEnable() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing disabled
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcDisable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        if (layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) {
+            rw_proc_state[ch][layer_id] = VDC5_RW_PROC_STATE_DISABLE;
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetRwProcDisable() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is ready or not
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is disabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The specified layer is not ready.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_resource_state_t state;
+
+    if ((layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][layer_id] == VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    } else {
+        state = VDC5_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetRwProcReady() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is already run or not
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is enabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The specified layer is not enabled.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_resource_state_t state;
+
+    if ((layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][layer_id] != VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    } else {
+        state = VDC5_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetRwProcEnabled() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the OIR is already run or not
+ * @param[in]   ch                      : Channel
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the OIR is valid and
+ *                the data write/read processing in the OIR is enabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The OIR is not enabled.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetOirRwProcEnabled (const vdc5_channel_t ch)
+{
+    vdc5_resource_state_t state;
+
+    state = VDC5_RESOURCE_ST_INVALID;
+
+    if ((layer_resource[ch][VDC5_LAYER_ID_OIR_WR] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][VDC5_LAYER_ID_OIR_WR] != VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    }
+    if ((layer_resource[ch][VDC5_LAYER_ID_OIR_RD] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][VDC5_LAYER_ID_OIR_RD] != VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetOirRwProcEnabled() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Gets the pointer to the resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Pointer to the resource state
+ *****************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer (const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type)
+{
+    vdc5_resource_state_t             * resource_state;
+    static vdc5_shared_param_resource_t param_resource[VDC5_CHANNEL_NUM] = {
+        {VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID},
+        {VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID}
+    };
+    static vdc5_resource_state_t        lvds_resource = VDC5_RESOURCE_ST_INVALID;
+
+    switch (rsrc_type) {
+        case VDC5_RESOURCE_PANEL_CLK:
+            resource_state = &param_resource[ch].rsrc_panel_clock;
+            break;
+        case VDC5_RESOURCE_VIDEO_IN:
+            resource_state = &param_resource[ch].rsrc_video_input;
+            break;
+        case VDC5_RESOURCE_VSYNC:
+            resource_state = &param_resource[ch].rsrc_vsync_signal;
+            break;
+        case VDC5_RESOURCE_LCD_PANEL:
+            resource_state = &param_resource[ch].rsrc_lcd_panel;
+            break;
+        case VDC5_RESOURCE_LVDS_CLK:
+            resource_state = &lvds_resource;
+            break;
+
+        default:
+            resource_state = NULL;
+            break;
+    }
+    return resource_state;
+}   /* End of function GetResourceStatePointer() */
+
+/**************************************************************************//**
+ * @brief       Product-sum operation
+ * @param[in]   red             : 8 bits for red
+ * @param[in]   green           : 8 bits for green
+ * @param[in]   blue            : 8 bits for blue
+ * @param[in]   coeff_r         : Coefficient value for Cr/R signal gain adjustment
+ * @param[in]   coeff_g         : Coefficient value for Y/G signal gain adjustment
+ * @param[in]   coeff_b         : Coefficient value for Cb/B signal gain adjustment
+ * @param[in]   offset          : Coefficient value for offset adjustment
+ * @retval      Answer
+ *****************************************************************************/
+static uint32_t SumProduct (
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset)
+{
+    int32_t color_val;
+
+    /* Coefficient values are represented in 11-bit two's complement integer. */
+    if (coeff_r >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+        coeff_r -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_g >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+        coeff_g -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_b >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+        coeff_b -= (int32_t)TWO_POWER_ELEVEN;
+    }
+
+    color_val  = (red * coeff_r) + (green * coeff_g) + (blue * coeff_b);
+    color_val /= (int32_t)VDC5_SPARA_DIV_256;
+    color_val += offset;
+    if (color_val < 0) {
+        color_val = 0;
+    } else if (color_val > (int32_t)VDC5_SPARA_COLOR_CONV_RANGE) {
+        color_val = (int32_t)VDC5_SPARA_COLOR_CONV_RANGE;
+    } else {
+    }
+    return (uint32_t)color_val;
+}   /* End of function SumProduct() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdc5/src/r_vdc5_shared_param.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,143 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_shared_param.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver shared parameter definitions
+******************************************************************************/
+
+#ifndef R_VDC5_SHARED_PARAM_H
+#define R_VDC5_SHARED_PARAM_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Color space */
+typedef enum {
+    VDC5_COLOR_SPACE_GBR    = 0,        /*!< GBR */
+    VDC5_COLOR_SPACE_YCBCR  = 1         /*!< YCbCr */
+} vdc5_color_space_t;
+
+/*! Resource state */
+typedef enum {
+    VDC5_RESOURCE_ST_INVALID    = 0,    /*!< Invalid */
+    VDC5_RESOURCE_ST_VALID      = 1     /*!< Valid */
+} vdc5_resource_state_t;
+
+/*! Resource type */
+typedef enum {
+    VDC5_RESOURCE_PANEL_CLK = 0,        /*!< Panel clock */
+    VDC5_RESOURCE_VIDEO_IN,             /*!< Input video */
+    VDC5_RESOURCE_VSYNC,                /*!< Vsync signal */
+    VDC5_RESOURCE_LCD_PANEL,            /*!< LCD panel (output video) */
+    VDC5_RESOURCE_LVDS_CLK,             /*!< LVDS PLL clock */
+    VDC5_RESOURCE_NUM
+} vdc5_resource_type_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_ShrdPrmInit(const vdc5_channel_t ch);
+
+void VDC5_ShrdPrmSetInitParam(const vdc5_channel_t ch, const vdc5_init_t * const param);
+void VDC5_ShrdPrmSetTerminate(const vdc5_channel_t ch);
+void VDC5_ShrdPrmSetInputParam(const vdc5_channel_t ch, const vdc5_input_t * const param);
+void VDC5_ShrdPrmSetSyncParam(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+void VDC5_ShrdPrmSetOutputParam(const vdc5_channel_t ch, const vdc5_output_t * const param);
+void VDC5_ShrdPrmSetWriteParam(
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param);
+void VDC5_ShrdPrmSetChgWriteParam(
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param);
+void VDC5_ShrdPrmSetReadParam(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param);
+void VDC5_ShrdPrmSetChgReadParam(
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param);
+void VDC5_ShrdPrmSetCascade(const vdc5_channel_t ch, const vdc5_onoff_t cascade);
+void VDC5_ShrdPrmSetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
+
+vdc5_panel_clksel_t VDC5_ShrdPrmGetPanelClkSel(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetLvdsClkRef(void);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace(const vdc5_channel_t ch);
+vdc5_input_sel_t VDC5_ShrdPrmGetInputSelect(const vdc5_channel_t ch);
+vdc5_res_vs_in_sel_t VDC5_ShrdPrmGetVsInSel(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetCascade(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetUndSel(const vdc5_channel_t ch);
+uint32_t VDC5_ShrdPrmGetBgColor(const vdc5_channel_t ch, const vdc5_color_space_t color_space);
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+void * VDC5_ShrdPrmGetFrBuffBtm(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id);
+vdc5_channel_t VDC5_ShrdPrmGetLvdsCh(void);
+
+void VDC5_ShrdPrmSetResource(
+    const vdc5_channel_t        ch,
+    const vdc5_resource_type_t  rsrc_type,
+    const vdc5_resource_state_t rsrc_state);
+void VDC5_ShrdPrmSetLayerResource(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_resource_state_t rsrc_state);
+vdc5_resource_state_t VDC5_ShrdPrmGetResource(const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type);
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+
+void VDC5_ShrdPrmSetRwProcEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_ShrdPrmSetRwProcDisable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetOirRwProcEnabled(const vdc5_channel_t ch);
+
+
+#endif  /* R_VDC5_SHARED_PARAM_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/include/r_vdec.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,636 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver API definitions
+******************************************************************************/
+
+#ifndef R_VDEC_H
+#define R_VDEC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec_user.h"
+
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! The number of chroma filter TAP coefficient values for Y/C separation */
+#define     VDEC_CHRFIL_TAPCOEF_NUM     (9)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDEC driver */
+typedef enum {
+    VDEC_OK = 0,                /*!< Normal termination */
+    VDEC_ERR_CHANNEL,           /*!< Invalid channel error */
+    VDEC_ERR_PARAM,             /*!< Parameter error */
+    VDEC_ERR_NUM                /*!< The number of the error codes */
+} vdec_error_t;
+
+/*! VDEC channel */
+typedef enum {
+    VDEC_CHANNEL_0 = 0,         /*!< Channel 0 */
+    VDEC_CHANNEL_1,             /*!< Channel 1 */
+    VDEC_CHANNEL_NUM            /*!< The number of channels */
+} vdec_channel_t;
+
+/*! On/Off */
+typedef enum {
+    VDEC_OFF    = 0,            /*!< Off */
+    VDEC_ON     = 1             /*!< On */
+} vdec_onoff_t;
+
+/***********************    For R_VDEC_Initialize       ***********************/
+/*! Input pin control */
+typedef enum {
+    VDEC_ADC_VINSEL_VIN1 = 0,       /*!< VIN1 input */
+    VDEC_ADC_VINSEL_VIN2,           /*!< VIN2 input */
+    VDEC_ADC_VINSEL_NUM             /*!< The number of input pins */
+} vdec_adc_vinsel_t;
+
+/***********************    For R_VDEC_ActivePeriod     ***********************/
+/*! Active image period parameter */
+typedef struct {
+    uint16_t    srcleft;            /*!< Left end of input video signal capturing area */
+    uint16_t    srctop;             /*!< Top end of input video signal capturing area */
+    uint16_t    srcheight;          /*!< Height of input video signal capturing area */
+    uint16_t    srcwidth;           /*!< Width of input video signal capturing area */
+} vdec_active_period_t;
+
+/***********************    For R_VDEC_SyncSeparation   ***********************/
+/*! LPF cutoff frequency before vertical sync separation */
+typedef enum {
+    VDEC_LPF_VSYNC_NONE = 0,        /*!< None */
+    VDEC_LPF_VSYNC_0_94,            /*!< 0.94 MHz */
+    VDEC_LPF_VSYNC_0_67,            /*!< 0.67 MHz */
+    VDEC_LPF_VSYNC_0_54,            /*!< 0.54 MHz */
+    VDEC_LPF_VSYNC_0_47,            /*!< 0.47 MHz */
+    VDEC_LPF_VSYNC_0_34,            /*!< 0.34 MHz */
+    VDEC_LPF_VSYNC_0_27,            /*!< 0.27 MHz */
+    VDEC_LPF_VSYNC_0_23,            /*!< 0.23 MHz */
+    VDEC_LPF_VSYNC_NUM
+} vdec_lpfvsync_t;
+/*! LPF cutoff frequency before horizontal sync separation */
+typedef enum {
+    VDEC_LPF_HSYNC_NONE = 0,        /*!< None */
+    VDEC_LPF_HSYNC_2_15,            /*!< 2.15 MHz */
+    VDEC_LPF_HSYNC_1_88,            /*!< 1.88 MHz */
+    VDEC_LPF_HSYNC_1_34,            /*!< 1.34 MHz */
+    VDEC_LPF_HSYNC_1_07,            /*!< 1.07 MHz */
+    VDEC_LPF_HSYNC_0_94,            /*!< 0.94 MHz */
+    VDEC_LPF_HSYNC_0_67,            /*!< 0.67 MHz */
+    VDEC_LPF_HSYNC_0_54,            /*!< 0.54 MHz */
+    VDEC_LPF_HSYNC_NUM
+} vdec_lpfhsync_t;
+/*! Noise reduction LPF parameter */
+typedef struct {
+    vdec_lpfvsync_t lpfvsync;       /*!< LPF cutoff frequency before vertical sync separation */
+    vdec_lpfhsync_t lpfhsync;       /*!< LPF cutoff frequency before horizontal sync separation */
+} vdec_noise_rd_lpf_t;
+/*! Reference level operation speed control for composite sync separation (for Hsync signal) */
+typedef enum {
+    VDEC_VELOCITY_SHIFT_1 = 0,      /*!< x1 */
+    VDEC_VELOCITY_SHIFT_2,          /*!< x2 */
+    VDEC_VELOCITY_SHIFT_4,          /*!< x4 */
+    VDEC_VELOCITY_SHIFT_8,          /*!< x8 */
+    VDEC_VELOCITY_SHIFT_16,         /*!< x16 */
+    VDEC_VELOCITY_SHIFT_32,         /*!< x32 */
+    VDEC_VELOCITY_SHIFT_64,         /*!< x64 */
+    VDEC_VELOCITY_SHIFT_128,        /*!< x128 */
+    VDEC_VELOCITY_SHIFT_256,        /*!< x256 */
+    VDEC_VELOCITY_SHIFT_NUM
+} vdec_velocityshift_h_t;
+/*! Auto-slice level setting for composite sync separation circuit */
+typedef enum {
+    VDEC_SLICE_MODE_MANULAL = 0,    /*!< Manual setting */
+    VDEC_SLICE_MODE_AUTO_25,        /*!< 25% of sync depth (Auto) */
+    VDEC_SLICE_MODE_AUTO_50,        /*!< 50% of sync depth (Auto) */
+    VDEC_SLICE_MODE_AUTO_75,        /*!< 75% of sync depth (Auto) */
+    VDEC_SLICE_MODE_NUM
+} vdec_slicermode_t;
+/*! Clipping level */
+typedef enum {
+    VDEC_CLIP_LV_512 = 0,           /*!< 512 */
+    VDEC_CLIP_LV_546,               /*!< 546 */
+    VDEC_CLIP_LV_580,               /*!< 580 */
+    VDEC_CLIP_LV_614,               /*!< 614 */
+    VDEC_CLIP_LV_648,               /*!< 648 */
+    VDEC_CLIP_LV_682,               /*!< 682 */
+    VDEC_CLIP_LV_716,               /*!< 716 */
+    VDEC_CLIP_LV_750,               /*!< 750 */
+    VDEC_CLIP_LV_785,               /*!< 785 */
+    VDEC_CLIP_LV_819,               /*!< 819 */
+    VDEC_CLIP_LV_853,               /*!< 853 */
+    VDEC_CLIP_LV_887,               /*!< 887 */
+    VDEC_CLIP_LV_921,               /*!< 921 */
+    VDEC_CLIP_LV_955,               /*!< 955 */
+    VDEC_CLIP_LV_989,               /*!< 989 */
+    VDEC_CLIP_LV_1023,              /*!< 1023 */
+    VDEC_CLIP_LV_NUM
+} vdec_ssclipsel_t;
+/*! Sync slicer */
+typedef struct {
+    vdec_velocityshift_h_t  velocityshift_h;    /*!< Reference level operation speed control for
+                                                     composite sync separation (for Hsync signal) */
+    vdec_slicermode_t       slicermode_h;       /*!< Auto-slice level setting for composite sync separation circuit
+                                                     (for Hsync signal) */
+    vdec_slicermode_t       slicermode_v;       /*!< Auto-slice level setting for composite sync separation circuit
+                                                     (for Vsync signal) */
+    uint16_t                syncmaxduty_h;      /*!< Max ratio of horizontal cycle
+                                                     to horizontal sync signal pulse width */
+    uint16_t                syncminduty_h;      /*!< Min ratio of horizontal cycle
+                                                     to horizontal sync signal pulse width */
+    vdec_ssclipsel_t        ssclipsel;          /*!< Clipping level */
+    uint16_t                csyncslice_h;       /*!< Slice level for composite sync signal separation
+                                                     (for Hsync signal) */
+    uint16_t                syncmaxduty_v;      /*!< Max ratio of horizontal cycle
+                                                     to vertical sync signal pulse width */
+    uint16_t                syncminduty_v;      /*!< Min ratio of horizontal cycle
+                                                     to horizontal sync signal pulse width */
+    vdec_onoff_t            vsyncdelay;         /*!< Delays the separated vertical sync signal
+                                                     for 1/4 horizontal cycle */
+    uint16_t                vsyncslice;         /*!< Threshold for vertical sync separation */
+    uint16_t                csyncslice_v;       /*!< Slice level for composite sync signal separation
+                                                     (for Vsync signal) */
+} vdec_sync_slicer_t;
+/*! Horizontal AFC VBI period operating mode */
+typedef enum {
+    VDEC_HAFCMD_FIX_PHST = 0,               /*!< Loop gain is fixed and phase comparison is stopped
+                                                 during VBI period */
+    VDEC_HAFCMD_FIX_LGRD,                   /*!< Loop gain is fixed and loop gain is reduced during VBI period */
+    VDEC_HAFCMD_AUTO_PHST,                  /*!< Loop gain is automatically controlled and
+                                                 phase comparison is stopped during VBI period */
+    VDEC_HAFCMD_AUTO_LGRD,                  /*!< Loop gain is automatically controlled and loop gain is reduced
+                                                 during VBI period */
+    VDEC_HAFCMD_NUM
+} vdec_hafcmode_t;
+/*! Phase comparator feedback adjust for low sync signal lock stability */
+typedef enum {
+    VDEC_PHDET_DIV_1_1 = 0,                 /*!< 1/1 */
+    VDEC_PHDET_DIV_1_2,                     /*!< 1/2 */
+    VDEC_PHDET_DIV_1_4,                     /*!< 1/4 */
+    VDEC_PHDET_DIV_1_8,                     /*!< 1/8 */
+    VDEC_PHDET_DIV_1_16,                    /*!< 1/16 */
+    VDEC_PHDET_DIV_1_32,                    /*!< 1/32 */
+    VDEC_PHDET_DIV_NUM
+} vdec_phdet_div_t;
+/*! Horizontal AFC parameter */
+typedef struct {
+    uint16_t            hafcgain;           /*!< Horizontal AFC loop gain */
+    uint16_t            hafctyp;            /*!< Horizontal AFC center oscillation frequency */
+    uint16_t            hafcstart;          /*!< Start line of horizontal AFC normal operation
+                                                 (VBI process end line) */
+    vdec_onoff_t        nox2hosc;           /*!< Disable of horizontal AFC double speed detection */
+    uint16_t            hafcmax;            /*!< Maximum oscillation frequency of horizontal AFC */
+    uint16_t            hafcend;            /*!< End line of horizontal AFC normal operation
+                                                 (VBI process start line) */
+    vdec_hafcmode_t     hafcmode;           /*!< Horizontal AFC VBI period operating mode */
+    uint16_t            hafcmin;            /*!< Min oscillation frequency of horizontal AFC */
+    vdec_onoff_t        phdet_fix;          /*!< Forcible or LOWGAIN control */
+    vdec_phdet_div_t    phdet_div;          /*!< Phase comparator feedback adjust for low sync signal lock stability */
+} vdec_horizontal_afc_t;
+/*! Vertical countdown center oscillation frequency */
+typedef enum {
+    VDEC_VCD_FRQ_AUTO = 0,                  /*!< Auto-detection */
+    VDEC_VCD_FRQ_50HZ,                      /*!< 50.00 Hz */
+    VDEC_VCD_FRQ_59_94HZ,                   /*!< 59.94 Hz */
+    VDEC_VCD_FRQ_60HZ,                      /*!< 60.00 Hz */
+    VDEC_VCD_FRQ_NUM
+} vdec_vcddefault_t;
+/*! Vertical count-down parameter */
+typedef struct {
+    vdec_onoff_t        novcd50_;           /*!< Vertical countdown 50-Hz oscillation mode */
+    vdec_onoff_t        novcd60_;           /*!< Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
+    vdec_vcddefault_t   vcddefault;         /*!< Vertical countdown center oscillation frequency */
+    uint16_t            vcdwindow;          /*!< Vertical countdown sync area */
+    uint16_t            vcdoffset;          /*!< Vertical countdown minimum oscillation frequency */
+} vdec_vcount_down_t;
+/*! AGC/PGA parameter */
+typedef struct {
+    vdec_onoff_t    agcmode;                /*!< A/D converter AGC ON/OFF control & PGA switch */
+    vdec_onoff_t    doreduce;               /*!< Manual control of sync signal amplitude detection during VBI period */
+    vdec_onoff_t    noreduce_;              /*!< Control of sync signal amplitude detection during VBI period */
+    uint16_t        agcresponse;            /*!< AGC response speed */
+    uint16_t        agclevel;               /*!< Sync signal reference amplitude */
+    uint16_t        agcprecis;              /*!< AGC gain adjustment accuracy */
+    uint16_t        pga_gain;               /*!< PGA gain */
+} vdec_agc_t;
+/*! Peak luminance value to operate peak limiter */
+typedef enum {
+    VDEC_PEAKLV_LIM_OFF =0,                 /*!< Limiter OFF */
+    VDEC_PEAKLV_1008,                       /*!< 1008 LSB */
+    VDEC_PEAKLV_992,                        /*!< 992 LSB */
+    VDEC_PEAKLV_960,                        /*!< 960 LSB */
+    VDEC_PEAKLV_NUM
+} vdec_peaklevel_t;
+/*! Maximum compression rate of peak limiter */
+typedef enum {
+    VDEC_PEAKRATIO_50 = 0,                  /*!< Compressed up to 50% */
+    VDEC_PEAKRATIO_25,                      /*!< Compressed up to 25% */
+    VDEC_PEAKRATIO_12_5,                    /*!< Compressed up to 12.5% */
+    VDEC_PEAKRATIO_0,                       /*!< Compressed up to 0% */
+    VDEC_PEAKRATIO_NUM
+} vdec_peakratio_t;
+/*! Peak limiter control parameter */
+typedef struct {
+    vdec_peaklevel_t    peaklevel;          /*!< Peak luminance value limited by peak limiter (video signal level) */
+    uint16_t            peakattack;         /*!< Response speed with peak limiter gain decreased */
+    uint16_t            peakrelease;        /*!< Response speed with peak limiter gain increased */
+    vdec_peakratio_t    peakratio;          /*!< Maximum compression rate of peak limiter */
+    uint16_t            maxpeaksamples;     /*!< Allowable number of overflowing pixels */
+} vdec_peak_limiter_t;
+/*! Sync separation parameter */
+typedef struct {
+    vdec_noise_rd_lpf_t   * noise_rd_lpf;       /*!< Noise reduction LPF parameter */
+    vdec_sync_slicer_t    * sync_slicer;        /*!< Auto level control sync slicer parameter */
+    vdec_horizontal_afc_t * horizontal_afc;     /*!< Horizontal AFC parameter */
+    vdec_vcount_down_t    * vcount_down;        /*!< Vertical count-down parameter */
+    vdec_agc_t            * agc;                /*!< AGC/PGA parameter */
+    vdec_peak_limiter_t   * peak_limiter;       /*!< Peak limiter control parameter */
+} vdec_sync_separation_t;
+
+/***********************    For R_VDEC_YcSeparation     ***********************/
+/*! Over-range control parameter */
+typedef struct {
+    uint16_t        radj_o_level0;          /*!< A/D over-threshold level (between levels 0 and 1) */
+    uint16_t        radj_u_level0;          /*!< A/D under-threshold level (between levels 2 and 3) */
+    uint16_t        radj_o_level1;          /*!< A/D over-threshold level (between levels 1 and 2) */
+    uint16_t        radj_u_level1;          /*!< A/D under-threshold level (between levels 1 and 2) */
+    uint16_t        radj_o_level2;          /*!< A/D over-threshold level (between levels 2 and 3) */
+    uint16_t        radj_u_level2;          /*!< A/D under-threshold level (between levels 0 and 1) */
+    vdec_onoff_t    ucmp_sw;                /*!< Over-range detection enable */
+    vdec_onoff_t    dcmp_sw;                /*!< Under-range detection enable */
+    vdec_onoff_t    hwide_sw;               /*!< Horizontal enlargement of over/under-range level */
+} vdec_over_range_t;
+/*! Latter-stage BPF select */
+typedef enum {
+    VDEC_LSTG_BPFSEL_BYPASS     = 0,        /*!< Bypass */
+    VDEC_LSTG_BPFSEL_17TAP      = 1         /*!< 17 TAP */
+} vdec_lstg_bpfsel_t;
+/*! Former-stage BPF select */
+typedef enum {
+    VDEC_FSTG_BPFSEL_17TAP      = 0,        /*!< 17 TAP */
+    VDEC_FSTG_BPFSEL_9TAP       = 1         /*!< 9 TAP */
+} vdec_fstg_bpfsel_t;
+/*! Horizontal filter and horizontal/vertical filter bandwidth switch signal */
+typedef enum {
+    VDEC_HFIL_TAP_SEL_17TAP     = 0,        /*!< 17 TAP */
+    VDEC_HFIL_TAP_SEL_9TAP      = 1         /*!< 9 TAP */
+} vdec_hfil_tap_sel_t;
+/*! Mixing ratio of signals after passing filters */
+typedef enum {
+    VDEC_FILMIX_RATIO_0 = 0,            /*!< 0% */
+    VDEC_FILMIX_RATIO_12_5,             /*!< 12.5% */
+    VDEC_FILMIX_RATIO_25,               /*!< 25% */
+    VDEC_FILMIX_RATIO_37_5,             /*!< 37.5% */
+    VDEC_FILMIX_RATIO_50,               /*!< 50% */
+    VDEC_FILMIX_RATIO_62_5,             /*!< 62.5% */
+    VDEC_FILMIX_RATIO_75,               /*!< 75% */
+    VDEC_FILMIX_RATIO_87_5,             /*!< 87.5% */
+    VDEC_FILMIX_RATIO_100,              /*!< 100% */
+    VDEC_FILMIX_RATIO_NUM
+} vdec_filmix_ratio_t;
+/*! Two-dimensional cascade/TAKE-OFF filter mode select */
+typedef enum {
+    VDEC_2DFIL_MDSEL_BYPASS = 0,        /*!< Bypass */
+    VDEC_2DFIL_MDSEL_CASCADE,           /*!< Cascade filter */
+    VDEC_2DFIL_MDSEL_TAKEOFF,           /*!< TAKE-OFF filter */
+    VDEC_2DFIL_MDSEL_NUM
+} vdec_2dfil_mdsel_t;
+/*! Two-dimensional cascade filter select */
+typedef enum {
+    VDEC_2D_FIL_SEL_BYPASS      = 0,        /*!< Bypass */
+    VDEC_2D_FIL_SEL_17TAP       = 1         /*!< 17 TAP */
+} vdec_2d_fil_sel_t;
+/*! Y/C separation control parameter */
+typedef struct {
+    uint16_t            k15;            /*!< Two-dimensional Y/C separation filter select coefficient, K15 */
+    uint16_t            k13;            /*!< Two-dimensional Y/C separation filter select coefficient, K13 */
+    uint16_t            k11;            /*!< Two-dimensional Y/C separation filter select coefficient, K11 */
+    uint16_t            k16;            /*!< Two-dimensional Y/C separation filter select coefficient, K16 */
+    uint16_t            k14;            /*!< Two-dimensional Y/C separation filter select coefficient, K14 */
+    uint16_t            k12;            /*!< Two-dimensional Y/C separation filter select coefficient, K12 */
+    uint16_t            k22a;           /*!< Two-dimensional Y/C separation filter select coefficient, K22A */
+    uint16_t            k21a;           /*!< Two-dimensional Y/C separation filter select coefficient, K21A */
+    uint16_t            k22b;           /*!< Two-dimensional Y/C separation filter select coefficient, K22B */
+    uint16_t            k21b;           /*!< Two-dimensional Y/C separation filter select coefficient, K21B */
+    uint16_t            k23b;           /*!< Two-dimensional Y/C separation filter select coefficient, K23B */
+    uint16_t            k23a;           /*!< Two-dimensional Y/C separation filter select coefficient, K23A */
+    uint16_t            k24;            /*!< Two-dimensional Y/C separation filter select coefficient, K24 */
+    vdec_lstg_bpfsel_t  hbpf_narrow;    /*!< Latter-stage horizontal BPF select */
+    vdec_lstg_bpfsel_t  hvbpf_narrow;   /*!< Latter-stage horizontal/vertical BPF select */
+    vdec_fstg_bpfsel_t  hbpf1_9tap_on;  /*!< Former-stage horizontal BPF select */
+    vdec_fstg_bpfsel_t  hvbpf1_9tap_on; /*!< Former-stage horizontal/vertical BPF select */
+    vdec_hfil_tap_sel_t hfil_tap_sel;   /*!< Horizontal filter and horizontal/vertical filter
+                                             bandwidth switch signal */
+    vdec_onoff_t        det2_on;        /*!< Two-dimensional filter mixing select */
+    vdec_filmix_ratio_t hsel_mix_y;     /*!< Mixing ratio of signal after passing horizontal filter
+                                             to signal after passing former-stage horizontal filter */
+    vdec_filmix_ratio_t vsel_mix_y;     /*!< Mixing ratio of signal after passing vertical filter
+                                             to signal after passing former-stage horizontal/vertical filter */
+    vdec_filmix_ratio_t hvsel_mix_y;    /*!< Mixing ratio of signal after passing horizontal/vertical filter
+                                             to signal after passing former-stage horizontal/vertical filter */
+    uint16_t            v_y_level;      /*!< Vertical luminance detection level for correlation detection filter */
+    vdec_filmix_ratio_t det2_mix_c;     /*!< Mixing ratio of C signal after passing horizontal/vertical adaptive filter
+                                             to signal after passing correlation detection filter */
+    vdec_filmix_ratio_t det2_mix_y;     /*!< Mixing ratio of C signal for Y generation after passing
+                                             horizontal/vertical adaptive filter to signal
+                                             after passing correlation detection filter */
+    vdec_2dfil_mdsel_t  fil2_mode_2d;   /*!< Two-dimensional cascade/TAKE-OFF filter mode select */
+    vdec_2d_fil_sel_t   fil2_narrow_2d; /*!< Two-dimensional cascade filter select */
+} vdec_yc_sep_ctrl_t;
+/*! Chroma filter TAP coefficient for Y/C separation */
+typedef struct {
+    uint16_t    fil2_2d_f[VDEC_CHRFIL_TAPCOEF_NUM];     /*!< Chroma filter TAP coefficient 0 to 8 */
+} vdec_chrfil_tap_t;
+/*! Y/C separation parameter */
+typedef struct {
+    vdec_over_range_t         * over_range;     /*!< Over-range control parameter */
+    vdec_yc_sep_ctrl_t        * yc_sep_ctrl;    /*!< Y/C separation control parameter */
+    const vdec_chrfil_tap_t   * fil2_2d_wa;     /*!< Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF
+                                                     filter TAP coefficient */
+    const vdec_chrfil_tap_t * fil2_2d_wb;       /*!< Two-dimensional cascade broadband (SECAM-DB) filter
+                                                     TAP coefficient */
+    const vdec_chrfil_tap_t * fil2_2d_na;       /*!< Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter
+                                                     TAP coefficient */
+    const vdec_chrfil_tap_t * fil2_2d_nb;       /*!< Two-dimensional cascade narrowband (SECAMDB) filter
+                                                     TAP coefficient */
+} vdec_yc_separation_t;
+
+/***********************    For R_VDEC_ChromaDecoding   ***********************/
+/*! Color system */
+typedef enum {
+    VDEC_COL_SYS_NTSC = 0,                  /*!< NTSC */
+    VDEC_COL_SYS_PAL,                       /*!< PAL */
+    VDEC_COL_SYS_SECAM,                     /*!< SECAM */
+    VDEC_COL_SYS_NON,                       /*!< Not specified/undetectable */
+    VDEC_COL_SYS_NUM                        /*!< The number of color system settings */
+} vdec_color_sys_t;
+/*! Averaging processing for pre-demodulated line */
+typedef enum {
+    VDEC_DEMOD_MD_NO    = 0,                /*!< No processing */
+    VDEC_DEMOD_MD_PAL   = 2                 /*!< For PAL */
+} vdec_demodmode_t;
+/*! Color system detection parameter */
+typedef struct {
+    vdec_color_sys_t    defaultsys;         /*!< Default color system */
+    vdec_onoff_t        nontsc358_;         /*!< NTSC-M detection control */
+    vdec_onoff_t        nontsc443_;         /*!< NTSC-4.43 detection control */
+    vdec_onoff_t        nopalm_;            /*!< PAL-M detection control */
+    vdec_onoff_t        nopaln_;            /*!< PAL-N detection control */
+    vdec_onoff_t        nopal443_;          /*!< PAL-B, G, H, I, D detection control */
+    vdec_onoff_t        nosecam_;           /*!< SECAM detection control */
+    uint16_t            lumadelay;          /*!< Luminance signal delay adjustment */
+    vdec_onoff_t        chromalpf;          /*!< LPF for demodulated chroma */
+    vdec_demodmode_t    demodmode;          /*!< Averaging processing for pre-demodulated line */
+} vdec_chrmdec_ctrl_t;
+/*! Burst lock PLL lock range */
+typedef enum {
+    VDEC_LOCK_RANGE_400HZ = 0,              /*!< +-400 Hz */
+    VDEC_LOCK_RANGE_800HZ,                  /*!< +-800 Hz */
+    VDEC_LOCK_RANGE_1200HZ,                 /*!< +-1200 Hz */
+    VDEC_LOCK_RANGE_1600HZ,                 /*!< +-1600 Hz */
+    VDEC_LOCK_RANGE_NUM
+} vdec_lockrange_t;
+/*! BCO parameter */
+typedef struct {
+    vdec_lockrange_t    lockrange;          /*!< Burst lock PLL lock range */
+    uint16_t            loopgain;           /*!< Burst lock PLL loop gain */
+    uint16_t            locklimit;          /*!< Level for burst lock PLL to re-search free-run frequency */
+    uint16_t            bgpcheck;           /*!< burst gate pulse position check */
+    uint16_t            bgpwidth;           /*!< burst gate pulse width */
+    uint16_t            bgpstart;           /*!< burst gate pulse start position */
+} vdec_burst_lock_t;
+/*! ACC operating mode */
+typedef enum {
+    VDEC_ACC_MD_AUTO    = 0,                /*!< Auto gain */
+    VDEC_ACC_MD_MANUAL  = 1                 /*!< Manual gain */
+} vdec_accmode_t;
+/*! Maximum ACC gain */
+typedef enum {
+    VDEC_ACC_MAX_GAIN_6 = 0,                /*!< 6 times */
+    VDEC_ACC_MAX_GAIN_8,                    /*!< 8 times */
+    VDEC_ACC_MAX_GAIN_12,                   /*!< 12 times */
+    VDEC_ACC_MAX_GAIN_16,                   /*!< 16 times */
+    VDEC_ACC_MAX_GAIN_NUM
+} vdec_accmaxgain_t;
+/*! Chroma manual gain (sub) */
+typedef enum {
+    VDEC_CHRM_SB_GAIN_1 = 0,                /*!< 1 time */
+    VDEC_CHRM_SB_GAIN_2,                    /*!< 2 times */
+    VDEC_CHRM_SB_GAIN_4,                    /*!< 4 times */
+    VDEC_CHRM_SB_GAIN_8,                    /*!< 8 times */
+    VDEC_CHRM_SB_GAIN_NUM
+} vdec_chrm_subgain_t;
+/*! ACC and color killer parameter */
+typedef struct {
+    vdec_accmode_t      accmode;            /*!< ACC operating mode */
+    vdec_accmaxgain_t   accmaxgain;         /*!< Maximum ACC Gain */
+    uint16_t            acclevel;           /*!< ACC reference color burst amplitude */
+    vdec_chrm_subgain_t chromasubgain;      /*!< Chroma manual gain (sub) */
+    uint16_t            chromamaingain;     /*!< Chroma manual gain (main) */
+    uint16_t            accresponse;        /*!< ACC response speed */
+    uint16_t            accprecis;          /*!< ACC gain adjustment accuracy */
+    vdec_onoff_t        killermode;         /*!< Forced color killer mode ON/OFF */
+    uint16_t            killerlevel;        /*!< Color killer operation start point */
+    uint16_t            killeroffset;       /*!< Color killer offset */
+} vdec_acc_t;
+/*! TINT correction/R-Y axis correction parameter (only valid for NTSC/PAL) */
+typedef struct {
+    uint16_t    tintsub;                    /*!< Fine adjustment of R-Y demodulation axis */
+    uint16_t    tintmain;                   /*!< Hue adjustment level */
+} vdec_tint_ry_t;
+/*! Chroma decoding parameter */
+typedef struct {
+    vdec_chrmdec_ctrl_t   * chrmdec_ctrl;   /*!< Color system detection parameter */
+    vdec_burst_lock_t     * burst_lock;     /*!< BCO parameter */
+    vdec_acc_t            * acc;            /*!< ACC and color killer parameter */
+    vdec_tint_ry_t        * tint_ry;        /*!< TINT correction/R-Y axis correction parameter */
+} vdec_chroma_decoding_t;
+
+/***********************    For R_VDEC_DigitalClamp     ***********************/
+/*! Clamp level setting mode */
+typedef enum {
+    VDEC_DCPMODE_MANUAL = 0,                /*!< Manual clamp level setting */
+    VDEC_DCPMODE_AUTO   = 1                 /*!< Auto clamp level setting */
+} vdec_dcpmode_t;
+/*! Pedestal clamp parameter */
+typedef struct {
+    vdec_dcpmode_t      dcpmode_y;          /*!< Clamp level setting mode (Y signal) */
+    uint16_t            blanklevel_y;       /*!< Clamp offset level (Y signal) */
+    uint16_t            dcppos_y;           /*!< Digital clamp pulse horizontal start position (Y signal) */
+} vdec_pedestal_clamp_t;
+/*! Center clamp parameter */
+typedef struct {
+    vdec_dcpmode_t      dcpmode_c;          /*!< Clamp level setting mode (Cb/Cr signal) */
+    uint16_t            blanklevel_cb;      /*!< Clamp offset level (Cb signal) */
+    uint16_t            blanklevel_cr;      /*!< Clamp offset level (Cr signal) */
+    uint16_t            dcppos_c;           /*!< Digital clamp pulse horizontal start position (Cb/Cr signal) */
+} vdec_center_clamp_t;
+/*! Video signal for autocorrelation function */
+typedef enum {
+    VDEC_ACFINPUT_Y = 0,                    /*!< Y signal */
+    VDEC_ACFINPUT_CB,                       /*!< Cb signal */
+    VDEC_ACFINPUT_CR,                       /*!< Cr signal */
+    VDEC_ACFINPUT_NUM
+} vdec_acfinput_t;
+/*! Noise detection parameter */
+typedef struct {
+    vdec_acfinput_t     acfinput;           /*!< Video signal for autocorrelation function */
+    uint16_t            acflagtime;         /*!< Delay time for autocorrelation function calculation */
+    uint16_t            acffilter;          /*!< Smoothing parameter of autocorrelation function data */
+} vdec_noise_det_t;
+/*! Digital clamp parameter */
+typedef struct {
+    vdec_onoff_t            dcpcheck;       /*!< Digital clamp pulse position check */
+    uint16_t                dcpresponse;    /*!< Digital clamp response speed */
+    uint16_t                dcpstart;       /*!< Digital clamp start line */
+    uint16_t                dcpend;         /*!< Digital clamp end line */
+    uint16_t                dcpwidth;       /*!< Digital clamp pulse width */
+    vdec_pedestal_clamp_t * pedestal_clamp; /*!< Pedestal clamp parameter */
+    vdec_center_clamp_t   * center_clamp;   /*!< Center clamp parameter */
+    vdec_noise_det_t      * noise_det;      /*!< Noise detection parameter */
+} vdec_degital_clamp_t;
+
+/***********************    For R_VDEC_Output           ***********************/
+/*! Output adjustment parameter */
+typedef struct {
+    uint16_t    y_gain2;                /*!< Y signal gain coefficient */
+    uint16_t    cb_gain2;               /*!< Cb signal gain coefficient */
+    uint16_t    cr_gain2;               /*!< Cr signal gain coefficient */
+} vdec_output_t;
+
+/***********************    For R_VDEC_Query            ***********************/
+/*! Answer */
+typedef enum {
+    VDEC_NO         = 0,            /*!< No */
+    VDEC_YES        = 1             /*!< Yes */
+} vdec_answer_t;
+/*! Lock state */
+typedef enum {
+    VDEC_UNLOCK     = 0,            /*!< Unlocked */
+    VDEC_LOCK       = 1             /*!< Locked */
+} vdec_lock_t;
+/*! Speed detection result */
+typedef enum {
+    VDEC_FHMD_NORMAL        = 0,    /*!< Normal speed */
+    VDEC_FHMD_MULTIPLIED    = 1     /*!< Multiplied speed */
+} vdec_fhmode_t;
+/*! Vertical countdown oscillation mode */
+typedef enum {
+    VDEC_FVMD_50HZ  = 0,            /*!< 50 Hz */
+    VDEC_FVMD_60HZ  = 1             /*!< 60 Hz */
+} vdec_fvmode_t;
+/*! Color sub-carrier frequency detection result */
+typedef enum {
+    VDEC_FSCMD_3_58     = 0,        /*!< 3.58 MHz */
+    VDEC_FSCMD_4_43     = 1         /*!< 4.43 MHz */
+} vdec_fscmode_t;
+/*! Sync separation parameters (for query) */
+typedef struct {
+    vdec_lock_t     fhlock;         /*!< Horizontal AFC lock detection result */
+    vdec_answer_t   isnoisy;        /*!< Detection result of low S/N signal by sync separation */
+    vdec_fhmode_t   fhmode;         /*!< Speed detection result */
+    vdec_answer_t   nosignal_;      /*!< No-signal detection result */
+    vdec_lock_t     fvlock;         /*!< Vertical countdown lock detection result */
+    vdec_fvmode_t   fvmode;         /*!< Vertical countdown oscillation mode */
+    vdec_answer_t   interlaced;     /*!< Interlace detection result */
+    uint16_t        fvcount;        /*!< Vertical cycle measurement result */
+    uint32_t        fhcount;        /*!< Horizontal AFC oscillation cycle */
+    vdec_answer_t   isreduced;      /*!< Sync amplitude detection result during VBI period */
+    uint16_t        syncdepth;      /*!< Sync pulse amplitude detection result */
+} vdec_q_sync_sep_t;
+/*! AGC parameters (for query) */
+typedef struct {
+    uint16_t    highsamples;        /*!< Number of pixels which have larger luminance value than peak luminance
+                                         limited by peak limiter */
+    uint16_t    peaksamples;        /*!< Number of overflowing pixels */
+    uint16_t    agcconverge;        /*!< AGC convergence detection result */
+    uint16_t    agcgain;            /*!< Current AGC gain value */
+} vdec_q_agc_t;
+/*! Chroma decoding parameters (for query) */
+typedef struct {
+    vdec_color_sys_t    colorsys;   /*!< Color system detection result */
+    vdec_fscmode_t      fscmode;    /*!< Color sub-carrier frequency detection result */
+    vdec_lock_t         fsclock;    /*!< Burst lock PLL lock state detection result */
+    vdec_answer_t       noburst_;   /*!< Color burst detection result */
+    vdec_chrm_subgain_t accsubgain; /*!< Current ACC gain value (sub) */
+    uint16_t            accmaingain;/*!< Current ACC gain value (main) */
+    vdec_answer_t       issecam;    /*!< SECAM detection result */
+    vdec_answer_t       ispal;      /*!< PAL detection result */
+    vdec_answer_t       isntsc;     /*!< NTSC detection result */
+    uint16_t            locklevel;  /*!< Low S/N signal detection result by burst lock PLL */
+} vdec_q_chroma_dec_t;
+/*! Digital clamp parameters (for query) */
+typedef struct {
+    uint16_t    clamplevel_cb;      /*!< Digital clamp subtraction value (Cb signal) */
+    uint16_t    clamplevel_y;       /*!< Digital clamp subtraction value (Y signal) */
+    uint16_t    clamplevel_cr;      /*!< Digital clamp subtraction value (Cr signal) */
+    uint16_t    acfstrength;        /*!< Noise autocorrelation strength at digital clamp pulse position */
+} vdec_q_digital_clamp_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdec_error_t R_VDEC_Initialize(
+    const vdec_channel_t    ch,
+    const vdec_adc_vinsel_t vinsel,
+    void           (* const init_func)(uint32_t),
+    const uint32_t          user_num);
+vdec_error_t R_VDEC_Terminate(const vdec_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdec_error_t R_VDEC_ActivePeriod(const vdec_channel_t ch, const vdec_active_period_t * const param);
+vdec_error_t R_VDEC_SyncSeparation(const vdec_channel_t ch, const vdec_sync_separation_t * const param);
+vdec_error_t R_VDEC_YcSeparation(const vdec_channel_t ch, const vdec_yc_separation_t * const param);
+vdec_error_t R_VDEC_ChromaDecoding(const vdec_channel_t ch, const vdec_chroma_decoding_t * const param);
+vdec_error_t R_VDEC_DigitalClamp(const vdec_channel_t ch, const vdec_degital_clamp_t * const param);
+vdec_error_t R_VDEC_Output(const vdec_channel_t ch, const vdec_output_t * const param);
+vdec_error_t R_VDEC_Query(
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp);
+
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_VDEC_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/include/r_vdec_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,49 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_user.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver user-defined header
+******************************************************************************/
+
+#ifndef R_VDEC_USER_H
+#define R_VDEC_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Compilation switch to enable parameter check functions<br>
+    If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_VDEC_CHECK_PARAMETERS
+
+
+#endif  /* R_VDEC_USER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/src/r_vdec.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,345 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_register.h"
+#include    "r_vdec_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       VDEC driver initialization
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Calls the user-defined function specified in init_func.
+ *              - Sets up the input pins.
+ * @param[in]   ch                      : Channel
+ * @param[in]   vinsel                  : Input pin control
+ *                                        - VDEC_ADC_VINSEL_VIN1
+ *                                        - VDEC_ADC_VINSEL_VIN2
+ * @param[in]   init_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Initialize (
+    const vdec_channel_t    ch,
+    const vdec_adc_vinsel_t vinsel,
+    void           (* const init_func)(uint32_t),
+    const uint32_t          user_num)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_InitializeCheckParam(vinsel);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        /* User-defined function */
+        if (init_func != 0) {
+            init_func(user_num);
+        }
+        VDEC_Initialize(ch, vinsel);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Initialize() */
+
+/**************************************************************************//**
+ * @brief       VDEC driver termination
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Calls the user-defined function specified in quit_func.
+ * @param[in]   ch                      : Channel
+ * @param[in]   quit_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Terminate (const vdec_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        /* User-defined function */
+        if (quit_func != 0) {
+            quit_func(user_num);
+        }
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Active image period setup
+ *
+ *              Description:<br>
+ *              This function configures the active image period.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Active image period parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_ActivePeriodCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_ActivePeriod(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_ActivePeriod() */
+
+/**************************************************************************//**
+ * @brief       Sync separation processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the noise reduction LPF.
+ *              - Configures the auto level control sync slicer.
+ *              - Configures the horizontal AFC.
+ *              - Configures the vertical count-down.
+ *              - Configures the AGC.
+ *              - Configures the peak limiter control.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_SyncSeparationCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_SyncSeparation(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_SyncSeparation() */
+
+/**************************************************************************//**
+ * @brief       Y/C separation processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the over-range control.
+ *              - Configures the Y/C separation control.
+ *              - Configures the chroma filter TAP coefficients for Y/C separation.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Y/C separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_YcSeparationCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_YcSeparation(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_YcSeparation() */
+
+/**************************************************************************//**
+ * @brief       Chroma decoding processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the color system detection.
+ *              - Configures the BCO.
+ *              - Configures the ACC/color killer.
+ *              - Configures the TINT correction/R-Y axis correction.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Chroma decoding parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_ChromaDecodingCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_ChromaDecoding(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_ChromaDecoding() */
+
+/**************************************************************************//**
+ * @brief       Digital clamp processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the digital clamp control.
+ *              - Configures the center clamp.
+ *              - Configures the pedestal clamp.
+ *              - Configures the noise detection control.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Digital clamp parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_DigitalClampCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_DigitalClamp(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief       Output adjustment processing
+ *
+ *              Description:<br>
+ *              This function makes settings for output adjustment.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Output adjustment parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_OutputCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_Output(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Output() */
+
+/**************************************************************************//**
+ * @brief       VDEC information acquisition processing
+ *
+ *              Description:<br>
+ *              This gets the parameters of the VDEC modules. The parameters that can be obtained are listed below.
+ *              - Sync separation parameters
+ *              - AGC parameters
+ *              - Chroma decoding parameters
+ *              - Digital clamp parameters
+ * @param[in]   ch                      : Channel
+ * @param[out]  q_sync_sep              : Pointer to the place where the sync separation parameters are stored.
+ * @param[out]  q_agc                   : Pointer to the place where the AGC parameters are stored.
+ * @param[out]  q_chroma_dec            : Pointer to the place where the chroma decoding parameters are stored.
+ * @param[out]  q_digital_clamp         : Pointer to the place where the digital clamp parameters are stored.
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Query (
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_Query(ch, q_sync_sep, q_agc, q_chroma_dec, q_digital_clamp);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Query() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/src/r_vdec_check_parameter.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,983 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_check_parameter.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_check_parameter.h"
+
+
+#ifdef      R_VDEC_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDEC_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDEC_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDEC_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDEC_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDEC_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDEC_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDEC_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDEC_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDEC_CPARA_RANGE_0X000001FF (0x000001FFu)
+#define VDEC_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDEC_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDEC_CPARA_RANGE_0X00001FFF (0x00001FFFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdec_error_t NoiseReductionLPFCheckParam(const vdec_noise_rd_lpf_t * const p_noise_rd_lpf);
+static vdec_error_t SyncSlicerCheckParam(const vdec_sync_slicer_t * const p_sync_slicer);
+static vdec_error_t HorizontalAFCCheckParam(const vdec_horizontal_afc_t * const p_horizontal_afc);
+static vdec_error_t VerticalCountdownCheckParam(const vdec_vcount_down_t * const p_vcount_down);
+static vdec_error_t AgcPgaCheckParam(const vdec_agc_t * const p_agc);
+static vdec_error_t PeakLimiterControlCheckParam(const vdec_peak_limiter_t * const p_peak_limiter);
+static vdec_error_t OverRangeControlCheckParam(const vdec_over_range_t * const p_over_range);
+static vdec_error_t YcSeparationControlCheckParam(const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl);
+static vdec_error_t FilterTAPsCoefficientCheckParam(const vdec_chrfil_tap_t * const fil2_2d);
+static vdec_error_t ChromaDecodingControlCheckParam(const vdec_chrmdec_ctrl_t * const p_chrmdec_ctrl);
+static vdec_error_t BurstLockCheckParam(const vdec_burst_lock_t * const p_burst_lock);
+static vdec_error_t AccColorKillerCheckParam(const vdec_acc_t * const p_acc);
+
+
+/**************************************************************************//**
+ * @brief       Checks on input pin control
+ * @param[in]   vinsel                  : Input pin control
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_InitializeCheckParam (const vdec_adc_vinsel_t vinsel)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if ((vinsel != VDEC_ADC_VINSEL_VIN1) && (vinsel != VDEC_ADC_VINSEL_VIN2)) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_InitializeCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on active image period parameter
+ * @param[in]   param                   : Active image period parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_ActivePeriodCheckParam (const vdec_active_period_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Left end of input video signal capturing area */
+    if (((uint32_t)param->srcleft & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Top end of input video signal capturing area */
+    if (((uint32_t)param->srctop & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Height of input video signal capturing area */
+    if (((uint32_t)param->srcheight & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Width of input video signal capturing area */
+    if (((uint32_t)param->srcwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X000007FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_ActivePeriodCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on sync separation parameter
+ * @param[in]   param                   : Sync separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_SyncSeparationCheckParam (const vdec_sync_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Noise reduction LPF */
+    vdec_error = NoiseReductionLPFCheckParam(param->noise_rd_lpf);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Sync slicer */
+    vdec_error = SyncSlicerCheckParam(param->sync_slicer);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Horizontal AFC */
+    vdec_error = HorizontalAFCCheckParam(param->horizontal_afc);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Vertical countdown */
+    vdec_error = VerticalCountdownCheckParam(param->vcount_down);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* AGC / PGA */
+    vdec_error = AgcPgaCheckParam(param->agc);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Peak limiter control */
+    vdec_error = PeakLimiterControlCheckParam(param->peak_limiter);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_SyncSeparationCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on Y/C separation parameter
+ * @param[in]   param                   : Y/C separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_YcSeparationCheckParam (const vdec_yc_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Over-range control */
+    vdec_error = OverRangeControlCheckParam(param->over_range);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Y/C separation control */
+    vdec_error = YcSeparationControlCheckParam(param->yc_sep_ctrl);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_wa);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_wb);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_na);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_nb);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_YcSeparationCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma decoding parameter
+ * @param[in]   param                   : Chroma decoding parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_ChromaDecodingCheckParam (const vdec_chroma_decoding_t * const param)
+{
+    vdec_tint_ry_t    * p_tint_ry;
+    vdec_error_t        vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Chroma decoding control */
+    vdec_error = ChromaDecodingControlCheckParam(param->chrmdec_ctrl);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Burst lock */
+    vdec_error = BurstLockCheckParam(param->burst_lock);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* ACC/color killer */
+    vdec_error = AccColorKillerCheckParam(param->acc);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* TINT/R-Y axis correction (only valid for NTSC/PAL) */
+    p_tint_ry = param->tint_ry;
+    if (p_tint_ry != NULL) {
+        /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
+        if ((((uint32_t)p_tint_ry->tintsub & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_tint_ry->tintmain & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_ChromaDecodingCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on digital clamp parameter
+ * @param[in]   param                   : Digital clamp parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_DigitalClampCheckParam (const vdec_degital_clamp_t * const param)
+{
+    vdec_pedestal_clamp_t     * p_pedestal_clamp;
+    vdec_center_clamp_t       * p_center_clamp;
+    vdec_noise_det_t          * p_noise_det;
+    vdec_error_t                vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp response speed */
+    if (((uint32_t)param->dcpresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000007)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp start line (in 1-line units) */
+    if (((uint32_t)param->dcpstart & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp end line (in 1-line units) */
+    if (((uint32_t)param->dcpend & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp pulse width */
+    if (((uint32_t)param->dcpwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X0000007F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+
+    /* Pedestal clamp */
+    p_pedestal_clamp = param->pedestal_clamp;
+    if (p_pedestal_clamp != NULL) {
+        /* Clamp offset level (Y signal) */
+        if (((uint32_t)p_pedestal_clamp->blanklevel_y & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Digital clamp pulse horizontal start position (Y signal) */
+        if (((uint32_t)p_pedestal_clamp->dcppos_y & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+    /* Center clamp */
+    p_center_clamp = param->center_clamp;
+    if (p_center_clamp != NULL) {
+        /* Clamp offset level (Cb signal) */
+        if (((uint32_t)p_center_clamp->blanklevel_cb & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Clamp offset level (Cr signal) */
+        if (((uint32_t)p_center_clamp->blanklevel_cr & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
+        if (((uint32_t)p_center_clamp->dcppos_c & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+    /* Noise detection */
+    p_noise_det = param->noise_det;
+    if (p_noise_det != NULL) {
+        /* Video signal for autocorrelation function */
+        if (p_noise_det->acfinput >= VDEC_ACFINPUT_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Delay time for autocorrelation function calculation */
+        if (((uint32_t)p_noise_det->acflagtime & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Smoothing parameter of autocorrelation function data */
+        if (((uint32_t)p_noise_det->acffilter & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_DigitalClampCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on output adjustment parameter
+ * @param[in]   param                   : Output adjustment parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_OutputCheckParam (const vdec_output_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Y signal gain coefficient */
+    if (((uint32_t)param->y_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Cb signal gain coefficient */
+    if (((uint32_t)param->cb_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Cr signal gain coefficient */
+    if (((uint32_t)param->cr_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_OutputCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on noise reduction LPF parameter
+ * @param[in]   p_noise_rd_lpf          : Noise reduction LPF parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t NoiseReductionLPFCheckParam (const vdec_noise_rd_lpf_t * const p_noise_rd_lpf)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Noise reduction LPF */
+    if (p_noise_rd_lpf != NULL) {
+        /* LPF cutoff frequency before vertical sync separation */
+        if (p_noise_rd_lpf->lpfvsync >= VDEC_LPF_VSYNC_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* LPF cutoff frequency before horizontal sync separation */
+        if (p_noise_rd_lpf->lpfhsync >= VDEC_LPF_HSYNC_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function NoiseReductionLPFCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on auto level control sync slicer parameter
+ * @param[in]   p_sync_slicer           : Auto level control sync slicer parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t SyncSlicerCheckParam (const vdec_sync_slicer_t * const p_sync_slicer)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Sync slicer */
+    if (p_sync_slicer != NULL) {
+        /* Reference level operation speed control for composite sync separation (for Hsync signal) */
+        if (p_sync_slicer->velocityshift_h >= VDEC_VELOCITY_SHIFT_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Auto-slice level setting for composite sync separator circuit (for Hsync signal) */
+        if (p_sync_slicer->slicermode_h >= VDEC_SLICE_MODE_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
+        if (p_sync_slicer->slicermode_v >= VDEC_SLICE_MODE_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
+        if ((((uint32_t)p_sync_slicer->syncmaxduty_h & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_sync_slicer->syncminduty_h & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Clipping level */
+        if (p_sync_slicer->ssclipsel >= VDEC_CLIP_LV_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Slice level for composite sync signal separation (for Hsync signal) */
+        if (((uint32_t)p_sync_slicer->csyncslice_h & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
+        if ((((uint32_t)p_sync_slicer->syncmaxduty_v & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_sync_slicer->syncminduty_v & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Threshold for vertical sync separation */
+        if (((uint32_t)p_sync_slicer->vsyncslice & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Slice level for composite sync signal separation (for Vsync signal) */
+        if (((uint32_t)p_sync_slicer->csyncslice_v & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function SyncSlicerCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on horizontal AFC parameter
+ * @param[in]   p_horizontal_afc        : Horizontal AFC parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t HorizontalAFCCheckParam (const vdec_horizontal_afc_t * const p_horizontal_afc)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Horizontal AFC */
+    if (p_horizontal_afc != NULL) {
+        /* Horizontal AFC loop gain */
+        if (((uint32_t)p_horizontal_afc->hafcgain & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Horizontal AFC center oscillation frequency */
+        if (((uint32_t)p_horizontal_afc->hafcgain & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Start line of horizontal AFC normal operation */
+        if (((uint32_t)p_horizontal_afc->hafcstart & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Maximum oscillation frequency of horizontal AFC */
+        if (((uint32_t)p_horizontal_afc->hafcmax & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* End line of horizontal AFC normal operation */
+        if (((uint32_t)p_horizontal_afc->hafcend & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Horizontal AFC VBI period operating mode */
+        if (p_horizontal_afc->hafcmode >= VDEC_HAFCMD_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Min oscillation frequency of horizontal AFC */
+        if (((uint32_t)p_horizontal_afc->hafcmin & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Phase comparator feedback adjust for low sync signal lock stability */
+        if (p_horizontal_afc->phdet_div >= VDEC_PHDET_DIV_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function HorizontalAFCCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on vertical count-down parameter
+ * @param[in]   p_vcount_down           : Vertical count-down parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t VerticalCountdownCheckParam (const vdec_vcount_down_t * const p_vcount_down)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Vertical countdown */
+    if (p_vcount_down != NULL) {
+        /* Vertical countdown center oscillation frequency */
+        if (p_vcount_down->vcddefault >= VDEC_VCD_FRQ_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Vertical countdown sync area */
+        if (((uint32_t)p_vcount_down->vcdwindow & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Vertical countdown minimum oscillation frequency */
+        if (((uint32_t)p_vcount_down->vcdoffset & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function VerticalCountdownCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on AGC/PGA parameter
+ * @param[in]   p_agc                   : AGC/PGA parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t AgcPgaCheckParam (const vdec_agc_t * const p_agc)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* AGC / PGA */
+    if (p_agc != NULL) {
+        /* AGC response speed */
+        if (((uint32_t)p_agc->agcresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000007)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Sync signal reference amplitude */
+        if (((uint32_t)p_agc->agclevel & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* AGC gain adjustment accuracy */
+        if (((uint32_t)p_agc->agcprecis & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* PGA gain */
+        if (((uint32_t)p_agc->pga_gain & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function AgcPgaCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on peak limiter control parameter
+ * @param[in]   p_peak_limiter          : Peak limiter control parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t PeakLimiterControlCheckParam (const vdec_peak_limiter_t * const p_peak_limiter)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Peak limiter control */
+    if (p_peak_limiter != NULL) {
+        /* Peak luminance value to operate peak limiter */
+        if (p_peak_limiter->peaklevel >= VDEC_PEAKLV_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+
+        /* Response speed with peak limiter gain decreased */
+        if (((uint32_t)p_peak_limiter->peakattack & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Response speed with peak limiter gain increased */
+        if (((uint32_t)p_peak_limiter->peakrelease & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Maximum compression rate of peak limiter */
+        if (p_peak_limiter->peakratio >= VDEC_PEAKRATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Allowable number of overflowing pixels */
+        if (((uint32_t)p_peak_limiter->maxpeaksamples & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function PeakLimiterControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on over-range control parameter
+ * @param[in]   p_over_range            : Over-range control parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t OverRangeControlCheckParam (const vdec_over_range_t * const p_over_range)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Over-range control */
+    if (p_over_range != NULL) {
+        /* A/D over-threshold level (between levels 0 and 1) */
+        if (((uint32_t)p_over_range->radj_o_level0 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D under-threshold level (between levels 2 and 3) */
+        if (((uint32_t)p_over_range->radj_u_level0 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D over-threshold level (between levels 1 and 2) */
+        if (((uint32_t)p_over_range->radj_o_level1 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D under-threshold level (between levels 1 and 2) */
+        if (((uint32_t)p_over_range->radj_u_level1 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D over-threshold level (between levels 2 and 3) */
+        if (((uint32_t)p_over_range->radj_o_level2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D under-threshold level (between levels 0 and 1) */
+        if (((uint32_t)p_over_range->radj_u_level2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function OverRangeControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on Y/C separation control parameter
+ * @param[in]   p_yc_sep_ctrl           : Y/C separation control parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t YcSeparationControlCheckParam (const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Y/C separation control */
+    if (p_yc_sep_ctrl != NULL) {
+        /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
+        if ((((uint32_t)p_yc_sep_ctrl->k15 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k13 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k11 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
+        if ((((uint32_t)p_yc_sep_ctrl->k16 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k14 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k12 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
+        if ((((uint32_t)p_yc_sep_ctrl->k22a & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k21a & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
+        if ((((uint32_t)p_yc_sep_ctrl->k22b & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k21b & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
+        if ((((uint32_t)p_yc_sep_ctrl->k23b & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k23a & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k24 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of signal after passing horizontal filter
+          to signal after passing former-stage horizontal filter */
+        if (p_yc_sep_ctrl->hsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of signal after passing vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        if (p_yc_sep_ctrl->vsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of signal after passing horizontal/vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        if (p_yc_sep_ctrl->hvsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Vertical luminance detection level for correlation detection filter */
+        if (((uint32_t)p_yc_sep_ctrl->v_y_level & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+
+        /* Mixing ratio of c signal after passing horizontal/vertical adaptive filter
+           to signal after passing correlation detection filter */
+        if (p_yc_sep_ctrl->det2_mix_c >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of C signal for Y generation after passing
+           horizontal/vertical adaptive filter to signal after passing correlation */
+        if (p_yc_sep_ctrl->det2_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional cascade/TAKE-OFF filter mode select */
+        if (p_yc_sep_ctrl->fil2_mode_2d >= VDEC_2DFIL_MDSEL_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function YcSeparationControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma filter TAP coefficient for Y/C separation
+ * @param[in]   fil2_2d                 : Chroma filter TAP coefficient for Y/C separation
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t FilterTAPsCoefficientCheckParam (const vdec_chrfil_tap_t * const fil2_2d)
+{
+    int32_t             tap_coef;
+    const uint16_t    * taps;
+    vdec_error_t        vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (fil2_2d != NULL) {
+        taps = fil2_2d->fil2_2d_f;
+        for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
+            if (((uint32_t)*taps & (uint32_t)(~VDEC_CPARA_RANGE_0X00001FFF)) != 0u) {
+                vdec_error = VDEC_ERR_PARAM;
+                goto END;
+            }
+            taps++;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function FilterTAPsCoefficientCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on color system detection parameter
+ * @param[in]   p_chrmdec_ctrl          : Color system detection parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t ChromaDecodingControlCheckParam (const vdec_chrmdec_ctrl_t * const p_chrmdec_ctrl)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Chroma decoding control */
+    if (p_chrmdec_ctrl != NULL) {
+        /* Default color system */
+        if (p_chrmdec_ctrl->defaultsys >= VDEC_COL_SYS_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Luminance signal delay adjustment */
+        if (((uint32_t)p_chrmdec_ctrl->lumadelay & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Averaging processing for pre-demodulated line */
+        if ((p_chrmdec_ctrl->demodmode != VDEC_DEMOD_MD_NO) && (p_chrmdec_ctrl->demodmode != VDEC_DEMOD_MD_PAL)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function ChromaDecodingControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on BCO parameter
+ * @param[in]   p_burst_lock            : BCO parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t BurstLockCheckParam (const vdec_burst_lock_t * const p_burst_lock)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Burst lock */
+    if (p_burst_lock != NULL) {
+        /* Burst lock PLL lock range */
+        if (p_burst_lock->lockrange >= VDEC_LOCK_RANGE_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Burst lock PLL loop gain */
+        if (((uint32_t)p_burst_lock->loopgain & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Level for burst lock PLL to re-search free-run frequency */
+        if (((uint32_t)p_burst_lock->locklimit & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* burst gate pulse position check */
+        if (((uint32_t)p_burst_lock->bgpcheck & (uint32_t)(~VDEC_CPARA_RANGE_0X00000001)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* burst gate pulse width */
+        if (((uint32_t)p_burst_lock->bgpwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X0000007F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* burst gate pulse start position */
+        if (((uint32_t)p_burst_lock->bgpstart & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function BurstLockCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on ACC and color killer parameter
+ * @param[in]   p_acc                   : ACC and color killer parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t AccColorKillerCheckParam (const vdec_acc_t * const p_acc)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* ACC/color killer */
+    if (p_acc != NULL) {
+        /* Maximum ACC Gain */
+        if (p_acc->accmaxgain >= VDEC_ACC_MAX_GAIN_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* ACC reference color burst amplitude */
+        if (((uint32_t)p_acc->acclevel & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Chroma manual gain (sub) */
+        if (p_acc->chromasubgain >= VDEC_CHRM_SB_GAIN_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Chroma manual gain (main) */
+        if (((uint32_t)p_acc->chromamaingain & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* ACC response speed */
+        if (((uint32_t)p_acc->accresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* ACC gain adjustment accuracy */
+        if (((uint32_t)p_acc->accprecis & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Color killer operation start point */
+        if (((uint32_t)p_acc->killerlevel & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* The offset level to turn off the color killer */
+        if (((uint32_t)p_acc->killeroffset & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function AccColorKillerCheckParam() */
+
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/src/r_vdec_check_parameter.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,66 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_check_parameter.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver parameter check definitions
+******************************************************************************/
+
+#ifndef R_VDEC_CHECK_PARAMETER_H
+#define R_VDEC_CHECK_PARAMETER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+
+#ifdef      R_VDEC_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdec_error_t VDEC_InitializeCheckParam(const vdec_adc_vinsel_t vinsel);
+vdec_error_t VDEC_ActivePeriodCheckParam(const vdec_active_period_t * const param);
+vdec_error_t VDEC_SyncSeparationCheckParam(const vdec_sync_separation_t * const param);
+vdec_error_t VDEC_YcSeparationCheckParam(const vdec_yc_separation_t * const param);
+vdec_error_t VDEC_ChromaDecodingCheckParam(const vdec_chroma_decoding_t * const param);
+vdec_error_t VDEC_DigitalClampCheckParam(const vdec_degital_clamp_t * const param);
+vdec_error_t VDEC_OutputCheckParam(const vdec_output_t * const param);
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+
+#endif  /* R_VDEC_CHECK_PARAMETER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/src/r_vdec_register.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,977 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_register.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* shift value */
+#define     VEDC_REG_SHIFT_15            (15u)
+#define     VEDC_REG_SHIFT_14            (14u)
+#define     VEDC_REG_SHIFT_13            (13u)
+#define     VEDC_REG_SHIFT_12            (12u)
+#define     VEDC_REG_SHIFT_11            (11u)
+#define     VEDC_REG_SHIFT_10            (10u)
+#define     VEDC_REG_SHIFT_9             (9u)
+#define     VEDC_REG_SHIFT_8             (8u)
+#define     VEDC_REG_SHIFT_6             (6u)
+#define     VEDC_REG_SHIFT_5             (5u)
+#define     VEDC_REG_SHIFT_4             (4u)
+#define     VEDC_REG_SHIFT_2             (2u)
+#define     VEDC_REG_SHIFT_1             (1u)
+
+/* bit set pattern */
+#define     VDEC_REG_SET_0X8000         (0x8000u)
+#define     VDEC_REG_SET_0X4000         (0x4000u)
+#define     VDEC_REG_SET_0X2000         (0x2000u)
+#define     VDEC_REG_SET_0X1000         (0x1000u)
+#define     VDEC_REG_SET_0X0800         (0x0800u)
+#define     VDEC_REG_SET_0X0100         (0x0100u)
+#define     VDEC_REG_SET_0X0080         (0x0080u)
+#define     VDEC_REG_SET_0X0020         (0x0020u)
+#define     VDEC_REG_SET_0X0010         (0x0010u)
+#define     VDEC_REG_SET_0X0008         (0x0008u)
+#define     VDEC_REG_SET_0X0004         (0x0004u)
+#define     VDEC_REG_SET_0X0002         (0x0002u)
+#define     VDEC_REG_SET_0X0001         (0x0001u)
+
+/* bit mask pattern */
+#define     VDEC_REG_BIT_MASK_0X8000    (0x8000u)
+#define     VDEC_REG_BIT_MASK_0X4000    (0x4000u)
+#define     VDEC_REG_BIT_MASK_0X2000    (0x2000u)
+#define     VDEC_REG_BIT_MASK_0X1000    (0x1000u)
+#define     VDEC_REG_BIT_MASK_0X0800    (0x0800u)
+#define     VDEC_REG_BIT_MASK_0X0400    (0x0400u)
+#define     VDEC_REG_BIT_MASK_0X0200    (0x0200u)
+#define     VDEC_REG_BIT_MASK_0X0100    (0x0100u)
+
+/* register mask value */
+#define     VDEC_REG_MASK_0X03FF        (0x03FFu) /* mask vdec_reg->syncssr  */
+#define     VDEC_REG_MASK_0XFF1F        (0xFF1Fu) /* mask vdec_reg->ycscr7   */
+#define     VDEC_REG_MASK_0XF3FF        (0xF3FFu) /* mask vdec_reg->hafccr1  */
+#define     VDEC_REG_MASK_0X83FF        (0x83FFu) /* mask vdec_reg->dcpcr1   */
+#define     VDEC_REG_MASK_0X01FF        (0x01FFu) /* mask vdec_reg->ycscr11  */
+#define     VDEC_REG_MASK_0X1C00        (0x1C00u) /* mask vdec_reg->dcpcr9   */
+#define     VDEC_REG_MASK_0X1F00        (0x1F00u) /* mask vdec_reg->pgacr    */
+#define     VDEC_REG_MASK_0X3F00        (0x3F00u) /* mask vdec_reg->agccr2   */
+#define     VDEC_REG_MASK_0X0007        (0x0007u) /* mask vdec_reg->rgorcr7  */
+#define     VDEC_REG_MASK_0XF800        (0xF800u) /* mask vdec_reg->ycscr8   */
+#define     VDEC_REG_MASK_0XFC00        (0xFC00u) /* mask vdec_reg->synscr1  */
+#define     VDEC_REG_MASK_0X00FF        (0x00FFu) /* mask vdec_reg->synscr1  */
+#define     VDEC_REG_MASK_0X0003        (0x0003u) /* mask vdec_reg->cromasr1 */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void NoiseReductionLPF(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_noise_rd_lpf_t   * const p_noise_rd_lpf);
+static void SyncSlicer(const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer);
+static void HorizontalAFC(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_horizontal_afc_t * const p_horizontal_afc);
+static void VerticalCountdown(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_vcount_down_t    * const p_vcount_down);
+static void AgcPga(const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc);
+static void PeakLimiterControl(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_peak_limiter_t   * const p_peak_limiter);
+static void OverRangeControl(const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range);
+static void YcSeparationControl(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_yc_sep_ctrl_t    * const p_yc_sep_ctrl);
+static void FilterTAPsCoefficient(
+    volatile uint16_t       * const   * fil_reg_address,
+    const vdec_chrfil_tap_t * const     fil2_2d);
+
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   ch                      : Channel
+ * @param[in]   vinsel                  : Input pin control
+ * @retval      None
+ *****************************************************************************/
+void VDEC_Initialize (const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    uint16_t                    reg_data;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Input pin control */
+    if (vinsel == VDEC_ADC_VINSEL_VIN1) {
+        reg_data            = (uint16_t)((uint32_t)*(vdec_reg->adccr2) & (~0x0001u));
+        *(vdec_reg->adccr2) = reg_data;
+    } else {
+        reg_data            = (uint16_t)((uint32_t)*(vdec_reg->adccr2) | (0x0001u));
+        *(vdec_reg->adccr2) = reg_data;
+    }
+    return;
+}   /* End of function VDEC_Initialize() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for active image period
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Active image period parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
+{
+    const vdec_reg_address_t * vdec_reg;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Left end of input video signal capturing area */
+    *(vdec_reg->tgcr1) = param->srcleft;
+    /* Top end of input video signal capturing area
+       and height of input video signal capturing area */
+    *(vdec_reg->tgcr2) = (uint16_t)(((uint32_t)param->srctop << VEDC_REG_SHIFT_10) | (uint32_t)param->srcheight);
+    /* Width of input video signal capturing area */
+    *(vdec_reg->tgcr3) = param->srcwidth;
+
+    return;
+}   /* End of function VDEC_ActivePeriod() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for sync separation
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync separation parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+
+    vdec_reg            = &vdec_reg_address[ch];
+
+    /* Noise reduction LPF */
+    NoiseReductionLPF(vdec_reg, param->noise_rd_lpf);
+    /* Auto level control sync slicer */
+    SyncSlicer(vdec_reg, param->sync_slicer);
+    /* Horizontal AFC */
+    HorizontalAFC(vdec_reg, param->horizontal_afc);
+    /* Vertical count-down */
+    VerticalCountdown(vdec_reg, param->vcount_down);
+    /* AGC/PGA */
+    AgcPga(vdec_reg, param->agc);
+    /* Peak limiter control */
+    PeakLimiterControl(vdec_reg, param->peak_limiter);
+
+    return;
+}   /* End of function VDEC_SyncSeparation() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for Y/C separation
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Y/C separation parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+
+    vdec_reg        = &vdec_reg_address[ch];
+
+    /* Over-range control */
+    OverRangeControl(vdec_reg, param->over_range);
+    /* Y/C separation control */
+    YcSeparationControl(vdec_reg, param->yc_sep_ctrl);
+
+    /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwa_f, param->fil2_2d_wa);
+    /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwb_f, param->fil2_2d_wb);
+    /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctna_f, param->fil2_2d_na);
+    /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctnb_f, param->fil2_2d_nb);
+
+    return;
+}   /* End of function VDEC_YcSeparation() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma decoding
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Chroma decoding parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    vdec_chrmdec_ctrl_t       * p_chrmdec_ctrl;
+    vdec_burst_lock_t         * p_burst_lock;
+    vdec_acc_t                * p_acc;
+    vdec_tint_ry_t            * p_tint_ry;
+    uint32_t                    reg_data;
+
+    vdec_reg        = &vdec_reg_address[ch];
+    p_chrmdec_ctrl  = param->chrmdec_ctrl;
+    p_burst_lock    = param->burst_lock;
+    p_acc           = param->acc;
+    p_tint_ry       = param->tint_ry;
+
+    /* Color system detection */
+    if (p_chrmdec_ctrl != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
+        /* Default color system */
+        reg_data   |= (uint32_t)p_chrmdec_ctrl->defaultsys << VEDC_REG_SHIFT_6;
+        /* NTSC-M detection control */
+        reg_data   |= (p_chrmdec_ctrl->nontsc358_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0020 : (uint32_t)0x0000u;
+        /* NTSC-4.43 detection control */
+        reg_data   |= (p_chrmdec_ctrl->nontsc443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0010 : (uint32_t)0x0000u;
+        /* PAL-M detection control */
+        reg_data   |= (p_chrmdec_ctrl->nopalm_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0008 : (uint32_t)0x0000u;
+        /* PAL-N detection control */
+        reg_data   |= (p_chrmdec_ctrl->nopaln_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0004 : (uint32_t)0x0000u;
+        /* PAL-B, G, H, I, D detection control */
+        reg_data   |= (p_chrmdec_ctrl->nopal443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0002 : (uint32_t)0x0000u;
+        /* SECAM detection control */
+        reg_data   |= (p_chrmdec_ctrl->nosecam_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0001 : (uint32_t)0x0000u;
+
+        *(vdec_reg->btlcr) = (uint16_t)reg_data;
+
+        /* Luminance signal delay adjustment */
+        reg_data    = (uint32_t)p_chrmdec_ctrl->lumadelay << VEDC_REG_SHIFT_4;
+        /* LPF for demodulated chroma */
+        reg_data   |= (p_chrmdec_ctrl->chromalpf == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
+        /* Averaging processing for pre-demodulated line */
+        reg_data   |= (uint32_t)p_chrmdec_ctrl->demodmode;
+
+        *(vdec_reg->ycdcr) = (uint16_t)reg_data;
+    }
+    /* BCO */
+    if (p_burst_lock != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
+        /* Burst lock PLL lock range */
+        reg_data   |= (uint32_t)p_burst_lock->lockrange << VEDC_REG_SHIFT_14;
+        /* Burst lock PLL loop gain */
+        reg_data   |= (uint32_t)p_burst_lock->loopgain << VEDC_REG_SHIFT_12;
+        /* Level for burst lock PLL to re-search free-run frequency */
+        reg_data   |= (uint32_t)p_burst_lock->locklimit << VEDC_REG_SHIFT_10;
+
+        *(vdec_reg->btlcr) = (uint16_t)reg_data;
+
+        /* burst gate pulse position check */
+        reg_data    = (uint32_t)p_burst_lock->bgpcheck << VEDC_REG_SHIFT_15;
+        /* burst gate pulse width */
+        reg_data   |= (uint32_t)p_burst_lock->bgpwidth << VEDC_REG_SHIFT_8;
+        /* burst gate pulse start position */
+        reg_data   |= (uint32_t)p_burst_lock->bgpstart;
+
+        *(vdec_reg->btgpcr) = (uint16_t)reg_data;
+    }
+    /* ACC and color killer */
+    if (p_acc != NULL) {
+        /* ACC operating mode */
+        reg_data    = (p_acc->accmode == VDEC_ACC_MD_AUTO) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
+        /* Maximum ACC Gain */
+        reg_data   |= (uint32_t)p_acc->accmaxgain << VEDC_REG_SHIFT_9;
+        /* ACC reference color burst amplitude */
+        reg_data   |= (uint32_t)p_acc->acclevel;
+        /* Color killer offset */
+        reg_data   |= (uint32_t)p_acc->killeroffset << VEDC_REG_SHIFT_12;
+
+        *(vdec_reg->acccr1) = (uint16_t)reg_data;
+
+        /* Chroma manual gain (sub) */
+        reg_data    = (uint32_t)p_acc->chromasubgain << VEDC_REG_SHIFT_9;
+        /* Chroma manual gain (main) */
+        reg_data   |= (uint32_t)p_acc->chromamaingain;
+
+        *(vdec_reg->acccr2) = (uint16_t)reg_data;
+
+        /* ACC response speed */
+        reg_data    = (uint32_t)p_acc->accresponse << VEDC_REG_SHIFT_14;
+        /* ACC gain adjustment accuracy */
+        reg_data   |= (uint32_t)p_acc->accprecis << VEDC_REG_SHIFT_8;
+        /* Forced color killer mode ON/OFF */
+        reg_data   |= (p_acc->killermode == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0080;
+        /* Color killer operation start point */
+        reg_data   |= (uint32_t)p_acc->killerlevel << VEDC_REG_SHIFT_1;
+
+        *(vdec_reg->acccr3) = (uint16_t)reg_data;
+    }
+    /* TINT correction/R-Y axis correction (only valid for NTSC/PAL) */
+    if (p_tint_ry != NULL) {
+        /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
+        reg_data    = (uint32_t)p_tint_ry->tintsub << VEDC_REG_SHIFT_10;
+        reg_data   |= (uint32_t)p_tint_ry->tintmain;
+
+        *(vdec_reg->tintcr) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function VDEC_ChromaDecoding() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for digital clamp
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Digital clamp parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    vdec_pedestal_clamp_t     * p_pedestal_clamp;
+    vdec_center_clamp_t       * p_center_clamp;
+    vdec_noise_det_t          * p_noise_det;
+    uint32_t                    reg_data;
+
+    vdec_reg            = &vdec_reg_address[ch];
+    p_pedestal_clamp    = param->pedestal_clamp;
+    p_center_clamp      = param->center_clamp;
+    p_noise_det         = param->noise_det;
+
+    /* Digital clamp pulse position check */
+    reg_data = (uint32_t)*(vdec_reg->dcpcr1);
+    if (param->dcpcheck == VDEC_OFF) {
+        reg_data &= (uint32_t)(~VDEC_REG_SET_0X0800);
+    } else {
+        reg_data |= (uint32_t)VDEC_REG_SET_0X0800;
+    }
+    *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
+
+    /* Digital clamp response speed */
+    *(vdec_reg->dcpcr3) = (uint16_t)((uint32_t)param->dcpresponse << VEDC_REG_SHIFT_12);
+    /* Digital clamp start line */
+    *(vdec_reg->dcpcr4) = (uint16_t)((uint32_t)param->dcpstart << VEDC_REG_SHIFT_10);
+    /* Digital clamp end line */
+    *(vdec_reg->dcpcr5) = (uint16_t)((uint32_t)param->dcpend << VEDC_REG_SHIFT_10);
+    /* Digital clamp pulse width */
+    *(vdec_reg->dcpcr6) = (uint16_t)((uint32_t)param->dcpwidth << VEDC_REG_SHIFT_8);
+
+    /* Pedestal clamp */
+    if (p_pedestal_clamp != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->dcpcr1) & (uint32_t)(~VDEC_REG_MASK_0X83FF);
+        /* Clamp level setting mode (Y signal) */
+        reg_data   |= (p_pedestal_clamp->dcpmode_y == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X8000;
+        /* Clamp offset level (Y signal) */
+        reg_data   |= (uint32_t)p_pedestal_clamp->blanklevel_y;
+
+        *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
+
+        /* Digital clamp pulse horizontal start position (Y signal) */
+        *(vdec_reg->dcpcr7) = (uint16_t)((uint32_t)p_pedestal_clamp->dcppos_y << VEDC_REG_SHIFT_8);
+    }
+    /* Center clamp */
+    if (p_center_clamp != NULL) {
+        /* Clamp level setting mode (Cb/Cr signal) */
+        reg_data    = (p_center_clamp->dcpmode_c == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X8000;
+        /* Clamp offset level (Cb signal) */
+        reg_data   |= (uint32_t)p_center_clamp->blanklevel_cb << VEDC_REG_SHIFT_6;
+        /* Clamp offset level (Cr signal) */
+        reg_data   |= (uint32_t)p_center_clamp->blanklevel_cr;
+
+        *(vdec_reg->dcpcr2) = (uint16_t)reg_data;
+
+        /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
+        *(vdec_reg->dcpcr8) = (uint16_t)((uint32_t)p_center_clamp->dcppos_c << VEDC_REG_SHIFT_8);
+    }
+    /* Noise detection */
+    if (p_noise_det != NULL) {
+        /* Video signal for autocorrelation function */
+        reg_data    = (uint32_t)p_noise_det->acfinput << VEDC_REG_SHIFT_12;
+        /* Delay time for autocorrelation function calculation */
+        reg_data   |= (uint32_t)p_noise_det->acflagtime << VEDC_REG_SHIFT_4;
+        /* Smoothing parameter of autocorrelation function data */
+        reg_data   |= (uint32_t)p_noise_det->acffilter;
+
+        *(vdec_reg->nsdcr) = (uint16_t)reg_data;
+    }
+    /* Clamp data hold processing (Y, Cb, Cr) OFF */
+    reg_data            = (uint32_t)*(vdec_reg->dcpcr9) & (uint32_t)(~VDEC_REG_MASK_0X1C00);
+    *(vdec_reg->dcpcr9) = (uint16_t)reg_data;
+
+    return;
+}   /* End of function VDEC_DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for output adjustment
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Output adjustment parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
+{
+    const vdec_reg_address_t * vdec_reg;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Y, Cb and Cr signal gain coefficient */
+    *(vdec_reg->ygaincr)    = param->y_gain2;
+    *(vdec_reg->cbgaincr)   = param->cb_gain2;
+    *(vdec_reg->crgaincr)   = param->cr_gain2;
+
+    return;
+}   /* End of function VDEC_Output() */
+
+/**************************************************************************//**
+ * @brief       Query VDEC parameters
+ * @param[in]   ch                      : Channel
+ * @param[out]  q_sync_sep              : Sync separation parameters
+ * @param[out]  q_agc                   : Agc parameters
+ * @param[out]  q_chroma_dec            : Chroma decoding parameters
+ * @param[out]  q_digital_clamp         : Digital clamp parameters
+ * @retval      None
+ *****************************************************************************/
+void VDEC_Query (
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    uint32_t                    reg_value;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Sync separation */
+    if (q_sync_sep != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->vsyncsr);
+        /* Horizontal AFC lock detection result */
+        q_sync_sep->fhlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X4000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+        /* Detection result of low S/N signal by sync separation */
+        q_sync_sep->isnoisy = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Speed detection result */
+        q_sync_sep->fhmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_FHMD_NORMAL :
+                             VDEC_FHMD_MULTIPLIED;
+        /* No-signal detection result */
+        q_sync_sep->nosignal_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
+        /* Vertical countdown lock detection result */
+        q_sync_sep->fvlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+        /* Vertical countdown oscillation mode */
+        q_sync_sep->fvmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0200) == 0u) ? VDEC_FVMD_50HZ :
+                             VDEC_FVMD_60HZ;
+        /* Interlace detection result */
+        q_sync_sep->interlaced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Vertical cycle measurement result */
+        q_sync_sep->fvcount = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+        /* Horizontal AFC oscillation cycle */
+        q_sync_sep->fhcount  = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X8000) == 0u) ? 0x0000u : (uint32_t)0x0001u;
+        q_sync_sep->fhcount |= (uint32_t)*(vdec_reg->hsyncsr) << VEDC_REG_SHIFT_1;
+
+        reg_value = (uint32_t)*(vdec_reg->syncssr);
+        /* Sync amplitude detection result during VBI period */
+        q_sync_sep->isreduced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Sync pulse amplitude detection result */
+        q_sync_sep->syncdepth = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
+    }
+    /* Agc */
+    if (q_agc != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->agccsr1);
+        /* Number of pixels which have larger luminance value than peak luminance limited by peak limiter */
+        q_agc->highsamples = (uint16_t)(reg_value >> VEDC_REG_SHIFT_8);
+        /* Number of overflowing pixels */
+        q_agc->peaksamples = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+
+        reg_value = (uint32_t)*(vdec_reg->agccsr2);
+        /* AGC convergence detection result */
+        if ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) {
+            q_agc->agcconverge = (uint16_t)0x0000u;
+        } else {
+            q_agc->agcconverge = (uint16_t)0x0001u;
+        }
+        /* Current AGC gain value */
+        q_agc->agcgain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+    }
+    /* Chroma decoding */
+    if (q_chroma_dec != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->cromasr1);
+        /* Color system detection result */
+        q_chroma_dec->colorsys = (vdec_color_sys_t)(reg_value >> VEDC_REG_SHIFT_14);
+        /* Color sub-carrier frequency detection result */
+        q_chroma_dec->fscmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_FSCMD_3_58 :
+                                VDEC_FSCMD_4_43;
+        /* Burst lock PLL lock state detection result */
+        q_chroma_dec->fsclock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+        /* Color burst detection result */
+        q_chroma_dec->noburst_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
+        /* Current ACC gain value (sub) */
+        q_chroma_dec->accsubgain = (vdec_chrm_subgain_t)((reg_value >> VEDC_REG_SHIFT_9) &
+                                   (uint32_t)VDEC_REG_MASK_0X0003);
+        /* Current ACC gain value (main) */
+        q_chroma_dec->accmaingain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X01FF);
+
+        reg_value = (uint32_t)*(vdec_reg->cromasr2);
+        /* SECAM detection result */
+        q_chroma_dec->issecam = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
+        /* PAL detection result */
+        q_chroma_dec->ispal = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_NO : VDEC_YES;
+        /* NTSC detection result */
+        q_chroma_dec->isntsc = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Low S/N signal detection result by burst lock PLL */
+        q_chroma_dec->locklevel = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+    }
+    /* Digital clamp */
+    if (q_digital_clamp != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->dcpsr1);
+        /* Digital clamp subtraction value (Cb signal) */
+        q_digital_clamp->clamplevel_cb = (uint16_t)(reg_value >> VEDC_REG_SHIFT_10);
+        /* Digital clamp subtraction value (Y signal) */
+        q_digital_clamp->clamplevel_y = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
+
+        /* Digital clamp subtraction value (Cr signal) */
+        q_digital_clamp->clamplevel_cr = (uint16_t)((uint32_t)*(vdec_reg->dcpsr2) >> VEDC_REG_SHIFT_10);
+
+        /* Noise autocorrelation strength at digital clamp pulse position */
+        q_digital_clamp->acfstrength = *(vdec_reg->nsdsr);
+    }
+    return;
+}   /* End of function VDEC_Query() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for noise reduction LPF
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_noise_rd_lpf          : Noise reduction LPF parameter
+ * @retval      None
+ *****************************************************************************/
+static void NoiseReductionLPF (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_noise_rd_lpf_t   * const p_noise_rd_lpf)
+{
+    uint32_t reg_data;
+
+    /* Noise reduction LPF */
+    if (p_noise_rd_lpf != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
+        /* LPF cutoff frequency before vertical sync separation */
+        reg_data   |= (uint32_t)p_noise_rd_lpf->lpfvsync << VEDC_REG_SHIFT_13;
+        /* LPF cutoff frequency before horizontal sync separation */
+        reg_data   |= (uint32_t)p_noise_rd_lpf->lpfhsync << VEDC_REG_SHIFT_10;
+
+        *(vdec_reg->synscr1) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function NoiseReductionLPF() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for auto level control sync slicer
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_sync_slicer           : Auto level control sync slicer parameter
+ * @retval      None
+ *****************************************************************************/
+static void SyncSlicer (const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer)
+{
+    uint32_t reg_data;
+
+    /* Auto level control sync slicer */
+    if (p_sync_slicer != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
+        /* Reference level operation speed control for composite sync separation (for Hsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->velocityshift_h << VEDC_REG_SHIFT_4;
+        /* Auto-slice level setting for composite sync separation circuit (for Hsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->slicermode_h << VEDC_REG_SHIFT_2;
+        /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->slicermode_v;
+
+        *(vdec_reg->synscr1) = (uint16_t)reg_data;
+
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
+        reg_data    = (uint32_t)p_sync_slicer->syncmaxduty_h << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_sync_slicer->syncminduty_h;
+
+        *(vdec_reg->synscr2) = (uint16_t)reg_data;
+
+        /* Clipping level and slice level for composite sync signal separation (for Hsync signal) */
+        reg_data    = (uint32_t)p_sync_slicer->ssclipsel << VEDC_REG_SHIFT_10;
+        reg_data   |= (uint32_t)p_sync_slicer->csyncslice_h;
+
+        *(vdec_reg->synscr3) = (uint16_t)reg_data;
+
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
+        reg_data    = (uint32_t)p_sync_slicer->syncmaxduty_v << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_sync_slicer->syncminduty_v;
+
+        *(vdec_reg->synscr4) = (uint16_t)reg_data;
+
+        /* Delays the separated vertical sync signal for 1/4 horizontal cycle */
+        reg_data    = (p_sync_slicer->vsyncdelay == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
+        /* Threshold for vertical sync separation */
+        reg_data   |= (uint32_t)p_sync_slicer->vsyncslice << VEDC_REG_SHIFT_10;
+        /* Slice level for composite sync signal separation (for Vsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->csyncslice_v;
+
+        *(vdec_reg->synscr5) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function SyncSlicer() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for horizontal AFC
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_horizontal_afc        : Horizontal AFC parameter
+ * @retval      None
+ *****************************************************************************/
+static void HorizontalAFC (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_horizontal_afc_t * const p_horizontal_afc)
+{
+    uint32_t reg_data;
+
+    /* Horizontal AFC */
+    if (p_horizontal_afc != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->hafccr1) & (uint32_t)(~VDEC_REG_MASK_0XF3FF);
+        /* Horizontal AFC loop gain */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcgain << VEDC_REG_SHIFT_12;
+        /* Horizontal AFC center oscillation frequency */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafctyp;
+
+        *(vdec_reg->hafccr1) = (uint16_t)reg_data;
+
+        /* Start line of horizontal AFC normal operation
+           and Horizontal AFC forced double-speed oscillation (DOX2HOSC = 0, auto control) */
+        reg_data    = (uint32_t)p_horizontal_afc->hafcstart << VEDC_REG_SHIFT_12;
+        /* Disable of horizontal AFC double speed detection */
+        reg_data   |= (p_horizontal_afc->nox2hosc == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
+        /* Maximum oscillation frequency of horizontal AFC */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcmax;
+
+        *(vdec_reg->hafccr2) = (uint16_t)reg_data;
+
+        /* End line of horizontal AFC normal operation */
+        reg_data    = (uint32_t)p_horizontal_afc->hafcend << VEDC_REG_SHIFT_12;
+        /* Horizontal AFC VBI period operating mode */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcmode << VEDC_REG_SHIFT_10;
+        /* Min oscillation frequency of horizontal AFC */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcmin;
+
+        *(vdec_reg->hafccr3) = (uint16_t)reg_data;
+
+        /* Forcible or LOWGAIN control */
+        reg_data    = (p_horizontal_afc->phdet_fix == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0010;
+        /* Phase comparator feedback adjust for low sync signal lock stability */
+        reg_data   |= (uint32_t)p_horizontal_afc->phdet_div;
+
+        *(vdec_reg->afcpfcr) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function HorizontalAFC() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for vertical count-down
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_vcount_down           : Vertical count-down parameter
+ * @retval      None
+ *****************************************************************************/
+static void VerticalCountdown (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_vcount_down_t    * const p_vcount_down)
+{
+    uint32_t reg_data;
+
+    /* Vertical count-down */
+    if (p_vcount_down != NULL) {
+        /* Vertical countdown 50-Hz oscillation mode
+           and Vertical countdown free-run oscillation mode (VCDFREERUN = OFF) */
+        reg_data    = (p_vcount_down->novcd50_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X4000 : (uint32_t)0x0000u;
+        /* Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
+        reg_data   |= (p_vcount_down->novcd60_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X2000 : (uint32_t)0x0000u;
+        /* Vertical countdown center oscillation frequency */
+        reg_data   |= (uint32_t)p_vcount_down->vcddefault << VEDC_REG_SHIFT_11;
+        /* Vertical countdown sync area */
+        reg_data   |= (uint32_t)p_vcount_down->vcdwindow << VEDC_REG_SHIFT_5;
+        /* Vertical countdown minimum oscillation frequency */
+        reg_data   |= (uint32_t)p_vcount_down->vcdoffset;
+
+        *(vdec_reg->vcdwcr1) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function VerticalCountdown() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for AGC/PGA
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_agc                   : AGC/PGA parameter
+ * @retval      None
+ *****************************************************************************/
+static void AgcPga (const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc)
+{
+    uint32_t reg_data;
+
+    /* AGC/PGA */
+    if (p_agc != NULL) {
+        /* A/D converter AGC ON/OFF control & PGA switch */
+        if (p_agc->agcmode == VDEC_OFF) {
+            reg_data            = (uint32_t)*(vdec_reg->pgacr) | (uint32_t)VDEC_REG_SET_0X2000;
+            *(vdec_reg->pgacr)  = (uint16_t)reg_data;
+            *(vdec_reg->adccr1) = (uint16_t)0u;
+        } else {
+            *(vdec_reg->adccr1) = (uint16_t)VDEC_REG_SET_0X0100;
+            reg_data            = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_SET_0X2000);
+            *(vdec_reg->pgacr)  = (uint16_t)reg_data;
+        }
+        /* PGA gain */
+        reg_data    = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_MASK_0X1F00);
+        reg_data   |= (uint32_t)p_agc->pga_gain << VEDC_REG_SHIFT_8;
+
+        *(vdec_reg->pgacr) = (uint16_t)reg_data;
+
+        /* PGA register update register */
+        *(vdec_reg->pga_update) = (uint16_t)1u;
+
+        /* Manual control of sync signal amplitude detection during VBI period */
+        reg_data    = (p_agc->doreduce == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X2000;
+        /* Control of sync signal amplitude detection during VBI period */
+        reg_data   |= (p_agc->noreduce_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X1000 : (uint32_t)0x0000u;
+        /* AGC response speed */
+        reg_data   |= (uint32_t)p_agc->agcresponse << VEDC_REG_SHIFT_9;
+        /* Sync signal reference amplitude */
+        reg_data   |= (uint32_t)p_agc->agclevel;
+
+        *(vdec_reg->agccr1) = (uint16_t)reg_data;
+
+        /* AGC gain adjustment accuracy */
+        reg_data    = (uint32_t)*(vdec_reg->agccr2) & (uint32_t)(~VDEC_REG_MASK_0X3F00);
+        reg_data   |= (uint32_t)p_agc->agcprecis << VEDC_REG_SHIFT_8;
+
+        *(vdec_reg->agccr2) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function AgcPga() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for peak limiter control
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_peak_limiter          : Peak limiter control parameter
+ * @retval      None
+ *****************************************************************************/
+static void PeakLimiterControl (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_peak_limiter_t   * const p_peak_limiter)
+{
+    uint32_t reg_data;
+
+    /* Peak limiter control */
+    if (p_peak_limiter != NULL) {
+        /* Peak luminance value limited by peak limiter */
+        reg_data    = (uint32_t)p_peak_limiter->peaklevel << VEDC_REG_SHIFT_14;
+        /* Response speed with peak limiter gain decreased */
+        reg_data   |= (uint32_t)p_peak_limiter->peakattack << VEDC_REG_SHIFT_12;
+        /* Response speed with peak limiter gain increased */
+        reg_data   |= (uint32_t)p_peak_limiter->peakrelease << VEDC_REG_SHIFT_10;
+        /* Maximum compression rate of peak limiter */
+        reg_data   |= (uint32_t)p_peak_limiter->peakratio << VEDC_REG_SHIFT_8;
+        /* Allowable number of overflowing pixels */
+        reg_data   |= (uint32_t)p_peak_limiter->maxpeaksamples;
+
+        *(vdec_reg->pklimitcr) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function PeakLimiterControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for over-range control
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_over_range            : Over-range control parameter
+ * @retval      None
+ *****************************************************************************/
+static void OverRangeControl (const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range)
+{
+    uint32_t reg_data;
+
+    /* Over-range control */
+    if (p_over_range != NULL) {
+        /* A/D over-threshold level (between levels 0 and 1) */
+        *(vdec_reg->rgorcr1) = p_over_range->radj_o_level0;
+        /* A/D under-threshold level (between levels 2 and 3) */
+        *(vdec_reg->rgorcr2) = p_over_range->radj_u_level0;
+        /* A/D over-threshold level (between levels 1 and 2) */
+        *(vdec_reg->rgorcr3) = p_over_range->radj_o_level1;
+        /* A/D under-threshold level (between levels 1 and 2) */
+        *(vdec_reg->rgorcr4) = p_over_range->radj_u_level1;
+        /* A/D over-threshold level (between levels 2 and 3) */
+        *(vdec_reg->rgorcr5) = p_over_range->radj_o_level2;
+        /* A/D under-threshold level (between levels 0 and 1) */
+        *(vdec_reg->rgorcr6) = p_over_range->radj_u_level2;
+
+        reg_data    = (uint32_t)*(vdec_reg->rgorcr7) & (uint32_t)(~VDEC_REG_MASK_0X0007);
+        /* Over-range detection enable */
+        reg_data   |= (p_over_range->ucmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
+        /* Under-range detection enable */
+        reg_data   |= (p_over_range->dcmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0002;
+        /* Horizontal enlargement of over/under-range level */
+        reg_data   |= (p_over_range->hwide_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)0x0001u;
+
+        *(vdec_reg->rgorcr7) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function OverRangeControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for Y/C separation control
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_yc_sep_ctrl           : Y/C separation control parameter
+ * @retval      None
+ *****************************************************************************/
+static void YcSeparationControl (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_yc_sep_ctrl_t    * const p_yc_sep_ctrl)
+{
+    uint32_t reg_data;
+
+    /* Y/C separation control */
+    if (p_yc_sep_ctrl != NULL) {
+        /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k15 << VEDC_REG_SHIFT_12;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k13 << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k11;
+
+        *(vdec_reg->ycscr3) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k16 << VEDC_REG_SHIFT_12;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k14 << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k12;
+
+        *(vdec_reg->ycscr4) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k22a << VEDC_REG_SHIFT_8;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k21a;
+
+        *(vdec_reg->ycscr5) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k22b << VEDC_REG_SHIFT_8;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k21b;
+
+        *(vdec_reg->ycscr6) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
+        reg_data    = (uint32_t)*(vdec_reg->ycscr7) & (uint32_t)(~VDEC_REG_MASK_0XFF1F);
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k23b << VEDC_REG_SHIFT_12;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k23a << VEDC_REG_SHIFT_8;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k24;
+
+        *(vdec_reg->ycscr7) = (uint16_t)reg_data;
+
+        reg_data    = (uint32_t)*(vdec_reg->ycscr8) & (uint32_t)(~VDEC_REG_MASK_0XF800);
+        /* Latter-stage horizontal BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X8000;
+        /* Latter-stage horizontal/vertical BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hvbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X4000;
+        /* Former-stage horizontal BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X2000;
+        /* Former-stage horizontal/vertical BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hvbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X1000;
+        /* Horizontal filter and horizontal/vertical filter bandwidth switch signal */
+        reg_data   |= (p_yc_sep_ctrl->hfil_tap_sel == VDEC_HFIL_TAP_SEL_17TAP) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X0800;
+
+        *(vdec_reg->ycscr8) = (uint16_t)reg_data;
+
+        /* Two-dimensional filter mixing select */
+        reg_data    = (p_yc_sep_ctrl->det2_on == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
+        /* Mixing ratio of signal after passing horizontal filter
+          to signal after passing former-stage horizontal filter */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->hsel_mix_y << VEDC_REG_SHIFT_8;
+        /* Mixing ratio of signal after passing vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->vsel_mix_y << VEDC_REG_SHIFT_4;
+        /* Mixing ratio of signal after passing horizontal/vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->hvsel_mix_y;
+
+        *(vdec_reg->ycscr9) = (uint16_t)reg_data;
+
+        /* Vertical luminance detection level for correlation detection filter */
+        reg_data    = (uint32_t)*(vdec_reg->ycscr11) & (uint32_t)(~VDEC_REG_MASK_0X01FF);
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->v_y_level;
+
+        *(vdec_reg->ycscr11) = (uint16_t)reg_data;
+
+        if (p_yc_sep_ctrl->det2_on == VDEC_OFF) {
+            reg_data    = ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_12) |
+                          ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_8);
+        } else {
+            /* Mixing ratio of C signal after passing horizontal/vertical adaptive filter
+               to signal after passing correlation detection filter */
+            reg_data    = (uint32_t)p_yc_sep_ctrl->det2_mix_c << VEDC_REG_SHIFT_12;
+            /* Mixing ratio of C signal for Y generation after passing
+               horizontal/vertical adaptive filter to signal after passing correlation */
+            reg_data   |= (uint32_t)p_yc_sep_ctrl->det2_mix_y << VEDC_REG_SHIFT_8;
+        }
+        /* Two-dimensional cascade/TAKE-OFF filter mode select */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->fil2_mode_2d << VEDC_REG_SHIFT_2;
+        /* Two-dimensional cascade filter select */
+        reg_data   |= (p_yc_sep_ctrl->fil2_narrow_2d == VDEC_2D_FIL_SEL_BYPASS) ? (uint32_t)0x0000u :
+                      (uint32_t)0x0001u;
+
+        *(vdec_reg->ycscr12) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function YcSeparationControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma filter TAP coefficient
+ * @param[in]   fil_reg_address         : 2D filter TAP coefficient registers
+ * @param[in]   fil2_2d                 : Chroma filter TAP coefficient for Y/C separation
+ * @retval      None
+ *****************************************************************************/
+static void FilterTAPsCoefficient (
+    volatile uint16_t       * const   * fil_reg_address,
+    const vdec_chrfil_tap_t * const     fil2_2d)
+{
+    int32_t             tap_coef;
+    volatile uint16_t * fil_reg;
+    const uint16_t    * taps;
+
+    if (fil2_2d != NULL) {
+        taps = fil2_2d->fil2_2d_f;
+        for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
+            fil_reg = *fil_reg_address;
+            fil_reg_address++;
+            *fil_reg = *taps;
+            taps++;
+        }
+    }
+    return;
+}   /* End of function FilterTAPsCoefficient() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/src/r_vdec_register.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,153 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_register.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDEC_REGISTER_H
+#define R_VDEC_REGISTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDEC register address list */
+typedef struct {
+    volatile uint16_t * adccr1;
+    volatile uint16_t * tgcr1;
+    volatile uint16_t * tgcr2;
+    volatile uint16_t * tgcr3;
+    volatile uint16_t * synscr1;
+    volatile uint16_t * synscr2;
+    volatile uint16_t * synscr3;
+    volatile uint16_t * synscr4;
+    volatile uint16_t * synscr5;
+    volatile uint16_t * hafccr1;
+    volatile uint16_t * hafccr2;
+    volatile uint16_t * hafccr3;
+    volatile uint16_t * vcdwcr1;
+    volatile uint16_t * dcpcr1;
+    volatile uint16_t * dcpcr2;
+    volatile uint16_t * dcpcr3;
+    volatile uint16_t * dcpcr4;
+    volatile uint16_t * dcpcr5;
+    volatile uint16_t * dcpcr6;
+    volatile uint16_t * dcpcr7;
+    volatile uint16_t * dcpcr8;
+    volatile uint16_t * nsdcr;
+    volatile uint16_t * btlcr;
+    volatile uint16_t * btgpcr;
+    volatile uint16_t * acccr1;
+    volatile uint16_t * acccr2;
+    volatile uint16_t * acccr3;
+    volatile uint16_t * tintcr;
+    volatile uint16_t * ycdcr;
+    volatile uint16_t * agccr1;
+    volatile uint16_t * agccr2;
+    volatile uint16_t * pklimitcr;
+    volatile uint16_t * rgorcr1;
+    volatile uint16_t * rgorcr2;
+    volatile uint16_t * rgorcr3;
+    volatile uint16_t * rgorcr4;
+    volatile uint16_t * rgorcr5;
+    volatile uint16_t * rgorcr6;
+    volatile uint16_t * rgorcr7;
+    volatile uint16_t * afcpfcr;
+    volatile uint16_t * rupdcr;
+    volatile uint16_t * vsyncsr;
+    volatile uint16_t * hsyncsr;
+    volatile uint16_t * dcpsr1;
+    volatile uint16_t * dcpsr2;
+    volatile uint16_t * nsdsr;
+    volatile uint16_t * cromasr1;
+    volatile uint16_t * cromasr2;
+    volatile uint16_t * syncssr;
+    volatile uint16_t * agccsr1;
+    volatile uint16_t * agccsr2;
+    volatile uint16_t * ycscr3;
+    volatile uint16_t * ycscr4;
+    volatile uint16_t * ycscr5;
+    volatile uint16_t * ycscr6;
+    volatile uint16_t * ycscr7;
+    volatile uint16_t * ycscr8;
+    volatile uint16_t * ycscr9;
+    volatile uint16_t * ycscr11;
+    volatile uint16_t * ycscr12;
+    volatile uint16_t * dcpcr9;
+    volatile uint16_t * ygaincr;
+    volatile uint16_t * cbgaincr;
+    volatile uint16_t * crgaincr;
+    volatile uint16_t * pga_update;
+    volatile uint16_t * pgacr;
+    volatile uint16_t * adccr2;
+} vdec_reg_address_t;
+
+/*! VDEC register address list (for 2D filter tap coefficient) */
+typedef struct {
+    volatile uint16_t * yctwa_f[VDEC_CHRFIL_TAPCOEF_NUM];
+    volatile uint16_t * yctwb_f[VDEC_CHRFIL_TAPCOEF_NUM];
+    volatile uint16_t * yctna_f[VDEC_CHRFIL_TAPCOEF_NUM];
+    volatile uint16_t * yctnb_f[VDEC_CHRFIL_TAPCOEF_NUM];
+} vdec_filter_reg_address_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdec_reg_address_t         vdec_reg_address[VDEC_CHANNEL_NUM];
+extern const vdec_filter_reg_address_t  vdec_filter_reg_address[VDEC_CHANNEL_NUM];
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDEC_Initialize(const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel);
+void VDEC_ActivePeriod(const vdec_channel_t ch, const vdec_active_period_t * const param);
+void VDEC_SyncSeparation(const vdec_channel_t ch, const vdec_sync_separation_t * const param);
+void VDEC_YcSeparation(const vdec_channel_t ch, const vdec_yc_separation_t * const param);
+void VDEC_ChromaDecoding(const vdec_channel_t ch, const vdec_chroma_decoding_t * const param);
+void VDEC_DigitalClamp(const vdec_channel_t ch, const vdec_degital_clamp_t * const param);
+void VDEC_Output(const vdec_channel_t ch, const vdec_output_t * const param);
+void VDEC_Query(
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp);
+
+
+#endif  /* R_VDEC_REGISTER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/drivers/vdec/src/r_vdec_register_address.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,287 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_register_address.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDEC register address list */
+const vdec_reg_address_t vdec_reg_address[VDEC_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &DVDEC0.ADCCR1,
+        &DVDEC0.TGCR1,
+        &DVDEC0.TGCR2,
+        &DVDEC0.TGCR3,
+        &DVDEC0.SYNSCR1,
+        &DVDEC0.SYNSCR2,
+        &DVDEC0.SYNSCR3,
+        &DVDEC0.SYNSCR4,
+        &DVDEC0.SYNSCR5,
+        &DVDEC0.HAFCCR1,
+        &DVDEC0.HAFCCR2,
+        &DVDEC0.HAFCCR3,
+        &DVDEC0.VCDWCR1,
+        &DVDEC0.DCPCR1,
+        &DVDEC0.DCPCR2,
+        &DVDEC0.DCPCR3,
+        &DVDEC0.DCPCR4,
+        &DVDEC0.DCPCR5,
+        &DVDEC0.DCPCR6,
+        &DVDEC0.DCPCR7,
+        &DVDEC0.DCPCR8,
+        &DVDEC0.NSDCR,
+        &DVDEC0.BTLCR,
+        &DVDEC0.BTGPCR,
+        &DVDEC0.ACCCR1,
+        &DVDEC0.ACCCR2,
+        &DVDEC0.ACCCR3,
+        &DVDEC0.TINTCR,
+        &DVDEC0.YCDCR,
+        &DVDEC0.AGCCR1,
+        &DVDEC0.AGCCR2,
+        &DVDEC0.PKLIMITCR,
+        &DVDEC0.RGORCR1,
+        &DVDEC0.RGORCR2,
+        &DVDEC0.RGORCR3,
+        &DVDEC0.RGORCR4,
+        &DVDEC0.RGORCR5,
+        &DVDEC0.RGORCR6,
+        &DVDEC0.RGORCR7,
+        &DVDEC0.AFCPFCR,
+        &DVDEC0.RUPDCR,
+        &DVDEC0.VSYNCSR,
+        &DVDEC0.HSYNCSR,
+        &DVDEC0.DCPSR1,
+        &DVDEC0.DCPSR2,
+        &DVDEC0.NSDSR,
+        &DVDEC0.CROMASR1,
+        &DVDEC0.CROMASR2,
+        &DVDEC0.SYNCSSR,
+        &DVDEC0.AGCCSR1,
+        &DVDEC0.AGCCSR2,
+        &DVDEC0.YCSCR3,
+        &DVDEC0.YCSCR4,
+        &DVDEC0.YCSCR5,
+        &DVDEC0.YCSCR6,
+        &DVDEC0.YCSCR7,
+        &DVDEC0.YCSCR8,
+        &DVDEC0.YCSCR9,
+        &DVDEC0.YCSCR11,
+        &DVDEC0.YCSCR12,
+        &DVDEC0.DCPCR9,
+        &DVDEC0.YGAINCR,
+        &DVDEC0.CBGAINCR,
+        &DVDEC0.CRGAINCR,
+        &DVDEC0.PGA_UPDATE,
+        &DVDEC0.PGACR,
+        &DVDEC0.ADCCR2
+    },
+    {   /* Channel 1 */
+        &DVDEC1.ADCCR1,
+        &DVDEC1.TGCR1,
+        &DVDEC1.TGCR2,
+        &DVDEC1.TGCR3,
+        &DVDEC1.SYNSCR1,
+        &DVDEC1.SYNSCR2,
+        &DVDEC1.SYNSCR3,
+        &DVDEC1.SYNSCR4,
+        &DVDEC1.SYNSCR5,
+        &DVDEC1.HAFCCR1,
+        &DVDEC1.HAFCCR2,
+        &DVDEC1.HAFCCR3,
+        &DVDEC1.VCDWCR1,
+        &DVDEC1.DCPCR1,
+        &DVDEC1.DCPCR2,
+        &DVDEC1.DCPCR3,
+        &DVDEC1.DCPCR4,
+        &DVDEC1.DCPCR5,
+        &DVDEC1.DCPCR6,
+        &DVDEC1.DCPCR7,
+        &DVDEC1.DCPCR8,
+        &DVDEC1.NSDCR,
+        &DVDEC1.BTLCR,
+        &DVDEC1.BTGPCR,
+        &DVDEC1.ACCCR1,
+        &DVDEC1.ACCCR2,
+        &DVDEC1.ACCCR3,
+        &DVDEC1.TINTCR,
+        &DVDEC1.YCDCR,
+        &DVDEC1.AGCCR1,
+        &DVDEC1.AGCCR2,
+        &DVDEC1.PKLIMITCR,
+        &DVDEC1.RGORCR1,
+        &DVDEC1.RGORCR2,
+        &DVDEC1.RGORCR3,
+        &DVDEC1.RGORCR4,
+        &DVDEC1.RGORCR5,
+        &DVDEC1.RGORCR6,
+        &DVDEC1.RGORCR7,
+        &DVDEC1.AFCPFCR,
+        &DVDEC1.RUPDCR,
+        &DVDEC1.VSYNCSR,
+        &DVDEC1.HSYNCSR,
+        &DVDEC1.DCPSR1,
+        &DVDEC1.DCPSR2,
+        &DVDEC1.NSDSR,
+        &DVDEC1.CROMASR1,
+        &DVDEC1.CROMASR2,
+        &DVDEC1.SYNCSSR,
+        &DVDEC1.AGCCSR1,
+        &DVDEC1.AGCCSR2,
+        &DVDEC1.YCSCR3,
+        &DVDEC1.YCSCR4,
+        &DVDEC1.YCSCR5,
+        &DVDEC1.YCSCR6,
+        &DVDEC1.YCSCR7,
+        &DVDEC1.YCSCR8,
+        &DVDEC1.YCSCR9,
+        &DVDEC1.YCSCR11,
+        &DVDEC1.YCSCR12,
+        &DVDEC1.DCPCR9,
+        &DVDEC1.YGAINCR,
+        &DVDEC1.CBGAINCR,
+        &DVDEC1.CRGAINCR,
+        &DVDEC1.PGA_UPDATE,
+        &DVDEC1.PGACR,
+        &DVDEC1.ADCCR2
+    }
+};
+
+/* VDEC register address list (for 2D filter tap coefficient) */
+const vdec_filter_reg_address_t vdec_filter_reg_address[VDEC_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        {
+            &DVDEC0.YCTWA_F0,
+            &DVDEC0.YCTWA_F1,
+            &DVDEC0.YCTWA_F2,
+            &DVDEC0.YCTWA_F3,
+            &DVDEC0.YCTWA_F4,
+            &DVDEC0.YCTWA_F5,
+            &DVDEC0.YCTWA_F6,
+            &DVDEC0.YCTWA_F7,
+            &DVDEC0.YCTWA_F8
+        },
+        {
+            &DVDEC0.YCTWB_F0,
+            &DVDEC0.YCTWB_F1,
+            &DVDEC0.YCTWB_F2,
+            &DVDEC0.YCTWB_F3,
+            &DVDEC0.YCTWB_F4,
+            &DVDEC0.YCTWB_F5,
+            &DVDEC0.YCTWB_F6,
+            &DVDEC0.YCTWB_F7,
+            &DVDEC0.YCTWB_F8
+        },
+        {
+            &DVDEC0.YCTNA_F0,
+            &DVDEC0.YCTNA_F1,
+            &DVDEC0.YCTNA_F2,
+            &DVDEC0.YCTNA_F3,
+            &DVDEC0.YCTNA_F4,
+            &DVDEC0.YCTNA_F5,
+            &DVDEC0.YCTNA_F6,
+            &DVDEC0.YCTNA_F7,
+            &DVDEC0.YCTNA_F8
+        },
+        {
+            &DVDEC0.YCTNB_F0,
+            &DVDEC0.YCTNB_F1,
+            &DVDEC0.YCTNB_F2,
+            &DVDEC0.YCTNB_F3,
+            &DVDEC0.YCTNB_F4,
+            &DVDEC0.YCTNB_F5,
+            &DVDEC0.YCTNB_F6,
+            &DVDEC0.YCTNB_F7,
+            &DVDEC0.YCTNB_F8
+        }
+    },
+    {   /* Channel 1 */
+        {
+            &DVDEC1.YCTWA_F0,
+            &DVDEC1.YCTWA_F1,
+            &DVDEC1.YCTWA_F2,
+            &DVDEC1.YCTWA_F3,
+            &DVDEC1.YCTWA_F4,
+            &DVDEC1.YCTWA_F5,
+            &DVDEC1.YCTWA_F6,
+            &DVDEC1.YCTWA_F7,
+            &DVDEC1.YCTWA_F8
+        },
+        {
+            &DVDEC1.YCTWB_F0,
+            &DVDEC1.YCTWB_F1,
+            &DVDEC1.YCTWB_F2,
+            &DVDEC1.YCTWB_F3,
+            &DVDEC1.YCTWB_F4,
+            &DVDEC1.YCTWB_F5,
+            &DVDEC1.YCTWB_F6,
+            &DVDEC1.YCTWB_F7,
+            &DVDEC1.YCTWB_F8
+        },
+        {
+            &DVDEC1.YCTNA_F0,
+            &DVDEC1.YCTNA_F1,
+            &DVDEC1.YCTNA_F2,
+            &DVDEC1.YCTNA_F3,
+            &DVDEC1.YCTNA_F4,
+            &DVDEC1.YCTNA_F5,
+            &DVDEC1.YCTNA_F6,
+            &DVDEC1.YCTNA_F7,
+            &DVDEC1.YCTNA_F8
+        },
+        {
+            &DVDEC1.YCTNB_F0,
+            &DVDEC1.YCTNB_F1,
+            &DVDEC1.YCTNB_F2,
+            &DVDEC1.YCTNB_F3,
+            &DVDEC1.YCTNB_F4,
+            &DVDEC1.YCTNB_F5,
+            &DVDEC1.YCTNB_F6,
+            &DVDEC1.YCTNB_F7,
+            &DVDEC1.YCTNB_F8
+        }
+    }
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/gr_peach_vdc5.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1520 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         gr_peach_vdc5.c
+* @version
+* $Rev:
+* $Date::
+* @brief        VDC5 driver API wrapper function in C interface
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <string.h>
+
+#include    "r_typedefs.h"
+#include    "r_vdc5.h"
+#include    "video_decoder.h"
+#include    "lvds_pll_calc.h"
+#include    "gr_board_vdc5.h"
+#include    "r_ceu.h"
+
+#include    "mbed_assert.h"
+#include    "pinmap.h"
+#include    "RZ_A1_Init.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define STP91_BIT   (0x02u)
+#define STP90_BIT   (0x01u)
+#define STBRQ25_BIT (0x20u)
+#define STBAK25_BIT (0x20u)
+#define STBRQ24_BIT (0x10u)
+#define STBAK24_BIT (0x10u)
+#define CLUT8_TABLE_NUM         (256u)
+#define CLUT4_TABLE_NUM         (16u)
+#define CLUT1_TABLE_NUM         (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef enum {
+    VDC5_CH0,
+    VDC5_CH1,
+} VDC5Name;
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+static const PinMap PinMap_DV_INPUT_PIN[] = {
+    {P8_11 , VDC5_CH0, 8}, /* DV0_CLK    */
+    {P10_0 , VDC5_CH0, 1}, /* DV0_CLK    */
+    {P1_12 , VDC5_CH0, 2}, /* DV0_VSYNC  */
+    {P1_13 , VDC5_CH0, 2}, /* DV0_HSYNC  */
+    {P1_1  , VDC5_CH0, 6}, /* DV0_HSYNC  */
+    {P1_0  , VDC5_CH0, 6}, /* DV0_VSYNC  */
+    {P1_9  , VDC5_CH0, 6}, /* DV0_DATA15 */
+    {P2_15 , VDC5_CH0, 3}, /* DV0_DATA15 */
+    {P4_7  , VDC5_CH0, 7}, /* DV0_DATA15 */
+    {P5_7  , VDC5_CH0, 4}, /* DV0_DATA15 */
+    {P1_8  , VDC5_CH0, 6}, /* DV0_DATA14 */
+    {P2_14 , VDC5_CH0, 3}, /* DV0_DATA14 */
+    {P4_6  , VDC5_CH0, 7}, /* DV0_DATA14 */
+    {P5_6  , VDC5_CH0, 4}, /* DV0_DATA14 */
+    {P1_7  , VDC5_CH0, 6}, /* DV0_DATA13 */
+    {P2_13 , VDC5_CH0, 3}, /* DV0_DATA13 */
+    {P4_5  , VDC5_CH0, 7}, /* DV0_DATA13 */
+    {P5_5  , VDC5_CH0, 4}, /* DV0_DATA13 */
+    {P1_6  , VDC5_CH0, 6}, /* DV0_DATA12 */
+    {P4_4  , VDC5_CH0, 7}, /* DV0_DATA12 */
+    {P5_4  , VDC5_CH0, 4}, /* DV0_DATA12 */
+    {P10_5 , VDC5_CH0, 1}, /* DV0_DATA11 */
+    {P2_10 , VDC5_CH0, 3}, /* DV0_DATA10 */
+    {P10_14, VDC5_CH0, 1}, /* DV0_DATA10 */
+    {P2_9  , VDC5_CH0, 3}, /* DV0_DATA9  */
+    {P10_13, VDC5_CH0, 1}, /* DV0_DATA9  */
+    {P10_12, VDC5_CH0, 1}, /* DV0_DATA8  */
+    {P2_7  , VDC5_CH0, 3}, /* DV0_DATA7  */
+    {P2_6  , VDC5_CH0, 3}, /* DV0_DATA6  */
+    {P2_5  , VDC5_CH0, 3}, /* DV0_DATA5  */
+    {P2_4  , VDC5_CH0, 3}, /* DV0_DATA4  */
+    {P2_3  , VDC5_CH0, 3}, /* DV0_DATA3  */
+    {P2_2  , VDC5_CH0, 3}, /* DV0_DATA2  */
+    {P2_1  , VDC5_CH0, 3}, /* DV0_DATA1  */
+    {P2_0  , VDC5_CH0, 3}, /* DV0_DATA0  */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_CEU_PIN[] = {
+    {P1_5  , 0, 5}, /* VIO_CLK    */
+    {P10_0 , 0, 6}, /* VIO_CLK    */
+    {P1_0  , 0, 5}, /* VIO_VD     */
+    {P10_1 , 0, 6}, /* VIO_VD     */
+    {P1_1  , 0, 5}, /* VIO_HD     */
+    {P10_2 , 0, 6}, /* VIO_HD     */
+    {P2_7  , 0, 7}, /* VIO_D7     */
+    {P10_11, 0, 6}, /* VIO_D7     */
+    {P2_6  , 0, 7}, /* VIO_D6     */
+    {P10_10, 0, 6}, /* VIO_D6     */
+    {P2_5  , 0, 7}, /* VIO_D5     */
+    {P10_9 , 0, 6}, /* VIO_D5     */
+    {P2_4  , 0, 7}, /* VIO_D4     */
+    {P10_8 , 0, 6}, /* VIO_D4     */
+    {P2_3  , 0, 7}, /* VIO_D3     */
+    {P10_7 , 0, 6}, /* VIO_D3     */
+    {P2_2  , 0, 7}, /* VIO_D2     */
+    {P10_6 , 0, 6}, /* VIO_D2     */
+    {P2_1  , 0, 7}, /* VIO_D1     */
+    {P10_5 , 0, 6}, /* VIO_D1     */
+    {P2_0  , 0, 7}, /* VIO_D0     */
+    {P10_4 , 0, 6}, /* VIO_D0     */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_LCD_DISP_PIN[] = {
+    {P2_7  , VDC5_CH0, 8}, /* LCD0_DATA23  */
+    {P5_7  , VDC5_CH0, 3}, /* LCD0_DATA23  */
+    {P10_0 , VDC5_CH0, 5}, /* LCD0_DATA23  */
+    {P2_6  , VDC5_CH0, 8}, /* LCD0_DATA22  */
+    {P5_6  , VDC5_CH0, 3}, /* LCD0_DATA22  */
+    {P10_1 , VDC5_CH0, 5}, /* LCD0_DATA22  */
+    {P2_5  , VDC5_CH0, 8}, /* LCD0_DATA21  */
+    {P5_5  , VDC5_CH0, 3}, /* LCD0_DATA21  */
+    {P10_2 , VDC5_CH0, 5}, /* LCD0_DATA21  */
+    {P2_4  , VDC5_CH0, 8}, /* LCD0_DATA20  */
+    {P5_4  , VDC5_CH0, 3}, /* LCD0_DATA20  */
+    {P10_3 , VDC5_CH0, 5}, /* LCD0_DATA20  */
+    {P2_3  , VDC5_CH0, 8}, /* LCD0_DATA19  */
+    {P5_3  , VDC5_CH0, 3}, /* LCD0_DATA19  */
+    {P10_4 , VDC5_CH0, 5}, /* LCD0_DATA19  */
+    {P2_2  , VDC5_CH0, 8}, /* LCD0_DATA18  */
+    {P5_2  , VDC5_CH0, 3}, /* LCD0_DATA18  */
+    {P10_5 , VDC5_CH0, 5}, /* LCD0_DATA18  */
+    {P2_1  , VDC5_CH0, 8}, /* LCD0_DATA17  */
+    {P5_1  , VDC5_CH0, 3}, /* LCD0_DATA17  */
+    {P10_7 , VDC5_CH0, 5}, /* LCD0_DATA17  */
+    {P2_0  , VDC5_CH0, 8}, /* LCD0_DATA16  */
+    {P5_0  , VDC5_CH0, 3}, /* LCD0_DATA16  */
+    {P10_6 , VDC5_CH0, 5}, /* LCD0_DATA16  */
+    {P4_7  , VDC5_CH0, 1}, /* LCD0_DATA15  */
+    {P10_8 , VDC5_CH0, 5}, /* LCD0_DATA15  */
+    {P4_6  , VDC5_CH0, 1}, /* LCD0_DATA14  */
+    {P10_9 , VDC5_CH0, 5}, /* LCD0_DATA14  */
+    {P4_5  , VDC5_CH0, 1}, /* LCD0_DATA13  */
+    {P10_10, VDC5_CH0, 5}, /* LCD0_DATA13  */
+    {P4_4  , VDC5_CH0, 1}, /* LCD0_DATA12  */
+    {P10_11, VDC5_CH0, 5}, /* LCD0_DATA12  */
+    {P10_12, VDC5_CH0, 5}, /* LCD0_DATA11  */
+    {P10_13, VDC5_CH0, 5}, /* LCD0_DATA10  */
+    {P10_14, VDC5_CH0, 5}, /* LCD0_DATA9   */
+    {P4_0  , VDC5_CH0, 1}, /* LCD0_DATA8   */
+    {P10_15, VDC5_CH0, 5}, /* LCD0_DATA8   */
+    {P3_15 , VDC5_CH0, 1}, /* LCD0_DATA7   */
+    {P11_0 , VDC5_CH0, 5}, /* LCD0_DATA7   */
+    {P3_14 , VDC5_CH0, 1}, /* LCD0_DATA6   */
+    {P11_1 , VDC5_CH0, 5}, /* LCD0_DATA6   */
+    {P3_13 , VDC5_CH0, 1}, /* LCD0_DATA5   */
+    {P11_2 , VDC5_CH0, 5}, /* LCD0_DATA5   */
+    {P3_12 , VDC5_CH0, 1}, /* LCD0_DATA4   */
+    {P11_3 , VDC5_CH0, 5}, /* LCD0_DATA4   */
+    {P3_11 , VDC5_CH0, 1}, /* LCD0_DATA3   */
+    {P11_4 , VDC5_CH0, 5}, /* LCD0_DATA3   */
+    {P3_10 , VDC5_CH0, 1}, /* LCD0_DATA2   */
+    {P11_5 , VDC5_CH0, 5}, /* LCD0_DATA2   */
+    {P3_9  , VDC5_CH0, 1}, /* LCD0_DATA1   */
+    {P11_6 , VDC5_CH0, 5}, /* LCD0_DATA1   */
+    {P3_8  , VDC5_CH0, 1}, /* LCD0_DATA0   */
+    {P11_7 , VDC5_CH0, 5}, /* LCD0_DATA0   */
+    {P11_10, VDC5_CH0, 5}, /* LCD0_TCON4   */
+    {P11_11, VDC5_CH0, 5}, /* LCD0_TCON3   */
+    {P11_12, VDC5_CH0, 5}, /* LCD0_TCON2   */
+    {P3_2  , VDC5_CH0, 1}, /* LCD0_TCON1   */
+    {P11_13, VDC5_CH0, 5}, /* LCD0_TCON1   */
+    {P11_14, VDC5_CH0, 5}, /* LCD0_TCON0   */
+    {P11_15, VDC5_CH0, 5}, /* LCD0_CLK     */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_LVDS_DISP_PIN[] = {
+    {P5_7  , VDC5_CH0, 1}, /* TXOUT0M   */
+    {P5_6  , VDC5_CH0, 1}, /* TXOUT0P   */
+    {P5_5  , VDC5_CH0, 1}, /* TXOUT1M   */
+    {P5_4  , VDC5_CH0, 1}, /* TXOUT1P   */
+    {P5_3  , VDC5_CH0, 1}, /* TXOUT2M   */
+    {P5_2  , VDC5_CH0, 1}, /* TXOUT2P   */
+    {P5_1  , VDC5_CH0, 1}, /* TXCLKOUTM */
+    {P5_0  , VDC5_CH0, 1}, /* TXCLKOUTP */
+    {NC    , NC   , 0}
+};
+
+static const IRQn_Type vdc5_irq_set_tbl[] = {
+    S0_VI_VSYNC0_IRQn,
+    S0_LO_VSYNC0_IRQn,
+    S0_VSYNCERR0_IRQn,
+    GR3_VLINE0_IRQn,
+    S0_VFIELD0_IRQn,
+    IV1_VBUFERR0_IRQn,
+    IV3_VBUFERR0_IRQn,
+    IV5_VBUFERR0_IRQn,
+    IV6_VBUFERR0_IRQn,
+    S0_WLINE0_IRQn,
+    S1_VI_VSYNC0_IRQn,
+    S1_LO_VSYNC0_IRQn,
+    S1_VSYNCERR0_IRQn,
+    S1_VFIELD0_IRQn,
+    IV2_VBUFERR0_IRQn,
+    IV4_VBUFERR0_IRQn,
+    S1_WLINE0_IRQn,
+    OIR_VI_VSYNC0_IRQn,
+    OIR_LO_VSYNC0_IRQn,
+    OIR_VSYNCERR0_IRQn,
+    OIR_VFIELD0_IRQn,
+    IV7_VBUFERR0_IRQn,
+    IV8_VBUFERR0_IRQn
+};
+
+static const uint32_t color_table256[CLUT8_TABLE_NUM] = {
+  0xFF000000u, 0xFF010101u, 0xFF020202u, 0xFF030303u, 0xFF040404u, 0xFF050505u, 0xFF060606u, 0xFF070707u, /*   0 -   7 */
+  0xFF080808u, 0xFF090909u, 0xFF0A0A0Au, 0xFF0B0B0Bu, 0xFF0C0C0Cu, 0xFF0D0D0Du, 0xFF0E0E0Eu, 0xFF0F0F0Fu, /*   8 -  15 */
+  0xFF101010u, 0xFF111111u, 0xFF121212u, 0xFF131313u, 0xFF141414u, 0xFF151515u, 0xFF161616u, 0xFF171717u, /*  16 -  23 */
+  0xFF181818u, 0xFF191919u, 0xFF1A1A1Au, 0xFF1B1B1Bu, 0xFF1C1C1Cu, 0xFF1E1E1Eu, 0xFF1E1E1Eu, 0xFF1F1F1Fu, /*  24 -  31 */
+  0xFF202020u, 0xFF212121u, 0xFF222222u, 0xFF232323u, 0xFF242424u, 0xFF252525u, 0xFF262626u, 0xFF272727u, /*  32 -  39 */
+  0xFF282828u, 0xFF292929u, 0xFF2A2A2Au, 0xFF2B2B2Bu, 0xFF2C2C2Cu, 0xFF2E2E2Eu, 0xFF2E2E2Eu, 0xFF2F2F2Fu, /*  40 -  47 */
+  0xFF303030u, 0xFF313131u, 0xFF323232u, 0xFF333333u, 0xFF343434u, 0xFF353535u, 0xFF363636u, 0xFF373737u, /*  48 -  55 */
+  0xFF383838u, 0xFF393939u, 0xFF3A3A3Au, 0xFF3B3B3Bu, 0xFF3C3C3Cu, 0xFF3E3E3Eu, 0xFF3E3E3Eu, 0xFF3F3F3Fu, /*  56 -  63 */
+  0xFF404040u, 0xFF414141u, 0xFF424242u, 0xFF434343u, 0xFF444444u, 0xFF454545u, 0xFF464646u, 0xFF474747u, /*  64 -  71 */
+  0xFF484848u, 0xFF494949u, 0xFF4A4A4Au, 0xFF4B4B4Bu, 0xFF4C4C4Cu, 0xFF4E4E4Eu, 0xFF4E4E4Eu, 0xFF4F4F4Fu, /*  72 -  79 */
+  0xFF505050u, 0xFF515151u, 0xFF525252u, 0xFF535353u, 0xFF545454u, 0xFF555555u, 0xFF565656u, 0xFF575757u, /*  80 -  87 */
+  0xFF585858u, 0xFF595959u, 0xFF5A5A5Au, 0xFF5B5B5Bu, 0xFF5C5C5Cu, 0xFF5E5E5Eu, 0xFF5E5E5Eu, 0xFF5F5F5Fu, /*  88 -  95 */
+  0xFF606060u, 0xFF616161u, 0xFF626262u, 0xFF636363u, 0xFF646464u, 0xFF656565u, 0xFF666666u, 0xFF676767u, /*  96 - 103 */
+  0xFF686868u, 0xFF696969u, 0xFF6A6A6Au, 0xFF6B6B6Bu, 0xFF6C6C6Cu, 0xFF6E6E6Eu, 0xFF6E6E6Eu, 0xFF6F6F6Fu, /* 104 - 111 */
+  0xFF707070u, 0xFF717171u, 0xFF727272u, 0xFF737373u, 0xFF747474u, 0xFF757575u, 0xFF767676u, 0xFF777777u, /* 112 - 119 */
+  0xFF787878u, 0xFF797979u, 0xFF7A7A7Au, 0xFF7B7B7Bu, 0xFF7C7C7Cu, 0xFF7E7E7Eu, 0xFF7E7E7Eu, 0xFF7F7F7Fu, /* 120 - 127 */
+  0xFF808080u, 0xFF818181u, 0xFF828282u, 0xFF838383u, 0xFF848484u, 0xFF858585u, 0xFF868686u, 0xFF878787u, /* 128 - 135 */
+  0xFF888888u, 0xFF898989u, 0xFF8A8A8Au, 0xFF8B8B8Bu, 0xFF8C8C8Cu, 0xFF8E8E8Eu, 0xFF8E8E8Eu, 0xFF8F8F8Fu, /* 136 - 143 */
+  0xFF909090u, 0xFF919191u, 0xFF929292u, 0xFF939393u, 0xFF949494u, 0xFF959595u, 0xFF969696u, 0xFF979797u, /* 144 - 151 */
+  0xFF989898u, 0xFF999999u, 0xFF9A9A9Au, 0xFF9B9B9Bu, 0xFF9C9C9Cu, 0xFF9E9E9Eu, 0xFF9E9E9Eu, 0xFF9F9F9Fu, /* 152 - 159 */
+  0xFFA0A0A0u, 0xFFA1A1A1u, 0xFFA2A2A2u, 0xFFA3A3A3u, 0xFFA4A4A4u, 0xFFA5A5A5u, 0xFFA6A6A6u, 0xFFA7A7A7u, /* 160 - 167 */
+  0xFFA8A8A8u, 0xFFA9A9A9u, 0xFFAAAAAAu, 0xFFABABABu, 0xFFACACACu, 0xFFAEAEAEu, 0xFFAEAEAEu, 0xFFAFAFAFu, /* 168 - 175 */
+  0xFFB0B0B0u, 0xFFB1B1B1u, 0xFFB2B2B2u, 0xFFB3B3B3u, 0xFFB4B4B4u, 0xFFB5B5B5u, 0xFFB6B6B6u, 0xFFB7B7B7u, /* 176 - 183 */
+  0xFFB8B8B8u, 0xFFB9B9B9u, 0xFFBABABAu, 0xFFBBBBBBu, 0xFFBCBCBCu, 0xFFBEBEBEu, 0xFFBEBEBEu, 0xFFBFBFBFu, /* 184 - 191 */
+  0xFFC0C0C0u, 0xFFC1C1C1u, 0xFFC2C2C2u, 0xFFC3C3C3u, 0xFFC4C4C4u, 0xFFC5C5C5u, 0xFFC6C6C6u, 0xFFC7C7C7u, /* 192 - 199 */
+  0xFFC8C8C8u, 0xFFC9C9C9u, 0xFFCACACAu, 0xFFCBCBCBu, 0xFFCCCCCCu, 0xFFCECECEu, 0xFFCECECEu, 0xFFCFCFCFu, /* 200 - 207 */
+  0xFFD0D0D0u, 0xFFD1D1D1u, 0xFFD2D2D2u, 0xFFD3D3D3u, 0xFFD4D4D4u, 0xFFD5D5D5u, 0xFFD6D6D6u, 0xFFD7D7D7u, /* 208 - 215 */
+  0xFFD8D8D8u, 0xFFD9D9D9u, 0xFFDADADAu, 0xFFDBDBDBu, 0xFFDCDCDCu, 0xFFDEDEDEu, 0xFFDEDEDEu, 0xFFDFDFDFu, /* 216 - 223 */
+  0xFFE0E0E0u, 0xFFE1E1E1u, 0xFFE2E2E2u, 0xFFE3E3E3u, 0xFFE4E4E4u, 0xFFE5E5E5u, 0xFFE6E6E6u, 0xFFE7E7E7u, /* 224 - 231 */
+  0xFFE8E8E8u, 0xFFE9E9E9u, 0xFFEAEAEAu, 0xFFEBEBEBu, 0xFFECECECu, 0xFFEEEEEEu, 0xFFEEEEEEu, 0xFFEFEFEFu, /* 232 - 239 */
+  0xFFF0F0F0u, 0xFFF1F1F1u, 0xFFF2F2F2u, 0xFFF3F3F3u, 0xFFF4F4F4u, 0xFFF5F5F5u, 0xFFF6F6F6u, 0xFFF7F7F7u, /* 240 - 247 */
+  0xFFF8F8F8u, 0xFFF9F9F9u, 0xFFFAFAFAu, 0xFFFBFBFBu, 0xFFFCFCFCu, 0xFFFEFEFEu, 0xFFFEFEFEu, 0xFFFFFFFFu  /* 248 - 255 */
+};
+
+static const uint32_t color_table16[CLUT4_TABLE_NUM] = {
+  0xFF000000u, 0xFF111111u, 0xFF222222u, 0xFF333333u, 0xFF444444u, 0xFF555555u, 0xFF666666u, 0xFF777777u, /*   0 -   7 */
+  0xFF888888u, 0xFF999999u, 0xFFAAAAAAu, 0xFFBBBBBBu, 0xFFCCCCCCu, 0xFFDDDDDDu, 0xFFEEEEEEu, 0xFFFFFFFFu  /*   8 -  15 */
+};
+
+static const uint32_t color_table2[CLUT1_TABLE_NUM] = {
+  0xFF000000u, 0xFFFFFFFFu
+};
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static drv_video_input_sel_t _drv_video_input_sel;
+
+static void init_func (const uint32_t user_num);
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable);
+
+/**************************************************************************//**
+ * @brief       User-defined function within R_VDC5_Initialize
+ * @param[in]   user_num                : VDC5 channel
+ * @retval      None
+******************************************************************************/
+static void init_func (const uint32_t user_num)
+{
+    uint32_t            reg_data;
+    volatile uint8_t    dummy_read;
+
+    if ((vdc5_channel_t)user_num == VDC5_CHANNEL_0) {
+
+        /* Standby control register 9 (STBCR9)
+            b1      ------0-;  MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
+        reg_data    = (uint32_t)CPG.STBCR9 & (uint32_t)~STP91_BIT;
+        CPG.STBCR9  = (uint8_t)reg_data;
+        /* In order to reflect the change, a dummy read should be done. */
+        dummy_read = CPG.STBCR9;
+
+        /* Standby Request Register 2 (STBREQ2)
+            b5      --0-----;  STBRQ25 : The standby request to VDC5 channel 0 is invalid. */
+        reg_data    = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ25_BIT;
+        CPG.STBREQ2 = (uint8_t)reg_data;
+        /* Standby Acknowledge Register 2 (STBACK2)
+            b5      --*-----;  STBAK25 : Standby acknowledgement from VDC5 channel 0. */
+        while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK25_BIT) != 0u) {
+            /* Wait for the STBAK25 to be cleared to 0. */
+        }
+
+        /* Standby control register 9 (STBCR9)
+            b0      -------0;  MSTP90 : 0 : Video display controller channel 1 enable */
+        reg_data    = (uint32_t)CPG.STBCR9 & (uint32_t)~(STP91_BIT|STP90_BIT);
+        CPG.STBCR9  = (uint8_t)reg_data;
+        /* In order to reflect the change, a dummy read should be done. */
+        dummy_read = CPG.STBCR9;
+        (void)dummy_read; /* unused */
+
+        /* Standby Request Register 2 (STBREQ2)
+            b4      ---0----;  STBRQ24 : The standby request to VDC5 channel 1 is invalid. */
+        reg_data    = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ24_BIT;
+        CPG.STBREQ2 = (uint8_t)reg_data;
+        /* Standby Acknowledge Register 2 (STBACK2)
+            b4      ---*----;  STBAK24 : Standby acknowledgement from VDC5 channel 1. */
+        while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK24_BIT) != 0u) {
+            /* Wait for the STBAK24 to be cleared to 0. */
+        }
+    }
+}   /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   enable                  : VDC5 interrupt enable
+ * @retval      None
+******************************************************************************/
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable)
+{
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    IRQn_Type IRQn;
+    IRQHandler handler;
+
+    IRQn = vdc5_irq_set_tbl[irq];
+    handler = R_VDC5_GetISR(ch, irq);
+
+    if (enable) {
+        InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+        GIC_SetPriority(IRQn, 5);
+        GIC_EnableIRQ(IRQn);
+    } else {
+        GIC_DisableIRQ(IRQn);
+    }
+} /* End of function DRV_Graphics_Irq_Set() */
+
+static void (* ceu_callback_func)(vdc5_int_type_t);
+static void Ceu_Irq_Handler_wrapper(ceu_int_type_t ceu_int_type) {
+    if ((ceu_callback_func != NULL) && ((ceu_int_type & CEU_INT_CPEIE) != 0)) {
+        ceu_callback_func(VDC5_INT_TYPE_S0_VFIELD);
+    }
+}
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   num                     : Interrupt line number
+ * @param[in]   * callback              : Interrupt callback function pointer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(
+    vdc5_int_type_t irq,
+    uint16_t num,
+    void (* callback)(vdc5_int_type_t)  )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+
+    if ((_drv_video_input_sel == DRV_INPUT_SEL_CEU) && (irq == VDC5_INT_TYPE_S0_VFIELD)) {
+        /* ceu wrapper */
+        if( callback == NULL ) {
+            R_CEU_InterruptDisable();
+            ceu_callback_func = NULL;
+        } else {
+            ceu_callback_func = callback;
+            R_CEU_InterruptEnable(CEU_INT_CPEIE, &Ceu_Irq_Handler_wrapper);
+        }
+    } else {
+        vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+        vdc5_error_t            error;
+        vdc5_int_t              interrupt;
+
+        if( callback == NULL ) {
+            DRV_Graphics_Irq_Set( irq, 0 );
+        } else {
+            DRV_Graphics_Irq_Set( irq, 1 );
+        }
+
+        /* Interrupt parameter */
+        interrupt.type      = irq;        /* Interrupt type */
+        interrupt.line_num  = num ;       /* Line number */
+
+        /* Interrupt parameter */
+        interrupt.callback = callback;    /* Callback function pointer */
+        /* Set interrupt service routine */
+        error = R_VDC5_CallbackISR(ch, &interrupt);
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error ;
+} /* End of function DRV_Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief       LCD output port initialization processing
+ * @param[in]   pin                     : Pin assign for LCD output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
+        pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       LVDS output port initialization processing
+ * @param[in]   pin                     : Pin assign for LVDS output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN);
+        pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Digital video inpout port initialization processing
+ * @param[in]   pin                     : Pin assign for digital video input port
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
+        pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       CEU inpout port initialization processing
+ * @param[in]   pin                     : Pin assign for digital video input port
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_CEU_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_CEU_PIN);
+        pinmap_pinout(pin[count], PinMap_CEU_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_CEU_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Graphics initialization processing
+ * @param[in]   drv_lcd_config          : LCD configuration
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_init_t             init;
+    vdc5_lvds_t             vdc5_lvds;
+    pll_parameter_t         pll_parameter;
+    double                  InputClock;
+    double                  OutputClock  = DEFAULT_OUTPUT_CLOCK;
+    uint32_t                LvdsUsed     = LVDS_IF_USE;
+
+    /* Initialization parameter */
+    init.panel_icksel   = VDC5_PANEL_ICKSEL_LVDS;      /* Panel clock select */
+    init.panel_dcdr     = VDC5_PANEL_CLKDIV_1_1;       /* Panel clock frequency division ratio */
+
+    if (RZ_A1_IsClockMode0() == false) {
+        InputClock = CM1_RENESAS_RZ_A1_P1_CLK / 1000000;
+    } else {
+        InputClock = CM0_RENESAS_RZ_A1_P1_CLK / 1000000;
+    }
+
+    if( drv_lcd_config != NULL ) {
+        OutputClock = drv_lcd_config->outputClock;
+
+        /* LVDS PLL Setting Calculation */
+        if( drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS ) {
+            LvdsUsed = LVDS_IF_USE;
+            init.panel_icksel   = VDC5_PANEL_ICKSEL_LVDS_DIV7;      /* Panel clock select */
+        } else {
+            LvdsUsed = LVDS_IF_NOT_USE;
+        }
+    }
+    lvds_pll_calc( InputClock, OutputClock, LvdsUsed, &pll_parameter );
+
+    vdc5_lvds.lvds_in_clk_sel  = VDC5_LVDS_INCLK_SEL_PERI; /* P1 */
+    vdc5_lvds.lvds_idiv_set    = (vdc5_lvds_ndiv_t)pll_parameter.nidiv;
+    vdc5_lvds.lvdspll_tst      = 16u;
+    vdc5_lvds.lvds_odiv_set    = (vdc5_lvds_ndiv_t)pll_parameter.nodiv;
+    vdc5_lvds.lvdspll_tst      = 16u;
+    vdc5_lvds.lvds_vdc_sel     = ch;
+    vdc5_lvds.lvdspll_fd       = pll_parameter.nfd;
+    vdc5_lvds.lvdspll_rd       = pll_parameter.nrd;
+    vdc5_lvds.lvdspll_od       = (vdc5_lvds_pll_nod_t)pll_parameter.nod;
+    init.lvds                  = &vdc5_lvds;               /* LVDS parameter */
+
+    /* Initialize (Set module clock to VDC5) */
+    error = R_VDC5_Initialize( ch, &init, &init_func, (uint32_t)ch );
+    if (error != VDC5_OK) {
+        drv_error = DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    if ( drv_error == DRV_GRAPHICS_OK ) {
+        vdc5_sync_ctrl_t        sync_ctrl;
+
+        /* Sync signal control */
+        sync_ctrl.res_vs_sel    = VDC5_ON;                              /* Vsync signal output select (free-running Vsync on/off control) */
+        /* Sync signal output and full-screen enable signal select */
+        sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;
+        sync_ctrl.res_fv        = drv_lcd_config->v_toatal_period-1;    /* Free-running Vsync period setting */
+        sync_ctrl.res_fh        = drv_lcd_config->h_toatal_period-1;    /* Hsync period setting */
+        sync_ctrl.res_vsdly     = (uint16_t)0u;                         /* Vsync signal delay control */
+        /* Full-screen enable control */
+        sync_ctrl.res_f.vs      = (drv_lcd_config->v_back_porch);
+        sync_ctrl.res_f.vw      = (drv_lcd_config->v_disp_widht);
+        sync_ctrl.res_f.hs      = (drv_lcd_config->h_back_porch);
+        sync_ctrl.res_f.hw      = (drv_lcd_config->h_disp_widht);
+        sync_ctrl.vsync_cpmpe   = NULL;                                 /* Vsync signal compensation */
+        /* Sync control */
+        error = R_VDC5_SyncControl( ch, &sync_ctrl );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+
+    if ( drv_error == DRV_GRAPHICS_OK ) {
+        vdc5_output_t           output;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_VS;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_VE;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_HS;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_HE;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_DE;
+
+        /* Output parameter */
+        output.tcon_half        = (drv_lcd_config->h_toatal_period-1)/2; /* TCON reference timing, 1/2fH timing */
+        output.tcon_offset      = 0;                                     /* TCON reference timing, offset Hsync signal timing */
+
+        /* LCD TCON timing setting */
+        if( drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_VS.tcon_hsvs   = 0u;
+            lcd_tcon_timing_VS.tcon_hwvw   = (drv_lcd_config->v_sync_width * 2u);
+            lcd_tcon_timing_VS.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_VS.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->v_sync_port_polarity;
+            lcd_tcon_timing_VS.tcon_pin    = (vdc5_lcd_tcon_pin_t)drv_lcd_config->v_sync_port;
+            lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = &lcd_tcon_timing_VS;  /* STVA/VS: Vsync      */
+        } else {
+            output.outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = NULL;                 /* STVA/VS: Vsync      */
+        }
+
+        if( drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_HS.tcon_hsvs   = 0u;
+            lcd_tcon_timing_HS.tcon_hwvw   = drv_lcd_config->h_sync_width;
+            lcd_tcon_timing_HS.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_HS.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->h_sync_port_polarity;
+            lcd_tcon_timing_HS.tcon_pin    = (vdc5_lcd_tcon_pin_t)drv_lcd_config->h_sync_port;
+            lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS]   = &lcd_tcon_timing_HS;  /* STH/SP/HS: Hsync       */
+        } else {
+            output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS]   = NULL;                 /* STH/SP/HS: Hsync       */
+        }
+
+        if( drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_VE.tcon_hsvs   = (drv_lcd_config->v_back_porch * 2u);
+            lcd_tcon_timing_VE.tcon_hwvw   = (drv_lcd_config->v_disp_widht * 2u);
+            lcd_tcon_timing_VE.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_VE.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_VE.tcon_pin    = VDC5_LCD_TCON_PIN_NON;
+            lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = &lcd_tcon_timing_VE;  /* STVB/VE: Not used   */
+
+            lcd_tcon_timing_HE.tcon_hsvs   = drv_lcd_config->h_back_porch;
+            lcd_tcon_timing_HE.tcon_hwvw   = drv_lcd_config->h_disp_widht;
+            lcd_tcon_timing_HE.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_HE.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_HE.tcon_pin    = VDC5_LCD_TCON_PIN_NON;
+            lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE;  /* STB/LP/HE: Not used */
+
+            lcd_tcon_timing_DE.tcon_hsvs   = 0u;
+            lcd_tcon_timing_DE.tcon_hwvw   = 0u;
+            lcd_tcon_timing_DE.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_DE.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_DE.tcon_pin    = (vdc5_lcd_tcon_pin_t)drv_lcd_config->de_port;
+            lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_DE]   = &lcd_tcon_timing_DE;  /* DE      */
+        } else {
+            output.outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;            /* STVB/VE: Not used   */
+            output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;            /* STB/LP/HE: Not used */
+            output.outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;            /* DE                  */
+        }
+
+        output.outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;
+        output.outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;
+        output.outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;
+
+        output.outcnt_lcd_edge  = (vdc5_edge_t)drv_lcd_config->lcd_edge;  /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+        output.out_endian_on    = VDC5_OFF;                               /* Bit endian change on/off control */
+        output.out_swap_on      = VDC5_OFF;                               /* B/R signal swap on/off control */
+        output.out_format       = (vdc5_lcd_outformat_t)drv_lcd_config->lcd_outformat;    /* Output format select */
+        output.out_frq_sel      = VDC5_LCD_PARALLEL_CLKFRQ_1;             /* Clock frequency control */
+        output.out_dir_sel      = VDC5_LCD_SERIAL_SCAN_FORWARD;           /* Scan direction select */
+        output.out_phase        = VDC5_LCD_SERIAL_CLKPHASE_0;             /* Clock phase adjustment */
+        output.bg_color         = (uint32_t)0x00000000u;                  /* Background color in 24-bit RGB color format */
+        /* Display output */
+        error = R_VDC5_DisplayOutput( ch, &output );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Init() */
+
+/**************************************************************************//**
+ * @brief       Video initialization processing
+ * @param[in]   drv_video_ext_in_config   : Video configuration
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_error_t            error;
+    vdc5_input_t            input;
+    vdc5_ext_in_sig_t       ext_in_sig;
+    vdc5_sync_delay_t       sync_delay;
+
+    if ((drv_video_input_sel != DRV_INPUT_SEL_VDEC)
+     && (drv_video_input_sel != DRV_INPUT_SEL_EXT)
+     && (drv_video_input_sel != DRV_INPUT_SEL_CEU)) {
+        return DRV_GRAPHICS_VDC5_ERR;
+    }
+    _drv_video_input_sel = drv_video_input_sel;
+
+    if (drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Initialize(&R_CEU_OnInitialize, 0);
+        return DRV_GRAPHICS_OK;
+    }
+
+    input.inp_sel   = (vdc5_input_sel_t)drv_video_input_sel; /* Input select */
+    input.inp_fh50  = (uint16_t)VSYNC_1_2_FH_TIMING;         /* Vsync signal 1/2fH phase timing */
+    input.inp_fh25  = (uint16_t)VSYNC_1_4_FH_TIMING;         /* Vsync signal 1/4fH phase timing */
+
+    if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
+        input.dly       = NULL;                      /* Sync signal delay adjustment */
+        input.ext_sig   = NULL;                      /* External input signal        */
+    } else {
+        ext_in_sig.inp_format     = (vdc5_extin_format_t)drv_video_ext_in_config->inp_format;
+        ext_in_sig.inp_pxd_edge   = (vdc5_edge_t)drv_video_ext_in_config->inp_pxd_edge;
+        ext_in_sig.inp_vs_edge    = (vdc5_edge_t)drv_video_ext_in_config->inp_vs_edge;
+        ext_in_sig.inp_hs_edge    = (vdc5_edge_t)drv_video_ext_in_config->inp_hs_edge;
+        ext_in_sig.inp_endian_on  = (vdc5_onoff_t)drv_video_ext_in_config->inp_endian_on;
+        ext_in_sig.inp_swap_on    = (vdc5_onoff_t)drv_video_ext_in_config->inp_swap_on;
+        ext_in_sig.inp_vs_inv     = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_vs_inv;
+        ext_in_sig.inp_hs_inv     = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_hs_inv;
+        ext_in_sig.inp_h_edge_sel = (vdc5_extin_ref_hsync_t)drv_video_ext_in_config->inp_hs_edge;
+        ext_in_sig.inp_f525_625   = (vdc5_extin_input_line_t)drv_video_ext_in_config->inp_f525_625;
+        ext_in_sig.inp_h_pos      = (vdc5_extin_h_pos_t)drv_video_ext_in_config->inp_h_pos;
+
+        sync_delay.inp_vs_dly_l   = 0u;
+        sync_delay.inp_vs_dly     = 16u;
+        sync_delay.inp_hs_dly     = 16u;
+        sync_delay.inp_fld_dly    = 16u;
+
+        input.dly       = &sync_delay;   /* Sync signal delay adjustment */
+        input.ext_sig   = &ext_in_sig;   /* External input signal        */
+    }
+    /* Video input 0ch */
+    error = R_VDC5_VideoInput( VDC5_CHANNEL_0, &input );
+    if (error != VDC5_OK) {
+        drv_error = DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    if( drv_video_input_sel == DRV_INPUT_SEL_VDEC ) {
+        if ( drv_error == DRV_GRAPHICS_OK ) {
+            /* Video input 1ch */
+            error = R_VDC5_VideoInput( VDC5_CHANNEL_1, &input );
+            if (error != VDC5_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Init() */
+
+/**************************************************************************//**
+ * @brief       Start the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      drv_graphics_error_t
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_start_t            start;
+    vdc5_gr_disp_sel_t      gr_disp_sel;
+    vdc5_layer_id_t         vdc5_layer_id;
+
+    switch( layer_id ) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id   = VDC5_LAYER_ID_0_RD;
+            gr_disp_sel     = VDC5_DISPSEL_CURRENT;
+            break;
+        case DRV_GRAPHICS_LAYER_1:
+            vdc5_layer_id   = VDC5_LAYER_ID_1_RD;
+            gr_disp_sel     = VDC5_DISPSEL_BLEND;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id   = VDC5_LAYER_ID_2_RD;
+            gr_disp_sel     = VDC5_DISPSEL_BLEND;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id   = VDC5_LAYER_ID_3_RD;
+            gr_disp_sel     = VDC5_DISPSEL_BLEND;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Start process */
+        start.gr_disp_sel = &gr_disp_sel;
+        error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_layer_id_t         vdc5_layer_id;
+
+    switch( layer_id ) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id   = VDC5_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_1:
+            vdc5_layer_id   = VDC5_LAYER_ID_1_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id   = VDC5_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id   = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Stop process */
+        error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief      Start the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+
+    if (_drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Start();
+    } else {
+        vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+        vdc5_error_t            error;
+        vdc5_start_t            start;
+        vdc5_gr_disp_sel_t      gr_disp_sel;
+        vdc5_layer_id_t         vdc5_layer_id;
+
+        if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+            vdc5_layer_id   = VDC5_LAYER_ID_0_WR;
+        } else if ( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+            vdc5_layer_id   = VDC5_LAYER_ID_1_WR;
+        } else {
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+        }
+
+        if( drv_error == DRV_GRAPHICS_OK ) {
+            /* Start process */
+            gr_disp_sel         = VDC5_DISPSEL_CURRENT;    /* CURRENT fixed for weave input mode */
+            start.gr_disp_sel   = &gr_disp_sel;
+            error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
+            if (error != VDC5_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+
+    if (_drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Stop();
+    } else {
+        vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+        vdc5_error_t            error;
+        vdc5_layer_id_t         vdc5_layer_id;
+
+        switch (video_input_ch) {
+            case DRV_VIDEO_INPUT_CHANNEL_0:
+                vdc5_layer_id   = VDC5_LAYER_ID_0_WR;
+                break;
+            case DRV_VIDEO_INPUT_CHANNEL_1:
+                vdc5_layer_id   = VDC5_LAYER_ID_1_WR;
+                break;
+            default:
+                drv_error = DRV_GRAPHICS_LAYER_ERR;
+                break;
+        }
+
+        if( drv_error == DRV_GRAPHICS_OK ) {
+            /* Stop process */
+            error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
+            if (error != VDC5_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Stop() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process setting
+ *
+ *              Description:<br>
+ *              This function supports the following 4 image format.
+ *                  YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @param[in]   gr_format               : Format of the frame buffer read signal
+ * @param[in]   gr_rect                 : Graphics display area
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Setting (
+    drv_graphics_layer_t        layer_id,
+    void                      * framebuff,
+    uint32_t                    fb_stride,
+    drv_graphics_format_t       gr_format,
+    drv_wr_rd_swa_t             wr_rd_swa,
+    drv_rect_t                * gr_rect,
+    drv_clut_t                * gr_clut )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_layer_id_t         vdc5_layer_id;
+    vdc5_gr_format_t        vdc5_gr_format;
+    vdc5_read_t             read;
+
+    switch(layer_id) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_1:
+            vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        switch( gr_format ) {
+            case DRV_GRAPHICS_FORMAT_YCBCR422:
+                vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422;
+                break;
+            case DRV_GRAPHICS_FORMAT_RGB565:
+                vdc5_gr_format = VDC5_GR_FORMAT_RGB565;
+                break;
+            case DRV_GRAPHICS_FORMAT_RGB888:
+                vdc5_gr_format = VDC5_GR_FORMAT_RGB888;
+                break;
+            case DRV_GRAPHICS_FORMAT_ARGB8888:
+                vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888;
+                break;
+            case DRV_GRAPHICS_FORMAT_ARGB4444:
+                vdc5_gr_format = VDC5_GR_FORMAT_ARGB4444;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT8:
+                vdc5_gr_format = VDC5_GR_FORMAT_CLUT8;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT4:
+                vdc5_gr_format = VDC5_GR_FORMAT_CLUT4;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT1:
+                vdc5_gr_format = VDC5_GR_FORMAT_CLUT1;
+                break;
+            default:
+                drv_error = DRV_GRAPHICS_FORMAT_ERR;
+                break;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Read data parameter */
+        read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+        read.gr_flm_sel     = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+        read.gr_imr_flm_inv = VDC5_OFF;                 /* Frame buffer number for distortion correction */
+        read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+        read.gr_base        = framebuff;                /* Frame buffer base address */
+        read.gr_ln_off      = fb_stride;                /* Frame buffer line offset address */
+
+        read.width_read_fb  = NULL;                     /* Width of the image read from frame buffer */
+
+        read.adj_sel        = VDC5_OFF;                 /* Measures to decrease the influence
+                                                           by folding pixels/lines (on/off) */
+        read.gr_format      = vdc5_gr_format;           /* Format of the frame buffer read signal */
+        read.gr_ycc_swap    = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
+                                                           in the YCbCr422 format */
+        read.gr_rdswa       = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
+        /* Display area */
+        read.gr_grc.vs      = gr_rect->vs;
+        read.gr_grc.vw      = gr_rect->vw;
+        read.gr_grc.hs      = gr_rect->hs;
+        read.gr_grc.hw      = gr_rect->hw;
+
+        /* Read data control */
+        error = R_VDC5_ReadDataControl( ch, vdc5_layer_id, &read );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if ((vdc5_gr_format == VDC5_GR_FORMAT_CLUT8)
+         || (vdc5_gr_format == VDC5_GR_FORMAT_CLUT4)
+         || (vdc5_gr_format == VDC5_GR_FORMAT_CLUT1)) {
+            vdc5_clut_t vdc5_clut;
+
+            if (gr_clut != NULL) {
+                vdc5_clut.color_num = gr_clut->color_num;
+                vdc5_clut.clut = gr_clut->clut;
+            } else if (vdc5_gr_format == VDC5_GR_FORMAT_CLUT8) {
+                vdc5_clut.color_num = CLUT8_TABLE_NUM;
+                vdc5_clut.clut = color_table256;
+            } else if (vdc5_gr_format == VDC5_GR_FORMAT_CLUT4) {
+                vdc5_clut.color_num = CLUT4_TABLE_NUM;
+                vdc5_clut.clut = color_table16;
+            } else {
+                vdc5_clut.color_num = CLUT1_TABLE_NUM;
+                vdc5_clut.clut = color_table2;
+            }
+            error = R_VDC5_CLUT(ch, vdc5_layer_id, &vdc5_clut);
+            if (error != VDC5_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+
+    return drv_error;
+}   /* End of function DRV_Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read buffer change process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Change (
+    drv_graphics_layer_t    layer_id,
+    void                 *  framebuff)
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_layer_id_t         vdc5_layer_id;
+    vdc5_read_chg_t         read_chg;
+
+    switch(layer_id) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_1:
+            vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Read data parameter */
+        read_chg.width_read_fb  = NULL;         /* Width of the image read from frame buffer */
+        read_chg.gr_grc         = NULL;         /* Display area */
+        read_chg.gr_disp_sel    = NULL;         /* Graphics display mode */
+        read_chg.gr_base        = framebuff;     /* Frame buffer base address */
+
+        /* Change read process */
+        error = R_VDC5_ChangeReadProcess( ch, vdc5_layer_id, &read_chg );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Read_Change() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting
+ *
+ *              Description:<br>
+ *              This function set the video write process. Input form is weave
+ *              (progressive) mode fixed.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   video_input_ch          : Video input channel
+ * @param[in]   col_sys                 : Analog video signal color system
+ * @param[in]   adc_vinsel              : Video input pin
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   video_adc_vinsel        : Input pin control
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting (
+    drv_video_input_channel_t       video_input_ch,
+    drv_graphics_video_col_sys_t    col_sys,
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_adc_vinsel_t          video_adc_vinsel )
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t              ch          = VDC5_CHANNEL_0;
+    vdc5_error_t                error;
+    vdc5_layer_id_t             vdc5_layer_id;
+    vdc5_write_t                write;
+    vdc5_scalingdown_rot_t    * scldw_rot;
+    vdc5_res_md_t               res_md;
+    drv_rect_t                  video_in_rect;
+    uint8_t                   * framebuffer_t;
+    uint8_t                   * framebuffer_b;
+
+    if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+        GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t)video_adc_vinsel, VDEC_CHANNEL_0, (graphics_col_sys_t)col_sys );
+    } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+        GRAPHICS_VideoDecoderInit( (vdec_adc_vinsel_t)video_adc_vinsel, VDEC_CHANNEL_1, (graphics_col_sys_t)col_sys );
+    } else {
+        drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+            vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+        } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+            vdc5_layer_id = VDC5_LAYER_ID_1_WR;
+        } else {
+            drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
+            res_md = VDC5_RES_MD_YCBCR422;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
+            res_md = VDC5_RES_MD_RGB888;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
+            res_md = VDC5_RES_MD_RGB565;
+        } else {
+            drv_error = DRV_GRAPHICS_FORMAT_ERR;
+        }
+    }
+
+    if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) {
+        video_in_rect.hs = IMGCAP_SIZE_NTSC_HS * 2;
+        video_in_rect.hw = IMGCAP_SIZE_NTSC_HW * 2;
+        video_in_rect.vs = IMGCAP_SIZE_NTSC_VS;
+        video_in_rect.vw = IMGCAP_SIZE_NTSC_VW;
+    } else {
+        video_in_rect.hs = IMGCAP_SIZE_PAL_HS * 2;
+        video_in_rect.hw = IMGCAP_SIZE_PAL_HW * 2;
+        video_in_rect.vs = IMGCAP_SIZE_PAL_VS;
+        video_in_rect.vw = IMGCAP_SIZE_PAL_VW;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) {
+            if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
+                drv_error = DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR;
+            }
+        } else {
+            if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
+                drv_error = DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR;
+            }
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if( video_write_buff_hw > 800 ) {
+            drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Scaling-down and rotation parameter */
+        scldw_rot = &write.scalingdown_rot;
+        /* Image area to be captured */
+        scldw_rot->res.vs   = (uint16_t)((uint32_t)video_in_rect.vs - 1u);
+        scldw_rot->res.vw   = video_in_rect.vw;
+        scldw_rot->res.hs   = video_in_rect.hs;
+        scldw_rot->res.hw   = video_in_rect.hw;
+
+        /* Write data parameter */
+        framebuffer_t      = framebuff;
+        framebuffer_b      = &framebuffer_t[fb_stride];
+        scldw_rot->res_pfil_sel = VDC5_ON;                   /* Prefilter mode select for brightness signals (on/off) */
+        scldw_rot->res_out_vw   = video_write_buff_vw / 2u;  /* Number of valid lines in vertical direction
+                                                                output by scaling-down control block */
+        scldw_rot->res_out_hw   = video_write_buff_hw;       /* Number of valid horizontal pixels
+                                                                output by scaling-down control block */
+        scldw_rot->adj_sel      = VDC5_ON;                   /* Measures to decrease the influence
+                                                                by lack of last-input line (on/off) */
+        scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL;         /* Frame buffer writing mode */
+        write.res_wrswa     = (vdc5_wr_rd_swa_t)wr_rd_swa;   /* Frame buffer swap setting */
+        write.res_md        = res_md;                        /* Frame buffer video-signal writing format */
+        write.res_bst_md    = VDC5_BST_MD_32BYTE;            /* Transfer burst length for frame buffer */
+        write.res_inter     = VDC5_RES_INTER_PROGRESSIVE;    /* Field operating mode select */
+        write.res_fs_rate   = VDC5_RES_FS_RATE_PER1;         /* Writing rate */
+        write.res_fld_sel   = VDC5_RES_FLD_SEL_TOP;          /* Write field select */
+        write.res_dth_on    = VDC5_ON;                       /* Dither correction on/off */
+        write.base          = framebuff;                     /* Frame buffer base address */
+        write.ln_off        = fb_stride * 2u;                /* Frame buffer line offset address [byte] */
+        write.flm_num       = (uint32_t)(1u - 1u);            /* Number of frames of buffer (res_flm_num + 1) */
+        /* Frame buffer frame offset address */
+        write.flm_off       = fb_stride * 2u * (uint32_t)scldw_rot->res_out_vw;
+        write.btm_base      = framebuffer_b;                   /* Frame buffer base address for bottom */
+
+        /* Write data control */
+        error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting for digital input
+ *
+ *              Description:<br>
+ *              This function set the video write process for digital input.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   cap_area                : Capture area
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting_Digital (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_rect_t                    * cap_area )
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t              ch          = VDC5_CHANNEL_0;
+    vdc5_error_t                error;
+    vdc5_layer_id_t             vdc5_layer_id;
+    vdc5_write_t                write;
+    vdc5_scalingdown_rot_t    * scldw_rot;
+    vdc5_res_md_t               res_md;
+
+    vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
+            res_md = VDC5_RES_MD_YCBCR422;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
+            res_md = VDC5_RES_MD_RGB888;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
+            res_md = VDC5_RES_MD_RGB565;
+        } else {
+            drv_error = DRV_GRAPHICS_FORMAT_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Scaling-down and rotation parameter */
+        scldw_rot = &write.scalingdown_rot;
+        /* Image area to be captured */
+        scldw_rot->res.vs   = (uint16_t)((uint32_t)cap_area->vs - 1u);
+        scldw_rot->res.vw   = cap_area->vw;
+        scldw_rot->res.hs   = cap_area->hs;
+        scldw_rot->res.hw   = cap_area->hw;
+
+        /* Write data parameter */
+        scldw_rot->res_pfil_sel = VDC5_ON;                   /* Prefilter mode select for brightness signals (on/off) */
+        scldw_rot->res_out_vw   = video_write_buff_vw ;      /* Number of valid lines in vertical direction
+                                                                output by scaling-down control block */
+        scldw_rot->res_out_hw   = video_write_buff_hw;       /* Number of valid horizontal pixels
+                                                                output by scaling-down control block */
+        scldw_rot->adj_sel      = VDC5_ON;                   /* Measures to decrease the influence
+                                                                by lack of last-input line (on/off) */
+        scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL;         /* Frame buffer writing mode */
+        write.res_wrswa     = (vdc5_wr_rd_swa_t)wr_rd_swa;   /* Frame buffer swap setting */
+        write.res_md        = res_md;                        /* Frame buffer video-signal writing format */
+        write.res_bst_md    = VDC5_BST_MD_32BYTE;            /* Transfer burst length for frame buffer */
+        write.res_inter     = VDC5_RES_INTER_PROGRESSIVE;    /* Field operating mode select */
+        write.res_fs_rate   = VDC5_RES_FS_RATE_PER1;         /* Writing rate */
+        write.res_fld_sel   = VDC5_RES_FLD_SEL_TOP;          /* Write field select */
+        write.res_dth_on    = VDC5_ON;                       /* Dither correction on/off */
+        write.base          = framebuff;                     /* Frame buffer base address */
+        write.ln_off        = fb_stride;
+        /* Frame buffer line offset address [byte] */
+        write.flm_num       = (uint32_t)(1u - 1u);           /* Number of frames of buffer (res_flm_num + 1) */
+        /* Frame buffer frame offset address */
+        write.flm_off       = fb_stride * (uint32_t)scldw_rot->res_out_vw;
+        write.btm_base      = NULL;                          /* Frame buffer base address for bottom */
+
+        /* Write data control */
+        error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Write_Setting_Digital() */
+
+drv_graphics_error_t DRV_Video_Write_Setting_Ceu (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_ext_in_config_t     * drv_video_ext_in_config)
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    ceu_cap_rect_t              ceu_cap;
+    ceu_config_t                ceu_config;
+
+    if (video_format != DRV_VIDEO_FORMAT_YCBCR422) {
+        return DRV_GRAPHICS_FORMAT_ERR;
+    }
+
+    /* CEU mode */
+    ceu_config.jpg = CEU_DATA_SYNC_MODE;
+
+    /* Capture timing */
+    if (drv_video_ext_in_config->cap_hs_pos <= 100) {
+        ceu_cap.hofst = drv_video_ext_in_config->cap_hs_pos * 4;
+    } else {
+        ceu_cap.hofst = 0;
+    }
+    if (drv_video_ext_in_config->cap_vs_pos >= 10) {
+        ceu_cap.vofst = drv_video_ext_in_config->cap_vs_pos * 4;
+    } else {
+        ceu_cap.vofst = 0;
+    }
+    ceu_cap.hwdth = video_write_buff_hw * 2;
+    ceu_cap.vwdth = video_write_buff_vw;
+    ceu_config.cap = &ceu_cap;
+
+    /* Capture Filter Size (Set this param if Image capture mode.) */
+    ceu_config.clp = NULL;
+
+    /* Data bus */
+    ceu_config.dtif = CEU_8BIT_DATA_PINS; /* Data pin 8bit  */
+
+    /* Write Data Swap */
+    switch (wr_rd_swa) {
+        default:
+        case DRV_WR_RD_WRSWA_NON:               /* Not swapped: 1-2-3-4-5-6-7-8 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_8BIT:              /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_16BIT:             /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_16_8BIT:           /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_32BIT:             /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_32_8BIT:           /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_32_16BIT:          /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_32_16_8BIT:        /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_ON;
+            break;
+    }
+
+    /* input order */
+    switch (drv_video_ext_in_config->inp_h_pos) {
+        default:
+        case DRV_EXTIN_H_POS_CBYCRY:        /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+            ceu_config.dtary = CEU_CB0_Y0_CR0_Y1;
+            if (ceu_config.cows == CEU_ON) {
+                ceu_config.cows = CEU_OFF;
+            } else {
+                ceu_config.cows = CEU_ON;
+            }
+            break;
+        case DRV_EXTIN_H_POS_YCRYCB:        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+            ceu_config.dtary = CEU_Y0_CR0_Y1_CB0;
+            if (ceu_config.cobs == CEU_ON) {
+                ceu_config.cobs = CEU_OFF;
+            } else {
+                ceu_config.cobs = CEU_ON;
+            }
+            if (ceu_config.cows == CEU_ON) {
+                ceu_config.cows = CEU_OFF;
+            } else {
+                ceu_config.cows = CEU_ON;
+            }
+            break;
+        case DRV_EXTIN_H_POS_CRYCBY:        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+            ceu_config.dtary = CEU_CR0_Y0_CB0_Y1;
+            break;
+        case DRV_EXTIN_H_POS_YCBYCR:        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+            ceu_config.dtary = CEU_Y0_CB0_Y1_CR0;
+            if (ceu_config.cobs == CEU_ON) {
+                ceu_config.cobs = CEU_OFF;
+            } else {
+                ceu_config.cobs = CEU_ON;
+            }
+            break;
+    }
+
+    /* Signal polarity */
+    /* Hsync */
+    if (drv_video_ext_in_config->inp_hs_inv == DRV_SIG_POL_NOT_INVERTED) {
+        ceu_config.hdpol = CEU_HIGH_ACTIVE;
+    } else {
+        ceu_config.hdpol = CEU_LOW_ACTIVE;
+    }
+    if (drv_video_ext_in_config->cap_hs_pos >= 100) {
+        /* inverted */
+        if (ceu_config.hdpol == CEU_HIGH_ACTIVE) {
+            ceu_config.hdpol = CEU_LOW_ACTIVE;
+        } else {
+            ceu_config.hdpol = CEU_HIGH_ACTIVE;
+        }
+    }
+
+    /* Vsync */
+    if (drv_video_ext_in_config->inp_vs_inv == DRV_SIG_POL_NOT_INVERTED) {
+        ceu_config.vdpol = CEU_HIGH_ACTIVE;
+    } else {
+        ceu_config.vdpol = CEU_LOW_ACTIVE;
+    }
+
+    R_CEU_Open(&ceu_config);
+    R_CEU_Execute_Setting(framebuff, (void *)NULL, fb_stride, CEU_ON);
+
+    return drv_error;
+}
+
+/**************************************************************************//**
+ * @brief       Video surface write buffer change process
+ * @param[in]   video_input_ch          : Video input channle
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Change (
+    drv_video_input_channel_t     video_input_ch,
+    void                        * framebuff,
+    uint32_t                      fb_stride )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint8_t               * framebuffer_t;
+    uint8_t               * framebuffer_b;
+
+    framebuffer_t = (uint8_t *)((uint32_t)framebuff & ~0x1F);
+    framebuffer_b = &framebuffer_t[fb_stride];
+
+    if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+        VDC50.SC0_SCL1_WR2 = (uint32_t)framebuffer_t;
+        VDC50.SC0_SCL1_WR8 = (uint32_t)framebuffer_b;
+        VDC50.SC0_SCL1_UPDATE = 0x10;
+    } else if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1 ) {
+        VDC50.SC1_SCL1_WR2 = (uint32_t)framebuffer_t;
+        VDC50.SC1_SCL1_WR8 = (uint32_t)framebuffer_b;
+        VDC50.SC1_SCL1_UPDATE = 0x10;
+    } else {
+        drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+    }
+    return drv_error;
+} /* End of function DRV_Video_Write_Change() */
+
+/* End of file */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/inc/lcd_analog_rgb.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,134 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel  definition header
+******************************************************************************/
+
+#ifndef LCD_ANALOG_RGB_H
+#define LCD_ANALOG_RGB_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* SVGA signal 800x600
+    Pixel clock frequency: 40.0 MHz
+    Refresh rate: 60.3 Hz
+    Polarity of horizontal sync pulse: Positive
+    Polarity of vertical sync pulse: Positive
+*/
+#define     LCD_SVGA_H_VISIBLE_AREA     (800u)                      /* Horizontal visible area [pixel] */
+#define     LCD_SVGA_H_FRONT_PORCH      (40u)                       /* Horizontal front porch [pixel] */
+#define     LCD_SVGA_H_SYNC_WIDTH       (128u)                      /* Horizontal sync pulse width [pixel] */
+#define     LCD_SVGA_H_BACK_PORCH       (88u)                       /* Horizontal back porch [pixel] */
+/* Horizontal total (one line) [pixel] */
+#define     LCD_SVGA_H_TOTAL            (LCD_SVGA_H_VISIBLE_AREA +\
+                                        LCD_SVGA_H_FRONT_PORCH +\
+                                        LCD_SVGA_H_SYNC_WIDTH +\
+                                        LCD_SVGA_H_BACK_PORCH)
+#define     LCD_SVGA_H_POLARITY         (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of horizontal sync pulse */
+
+#define     LCD_SVGA_V_VISIBLE_AREA     (600u)                      /* Vertical visible area [line] */
+#define     LCD_SVGA_V_FRONT_PORCH      (1u)                        /* Vertical front porch [line] */
+#define     LCD_SVGA_V_SYNC_WIDTH       (4u)                        /* Vertical sync pulse width [line] */
+#define     LCD_SVGA_V_BACK_PORCH       (23u)                       /* Vertical back porch [line] */
+/* Vertical total (one frame) [line] */
+#define     LCD_SVGA_V_TOTAL            (LCD_SVGA_V_VISIBLE_AREA +\
+                                        LCD_SVGA_V_FRONT_PORCH +\
+                                        LCD_SVGA_V_SYNC_WIDTH +\
+                                        LCD_SVGA_V_BACK_PORCH)
+#define     LCD_SVGA_V_POLARITY         (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of vertical sync pulse */
+
+
+/* XGA signal 1024x768
+    Pixel clock frequency: 65.0 MHz
+    Refresh rate: 60.0 Hz
+    Polarity of horizontal sync pulse: Negative
+    Polarity of vertical sync pulse: Negative
+*/
+#define     LCD_XGA_H_VISIBLE_AREA      (1024u)                     /* Horizontal visible area [pixel] */
+#define     LCD_XGA_H_FRONT_PORCH       (24u)                       /* Horizontal front porch [pixel] */
+#define     LCD_XGA_H_SYNC_WIDTH        (136u)                      /* Horizontal sync pulse width [pixel] */
+#define     LCD_XGA_H_BACK_PORCH        (160u)                      /* Horizontal back porch [pixel] */
+/* Horizontal total (one line) [pixel] */
+#define     LCD_XGA_H_TOTAL             (LCD_XGA_H_VISIBLE_AREA +\
+                                        LCD_XGA_H_FRONT_PORCH +\
+                                        LCD_XGA_H_SYNC_WIDTH +\
+                                        LCD_XGA_H_BACK_PORCH)
+#define     LCD_XGA_H_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of horizontal sync pulse */
+
+#define     LCD_XGA_V_VISIBLE_AREA      (768u)                      /* Vertical visible area [line] */
+#define     LCD_XGA_V_FRONT_PORCH       (3u)                        /* Vertical front porch [line] */
+#define     LCD_XGA_V_SYNC_WIDTH        (6u)                        /* Vertical sync pulse width [line] */
+#define     LCD_XGA_V_BACK_PORCH        (29u)                       /* Vertical back porch [line] */
+/* Vertical total (one frame) [line] */
+#define     LCD_XGA_V_TOTAL             (LCD_XGA_V_VISIBLE_AREA +\
+                                        LCD_XGA_V_FRONT_PORCH +\
+                                        LCD_XGA_V_SYNC_WIDTH +\
+                                        LCD_XGA_V_BACK_PORCH)
+#define     LCD_XGA_V_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of vertical sync pulse */
+
+
+/* VGA signal 640x480
+    Pixel clock frequency: 25.175 MHz
+    Refresh rate: 59.94 Hz
+    Polarity of horizontal sync pulse: Negative
+    Polarity of vertical sync pulse: Negative
+*/
+#define     LCD_VGA_H_VISIBLE_AREA      (640u)                      /* Horizontal visible area [pixel] */
+#define     LCD_VGA_H_FRONT_PORCH       (16u)                       /* Horizontal front porch [pixel] */
+#define     LCD_VGA_H_SYNC_WIDTH        (96u)                       /* Horizontal sync pulse width [pixel] */
+#define     LCD_VGA_H_BACK_PORCH        (48u)                       /* Horizontal back porch [pixel] */
+/* Horizontal total (one line) [pixel] */
+#define     LCD_VGA_H_TOTAL             (LCD_VGA_H_VISIBLE_AREA +\
+                                        LCD_VGA_H_FRONT_PORCH +\
+                                        LCD_VGA_H_SYNC_WIDTH +\
+                                        LCD_VGA_H_BACK_PORCH)
+#define     LCD_VGA_H_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of horizontal sync pulse */
+
+#define     LCD_VGA_V_VISIBLE_AREA      (480u)                      /* Vertical visible area [line] */
+#define     LCD_VGA_V_FRONT_PORCH       (10u)                       /* Vertical front porch [line] */
+#define     LCD_VGA_V_SYNC_WIDTH        (2u)                        /* Vertical sync pulse width [line] */
+#define     LCD_VGA_V_BACK_PORCH        (33u)                       /* Vertical back porch [line] */
+/* Vertical total (one frame) [line] */
+#define     LCD_VGA_V_TOTAL             (LCD_VGA_V_VISIBLE_AREA +\
+                                        LCD_VGA_V_FRONT_PORCH +\
+                                        LCD_VGA_V_SYNC_WIDTH +\
+                                        LCD_VGA_V_BACK_PORCH)
+#define     LCD_VGA_V_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of vertical sync pulse */
+
+
+#endif  /* LCD_ANALOG_RGB_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/inc/lcd_analog_rgb_ch0.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,95 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb_ch0.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 definition header
+******************************************************************************/
+
+#ifndef LCD_ANALOG_RGB_CH0_H
+#define LCD_ANALOG_RGB_CH0_H
+
+#ifndef LCD_PANEL_H
+#error  Do not include this file directly!
+#else
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "lcd_analog_rgb.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Option board (part number: RTK7721000B00000BR)
+    ADV7123 (Video DAC), U8
+    Analog RGB D-sub15 (RGB888), J15 */
+#define     LCD_CH0_S_HSYNC         (0u)                        /* Hsync start position */
+#define     LCD_CH0_W_HSYNC         (LCD_SVGA_H_SYNC_WIDTH)     /* Hsync width */
+#define     LCD_CH0_POL_HSYNC       (LCD_SVGA_H_POLARITY)       /* Polarity of Hsync pulse */
+/* LCD display area size, horizontal start position */
+#define     LCD_CH0_DISP_HS         (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH)
+#define     LCD_CH0_DISP_HW         (LCD_SVGA_H_VISIBLE_AREA)   /* LCD display area size, horizontal width */
+
+/* Vsync start position */
+#define     LCD_CH0_S_VSYNC         (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH)
+#define     LCD_CH0_W_VSYNC         (LCD_SVGA_V_SYNC_WIDTH)     /* Vsync width */
+#define     LCD_CH0_POL_VSYNC       (LCD_SVGA_V_POLARITY)       /* Polarity of Vsync pulse */
+#define     LCD_CH0_DISP_VS         (LCD_SVGA_V_BACK_PORCH)     /* LCD display area size, vertical start position */
+#define     LCD_CH0_DISP_VW         (LCD_SVGA_V_VISIBLE_AREA)   /* LCD display area size, height (vertical width) */
+
+#define     LCD_CH0_SIG_FV          (LCD_SVGA_V_TOTAL - 1u)     /* Free-running Vsync period */
+#define     LCD_CH0_SIG_FH          (LCD_SVGA_H_TOTAL - 1u)     /* Hsync period */
+/* Pixel data is latched in the rising edge of pixel clock on ADV7123.
+   Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */
+#define     LCD_CH0_OUT_EDGE        VDC5_EDGE_FALLING           /* Output phase control of LCD_DATA[23:0] signal */
+#define     LCD_CH0_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB888   /* LCD output format select */
+
+#define     LCD_CH0_PANEL_CLK       VDC5_PANEL_ICKSEL_LVDS      /* Panel clock select */
+#define     LCD_CH0_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_1       /* Panel clock frequency division ratio */
+
+#define     LCD_CH0_TCON_HALF       (LCD_CH0_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
+#define     LCD_CH0_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0(void);
+void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * const outctrl);
+
+
+#endif  /* LCD_PANEL_H not defined */
+#endif  /* LCD_ANALOG_RGB_CH0_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/inc/lcd_analog_rgb_ch1.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,95 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb_ch1.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 1 definition header
+******************************************************************************/
+
+#ifndef LCD_ANALOG_RGB_CH1_H
+#define LCD_ANALOG_RGB_CH1_H
+
+#ifndef LCD_PANEL_H
+#error  Do not include this file directly!
+#else
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "lcd_analog_rgb.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Option board (part number: RTK7721000B00000BR)
+    ADV7123 (Video DAC), U10
+    Analog RGB D-sub15 (RGB888), J16 */
+#define     LCD_CH1_S_HSYNC         (0u)                        /* Hsync start position */
+#define     LCD_CH1_W_HSYNC         (LCD_SVGA_H_SYNC_WIDTH)     /* Hsync width */
+#define     LCD_CH1_POL_HSYNC       (LCD_SVGA_H_POLARITY)       /* Polarity of Hsync pulse */
+/* LCD display area size, horizontal start position */
+#define     LCD_CH1_DISP_HS         (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH)
+#define     LCD_CH1_DISP_HW         (LCD_SVGA_H_VISIBLE_AREA)   /* LCD display area size, horizontal width */
+
+/* Vsync start position */
+#define     LCD_CH1_S_VSYNC         (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH)
+#define     LCD_CH1_W_VSYNC         (LCD_SVGA_V_SYNC_WIDTH)     /* Vsync width */
+#define     LCD_CH1_POL_VSYNC       (LCD_SVGA_V_POLARITY)       /* Polarity of Vsync pulse */
+#define     LCD_CH1_DISP_VS         (LCD_SVGA_V_BACK_PORCH)     /* LCD display area size, vertical start position */
+#define     LCD_CH1_DISP_VW         (LCD_SVGA_V_VISIBLE_AREA)   /* LCD display area size, height (vertical width) */
+
+#define     LCD_CH1_SIG_FV          (LCD_SVGA_V_TOTAL - 1u)     /* Free-running Vsync period */
+#define     LCD_CH1_SIG_FH          (LCD_SVGA_H_TOTAL - 1u)     /* Hsync period */
+/* Pixel data is latched in the rising edge of pixel clock on ADV7123.
+   Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */
+#define     LCD_CH1_OUT_EDGE        VDC5_EDGE_FALLING           /* Output phase control of LCD_DATA[23:0] signal */
+#define     LCD_CH1_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB888   /* LCD output format select */
+
+#define     LCD_CH1_PANEL_CLK       VDC5_PANEL_ICKSEL_LVDS      /* Panel clock select */
+#define     LCD_CH1_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_1       /* Panel clock frequency division ratio */
+
+#define     LCD_CH1_TCON_HALF       (LCD_CH1_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
+#define     LCD_CH1_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch1(void);
+void GRAPHICS_SetLcdTconSettings_Ch1(const vdc5_lcd_tcon_timing_t * * const outctrl);
+
+
+#endif  /* LCD_PANEL_H not defined */
+#endif  /* LCD_ANALOG_RGB_CH1_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/inc/lcd_gr_peach_ch0.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,81 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_gr_peach_ch0.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 definition header
+******************************************************************************/
+
+#ifndef LCD_GR_PEACH_CH0_H
+#define LCD_GR_PEACH_CH0_H
+
+#ifndef LCD_PANEL_H
+#error  Do not include this file directly!
+#else
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Not support */
+#define     LCD_CH0_DISP_HS         (128u)                      /* LCD display area size, horizontal start position */
+#define     LCD_CH0_DISP_HW         (800u)                      /* LCD display area size, horizontal width */
+#define     LCD_CH0_DISP_VS         (10u)                       /* LCD display area size, vertical start position */
+#define     LCD_CH0_DISP_VW         (480u)                      /* LCD display area size, height (vertical width) */
+#define     LCD_CH0_SIG_FV          (525u - 1u)                 /* Free-running Vsync period */
+#define     LCD_CH0_SIG_FH          (1056u - 1u)                /* Hsync period */
+/* Pixel data is latched in the falling edge of pixel clock.
+   Therefore, pixel data should be output from VDC5 at the rising edge of the clock. */
+#define     LCD_CH0_OUT_EDGE        VDC5_EDGE_RISING            /* Output phase control of LCD_DATA[23:0] signal */
+#define     LCD_CH0_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB666   /* LCD output format select */
+
+#define     LCD_CH0_PANEL_CLK       VDC5_PANEL_ICKSEL_PERI      /* Panel clock select */
+#define     LCD_CH0_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_2       /* Panel clock frequency division ratio */
+
+#define     LCD_CH0_TCON_HALF       (LCD_CH0_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
+#define     LCD_CH0_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0(void);
+void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * const outctrl);
+
+
+#endif  /* LCD_PANEL_H not defined */
+#endif  /* LCD_GR_PEACH_CH0_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/inc/lcd_panel.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,89 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_panel.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel definition header
+******************************************************************************/
+
+#ifndef LCD_PANEL_H
+#define LCD_PANEL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* LCD panel select (CH0)
+    1: Analog RGB D-sub15, SVGA 800x600  debug code for GENMAI Board
+    2: Gr-peach, WVGA 800x480 Not support
+*/
+#define     LCD_CH0_PANEL_ANALOG_RGB            (1) /* debug */
+#define     LCD_CH0_PANEL_GR_PEACH              (2) /* Not support */
+#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_GR_PEACH
+
+/* LCD panel select (CH1)
+    1: Analog RGB D-sub15, SVGA 800x600  debug code for GENMAI Board
+*/
+#define     LCD_CH1_PANEL_ANALOG_RGB            (1) /* debug */
+#define     LCD_VDC5_CH1_PANEL                  LCD_CH1_PANEL_ANALOG_RGB
+
+
+#if     (LCD_VDC5_CH0_PANEL==1)
+#include    "lcd_analog_rgb_ch0.h"
+#elif     (LCD_VDC5_CH0_PANEL==2)
+#include    "lcd_gr_peach_ch0.h"   /* Not support */
+#else
+#error  Undefined LCD panel!
+#endif
+
+#if     (LCD_VDC5_CH1_PANEL==1)
+#include    "lcd_analog_rgb_ch1.h"
+#else
+#error  Undefined LCD panel!
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel(const vdc5_channel_t channel);
+void GRAPHICS_SetLcdTconSettings(const vdc5_channel_t channel, const vdc5_lcd_tcon_timing_t * * const outctrl);
+vdc5_lvds_t * GRAPHICS_GetLvdsParam(const vdc5_channel_t channel);
+
+
+#endif  /* LCD_PANEL_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/inc/lvds_pll_calc.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lvds_pll_calc.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Debug function header
+******************************************************************************/
+
+#ifndef LVDS_PLL_CALC_H
+#define LVDS_PLL_CALC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+typedef struct {
+    double comparison_freq;
+    double output_freq;
+    double nidiv;
+    double nrd;
+    double nfd;
+    double nod;
+    double nodiv;
+} pll_parameter_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+#define LVDS_IF_NOT_USE (0u)
+#define LVDS_IF_USE     (1u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+extern int32_t lvds_pll_calc(
+    const double      InClock,
+    const double      OuClock,
+    const uint32_t    Lvds,
+    pll_parameter_t * result  );
+
+#endif  /* LVDS_PLL_CALC_H */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/inc/video_decoder.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         video_decoder.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Video decoder function header
+******************************************************************************/
+
+#ifndef VIDEO_DECODER_H
+#define VIDEO_DECODER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+#include    <string.h>
+
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Video color system */
+typedef enum {
+    GRPH_COL_SYS_UNKNOWN        = -1,       /*!< Unknown */
+    GRPH_COL_SYS_NTSC_358       = 0,        /*!< NTSC-3.58 */
+    GRPH_COL_SYS_NTSC_443       = 1,        /*!< NTSC-4.43 */
+    GRPH_COL_SYS_PAL_443        = 2,        /*!< PAL-4.43 */
+    GRPH_COL_SYS_PAL_M          = 3,        /*!< PAL-M */
+    GRPH_COL_SYS_PAL_N          = 4,        /*!< PAL-N */
+    GRPH_COL_SYS_SECAM          = 5,        /*!< SECAM */
+    GRPH_COL_SYS_NTSC_443_60    = 6,        /*!< NTSC-4.43 (60Hz) */
+    GRPH_COL_SYS_PAL_60         = 7,        /*!< PAL-60 */
+    GRPH_COL_SYS_NUM            = 8
+} graphics_col_sys_t;
+
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdec_error_t GRAPHICS_VideoDecoderInit (const vdec_adc_vinsel_t adc_vinsel, const vdec_channel_t channel, graphics_col_sys_t col_sys);
+
+
+#endif  /* VIDEO_DECODER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/lvds/lvds_pll_data.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,321 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         lvds_pll_data.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        lvds pll for vdc5 channel 0 data
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <stdlib.h>
+
+
+/******************************************************************************
+Variables
+******************************************************************************/
+const double NIDIV_data[] = {
+    1.0,    2.0,    4.0,
+    0.0
+};
+
+const double NRD_data[] = {
+    1.0,    2.0,    3.0,    4.0,    5.0,    6.0,    7.0,    8.0,
+    9.0,    10.0,   11.0,   12.0,   13.0,   14.0,   15.0,   16.0,
+    17.0,   18.0,   19.0,   20.0,   21.0,   22.0,   23.0,   24.0,
+    25.0,   26.0,   27.0,   28.0,   29.0,   30.0,   31.0,   32.0,
+    0.0
+};
+
+const double NFD_data[] = {
+    24.0,   25.0,   26.0,   27.0,
+    32.0,   33.0,   34.0,   35.0,   36.0,
+    40.0,   41.0,   42.0,   43.0,   44.0,   45.0,
+    48.0,   49.0,   50.0,   51.0,   52.0,   53.0,   54.0,
+    56.0,   57.0,   58.0,   59.0,   60.0,   61.0,   62.0,   63.0,
+    64.0,   65.0,   66.0,   67.0,   68.0,   69.0,   70.0,   71.0,
+    72.0,   73.0,   74.0,   75.0,   76.0,   77.0,   78.0,   79.0,
+    80.0,   81.0,   82.0,   83.0,   84.0,   85.0,   86.0,   87.0,
+    88.0,   89.0,   90.0,   91.0,   92.0,   93.0,   94.0,   95.0,
+    96.0,   97.0,   98.0,   99.0,   100.0,  101.0,  102.0,  103.0,
+    104.0,  105.0,  106.0,  107.0,  108.0,  109.0,  110.0,  111.0,
+    112.0,  113.0,  114.0,  115.0,  116.0,  117.0,  118.0,  119.0,
+    120.0,  121.0,  122.0,  123.0,  124.0,  125.0,  126.0,  127.0,
+    128.0,  129.0,  130.0,  131.0,  132.0,  133.0,  134.0,  135.0,
+    136.0,  137.0,  138.0,  139.0,  140.0,  141.0,  142.0,  143.0,
+    144.0,  145.0,  146.0,  147.0,  148.0,  149.0,  150.0,  151.0,
+    152.0,  153.0,  154.0,  155.0,  156.0,  157.0,  158.0,  159.0,
+    160.0,  161.0,  162.0,  163.0,  164.0,  165.0,  166.0,  167.0,
+    168.0,  169.0,  170.0,  171.0,  172.0,  173.0,  174.0,  175.0,
+    176.0,  177.0,  178.0,  179.0,  180.0,  181.0,  182.0,  183.0,
+    184.0,  185.0,  186.0,  187.0,  188.0,  189.0,  190.0,  191.0,
+    192.0,  193.0,  194.0,  195.0,  196.0,  197.0,  198.0,  199.0,
+    200.0,  201.0,  202.0,  203.0,  204.0,  205.0,  206.0,  207.0,
+    208.0,  209.0,  210.0,  211.0,  212.0,  213.0,  214.0,  215.0,
+    216.0,  217.0,  218.0,  219.0,  220.0,  221.0,  222.0,  223.0,
+    224.0,  225.0,  226.0,  227.0,  228.0,  229.0,  230.0,  231.0,
+    232.0,  233.0,  234.0,  235.0,  236.0,  237.0,  238.0,  239.0,
+    240.0,  241.0,  242.0,  243.0,  244.0,  245.0,  246.0,  247.0,
+    248.0,  249.0,  250.0,  251.0,  252.0,  253.0,  254.0,  255.0,
+    256.0,  257.0,  258.0,  259.0,  260.0,  261.0,  262.0,  263.0,
+    264.0,  265.0,  266.0,  267.0,  268.0,  269.0,  270.0,  271.0,
+    272.0,  273.0,  274.0,  275.0,  276.0,  277.0,  278.0,  279.0,
+    280.0,  281.0,  282.0,  283.0,  284.0,  285.0,  286.0,  287.0,
+    288.0,  289.0,  290.0,  291.0,  292.0,  293.0,  294.0,  295.0,
+    296.0,  297.0,  298.0,  299.0,  300.0,  301.0,  302.0,  303.0,
+    304.0,  305.0,  306.0,  307.0,  308.0,  309.0,  310.0,  311.0,
+    312.0,  313.0,  314.0,  315.0,  316.0,  317.0,  318.0,  319.0,
+    320.0,  321.0,  322.0,  323.0,  324.0,  325.0,  326.0,  327.0,
+    328.0,  329.0,  330.0,  331.0,  332.0,  333.0,  334.0,  335.0,
+    336.0,  337.0,  338.0,  339.0,  340.0,  341.0,  342.0,  343.0,
+    344.0,  345.0,  346.0,  347.0,  348.0,  349.0,  350.0,  351.0,
+    352.0,  353.0,  354.0,  355.0,  356.0,  357.0,  358.0,  359.0,
+    360.0,  361.0,  362.0,  363.0,  364.0,  365.0,  366.0,  367.0,
+    368.0,  369.0,  370.0,  371.0,  372.0,  373.0,  374.0,  375.0,
+    376.0,  377.0,  378.0,  379.0,  380.0,  381.0,  382.0,  383.0,
+    384.0,  385.0,  386.0,  387.0,  388.0,  389.0,  390.0,  391.0,
+    392.0,  393.0,  394.0,  395.0,  396.0,  397.0,  398.0,  399.0,
+    400.0,  401.0,  402.0,  403.0,  404.0,  405.0,  406.0,  407.0,
+    408.0,  409.0,  410.0,  411.0,  412.0,  413.0,  414.0,  415.0,
+    416.0,  417.0,  418.0,  419.0,  420.0,  421.0,  422.0,  423.0,
+    424.0,  425.0,  426.0,  427.0,  428.0,  429.0,  430.0,  431.0,
+    432.0,  433.0,  434.0,  435.0,  436.0,  437.0,  438.0,  439.0,
+    440.0,  441.0,  442.0,  443.0,  444.0,  445.0,  446.0,  447.0,
+    448.0,  449.0,  450.0,  451.0,  452.0,  453.0,  454.0,  455.0,
+    456.0,  457.0,  458.0,  459.0,  460.0,  461.0,  462.0,  463.0,
+    464.0,  465.0,  466.0,  467.0,  468.0,  469.0,  470.0,  471.0,
+    472.0,  473.0,  474.0,  475.0,  476.0,  477.0,  478.0,  479.0,
+    480.0,  481.0,  482.0,  483.0,  484.0,  485.0,  486.0,  487.0,
+    488.0,  489.0,  490.0,  491.0,  492.0,  493.0,  494.0,  495.0,
+    496.0,  497.0,  498.0,  499.0,  500.0,  501.0,  502.0,  503.0,
+    504.0,  505.0,  506.0,  507.0,  508.0,  509.0,  510.0,  511.0,
+    512.0,  513.0,  514.0,  515.0,  516.0,  517.0,  518.0,  519.0,
+    520.0,  521.0,  522.0,  523.0,  524.0,  525.0,  526.0,  527.0,
+    528.0,  529.0,  530.0,  531.0,  532.0,  533.0,  534.0,  535.0,
+    536.0,  537.0,  538.0,  539.0,  540.0,  541.0,  542.0,  543.0,
+    544.0,  545.0,  546.0,  547.0,  548.0,  549.0,  550.0,  551.0,
+    552.0,  553.0,  554.0,  555.0,  556.0,  557.0,  558.0,  559.0,
+    560.0,  561.0,  562.0,  563.0,  564.0,  565.0,  566.0,  567.0,
+    568.0,  569.0,  570.0,  571.0,  572.0,  573.0,  574.0,  575.0,
+    576.0,  577.0,  578.0,  579.0,  580.0,  581.0,  582.0,  583.0,
+    584.0,  585.0,  586.0,  587.0,  588.0,  589.0,  590.0,  591.0,
+    592.0,  593.0,  594.0,  595.0,  596.0,  597.0,  598.0,  599.0,
+    600.0,  601.0,  602.0,  603.0,  604.0,  605.0,  606.0,  607.0,
+    608.0,  609.0,  610.0,  611.0,  612.0,  613.0,  614.0,  615.0,
+    616.0,  617.0,  618.0,  619.0,  620.0,  621.0,  622.0,  623.0,
+    624.0,  625.0,  626.0,  627.0,  628.0,  629.0,  630.0,  631.0,
+    632.0,  633.0,  634.0,  635.0,  636.0,  637.0,  638.0,  639.0,
+    640.0,  641.0,  642.0,  643.0,  644.0,  645.0,  646.0,  647.0,
+    648.0,  649.0,  650.0,  651.0,  652.0,  653.0,  654.0,  655.0,
+    656.0,  657.0,  658.0,  659.0,  660.0,  661.0,  662.0,  663.0,
+    664.0,  665.0,  666.0,  667.0,  668.0,  669.0,  670.0,  671.0,
+    672.0,  673.0,  674.0,  675.0,  676.0,  677.0,  678.0,  679.0,
+    680.0,  681.0,  682.0,  683.0,  684.0,  685.0,  686.0,  687.0,
+    688.0,  689.0,  690.0,  691.0,  692.0,  693.0,  694.0,  695.0,
+    696.0,  697.0,  698.0,  699.0,  700.0,  701.0,  702.0,  703.0,
+    704.0,  705.0,  706.0,  707.0,  708.0,  709.0,  710.0,  711.0,
+    712.0,  713.0,  714.0,  715.0,  716.0,  717.0,  718.0,  719.0,
+    720.0,  721.0,  722.0,  723.0,  724.0,  725.0,  726.0,  727.0,
+    728.0,  729.0,  730.0,  731.0,  732.0,  733.0,  734.0,  735.0,
+    736.0,  737.0,  738.0,  739.0,  740.0,  741.0,  742.0,  743.0,
+    744.0,  745.0,  746.0,  747.0,  748.0,  749.0,  750.0,  751.0,
+    752.0,  753.0,  754.0,  755.0,  756.0,  757.0,  758.0,  759.0,
+    760.0,  761.0,  762.0,  763.0,  764.0,  765.0,  766.0,  767.0,
+    768.0,  769.0,  770.0,  771.0,  772.0,  773.0,  774.0,  775.0,
+    776.0,  777.0,  778.0,  779.0,  780.0,  781.0,  782.0,  783.0,
+    784.0,  785.0,  786.0,  787.0,  788.0,  789.0,  790.0,  791.0,
+    792.0,  793.0,  794.0,  795.0,  796.0,  797.0,  798.0,  799.0,
+    800.0,  801.0,  802.0,  803.0,  804.0,  805.0,  806.0,  807.0,
+    808.0,  809.0,  810.0,  811.0,  812.0,  813.0,  814.0,  815.0,
+    816.0,  817.0,  818.0,  819.0,  820.0,  821.0,  822.0,  823.0,
+    824.0,  825.0,  826.0,  827.0,  828.0,  829.0,  830.0,  831.0,
+    832.0,  833.0,  834.0,  835.0,  836.0,  837.0,  838.0,  839.0,
+    840.0,  841.0,  842.0,  843.0,  844.0,  845.0,  846.0,  847.0,
+    848.0,  849.0,  850.0,  851.0,  852.0,  853.0,  854.0,  855.0,
+    856.0,  857.0,  858.0,  859.0,  860.0,  861.0,  862.0,  863.0,
+    864.0,  865.0,  866.0,  867.0,  868.0,  869.0,  870.0,  871.0,
+    872.0,  873.0,  874.0,  875.0,  876.0,  877.0,  878.0,  879.0,
+    880.0,  881.0,  882.0,  883.0,  884.0,  885.0,  886.0,  887.0,
+    888.0,  889.0,  890.0,  891.0,  892.0,  893.0,  894.0,  895.0,
+    896.0,  897.0,  898.0,  899.0,  900.0,  901.0,  902.0,  903.0,
+    904.0,  905.0,  906.0,  907.0,  908.0,  909.0,  910.0,  911.0,
+    912.0,  913.0,  914.0,  915.0,  916.0,  917.0,  918.0,  919.0,
+    920.0,  921.0,  922.0,  923.0,  924.0,  925.0,  926.0,  927.0,
+    928.0,  929.0,  930.0,  931.0,  932.0,  933.0,  934.0,  935.0,
+    936.0,  937.0,  938.0,  939.0,  940.0,  941.0,  942.0,  943.0,
+    944.0,  945.0,  946.0,  947.0,  948.0,  949.0,  950.0,  951.0,
+    952.0,  953.0,  954.0,  955.0,  956.0,  957.0,  958.0,  959.0,
+    960.0,  961.0,  962.0,  963.0,  964.0,  965.0,  966.0,  967.0,
+    968.0,  969.0,  970.0,  971.0,  972.0,  973.0,  974.0,  975.0,
+    976.0,  977.0,  978.0,  979.0,  980.0,  981.0,  982.0,  983.0,
+    984.0,  985.0,  986.0,  987.0,  988.0,  989.0,  990.0,  991.0,
+    992.0,  993.0,  994.0,  995.0,  996.0,  997.0,  998.0,  999.0,
+    1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0, 1006.0, 1007.0,
+    1008.0, 1009.0, 1010.0, 1011.0, 1012.0, 1013.0, 1014.0, 1015.0,
+    1016.0, 1017.0, 1018.0, 1019.0, 1020.0, 1021.0, 1022.0, 1023.0,
+    1024.0, 1025.0, 1026.0, 1027.0, 1028.0, 1029.0, 1030.0, 1031.0,
+    1032.0, 1033.0, 1034.0, 1035.0, 1036.0, 1037.0, 1038.0, 1039.0,
+    1040.0, 1041.0, 1042.0, 1043.0, 1044.0, 1045.0, 1046.0, 1047.0,
+    1048.0, 1049.0, 1050.0, 1051.0, 1052.0, 1053.0, 1054.0, 1055.0,
+    1056.0, 1057.0, 1058.0, 1059.0, 1060.0, 1061.0, 1062.0, 1063.0,
+    1064.0, 1065.0, 1066.0, 1067.0, 1068.0, 1069.0, 1070.0, 1071.0,
+    1072.0, 1073.0, 1074.0, 1075.0, 1076.0, 1077.0, 1078.0, 1079.0,
+    1080.0, 1081.0, 1082.0, 1083.0, 1084.0, 1085.0, 1086.0, 1087.0,
+    1088.0, 1089.0, 1090.0, 1091.0, 1092.0, 1093.0, 1094.0, 1095.0,
+    1096.0, 1097.0, 1098.0, 1099.0, 1100.0, 1101.0, 1102.0, 1103.0,
+    1104.0, 1105.0, 1106.0, 1107.0, 1108.0, 1109.0, 1110.0, 1111.0,
+    1112.0, 1113.0, 1114.0, 1115.0, 1116.0, 1117.0, 1118.0, 1119.0,
+    1120.0, 1121.0, 1122.0, 1123.0, 1124.0, 1125.0, 1126.0, 1127.0,
+    1128.0, 1129.0, 1130.0, 1131.0, 1132.0, 1133.0, 1134.0, 1135.0,
+    1136.0, 1137.0, 1138.0, 1139.0, 1140.0, 1141.0, 1142.0, 1143.0,
+    1144.0, 1145.0, 1146.0, 1147.0, 1148.0, 1149.0, 1150.0, 1151.0,
+    1152.0, 1153.0, 1154.0, 1155.0, 1156.0, 1157.0, 1158.0, 1159.0,
+    1160.0, 1161.0, 1162.0, 1163.0, 1164.0, 1165.0, 1166.0, 1167.0,
+    1168.0, 1169.0, 1170.0, 1171.0, 1172.0, 1173.0, 1174.0, 1175.0,
+    1176.0, 1177.0, 1178.0, 1179.0, 1180.0, 1181.0, 1182.0, 1183.0,
+    1184.0, 1185.0, 1186.0, 1187.0, 1188.0, 1189.0, 1190.0, 1191.0,
+    1192.0, 1193.0, 1194.0, 1195.0, 1196.0, 1197.0, 1198.0, 1199.0,
+    1200.0, 1201.0, 1202.0, 1203.0, 1204.0, 1205.0, 1206.0, 1207.0,
+    1208.0, 1209.0, 1210.0, 1211.0, 1212.0, 1213.0, 1214.0, 1215.0,
+    1216.0, 1217.0, 1218.0, 1219.0, 1220.0, 1221.0, 1222.0, 1223.0,
+    1224.0, 1225.0, 1226.0, 1227.0, 1228.0, 1229.0, 1230.0, 1231.0,
+    1232.0, 1233.0, 1234.0, 1235.0, 1236.0, 1237.0, 1238.0, 1239.0,
+    1240.0, 1241.0, 1242.0, 1243.0, 1244.0, 1245.0, 1246.0, 1247.0,
+    1248.0, 1249.0, 1250.0, 1251.0, 1252.0, 1253.0, 1254.0, 1255.0,
+    1256.0, 1257.0, 1258.0, 1259.0, 1260.0, 1261.0, 1262.0, 1263.0,
+    1264.0, 1265.0, 1266.0, 1267.0, 1268.0, 1269.0, 1270.0, 1271.0,
+    1272.0, 1273.0, 1274.0, 1275.0, 1276.0, 1277.0, 1278.0, 1279.0,
+    1280.0, 1281.0, 1282.0, 1283.0, 1284.0, 1285.0, 1286.0, 1287.0,
+    1288.0, 1289.0, 1290.0, 1291.0, 1292.0, 1293.0, 1294.0, 1295.0,
+    1296.0, 1297.0, 1298.0, 1299.0, 1300.0, 1301.0, 1302.0, 1303.0,
+    1304.0, 1305.0, 1306.0, 1307.0, 1308.0, 1309.0, 1310.0, 1311.0,
+    1312.0, 1313.0, 1314.0, 1315.0, 1316.0, 1317.0, 1318.0, 1319.0,
+    1320.0, 1321.0, 1322.0, 1323.0, 1324.0, 1325.0, 1326.0, 1327.0,
+    1328.0, 1329.0, 1330.0, 1331.0, 1332.0, 1333.0, 1334.0, 1335.0,
+    1336.0, 1337.0, 1338.0, 1339.0, 1340.0, 1341.0, 1342.0, 1343.0,
+    1344.0, 1345.0, 1346.0, 1347.0, 1348.0, 1349.0, 1350.0, 1351.0,
+    1352.0, 1353.0, 1354.0, 1355.0, 1356.0, 1357.0, 1358.0, 1359.0,
+    1360.0, 1361.0, 1362.0, 1363.0, 1364.0, 1365.0, 1366.0, 1367.0,
+    1368.0, 1369.0, 1370.0, 1371.0, 1372.0, 1373.0, 1374.0, 1375.0,
+    1376.0, 1377.0, 1378.0, 1379.0, 1380.0, 1381.0, 1382.0, 1383.0,
+    1384.0, 1385.0, 1386.0, 1387.0, 1388.0, 1389.0, 1390.0, 1391.0,
+    1392.0, 1393.0, 1394.0, 1395.0, 1396.0, 1397.0, 1398.0, 1399.0,
+    1400.0, 1401.0, 1402.0, 1403.0, 1404.0, 1405.0, 1406.0, 1407.0,
+    1408.0, 1409.0, 1410.0, 1411.0, 1412.0, 1413.0, 1414.0, 1415.0,
+    1416.0, 1417.0, 1418.0, 1419.0, 1420.0, 1421.0, 1422.0, 1423.0,
+    1424.0, 1425.0, 1426.0, 1427.0, 1428.0, 1429.0, 1430.0, 1431.0,
+    1432.0, 1433.0, 1434.0, 1435.0, 1436.0, 1437.0, 1438.0, 1439.0,
+    1440.0, 1441.0, 1442.0, 1443.0, 1444.0, 1445.0, 1446.0, 1447.0,
+    1448.0, 1449.0, 1450.0, 1451.0, 1452.0, 1453.0, 1454.0, 1455.0,
+    1456.0, 1457.0, 1458.0, 1459.0, 1460.0, 1461.0, 1462.0, 1463.0,
+    1464.0, 1465.0, 1466.0, 1467.0, 1468.0, 1469.0, 1470.0, 1471.0,
+    1472.0, 1473.0, 1474.0, 1475.0, 1476.0, 1477.0, 1478.0, 1479.0,
+    1480.0, 1481.0, 1482.0, 1483.0, 1484.0, 1485.0, 1486.0, 1487.0,
+    1488.0, 1489.0, 1490.0, 1491.0, 1492.0, 1493.0, 1494.0, 1495.0,
+    1496.0, 1497.0, 1498.0, 1499.0, 1500.0, 1501.0, 1502.0, 1503.0,
+    1504.0, 1505.0, 1506.0, 1507.0, 1508.0, 1509.0, 1510.0, 1511.0,
+    1512.0, 1513.0, 1514.0, 1515.0, 1516.0, 1517.0, 1518.0, 1519.0,
+    1520.0, 1521.0, 1522.0, 1523.0, 1524.0, 1525.0, 1526.0, 1527.0,
+    1528.0, 1529.0, 1530.0, 1531.0, 1532.0, 1533.0, 1534.0, 1535.0,
+    1536.0, 1537.0, 1538.0, 1539.0, 1540.0, 1541.0, 1542.0, 1543.0,
+    1544.0, 1545.0, 1546.0, 1547.0, 1548.0, 1549.0, 1550.0, 1551.0,
+    1552.0, 1553.0, 1554.0, 1555.0, 1556.0, 1557.0, 1558.0, 1559.0,
+    1560.0, 1561.0, 1562.0, 1563.0, 1564.0, 1565.0, 1566.0, 1567.0,
+    1568.0, 1569.0, 1570.0, 1571.0, 1572.0, 1573.0, 1574.0, 1575.0,
+    1576.0, 1577.0, 1578.0, 1579.0, 1580.0, 1581.0, 1582.0, 1583.0,
+    1584.0, 1585.0, 1586.0, 1587.0, 1588.0, 1589.0, 1590.0, 1591.0,
+    1592.0, 1593.0, 1594.0, 1595.0, 1596.0, 1597.0, 1598.0, 1599.0,
+    1600.0, 1601.0, 1602.0, 1603.0, 1604.0, 1605.0, 1606.0, 1607.0,
+    1608.0, 1609.0, 1610.0, 1611.0, 1612.0, 1613.0, 1614.0, 1615.0,
+    1616.0, 1617.0, 1618.0, 1619.0, 1620.0, 1621.0, 1622.0, 1623.0,
+    1624.0, 1625.0, 1626.0, 1627.0, 1628.0, 1629.0, 1630.0, 1631.0,
+    1632.0, 1633.0, 1634.0, 1635.0, 1636.0, 1637.0, 1638.0, 1639.0,
+    1640.0, 1641.0, 1642.0, 1643.0, 1644.0, 1645.0, 1646.0, 1647.0,
+    1648.0, 1649.0, 1650.0, 1651.0, 1652.0, 1653.0, 1654.0, 1655.0,
+    1656.0, 1657.0, 1658.0, 1659.0, 1660.0, 1661.0, 1662.0, 1663.0,
+    1664.0, 1665.0, 1666.0, 1667.0, 1668.0, 1669.0, 1670.0, 1671.0,
+    1672.0, 1673.0, 1674.0, 1675.0, 1676.0, 1677.0, 1678.0, 1679.0,
+    1680.0, 1681.0, 1682.0, 1683.0, 1684.0, 1685.0, 1686.0, 1687.0,
+    1688.0, 1689.0, 1690.0, 1691.0, 1692.0, 1693.0, 1694.0, 1695.0,
+    1696.0, 1697.0, 1698.0, 1699.0, 1700.0, 1701.0, 1702.0, 1703.0,
+    1704.0, 1705.0, 1706.0, 1707.0, 1708.0, 1709.0, 1710.0, 1711.0,
+    1712.0, 1713.0, 1714.0, 1715.0, 1716.0, 1717.0, 1718.0, 1719.0,
+    1720.0, 1721.0, 1722.0, 1723.0, 1724.0, 1725.0, 1726.0, 1727.0,
+    1728.0, 1729.0, 1730.0, 1731.0, 1732.0, 1733.0, 1734.0, 1735.0,
+    1736.0, 1737.0, 1738.0, 1739.0, 1740.0, 1741.0, 1742.0, 1743.0,
+    1744.0, 1745.0, 1746.0, 1747.0, 1748.0, 1749.0, 1750.0, 1751.0,
+    1752.0, 1753.0, 1754.0, 1755.0, 1756.0, 1757.0, 1758.0, 1759.0,
+    1760.0, 1761.0, 1762.0, 1763.0, 1764.0, 1765.0, 1766.0, 1767.0,
+    1768.0, 1769.0, 1770.0, 1771.0, 1772.0, 1773.0, 1774.0, 1775.0,
+    1776.0, 1777.0, 1778.0, 1779.0, 1780.0, 1781.0, 1782.0, 1783.0,
+    1784.0, 1785.0, 1786.0, 1787.0, 1788.0, 1789.0, 1790.0, 1791.0,
+    1792.0, 1793.0, 1794.0, 1795.0, 1796.0, 1797.0, 1798.0, 1799.0,
+    1800.0, 1801.0, 1802.0, 1803.0, 1804.0, 1805.0, 1806.0, 1807.0,
+    1808.0, 1809.0, 1810.0, 1811.0, 1812.0, 1813.0, 1814.0, 1815.0,
+    1816.0, 1817.0, 1818.0, 1819.0, 1820.0, 1821.0, 1822.0, 1823.0,
+    1824.0, 1825.0, 1826.0, 1827.0, 1828.0, 1829.0, 1830.0, 1831.0,
+    1832.0, 1833.0, 1834.0, 1835.0, 1836.0, 1837.0, 1838.0, 1839.0,
+    1840.0, 1841.0, 1842.0, 1843.0, 1844.0, 1845.0, 1846.0, 1847.0,
+    1848.0, 1849.0, 1850.0, 1851.0, 1852.0, 1853.0, 1854.0, 1855.0,
+    1856.0, 1857.0, 1858.0, 1859.0, 1860.0, 1861.0, 1862.0, 1863.0,
+    1864.0, 1865.0, 1866.0, 1867.0, 1868.0, 1869.0, 1870.0, 1871.0,
+    1872.0, 1873.0, 1874.0, 1875.0, 1876.0, 1877.0, 1878.0, 1879.0,
+    1880.0, 1881.0, 1882.0, 1883.0, 1884.0, 1885.0, 1886.0, 1887.0,
+    1888.0, 1889.0, 1890.0, 1891.0, 1892.0, 1893.0, 1894.0, 1895.0,
+    1896.0, 1897.0, 1898.0, 1899.0, 1900.0, 1901.0, 1902.0, 1903.0,
+    1904.0, 1905.0, 1906.0, 1907.0, 1908.0, 1909.0, 1910.0, 1911.0,
+    1912.0, 1913.0, 1914.0, 1915.0, 1916.0, 1917.0, 1918.0, 1919.0,
+    1920.0, 1921.0, 1922.0, 1923.0, 1924.0, 1925.0, 1926.0, 1927.0,
+    1928.0, 1929.0, 1930.0, 1931.0, 1932.0, 1933.0, 1934.0, 1935.0,
+    1936.0, 1937.0, 1938.0, 1939.0, 1940.0, 1941.0, 1942.0, 1943.0,
+    1944.0, 1945.0, 1946.0, 1947.0, 1948.0, 1949.0, 1950.0, 1951.0,
+    1952.0, 1953.0, 1954.0, 1955.0, 1956.0, 1957.0, 1958.0, 1959.0,
+    1960.0, 1961.0, 1962.0, 1963.0, 1964.0, 1965.0, 1966.0, 1967.0,
+    1968.0, 1969.0, 1970.0, 1971.0, 1972.0, 1973.0, 1974.0, 1975.0,
+    1976.0, 1977.0, 1978.0, 1979.0, 1980.0, 1981.0, 1982.0, 1983.0,
+    1984.0, 1985.0, 1986.0, 1987.0, 1988.0, 1989.0, 1990.0, 1991.0,
+    1992.0, 1993.0, 1994.0, 1995.0, 1996.0, 1997.0, 1998.0, 1999.0,
+    2000.0, 2001.0, 2002.0, 2003.0, 2004.0, 2005.0, 2006.0, 2007.0,
+    2008.0, 2009.0, 2010.0, 2011.0, 2012.0, 2013.0, 2014.0, 2015.0,
+    2016.0, 2017.0, 2018.0, 2019.0, 2020.0, 2021.0, 2022.0, 2023.0,
+    2024.0, 2025.0, 2026.0, 2027.0, 2028.0, 2029.0, 2030.0, 2031.0,
+    2032.0, 2033.0, 2034.0, 2035.0, 2036.0, 2037.0, 2038.0, 2039.0,
+    2040.0, 2041.0, 2042.0, 2043.0, 2044.0, 2045.0, 2046.0, 2047.0,
+    0.0
+};
+
+const double NOD_data[] = {
+    1.0,    2.0,    4.0,    8.0,
+    0.0
+};
+
+const double NODIV_data[] = {
+    1.0,    2.0,    4.0,
+    0.0
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/lvds/lvds_pll_main.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,239 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lvds_pll_main.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        lvds pll setting value
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <stdlib.h>
+#include    <math.h>
+
+#include    "r_typedefs.h"
+#include    "lvds_pll_calc.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* FIN: LVDS PLL input frequency */
+#define     FIN_MIN             (9.0)           /*!< The lower limit of the FIN */
+#define     FIN_MAX             (30.0)          /*!< The upper limit of the FIN */
+/* FREF */
+#define     FREF_MIN            (2.5)           /*!< The lower limit of the FREF */
+#define     FREF_MAX            (30.0)          /*!< The upper limit of the FREF */
+/* FVCO: VCO output frequency */
+#define     FVCO_MIN            (750.0)         /*!< The lower limit of the FVCO */
+#define     FVCO_MAX            (1630.0)        /*!< The upper limit of the FVCO */
+/* FOUT: LVDS PLL output frequency */
+#define     FOUT_MIN            (0.0)           /*!< The lower limit of the FOUT */
+#define     FOUT_MAX            (609.0)         /*!< The upper limit of the FOUT */
+
+#define     DIVIDER_3           (7.0)           /*!< The frequency dividing value for frequency divider 3 */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const double NIDIV_data[];
+extern const double NRD_data[];
+extern const double NFD_data[];
+extern const double NOD_data[];
+extern const double NODIV_data[];
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static double   InputClock;
+static double   OutputClock;
+static int      LvdsUsed;
+
+
+
+/**************************************************************************//**
+ * @brief
+ * @param       [in,out]param
+ * @param       [in]fout
+ * @retval      int
+ *****************************************************************************/
+static int compare_nodiv (pll_parameter_t * param, double fout)
+{
+    int             change;
+    const double  * nodiv_list;
+    double          diff_freq;
+
+    change      = 0;
+    nodiv_list  = NODIV_data;
+    while (*nodiv_list != 0.0) {
+        diff_freq   = fabs(OutputClock - (fout / *nodiv_list));
+        if (param->comparison_freq > diff_freq) {
+            param->comparison_freq  = diff_freq;
+            param->output_freq      = fout / *nodiv_list;
+            param->nodiv            = *nodiv_list;
+            change                  = 1;
+        }
+        nodiv_list++;
+    }
+    return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param       [in,out]param
+ * @param       [in]fout
+ * @retval      int
+ *****************************************************************************/
+static int compare_div3 (pll_parameter_t * param, double fout)
+{
+    double  diff_freq;
+    int     change;
+
+    change      = 0;
+    diff_freq   = fabs(OutputClock - (fout / DIVIDER_3));
+
+    if (param->comparison_freq > diff_freq) {
+        param->comparison_freq  = diff_freq;
+        param->output_freq      = fout / DIVIDER_3;
+        change                  = 1;
+    }
+    return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param       [out]param
+ * @retval      None
+ *****************************************************************************/
+static void SeekValue (pll_parameter_t * param)
+{
+    const double  * nidiv_list;
+    const double  * nrd_list;
+    const double  * nfd_list;
+    const double  * nod_list;
+
+    double  fin;
+    double  fref;
+    double  fvco;
+    double  fout;
+    int     ret;
+
+    nidiv_list = NIDIV_data;
+    while (*nidiv_list != 0.0) {
+        fin = InputClock / *nidiv_list;
+        if ((fin < FIN_MIN) || (FIN_MAX < fin)) {
+            nidiv_list++;
+            continue;
+        }
+        nrd_list = NRD_data;
+        while (*nrd_list != 0.0) {
+            fref = fin / *nrd_list;
+            if ((fref < FREF_MIN) || (FREF_MAX < fref)) {
+                nrd_list++;
+                continue;
+            }
+            nfd_list = NFD_data;
+            while (*nfd_list != 0.0) {
+                fvco = fref * (*nfd_list);
+                if ((fvco < FVCO_MIN) || (FVCO_MAX < fvco)) {
+                    nfd_list++;
+                    continue;
+                }
+                nod_list = NOD_data;
+                while (*nod_list != 0.0) {
+                    fout = fvco / *nod_list;
+                    if ((fout < FOUT_MIN) || (FOUT_MAX < fout)) {
+                        nod_list++;
+                        continue;
+                    }
+
+                    if (LvdsUsed == 0) {
+                        ret = compare_nodiv(param, fout);
+                    } else {
+                        ret = compare_div3(param, fout);
+                    }
+                    if (ret != 0) {
+                        param->nidiv    = *nidiv_list;
+                        param->nrd      = *nrd_list;
+                        param->nfd      = *nfd_list;
+                        param->nod      = *nod_list;
+                    }
+                    nod_list++;
+                }
+                nfd_list++;
+            }
+            nrd_list++;
+        }
+        nidiv_list++;
+    }
+}
+/**************************************************************************//**
+ * @brief       PLL value Calculation function
+ * @param[in]   InClock     : Input clock frequency [MHz]
+ * @param[in]   OuClock     : Output clock frequency [MHz]
+ * @param[in]   Lvds        : The LVDS output interface is used (=1) or not (=0)
+ * @param[out]  result      : pll_parameter_t
+ * @retval      error (-1)
+******************************************************************************/
+int32_t lvds_pll_calc(
+    const double      InClock,
+    const double      OuClock,
+    const uint32_t    Lvds,
+    pll_parameter_t * result  )
+{
+    result->comparison_freq  = 1000.0;
+    result->output_freq      = 0.0;
+    result->nidiv            = 0.0;
+    result->nrd              = 0.0;
+    result->nfd              = 0.0;
+    result->nod              = 0.0;
+    result->nodiv            = 0.0;
+
+    InputClock   = InClock;
+    OutputClock  = OuClock;
+    LvdsUsed     = Lvds;
+
+    /* Calculation */
+    SeekValue(result);
+
+    result->nidiv = result->nidiv/2;
+    result->nodiv = result->nodiv/2;
+    if( result->nod <= 4 ) {
+        result->nod = result->nod/2;
+    } else if( result->nod == 8 ) {
+        result->nod = 3;
+    } else {
+    }
+    result->nrd -=1;        /* nrd-1 */
+    return 0;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1H/video_decoder/video_decoder.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,990 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         video_decoder.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Video decoder function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+#include    <string.h>
+
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+#include    "video_decoder.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     STBCR7_BIT7                 (0x80u)
+#define     STBCR7_BIT6                 (0x40u)
+
+/*! Video decoder recommended value */
+#define SRCLEFT_NTSC_3_58       ((uint16_t)256u)
+#define SRCLEFT_NTSC_4_43       ((uint16_t)256u)
+#define SRCLEFT_PAL_4_43        ((uint16_t)256u)
+#define SRCLEFT_PAL_M           ((uint16_t)256u)
+#define SRCLEFT_PAL_N           ((uint16_t)256u)
+#define SRCLEFT_SECAM           ((uint16_t)256u)
+#define SRCLEFT_NTSC_443_60     ((uint16_t)256u)
+#define SRCLEFT_PAL_60          ((uint16_t)256u)
+
+#define SRCTOP_NTSC_3_58        ((uint16_t)16u)
+#define SRCTOP_NTSC_4_43        ((uint16_t)19u)
+#define SRCTOP_PAL_4_43         ((uint16_t)19u)
+#define SRCTOP_PAL_M            ((uint16_t)16u)
+#define SRCTOP_PAL_N            ((uint16_t)19u)
+#define SRCTOP_SECAM            ((uint16_t)19u)
+#define SRCTOP_NTSC_443_60      ((uint16_t)16u)
+#define SRCTOP_PAL_60           ((uint16_t)16u)
+
+#define SRCHEIGHT_NTSC_3_58     ((uint16_t)241u)
+#define SRCHEIGHT_NTSC_4_43     ((uint16_t)288u)
+#define SRCHEIGHT_PAL_4_43      ((uint16_t)288u)
+#define SRCHEIGHT_PAL_M         ((uint16_t)241u)
+#define SRCHEIGHT_PAL_N         ((uint16_t)288u)
+#define SRCHEIGHT_SECAM         ((uint16_t)288u)
+#define SRCHEIGHT_NTSC_443_60   ((uint16_t)241u)
+#define SRCHEIGHT_PAL_60        ((uint16_t)241u)
+
+#define SRCWIDTH_NTSC_3_58      ((uint16_t)1428u)
+#define SRCWIDTH_NTSC_4_43      ((uint16_t)1412u)
+#define SRCWIDTH_PAL_4_43       ((uint16_t)1412u)
+#define SRCWIDTH_PAL_M          ((uint16_t)1428u)
+#define SRCWIDTH_PAL_N          ((uint16_t)1412u)
+#define SRCWIDTH_SECAM          ((uint16_t)1412u)
+#define SRCWIDTH_NTSC_443_60    ((uint16_t)1428u)
+#define SRCWIDTH_PAL_60         ((uint16_t)1428u)
+
+#define HAFCTYP_NTSC_3_58       ((uint16_t)692u)
+#define HAFCTYP_NTSC_4_43       ((uint16_t)704u)
+#define HAFCTYP_PAL_4_43        ((uint16_t)704u)
+#define HAFCTYP_PAL_M           ((uint16_t)692u)
+#define HAFCTYP_PAL_N           ((uint16_t)704u)
+#define HAFCTYP_SECAM           ((uint16_t)704u)
+#define HAFCTYP_NTSC_443_60     ((uint16_t)692u)
+#define HAFCTYP_PAL_60          ((uint16_t)692u)
+
+#define HAFCMAX_NTSC_3_58       ((uint16_t)792u)
+#define HAFCMAX_NTSC_4_43       ((uint16_t)785u)
+#define HAFCMAX_PAL_4_43        ((uint16_t)785u)
+#define HAFCMAX_PAL_M           ((uint16_t)792u)
+#define HAFCMAX_PAL_N           ((uint16_t)785u)
+#define HAFCMAX_SECAM           ((uint16_t)785u)
+#define HAFCMAX_NTSC_443_60     ((uint16_t)792u)
+#define HAFCMAX_PAL_60          ((uint16_t)792u)
+
+#define HAFCMIN_NTSC_3_58       ((uint16_t)592u)
+#define HAFCMIN_NTSC_4_43       ((uint16_t)630u)
+#define HAFCMIN_PAL_4_43        ((uint16_t)630u)
+#define HAFCMIN_PAL_M           ((uint16_t)592u)
+#define HAFCMIN_PAL_N           ((uint16_t)630u)
+#define HAFCMIN_SECAM           ((uint16_t)630u)
+#define HAFCMIN_NTSC_443_60     ((uint16_t)592u)
+#define HAFCMIN_PAL_60          ((uint16_t)592u)
+
+#define VCDWINDOW_NTSC_3_58     ((uint16_t)30u)
+#define VCDWINDOW_NTSC_4_43     ((uint16_t)30u)
+#define VCDWINDOW_PAL_4_43      ((uint16_t)30u)
+#define VCDWINDOW_PAL_M         ((uint16_t)30u)
+#define VCDWINDOW_PAL_N         ((uint16_t)30u)
+#define VCDWINDOW_SECAM         ((uint16_t)30u)
+#define VCDWINDOW_NTSC_443_60   ((uint16_t)30u)
+#define VCDWINDOW_PAL_60        ((uint16_t)30u)
+
+#define VCDOFFSET_NTSC_3_58     ((uint16_t)15u)
+#define VCDOFFSET_NTSC_4_43     ((uint16_t)15u)
+#define VCDOFFSET_PAL_4_43      ((uint16_t)15u)
+#define VCDOFFSET_PAL_M         ((uint16_t)15u)
+#define VCDOFFSET_PAL_N         ((uint16_t)15u)
+#define VCDOFFSET_SECAM         ((uint16_t)15u)
+#define VCDOFFSET_NTSC_443_60   ((uint16_t)15u)
+#define VCDOFFSET_PAL_60        ((uint16_t)15u)
+
+#define ACCLEVEL_NTSC_3_58      ((uint16_t)220u)
+#define ACCLEVEL_NTSC_4_43      ((uint16_t)220u)
+#define ACCLEVEL_PAL_4_43       ((uint16_t)220u)
+#define ACCLEVEL_PAL_M          ((uint16_t)230u)
+#define ACCLEVEL_PAL_N          ((uint16_t)230u)
+#define ACCLEVEL_SECAM          ((uint16_t)220u)
+#define ACCLEVEL_NTSC_443_60    ((uint16_t)220u)
+#define ACCLEVEL_PAL_60         ((uint16_t)230u)
+
+#define AGCLEVEL_NTSC_3_58      ((uint16_t)230u)
+#define AGCLEVEL_NTSC_4_43      ((uint16_t)230u)
+#define AGCLEVEL_PAL_4_43       ((uint16_t)242u)
+#define AGCLEVEL_PAL_M          ((uint16_t)242u)
+#define AGCLEVEL_PAL_N          ((uint16_t)242u)
+#define AGCLEVEL_SECAM          ((uint16_t)242u)
+#define AGCLEVEL_NTSC_443_60    ((uint16_t)230u)
+#define AGCLEVEL_PAL_60         ((uint16_t)242u)
+
+#define K15_NTSC_3_58           ((uint16_t)2u)
+#define K15_NTSC_4_43           ((uint16_t)2u)
+#define K15_PAL_4_43            ((uint16_t)2u)
+#define K15_PAL_M               ((uint16_t)2u)
+#define K15_PAL_N               ((uint16_t)2u)
+#define K15_SECAM               ((uint16_t)2u)
+#define K15_NTSC_443_60         ((uint16_t)2u)
+#define K15_PAL_60              ((uint16_t)2u)
+
+#define K13_NTSC_3_58           ((uint16_t)8u)
+#define K13_NTSC_4_43           ((uint16_t)8u)
+#define K13_PAL_4_43            ((uint16_t)8u)
+#define K13_PAL_M               ((uint16_t)8u)
+#define K13_PAL_N               ((uint16_t)8u)
+#define K13_SECAM               ((uint16_t)8u)
+#define K13_NTSC_443_60         ((uint16_t)8u)
+#define K13_PAL_60              ((uint16_t)8u)
+
+#define K11_NTSC_3_58           ((uint16_t)4u)
+#define K11_NTSC_4_43           ((uint16_t)4u)
+#define K11_PAL_4_43            ((uint16_t)3u)
+#define K11_PAL_M               ((uint16_t)3u)
+#define K11_PAL_N               ((uint16_t)3u)
+#define K11_SECAM               ((uint16_t)4u)
+#define K11_NTSC_443_60         ((uint16_t)4u)
+#define K11_PAL_60              ((uint16_t)3u)
+
+#define K16_NTSC_3_58           ((uint16_t)3u)
+#define K16_NTSC_4_43           ((uint16_t)3u)
+#define K16_PAL_4_43            ((uint16_t)4u)
+#define K16_PAL_M               ((uint16_t)4u)
+#define K16_PAL_N               ((uint16_t)4u)
+#define K16_SECAM               ((uint16_t)3u)
+#define K16_NTSC_443_60         ((uint16_t)3u)
+#define K16_PAL_60              ((uint16_t)4u)
+
+#define K14_NTSC_3_58           ((uint16_t)16u)
+#define K14_NTSC_4_43           ((uint16_t)16u)
+#define K14_PAL_4_43            ((uint16_t)63u)
+#define K14_PAL_M               ((uint16_t)63u)
+#define K14_PAL_N               ((uint16_t)63u)
+#define K14_SECAM               ((uint16_t)16u)
+#define K14_NTSC_443_60         ((uint16_t)16u)
+#define K14_PAL_60              ((uint16_t)63u)
+
+#define K12_NTSC_3_58           ((uint16_t)8u)
+#define K12_NTSC_4_43           ((uint16_t)8u)
+#define K12_PAL_4_43            ((uint16_t)2u)
+#define K12_PAL_M               ((uint16_t)2u)
+#define K12_PAL_N               ((uint16_t)2u)
+#define K12_SECAM               ((uint16_t)1u)
+#define K12_NTSC_443_60         ((uint16_t)8u)
+#define K12_PAL_60              ((uint16_t)2u)
+
+#define K22A_NTSC_3_58          ((uint16_t)32u)
+#define K22A_NTSC_4_43          ((uint16_t)32u)
+#define K22A_PAL_4_43           ((uint16_t)32u)
+#define K22A_PAL_M              ((uint16_t)32u)
+#define K22A_PAL_N              ((uint16_t)32u)
+#define K22A_SECAM              ((uint16_t)32u)
+#define K22A_NTSC_443_60        ((uint16_t)32u)
+#define K22A_PAL_60             ((uint16_t)32u)
+
+#define K21A_NTSC_3_58          ((uint16_t)6u)
+#define K21A_NTSC_4_43          ((uint16_t)6u)
+#define K21A_PAL_4_43           ((uint16_t)10u)
+#define K21A_PAL_M              ((uint16_t)10u)
+#define K21A_PAL_N              ((uint16_t)10u)
+#define K21A_SECAM              ((uint16_t)10u)
+#define K21A_NTSC_443_60        ((uint16_t)6u)
+#define K21A_PAL_60             ((uint16_t)10u)
+
+#define K22B_NTSC_3_58          ((uint16_t)8u)
+#define K22B_NTSC_4_43          ((uint16_t)8u)
+#define K22B_PAL_4_43           ((uint16_t)15u)
+#define K22B_PAL_M              ((uint16_t)15u)
+#define K22B_PAL_N              ((uint16_t)15u)
+#define K22B_SECAM              ((uint16_t)15u)
+#define K22B_NTSC_443_60        ((uint16_t)8u)
+#define K22B_PAL_60             ((uint16_t)15u)
+
+#define K21B_NTSC_3_58          ((uint16_t)6u)
+#define K21B_NTSC_4_43          ((uint16_t)6u)
+#define K21B_PAL_4_43           ((uint16_t)10u)
+#define K21B_PAL_M              ((uint16_t)10u)
+#define K21B_PAL_N              ((uint16_t)10u)
+#define K21B_SECAM              ((uint16_t)6u)
+#define K21B_NTSC_443_60        ((uint16_t)6u)
+#define K21B_PAL_60             ((uint16_t)10u)
+
+#define K23B_NTSC_3_58          ((uint16_t)6u)
+#define K23B_NTSC_4_43          ((uint16_t)6u)
+#define K23B_PAL_4_43           ((uint16_t)3u)
+#define K23B_PAL_M              ((uint16_t)3u)
+#define K23B_PAL_N              ((uint16_t)3u)
+#define K23B_SECAM              ((uint16_t)3u)
+#define K23B_NTSC_443_60        ((uint16_t)6u)
+#define K23B_PAL_60             ((uint16_t)3u)
+
+#define K23A_NTSC_3_58          ((uint16_t)3u)
+#define K23A_NTSC_4_43          ((uint16_t)3u)
+#define K23A_PAL_4_43           ((uint16_t)3u)
+#define K23A_PAL_M              ((uint16_t)3u)
+#define K23A_PAL_N              ((uint16_t)3u)
+#define K23A_SECAM              ((uint16_t)3u)
+#define K23A_NTSC_443_60        ((uint16_t)3u)
+#define K23A_PAL_60             ((uint16_t)3u)
+
+#define K24_NTSC_3_58           ((uint16_t)5u)
+#define K24_NTSC_4_43           ((uint16_t)5u)
+#define K24_PAL_4_43            ((uint16_t)8u)
+#define K24_PAL_M               ((uint16_t)8u)
+#define K24_PAL_N               ((uint16_t)8u)
+#define K24_SECAM               ((uint16_t)8u)
+#define K24_NTSC_443_60         ((uint16_t)5u)
+#define K24_PAL_60              ((uint16_t)8u)
+
+/* SyncSep */
+#define SYNCMAXDUTY_H_VALUE  ((uint16_t)15u)
+#define SYNCMINDUTY_H_VALUE  ((uint16_t)10u)
+#define CSYNCSLICE_H_VALUE   ((uint16_t)146u)
+#define SYNCMAXDUTY_V_VALUE  ((uint16_t)15u)
+#define SYNCMINDUTY_V_VALUE  ((uint16_t)9u)
+#define VSYNCSLICE_VALUE     ((uint16_t)10u)
+#define CSYNCSLICE_V_VALUE   ((uint16_t)146u)
+#define HAFCGAIN_VALUE       ((uint16_t)12u)
+#define HAFCSTART_VALUE      ((uint16_t)0u)
+#define HAFCEND_VALUE        ((uint16_t)8u)
+#define AGCRESPONSE_VALUE    ((uint16_t)4u)
+#define AGCPRECIS_VALUE      ((uint16_t)10u)
+#define PGA_GAIN_VALUE       ((uint16_t)0u)
+#define PEAKATTACK_VALUE     ((uint16_t)2u)
+#define PEAKRELEASE_VALUE    ((uint16_t)3u)
+#define MAXPEAKSAMPLES_VALUE ((uint16_t)20u)
+
+/* YcSep */
+#define RADJ_O_LEVEL0_VALUE  ((uint16_t)928u)
+#define RADJ_U_LEVEL0_VALUE  ((uint16_t)32u)
+#define RADJ_O_LEVEL1_VALUE  ((uint16_t)960u)
+#define RADJ_U_LEVEL1_VALUE  ((uint16_t)48u)
+#define RADJ_O_LEVEL2_VALUE  ((uint16_t)992u)
+#define RADJ_U_LEVEL2_VALUE  ((uint16_t)64u)
+#define V_Y_LEVEL_VALUE      ((uint16_t)0u)
+
+/* ChromaDec */
+#define LUMADELAY_VALUE      ((uint16_t)0u)
+#define LOOPGAIN_VALUE       ((uint16_t)3u)
+#define LOCKLIMIT_VALUE      ((uint16_t)1u)
+#define BGPCHECK_VALUE       ((uint16_t)0u)
+#define BGPWIDTH_VALUE       ((uint16_t)54u)
+#define BGPSTART_VALUE       ((uint16_t)110u)
+#define CHROMAMAINGAIN_VALUE ((uint16_t)210u)
+#define ACCRESPONSE_VALUE    ((uint16_t)1u)
+#define ACCPRECIS_VALUE      ((uint16_t)8u)
+#define KILLERLEVEL_VALUE    ((uint16_t)4u)
+#define KILLEROFFSET_VALUE   ((uint16_t)5u)
+
+/* DigitalClamp */
+#define BLANKLEVEL_Y_VALUE   ((uint16_t)984u)
+#define DCPPOS_Y_VALUE       ((uint16_t)162u)
+#define BLANKLEVEL_CB_VALUE  ((uint16_t)0u)
+#define BLANKLEVEL_CR_VALUE  ((uint16_t)0u)
+#define DCPPOS_C_VALUE       ((uint16_t)54u)
+#define ACFLAGTIME_VALUE     ((uint16_t)0u)
+#define ACFFILTER_VALUE      ((uint16_t)3u)
+#define DCPRESPONSE_VALUE    ((uint16_t)0u)
+#define DCPSTART_VALUE       ((uint16_t)16u)
+#define DCPEND_VALUE         ((uint16_t)16u)
+#define DCPWIDTH_VALUE       ((uint16_t)27u)
+
+/* Output */
+#define Y_GAIN2_VALUE        ((uint16_t)816u)
+#define CB_GAIN2_VALUE       ((uint16_t)663u)
+#define CR_GAIN2_VALUE       ((uint16_t)663u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Video decoder recommended value */
+typedef struct {
+    /* Capturing position setting */
+    uint16_t            srcleft;
+    uint16_t            srctop;
+    uint16_t            srcheight;
+    uint16_t            srcwidth;
+    /* Horizontal AFC setting */
+    uint16_t            hafctyp;
+    uint16_t            hafcmax;
+    uint16_t            hafcmin;
+    /* Vertical countdown setting */
+    vdec_onoff_t        novcd50_;
+    vdec_onoff_t        novcd60_;
+    vdec_vcddefault_t   vcddefault;
+    uint16_t            vcdwindow;
+    uint16_t            vcdoffset;
+    /* BCO setting */
+    vdec_color_sys_t    defaultsys;
+    vdec_onoff_t        nontsc358_;
+    vdec_onoff_t        nontsc443_;
+    vdec_onoff_t        nopalm_;
+    vdec_onoff_t        nopaln_;
+    vdec_onoff_t        nopal443_;
+    vdec_onoff_t        nosecam_;
+    /* ACC level setting */
+    uint16_t            acclevel;
+    /* AGC level setting */
+    uint16_t            agclevel;
+    /* Y/C separation setting */
+    uint16_t            k15;
+    uint16_t            k13;
+    uint16_t            k11;
+    uint16_t            k16;
+    uint16_t            k14;
+    uint16_t            k12;
+    uint16_t            k22A;
+    uint16_t            k21A;
+    uint16_t            k22B;
+    uint16_t            k21B;
+    uint16_t            k23B;
+    uint16_t            k23A;
+    uint16_t            k24;
+    vdec_onoff_t        det2_on;
+    vdec_filmix_ratio_t hsel_mix_y;
+    vdec_filmix_ratio_t vsel_mix_y;
+    vdec_filmix_ratio_t hvsel_mix_y;
+    vdec_filmix_ratio_t det2_mix_c;
+    vdec_filmix_ratio_t det2_mix_y;
+    vdec_2dfil_mdsel_t  fil2_mode_2d;
+    vdec_2d_fil_sel_t   fil2_narrow_2d;
+} video_recmd_val_t;
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void Input(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void SyncSep(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void YcSep(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void ChromaDec(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void DigitalClamp(const vdec_channel_t channel);
+static void Output(const vdec_channel_t channel);
+
+static void init_func(const uint32_t user_num);
+
+static const video_recmd_val_t RecommendedValue[GRPH_COL_SYS_NUM] = {
+    {   /* NTSC-3.58 */
+        /* Capturing position setting */
+        SRCLEFT_NTSC_3_58, SRCTOP_NTSC_3_58, SRCHEIGHT_NTSC_3_58, SRCWIDTH_NTSC_3_58,
+        /* Horizontal AFC setting */
+        HAFCTYP_NTSC_3_58, HAFCMAX_NTSC_3_58, HAFCMIN_NTSC_3_58,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_NTSC_3_58, VCDOFFSET_NTSC_3_58,
+        /* BCO setting */
+        VDEC_COL_SYS_NTSC, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_NTSC_3_58,
+        /* AGC level setting */
+        AGCLEVEL_NTSC_3_58,
+        /* Y/C separation setting */
+        K15_NTSC_3_58, K13_NTSC_3_58, K11_NTSC_3_58, K16_NTSC_3_58, K14_NTSC_3_58, K12_NTSC_3_58,
+        K22A_NTSC_3_58, K21A_NTSC_3_58, K22B_NTSC_3_58, K21B_NTSC_3_58, K23B_NTSC_3_58, K23A_NTSC_3_58, K24_NTSC_3_58,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* NTSC-4.43 */
+        /* Capturing position setting */
+        SRCLEFT_NTSC_4_43, SRCTOP_NTSC_4_43, SRCHEIGHT_NTSC_4_43, SRCWIDTH_NTSC_4_43,
+        /* Horizontal AFC setting */
+        HAFCTYP_NTSC_4_43, HAFCMAX_NTSC_4_43, HAFCMIN_NTSC_4_43,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_NTSC_4_43, VCDOFFSET_NTSC_4_43,
+        /* BCO setting */
+        VDEC_COL_SYS_NTSC, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_NTSC_4_43,
+        /* AGC level setting */
+        AGCLEVEL_NTSC_4_43,
+        /* Y/C separation setting */
+        K15_NTSC_4_43, K13_NTSC_4_43, K11_NTSC_4_43, K16_NTSC_4_43, K14_NTSC_4_43, K12_NTSC_4_43,
+        K22A_NTSC_4_43, K21A_NTSC_4_43, K22B_NTSC_4_43, K21B_NTSC_4_43, K23B_NTSC_4_43, K23A_NTSC_4_43, K24_NTSC_4_43,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-4.43 */
+        /* Capturing position setting */
+        SRCLEFT_PAL_4_43, SRCTOP_PAL_4_43, SRCHEIGHT_PAL_4_43, SRCWIDTH_PAL_4_43,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_4_43, HAFCMAX_PAL_4_43, HAFCMIN_PAL_4_43,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_PAL_4_43, VCDOFFSET_PAL_4_43,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_4_43,
+        /* AGC level setting */
+        AGCLEVEL_PAL_4_43,
+        /* Y/C separation setting */
+        K15_PAL_4_43, K13_PAL_4_43, K11_PAL_4_43, K16_PAL_4_43, K14_PAL_4_43, K12_PAL_4_43,
+        K22A_PAL_4_43, K21A_PAL_4_43, K22B_PAL_4_43, K21B_PAL_4_43, K23B_PAL_4_43, K23A_PAL_4_43, K24_PAL_4_43,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-M */
+        /* Capturing position setting */
+        SRCLEFT_PAL_M, SRCTOP_PAL_M, SRCHEIGHT_PAL_M, SRCWIDTH_PAL_M,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_M, HAFCMAX_PAL_M, HAFCMIN_PAL_M,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_PAL_M, VCDOFFSET_PAL_M,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_M,
+        /* AGC level setting */
+        AGCLEVEL_PAL_M,
+        /* Y/C separation setting */
+        K15_PAL_M, K13_PAL_M, K11_PAL_M, K16_PAL_M, K14_PAL_M, K12_PAL_M,
+        K22A_PAL_M, K21A_PAL_M, K22B_PAL_M, K21B_PAL_M, K23B_PAL_M, K23A_PAL_M, K24_PAL_M,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-N */
+        /* Capturing position setting */
+        SRCLEFT_PAL_N, SRCTOP_PAL_N, SRCHEIGHT_PAL_N, SRCWIDTH_PAL_N,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_N, HAFCMAX_PAL_N, HAFCMIN_PAL_N,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_PAL_N, VCDOFFSET_PAL_N,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_N,
+        /* AGC level setting */
+        AGCLEVEL_PAL_N,
+        /* Y/C separation setting */
+        K15_PAL_N, K13_PAL_N, K11_PAL_N, K16_PAL_N, K14_PAL_N, K12_PAL_N,
+        K22A_PAL_N, K21A_PAL_N, K22B_PAL_N, K21B_PAL_N, K23B_PAL_N, K23A_PAL_N, K24_PAL_N,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* SECAM */
+        /* Capturing position setting */
+        SRCLEFT_SECAM, SRCTOP_SECAM, SRCHEIGHT_SECAM, SRCWIDTH_SECAM,
+        /* Horizontal AFC setting */
+        HAFCTYP_SECAM, HAFCMAX_SECAM, HAFCMIN_SECAM,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_SECAM, VCDOFFSET_SECAM,
+        /* BCO setting */
+        VDEC_COL_SYS_SECAM, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON,
+        /* ACC level setting */
+        ACCLEVEL_SECAM,
+        /* AGC level setting */
+        AGCLEVEL_SECAM,
+        /* Y/C separation setting */
+        K15_SECAM, K13_SECAM, K11_SECAM, K16_SECAM, K14_SECAM, K12_SECAM,
+        K22A_SECAM, K21A_SECAM, K22B_SECAM, K21B_SECAM, K23B_SECAM, K23A_SECAM, K24_SECAM,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* NTSC-4.43 (60Hz) */
+        /* Capturing position setting */
+        SRCLEFT_NTSC_443_60, SRCTOP_NTSC_443_60, SRCHEIGHT_NTSC_443_60, SRCWIDTH_NTSC_443_60,
+        /* Horizontal AFC setting */
+        HAFCTYP_NTSC_443_60, HAFCMAX_NTSC_443_60, HAFCMIN_NTSC_443_60,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_NTSC_443_60, VCDOFFSET_NTSC_443_60,
+        /* BCO setting */
+        VDEC_COL_SYS_NTSC, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_NTSC_443_60,
+        /* AGC level setting */
+        AGCLEVEL_NTSC_443_60,
+        /* Y/C separation setting */
+        K15_NTSC_443_60, K13_NTSC_443_60, K11_NTSC_443_60, K16_NTSC_443_60, K14_NTSC_443_60, K12_NTSC_443_60,
+        K22A_NTSC_443_60, K21A_NTSC_443_60, K22B_NTSC_443_60, K21B_NTSC_443_60, K23B_NTSC_443_60, K23A_NTSC_443_60,
+        K24_NTSC_443_60,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-60 */
+        /* Capturing position setting */
+        SRCLEFT_PAL_60, SRCTOP_PAL_60, SRCHEIGHT_PAL_60, SRCWIDTH_PAL_60,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_60, HAFCMAX_PAL_60, HAFCMIN_PAL_60,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_PAL_60, VCDOFFSET_PAL_60,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_60,
+        /* AGC level setting */
+        AGCLEVEL_PAL_60,
+        /* Y/C separation setting */
+        K15_PAL_60, K13_PAL_60, K11_PAL_60, K16_PAL_60, K14_PAL_60, K12_PAL_60,
+        K22A_PAL_60, K21A_PAL_60, K22B_PAL_60, K21B_PAL_60, K23B_PAL_60, K23A_PAL_60, K24_PAL_60,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    }
+};
+/* Two-Dimensional Cascade Broadband and Narrowband (3.58/4.43) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wana_ntsc = {
+    {
+        (uint16_t)24u, (uint16_t)44u, (uint16_t)20u, (uint16_t)(0x1000u | 52u), (uint16_t)(0x1000u | 128u),
+        (uint16_t)(0x1000u | 128u), (uint16_t)(0x1000u | 12u), (uint16_t)132u, (uint16_t)200u
+    }
+};
+/* Two-Dimensional Cascade Broadband (SECAM-DR) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wa_secam = {
+    {
+        (uint16_t)(0x1000u | 20u), (uint16_t)24u, (uint16_t)64u, (uint16_t)40u, (uint16_t)(0x1000u | 76u),
+        (uint16_t)(0x1000u | 164u), (uint16_t)(0x1000u | 84u), (uint16_t)108u, (uint16_t)216u
+    }
+};
+/* Two-Dimensional Cascade Broadband (SECAM-DB) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wb_secam = {
+    {
+        (uint16_t)(0x1000u | 12u), (uint16_t)40u, (uint16_t)60u, (uint16_t)12u, (uint16_t)(0x1000u | 104u),
+        (uint16_t)(0x1000u | 156u), (uint16_t)(0x1000u | 64u), (uint16_t)120u, (uint16_t)208u
+    }
+};
+/* Two-Dimensional Cascade Narrowband (SECAM-DR) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t na_secam = {
+    {
+        (uint16_t)(0x1000u | 1008u), (uint16_t)1976u, (uint16_t)(0x1000u | 2024u), (uint16_t)444u, (uint16_t)1868u,
+        (uint16_t)(0x1000u | 2864u), (uint16_t)1352u, (uint16_t)1376u, (uint16_t)(0x1000u | 2240u)
+    }
+};
+/* Two-Dimensional Cascade Narrowband (SECAM-DB) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t nb_secam = {
+    {
+        (uint16_t)(0x1000u | 1080u), (uint16_t)2800u, (uint16_t)(0x1000u | 3308u), (uint16_t)1628u, (uint16_t)1444u,
+        (uint16_t)(0x1000u | 3308u), (uint16_t)2140u, (uint16_t)376u, (uint16_t)(0x1000u | 1384u)
+    }
+};
+
+
+/**************************************************************************//**
+ * @brief       Video decoder initialization
+ * @param       [in]adc_vinsel      : Input pin control
+ * @param       [in]channel         : Channel
+ * @retval      Detected color system
+ *****************************************************************************/
+vdec_error_t GRAPHICS_VideoDecoderInit (const vdec_adc_vinsel_t adc_vinsel, const vdec_channel_t channel, graphics_col_sys_t col_sys)
+{
+    vdec_error_t        error = VDEC_OK;
+
+    /* Video Decoder Driver Initialization */
+    error = R_VDEC_Initialize(channel, adc_vinsel, &init_func, (uint32_t)channel);
+    if (error == VDEC_OK) {
+        if (col_sys != GRPH_COL_SYS_UNKNOWN) {
+            /* Input */
+            Input(col_sys, channel);
+            /* Sync separation */
+            SyncSep(col_sys, channel);
+            /* Y/C separation */
+            YcSep(col_sys, channel);
+            /* Chroma decoding */
+            ChromaDec(col_sys, channel);
+            /* Digital clamp */
+            DigitalClamp(channel);
+            /* Output */
+            Output(channel);
+        } else {
+            error = VDEC_ERR_PARAM;
+        }
+    }
+    return error;
+}   /* End of function GRAPHICS_VideoDecoderInit() */
+
+
+/**************************************************************************//**
+ * @brief       User-defined function
+ * @param       [in]user_num
+ * @retval      None
+ *****************************************************************************/
+static void init_func (const uint32_t user_num)
+{
+    uint32_t            reg_data;
+    volatile uint8_t    dummy_read;
+
+    reg_data = (uint32_t)CPG.STBCR7;
+    if ((vdec_channel_t)user_num == VDEC_CHANNEL_0) {
+        /* Standby control register 7 (STBCR7)
+            b7      0-------;  MSTP77 : 0 : Video decoder channel 0 enable */
+        reg_data &= (uint32_t)~STBCR7_BIT7;
+    } else {
+        /* Standby control register 7 (STBCR7)
+            b6      -0------;  MSTP76 : 0 : Video decoder channel 1 enable */
+        reg_data &= (uint32_t)~STBCR7_BIT6;
+    }
+    CPG.STBCR7 = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR7;
+#if(1) /* mbed */
+    (void)dummy_read; /* unused */
+#endif
+}   /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief       Video decoder input setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void Input (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_active_period_t        param;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    param.srcleft   = RecommendValTbl->srcleft;     /* Left end of input video signal capturing area */
+    param.srctop    = RecommendValTbl->srctop;      /* Top end of input video signal capturing area */
+    param.srcheight = RecommendValTbl->srcheight;   /* Height of input video signal capturing area */
+    param.srcwidth  = RecommendValTbl->srcwidth;    /* Width of input video signal capturing area */
+    /* Video decoder driver input */
+    error = R_VDEC_ActivePeriod(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function Input() */
+
+/**************************************************************************//**
+ * @brief       Video decoder sync separation setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void SyncSep (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_sync_separation_t      param;
+    vdec_noise_rd_lpf_t         noise_rd_lpf_tmp;
+    vdec_sync_slicer_t          sync_slicer_tmp;
+    vdec_horizontal_afc_t       horizontal_afc_tmp;
+    vdec_vcount_down_t          vcount_down_tmp;
+    vdec_agc_t                  agc_tmp;
+    vdec_peak_limiter_t         peak_limiter_tmp;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    /* Noise reduction LPF */
+    noise_rd_lpf_tmp.lpfvsync   = VDEC_LPF_VSYNC_0_54;      /* LPF cutoff frequency before vertical sync separation */
+    noise_rd_lpf_tmp.lpfhsync   = VDEC_LPF_HSYNC_0_94;      /* LPF cutoff frequency before horizontal sync separation */
+    /* Sync slicer */
+    sync_slicer_tmp.velocityshift_h = VDEC_VELOCITY_SHIFT_4;    /* Reference level operation speed control for
+                                                                   composite sync separation (for Hsync signal) */
+    sync_slicer_tmp.slicermode_h    = VDEC_SLICE_MODE_AUTO_50;  /* Auto-slice level setting for composite sync
+                                                                   separator circuit (for Hsync signal) */
+    sync_slicer_tmp.slicermode_v    = VDEC_SLICE_MODE_AUTO_50;  /* Auto-slice level setting for composite sync
+                                                                   separation circuit (for Vsync signal) */
+    sync_slicer_tmp.syncmaxduty_h   = SYNCMAXDUTY_H_VALUE;      /* Max ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Hsync signal) */
+    sync_slicer_tmp.syncminduty_h   = SYNCMINDUTY_H_VALUE;      /* Min ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Hsync signal) */
+    sync_slicer_tmp.ssclipsel       = VDEC_CLIP_LV_1023;        /* Clipping level */
+    sync_slicer_tmp.csyncslice_h    = CSYNCSLICE_H_VALUE;       /* Slice level for composite sync
+                                                                   signal separation (for Hsync signal) */
+    sync_slicer_tmp.syncmaxduty_v   = SYNCMAXDUTY_V_VALUE;      /* Max ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Vsync signal) */
+    sync_slicer_tmp.syncminduty_v   = SYNCMINDUTY_V_VALUE;      /* Min ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Vsync signal) */
+    sync_slicer_tmp.vsyncdelay      = VDEC_OFF;                 /* Delays the separated vertical sync signal for
+                                                                   1/4 horizontal cycle */
+    sync_slicer_tmp.vsyncslice      = VSYNCSLICE_VALUE;         /* Threshold for vertical sync separation */
+    sync_slicer_tmp.csyncslice_v    = CSYNCSLICE_V_VALUE;       /* Slice level for composite sync
+                                                                   signal separation (for Vsync signal) */
+    /* Horizontal AFC */
+    horizontal_afc_tmp.hafcgain     = HAFCGAIN_VALUE;           /* Horizontal AFC loop gain */
+    horizontal_afc_tmp.hafctyp      = RecommendValTbl->hafctyp; /* Horizontal AFC center oscillation frequency */
+    horizontal_afc_tmp.hafcstart    = HAFCSTART_VALUE;          /* Start line of horizontal AFC normal operation */
+    horizontal_afc_tmp.nox2hosc     = VDEC_ON;                  /* Disable of horizontal AFC double speed detection */
+    horizontal_afc_tmp.hafcmax      = RecommendValTbl->hafcmax; /* Maximum oscillation frequency of horizontal AFC */
+    horizontal_afc_tmp.hafcend      = HAFCEND_VALUE;            /* End line of horizontal AFC normal operation */
+    horizontal_afc_tmp.hafcmode     = VDEC_HAFCMD_AUTO_PHST;    /* Horizontal AFC VBI period operating mode */
+    horizontal_afc_tmp.hafcmin      = RecommendValTbl->hafcmin; /* Min oscillation frequency of horizontal AFC */
+    horizontal_afc_tmp.phdet_fix    = VDEC_OFF;                 /* Forcible or LOWGAIN control */
+    horizontal_afc_tmp.phdet_div    = VDEC_PHDET_DIV_1_32;      /* Phase comparator feedback adjust for
+                                                                   low sync signal lock stability */
+    /* Vertical countdown */
+    vcount_down_tmp.novcd50_    = RecommendValTbl->novcd50_;    /* Vertical countdown 50-Hz oscillation mode */
+    vcount_down_tmp.novcd60_    = RecommendValTbl->novcd60_;    /* Vertical countdown 60-Hz (59.94-Hz)
+                                                                   oscillation mode */
+    vcount_down_tmp.vcddefault  = RecommendValTbl->vcddefault;  /* Vertical countdown center oscillation frequency */
+    vcount_down_tmp.vcdwindow   = RecommendValTbl->vcdwindow;   /* Vertical countdown sync area */
+    vcount_down_tmp.vcdoffset   = RecommendValTbl->vcdoffset;   /* Vertical countdown minimum oscillation frequency */
+    /* AGC / PGA */
+    agc_tmp.agcmode     = VDEC_ON;                  /* A/D converter AGC ON/OFF control & PGA gain select */
+    agc_tmp.doreduce    = VDEC_OFF;                 /* Manual control of sync signal amplitude detection
+                                                       during VBI period */
+    agc_tmp.noreduce_   = VDEC_ON;                  /* Control of sync signal amplitude detection during VBI period */
+    agc_tmp.agcresponse = AGCRESPONSE_VALUE;        /* AGC response speed */
+    agc_tmp.agclevel    = RecommendValTbl->agclevel;/* Sync signal reference amplitude */
+    agc_tmp.agcprecis   = AGCPRECIS_VALUE;          /* AGC gain adjustment accuracy */
+    agc_tmp.pga_gain    = PGA_GAIN_VALUE;           /* PGA gain */
+    /* Peak limiter control */
+    peak_limiter_tmp.peaklevel      = VDEC_PEAKLV_992;      /* Peak luminance value to operate peak limiter */
+    peak_limiter_tmp.peakattack     = PEAKATTACK_VALUE;     /* Response speed with peak limiter gain decreased */
+    peak_limiter_tmp.peakrelease    = PEAKRELEASE_VALUE;    /* Response speed with peak limiter gain increased */
+    peak_limiter_tmp.peakratio      = VDEC_PEAKRATIO_50;    /* Maximum compression rate of peak limiter */
+    peak_limiter_tmp.maxpeaksamples = MAXPEAKSAMPLES_VALUE; /* Allowable number of overflowing pixels */
+
+    param.noise_rd_lpf      = &noise_rd_lpf_tmp;    /* Noise reduction LPF */
+    param.sync_slicer       = &sync_slicer_tmp;     /* Sync slicer */
+    param.horizontal_afc    = &horizontal_afc_tmp;  /* Horizontal AFC */
+    param.vcount_down       = &vcount_down_tmp;     /* Vertical countdown */
+    param.agc               = &agc_tmp;             /* AGC / PGA */
+    param.peak_limiter      = &peak_limiter_tmp;    /* Peak limiter control */
+    /* Video decoder driver sync separation */
+    error = R_VDEC_SyncSeparation(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function SyncSep() */
+
+/**************************************************************************//**
+ * @brief       Video decoder Y/C separation setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void YcSep (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_yc_separation_t        param;
+    vdec_over_range_t           over_range_tmp;
+    vdec_yc_sep_ctrl_t          yc_sep_ctrl_tmp;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    /* Over-range control */
+    over_range_tmp.radj_o_level0    = RADJ_O_LEVEL0_VALUE;   /* A/D over-threshold level (between levels 0 and 1) */
+    over_range_tmp.radj_u_level0    = RADJ_U_LEVEL0_VALUE;   /* A/D under-threshold level (between levels 2 and 3) */
+    over_range_tmp.radj_o_level1    = RADJ_O_LEVEL1_VALUE;   /* A/D over-threshold level (between levels 1 and 2) */
+    over_range_tmp.radj_u_level1    = RADJ_U_LEVEL1_VALUE;   /* A/D under-threshold level (between levels 1 and 2) */
+    over_range_tmp.radj_o_level2    = RADJ_O_LEVEL2_VALUE;   /* A/D over-threshold level (between levels 2 and 3) */
+    over_range_tmp.radj_u_level2    = RADJ_U_LEVEL2_VALUE;   /* A/D under-threshold level (between levels 0 and 1) */
+    over_range_tmp.ucmp_sw          = VDEC_ON;          /* Over-range detection */
+    over_range_tmp.dcmp_sw          = VDEC_ON;          /* Under-range detection */
+    over_range_tmp.hwide_sw         = VDEC_ON;          /* Horizontal enlargement of over/under-range level */
+    /* Y/C separation control */
+    /* Two-dimensional Y/C separation filter select coefficient */
+    yc_sep_ctrl_tmp.k15             = RecommendValTbl->k15;         /* K15 */
+    yc_sep_ctrl_tmp.k13             = RecommendValTbl->k13;         /* K13 */
+    yc_sep_ctrl_tmp.k11             = RecommendValTbl->k11;         /* K11 */
+    yc_sep_ctrl_tmp.k16             = RecommendValTbl->k16;         /* K16 */
+    yc_sep_ctrl_tmp.k14             = RecommendValTbl->k14;         /* K14 */
+    yc_sep_ctrl_tmp.k12             = RecommendValTbl->k12;         /* K12 */
+    yc_sep_ctrl_tmp.k22a            = RecommendValTbl->k22A;        /* K22A */
+    yc_sep_ctrl_tmp.k21a            = RecommendValTbl->k21A;        /* K21A */
+    yc_sep_ctrl_tmp.k22b            = RecommendValTbl->k22B;        /* K22B */
+    yc_sep_ctrl_tmp.k21b            = RecommendValTbl->k21B;        /* K21B */
+    yc_sep_ctrl_tmp.k23b            = RecommendValTbl->k23B;        /* K23B */
+    yc_sep_ctrl_tmp.k23a            = RecommendValTbl->k23A;        /* K23A */
+    yc_sep_ctrl_tmp.k24             = RecommendValTbl->k24;         /* K24 */
+    yc_sep_ctrl_tmp.hbpf_narrow     = VDEC_LSTG_BPFSEL_BYPASS;      /* Latter-stage horizontal BPF select */
+    yc_sep_ctrl_tmp.hvbpf_narrow    = VDEC_LSTG_BPFSEL_BYPASS;      /* Latter-stage horizontal/vertical BPF select */
+    yc_sep_ctrl_tmp.hbpf1_9tap_on   = VDEC_FSTG_BPFSEL_17TAP;       /* Former-stage horizontal BPF select */
+    yc_sep_ctrl_tmp.hvbpf1_9tap_on  = VDEC_FSTG_BPFSEL_17TAP;       /* Former-stage horizontal/vertical BPF select */
+    yc_sep_ctrl_tmp.hfil_tap_sel    = VDEC_HFIL_TAP_SEL_17TAP;      /* Horizontal filter and horizontal/vertical filter
+                                                                       bandwidth switch signal */
+    yc_sep_ctrl_tmp.det2_on         = RecommendValTbl->det2_on;     /* Two-dimensional filter mixing select */
+    yc_sep_ctrl_tmp.hsel_mix_y      = RecommendValTbl->hsel_mix_y;  /* Mixing ratio of signal after passing
+                                                                       horizontal filter to signal after passing
+                                                                       former-stage horizontal filter */
+    yc_sep_ctrl_tmp.vsel_mix_y      = RecommendValTbl->vsel_mix_y;  /* Mixing ratio of signal after passing
+                                                                       vertical filter to signal after passing
+                                                                       former-stage horizontal/vertical filter */
+    yc_sep_ctrl_tmp.hvsel_mix_y     = RecommendValTbl->hvsel_mix_y; /* Mixing ratio of signal after passing
+                                                                       horizontal/vertical filter to signal
+                                                                       after passing former-stage
+                                                                       horizontal/vertical filter */
+    yc_sep_ctrl_tmp.v_y_level       = V_Y_LEVEL_VALUE;              /* Vertical luminance detection level
+                                                                       for correlation detection filter */
+    yc_sep_ctrl_tmp.det2_mix_c      = RecommendValTbl->det2_mix_c;  /* Mixing ratio of c signal after passing
+                                                                       horizontal/vertical adaptive filter
+                                                                       to signal after passing correlation detection
+                                                                       filter */
+    yc_sep_ctrl_tmp.det2_mix_y      = RecommendValTbl->det2_mix_y;  /* Mixing ratio of c signal for y generation after
+                                                                       passing horizontal/vertical adaptive filter to
+                                                                       signal after passing correlation */
+    yc_sep_ctrl_tmp.fil2_mode_2d    = RecommendValTbl->fil2_mode_2d;/* Two-dimensional cascade/TAKE-OFF
+                                                                       filter mode select */
+    yc_sep_ctrl_tmp.fil2_narrow_2d  = RecommendValTbl->fil2_narrow_2d;  /* Two-dimensional cascade filter select */
+
+    param.over_range    = &over_range_tmp;  /* Over-range control */
+    param.yc_sep_ctrl   = &yc_sep_ctrl_tmp; /* Y/C separation control */
+    param.fil2_2d_wa    = NULL;             /* Two-dimensional cascade broadband
+                                               (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+    param.fil2_2d_wb    = NULL;             /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+    param.fil2_2d_na    = NULL;             /* Two-dimensional cascade narrowband
+                                               (3.58/4.43/SECAM-DR) filter TAP coefficient */
+    param.fil2_2d_nb    = NULL;             /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+    if ((color_system == GRPH_COL_SYS_NTSC_358) ||
+            (color_system == GRPH_COL_SYS_NTSC_443) ||
+            (color_system == GRPH_COL_SYS_NTSC_443_60)) {
+        param.fil2_2d_wa = &wana_ntsc;
+        param.fil2_2d_na = &wana_ntsc;
+    } else if (color_system == GRPH_COL_SYS_SECAM) {
+        param.fil2_2d_wa = &wa_secam;
+        param.fil2_2d_wb = &wb_secam;
+        param.fil2_2d_na = &na_secam;
+        param.fil2_2d_nb = &nb_secam;
+    } else {
+        /* Do nothing */
+    }
+    /* Video decoder driver y/c separation */
+    error = R_VDEC_YcSeparation(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function YcSep() */
+
+/**************************************************************************//**
+ * @brief       Video decoder chroma decoding setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void ChromaDec (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_chroma_decoding_t      param;
+    vdec_chrmdec_ctrl_t         chrmdec_ctrl_tmp;
+    vdec_burst_lock_t           burst_lock_tmp;
+    vdec_acc_t                  acc_tmp;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    /* Chroma decoding control */
+    chrmdec_ctrl_tmp.defaultsys = RecommendValTbl->defaultsys;  /* Default color system */
+    chrmdec_ctrl_tmp.nontsc358_ = RecommendValTbl->nontsc358_;  /* NTSC-M detection control */
+    chrmdec_ctrl_tmp.nontsc443_ = RecommendValTbl->nontsc443_;  /* NTSC-4.43 detection control */
+    chrmdec_ctrl_tmp.nopalm_    = RecommendValTbl->nopalm_;     /* PAL-M detection control */
+    chrmdec_ctrl_tmp.nopaln_    = RecommendValTbl->nopaln_;     /* PAL-N detection control */
+    chrmdec_ctrl_tmp.nopal443_  = RecommendValTbl->nopal443_;   /* PAL-B, G, H, I, D detection control */
+    chrmdec_ctrl_tmp.nosecam_   = RecommendValTbl->nosecam_;    /* SECAM detection control */
+    chrmdec_ctrl_tmp.lumadelay  = LUMADELAY_VALUE;              /* Luminance signal delay adjustment */
+    chrmdec_ctrl_tmp.chromalpf  = VDEC_OFF;                     /* LPF for demodulated chroma */
+    chrmdec_ctrl_tmp.demodmode  = VDEC_DEMOD_MD_PAL;            /* Averaging processing for pre-demodulated line */
+    /* Burst lock */
+    burst_lock_tmp.lockrange    = VDEC_LOCK_RANGE_800HZ;/* Burst lock PLL lock range */
+    burst_lock_tmp.loopgain     = LOOPGAIN_VALUE;       /* Burst lock PLL loop gain */
+    burst_lock_tmp.locklimit    = LOCKLIMIT_VALUE;      /* Level for burst lock PLL to re-search free-run frequency */
+    burst_lock_tmp.bgpcheck     = BGPCHECK_VALUE;       /* burst gate pulse position check */
+    burst_lock_tmp.bgpwidth     = BGPWIDTH_VALUE;       /* burst gate pulse width */
+    burst_lock_tmp.bgpstart     = BGPSTART_VALUE;       /* burst gate pulse start position */
+    /* ACC / color killer */
+    acc_tmp.accmode         = VDEC_ACC_MD_AUTO;         /* ACC operating mode */
+    acc_tmp.accmaxgain      = VDEC_ACC_MAX_GAIN_6;      /* Maximum ACC Gain */
+    acc_tmp.acclevel        = RecommendValTbl->acclevel;/* ACC reference color burst amplitude */
+    acc_tmp.chromasubgain   = VDEC_CHRM_SB_GAIN_1;      /* Chroma manual gain (sub) */
+    acc_tmp.chromamaingain  = CHROMAMAINGAIN_VALUE;     /* Chroma manual gain (main) */
+    acc_tmp.accresponse     = ACCRESPONSE_VALUE;        /* ACC response speed */
+    acc_tmp.accprecis       = ACCPRECIS_VALUE;          /* ACC gain adjustment accuracy */
+    acc_tmp.killermode      = VDEC_OFF;                 /* Forced color killer mode ON/OFF */
+    acc_tmp.killerlevel     = KILLERLEVEL_VALUE;        /* Color killer operation start point */
+    acc_tmp.killeroffset    = KILLEROFFSET_VALUE;       /* The offset level to turn off the color killer */
+
+    param.chrmdec_ctrl  = &chrmdec_ctrl_tmp;    /* Chroma decoding control */
+    param.burst_lock    = &burst_lock_tmp;      /* Burst lock */
+    param.acc           = &acc_tmp;             /* ACC/color killer */
+    param.tint_ry       = NULL;                 /* TINT/R-Y axis correction (only valid for NTSC/PAL) */
+    /* Video decoder driver chroma decoding */
+    error = R_VDEC_ChromaDecoding(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function ChromaDec() */
+
+/**************************************************************************//**
+ * @brief       Video decoder digital clamp setup
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void DigitalClamp (const vdec_channel_t channel)
+{
+    vdec_error_t            error;
+    vdec_degital_clamp_t    param;
+    vdec_pedestal_clamp_t   pedestal_clamp_tmp;
+    vdec_center_clamp_t     center_clamp_tmp;
+    vdec_noise_det_t        noise_det_tmp;
+
+    /* Pedestal clamp */
+    pedestal_clamp_tmp.dcpmode_y    = VDEC_DCPMODE_AUTO;    /* Clamp level setting mode */
+    pedestal_clamp_tmp.blanklevel_y = BLANKLEVEL_Y_VALUE;   /* Clamp offset level (Y signal) */
+    pedestal_clamp_tmp.dcppos_y     = DCPPOS_Y_VALUE;   /* Digital clamp pulse horizontal start position (Y signal) */
+    /* Center clamp */
+    center_clamp_tmp.dcpmode_c      = VDEC_DCPMODE_MANUAL;  /* Clamp level setting mode */
+    center_clamp_tmp.blanklevel_cb  = BLANKLEVEL_CB_VALUE;  /* Clamp offset level (Cb signal) */
+    center_clamp_tmp.blanklevel_cr  = BLANKLEVEL_CR_VALUE;  /* Clamp offset level (Cr signal) */
+    center_clamp_tmp.dcppos_c       = DCPPOS_C_VALUE;       /* Digital clamp pulse
+                                                               horizontal start position (Cb/Cr signal) */
+    /* Noise detection */
+    noise_det_tmp.acfinput      = VDEC_ACFINPUT_Y;  /* Video signal for autocorrelation function */
+    noise_det_tmp.acflagtime    = ACFLAGTIME_VALUE; /* Delay time for autocorrelation function calculation */
+    noise_det_tmp.acffilter     = ACFFILTER_VALUE;  /* Smoothing parameter of autocorrelation function data */
+
+    param.dcpcheck          = VDEC_OFF;             /* Digital clamp pulse position check */
+    param.dcpresponse       = DCPRESPONSE_VALUE;    /* Digital clamp response speed */
+    param.dcpstart          = DCPSTART_VALUE;       /* Digital clamp start line (in 1-line units) */
+    param.dcpend            = DCPEND_VALUE;         /* Digital clamp end line (in 1-line units) */
+    param.dcpwidth          = DCPWIDTH_VALUE;       /* Digital clamp pulse width */
+    param.pedestal_clamp    = &pedestal_clamp_tmp;  /* Pedestal clamp */
+    param.center_clamp      = &center_clamp_tmp;    /* Center clamp */
+    param.noise_det         = &noise_det_tmp;       /* Noise detection */
+    /* Video decoder driver digital clamp */
+    error = R_VDEC_DigitalClamp(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief       Video decoder output adjustment setup
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void Output (const vdec_channel_t channel)
+{
+    vdec_error_t        error;
+    vdec_output_t       param;
+
+    param.y_gain2   = Y_GAIN2_VALUE;        /* Y signal gain coefficient */
+    param.cb_gain2  = CB_GAIN2_VALUE;       /* Cb signal gain coefficient */
+    param.cr_gain2  = CR_GAIN2_VALUE;       /* Cr signal gain coefficient */
+    /* Video decoder driver output */
+    error = R_VDEC_Output(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function Output() */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/include/r_vdc5.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1011 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5.h
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver API definitions
+******************************************************************************/
+
+#ifndef R_VDC5_H
+#define R_VDC5_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5_user.h"
+
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_GAM_GAIN_ADJ_NUM       (32u)   /*!< The number of the gamma correction gain coefficient */
+#define     VDC5_GAM_START_TH_NUM       (31u)   /*!< The number of the gamma correction start threshold */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDC5 driver */
+typedef enum
+{
+    VDC5_OK = 0,                /*!< Normal termination */
+    VDC5_ERR_PARAM_CHANNEL,     /*!< Invalid channel error (parameter error): An illegal channel is specified. */
+    VDC5_ERR_PARAM_LAYER_ID,    /*!< Invalid layer ID error (parameter error): An illegal layer ID is specified. */
+    VDC5_ERR_PARAM_NULL,        /*!< NULL specification error (parameter error):
+                                     NULL is specified for a required parameter. */
+    VDC5_ERR_PARAM_BIT_WIDTH,   /*!< Bit width error (parameter error):
+                                     A value exceeding the possible bit width is specified. */
+    VDC5_ERR_PARAM_UNDEFINED,   /*!< Undefined parameter error (parameter error):
+                                     A value that is not defined in the specification is specified. */
+    VDC5_ERR_PARAM_EXCEED_RANGE,/*!< Out-of-value-range error (parameter error):
+                                     The specified parameter value is beyond the value range defined
+                                     in the specification. */
+    VDC5_ERR_PARAM_CONDITION,   /*!< Unauthorized condition error (parameter error):
+                                     A parameter is specified under conditions that are not authorized
+                                     by the specification. */
+    VDC5_ERR_IF_CONDITION,      /*!< Interface condition error (interface error):
+                                     An API function is called under unauthorized conditions. */
+    VDC5_ERR_RESOURCE_CLK,      /*!< Clock resource error (resource error): No panel clock is set up. */
+    VDC5_ERR_RESOURCE_VSYNC,    /*!< Vsync signal resource error (resource error): No Vsync signal is set up. */
+    VDC5_ERR_RESOURCE_INPUT,    /*!< Input signal resource error (resource error): No video image input is set up. */
+    VDC5_ERR_RESOURCE_OUTPUT,   /*!< Output resource error (resource error): No display output is set up. */
+    VDC5_ERR_RESOURCE_LAYER,    /*!< Layer resource error (resource error):
+                                     The specified layer is under unavailable conditions. */
+    VDC5_ERR_NUM                /*!< The number of error codes */
+} vdc5_error_t;
+
+/*! VDC5 channels */
+typedef enum
+{
+    VDC5_CHANNEL_0 = 0,         /*!< Channel 0 */
+    VDC5_CHANNEL_NUM            /*!< The number of channels */
+} vdc5_channel_t;
+
+/*! On/off */
+typedef enum
+{
+    VDC5_OFF    = 0,            /*!< Off */
+    VDC5_ON     = 1             /*!< On */
+} vdc5_onoff_t;
+/*! Edge of a signal */
+typedef enum
+{
+    VDC5_EDGE_RISING    = 0,    /*!< Rising edge */
+    VDC5_EDGE_FALLING   = 1     /*!< Falling edge */
+} vdc5_edge_t;
+/*! Polarity of a signal */
+typedef enum
+{
+    VDC5_SIG_POL_NOT_INVERTED   = 0,    /*!< Not inverted */
+    VDC5_SIG_POL_INVERTED       = 1     /*!< Inverted */
+} vdc5_sig_pol_t;
+
+/*! Scaling type ID */
+typedef enum
+{
+    VDC5_SC_TYPE_SC0 = 0,               /*!< Scaler 0 */
+    VDC5_SC_TYPE_NUM                    /*!< The number of scaler types */
+} vdc5_scaling_type_t;
+/*! Graphics type ID */
+typedef enum
+{
+    VDC5_GR_TYPE_GR0 = 0,               /*!< Graphics 0 */
+    VDC5_GR_TYPE_GR2,                   /*!< Graphics 2 */
+    VDC5_GR_TYPE_GR3,                   /*!< Graphics 3 */
+    VDC5_GR_TYPE_NUM                    /*!< The number of graphics types */
+} vdc5_graphics_type_t;
+/*! Layer ID */
+typedef enum
+{
+    VDC5_LAYER_ID_ALL       = -1,                                       /*!< All layers */
+    VDC5_LAYER_ID_0_WR      = (VDC5_SC_TYPE_SC0 + 0),                   /*!< Write process for layer 0 */
+    VDC5_LAYER_ID_0_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR0),    /*!< Read process for layer 0 */
+    VDC5_LAYER_ID_2_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR2),    /*!< Read process for layer 2 */
+    VDC5_LAYER_ID_3_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR3),    /*!< Read process for layer 3 */
+    VDC5_LAYER_ID_NUM       = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_NUM)     /*!< The number of layer IDs */
+} vdc5_layer_id_t;
+/*! The horizontal/vertical timing of the VDC5 signals */
+typedef struct
+{
+    uint16_t    vs;                 /*!< Vertical signal start position from the reference signal */
+    uint16_t    vw;                 /*!< Vertical signal width (height) */
+    uint16_t    hs;                 /*!< Horizontal signal start position from the reference signal */
+    uint16_t    hw;                 /*!< Horizontal signal width */
+} vdc5_period_rect_t;
+/*! The relative position within the graphics display area */
+typedef struct
+{
+    uint16_t   vs_rel;              /*!< Vertical start position */
+    uint16_t   vw_rel;              /*!< Vertical width (height) */
+    uint16_t   hs_rel;              /*!< Horizontal start position */
+    uint16_t   hw_rel;              /*!< Horizontal width */
+} vdc5_pd_disp_rect_t;
+
+/***********************    For R_VDC5_Initialize       ***********************/
+/*! Panel clock select */
+typedef enum
+{
+    VDC5_PANEL_ICKSEL_IMG_DV = 0,   /*!< Divided video image clock (DV_CLK) */
+    VDC5_PANEL_ICKSEL_EXT_0,        /*!< Divided external clock (LCD0_EXTCLK) */
+    VDC5_PANEL_ICKSEL_PERI,         /*!< Divided peripheral clock 1 */
+    VDC5_PANEL_ICKSEL_NUM           /*!< The number of panel clock select settings */
+} vdc5_panel_clksel_t;
+/*! Clock frequency division ratio */
+typedef enum
+{
+    VDC5_PANEL_CLKDIV_1_1 = 0,      /*!< Division Ratio 1/1 */
+    VDC5_PANEL_CLKDIV_1_2,          /*!< Division Ratio 1/2 */
+    VDC5_PANEL_CLKDIV_1_3,          /*!< Division Ratio 1/3 */
+    VDC5_PANEL_CLKDIV_1_4,          /*!< Division Ratio 1/4 */
+    VDC5_PANEL_CLKDIV_1_5,          /*!< Division Ratio 1/5 */
+    VDC5_PANEL_CLKDIV_1_6,          /*!< Division Ratio 1/6 */
+    VDC5_PANEL_CLKDIV_1_7,          /*!< Division Ratio 1/7 */
+    VDC5_PANEL_CLKDIV_1_8,          /*!< Division Ratio 1/8 */
+    VDC5_PANEL_CLKDIV_1_9,          /*!< Division Ratio 1/9 */
+    VDC5_PANEL_CLKDIV_1_12,         /*!< Division Ratio 1/12 */
+    VDC5_PANEL_CLKDIV_1_16,         /*!< Division Ratio 1/16 */
+    VDC5_PANEL_CLKDIV_1_24,         /*!< Division Ratio 1/24 */
+    VDC5_PANEL_CLKDIV_1_32,         /*!< Division Ratio 1/32 */
+    VDC5_PANEL_CLKDIV_NUM           /*!< The number of division ratio settings */
+} vdc5_panel_clk_dcdr_t;
+/*! The clock input to frequency divider 1 */
+typedef enum
+{
+    VDC5_LVDS_INCLK_SEL_IMG = 0,    /*!< Video image clock (VIDEO_X1) */
+    VDC5_LVDS_INCLK_SEL_DV_0,       /*!< Video image clock (DV0_CLK) */
+    VDC5_LVDS_INCLK_SEL_DV_1,       /*!< Video image clock (DV1_CLK) */
+    VDC5_LVDS_INCLK_SEL_EXT_0,      /*!< External clock (LCD0_EXTCLK) */
+    VDC5_LVDS_INCLK_SEL_EXT_1,      /*!< External clock (LCD1_EXTCLK) */
+    VDC5_LVDS_INCLK_SEL_PERI,       /*!< Peripheral clock 1 */
+    VDC5_LVDS_INCLK_SEL_NUM
+} vdc5_lvds_in_clk_sel_t;
+/*! The frequency dividing value (NIDIV or NODIV) */
+typedef enum
+{
+    VDC5_LVDS_NDIV_1 = 0,           /*!< Div 1 */
+    VDC5_LVDS_NDIV_2,               /*!< Div 2 */
+    VDC5_LVDS_NDIV_4,               /*!< Div 4 */
+    VDC5_LVDS_NDIV_NUM
+} vdc5_lvds_ndiv_t;
+/*! The frequency dividing value (NOD) for the output frequency */
+typedef enum
+{
+    VDC5_LVDS_PLL_NOD_1 = 0,        /*!< Div 1 */
+    VDC5_LVDS_PLL_NOD_2,            /*!< Div 2 */
+    VDC5_LVDS_PLL_NOD_4,            /*!< Div 4 */
+    VDC5_LVDS_PLL_NOD_8,            /*!< Div 8 */
+    VDC5_LVDS_PLL_NOD_NUM
+} vdc5_lvds_pll_nod_t;
+/*! LVDS parameter */
+typedef struct
+{
+    vdc5_lvds_in_clk_sel_t  lvds_in_clk_sel;/*!< The clock input to frequency divider 1 */
+    vdc5_lvds_ndiv_t        lvds_idiv_set;  /*!< The frequency dividing value (NIDIV) for frequency divider 1 */
+    uint16_t                lvdspll_tst;    /*!< Internal parameter setting for LVDS PLL */
+    vdc5_lvds_ndiv_t        lvds_odiv_set;  /*!< The frequency dividing value (NODIV) for frequency divider 2 */
+    vdc5_channel_t          lvds_vdc_sel;   /*!< A channel in VDC5 whose data is to be output through the LVDS */
+    uint16_t                lvdspll_fd;     /*!< The frequency dividing value (NFD) for the feedback frequency */
+    uint16_t                lvdspll_rd;     /*!< The frequency dividing value (NRD) for the input frequency */
+    vdc5_lvds_pll_nod_t     lvdspll_od;     /*!< The frequency dividing value (NOD) for the output frequency */
+} vdc5_lvds_t;
+/*! Initialization parameter */
+typedef struct
+{
+    vdc5_panel_clksel_t     panel_icksel;   /*!< Panel clock select */
+    vdc5_panel_clk_dcdr_t   panel_dcdr;     /*!< Clock frequency division ratio */
+    const vdc5_lvds_t     * lvds;           /*!< LVDS-related parameter */
+} vdc5_init_t;
+
+/***********************    For R_VDC5_VideoInput       ***********************/
+/*! Input select */
+typedef enum
+{
+    VDC5_INPUT_SEL_EXT      = 1     /*!< Signals supplied via the external input pins */
+} vdc5_input_sel_t;
+/*! Sync signal delay adjustment parameter */
+typedef struct
+{
+    uint16_t    inp_vs_dly_l;       /*!< Number of lines for delaying Vsync signal and field differentiation signal */
+    uint16_t    inp_fld_dly;        /*!< Field differentiation signal delay amount */
+    uint16_t    inp_vs_dly;         /*!< Vsync signal delay amount */
+    uint16_t    inp_hs_dly;         /*!< Hsync signal delay amount */
+} vdc5_sync_delay_t;
+/*! External input format select */
+typedef enum
+{
+    VDC5_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 */
+    VDC5_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+    VDC5_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+    VDC5_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+    VDC5_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+    VDC5_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+    VDC5_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 */
+    VDC5_EXTIN_FORMAT_NUM
+} vdc5_extin_format_t;
+/*! Reference select for external input BT.656 Hsync signal */
+typedef enum
+{
+    VDC5_EXTIN_REF_H_EAV    = 0,    /*!< EAV */
+    VDC5_EXTIN_REF_H_SAV    = 1     /*!< SAV */
+} vdc5_extin_ref_hsync_t;
+/*! Number of lines for BT.656 external input */
+typedef enum
+{
+    VDC5_EXTIN_LINE_525     = 0,    /*!< 525 lines */
+    VDC5_EXTIN_LINE_625     = 1     /*!< 625 lines */
+} vdc5_extin_input_line_t;
+/*! Y/Cb/Y/Cr data string start timing */
+typedef enum
+{
+    VDC5_EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+    VDC5_EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+    VDC5_EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+    VDC5_EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+    VDC5_EXTIN_H_POS_NUM
+} vdc5_extin_h_pos_t;
+/*! External input signal parameter */
+typedef struct
+{
+    vdc5_extin_format_t     inp_format;     /*!< External input format select */
+    vdc5_edge_t             inp_pxd_edge;   /*!< Clock edge select for capturing external input video image signals */
+    vdc5_edge_t             inp_vs_edge;    /*!< Clock edge select for capturing external input Vsync signals */
+    vdc5_edge_t             inp_hs_edge;    /*!< Clock edge select for capturing external input Hsync signals */
+    vdc5_onoff_t            inp_endian_on;  /*!< External input bit endian change on/off control */
+    vdc5_onoff_t            inp_swap_on;    /*!< External input B/R signal swap on/off control */
+    vdc5_sig_pol_t          inp_vs_inv;     /*!< External input Vsync signal DV_VSYNC inversion control */
+    vdc5_sig_pol_t          inp_hs_inv;     /*!< External input Hsync signal DV_HSYNC inversion control */
+    vdc5_extin_ref_hsync_t  inp_h_edge_sel; /*!< Reference select for external input BT.656 Hsync signal */
+    vdc5_extin_input_line_t inp_f525_625;   /*!< Number of lines for BT.656 external input */
+    vdc5_extin_h_pos_t      inp_h_pos;      /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+} vdc5_ext_in_sig_t;
+/*! Video input setup parameter */
+typedef struct
+{
+    vdc5_input_sel_t            inp_sel;    /*!< Input select */
+    uint16_t                    inp_fh50;   /*!< Vsync signal 1/2fH phase timing */
+    uint16_t                    inp_fh25;   /*!< Vsync signal 1/4fH phase timing */
+    const vdc5_sync_delay_t   * dly;        /*!< Sync signal delay adjustment parameter */
+    const vdc5_ext_in_sig_t   * ext_sig;    /*!< External input signal parameter */
+} vdc5_input_t;
+
+/***********************    For R_VDC5_SyncControl      ***********************/
+/*! Horizontal/vertical sync signal output and full-screen enable signal select */
+typedef enum
+{
+    VDC5_RES_VS_IN_SEL_SC0  = 0     /*!< Sync signal output and full-screen enable signal from scaler 0 */
+} vdc5_res_vs_in_sel_t;
+/*! Vsync signal compensation parameter */
+typedef struct
+{
+    uint16_t        res_vmask;              /*!< Repeated Vsync signal masking period */
+    uint16_t        res_vlack;              /*!< Missing-Sync compensating pulse output wait time */
+} vdc5_vsync_cpmpe_t;
+/*! Synchronization control parameter */
+typedef struct
+{
+    vdc5_onoff_t                res_vs_sel;     /*!< Vsync signal output select (free-running Vsync on/off control) */
+    vdc5_res_vs_in_sel_t        res_vs_in_sel;  /*!< Horizontal/vertical sync signal output
+                                                     and full-screen enable signal select */
+    uint16_t                    res_fv;         /*!< Free-running Vsync period setting */
+    uint16_t                    res_fh;         /*!< Hsync period setting */
+    uint16_t                    res_vsdly;      /*!< Vsync signal delay control */
+    vdc5_period_rect_t          res_f;          /*!< Full-screen enable signal */
+    const vdc5_vsync_cpmpe_t  * vsync_cpmpe;    /*!< Vsync signal compensation parameter */
+} vdc5_sync_ctrl_t;
+
+/***********************    For R_VDC5_DisplayOutput    ***********************/
+/*! POLA/POLB signal generation mode select */
+typedef enum
+{
+    VDC5_LCD_TCON_POLMD_NORMAL = 0,         /*!< Normal mode */
+    VDC5_LCD_TCON_POLMD_1X1REV,             /*!< 1x1 reverse mode */
+    VDC5_LCD_TCON_POLMD_1X2REV,             /*!< 1x2 reverse mode */
+    VDC5_LCD_TCON_POLMD_2X2REV,             /*!< 2x2 reverse mode */
+    VDC5_LCD_TCON_POLMD_NUM
+} vdc5_lcd_tcon_polmode_t;
+/*! Signal operating reference select */
+typedef enum
+{
+    VDC5_LCD_TCON_REFSEL_HSYNC      = 0,    /*!< Hsync signal reference */
+    VDC5_LCD_TCON_REFSEL_OFFSET_H   = 1     /*!< Offset Hsync signal reference */
+} vdc5_lcd_tcon_refsel_t;
+/*! LCD TCON output pin select */
+typedef enum
+{
+    VDC5_LCD_TCON_PIN_NON = -1,             /*!< Nothing output */
+    VDC5_LCD_TCON_PIN_0,                    /*!< LCD_TCON0 */
+    VDC5_LCD_TCON_PIN_1,                    /*!< LCD_TCON1 */
+    VDC5_LCD_TCON_PIN_2,                    /*!< LCD_TCON2 */
+    VDC5_LCD_TCON_PIN_3,                    /*!< LCD_TCON3 */
+    VDC5_LCD_TCON_PIN_4,                    /*!< LCD_TCON4 */
+    VDC5_LCD_TCON_PIN_5,                    /*!< LCD_TCON5 */
+    VDC5_LCD_TCON_PIN_6,                    /*!< LCD_TCON6 */
+    VDC5_LCD_TCON_PIN_NUM
+} vdc5_lcd_tcon_pin_t;
+/*! LCD TCON timing signal parameter */
+typedef struct
+{
+    uint16_t                tcon_hsvs;      /*!< Signal pulse start position */
+    uint16_t                tcon_hwvw;      /*!< Pulse width */
+    vdc5_lcd_tcon_polmode_t tcon_md;        /*!< POLA/POLB signal generation mode select */
+    vdc5_lcd_tcon_refsel_t  tcon_hs_sel;    /*!< Signal operating reference select */
+    vdc5_sig_pol_t          tcon_inv;       /*!< Polarity inversion control of signal */
+    vdc5_lcd_tcon_pin_t     tcon_pin;       /*!< LCD TCON output pin select */
+    vdc5_edge_t             outcnt_edge;    /*!< Output phase control of signal */
+} vdc5_lcd_tcon_timing_t;
+/*! Timing signals for driving the LCD panel */
+typedef enum
+{
+    VDC5_LCD_TCONSIG_STVA_VS = 0,           /*!< STVA/VS */
+    VDC5_LCD_TCONSIG_STVB_VE,               /*!< STVB/VE */
+    VDC5_LCD_TCONSIG_STH_SP_HS,             /*!< STH/SP/HS */
+    VDC5_LCD_TCONSIG_STB_LP_HE,             /*!< STB/LP/HE */
+    VDC5_LCD_TCONSIG_CPV_GCK,               /*!< CPV/GCK */
+    VDC5_LCD_TCONSIG_POLA,                  /*!< POLA */
+    VDC5_LCD_TCONSIG_POLB,                  /*!< POLB */
+    VDC5_LCD_TCONSIG_DE,                    /*!< DE */
+    VDC5_LCD_TCONSIG_NUM
+} vdc5_lcd_tcon_sigsel_t;
+/*! Output format select */
+typedef enum
+{
+    VDC5_LCD_OUTFORMAT_RGB888 = 0,          /*!< RGB888 */
+    VDC5_LCD_OUTFORMAT_RGB666,              /*!< RGB666 */
+    VDC5_LCD_OUTFORMAT_RGB565,              /*!< RGB565 */
+    VDC5_LCD_OUTFORMAT_SERIAL_RGB,          /*!< Serial RGB */
+    VDC5_LCD_OUTFORMAT_NUM
+} vdc5_lcd_outformat_t;
+/*! Clock frequency control */
+typedef enum
+{
+    VDC5_LCD_PARALLEL_CLKFRQ_1 = 0,         /*!< 100% speed (parallel RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_3,               /*!< Triple speed (serial RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_4,               /*!< Quadruple speed (serial RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_NUM
+} vdc5_lcd_clkfreqsel_t;
+/*! Scan direction select */
+typedef enum
+{
+    VDC5_LCD_SERIAL_SCAN_FORWARD   = 0,     /*!< Forward scan */
+    VDC5_LCD_SERIAL_SCAN_REVERSE   = 1      /*!< Reverse scan */
+} vdc5_lcd_scan_t;
+/*! Clock phase adjustment for serial RGB output */
+typedef enum
+{
+    VDC5_LCD_SERIAL_CLKPHASE_0 = 0,         /*!< 0[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_1,             /*!< 1[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_2,             /*!< 2[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_3,             /*!< 3[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_NUM
+} vdc5_lcd_clkphase_t;
+/*! Display output configuration parameter */
+typedef struct
+{
+    uint16_t                        tcon_half;                      /*!< 1/2fH timing */
+    uint16_t                        tcon_offset;                    /*!< Offset Hsync signal timing */
+    const vdc5_lcd_tcon_timing_t  * outctrl[VDC5_LCD_TCONSIG_NUM];  /*!< LCD TCON timing signal parameter */
+    vdc5_edge_t                     outcnt_lcd_edge;                /*!< Output phase control of LCD_DATA23
+                                                                         to LCD_DATA0 pin */
+    vdc5_onoff_t                    out_endian_on;                  /*!< Bit endian change on/off control */
+    vdc5_onoff_t                    out_swap_on;                    /*!< B/R signal swap on/off control */
+    vdc5_lcd_outformat_t            out_format;                     /*!< Output format select */
+    vdc5_lcd_clkfreqsel_t           out_frq_sel;                    /*!< Clock frequency control */
+    vdc5_lcd_scan_t                 out_dir_sel;                    /*!< Scan direction select */
+    vdc5_lcd_clkphase_t             out_phase;                      /*!< Clock phase adjustment
+                                                                         for serial RGB output */
+    uint32_t                        bg_color;                       /*!< Background color in 24-bit RGB color format */
+} vdc5_output_t;
+
+/***********************    For R_VDC5_CallbackISR      ***********************/
+/*! VDC5 interrupt type */
+typedef enum
+{
+    VDC5_INT_TYPE_S0_VI_VSYNC = 0,      /*!< Vsync signal input to scaler 0 */
+    VDC5_INT_TYPE_S0_LO_VSYNC,          /*!< Vsync signal output from scaler 0 */
+    VDC5_INT_TYPE_S0_VSYNCERR,          /*!< Missing Vsync signal for scaler 0 */
+    VDC5_INT_TYPE_VLINE,                /*!< Specified line signal for panel output in graphics 3 */
+    VDC5_INT_TYPE_S0_VFIELD,            /*!< Field end signal for recording function in scaler 0 */
+    VDC5_INT_TYPE_IV1_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 0 */
+    VDC5_INT_TYPE_IV3_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 0 */
+    VDC5_INT_TYPE_IV5_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 2 */
+    VDC5_INT_TYPE_IV6_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 3 */
+    VDC5_INT_TYPE_S0_WLINE,             /*!< Write specification line signal input to scaling-down control block
+                                            in scaler 0 */
+    VDC5_INT_TYPE_NUM                   /*!< The number of VDC5 interrupt types */
+} vdc5_int_type_t;
+/*! Interrupt callback setup parameter */
+typedef struct
+{
+    vdc5_int_type_t     type;                       /*!< VDC5 interrupt type */
+    void             (* callback)(vdc5_int_type_t); /*!< Interrupt callback function pointer */
+    uint16_t            line_num;                   /*!< Line interrupt set */
+} vdc5_int_t;
+
+/***********************    For R_VDC5_WriteDataControl ***********************/
+/*! Frame buffer writing mode for image processing */
+typedef enum
+{
+    VDC5_WR_MD_NORMAL = 0,                  /*!< Normal */
+    VDC5_WR_MD_MIRROR,                      /*!< Horizontal mirroring */
+    VDC5_WR_MD_ROT_90DEG,                   /*!< 90 degree rotation */
+    VDC5_WR_MD_ROT_180DEG,                  /*!< 180 degree rotation */
+    VDC5_WR_MD_ROT_270DEG,                  /*!< 270 degree rotation */
+    VDC5_WR_MD_NUM
+} vdc5_wr_md_t;
+/*! Scaling-down and rotation parameter */
+typedef struct
+{
+    vdc5_period_rect_t  res;                /*!< Image area to be captured */
+    vdc5_onoff_t        res_pfil_sel;       /*!< Prefilter mode select for brightness signals (on/off) */
+    uint16_t            res_out_vw;         /*!< Number of valid lines in vertical direction
+                                                 output by scaling-down control block */
+    uint16_t            res_out_hw;         /*!< Number of valid horizontal pixels
+                                                 output by scaling-down control block */
+    vdc5_onoff_t        adj_sel;            /*!< Handling for lack of last-input line (on/off) */
+    vdc5_wr_md_t        res_ds_wr_md;       /*!< Frame buffer writing mode for image processing */
+} vdc5_scalingdown_rot_t;
+/*! Frame buffer swap setting */
+typedef enum
+{
+    VDC5_WR_RD_WRSWA_NON = 0,           /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+    VDC5_WR_RD_WRSWA_8BIT,              /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+    VDC5_WR_RD_WRSWA_16BIT,             /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+    VDC5_WR_RD_WRSWA_16_8BIT,           /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+    VDC5_WR_RD_WRSWA_32BIT,             /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+    VDC5_WR_RD_WRSWA_32_8BIT,           /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+    VDC5_WR_RD_WRSWA_32_16BIT,          /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+    VDC5_WR_RD_WRSWA_32_16_8BIT,        /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    VDC5_WR_RD_WRSWA_NUM
+} vdc5_wr_rd_swa_t;
+/*! Frame buffer video-signal writing format */
+typedef enum
+{
+    VDC5_RES_MD_YCBCR422 = 0,               /*!< YCbCr422 */
+    VDC5_RES_MD_RGB565,                     /*!< RGB565 */
+    VDC5_RES_MD_RGB888,                     /*!< RGB888 */
+    VDC5_RES_MD_YCBCR444,                   /*!< YCbCr444 */
+    VDC5_RES_MD_NUM
+} vdc5_res_md_t;
+/*! Transfer burst length */
+typedef enum
+{
+    VDC5_BST_MD_32BYTE = 0,                 /*!< 32-byte transfer (4 bursts) */
+    VDC5_BST_MD_128BYTE                     /*!< 128-byte transfer (16 bursts) */
+} vdc5_bst_md_t;
+/*! Field operating mode select */
+typedef enum
+{
+    VDC5_RES_INTER_PROGRESSIVE  = 0,        /*!< Progressive */
+    VDC5_RES_INTER_INTERLACE    = 1         /*!< Interlace */
+} vdc5_res_inter_t;
+/*! Writing rate */
+typedef enum
+{
+    VDC5_RES_FS_RATE_PER1 = 0,              /* 1/1 an input signal */
+    VDC5_RES_FS_RATE_PER2,                  /* 1/2 an input signal */
+    VDC5_RES_FS_RATE_PER4,                  /* 1/4 an input signal */
+    VDC5_RES_FS_RATE_PER8,                  /* 1/8 an input signal */
+    VDC5_RES_FS_RATE_NUM
+} vdc5_res_fs_rate_t;
+/*! Write field select */
+typedef enum
+{
+    VDC5_RES_FLD_SEL_TOP    = 0,            /*!< Top field */
+    VDC5_RES_FLD_SEL_BOTTOM = 1             /*!< Bottom field */
+} vdc5_res_fld_sel_t;
+/*! Data write control parameter */
+typedef struct
+{
+    vdc5_scalingdown_rot_t  scalingdown_rot;/*!< Scaling-down and rotation parameter */
+    vdc5_wr_rd_swa_t        res_wrswa;      /*!< Swap setting in frame buffer writing */
+    vdc5_res_md_t           res_md;         /*!< Frame buffer video-signal writing format */
+    vdc5_bst_md_t           res_bst_md;     /*!< Transfer burst length for frame buffer writing */
+    vdc5_res_inter_t        res_inter;      /*!< Field operating mode select */
+    vdc5_res_fs_rate_t      res_fs_rate;    /*!< Writing rate */
+    vdc5_res_fld_sel_t      res_fld_sel;    /*!< Write field select */
+    vdc5_onoff_t            res_dth_on;     /*!< Dither correction on/off */
+    void                  * base;           /*!< Frame buffer base address */
+    uint32_t                ln_off;         /*!< Frame buffer line offset address [byte] */
+    uint32_t                flm_num;        /*!< Number of frames of buffer to be written to (res_flm_num + 1) */
+    uint32_t                flm_off;        /*!< Frame buffer frame offset address [byte] */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+} vdc5_write_t;
+
+/***********************  For R_VDC5_ChangeWriteProcess ***********************/
+/*! Data write change parameter */
+typedef struct
+{
+    vdc5_scalingdown_rot_t  scalingdown_rot;/*!< Scaling-down and rotation parameter */
+} vdc5_write_chg_t;
+
+/***********************  For R_VDC5_ReadDataControl    ***********************/
+/*! Line offset address direction of the frame buffer */
+typedef enum
+{
+    VDC5_GR_LN_OFF_DIR_INC = 0,             /*!< Increments the address by the line offset address */
+    VDC5_GR_LN_OFF_DIR_DEC                  /*!< Decrements the address by the line offset address */
+} vdc5_gr_ln_off_dir_t;
+/*! Frame buffer address setting signal */
+typedef enum
+{
+    VDC5_GR_FLM_SEL_SCALE_DOWN      = 0,        /*!< Links to scaling-down process */
+    VDC5_GR_FLM_SEL_FLM_NUM         = 1,        /*!< Selects frame 0 (graphics display) */
+    VDC5_GR_FLM_SEL_POINTER_BUFF    = 3         /*!< Links to pointer buffer */
+} vdc5_gr_flm_sel_t;
+/*! Size of the frame buffer to be read */
+typedef struct
+{
+    uint16_t                in_vw;          /*!< Number of lines in a frame */
+    uint16_t                in_hw;          /*!< Width of the horizontal valid period */
+} vdc5_width_read_fb_t;
+/*! Format of the frame buffer read signal */
+typedef enum
+{
+    VDC5_GR_FORMAT_RGB565 = 0,              /*!< RGB565 */
+    VDC5_GR_FORMAT_RGB888,                  /*!< RGB888 */
+    VDC5_GR_FORMAT_ARGB1555,                /*!< ARGB1555 */
+    VDC5_GR_FORMAT_ARGB4444,                /*!< ARGB4444 */
+    VDC5_GR_FORMAT_ARGB8888,                /*!< ARGB8888 */
+    VDC5_GR_FORMAT_CLUT8,                   /*!< CLUT8 */
+    VDC5_GR_FORMAT_CLUT4,                   /*!< CLUT4 */
+    VDC5_GR_FORMAT_CLUT1,                   /*!< CLUT1 */
+    VDC5_GR_FORMAT_YCBCR422,                /*!< YCbCr422: This setting is prohibited for the graphics 2 and 3 */
+    VDC5_GR_FORMAT_YCBCR444,                /*!< YCbCr444: This setting is prohibited for the graphics 2 and 3 */
+    VDC5_GR_FORMAT_RGBA5551,                /*!< RGBA5551 */
+    VDC5_GR_FORMAT_RGBA8888,                /*!< RGBA8888 */
+    VDC5_GR_FORMAT_NUM                      /*!< The number of signal formats */
+} vdc5_gr_format_t;
+/*! Swapping of data read from buffer in the YCbCr422 format */
+typedef enum
+{
+    VDC5_GR_YCCSWAP_CBY0CRY1 = 0,
+    VDC5_GR_YCCSWAP_Y0CBY1CR,
+    VDC5_GR_YCCSWAP_CRY0CBY1,
+    VDC5_GR_YCCSWAP_Y0CRY1CB,
+    VDC5_GR_YCCSWAP_Y1CRY0CB,
+    VDC5_GR_YCCSWAP_CRY1CBY0,
+    VDC5_GR_YCCSWAP_Y1CBY0CR,
+    VDC5_GR_YCCSWAP_CBY1CRY0,
+    VDC5_GR_YCCSWAP_NUM
+} vdc5_gr_ycc_swap_t;
+/*! Data read control parameter */
+typedef struct
+{
+    vdc5_gr_ln_off_dir_t            gr_ln_off_dir;  /*!< Line offset address direction of the frame buffer */
+    vdc5_gr_flm_sel_t               gr_flm_sel;     /*!< Frame buffer address setting signal */
+    vdc5_onoff_t                    gr_imr_flm_inv; /*!< Frame buffer number for distortion correction */
+    vdc5_bst_md_t                   gr_bst_md;      /*!< Frame buffer burst transfer mode */
+    void                          * gr_base;        /*!< Frame buffer base address */
+    uint32_t                        gr_ln_off;      /*!< Frame buffer line offset address */
+    const vdc5_width_read_fb_t    * width_read_fb;  /*!< Size of the frame buffer to be read */
+    vdc5_onoff_t                    adj_sel;        /*!< Folding handling (on/off) */
+    vdc5_gr_format_t                gr_format;      /*!< Format of the frame buffer read signal */
+    vdc5_gr_ycc_swap_t              gr_ycc_swap;    /*!< Swapping of data read from buffer
+                                                         in the YCbCr422 format */
+    vdc5_wr_rd_swa_t                gr_rdswa;       /*!< Swap setting in frame buffer reading */
+    vdc5_period_rect_t              gr_grc;         /*!< Graphics display area */
+} vdc5_read_t;
+
+/******************************* For R_VDC5_ChangeReadProcess       *******************************/
+/*! The type of graphics display modes */
+typedef enum
+{
+    VDC5_DISPSEL_IGNORED    = -1,       /*!< Ignored */
+    VDC5_DISPSEL_BACK       = 0,        /*!< Background color display */
+    VDC5_DISPSEL_LOWER      = 1,        /*!< Lower-layer graphics display */
+    VDC5_DISPSEL_CURRENT    = 2,        /*!< Current graphics display */
+    VDC5_DISPSEL_BLEND      = 3,        /*!< Blended display of lower-layer graphics and current graphics */
+    VDC5_DISPSEL_NUM        = 4         /*!< The number of graphics display modes */
+} vdc5_gr_disp_sel_t;
+/*! Data read change parameter */
+typedef struct
+{
+    void                          * gr_base;        /*!< Frame buffer base address */
+    const vdc5_width_read_fb_t    * width_read_fb;  /*!< Size of the frame buffer to be read */
+    const vdc5_period_rect_t      * gr_grc;         /*!< Graphics display area */
+    const vdc5_gr_disp_sel_t      * gr_disp_sel;    /*!< Graphics display mode */
+} vdc5_read_chg_t;
+
+/******************************* For R_VDC5_StartProcess            *******************************/
+/*! Data write/read start parameter */
+typedef struct
+{
+    const vdc5_gr_disp_sel_t      * gr_disp_sel;    /*!< Graphics display mode */
+} vdc5_start_t;
+
+/******************************* For R_VDC5_VideoNoiseReduction     *******************************/
+/*! TAP select */
+typedef enum
+{
+    VDC5_NR_TAPSEL_1 = 0,           /*!< Adjacent pixel */
+    VDC5_NR_TAPSEL_2,               /*!< 2 adjacent pixels */
+    VDC5_NR_TAPSEL_3,               /*!< 3 adjacent pixels */
+    VDC5_NR_TAPSEL_4,               /*!< 4 adjacent pixels */
+    VDC5_NR_TAPSEL_NUM
+} vdc5_nr_tap_t;
+/*! Noise reduction gain adjustment */
+typedef enum
+{
+    VDC5_NR_GAIN_1_2 = 0,           /*!< 1/2 */
+    VDC5_NR_GAIN_1_4,               /*!< 1/4 */
+    VDC5_NR_GAIN_1_8,               /*!< 1/8 */
+    VDC5_NR_GAIN_1_16,              /*!< 1/16 */
+    VDC5_NR_GAIN_NUM
+} vdc5_nr_gain_t;
+/*! Noise reduction parameter */
+typedef struct
+{
+    vdc5_nr_tap_t   nr1d_tap;       /*!< TAP select */
+    uint32_t        nr1d_th;        /*!< Maximum value of coring (absolute value) */
+    vdc5_nr_gain_t  nr1d_gain;      /*!< Noise reduction gain adjustment */
+} vdc5_nr_param_t;
+/*! Noise reduction setup parameter */
+typedef struct
+{
+    vdc5_nr_param_t     y;          /*!< Y/G signal noise reduction parameter */
+    vdc5_nr_param_t     cb;         /*!< Cb/B signal noise reduction parameter */
+    vdc5_nr_param_t     cr;         /*!< Cr/R signal noise reduction parameter */
+} vdc5_noise_reduction_t;
+
+/******************************* For R_VDC5_ImageColorMatrix        *******************************/
+/*! Color matrix module */
+typedef enum
+{
+    VDC5_COLORMTX_IMGCNT = 0,           /*!< Input Controller (input video signal) */
+    VDC5_COLORMTX_ADJ_0,                /*!< Image quality improver 0 (scaler 0 output) */
+    VDC5_COLORMTX_NUM
+} vdc5_colormtx_module_t;
+/*! Operating mode */
+typedef enum
+{
+    VDC5_COLORMTX_GBR_GBR = 0,          /*!< GBR to GBR */
+    VDC5_COLORMTX_GBR_YCBCR,            /*!< GBR to YCbCr */
+    VDC5_COLORMTX_YCBCR_GBR,            /*!< YCbCr to GBR */
+    VDC5_COLORMTX_YCBCR_YCBCR,          /*!< YCbCr to YCbCr */
+    VDC5_COLORMTX_MODE_NUM              /*!< The number of operating modes */
+} vdc5_colormtx_mode_t;
+/*! Color matrix offset (DC) adjustment */
+typedef enum
+{
+    VDC5_COLORMTX_OFFST_YG = 0,         /*!< YG */
+    VDC5_COLORMTX_OFFST_B,              /*!< B */
+    VDC5_COLORMTX_OFFST_R,              /*!< R */
+    VDC5_COLORMTX_OFFST_NUM             /*!< The number of the color matrix DC offset values */
+} vdc5_colormtx_offset_t;
+/*! Color matrix signal gain adjustment */
+typedef enum
+{
+    VDC5_COLORMTX_GAIN_GG = 0,          /*!< GG */
+    VDC5_COLORMTX_GAIN_GB,              /*!< GB */
+    VDC5_COLORMTX_GAIN_GR,              /*!< GR */
+    VDC5_COLORMTX_GAIN_BG,              /*!< BG */
+    VDC5_COLORMTX_GAIN_BB,              /*!< BB */
+    VDC5_COLORMTX_GAIN_BR,              /*!< BR */
+    VDC5_COLORMTX_GAIN_RG,              /*!< RG */
+    VDC5_COLORMTX_GAIN_RB,              /*!< RB */
+    VDC5_COLORMTX_GAIN_RR,              /*!< RR */
+    VDC5_COLORMTX_GAIN_NUM              /*!< The number of the color matrix gain values */
+} vdc5_colormtx_gain_t;
+/*! Color matrix setup parameter */
+typedef struct
+{
+    vdc5_colormtx_module_t  module;                         /*!< Color matrix module */
+    vdc5_colormtx_mode_t    mtx_mode;                       /*!< Operating mode */
+    uint16_t                offset[VDC5_COLORMTX_OFFST_NUM];/*!< Offset (DC) adjustment of Y/G, B, and R signal */
+    uint16_t                gain[VDC5_COLORMTX_GAIN_NUM];   /*!< GG, GB, GR, BG, BB, BR, RG, RB, and RR signal
+                                                                 gain adjustment */
+} vdc5_color_matrix_t;
+
+/******************************* For R_VDC5_ImageEnhancement        *******************************/
+/*! Image quality improver ID */
+typedef enum
+{
+    VDC5_IMG_IMPRV_0 = 0,           /*!< Image quality improver 0 */
+    VDC5_IMG_IMPRV_NUM              /*!< The number of image quality improvers */
+} vdc5_imgimprv_id_t;
+
+/*! Sharpness band */
+typedef enum
+{
+    VDC5_IMGENH_SHARP_H1 = 0,       /*!< H1: Adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_H2,           /*!< H2: Second adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_H3,           /*!< H3: Third adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_NUM           /*!< The number of horizontal sharpness bands */
+} vdc5_img_enh_sh_t;
+/*! Sharpness control parameter */
+typedef struct
+{
+    uint8_t     shp_clip_o;         /*!< Sharpness correction value clipping (on the overshoot side) */
+    uint8_t     shp_clip_u;         /*!< Sharpness correction value clipping (on the undershoot side) */
+    uint8_t     shp_gain_o;         /*!< Sharpness edge amplitude value gain (on the overshoot side) */
+    uint8_t     shp_gain_u;         /*!< Sharpness edge amplitude value gain (on the undershoot side) */
+    uint8_t     shp_core;           /*!< Active sharpness range */
+} vdc5_sharpness_ctrl_t;
+/*! Sharpness setup parameter */
+typedef struct
+{
+    vdc5_onoff_t            shp_h2_lpf_sel;                     /*!< LPF selection for folding prevention
+                                                                     before H2 edge detection */
+    vdc5_sharpness_ctrl_t   hrz_sharp[VDC5_IMGENH_SHARP_NUM];   /*!< Sharpness control parameter (H1, H2, and H3) */
+} vdc5_enhance_sharp_t;
+/*! LTI band */
+typedef enum
+{
+    VDC5_IMGENH_LTI1 = 0,           /*!< H2: Second adjacent pixel used as reference */
+    VDC5_IMGENH_LTI2,               /*!< H4: Fourth adjacent pixel used as reference */
+    VDC5_IMGENH_LTI_NUM             /*!< The number of horizontal LTI bands */
+} vdc5_img_enh_lti_t;
+/*! Median filter reference pixel select */
+typedef enum
+{
+    VDC5_LTI_MDFIL_SEL_ADJ2 = 0,    /*!< Second adjacent pixel selected as reference */
+    VDC5_LTI_MDFIL_SEL_ADJ1         /*!< Adjacent pixel selected as reference */
+} vdc5_lti_mdfil_sel_t;
+/*! LTI control parameter */
+typedef struct
+{
+    uint8_t     lti_inc_zero;       /*!< Median filter LTI correction threshold */
+    uint8_t     lti_gain;           /*!< LTI edge amplitude value gain */
+    uint8_t     lti_core;           /*!< LTI coring (maximum core value of 255) */
+} vdc5_lti_ctrl_t;
+/*! Luminance Transient Improvement setup parameter */
+typedef struct
+{
+    vdc5_onoff_t            lti_h2_lpf_sel;             /*!< LPF selection for folding prevention
+                                                             before H2 edge detection */
+    vdc5_lti_mdfil_sel_t    lti_h4_median_tap_sel;      /*!< Median filter reference pixel select */
+    vdc5_lti_ctrl_t         lti[VDC5_IMGENH_LTI_NUM];   /*!< LTI control parameter (H2 and H4) */
+} vdc5_enhance_lti_t;
+
+/******************************* For R_VDC5_ImageBlackStretch       *******************************/
+/*! Black stretch setup parameter */
+typedef struct
+{
+    uint16_t    bkstr_st;           /*!< Black stretch start point */
+    uint16_t    bkstr_d;            /*!< Black stretch depth */
+    uint16_t    bkstr_t1;           /*!< Black stretch time constant (T1) */
+    uint16_t    bkstr_t2;           /*!< Black stretch time constant (T2) */
+} vdc5_black_t;
+
+/******************************* For R_VDC5_AlphaBlending           *******************************/
+/*! Alpha signal of the ARGB1555/ARGB5551 format */
+typedef struct
+{
+    uint8_t     gr_a0;                  /*!< Alpha signal when alpha is set to '0' */
+    uint8_t     gr_a1;                  /*!< Alpha signal when alpha is set to '1' */
+} vdc5_alpha_argb1555_t;
+/*! Alpha blending in one-pixel units */
+typedef struct
+{
+    vdc5_onoff_t    gr_acalc_md;        /*!< Premultiplication processing at alpha blending
+                                             in one-pixel units (on/off) */
+} vdc5_alpha_pixel_t;
+/*! Alpha blending setup parameter */
+typedef struct
+{
+    const vdc5_alpha_argb1555_t   * alpha_1bit; /*!< Alpha signal of the ARGB1555/ARGB5551 format */
+    const vdc5_alpha_pixel_t      * alpha_pixel;/*!< Premultiplication processing at alpha blending in one-pixel */
+} vdc5_alpha_blending_t;
+
+/******************************* For R_VDC5_AlphaBlendingRect       *******************************/
+/*! Parameter for alpha blending in a rectangular area */
+typedef struct
+{
+    int16_t         gr_arc_coef;        /*!< Alpha coefficient for alpha blending in a rectangular area
+                                             (-255 to 255) */
+    uint8_t         gr_arc_rate;        /*!< Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+    uint8_t         gr_arc_def;         /*!< Initial alpha value for alpha blending in a rectangular area */
+    vdc5_onoff_t    gr_arc_mul;         /*!< Multiplication processing with current alpha at alpha blending
+                                             in a rectangular area (on/off) */
+} vdc5_alpha_rect_t;
+/*! Selection of lower-layer plane in scaler */
+typedef struct
+{
+    vdc5_onoff_t    gr_vin_scl_und_sel; /*!< Selection of lower-layer plane in scaler
+                                             - VDC5_OFF: Selects graphics 0 as lower-layer graphics
+                                                         and graphics 1 as current graphics
+                                             - VDC5_ON: Selects graphics 1 as lower-layer graphics
+                                                        and graphics 0 as current graphics */
+} vdc5_scl_und_sel_t;
+/*! Setup parameter for alpha blending in a rectangular area */
+typedef struct
+{
+    const vdc5_pd_disp_rect_t * gr_arc;     /*!< Rectangular area subjected to alpha blending */
+    const vdc5_alpha_rect_t   * alpha_rect; /*!< Parameter for alpha blending in a rectangular area */
+    const vdc5_scl_und_sel_t  * scl_und_sel;/*!< Selection of lower-layer plane in scaler */
+} vdc5_alpha_blending_rect_t;
+
+/******************************* For R_VDC5_Chromakey               *******************************/
+/*! Chroma-key setup parameter */
+typedef struct
+{
+    uint32_t    ck_color;       /*!< RGB/CLUT signal for RGB/CLUT-index chroma-key processing */
+    uint32_t    rep_color;      /*!< Replaced ARGB signal after RGB/CLUT-index chroma-key processing */
+    uint8_t     rep_alpha;      /*!< Replaced alpha signal after RGB-index chroma-key processing (in 8 bits) */
+} vdc5_chromakey_t;
+
+/******************************* For R_VDC5_CLUT                    *******************************/
+/*! CLUT setup parameter */
+typedef struct
+{
+    uint32_t            color_num;  /*!< The number of colors in CLUT */
+    const uint32_t    * clut;       /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
+} vdc5_clut_t;
+
+/******************************* For R_VDC5_DisplayCalibration      *******************************/
+/*! Correction circuit sequence control */
+typedef enum
+{
+    VDC5_CALIBR_ROUTE_BCG = 0,          /*!< Brightness -> contrast -> gamma correction */
+    VDC5_CALIBR_ROUTE_GBC               /*!< Gamma correction -> brightness -> contrast */
+} vdc5_calibr_route_t;
+/*! Brightness (DC) adjustment parameter */
+typedef struct
+{
+    uint16_t    pbrt_g;                 /*!< Brightness (DC) adjustment of G signal */
+    uint16_t    pbrt_b;                 /*!< Brightness (DC) adjustment of B signal */
+    uint16_t    pbrt_r;                 /*!< Brightness (DC) adjustment of R signal */
+} vdc5_calibr_bright_t;
+/*! Contrast (gain) adjustment parameter */
+typedef struct
+{
+    uint8_t     cont_g;                 /*!< Contrast (gain) adjustment of G signal */
+    uint8_t     cont_b;                 /*!< Contrast (gain) adjustment of B signal */
+    uint8_t     cont_r;                 /*!< Contrast (gain) adjustment of R signal */
+} vdc5_calibr_contrast_t;
+/*! Panel dither operation mode */
+typedef enum
+{
+    VDC5_PDTH_MD_TRU = 0,               /*!< Truncate */
+    VDC5_PDTH_MD_RDOF,                  /*!< Round-off */
+    VDC5_PDTH_MD_2X2,                   /*!< 2 x 2 pattern dither */
+    VDC5_PDTH_MD_RAND,                  /*!< Random pattern dither */
+    VDC5_PDTH_MD_NUM
+} vdc5_panel_dither_md_t;
+/*! Panel dithering parameter */
+typedef struct
+{
+    vdc5_panel_dither_md_t  pdth_sel;   /*!< Panel dither operation mode */
+    uint8_t                 pdth_pa;    /*!< Pattern value (A) of 2x2 pattern dither */
+    uint8_t                 pdth_pb;    /*!< Pattern value (B) of 2x2 pattern dither */
+    uint8_t                 pdth_pc;    /*!< Pattern value (C) of 2x2 pattern dither */
+    uint8_t                 pdth_pd;    /*!< Pattern value (D) of 2x2 pattern dither */
+} vdc5_calibr_dither_t;
+/*! Display calibration parameter */
+typedef struct
+{
+    vdc5_calibr_route_t             route;          /*!< Correction circuit sequence control */
+    const vdc5_calibr_bright_t    * bright;         /*!< Brightness (DC) adjustment parameter */
+    const vdc5_calibr_contrast_t  * contrast;       /*!< Contrast (gain) adjustment parameter */
+    const vdc5_calibr_dither_t    * panel_dither;   /*!< Panel dithering parameter */
+} vdc5_disp_calibration_t;
+
+/******************************* For R_VDC5_GammaCorrection         *******************************/
+/*! Gamma correction setup parameter */
+typedef struct
+{
+    const uint16_t    * gam_g_gain;     /*!< Gain adjustment of area 0 to 31 of G signal */
+    const uint8_t     * gam_g_th;       /*!< Start threshold of area 1 to 31 of G signal */
+    const uint16_t    * gam_b_gain;     /*!< Gain adjustment of area 0 to 31 of B signal */
+    const uint8_t     * gam_b_th;       /*!< Start threshold of area 1 to 31 of B signal */
+    const uint16_t    * gam_r_gain;     /*!< Gain adjustment of area 0 to 31 of R signal */
+    const uint8_t     * gam_r_th;       /*!< Start threshold of area 1 to 31 of R signal */
+} vdc5_gamma_correction_t;
+
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdc5_error_t R_VDC5_Initialize(
+    const vdc5_channel_t        ch,
+    const vdc5_init_t   * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num);
+vdc5_error_t R_VDC5_Terminate(const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdc5_error_t R_VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
+vdc5_error_t R_VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+vdc5_error_t R_VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
+vdc5_error_t R_VDC5_CallbackISR(const vdc5_channel_t ch, const vdc5_int_t * const param);
+vdc5_error_t R_VDC5_WriteDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param);
+vdc5_error_t R_VDC5_ChangeWriteProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t   * const param);
+vdc5_error_t R_VDC5_ReadDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_read_t   * const param);
+vdc5_error_t R_VDC5_ChangeReadProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param);
+vdc5_error_t R_VDC5_StartProcess(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param);
+vdc5_error_t R_VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_VideoNoiseReduction(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param);
+vdc5_error_t R_VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+vdc5_error_t R_VDC5_ImageEnhancement(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area);
+vdc5_error_t R_VDC5_ImageBlackStretch(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param);
+vdc5_error_t R_VDC5_AlphaBlending(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param);
+vdc5_error_t R_VDC5_AlphaBlendingRect(
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param);
+vdc5_error_t R_VDC5_Chromakey(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param);
+vdc5_error_t R_VDC5_CLUT(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param);
+vdc5_error_t R_VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+vdc5_error_t R_VDC5_GammaCorrection(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param);
+
+void (*R_VDC5_GetISR(const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense);
+
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_VDC5_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/include/r_vdc5_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_user.h
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver user-defined header
+******************************************************************************/
+
+#ifndef R_VDC5_USER_H
+#define R_VDC5_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Compilation switch to enable parameter check functions<br>
+    If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_VDC5_CHECK_PARAMETERS
+
+
+/*! GBR to YCbCr conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - Y  =  0.299 * R + 0.587 * G + 0.114 * B
+ *  - Cb = -0.169 * R - 0.331 * G + 0.500 * B
+ *  - Cr =  0.500 * R - 0.419 * G - 0.081 * B
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum
+{
+    VDC5_COLORCONV_Y_R  = (77u),
+    VDC5_COLORCONV_Y_G  = (150u),
+    VDC5_COLORCONV_Y_B  = (29u),
+    VDC5_COLORCONV_CB_R = (2005u),
+    VDC5_COLORCONV_CB_G = (1963u),
+    VDC5_COLORCONV_CB_B = (128u),
+    VDC5_COLORCONV_CR_R = (128u),
+    VDC5_COLORCONV_CR_G = (1941u),
+    VDC5_COLORCONV_CR_B = (2027u)
+} vdc5_colcnv_rgb_ycbcr_t;
+
+/*! YCbCr to GBR conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - G = 1.0 * Y - 0.344 * Cb - 0.714 * Cr
+ *  - B = 1.0 * Y + 1.772 * Cb +   0.0 * Cr
+ *  - R = 1.0 * Y +   0.0 * Cb + 1.402 * Cr
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum
+{
+    VDC5_COLORCONV_G_Y  = (256u),
+    VDC5_COLORCONV_G_CB = (1960u),
+    VDC5_COLORCONV_G_CR = (1865u),
+    VDC5_COLORCONV_B_Y  = (256u),
+    VDC5_COLORCONV_B_CB = (454u),
+    VDC5_COLORCONV_B_CR = (0u),
+    VDC5_COLORCONV_R_Y  = (256u),
+    VDC5_COLORCONV_R_CB = (0u),
+    VDC5_COLORCONV_R_CR = (359u)
+} vdc5_colcnv_ycbcr_rgb_t;
+
+/*! Color matrix DC offset typical value */
+#define     VDC5_COLORCONV_DC_OFFSET        (128u)
+/*! Color matrix coefficient value that represents one times */
+#define     VDC5_COLORCONV_1TIMES_GAIN      (256u)
+
+
+#endif  /* R_VDC5_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1204 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+#include    "r_vdc5_shared_param.h"
+#include    "r_vdc5_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_graphics_type_t ConvertRwProcId2GrId(const vdc5_layer_id_t layer_id);
+
+
+/**************************************************************************//**
+ * @brief       VDC5 driver initialization
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Initializes the VDC5 driver's internal variables.
+ *              - Calls the user-defined function specified in init_func.
+ *              - Sets up and enables the VDC5's panel clock.
+ *              - Disables all the VDC5 interrupts.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   param                   : Initialization parameter
+ * @param[in]   init_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Initialize (
+    const vdc5_channel_t        ch,
+    const vdc5_init_t   * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num)
+{
+    vdc5_error_t            ret;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_InitializeCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmInit();
+
+        /* Callback function */
+        if (init_func != 0)
+        {
+            init_func(user_num);
+        }
+
+        VDC5_Initialize(param);
+
+        /* Disable all VDC5 interrupts */
+        VDC5_Int_Disable();
+
+        VDC5_ShrdPrmSetResource(VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief       VDC5 driver termination
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Disables all the VDC5 interrupts.
+ *              - Disables the VDC5 panel clock.
+ *              - Calls the user-defined function specified in quit_func.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   quit_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Terminate (const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    vdc5_error_t    ret;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_TerminateCheckPrm(ch);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Disable all VDC5 interrupts */
+        VDC5_Int_Disable();
+
+        VDC5_Terminate();
+
+        VDC5_ShrdPrmSetResource(VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_INVALID);
+
+        /* Callback function */
+        if (quit_func != 0)
+        {
+            quit_func(user_num);
+        }
+    }
+    return ret;
+}   /* End of function R_VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Video input setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the phase timing of the input signals.
+ *              - Performs delay control on the sync signal for the video inputs.
+ *              - Sets up the parameters for the external input video signals.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_error_t ret;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_VideoInputCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmSetInputParam(param);
+
+        /* Setting VDC5 registers */
+        VDC5_VideoInput(param);
+
+        VDC5_ShrdPrmSetResource(VDC5_RESOURCE_VIDEO_IN, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Synchronization control setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Selects the vertical sync signal.
+ *              - Sets up the period of the sync signal.
+ *              - Sets up the delay of the vertical sync signal.
+ *              - Sets up the full-screen enable signal.
+ *              - Sets up the compensation for the vertical sync signal.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   param                   : Synchronization control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_SyncControlCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+        {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        if (param->res_vs_sel == VDC5_OFF)
+        {   /* External input Vsync signal is selected. */
+            rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_VIDEO_IN);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+            {
+                ret = VDC5_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_SyncControl(param);
+
+        VDC5_ShrdPrmSetResource(VDC5_RESOURCE_VSYNC, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Display output setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the timing signals for driving the LCD panel.
+ *              - Sets up the phase, data sequence, and format of the LCD panel output data.
+ *              - Sets up the background color.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_DisplayOutputCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+        {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        }
+        else
+        {
+            rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_VSYNC);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+            {
+                ret = VDC5_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmSetOutputParam(param);
+
+        /* Setting VDC5 registers */
+        VDC5_DisplayOutput(param);
+
+        VDC5_ShrdPrmSetResource(VDC5_RESOURCE_LCD_PANEL, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CallbackISR (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_CallbackISRCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+        {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        }
+        else
+        {
+            rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_VSYNC);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+            {
+                ret = VDC5_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_Int_SetInterrupt(param);
+    }
+    return ret;
+}   /* End of function R_VDC5_CallbackISR() */
+
+/**************************************************************************//**
+ * @brief       Data write control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the input image area to be captured.
+ *              - Makes input image scale-down/rotation control settings.
+ *              - Makes frame buffer write control settings.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_WR
+ * @param[in]   param                   : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_WriteDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_WriteDataControlCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is already used. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_VIDEO_IN);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+            {
+                ret = VDC5_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmSetWriteParam(param);
+
+        /* Setting VDC5 registers */
+        VDC5_WriteDataControl(param);
+
+        VDC5_ShrdPrmSetLayerResource(layer_id, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data write change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the input image area to be captured.
+ *              - Makes changes with respect to scaling-down/rotation control of the input image.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_WR
+ * @param[in]   param                   : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeWriteProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChangeWriteProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmSetChgWriteParam(param);
+
+        /* Setting VDC5 registers */
+        VDC5_ChangeWriteProcess(param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Data read control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the display area for graphics images.
+ *              - Makes image scale-up control settings (only layer 0).
+ *              - Makes frame buffer read control settings.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   param                   : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReadDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ReadDataControlCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is already used. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmSetReadParam(graphics_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ReadDataControl(graphics_id, param);
+
+        VDC5_ShrdPrmSetLayerResource(layer_id, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control, only layer 0).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   param                   : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeReadProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChangeReadProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmSetChgReadParam(graphics_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ChangeReadProcess(graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read start processing
+ *
+ *              Description:<br>
+ *              This function performs layer start processing. If the layer ID specified in layer_id
+ *              is VDC5_LAYER_ID_ALL, the function starts all the layers that are in the stopped state
+ *              and also enabled. If the layer ID is not VDC5_LAYER_ID_ALL, the function starts only
+ *              the specified layer.<br>
+ *              When performing start processing for write, the function starts a write to the frame buffer.
+ *              When performing start processing for read, the function starts a read from the frame buffer
+ *              and sets the graphics display mode to the specified values for each layer.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_ALL
+ *                                        - VDC5_LAYER_ID_0_WR
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StartProcess (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_StartProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL)
+        {
+            rsrc_state = VDC5_ShrdPrmGetRwProcReady(layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+            {   /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_StartProcess(layer_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read stop processing
+ *
+ *              Description:<br>
+ *              This function performs layer stop processing. If the layer ID specified in layer_id is
+ *              VDC5_LAYER_ID_ALL, the function stops all the layers that are enabled and running.
+ *              If the layer ID is not VDC5_LAYER_ID_ALL, the function stops only the specified layer.<br>
+ *              When performing stop processing for write, the function stops the write to the frame buffer.
+ *              When performing stop processing for read, the function stops the read from the frame buffer
+ *              and resets the graphics display mode to the initial values for each of the layers.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_ALL
+ *                                        - VDC5_LAYER_ID_0_WR
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_StopProcessCheckPrm(ch, layer_id);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL)
+        {
+            rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+            {   /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_StopProcess(layer_id);
+    }
+    return ret;
+}   /* End of function R_VDC5_StopSurface() */
+
+/**************************************************************************//**
+ * @brief       Data write/read control release processing
+ *
+ *              Description:<br>
+ *              If the layer ID specified in layer_id is VDC5_LAYER_ID_ALL, the function disables all the layers
+ *              that are not running and also enabled. If the layer ID is not VDC5_LAYER_ID_ALL, the function
+ *              disables only the specified layers.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_ALL
+ *                                        - VDC5_LAYER_ID_0_WR
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ReleaseDataControlCheckPrm(ch, layer_id);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL)
+        {
+            rsrc_state = VDC5_ShrdPrmGetRwProcReady(layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+            {   /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        VDC5_ShrdPrmSetLayerResource(layer_id, VDC5_RESOURCE_ST_INVALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief       Noise reduction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off noise reduction processing.
+ *              - Sets up the noise reduction parameters for the Y/G, Cb/B, and Cr/R signals.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoNoiseReduction (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_VideoNoiseReductCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_VIDEO_IN);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+        {
+            ret = VDC5_ERR_RESOURCE_INPUT;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_VideoNoiseReduction(nr1d_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Color matrix setup
+ *
+ *              Description:<br>
+ *              This function sets up the specified color matrix.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageColorMatrixCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        if (param->module == VDC5_COLORMTX_IMGCNT)
+        {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(VDC5_LAYER_ID_0_WR);
+        }
+        else    /* VDC5_COLORMTX_ADJ_0 */
+        {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(VDC5_LAYER_ID_0_RD);
+        }
+
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_ImageColorMatrix(param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Image enhancement processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off sharpness processing.
+ *              - Sets up the sharpness parameter.
+ *              - Turns on and off LTI processing.
+ *              - Sets up the LTI parameter.
+ *              - Sets up the enhancer-enabled area to be subjected to sharpness and LTI processing.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ *                                        - VDC5_IMG_IMPRV_0
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageEnhancement (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_color_space_t      color_space;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageEnhancementCheckPrm(ch, imgimprv_id, sharp_param, enh_area);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(VDC5_LAYER_ID_0_RD);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(VDC5_GR_TYPE_GR0);
+            if (color_space == VDC5_COLOR_SPACE_GBR)
+            {   /* The image quality improver does not act on RGB signals. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_ImageEnhancement(shp_h_on, sharp_param, lti_h_on, lti_param, enh_area);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Black stretch setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off black stretch processing.
+ *              - Sets up the black stretch parameters.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ *                                        - VDC5_IMG_IMPRV_0
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageBlackStretch (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_color_space_t      color_space;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageBlackStretchCheckPrm(ch, imgimprv_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(VDC5_LAYER_ID_0_RD);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(VDC5_GR_TYPE_GR0);
+            if (color_space == VDC5_COLOR_SPACE_GBR)
+            {   /* The image quality improver does not act on RGB signals. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_ImageBlackStretch(bkstr_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the alpha value of the ARGB1555/RGBA5551 formats.
+ *              - Make settings for premultiplication processing at alpha blending in one-pixel.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlending (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_AlphaBlendingCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_AlphaBlending(graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Rectangle alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off alpha blending in a rectangular area.
+ *              - Sets up the rectangular area subjected to alpha blending.
+ *              - Sets up the alpha value for alpha blending in a rectangular area.
+ *              - Makes fade-in/-out settings to be applied to rectangle alpha blending.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlendingRect (
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_AlphaBlendingRectCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_AlphaBlendingRect(graphics_id, gr_arc_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_AlphaBlendingRect() */
+
+/**************************************************************************//**
+ * @brief       Chroma-key setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off the chroma-key processing.
+ *              - Sets up the color signals to be subject to chroma-key processing and
+ *                the color signals after replacement.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Chromakey (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_color_space_t      color_space;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChromakeyCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(graphics_id);
+            if (color_space == VDC5_COLOR_SPACE_YCBCR)
+            {   /* Chroma-key processing cannot be used
+                   when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_Chromakey(graphics_id, gr_ck_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       CLUT setup
+ *
+ *              Description:<br>
+ *              This function sets up CLUT for the specified layer.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CLUT (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_CLUTCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_CLUT(graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_SetCLUT() */
+
+/**************************************************************************//**
+ * @brief       Display calibration processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up panel brightness adjustment.
+ *              - Sets up contrast adjustment.
+ *              - Sets up panel dithering.
+ *              - Makes control settings for the correction circuit sequence.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_DisplayCalibrationCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+        {
+            ret = VDC5_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_DisplayCalibration(param);
+    }
+    return ret;
+}   /* End of function R_VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Gamma correction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off gamma correction processing.
+ *              - Sets up the gamma correction gain adjustment values for the G/B/R signals.
+ *              - Sets up the gamma correction start threshold values for the G/B/R signals.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   gam_on                  : Gamma correction ON/OFF setting
+ * @param[in]   param                   : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_GammaCorrection (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_GammaCorrectionCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(VDC5_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID)
+        {
+            ret = VDC5_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC5_OK)
+    {
+        /* Setting VDC5 registers */
+        VDC5_GammaCorrection(gam_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Convert read/write process ID into graphics type ID
+ *
+ * @param[in]   layer_id              : Layer ID
+ * @retval      Graphics type ID
+ *****************************************************************************/
+static vdc5_graphics_type_t ConvertRwProcId2GrId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_graphics_type_t graphics_id;
+
+    switch (layer_id)
+    {
+        case VDC5_LAYER_ID_0_RD:                /* Layer 0, read process */
+            graphics_id = VDC5_GR_TYPE_GR0;     /* Graphics 0 */
+        break;
+        case VDC5_LAYER_ID_2_RD:                /* Layer 2, read process */
+            graphics_id = VDC5_GR_TYPE_GR2;     /* Graphics 2 */
+        break;
+        case VDC5_LAYER_ID_3_RD:                /* Layer 3, read process */
+            graphics_id = VDC5_GR_TYPE_GR3;     /* Graphics 3 */
+        break;
+        default:                                /* Error */
+            graphics_id = VDC5_GR_TYPE_NUM;
+        break;
+    }
+    return graphics_id;
+}   /* End of function ConvertRwProcId2GrId() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_check_parameter.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2034 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_check_parameter.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_shared_param.h"
+#include    "r_vdc5_check_parameter.h"
+
+
+#ifdef      R_VDC5_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDC5_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDC5_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDC5_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDC5_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDC5_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDC5_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDC5_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDC5_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDC5_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDC5_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDC5_CPARA_RANGE_0X00007FFF (0x00007FFFu)
+#define VDC5_CPARA_RANGE_0X0000FFFF (0x0000FFFFu)
+#define VDC5_CPARA_RANGE_0X007FFFFF (0x007FFFFFu)
+#define VDC5_CPARA_RANGE_0X00FFFFFF (0x00FFFFFFu)
+/* Valid range for signal delay amount */
+#define VDC5_CPARA_INP_FLD_DLY_MAX (254u)
+#define VDC5_CPARA_INP_VS_DLY_MAX  (254u)
+#define VDC5_CPARA_INP_HS_DLY_MAX  (254u)
+/* Valid range for NFS */
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_56 (56u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_24 (24u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_28 (28u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_31 (31u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_37 (37u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_39 (39u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_46 (46u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_47 (47u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_55 (55u)
+/* Valid range for HS + HW */
+#define VDC5_CPARA_HS_HW_MAX       (2015u)
+/* Valid range for HS */
+#define VDC5_CPARA_HS_MIN          (16u)
+/* Valid range for VS + VW */
+#define VDC5_CPARA_VS_VW_MAX       (2039u)
+/* Valid range for VS */
+#define VDC5_CPARA_VS_MIN          (4u)
+/* The max number of CLUT data values */
+#define VDC5_CPARA_CLUT8_NUM       (256u)
+#define VDC5_CPARA_CLUT4_NUM       (16u)
+#define VDC5_CPARA_CLUT1_NUM       (2u)
+/* Valid range for the alpha coefficient */
+#define VDC5_CPARA_GR_ARC_COEF_MIN (-255)
+#define VDC5_CPARA_GR_ARC_COEF_MAX (255)
+/* Valid range for HS of enhancer area */
+#define VDC5_CPARA_ENH_HS_LIMIT    (4u)
+/* Valid range for VS of enhancer area */
+#define VDC5_CPARA_ENH_VS_LIMIT    (2u)
+
+#define VDC5_BKSTR_T2_PROHIBITED    (31u)
+
+#define VDC5_MULTIPLE_4_MASK        (0x00000003u)
+#define VDC5_MULTIPLE_32_MASK       (0x0000001Fu)
+#define VDC5_MULTIPLE_128_MASK      (0x0000007Fu)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_error_t CheckChannel(const vdc5_channel_t ch);
+static vdc5_error_t CheckLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckGraphicsTypeLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckRect(const vdc5_period_rect_t * const rect);
+static vdc5_error_t CheckTcon_Vertical(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_Horizontal(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_HorizontalPol(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_DataEnable(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckGammaCrct_GainAdjustment(const uint16_t * gam_gain);
+
+
+/**************************************************************************//**
+ * @brief       Checks on initialization parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Initialization parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_InitializeCheckPrm (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Panel clock select */
+    if (param->panel_icksel >= VDC5_PANEL_ICKSEL_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Clock frequency division ratio */
+    if (param->panel_dcdr >= VDC5_PANEL_CLKDIV_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_InitializeCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_Terminate
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_TerminateCheckPrm (const vdc5_channel_t ch)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_TerminateCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on video input setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoInputCheckPrm (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_error_t                error;
+    const vdc5_sync_delay_t   * dly_tmp;
+    const vdc5_ext_in_sig_t   * ext_sig_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Vsync signal 1/2fH phase timing */
+    if (((uint32_t)param->inp_fh50 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal 1/4fH phase timing */
+    if (((uint32_t)param->inp_fh25 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL)
+    {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        if (((uint32_t)dly_tmp->inp_vs_dly_l & (uint32_t)~VDC5_CPARA_RANGE_0X00000007) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Field differentiation signal delay amount */
+        if (((uint32_t)dly_tmp->inp_fld_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_fld_dly > (uint32_t)VDC5_CPARA_INP_FLD_DLY_MAX)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Vsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_vs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_vs_dly > (uint32_t)VDC5_CPARA_INP_VS_DLY_MAX)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Hsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_hs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_hs_dly > (uint32_t)VDC5_CPARA_INP_HS_DLY_MAX)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* External input format select */
+    if (ext_sig_tmp->inp_format >= VDC5_EXTIN_FORMAT_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    if (ext_sig_tmp->inp_h_pos >= VDC5_EXTIN_H_POS_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_YCRYCB) || (ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_CRYCBY))
+    {
+        if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR422)
+        {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_VideoInputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sync control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Sync control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_SyncControlCheckPrm (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    if (param->res_vs_sel != VDC5_OFF)
+    {
+        /* Free-running Vsync period setting */
+        if (((uint32_t)param->res_fv & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Hsync period setting */
+    if (((uint32_t)param->res_fh & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal delay control */
+    if (((uint32_t)param->res_vsdly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Full-screen enable control */
+    error = CheckRect(&param->res_f);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_SyncControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display output configuration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayOutputCheckPrm (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_error_t                    error;
+    uint32_t                        tcon_sig_index;
+    static vdc5_error_t    (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+                                        const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing) =
+    {
+        &CheckTcon_Vertical,        /* STVA/VS */
+        &CheckTcon_Vertical,        /* STVB/VE */
+        &CheckTcon_Horizontal,      /* STH/HS */
+        &CheckTcon_Horizontal,      /* STB/HE */
+        &CheckTcon_Horizontal,      /* CPV/GCK */
+        &CheckTcon_HorizontalPol,   /* POLA */
+        &CheckTcon_HorizontalPol,   /* POLB */
+        &CheckTcon_DataEnable       /* DE */
+    };
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* 1/2fH timing */
+    if (((uint32_t)param->tcon_half & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Offset Hsync signal timing */
+    if (((uint32_t)param->tcon_offset & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* LCD TCON timing setting */
+    for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++)
+    {
+        if (param->outctrl[tcon_sig_index] != NULL)
+        {
+            error = tcon_function_tbl[tcon_sig_index](param->outctrl[tcon_sig_index]);
+            if (error != VDC5_OK)
+            {
+                goto END;
+            }
+        }
+    }
+
+    /* LCD output format select */
+    if (param->out_format >= VDC5_LCD_OUTFORMAT_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB)
+    {
+        /* Clock frequency control */
+        if (param->out_frq_sel >= VDC5_LCD_SERIAL_CLKFRQ_NUM)
+        {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC5_LCD_PARALLEL_CLKFRQ_1)
+        {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+        /* Clock phase adjustment */
+        if (param->out_phase >= VDC5_LCD_SERIAL_CLKPHASE_NUM)
+        {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC5_LCD_SERIAL_CLKFRQ_3)
+        {
+            if (param->out_phase == VDC5_LCD_SERIAL_CLKPHASE_3)
+            {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+    /* Background color in 24-bit RGB color format */
+    if ((param->bg_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_DisplayOutputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on interrupt callback setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CallbackISRCheckPrm (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* VDC5 interrupt type */
+    if (param->type >= VDC5_INT_TYPE_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Interrupt callback function pointer */
+    if (param->callback != 0)
+    {
+        if ((param->type == VDC5_INT_TYPE_VLINE) || (param->type == VDC5_INT_TYPE_S0_WLINE))
+        {
+            /* Line interrupt set */
+            if (((uint32_t)param->line_num & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_CallbackISRCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_WriteDataControlCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    if (layer_id != VDC5_LAYER_ID_0_WR)
+    {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode for image processing */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Swap setting in frame buffer writing */
+    if (param->res_wrswa >= VDC5_WR_RD_WRSWA_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer video-signal writing format */
+    if (param->res_md >= VDC5_RES_MD_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Writing rate */
+    if (param->res_fs_rate >= VDC5_RES_FS_RATE_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer base address */
+    if (param->base == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Frame buffer line offset address [byte] */
+    if ((param->ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->res_bst_md == VDC5_BST_MD_32BYTE)
+    {   /* 32-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else
+    {   /* 128-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    if ((param->flm_num & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u)
+    {
+        if ((param->flm_off & (uint32_t)~VDC5_CPARA_RANGE_0X007FFFFF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (param->res_bst_md == VDC5_BST_MD_32BYTE)
+        {   /* 32-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u)
+            {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+        else
+        {   /* 128-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u)
+            {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_WriteDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeWriteProcessCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t  * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    if (layer_id != VDC5_LAYER_ID_0_WR)
+    {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChangeWriteProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReadDataControlCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_error_t            error;
+    void                  * btm_base_tmp;
+    vdc5_resource_state_t   rsrc_state;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Frame buffer address setting signal */
+    if ((param->gr_flm_sel != VDC5_GR_FLM_SEL_SCALE_DOWN) &&
+        (param->gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) &&
+        (param->gr_flm_sel != VDC5_GR_FLM_SEL_POINTER_BUFF))
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (graphics_id == VDC5_GR_TYPE_GR0)
+    {
+        btm_base_tmp    = VDC5_ShrdPrmGetFrBuffBtm();
+        rsrc_state      = VDC5_ShrdPrmGetLayerResource(VDC5_LAYER_ID_0_WR);
+        if ((btm_base_tmp != NULL) && (rsrc_state != VDC5_RESOURCE_ST_INVALID))
+        {   /* btm_base_tmp is valid only when rsrc_state is valid. */
+            if (param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN)
+            {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+    else    /* VDC5_GR_TYPE_GR2 or VDC5_GR_TYPE_GR3 */
+    {
+        if (param->gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM)
+        {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Frame buffer base address */
+    if (param->gr_base == NULL)
+    {
+        if (param->gr_flm_sel != VDC5_GR_FLM_SEL_POINTER_BUFF)
+        {
+            error = VDC5_ERR_PARAM_NULL;
+            goto END;
+        }
+    }
+    /* Frame buffer line offset address */
+    if ((param->gr_ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->gr_bst_md == VDC5_BST_MD_32BYTE)
+    {   /* 32-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else
+    {   /* 128-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    if (param->width_read_fb != NULL)
+    {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Format of the frame buffer read signal */
+    if (param->gr_format >= VDC5_GR_FORMAT_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444))
+    {   /* YCbCr422 and YCbCr444 are supported for the graphics 0 and 1. */
+        if (graphics_id != VDC5_GR_TYPE_GR0)
+        {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    if (param->gr_format == VDC5_GR_FORMAT_YCBCR422)
+    {   /* Swapping of data read from buffer in the YCbCr422 format */
+        if (param->gr_ycc_swap >= VDC5_GR_YCCSWAP_NUM)
+        {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+    /* Swap setting in frame buffer reading */
+    if (param->gr_rdswa >= VDC5_WR_RD_WRSWA_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Graphics display area */
+    error = CheckRect(&param->gr_grc);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ReadDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeReadProcessCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Width of the image read from frame buffer */
+    if (param->width_read_fb != NULL)
+    {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Graphics display area */
+    if (param->gr_grc != NULL)
+    {
+        error = CheckRect(param->gr_grc);
+        if (error != VDC5_OK)
+        {
+            goto END;
+        }
+    }
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL)
+    {
+        if ((*(param->gr_disp_sel) < VDC5_DISPSEL_IGNORED) || (*(param->gr_disp_sel) >= VDC5_DISPSEL_NUM))
+        {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChangeReadProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write/read start parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StartProcessCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param)
+{
+    vdc5_error_t                error;
+    uint32_t                    graphics_types;
+    const vdc5_gr_disp_sel_t  * gr_disp_sel_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    gr_disp_sel_tmp = param->gr_disp_sel;
+    if (gr_disp_sel_tmp == NULL)
+    {
+        error = VDC5_OK;
+        goto END;
+    }
+    /* Graphics display mode */
+    if (layer_id == VDC5_LAYER_ID_ALL)
+    {
+        for (graphics_types = 0; graphics_types < VDC5_GR_TYPE_NUM; graphics_types++)
+        {
+            if ((gr_disp_sel_tmp[graphics_types] < VDC5_DISPSEL_IGNORED) ||
+                (gr_disp_sel_tmp[graphics_types] >= VDC5_DISPSEL_NUM))
+            {
+                error = VDC5_ERR_PARAM_UNDEFINED;
+                goto END;
+            }
+        }
+    }
+    else
+    {
+        if ((*gr_disp_sel_tmp < VDC5_DISPSEL_IGNORED) || (*gr_disp_sel_tmp >= VDC5_DISPSEL_NUM))
+        {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_StartProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_StopProcess
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StopProcessCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_StopProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_ReleaseDataControl
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReleaseDataControlCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ReleaseDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on noise reduction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoNoiseReductCheckPrm (const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param)
+{
+    vdc5_error_t            error;
+    const vdc5_nr_param_t * nr_param;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_OK;
+        goto END;
+    }
+
+    /* Y/G signal noise reduction parameter */
+    nr_param = &param->y;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cb/B signal noise reduction parameter */
+    nr_param = &param->cb;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cr/R signal noise reduction parameter */
+    nr_param = &param->cr;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_VideoNoiseReductCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on color matrix setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageColorMatrixCheckPrm (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    vdc5_error_t    error;
+    int32_t         colormtx_index;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Color matrix module */
+    if (param->module >= VDC5_COLORMTX_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Operating mode */
+    if (param->mtx_mode >= VDC5_COLORMTX_MODE_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->module != VDC5_COLORMTX_IMGCNT)
+    {
+        if ((param->mtx_mode == VDC5_COLORMTX_GBR_YCBCR) || (param->mtx_mode == VDC5_COLORMTX_YCBCR_YCBCR))
+        {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Offset (DC) adjustment of Y/G, B, and R signal */
+    for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_OFFST_NUM; colormtx_index++)
+    {
+        if (((uint32_t)param->offset[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_GAIN_NUM; colormtx_index++)
+    {
+        if (((uint32_t)param->gain[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageColorMatrixCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sharpness setup parameter and enhancer-enabled area setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   sharp_param : Sharpness setup parameter
+ * @param[in]   enh_area    : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageEnhancementCheckPrm (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC5_IMG_IMPRV_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Sharpness parameter */
+    if (sharp_param != NULL)
+    {
+        /* Sharpness control parameter (H1, H2, and H3) */
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Enhancer area */
+    if (enh_area != NULL)
+    {
+        /* Vertical start position */
+        if (((uint32_t)enh_area->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->vs < (uint32_t)VDC5_CPARA_ENH_VS_LIMIT)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Height (vertical width) */
+        if (((uint32_t)enh_area->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Horizontal start position */
+        if (((uint32_t)enh_area->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->hs < (uint32_t)VDC5_CPARA_ENH_HS_LIMIT)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Horizontal width */
+        if (((uint32_t)enh_area->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageEnhancementCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on black stretch setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   param       : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageBlackStretchCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_black_t  * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC5_IMG_IMPRV_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        /* Black stretch start point */
+        if (((uint32_t)param->bkstr_st & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch depth */
+        if (((uint32_t)param->bkstr_d & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T1) */
+        if (((uint32_t)param->bkstr_t1 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T2) */
+        if (((uint32_t)param->bkstr_t2 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->bkstr_t2 == VDC5_BKSTR_T2_PROHIBITED)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageBlackStretchCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on alpha blending setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingCheckPrm (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_2_RD) && (layer_id != VDC5_LAYER_ID_3_RD))
+    {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_AlphaBlendingCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on setup parameter for alpha blending in a rectangular area
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingRectCheckPrm (
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_2_RD) && (layer_id != VDC5_LAYER_ID_3_RD))
+    {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        /* Rectangular area subjected to alpha blending */
+        if (param->gr_arc != NULL)
+        {
+            /* Vertical start position */
+            if (((uint32_t)param->gr_arc->vs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Height (vertical width) */
+            if (((uint32_t)param->gr_arc->vw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal start position */
+            if (((uint32_t)param->gr_arc->hs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal width */
+            if (((uint32_t)param->gr_arc->hw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+        /* Alpha Blending in a rectangular area */
+        if (param->alpha_rect != NULL)
+        {
+            /* Frame rate for alpha blending in a rectangular area */
+            if ((param->alpha_rect->gr_arc_coef < (int16_t)VDC5_CPARA_GR_ARC_COEF_MIN) ||
+                (param->alpha_rect->gr_arc_coef > (int16_t)VDC5_CPARA_GR_ARC_COEF_MAX))
+            {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_AlphaBlendingRectCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma-key setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChromakeyCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_error_t        error;
+    vdc5_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(graphics_id);
+        switch (gr_format_tmp)
+        {
+            /* The following four cases are intentionally combined,
+              since the four types of graphics format are represented as 16 bit unsigned integer. */
+            case VDC5_GR_FORMAT_RGB565:
+            case VDC5_GR_FORMAT_ARGB1555:
+            case VDC5_GR_FORMAT_ARGB4444:
+            case VDC5_GR_FORMAT_RGBA5551:
+                if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u) ||
+                    ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u))
+                {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC5_GR_FORMAT_RGB888:
+                if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u) ||
+                    ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u))
+                {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC5_GR_FORMAT_CLUT8:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u)
+                {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC5_GR_FORMAT_CLUT4:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u)
+                {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC5_GR_FORMAT_CLUT1:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00000001) != 0u)
+                {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            default:
+                /* DO NOTHING */
+            break;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChromakeyCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on CLUT setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CLUTCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_clut_t   * const param)
+{
+    vdc5_error_t        error;
+    vdc5_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* The number of colors in CLUT */
+    if (param->color_num == 0u)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(graphics_id);
+    if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1)
+    {   /* CLUT1 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT1_NUM)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else if (gr_format_tmp == VDC5_GR_FORMAT_CLUT4)
+    {   /* CLUT4 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT4_NUM)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else
+    {   /* CLUT8 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT8_NUM)
+        {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* Address of the area storing the CLUT data (in ARGB8888 format) */
+    if (param->clut == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_CLUTCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display calibration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayCalibrationCheckPrm (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_calibr_bright_t    * bright_tmp;
+    const vdc5_calibr_dither_t    * panel_dither_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL)
+    {
+        /* Brightness (DC) adjustment of G signal */
+        if (((uint32_t)bright_tmp->pbrt_g & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of B signal */
+        if (((uint32_t)bright_tmp->pbrt_b & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of R signal */
+        if (((uint32_t)bright_tmp->pbrt_r & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u)
+        {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL)
+    {
+        /* Panel dither operation mode */
+        if (panel_dither_tmp->pdth_sel >= VDC5_PDTH_MD_NUM)
+        {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2)
+        {   /* Pattern value (A)-(D) of 2x2 pattern dither */
+            if (((uint32_t)panel_dither_tmp->pdth_pa & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pb & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pc & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pd & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_DisplayCalibrationCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on gamma correction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_GammaCorrectionCheckPrm (const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK)
+    {
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        /* Gain adjustment of area 0 to 31 of G signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_g_gain);
+        if (error != VDC5_OK)
+        {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of B signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_b_gain);
+        if (error != VDC5_OK)
+        {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of R signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_r_gain);
+        if (error != VDC5_OK)
+        {
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_GammaCorrectionCheckPrm() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Checks on VDC5 channel
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckChannel (const vdc5_channel_t ch)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if (ch >= VDC5_CHANNEL_NUM)
+    {
+        error = VDC5_ERR_PARAM_CHANNEL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckChannel() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckLayerId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if ((layer_id < VDC5_LAYER_ID_ALL) || (layer_id >= VDC5_LAYER_ID_NUM))
+    {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID related to graphics
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckGraphicsTypeLayerId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if ((layer_id != VDC5_LAYER_ID_0_RD) && (layer_id != VDC5_LAYER_ID_2_RD) && (layer_id != VDC5_LAYER_ID_3_RD))
+    {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckGraphicsTypeLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on horizontal/vertical timing of the VDC5 signals
+ * @param[in]   rect            : Horizontal/vertical timing of the VDC5 signals
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckRect (const vdc5_period_rect_t * const rect)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Vertical start position */
+    if (((uint32_t)rect->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->vs < (uint32_t)VDC5_CPARA_VS_MIN)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Height (vertical width) */
+    if (((uint32_t)rect->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->vs + (uint32_t)rect->vw) > (uint32_t)VDC5_CPARA_VS_VW_MAX)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+
+    /* Horizontal start position */
+    if (((uint32_t)rect->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->hs < (uint32_t)VDC5_CPARA_HS_MIN)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Horizontal width */
+    if (((uint32_t)rect->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->hs + (uint32_t)rect->hw) > (uint32_t)VDC5_CPARA_HS_HW_MAX)
+    {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckRect() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Horizontal (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM))
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Horizontal() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal (POLA/POLB)
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_HorizontalPol (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* POLA/POLB signal generation mode select */
+    if (lcd_tcon_timing->tcon_md >= VDC5_LCD_TCON_POLMD_NUM)
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM))
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_HorizontalPol() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for vertical panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Vertical (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM))
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Vertical() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for DE timing signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_DataEnable (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM))
+    {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_DataEnable() */
+
+/**************************************************************************//**
+ * @brief       Checks on gain adjustment of area 0 to 31 of G/B/R signal
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31 of G/B/R signal
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckGammaCrct_GainAdjustment (const uint16_t * gam_gain)
+{
+    uint32_t        gain_index;
+    vdc5_error_t    error;
+
+    error = VDC5_OK;
+
+    if (gam_gain != NULL)
+    {
+        for (gain_index = 0; gain_index < VDC5_GAM_GAIN_ADJ_NUM; gain_index++)
+        {
+            if (((uint32_t)*gam_gain & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            gam_gain++;
+        }
+    }
+END:
+    return error;
+}   /* End of function CheckGammaCrct_GainAdjustment() */
+
+#endif      /* R_VDC5_CHECK_PARAMETERS */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_check_parameter.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,122 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_check_parameter.h
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver parameter check definitions
+******************************************************************************/
+
+#ifndef R_VDC5_CHECK_PARAMETER_H
+#define R_VDC5_CHECK_PARAMETER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+#ifdef      R_VDC5_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdc5_error_t VDC5_InitializeCheckPrm(const vdc5_channel_t ch, const vdc5_init_t * const param);
+vdc5_error_t VDC5_TerminateCheckPrm(const vdc5_channel_t ch);
+vdc5_error_t VDC5_VideoInputCheckPrm(const vdc5_channel_t ch, const vdc5_input_t * const param);
+vdc5_error_t VDC5_SyncControlCheckPrm(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+vdc5_error_t VDC5_DisplayOutputCheckPrm(const vdc5_channel_t ch, const vdc5_output_t * const param);
+vdc5_error_t VDC5_CallbackISRCheckPrm(const vdc5_channel_t ch, const vdc5_int_t * const param);
+vdc5_error_t VDC5_WriteDataControlCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param);
+vdc5_error_t VDC5_ChangeWriteProcessCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t  * const param);
+vdc5_error_t VDC5_ReadDataControlCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param);
+vdc5_error_t VDC5_ChangeReadProcessCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param);
+vdc5_error_t VDC5_StartProcessCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param);
+vdc5_error_t VDC5_StopProcessCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t VDC5_ReleaseDataControlCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t VDC5_VideoNoiseReductCheckPrm(const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param);
+vdc5_error_t VDC5_ImageColorMatrixCheckPrm(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+vdc5_error_t VDC5_ImageEnhancementCheckPrm(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_period_rect_t    * const enh_area);
+vdc5_error_t VDC5_ImageBlackStretchCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_black_t  * const param);
+vdc5_error_t VDC5_AlphaBlendingCheckPrm(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param);
+vdc5_error_t VDC5_AlphaBlendingRectCheckPrm(
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_alpha_blending_rect_t    * const param);
+vdc5_error_t VDC5_ChromakeyCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_chromakey_t  * const param);
+vdc5_error_t VDC5_CLUTCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_clut_t   * const param);
+vdc5_error_t VDC5_DisplayCalibrationCheckPrm(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+vdc5_error_t VDC5_GammaCorrectionCheckPrm(const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param);
+
+
+#endif      /* R_VDC5_CHECK_PARAMETERS */
+
+#endif  /* R_VDC5_CHECK_PARAMETER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_interrupt.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,536 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_interrupt.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver interrupt related processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     UNUSED_PARAM(param)             (void)(param)
+
+#define VDC5_INT_BIT_S0_VI_VSYNC    ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_LO_VSYNC    ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_S0_VSYNCERR    ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_VLINE          ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_S0_VFIELD      ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_IV1_VBUFERR    ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV3_VBUFERR    ((uint32_t)0x01000000u)
+#define VDC5_INT_BIT_IV5_VBUFERR    ((uint32_t)0x10000000u)
+#define VDC5_INT_BIT_IV6_VBUFERR    ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_WLINE       ((uint32_t)0x00000010u)
+
+#define VDC5_GR_UPDATE_P_VEN_BIT    ((uint32_t)0x00000010u)
+#define VDC5_SCL0_UPDATE_VEN_A_BIT  ((uint32_t)0x00000001u)
+
+/* Valid bit range */
+#define VDC5_INT_RANGE_0X000007FF   (0x000007FFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_wline_ISR(const uint32_t int_sense);
+
+/*! List of the callback function pointers */
+static void (*vdc5_int_callback[VDC5_INT_TYPE_NUM])(vdc5_int_type_t int_type);
+
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ *              It returns a '0' if the channel specified in ch or the interrupt type specified in type
+ *              is found invalid.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC5_CHANNEL_0
+ * @param[in]   type                    : VDC5 interrupt type
+ * @retval      VDC5 Interrupt service routine
+ *****************************************************************************/
+void (*R_VDC5_GetISR (const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense)
+{
+    static void (* const isr_table[VDC5_INT_TYPE_NUM])(const uint32_t int_sense) =
+    {
+        &VDC5_Ch0_s0_vi_vsync_ISR,
+        &VDC5_Ch0_s0_lo_vsync_ISR,
+        &VDC5_Ch0_s0_vsyncerr_ISR,
+        &VDC5_Ch0_vline_ISR,
+        &VDC5_Ch0_s0_vfield_ISR,
+        &VDC5_Ch0_iv1_vbuferr_ISR,
+        &VDC5_Ch0_iv3_vbuferr_ISR,
+        &VDC5_Ch0_iv5_vbuferr_ISR,
+        &VDC5_Ch0_iv6_vbuferr_ISR,
+        &VDC5_Ch0_s0_wline_ISR
+    };
+    void (* isr_function)(const uint32_t int_sense);
+
+    isr_function = isr_table[type];
+
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    /* Channel and interrupt type */
+    if ((ch >= VDC5_CHANNEL_NUM) || (type >= VDC5_INT_TYPE_NUM))
+    {
+        isr_function = 0;
+    }
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+
+     return isr_function;
+}   /* End of function R_VDC5_GetISR() */
+
+/**************************************************************************//**
+ * @brief       Disables all VDC5 interrupts
+ * @param[in]   void
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Int_Disable (void)
+{
+    const vdc5_regaddr_system_ctrl_t  * system_ctrl;
+    int32_t                             int_type;
+
+    system_ctrl = &vdc5_regaddr_system_ctrl;
+
+    for (int_type = 0; int_type < VDC5_INT_TYPE_NUM; int_type++)
+    {
+        vdc5_int_callback[int_type] = 0;
+    }
+    /* Interrupt output off */
+    *(system_ctrl->syscnt_int4) = 0u;
+    *(system_ctrl->syscnt_int5) = 0u;
+
+}   /* End of function VDC5_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief       Enables/disables the specified VDC5 interrupt
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Int_SetInterrupt (const vdc5_int_t * const param)
+{
+    volatile uint32_t     * int_clhd_reg;
+    volatile uint32_t     * int_onoff_reg;
+    volatile uint32_t     * linenum_reg;
+    volatile uint16_t     * linenum16_reg;
+    volatile uint32_t     * linenum_update_reg;
+    uint32_t                mask_bit;
+    uint32_t                reg_data;
+    static const uint32_t   interrupt_bit_table[VDC5_INT_TYPE_NUM] =
+    {
+        VDC5_INT_BIT_S0_VI_VSYNC,
+        VDC5_INT_BIT_S0_LO_VSYNC,
+        VDC5_INT_BIT_S0_VSYNCERR,
+        VDC5_INT_BIT_VLINE,
+        VDC5_INT_BIT_S0_VFIELD,
+        VDC5_INT_BIT_IV1_VBUFERR,
+        VDC5_INT_BIT_IV3_VBUFERR,
+        VDC5_INT_BIT_IV5_VBUFERR,
+        VDC5_INT_BIT_IV6_VBUFERR,
+        VDC5_INT_BIT_S0_WLINE
+    };
+
+    if (param->type < VDC5_INT_TYPE_IV6_VBUFERR)
+    {   /* INT0: VDC5_INT_TYPE_S0_VI_VSYNC ~ INT7: VDC5_INT_TYPE_IV5_VBUFERR */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+        int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    }
+    else
+    {   /* INT8: VDC5_INT_TYPE_IV6_VBUFERR ~ INT9: VDC5_INT_TYPE_S0_WLINE */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int2;
+        int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int5;
+    }
+    mask_bit = interrupt_bit_table[param->type];
+
+    /* Interrupt callback function pointer */
+    vdc5_int_callback[param->type] = param->callback;
+
+    if (param->callback != 0)
+    {   /* ON */
+        if ((*int_onoff_reg & mask_bit) == 0u)
+        {   /* OFF to ON */
+            *int_onoff_reg |= mask_bit;
+            reg_data        = *int_onoff_reg;
+            *int_clhd_reg   = reg_data;
+        }
+
+        if (param->type == VDC5_INT_TYPE_VLINE)
+        {   /* Specified line signal for panel output in graphics 3 */
+            linenum_reg         = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR3].gr_clut;
+            linenum_update_reg  = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR3].gr_update;
+            *linenum_reg        &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
+            *linenum_reg        |= (uint32_t)param->line_num;
+            *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
+        }
+        else if (param->type == VDC5_INT_TYPE_S0_WLINE)
+        {   /* Write specification line signal input to scaling-down control block in scaler 0 */
+            linenum16_reg       = vdc5_regaddr_scaler.scl0_int;
+            linenum_update_reg  = vdc5_regaddr_scaler.scl0_update;
+            *linenum16_reg       = param->line_num;
+            *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
+        }
+        else
+        {   /* Do nothing */
+        }
+    }
+    else
+    {   /* OFF */
+        *int_onoff_reg &= (uint32_t)~mask_bit;
+        reg_data        = *int_onoff_reg;
+        *int_clhd_reg   = reg_data;
+    }
+
+}   /* End of function VDC5_Int_SetInterrupt() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_S0_VI_VSYNC] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_S0_LO_VSYNC] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_S0_VSYNCERR] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_VLINE] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_S0_VFIELD] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV1_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_IV1_VBUFERR] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV3_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_IV3_VBUFERR] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV5_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_IV5_VBUFERR] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV6_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_IV6_VBUFERR] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl.syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl.syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
+
+        if (vdc5_int_callback[VDC5_INT_TYPE_S0_WLINE] != 0)
+        {
+            vdc5_int_callback[VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_wline_ISR() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_register.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,3166 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+#include    "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     INITIAL_SCALING_PHASE          ((uint32_t)2048u)
+#define     SCALING_RATIO_SAME_SIZE        (4096u)
+/* Vsync signal delay control for OIR */
+#define     OIR_VSYNC_DELAY                 ((uint32_t)1u)
+
+/* Panel clock frequency division ratio */
+#define     VDC5_REG_CLKDIV_1_1            (1u)
+#define     VDC5_REG_CLKDIV_1_2            (2u)
+#define     VDC5_REG_CLKDIV_1_3            (3u)
+#define     VDC5_REG_CLKDIV_1_4            (4u)
+#define     VDC5_REG_CLKDIV_1_5            (5u)
+#define     VDC5_REG_CLKDIV_1_6            (6u)
+#define     VDC5_REG_CLKDIV_1_7            (7u)
+#define     VDC5_REG_CLKDIV_1_8            (8u)
+#define     VDC5_REG_CLKDIV_1_9            (9u)
+#define     VDC5_REG_CLKDIV_1_12           (12u)
+#define     VDC5_REG_CLKDIV_1_16           (16u)
+#define     VDC5_REG_CLKDIV_1_24           (24u)
+#define     VDC5_REG_CLKDIV_1_32           (32u)
+/* Panel clock select */
+#define     VDC5_REG_ICKSEL_IMG_DV         (0x0000u)
+#define     VDC5_REG_ICKSEL_EXT_0          (0x1000u)
+#define     VDC5_REG_ICKSEL_PERI           (0x3000u)
+/* Output pin edge select */
+#define     VDC5_REG_TCON0_EDGE            (0x0040u)
+#define     VDC5_REG_TCON1_EDGE            (0x0020u)
+#define     VDC5_REG_TCON2_EDGE            (0x0010u)
+#define     VDC5_REG_TCON3_EDGE            (0x0008u)
+#define     VDC5_REG_TCON4_EDGE            (0x0004u)
+#define     VDC5_REG_TCON5_EDGE            (0x0002u)
+#define     VDC5_REG_TCON6_EDGE            (0x0001u)
+/* Panel dither output format select */
+#define     VDC5_REG_PATH_FORMAT_RGB888    (0x00000000u)
+#define     VDC5_REG_PATH_FORMAT_RGB666    (0x00010000u)
+#define     VDC5_REG_PATH_FORMAT_RGB565    (0x00020000u)
+#define     VDC5_REG_PATH_FORMAT_NON       (0x00000000u)
+/* Calculate scaling ratio use value */
+#define     VDC5_REG_FLOAT_1_0 (1.0f)
+#define     VDC5_REG_FLOAT_0_5 (0.5f)
+/* bits per pixel */
+#define     VDC5_REG_BIT_PER_PIXEL_RGB565    (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGB888    (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB1555  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB4444  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB8888  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT8     (8u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT4     (4u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT1     (1u)
+#define     VDC5_REG_BIT_PER_PIXEL_YCBCR422  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_YCBCR444  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGBA5551  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGBA8888  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_VALUE_8   (8u)
+/* Convert the color data from 4 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_17      (17u)
+/* Convert the color data from 5 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_263     (263u)
+#define     VDC5_REG_EXTENSION_VALUE_32      (32u)
+/* Convert the color data from 6 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_259     (259u)
+#define     VDC5_REG_EXTENSION_VALUE_64      (64u)
+/* Round off */
+#define     VDC5_REG_ROUND_OFF_VALUE_1       (1u)
+#define     VDC5_REG_ROUND_OFF_VALUE_2       (2u)
+/* Color mask data */
+#define     VDC5_REG_ALPHA_8BIT              (0xFF000000u)
+#define     VDC5_REG_RGB_24BIT_MASK          (0x00FFFFFFu)
+#define     VDC5_REG_COLOR_8BIT_MASK         (0x000000FFu)
+#define     VDC5_REG_COLOR_6BIT_MASK         (0x0000003Fu)
+#define     VDC5_REG_COLOR_5BIT_MASK         (0x0000001Fu)
+#define     VDC5_REG_COLOR_4BIT_MASK         (0x0000000Fu)
+#define     VDC5_REG_ARGB8888_GB_MASK        (0x00FFFF00u)
+
+/* RGB565 bits mask data */
+#define     VDC5_REG_RGB565_R_MASK           (0x0000F800u)
+#define     VDC5_REG_RGB565_G_MASK           (0x000007E0u)
+#define     VDC5_REG_RGB565_B_MASK           (0x0000001Fu)
+/* ARGB4444 bits mask data */
+#define     VDC5_REG_ARGB4444_R_MASK         (0x00000F00u)
+#define     VDC5_REG_ARGB4444_G_MASK         (0x000000F0u)
+#define     VDC5_REG_ARGB4444_B_MASK         (0x0000000Fu)
+/* ARGB1555 bits mask data */
+#define     VDC5_REG_ARGB1555_R_MASK         (0x00007C00u)
+#define     VDC5_REG_ARGB1555_G_MASK         (0x000003E0u)
+#define     VDC5_REG_ARGB1555_B_MASK         (0x0000001Fu)
+/* RGBA5551 bits mask data */
+#define     VDC5_REG_RGBA5551_R_MASK         (0x0000F800u)
+#define     VDC5_REG_RGBA5551_G_MASK         (0x000007C0u)
+#define     VDC5_REG_RGBA5551_B_MASK         (0x0000003Eu)
+
+/* bit pattern */
+#define     VDC5_REG_BIT31          (0x80000000u)
+#define     VDC5_REG_BIT29          (0x20000000u)
+#define     VDC5_REG_BIT28          (0x10000000u)
+#define     VDC5_REG_BIT24          (0x01000000u)
+#define     VDC5_REG_BIT20          (0x00100000u)
+#define     VDC5_REG_BIT16          (0x00010000u)
+#define     VDC5_REG_BIT15          (0x00008000u)
+#define     VDC5_REG_BIT14          (0x00004000u)
+#define     VDC5_REG_BIT13          (0x00002000u)
+#define     VDC5_REG_BIT12          (0x00001000u)
+#define     VDC5_REG_BIT8           (0x00000100u)
+#define     VDC5_REG_BIT4           (0x00000010u)
+#define     VDC5_REG_BIT2           (0x00000004u)
+#define     VDC5_REG_BIT1           (0x00000002u)
+#define     VDC5_REG_BIT0           (0x00000001u)
+
+/* shift value */
+#define     VDC5_REG_SHIFT_28       (28u)
+#define     VDC5_REG_SHIFT_24       (24u)
+#define     VDC5_REG_SHIFT_20       (20u)
+#define     VDC5_REG_SHIFT_16       (16u)
+#define     VDC5_REG_SHIFT_13       (13u)
+#define     VDC5_REG_SHIFT_12       (12u)
+#define     VDC5_REG_SHIFT_11       (11u)
+#define     VDC5_REG_SHIFT_10       (10u)
+#define     VDC5_REG_SHIFT_8        (8u)
+#define     VDC5_REG_SHIFT_6        (6u)
+#define     VDC5_REG_SHIFT_5        (5u)
+#define     VDC5_REG_SHIFT_4        (4u)
+#define     VDC5_REG_SHIFT_2        (2u)
+#define     VDC5_REG_SHIFT_1        (1u)
+
+/* register set value */
+#define VDC5_REG_BIT_0XFFFF0000     (0xFFFF0000u) /* scaler_0->scl0_frc2                     */
+/* register mask value */
+#define VDC5_REG_MASK_0XF7FF1C3F    (0xF7FF1C3Fu) /* mask img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X0000D000    (0x0000D000u) /* mask img_synthesizer->gr_ab1            */
+#define VDC5_REG_MASK_0X01FF00FF    (0x01FF00FFu) /* mask img_synthesizer->gr_ab6            */
+#define VDC5_REG_MASK_0X0000007F    (0x0000007Fu) /* mask output_ctrl->out_clk_phase         */
+#define VDC5_REG_MASK_0X11003313    (0x11003313u) /* mask output_ctrl->out_set               */
+#define VDC5_REG_MASK_0X00030000    (0x00030000u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X0007000D    (0x0007000Du) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00000300    (0x00000300u) /* mask scaler->scl1_wr5                   */
+#define VDC5_REG_MASK_0X0703FF02    (0x0703FF02u) /* mask regaddr_lvds->lclkselr             */
+#define VDC5_REG_MASK_0X07FF1F30    (0x07FF1F30u) /* mask regaddr_lvds->lpllsetr             */
+#define VDC5_REG_MASK_0X00010301    (0x00010301u) /* mask img_synthesizer->gr_flm1           */
+#define VDC5_REG_MASK_0X7FFF03FF    (0x7FFF03FFu) /* mask img_synthesizer->gr_flm3           */
+#define VDC5_REG_MASK_0X0000E000    (0x0000E000u) /* mask img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X00007F33    (0x00007F33u) /* mask input_ctrl->imgcnt_nr_cnt0         */
+#define VDC5_REG_MASK_0X00FF0000    (0x00FF0000u) /* mask img_synthesizer->gr_ab7            */
+#define VDC5_REG_MASK_0X00300000    (0x00300000u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X00003333    (0x00003333u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X00007111    (0x00007111u) /* mask input_ctrl->inp_sel_cnt            */
+#define VDC5_REG_MASK_0X11110113    (0x11110113u) /* mask input_ctrl->inp_ext_sync_cnt       */
+#define VDC5_REG_MASK_0X000007FF    (0x000007FFu) /* mask img_synthesizer->gr_flm5           */
+#define VDC5_REG_MASK_0X0000FFFF    (0x0000FFFFu) /* mask scaler->scl0_ds4                   */
+                                                  /*      caler->scl0_us5                    */
+#define VDC5_REG_MASK_0X00000011    (0x00000011u) /* mask scaler->scl0_ds1                   */
+                                                  /*      scaler->scl0_us1                   */
+#define VDC5_REG_MASK_0X00000070    (0x00000070u) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00000080    (0x00000080u) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00003110    (0x00003110u) /* mask output_ctrl->tcon_tim_pola2        */
+                                                  /*      output_ctrl->tcon_tim_polb2        */
+#define VDC5_REG_MASK_0X000000FF    (0x000000FFu) /* mask scaler_0->scl0_frc5                */
+#define VDC5_REG_MASK_0X0000003F    (0x0000003Fu) /* mask img_synthesizer->gr_flm6           */
+                                                  /*      img_qlty_imp->adj_enh_shp1         */
+#define VDC5_REG_MASK_0XFF000000    (0xFF000000u) /* mask img_synthesizer->gr_ab10           */
+                                                  /*      img_synthesizer->gr_ab11           */
+#define VDC5_REG_MASK_0X00000110    (0x00000110u) /* mask output_ctrl->tcon_tim_sth2         */
+                                                  /*      output_ctrl->tcon_tim_stb2         */
+                                                  /*      output_ctrl->tcon_tim_cpv2         */
+#define VDC5_REG_MASK_0X00000007    (0x00000007u) /* mask *(output_pin_regaddr[tcon_pin])    */
+                                                  /*      img_synthesizer->gr_flm2           */
+                                                  /*      img_synthesizer->gr_flm2           */
+#define VDC5_REG_MASK_0X07FF0000    (0x07FF0000u) /* mask scaler_0->scl0_frc4                */
+                                                  /*      img_synthesizer->gr_flm5           */
+                                                  /*      img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X0FFF0FFF    (0x0FFF0FFFu) /* mask                                    */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+#define VDC5_REG_MASK_0X00000003    (0x00000003u) /* mask img_synthesizer->gr_ab1            */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void SetVideoExternalInput(
+    const vdc5_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc5_regaddr_input_ctrl_t * const input_ctrl);
+static void SetInitialConnection(void);
+static void SetGrapicsBackgroundColor(void);
+static void SetScalerBackgroundColor(const vdc5_color_space_t color_space);
+static void SetLcdTcon_STVA_VS(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STVB_VE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STH_HS(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STB_HE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_CPV_GCK(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLA(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLB(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_DE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetScalingDown(
+    const vdc5_scalingdown_rot_t    * const scldw_rot,
+    const vdc5_res_inter_t                  res_inter,
+    const vdc5_regaddr_scaler_t     * const scaler);
+static void SetScalingUp(
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_onoff_t                  adj_sel,
+    const vdc5_onoff_t                  ip_conversion,
+    const vdc5_wr_md_t                  res_ds_wr_md,
+    const vdc5_gr_ln_off_dir_t          ln_off_dir,
+    const vdc5_regaddr_scaler_t * const scaler);
+static uint32_t CalcScalingRatio(
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc5_onoff_t  adj_sel,
+    const vdc5_onoff_t  round_up);
+static void SetInputCntrlColorMtx(void);
+static vdc5_onoff_t ConfirmGraphicsEnlargement(
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc);
+static void SetScalerGraphics(
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_onoff_t                  gr_enlarge);
+static uint32_t DisplayStartPixelSetting(const uint32_t gr_base, const vdc5_gr_format_t gr_format);
+static void SetImgQaImproverColorMtx(const vdc5_color_space_t color_space);
+
+static void SetRwProcAbility_Write_0(const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_0(const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_2(const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_3(const vdc5_onoff_t ability);
+static void SetRegUpdateRwEnable(const vdc5_layer_id_t layer_id);
+
+static void SetGraphicsDisplayMode(const vdc5_layer_id_t layer_id, const vdc5_gr_disp_sel_t * const gr_disp_sel);
+static void SetColorMatrix(
+    const vdc5_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc5_regaddr_color_matrix_t   * const color_matrix);
+static void SetImageEnhancementSharpness(
+    const vdc5_onoff_t                          shp_h_on,
+    const vdc5_enhance_sharp_t          * const sharp_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetImageEnhancementLti(
+    const vdc5_onoff_t                          lti_h_on,
+    const vdc5_enhance_lti_t            * const lti_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetAlphaRectArea(
+    const vdc5_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc5_regaddr_img_synthesizer_t    * const img_synthesizer);
+static uint32_t ColorConversion(const vdc5_gr_format_t gr_format, const uint32_t input_color);
+static uint32_t ColorConversionFrom4to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom5to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom6to8(const uint32_t color_value);
+static uint32_t ColorConversionIntoAgbr(const uint32_t color_value);
+static void Set_Clut(const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut);
+static void Set_StartThreshold_Gamma(const uint8_t * gam_th, volatile uint32_t * const * const gam_area);
+static void Set_GainAdjustment_Gamma(const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut);
+
+/*! Color matrix offset (DC) adjustment (YG, B, and R) */
+static const uint16_t colormtx_offset_adj[VDC5_COLORMTX_OFFST_NUM] =
+{
+    (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET
+};
+/*! Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+static const uint16_t colormtx_gain_adj[VDC5_COLORMTX_MODE_NUM][VDC5_COLORMTX_GAIN_NUM] =
+{
+    {   /* GBR to GBR */
+        (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+    },
+    {   /* GBR to YCbCr */
+        (uint16_t)VDC5_COLORCONV_Y_G,  (uint16_t)VDC5_COLORCONV_Y_B,  (uint16_t)VDC5_COLORCONV_Y_R,
+        (uint16_t)VDC5_COLORCONV_CB_G, (uint16_t)VDC5_COLORCONV_CB_B, (uint16_t)VDC5_COLORCONV_CB_R,
+        (uint16_t)VDC5_COLORCONV_CR_G, (uint16_t)VDC5_COLORCONV_CR_B, (uint16_t)VDC5_COLORCONV_CR_R
+    },
+    {   /* YCbCr to GBR */
+        (uint16_t)VDC5_COLORCONV_G_Y, (uint16_t)VDC5_COLORCONV_G_CB, (uint16_t)VDC5_COLORCONV_G_CR,
+        (uint16_t)VDC5_COLORCONV_B_Y, (uint16_t)VDC5_COLORCONV_B_CB, (uint16_t)VDC5_COLORCONV_B_CR,
+        (uint16_t)VDC5_COLORCONV_R_Y, (uint16_t)VDC5_COLORCONV_R_CB, (uint16_t)VDC5_COLORCONV_R_CR
+    },
+    {   /* YCbCr to YCbCr */
+        (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+    }
+};
+
+static void (* const rw_proc_function_tbl[VDC5_LAYER_ID_NUM])(const vdc5_onoff_t ability) =
+{
+    &SetRwProcAbility_Write_0,          /* Write scaler 0 */
+    &SetRwProcAbility_Read_0,           /* Read graphics 0 */
+    &SetRwProcAbility_Read_2,           /* Read graphics 2 */
+    &SetRwProcAbility_Read_3            /* Read graphics 3 */
+};
+
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Initialize (const vdc5_init_t * const param)
+{
+    uint16_t                    syscnt_panel_clk_tmp;
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    volatile uint32_t         * inp_sel_cnt_reg;
+    static const uint16_t       panel_dcdr_tbl[VDC5_PANEL_CLKDIV_NUM] =
+    {   /* Panel clock frequency division ratio */
+        (uint16_t)VDC5_REG_CLKDIV_1_1,  (uint16_t)VDC5_REG_CLKDIV_1_2,
+        (uint16_t)VDC5_REG_CLKDIV_1_3,  (uint16_t)VDC5_REG_CLKDIV_1_4,
+        (uint16_t)VDC5_REG_CLKDIV_1_5,  (uint16_t)VDC5_REG_CLKDIV_1_6,
+        (uint16_t)VDC5_REG_CLKDIV_1_7,  (uint16_t)VDC5_REG_CLKDIV_1_8,
+        (uint16_t)VDC5_REG_CLKDIV_1_9,  (uint16_t)VDC5_REG_CLKDIV_1_12,
+        (uint16_t)VDC5_REG_CLKDIV_1_16, (uint16_t)VDC5_REG_CLKDIV_1_24,
+        (uint16_t)VDC5_REG_CLKDIV_1_32
+    };
+    static const uint16_t       panel_icksel_tbl[VDC5_PANEL_ICKSEL_NUM] =
+    {   /* Panel clock select */
+        (uint16_t)VDC5_REG_ICKSEL_IMG_DV, (uint16_t)VDC5_REG_ICKSEL_EXT_0, (uint16_t)VDC5_REG_ICKSEL_PERI
+    };
+
+    syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl.syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+    inp_sel_cnt_reg = vdc5_regaddr_input_ctrl.inp_sel_cnt;
+    /* Input select */
+    if (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV)
+    {
+        *inp_sel_cnt_reg |= (uint32_t)VDC5_REG_BIT20;
+    }
+    else
+    {
+        *inp_sel_cnt_reg &= (uint32_t)~VDC5_REG_BIT20;
+    }
+    syscnt_panel_clk_tmp    = panel_dcdr_tbl[param->panel_dcdr];
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp |
+                                        (uint32_t)panel_icksel_tbl[param->panel_icksel]);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+    /* Enable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp | VDC5_REG_BIT8);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+}   /* End of function VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for termination
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void VDC5_Terminate (void)
+{
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    uint16_t                    syscnt_panel_clk_tmp;
+
+    syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl.syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+}   /* End of function VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for video input
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_VideoInput (const vdc5_input_t * const param)
+{
+    const vdc5_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc5_sync_delay_t           * dly_tmp;
+    const vdc5_ext_in_sig_t           * ext_sig_tmp;
+
+    input_ctrl = &vdc5_regaddr_input_ctrl;
+
+    /* Input select */
+    *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT20;
+    /* Vsync signal 1/2fH and 1/4fH phase timing */
+    *(input_ctrl->inp_vsync_ph_adj)  = (uint32_t)param->inp_fh50 << VDC5_REG_SHIFT_16;
+    *(input_ctrl->inp_vsync_ph_adj) |= (uint32_t)param->inp_fh25;
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL)
+    {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        *(input_ctrl->inp_dly_adj)  = (uint32_t)dly_tmp->inp_vs_dly_l << VDC5_REG_SHIFT_24;
+        /* Field differentiation signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_fld_dly << VDC5_REG_SHIFT_16;
+        /* Vsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_vs_dly << VDC5_REG_SHIFT_8;
+        /* Hsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_hs_dly;
+    }
+
+    /* Horizontal noise reduction operating mode, Y/Cb/Cr mode */
+    *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT20;
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp != NULL)
+    {
+        /* Setting external input video signal */
+        SetVideoExternalInput(ext_sig_tmp, input_ctrl);
+
+        /* Horizontal noise reduction operating mode, G/B/R mode */
+        if ((ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+            (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+            (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB565))
+        {
+            *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT20;
+        }
+    }
+
+    /* Register update control register (INP_UPDATE)
+       b4       INP_EXT_UPDATE
+       b0       INP_IMG_UPDATE */
+    *(input_ctrl->inp_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+}   /* End of function VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for sync control
+ * @param[in]   param                   : Sync signal control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_SyncControl (const vdc5_sync_ctrl_t * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler_0;
+    uint32_t                        full_scr;
+
+    scaler_0    = &vdc5_regaddr_scaler;
+
+    if (param->vsync_cpmpe != NULL)
+    {
+        /* Frequent Vsync signal masking period */
+        *(scaler_0->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
+        /* Missing-Sync compensating pulse output wait time */
+        *(scaler_0->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
+        /* Frequent Vsync signal masking and missing Vsync signal compensation */
+        *(scaler_0->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
+    }
+    else
+    {   /* Frequent Vsync signal masking and missing Vsync signal compensation are disabled, if unnecessary. */
+        *(scaler_0->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
+    }
+
+    /* Hsync period setting and free-running Vsync period initialization */
+    *(scaler_0->scl0_frc4)      = (uint32_t)param->res_fh;
+    /* Vsync signal output select (free-running Vsync on/off control) */
+    if (param->res_vs_sel == VDC5_OFF)
+    {
+        *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+    else
+    {
+        *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(scaler_0->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
+    }
+
+    /* Sync signal output and full-screen enable signal select: Scaler 0 */
+    *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+
+    /* Vsync signal delay control */
+    *(scaler_0->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+    *(scaler_0->scl0_frc5) |= (uint32_t)param->res_vsdly;
+
+    /* Full-screen enable signal */
+    full_scr  = (uint32_t)param->res_f.vs << VDC5_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.vw;
+
+    *(scaler_0->scl0_frc6)   = full_scr;
+
+    full_scr  = (uint32_t)param->res_f.hs << VDC5_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.hw;
+
+    *(scaler_0->scl0_frc7)   = full_scr;
+
+    /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+       b8       SCL0_UPDATE
+       b4       SCL0_VEN_B */
+    *(scaler_0->scl0_update)   |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+    SetInitialConnection();
+}   /* End of function VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display output
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_DisplayOutput (const vdc5_output_t * const param)
+{
+    const vdc5_regaddr_output_ctrl_t      * output_ctrl;
+    volatile uint32_t                     * output_pin_regaddr[VDC5_LCD_TCON_PIN_NUM];
+    uint32_t                                tcon_sig_index;
+    const vdc5_lcd_tcon_timing_t  * const * lcd_tcon_timing;
+    static void                    (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+        const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+        const vdc5_regaddr_output_ctrl_t    * const output_ctrl) =
+    {
+        &SetLcdTcon_STVA_VS,    /* STVA/VS */
+        &SetLcdTcon_STVB_VE,    /* STVB/VE */
+        &SetLcdTcon_STH_HS,     /* STH_HS */
+        &SetLcdTcon_STB_HE,     /* STB_HE */
+        &SetLcdTcon_CPV_GCK,    /* CPV_GCK */
+        &SetLcdTcon_POLA,       /* POLA */
+        &SetLcdTcon_POLB,       /* POLB */
+        &SetLcdTcon_DE          /* DE */
+    };
+    const uint32_t                      output_pin_edge[VDC5_LCD_TCON_PIN_NUM] =
+    {
+       VDC5_REG_TCON0_EDGE, VDC5_REG_TCON1_EDGE, VDC5_REG_TCON2_EDGE, VDC5_REG_TCON3_EDGE,
+       VDC5_REG_TCON4_EDGE, VDC5_REG_TCON5_EDGE, VDC5_REG_TCON6_EDGE
+    };
+    vdc5_lcd_tcon_pin_t                 tcon_pin_tmp;
+    const vdc5_gr_disp_sel_t            gr_disp_sel_tbl[VDC5_GR_TYPE_NUM] =
+    {   /* Graphics display mode for initialization */
+        VDC5_DISPSEL_BACK,              /* Graphics 0 */
+        VDC5_DISPSEL_LOWER,             /* Graphics 2 */
+        VDC5_DISPSEL_LOWER              /* Graphics 3 */
+    };
+    const uint32_t                      dither_format[VDC5_LCD_OUTFORMAT_NUM] =
+    {   /* Panel dither output format select */
+        VDC5_REG_PATH_FORMAT_RGB888, VDC5_REG_PATH_FORMAT_RGB666,
+        VDC5_REG_PATH_FORMAT_RGB565, VDC5_REG_PATH_FORMAT_NON
+    };
+
+    output_ctrl = &vdc5_regaddr_output_ctrl;
+
+    /* 1/2fH timing */
+    *(output_ctrl->tcon_tim)  = (uint32_t)param->tcon_half << VDC5_REG_SHIFT_16;
+    /* Offset Hsync signal timing */
+    *(output_ctrl->tcon_tim) |= (uint32_t)param->tcon_offset;
+
+    /* Create output pin register address table */
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_0] = output_ctrl->tcon_tim_stva2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_1] = output_ctrl->tcon_tim_stvb2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_2] = output_ctrl->tcon_tim_sth2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_3] = output_ctrl->tcon_tim_stb2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_4] = output_ctrl->tcon_tim_cpv2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_5] = output_ctrl->tcon_tim_pola2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_6] = output_ctrl->tcon_tim_polb2;
+
+    /* Clear output phase control of LCT_TCON0~6 pin */
+    *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_MASK_0X0000007F;
+    /* LCD TCON */
+    lcd_tcon_timing = param->outctrl;
+    for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++)
+    {
+        if (*lcd_tcon_timing != NULL)
+        {
+            /* Setting LCD TCON */
+            tcon_function_tbl[tcon_sig_index](*lcd_tcon_timing, output_ctrl);
+
+            tcon_pin_tmp = (*lcd_tcon_timing)->tcon_pin;
+            if (tcon_pin_tmp != VDC5_LCD_TCON_PIN_NON)
+            {   /* LCD TCON output pin select */
+                *(output_pin_regaddr[tcon_pin_tmp]) &= (uint32_t)~VDC5_REG_MASK_0X00000007;
+                *(output_pin_regaddr[tcon_pin_tmp]) |= tcon_sig_index;
+                /* Output phase control of LCT_TCON pin */
+                if ((*lcd_tcon_timing)->outcnt_edge != VDC5_EDGE_RISING)
+                {
+                    *(output_ctrl->out_clk_phase) |= output_pin_edge[tcon_pin_tmp];
+                }
+            }
+        }
+        lcd_tcon_timing++;
+    }
+
+    *(output_ctrl->out_set) &= (uint32_t)~VDC5_REG_MASK_0X11003313;
+    /* Bit endian change ON/OFF control */
+    if (param->out_endian_on != VDC5_OFF)
+    {
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT28;
+    }
+    /* B/R signal swap ON/OFF control */
+    if (param->out_swap_on != VDC5_OFF)
+    {
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT24;
+    }
+    /* Output format select */
+    *(output_ctrl->out_set) |= (uint32_t)param->out_format << VDC5_REG_SHIFT_12;
+
+    /* Panel dither output format select */
+    *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00030000;
+    *(output_ctrl->out_pdtha) |= dither_format[param->out_format];
+
+    if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB)
+    {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_frq_sel << VDC5_REG_SHIFT_8;
+        /* Scan direction select */
+        if (param->out_dir_sel != VDC5_LCD_SERIAL_SCAN_FORWARD)
+        {
+            *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT4;
+        }
+        /* Clock phase adjustment */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_phase;
+    }
+    else
+    {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_LCD_PARALLEL_CLKFRQ_1 << VDC5_REG_SHIFT_8;
+    }
+
+    /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+    if (param->outcnt_lcd_edge == VDC5_EDGE_RISING)
+    {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT8;
+    }
+    else
+    {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT8;
+    }
+
+    /* Set background color */
+    SetGrapicsBackgroundColor();
+    /* Initialize graphics display mode */
+    SetGraphicsDisplayMode(VDC5_LAYER_ID_ALL, gr_disp_sel_tbl);
+
+    /* TCON register update control register (TCON_UPDATE)
+       b0       TCON_VEN */
+    *(output_ctrl->tcon_update) |= (uint32_t)VDC5_REG_BIT0;
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write control processing
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_WriteDataControl (const vdc5_write_t * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    const vdc5_scalingdown_rot_t  * scldw_rot;
+
+    scaler      = &vdc5_regaddr_scaler;
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X0007000D;
+    /* Swap setting in frame buffer writing */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_wrswa << VDC5_REG_SHIFT_16;
+    /* Frame buffer video-signal writing format */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_md << VDC5_REG_SHIFT_2;
+    /* Transfer burst length for frame buffer writing */
+    if (param->res_bst_md != VDC5_BST_MD_32BYTE)
+    {
+        *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    /* Frame buffer base address */
+    *(scaler->scl1_wr2) = (uint32_t)param->base;
+    /* Frame buffer line offset address[byte] */
+    *(scaler->scl1_wr3) = param->ln_off << VDC5_REG_SHIFT_16;
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    *(scaler->scl1_wr3) |= param->flm_num;
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u)
+    {
+        *(scaler->scl1_wr4) = param->flm_off;
+    }
+
+    /* Writing rate */
+    *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_MASK_0X00000300;
+    *(scaler->scl1_wr5) |= (uint32_t)param->res_fs_rate << VDC5_REG_SHIFT_8;
+
+    /* Dither correction on/off */
+    if (param->res_dth_on == VDC5_OFF)
+    {
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT4;
+    }
+    else
+    {
+        *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Bit Reduction */
+    if (param->res_md == VDC5_RES_MD_RGB565)
+    {   /* On */
+        *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT0;
+    }
+    else
+    {   /* Off */
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    /* Scaler 0 or 1 */
+    /* Field determination signal delay control */
+    if (param->flm_num == 0u)
+    {   /* Frame buffer: One plane */
+        *(scaler->scl0_frc5) &= (uint32_t)~VDC5_REG_BIT8;
+    }
+    else
+    {   /* Frame buffer: Two planes or more */
+        *(scaler->scl0_frc5) |= (uint32_t)VDC5_REG_BIT8;
+    }
+
+    /* Horizontal prefilter */
+    if (scldw_rot->res_pfil_sel == VDC5_OFF)
+    {
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+    }
+    else
+    {
+        *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+    /* Scaling-down */
+    SetScalingDown(scldw_rot, param->res_inter, scaler);
+
+    /* Frame buffer writing mode for image processing */
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+    *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+    /* Field operating mode select */
+    if (param->res_inter == VDC5_RES_INTER_PROGRESSIVE)
+    {   /* Progressive */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
+    }
+    else
+    {   /* Interlace */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT12;
+    }
+    /* Write field select */
+    if (param->res_fld_sel == VDC5_RES_FLD_SEL_TOP)
+    {   /* Top field */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT4;
+    }
+    else
+    {   /* Bottom field */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT4;
+    }
+
+    /* Frame buffer for bottom */
+    if (param->btm_base != NULL)
+    {
+        /* SC_RES_TB_ADD_MOD */
+        *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_MASK_0X00000080;
+
+        /* Frame buffer base address */
+        *(scaler->scl1_wr8) = (uint32_t)param->btm_base;
+        /* Frame buffer line offset address[byte] */
+        *(scaler->scl1_wr9)  = param->ln_off << VDC5_REG_SHIFT_16;
+        /* The number of frames of buffer (defined by res_flm_num + 1) */
+        *(scaler->scl1_wr9) |= param->flm_num;
+        /* Frame buffer frame offset address */
+        if (param->flm_num != 0u)
+        {
+            *(scaler->scl1_wr10) = param->flm_off;
+        }
+    }
+    else
+    {
+        /* SC_RES_TB_ADD_MOD */
+        *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000080;
+    }
+
+    /* Register update control register (SC0_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+    /* Register update control register (SC0_SCL1_UPDATE)
+       b16      SCL1_UPDATE_A
+       b4       SCL1_VEN_B
+       b0       SCL1_VEN_A */
+    *(scaler->scl1_update)   |= (uint32_t)(VDC5_REG_BIT16 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+    SetInputCntrlColorMtx();
+}   /* End of function VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write change processing
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ChangeWriteProcess (const vdc5_write_chg_t * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    const vdc5_scalingdown_rot_t  * scldw_rot;
+    vdc5_res_inter_t                res_inter_tmp;
+
+    scaler      = &vdc5_regaddr_scaler;
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    /* Horizontal prefilter */
+    if (scldw_rot->res_pfil_sel == VDC5_OFF)
+    {
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+    }
+    else
+    {
+        *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+    /* Progressive or interlace */
+    res_inter_tmp = VDC5_ShrdPrmGetInterlace();
+    /* Scaling-down */
+    SetScalingDown(scldw_rot, res_inter_tmp, scaler);
+
+    /* Frame buffer writing mode for image processing */
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+    *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+    /* Register update control register (SC0_SCL1_UPDATE)
+       b4       SCL1_VEN_B
+       b0       SCL1_VEN_A */
+    *(scaler->scl1_update)   |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+
+    /* Register update control register (SC0_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+}   /* End of function VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read control processing
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ReadDataControl (const vdc5_graphics_type_t graphics_id, const vdc5_read_t * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_qlty_imp_t     * img_qlty_imp;
+    vdc5_width_read_fb_t                  * w_read_fb;
+    vdc5_onoff_t                            graphics_enlargement;
+    vdc5_color_space_t                      color_space;
+    uint32_t                                reg_data;
+
+    w_read_fb = VDC5_ShrdPrmGetFrBuffWidth_Rd(graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, param->gr_flm_sel, w_read_fb, &param->gr_grc);
+
+    if (graphics_id == VDC5_GR_TYPE_GR0)
+    {
+        SetScalerGraphics(graphics_id, w_read_fb, &param->gr_grc, param->gr_flm_sel, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+    *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_MASK_0X00010301;
+    /* Line offset address direction of the frame buffer */
+    if (param->gr_ln_off_dir != VDC5_GR_LN_OFF_DIR_INC)
+    {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Frame buffer address setting signal */
+    *(img_synthesizer->gr_flm1) |= (uint32_t)param->gr_flm_sel << VDC5_REG_SHIFT_8;
+    /* Frame buffer burst transfer mode */
+    if (param->gr_bst_md != VDC5_BST_MD_32BYTE)
+    {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    /* Frame buffer base address */
+    *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+    /* Frame buffer line offset address[byte] */
+    *(img_synthesizer->gr_flm3) &= (uint32_t)~VDC5_REG_MASK_0X7FFF03FF;
+    *(img_synthesizer->gr_flm3) |= param->gr_ln_off << VDC5_REG_SHIFT_16;
+
+    /* The number of lines when reading the addresses repeatedly */
+    *(img_synthesizer->gr_flm5) = (uint32_t)VDC5_REG_MASK_0X000007FF;
+    /* Number of lines in a frame */
+    *(img_synthesizer->gr_flm5) |= ((uint32_t)w_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+
+    *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0XF7FF1C3F;
+    /* Format of the frame buffer read signal */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_format << VDC5_REG_SHIFT_28;
+    /* Width of the horizontal valid period */
+    *(img_synthesizer->gr_flm6) |= ((uint32_t)w_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+    /* Swap setting in frame buffer reading */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_rdswa << VDC5_REG_SHIFT_10;
+
+    if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM))
+    {   /* Sets the amount of data to be skipped through */
+        *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, param->gr_format);
+    }
+
+    /* Graphics display mode */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+    if (graphics_id == VDC5_GR_TYPE_GR0)
+    {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+    }
+    else
+    {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+    }
+
+    /* Graphics display area */
+    *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc.vs << VDC5_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc.vw;
+    *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc.hs << VDC5_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc.hw;
+
+    /* Initialize alpha blending in a rectangular area */
+    if ((graphics_id == VDC5_GR_TYPE_GR2) || (graphics_id == VDC5_GR_TYPE_GR3))
+    {
+        /* Turns off alpha blending in a rectangular area */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X0000D000;
+        /* The valid image area for alpha blending in a rectangular area */
+        reg_data                   = *(img_synthesizer->gr_ab2);
+        *(img_synthesizer->gr_ab4) = reg_data;
+        reg_data                   = *(img_synthesizer->gr_ab3);
+        *(img_synthesizer->gr_ab5) = reg_data;
+        /* Disable fade-in and fade-out */
+        *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+        /* Set the initial alpha value to '255' */
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+    }
+    /* Turns off  chroma-key processing */
+    *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+
+    if (graphics_id == VDC5_GR_TYPE_GR0)
+    {   /* Alpha value is set to 255. */
+        *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+
+        /* Swapping of data read from buffer in the YCbCr422 format */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000E000;
+        if (param->gr_format == VDC5_GR_FORMAT_YCBCR422)
+        {
+            *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_ycc_swap << VDC5_REG_SHIFT_13;
+            /* The interpolation mode for YCC422 to YCbCr444 conversion is fixed to average interpolation */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_REG_BIT8;
+        }
+        else
+        {   /* If the format of the frame buffer read signal is not YCbCr422,
+               initialize the swapping of data read from buffer in the YCbCr422 format. */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_GR_YCCSWAP_CBY0CRY1 << VDC5_REG_SHIFT_13;
+        }
+
+        color_space = VDC5_ShrdPrmGetColorSpaceFbRd(graphics_id);
+
+        SetScalerBackgroundColor(color_space);
+        SetImgQaImproverColorMtx(color_space);
+
+        img_qlty_imp = &vdc5_regaddr_img_qlty_imp;
+        /* Operating mode */
+        if (color_space == VDC5_COLOR_SPACE_GBR)
+        {
+            *(img_qlty_imp->adj_enh_tim1) &= (uint32_t)~VDC5_REG_BIT4;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_tim1) |= (uint32_t)VDC5_REG_BIT4;
+        }
+        /* Register update control register (ADJx_UPDATE)
+           b0       ADJx_VEN */
+        *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b8       GRx_UPDATE
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+}   /* End of function VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read change processing
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ChangeReadProcess (const vdc5_graphics_type_t graphics_id, const vdc5_read_chg_t * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    vdc5_gr_flm_sel_t                       gr_flm_sel_tmp;
+    vdc5_period_rect_t                    * gr_grc_tmp;
+    vdc5_width_read_fb_t                  * w_read_fb;
+    vdc5_onoff_t                            graphics_enlargement;
+    vdc5_gr_format_t                        gr_format_tmp;
+
+    gr_flm_sel_tmp  = VDC5_ShrdPrmGetSelFbAddrSig(graphics_id);
+    gr_grc_tmp      = VDC5_ShrdPrmGetDisplayArea(graphics_id);
+    w_read_fb       = VDC5_ShrdPrmGetFrBuffWidth_Rd(graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, gr_flm_sel_tmp, w_read_fb, gr_grc_tmp);
+
+    if (graphics_id == VDC5_GR_TYPE_GR0)
+    {
+        SetScalerGraphics(graphics_id, w_read_fb, gr_grc_tmp, gr_flm_sel_tmp, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+    /* Frame buffer base address */
+    if (param->gr_base != NULL)
+    {
+        *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+        if ((gr_flm_sel_tmp == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel_tmp == VDC5_GR_FLM_SEL_FLM_NUM))
+        {
+            gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(graphics_id);
+            /* Sets the amount of data to be skipped through */
+            *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+            *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, gr_format_tmp);
+        }
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL)
+    {
+        /* Number of lines in a frame */
+        *(img_synthesizer->gr_flm5) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm5) |= ((uint32_t)param->width_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+        /* Width of the horizontal valid period */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm6) |= ((uint32_t)param->width_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+    }
+
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL)
+    {
+        if (*(param->gr_disp_sel) != VDC5_DISPSEL_IGNORED)
+        {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*(param->gr_disp_sel);
+        }
+    }
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL)
+    {
+        *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc->vs << VDC5_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc->vw;
+        *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc->hs << VDC5_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc->hw;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+}   /* End of function VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read start processing
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_StartProcess (const vdc5_layer_id_t layer_id, const vdc5_start_t * const param)
+{
+    uint32_t                    layer_id_num;
+    vdc5_resource_state_t       resource_state;
+
+    if (param->gr_disp_sel != NULL)
+    {   /* Set graphics display mode */
+        SetGraphicsDisplayMode(layer_id, param->gr_disp_sel);
+    }
+
+    if (layer_id != VDC5_LAYER_ID_ALL)
+    {
+        rw_proc_function_tbl[layer_id](VDC5_ON);
+    }
+    else
+    {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++)
+        {
+            resource_state = VDC5_ShrdPrmGetRwProcReady((vdc5_layer_id_t)layer_id_num);
+            if (resource_state != VDC5_RESOURCE_ST_INVALID)
+            {
+                rw_proc_function_tbl[layer_id_num](VDC5_ON);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(layer_id);
+}   /* End of function VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read stop processing
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+void VDC5_StopProcess (const vdc5_layer_id_t layer_id)
+{
+    uint32_t                    layer_id_num;
+    vdc5_resource_state_t       resource_state;
+
+    if (layer_id != VDC5_LAYER_ID_ALL)
+    {
+        rw_proc_function_tbl[layer_id](VDC5_OFF);
+    }
+    else
+    {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++)
+        {
+            resource_state = VDC5_ShrdPrmGetRwProcEnabled((vdc5_layer_id_t)layer_id_num);
+            if (resource_state != VDC5_RESOURCE_ST_INVALID)
+            {
+                rw_proc_function_tbl[layer_id_num](VDC5_OFF);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(layer_id);
+}   /* End of function VDC5_StopProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for noise reduction
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_VideoNoiseReduction (const vdc5_onoff_t nr1d_on, const vdc5_noise_reduction_t * const param)
+{
+    const vdc5_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc5_nr_param_t             * nr_param;
+
+    input_ctrl = &vdc5_regaddr_input_ctrl;
+
+    if (param != NULL)
+    {
+        /* Y/G signal noise reduction parameter */
+        nr_param = &param->y;
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_MASK_0X00007F33;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt0) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_gain;
+
+        /* Cb/B signal noise reduction parameter */
+        nr_param = &param->cb;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1)  = nr_param->nr1d_th << VDC5_REG_SHIFT_24;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_20;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain << VDC5_REG_SHIFT_16;
+
+        /* Cr/R signal noise reduction parameter */
+        nr_param = &param->cr;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain;
+    }
+
+    if (nr1d_on == VDC5_OFF)
+    {
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT16;
+    }
+    else
+    {
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT16;
+    }
+
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for color matrix
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageColorMatrix (const vdc5_color_matrix_t * const param)
+{
+    SetColorMatrix(param->mtx_mode, param->offset, param->gain, &vdc5_regaddr_color_matrix[param->module]);
+}   /* End of function VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for image enhancement processing
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageEnhancement (
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc5_regaddr_img_qlty_imp;
+
+    /* Sharpness */
+    SetImageEnhancementSharpness(shp_h_on, sharp_param, img_qlty_imp);
+
+    /* LTI */
+    SetImageEnhancementLti(lti_h_on, lti_param, img_qlty_imp);
+
+    /* Enhancer area */
+    if (enh_area != NULL)
+    {
+        *(img_qlty_imp->adj_enh_tim2)  = (uint32_t)enh_area->vs << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim2) |= (uint32_t)enh_area->vw;
+        *(img_qlty_imp->adj_enh_tim3)  = (uint32_t)enh_area->hs << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim3) |= (uint32_t)enh_area->hw;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for black stretch
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageBlackStretch (
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param)
+{
+    const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc5_regaddr_img_qlty_imp;
+
+    if (param != NULL)
+    {
+        /* Black stretch start point */
+        *(img_qlty_imp->adj_bkstr_set)  = (uint32_t)((uint32_t)param->bkstr_st << VDC5_REG_SHIFT_20);
+        /* Black stretch depth */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_d << VDC5_REG_SHIFT_16);
+        /* Black stretch time constant (T1) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_t1 << VDC5_REG_SHIFT_8);
+        /* Black stretch time constant (T2) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)param->bkstr_t2;
+    }
+
+    if (bkstr_on == VDC5_OFF)
+    {
+        *(img_qlty_imp->adj_bkstr_set) &= (uint32_t)~VDC5_REG_BIT24;
+    }
+    else
+    {
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)VDC5_REG_BIT24;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for alpha blending
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_AlphaBlending (const vdc5_graphics_type_t graphics_id, const vdc5_alpha_blending_t * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+    /* Alpha signal of the ARGB1555/ARGB5551 format */
+    if (param->alpha_1bit != NULL)
+    {
+        *(img_synthesizer->gr_ab10) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab10) |= (uint32_t)param->alpha_1bit->gr_a0 << VDC5_REG_SHIFT_24;
+        *(img_synthesizer->gr_ab11) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)param->alpha_1bit->gr_a1 << VDC5_REG_SHIFT_24;
+    }
+
+    /* Premultiplication processing at alpha blending in one-pixel */
+    if (param->alpha_pixel != NULL)
+    {
+        if (param->alpha_pixel->gr_acalc_md == VDC5_OFF)
+        {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT14;
+        }
+        else
+        {
+            *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT14;
+        }
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for rectangle alpha blending
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      None
+******************************************************************************/
+void VDC5_AlphaBlendingRect (
+    const vdc5_graphics_type_t                  graphics_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_alpha_rect_t               * alpha_rect_tmp;
+    uint32_t                                arc_coef;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+    /* Alpha blending on/off control in a rectangular area */
+    if (gr_arc_on == VDC5_OFF)
+    {
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+    }
+    else
+    {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT12;
+    }
+
+    if (param != NULL)
+    {
+        /* Rectangular area subjected to alpha blending */
+        SetAlphaRectArea(param->gr_arc, img_synthesizer);
+
+        /* Alpha blending in a rectangular area */
+        alpha_rect_tmp = param->alpha_rect;
+        if (alpha_rect_tmp != NULL)
+        {
+            /* Multiplication processing with current alpha at alpha blending in a rectangular area (on/off) */
+            if (alpha_rect_tmp->gr_arc_mul == VDC5_OFF)
+            {
+                *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT15;
+            }
+            else
+            {
+                *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT15;
+            }
+            /* Alpha coefficient for alpha blending in a rectangular area (-255 to 255) */
+            if (alpha_rect_tmp->gr_arc_coef < 0)
+            {
+                arc_coef = (uint32_t)(alpha_rect_tmp->gr_arc_coef * (-1));  /* Conversion into absolute value */
+                /* Subtraction of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)VDC5_REG_BIT24;
+            }
+            else
+            {
+                arc_coef = (uint32_t)alpha_rect_tmp->gr_arc_coef;
+                /* Addition of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)0x00000000u;
+            }
+            *(img_synthesizer->gr_ab6) |= arc_coef << VDC5_REG_SHIFT_16;
+            /* Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+            *(img_synthesizer->gr_ab6) |= (uint32_t)alpha_rect_tmp->gr_arc_rate;
+            /* Initial alpha value for alpha blending in a rectangular area */
+            *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_MASK_0X00FF0000;
+            *(img_synthesizer->gr_ab7) |= (uint32_t)alpha_rect_tmp->gr_arc_def << VDC5_REG_SHIFT_16;
+        }
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_AlphaBlendingRect() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma-key
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_Chromakey (
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_gr_format_t                        gr_format_tmp;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+    if (param != NULL)
+    {
+        gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(graphics_id);
+        if ((gr_format_tmp == VDC5_GR_FORMAT_CLUT1) ||
+            (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) ||
+            (gr_format_tmp == VDC5_GR_FORMAT_CLUT8))
+        {
+            *(img_synthesizer->gr_ab8)  = (uint32_t)(param->ck_color << VDC5_REG_SHIFT_24);
+            *(img_synthesizer->gr_ab9)  = ColorConversionIntoAgbr(param->rep_color);
+        }
+        else
+        {
+            /* Color conversion from gr_format_tmp into RGB888 format */
+            *(img_synthesizer->gr_ab8)  = ColorConversion(gr_format_tmp, param->ck_color);
+            *(img_synthesizer->gr_ab9)  = ColorConversion(gr_format_tmp, param->rep_color);
+        }
+        if (graphics_id == VDC5_GR_TYPE_GR0)
+        {   /* Alpha value is set to 255. */
+            *(img_synthesizer->gr_ab9) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+        }
+        else
+        {
+            *(img_synthesizer->gr_ab9) |= (uint32_t)param->rep_alpha << VDC5_REG_SHIFT_24;
+        }
+    }
+
+    if (gr_ck_on == VDC5_OFF)
+    {
+        *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+    else
+    {
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for CLUT
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_CLUT (const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param)
+{
+    vdc5_gr_format_t                        gr_format_tmp;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+    gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(graphics_id);
+    if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1)
+    {
+        if (param->color_num == ((uint32_t)1u))
+        {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            if (graphics_id == VDC5_GR_TYPE_GR0)
+            {   /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+            }
+        }
+        else
+        {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            *(img_synthesizer->gr_ab11) = ColorConversionIntoAgbr(param->clut[1]);
+            if (graphics_id == VDC5_GR_TYPE_GR0)
+            {   /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+                *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+            }
+        }
+    }
+    else        /* CLUT4 or CLUT8 */
+    {
+        Set_Clut(param, vdc5_regaddr_clut[graphics_id]);
+
+        /* CLUT table control register (GRx_CLUT)
+           b16      GRx_CLT_SEL - CLUT table select signal - XOR, flip signal */
+        *(img_synthesizer->gr_clut) ^= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_CLUT() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display calibration
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_DisplayCalibration (const vdc5_disp_calibration_t * const param)
+{
+    const vdc5_calibr_bright_t        * bright_tmp;
+    const vdc5_calibr_contrast_t      * contrast_tmp;
+    const vdc5_calibr_dither_t        * panel_dither_tmp;
+    const vdc5_regaddr_output_ctrl_t  * output_ctrl;
+
+    output_ctrl = &vdc5_regaddr_output_ctrl;
+
+    /* Correction circuit sequence control */
+    if (param->route == VDC5_CALIBR_ROUTE_BCG)
+    {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT12;
+    }
+    else
+    {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT12;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL)
+    {
+        *(output_ctrl->out_bright1)  = (uint32_t)bright_tmp->pbrt_g;
+        *(output_ctrl->out_bright2)  = (uint32_t)bright_tmp->pbrt_b << VDC5_REG_SHIFT_16;
+        *(output_ctrl->out_bright2) |= (uint32_t)bright_tmp->pbrt_r;
+    }
+
+    /* Contrast (gain) adjustment */
+    contrast_tmp = param->contrast;
+    if (contrast_tmp != NULL)
+    {
+        *(output_ctrl->out_contrast)  = (uint32_t)contrast_tmp->cont_g << VDC5_REG_SHIFT_16;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_b << VDC5_REG_SHIFT_8;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_r;
+    }
+
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL)
+    {
+        *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00300000;
+        *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_sel << VDC5_REG_SHIFT_20;
+        if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2)
+        {
+            *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00003333;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pa << VDC5_REG_SHIFT_12;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pb << VDC5_REG_SHIFT_8;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pc << VDC5_REG_SHIFT_4;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pd;
+        }
+    }
+
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for gamma correction
+ * @param[in]   gam_on      : Gamma correction ON/OFF setting
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_GammaCorrection (const vdc5_onoff_t gam_on, const vdc5_gamma_correction_t * const param)
+{
+    const vdc5_regaddr_gamma_t  * gamma;
+
+    gamma = &vdc5_regaddr_gamma;
+
+    /* Gamma correction on/off control */
+    *(gamma->gam_sw) = (gam_on == VDC5_OFF) ? 0x0000u : 0x0001u;
+
+    if (param != NULL)
+    {
+        /* Start threshold of area 1 to 31 of G signal */
+        Set_StartThreshold_Gamma(param->gam_g_th, gamma->gam_g_area);
+        /* Gain adjustment of area 0 to 31 of G signal */
+        Set_GainAdjustment_Gamma(param->gam_g_gain, gamma->gam_g_lut);
+        /* Register update control register G (GAM_G_UPDATE)
+           b0       GAM_G_VEN */
+        *(gamma->gam_g_update) |= (uint32_t)VDC5_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of B signal */
+        Set_StartThreshold_Gamma(param->gam_b_th, gamma->gam_b_area);
+        /* Gain adjustment of area 0 to 31 of B signal */
+        Set_GainAdjustment_Gamma(param->gam_b_gain, gamma->gam_b_lut);
+        /* Register update control register B (GAM_B_UPDATE)
+           b0       GAM_B_VEN */
+        *(gamma->gam_b_update) |= (uint32_t)VDC5_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of R signal */
+        Set_StartThreshold_Gamma(param->gam_r_th, gamma->gam_r_area);
+        /* Gain adjustment of area 0 to 31 of R signal */
+        Set_GainAdjustment_Gamma(param->gam_r_gain, gamma->gam_r_lut);
+        /* Register update control register R (GAM_R_UPDATE)
+           b0       GAM_R_VEN */
+        *(gamma->gam_r_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+}   /* End of function VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Sets external input video signal
+ * @param[in]   ext_sig_tmp             : External input signal parameter
+ * @param[in]   input_ctrl              : Input controller registers
+ * @retval      None
+******************************************************************************/
+static void SetVideoExternalInput (
+    const vdc5_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc5_regaddr_input_ctrl_t * const input_ctrl)
+{
+    *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_MASK_0X00007111;
+    /* External input format select */
+    if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR444)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_EXTIN_FORMAT_RGB888 << VDC5_REG_SHIFT_12;
+    }
+    else
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)ext_sig_tmp->inp_format << VDC5_REG_SHIFT_12;
+    }
+    /* Clock edge select for capturing external input video image signals */
+    if (ext_sig_tmp->inp_pxd_edge != VDC5_EDGE_RISING)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Clock edge select for capturing external input Vsync signals */
+    if (ext_sig_tmp->inp_vs_edge != VDC5_EDGE_RISING)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Clock edge select for capturing external input Hsync signals */
+    if (ext_sig_tmp->inp_hs_edge != VDC5_EDGE_RISING)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    *(input_ctrl->inp_ext_sync_cnt) &= (uint32_t)~VDC5_REG_MASK_0X11110113;
+    /* External input bit endian change on/off control */
+    if (ext_sig_tmp->inp_endian_on != VDC5_OFF)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT28;
+    }
+    /* External input B/R signal swap on/off control */
+    if (ext_sig_tmp->inp_swap_on != VDC5_OFF)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT24;
+    }
+    /* External input Vsync signal DV_VSYNC inversion control */
+    if (ext_sig_tmp->inp_vs_inv != VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT20;
+    }
+    /* External input Hsync signal DV_HSYNC inversion control */
+    if (ext_sig_tmp->inp_hs_inv != VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Reference select for external input BT.656 Hsync signal */
+    if (ext_sig_tmp->inp_h_edge_sel != VDC5_EXTIN_REF_H_EAV)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Number of lines for BT.656 external input */
+    if (ext_sig_tmp->inp_f525_625 != VDC5_EXTIN_LINE_525)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)ext_sig_tmp->inp_h_pos;
+}   /* End of function SetVideoExternalInput() */
+
+/**************************************************************************//**
+ * @brief       Initializes cascaded connection
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void SetInitialConnection (void)
+{
+    volatile uint32_t * vin_gr_update;
+    volatile uint32_t * vin_gr_ab1;
+
+    vin_gr_update   = &VDC50.GR_VIN_UPDATE;
+    vin_gr_ab1      = &VDC50.GR_VIN_AB1;
+
+    /* Selection of lower-layer plane in scaler: Selects graphics 0 as lower-layer graphics. */
+    *(vin_gr_ab1)  &= (uint32_t)~VDC5_REG_BIT2;
+    /* Graphics display mode in VIN */
+    *(vin_gr_ab1)  &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+    *(vin_gr_ab1)  |= (uint32_t)VDC5_DISPSEL_LOWER;
+    /* Graphics register update control register (GR_VIN_UPDATE)
+       b8       GR_VIN_UPDATE
+       b4       GR_VIN_P_VEN */
+    *(vin_gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+}   /* End of function SetInitialConnection() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for graphics
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void SetGrapicsBackgroundColor (void)
+{
+    uint32_t                bg_color_tmp;
+    uint32_t                bg_color_conv;
+    volatile uint32_t     * bg_color_reg;
+    volatile uint32_t     * update_reg;
+
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp = VDC5_ShrdPrmGetBgColor(VDC5_COLOR_SPACE_GBR);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+    /* GR2, GR3 */
+    /* Background color in GBR format (GR2_BASE) */
+    bg_color_reg    = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR2].gr_base;
+    *bg_color_reg   = bg_color_conv;
+    /* Graphics register update control register (GR2_UPDATE)
+       b4       GR2_P_VEN */
+    update_reg      = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR2].gr_update;
+    *update_reg    |= (uint32_t)VDC5_REG_BIT4;
+
+    /* Background color in GBR format (GR3_BASE) */
+    bg_color_reg    = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR3].gr_base;
+    *bg_color_reg   = bg_color_conv;
+    /* Graphics register update control register (GR3_UPDATE)
+       b4       GR3_P_VEN */
+    update_reg      = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR3].gr_update;
+    *update_reg    |= (uint32_t)VDC5_REG_BIT4;
+}   /* End of function SetGrapicsBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for scaler 0 (graphics 0)
+ *
+ *              Description:<br>
+ *              This function should be called only when graphics 0 is selected.
+ * @param[in]   color_space         : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetScalerBackgroundColor (const vdc5_color_space_t color_space)
+{
+    volatile uint32_t * scl0_update_reg;
+    volatile uint32_t * scl0_ovr1_reg;
+    volatile uint32_t * gr_base_reg;
+    volatile uint32_t * gr_update_reg;
+    uint32_t            bg_color_tmp;
+    uint32_t            bg_color_conv;
+
+    scl0_ovr1_reg   = vdc5_regaddr_scaler.scl0_ovr1;
+    scl0_update_reg = vdc5_regaddr_scaler.scl0_update;
+    gr_base_reg     = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR0].gr_base;
+    gr_update_reg   = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR0].gr_update;
+
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp    = VDC5_ShrdPrmGetBgColor(color_space);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+    /* Background color in RGB format or CrYCb format */
+    *scl0_ovr1_reg      = bg_color_tmp;
+    /* Register update control register
+       b4       SCL0_VEN_B */
+    *scl0_update_reg   |= (uint32_t)VDC5_REG_BIT4;
+
+    /* Background color in GBR format or YCbCr format */
+    *gr_base_reg        = bg_color_conv;
+    /* Graphics register update control register
+       b4       GRx_P_VEN */
+    *gr_update_reg     |= (uint32_t)VDC5_REG_BIT4;
+}   /* End of function SetScalerBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVA/VS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVA_VS (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stva1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stva1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_stva2) &= (uint32_t)~VDC5_REG_BIT4;
+    }
+    else
+    {
+        *(output_ctrl->tcon_tim_stva2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVA_VS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVB/VE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVB_VE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stvb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stvb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_stvb2) &= (uint32_t)~VDC5_REG_BIT4;
+    }
+    else
+    {
+        *(output_ctrl->tcon_tim_stvb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVB_VE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STH/HS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STH_HS (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_sth1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_sth1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_sth2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STH_HS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STB/HE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STB_HE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_stb2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STB_HE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - CPV/GCK
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_CPV_GCK (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_cpv1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_cpv1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_cpv2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_CPV_GCK() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLA
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLA (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_pola1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_pola1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_pola2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_pola2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLA() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLB
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLB (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_polb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_polb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_polb2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_polb2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLB() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - DE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_DE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Polarity inversion control of signal */
+    *(output_ctrl->tcon_tim_de) = (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) ? (uint32_t)0u : (uint32_t)1u;
+
+}   /* End of function SetLcdTcon_DE() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-down
+ * @param[in]   scldw_rot               : Scaling-down and rotation parameter
+ * @param[in]   res_inter               : Field operating mode select
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingDown (
+    const vdc5_scalingdown_rot_t    * const scldw_rot,
+    const vdc5_res_inter_t                  res_inter,
+    const vdc5_regaddr_scaler_t     * const scaler)
+{
+    uint32_t    vw_before_scld;    /* Vertical width before scaling-down */
+    uint32_t    hw_before_scld;    /* Horizontal width before scaling-down */
+    uint32_t    vw_after_scld;     /* Vertical width after scaling-down */
+    uint32_t    hw_after_scld;     /* Horizontal width after scaling-down */
+    uint32_t    scaling_ratio;
+
+    vw_before_scld = (uint32_t)scldw_rot->res.vw;
+    hw_before_scld = (uint32_t)scldw_rot->res.hw;
+
+    vw_after_scld = (uint32_t)scldw_rot->res_out_vw;
+    hw_after_scld = (uint32_t)scldw_rot->res_out_hw;
+
+    /* Vertical scaling-down: ON, vertical scaling-up: OFF */
+    *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT4;
+    *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+    if (vw_before_scld > vw_after_scld)
+    {
+        scaling_ratio = CalcScalingRatio(vw_before_scld, vw_after_scld, scldw_rot->adj_sel, VDC5_OFF);
+
+        *(scaler->scl0_ds6) = scaling_ratio;
+    }
+    else
+    {
+        *(scaler->scl0_ds6) = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    }
+
+    /* Horizontal scaling-down */
+    if (hw_before_scld > hw_after_scld)
+    {   /* ON */
+        *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(hw_before_scld, hw_after_scld, VDC5_ON, VDC5_ON);
+
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_ds4) |= scaling_ratio;
+    }
+    else
+    {   /* OFF */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    if (res_inter != VDC5_RES_INTER_PROGRESSIVE)
+    {   /* Top */
+        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+    }
+
+}   /* End of function SetScalingDown() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-up
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   adj_sel                 : Folding handling (on/off)
+ * @param[in]   ip_conversion           : IP conversion on/off
+ * @param[in]   res_ds_wr_md            : Frame buffer writing mode for image processing
+ * @param[in]   ln_off_dir              : Line offset address direction of the frame buffer
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingUp (
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_onoff_t                  adj_sel,
+    const vdc5_onoff_t                  ip_conversion,
+    const vdc5_wr_md_t                  res_ds_wr_md,
+    const vdc5_gr_ln_off_dir_t          ln_off_dir,
+    const vdc5_regaddr_scaler_t * const scaler)
+{
+    uint32_t            w_before_scl;       /* Width before scaling-up */
+    uint32_t            w_after_scl;        /* Width after scaling-up */
+    uint32_t            scaling_ratio;
+    vdc5_onoff_t        vscl_up;            /* Vertical scaling-up */
+
+    vscl_up = VDC5_OFF;
+
+    /* Vertical scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_vw;
+    w_after_scl     = (uint32_t)gr_grc->vw;
+    if (w_before_scl < w_after_scl)
+    {
+        /* Vertical scaling-down: OFF, vertical scaling-up: ON */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT4;
+        *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT4;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+        *(scaler->scl0_ds6) = scaling_ratio;
+
+        vscl_up = VDC5_ON;
+    }
+    else
+    {   /* Vertical scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+    }
+
+    /* Horizontal scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_hw;
+    w_after_scl     = (uint32_t)gr_grc->hw;
+    if (w_before_scl < w_after_scl)
+    {   /* Horizontal scaling-up: ON */
+        *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+
+        *(scaler->scl0_us5) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_us5) |= scaling_ratio;
+    }
+    else
+    {   /* Horizontal scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    if (ip_conversion == VDC5_OFF)
+    {
+        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    }
+    else
+    {
+        if (vscl_up != VDC5_OFF)
+        {
+            switch (res_ds_wr_md)
+            {
+                case VDC5_WR_MD_ROT_90DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    /* US_HB */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE;
+                break;
+                case VDC5_WR_MD_ROT_180DEG:
+                    if (ln_off_dir == VDC5_GR_LN_OFF_DIR_INC)
+                    {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                break;
+                case VDC5_WR_MD_ROT_270DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    /* US_HT */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+                break;
+                default:    /* Normal or horizontal mirroring */
+                    if (ln_off_dir == VDC5_GR_LN_OFF_DIR_DEC)
+                    {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                break;
+            }
+        }
+    }
+}   /* End of function SetScalingUp() */
+
+/**************************************************************************//**
+ * @brief       Calculates scaling ratio
+ *
+ *              Description:<br>
+ *              In this function, the overflow in calculation is not considered.
+ *              before_scl and after_scl are 11bit width, so the overflow does not occur.
+ * @param[in]   before_scl              : Size before scaling
+ * @param[in]   after_scl               : Size after scaling
+ * @param[in]   adj_sel                 : Handling for lack of last-input pixel/line, or folding handling
+ * @param[in]   round_up                : Round-up on/off
+ * @retval      Scaling ratio
+******************************************************************************/
+static uint32_t CalcScalingRatio (
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc5_onoff_t  adj_sel,
+    const vdc5_onoff_t  round_up)
+{
+    float32_t   ratio;
+    float32_t   sigma;
+    int32_t     ratio_int;
+    uint32_t    scaling_ratio;
+
+    /* When parameter checking is not performed,
+       following checks are necessary to avoid a division by zero exception and a negative number. */
+    if ((after_scl == 0u) || (after_scl == 1u))
+    {
+        scaling_ratio = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    }
+    else
+    {
+        /* ratio = before_scl * 4096.0 / after_scl */
+        ratio  = (float32_t)before_scl * (float32_t)SCALING_RATIO_SAME_SIZE;
+        ratio /= (float32_t)after_scl;
+
+        if (adj_sel != VDC5_OFF)
+        {
+            sigma  = ratio * ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+            sigma -= ((float32_t)before_scl - (float32_t)VDC5_REG_FLOAT_1_0) * (float32_t)SCALING_RATIO_SAME_SIZE;
+            sigma /= ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+            ratio -= sigma;
+        }
+
+        if (round_up == VDC5_OFF)
+        {   /* Round off */
+            ratio    += (float32_t)VDC5_REG_FLOAT_0_5;
+            ratio_int = (int32_t)ratio;
+        }
+        else
+        {   /* Round up */
+            ratio_int = (int32_t)ratio;
+            if ((float32_t)ratio_int < ratio)
+            {
+                ratio_int++;
+            }
+        }
+        scaling_ratio = (uint32_t)ratio_int;
+    }
+    return scaling_ratio;
+}   /* End of function CalcScalingRatio() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the input controller
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void SetInputCntrlColorMtx (void)
+{
+    vdc5_color_space_t      color_space_input;
+    vdc5_color_space_t      color_space_fb;
+    vdc5_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    color_space_input   = VDC5_ShrdPrmGetColorSpace();
+    color_space_fb      = VDC5_ShrdPrmGetColorSpaceFbWr();
+    /* Color matrix operating mode */
+    if (color_space_input == VDC5_COLOR_SPACE_GBR)
+    {
+        if (color_space_fb == VDC5_COLOR_SPACE_GBR)
+        {   /* GBR to GBR */
+            mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+        }
+        else
+        {   /* GBR to YCbCr */
+            mtx_mode_tmp = VDC5_COLORMTX_GBR_YCBCR;
+        }
+    }
+    else
+    {
+        if (color_space_fb == VDC5_COLOR_SPACE_GBR)
+        {   /* YCbCr to GBR */
+            mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+        }
+        else
+        {   /* YCbCr to YCbCr */
+            mtx_mode_tmp = VDC5_COLORMTX_YCBCR_YCBCR;
+        }
+    }
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[VDC5_COLORMTX_IMGCNT]);
+
+}   /* End of function SetInputCntrlColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Confirms whether the graphics enlargement will occur or not
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @retval      Graphics enlargement on/off
+******************************************************************************/
+static vdc5_onoff_t ConfirmGraphicsEnlargement (
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc)
+{
+    vdc5_onoff_t graphics_enlargement;
+
+    graphics_enlargement = VDC5_OFF;
+    if (gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM)
+    {
+        if (graphics_id == VDC5_GR_TYPE_GR0)
+        {
+            if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) ||
+                ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw))
+            {
+                graphics_enlargement = VDC5_ON;
+            }
+        }
+    }
+    else
+    {
+        if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) || ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw))
+        {
+            graphics_enlargement = VDC5_ON;
+        }
+    }
+    return graphics_enlargement;
+}   /* End of function ConfirmGraphicsEnlargement() */
+
+/**************************************************************************//**
+ * @brief       Sets scaler for graphics
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void SetScalerGraphics (
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_onoff_t                  gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_scaler_t           * scaler;
+    vdc5_res_inter_t                        res_inter_tmp;
+    vdc5_wr_md_t                            res_ds_wr_md_tmp;
+    vdc5_onoff_t                            adj_sel_tmp;
+    vdc5_onoff_t                            ip_conversion;
+    uint32_t                                reg_data;
+    vdc5_gr_ln_off_dir_t                    ln_off_dir;
+
+    scaler = &vdc5_regaddr_scaler;
+
+    if ((gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) && (gr_enlarge == VDC5_OFF))
+    {   /* Normal graphics display */
+        /* Sync signals from the graphics processing block */
+        *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
+
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b4       SCL0_VEN_B */
+        *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT4);
+    }
+    else
+    {   /* Video image or graphics enlargement */
+        /* Sync signals from the scaling-up control block */
+        *(scaler->scl0_us8) &= (uint32_t)~VDC5_REG_BIT4;
+
+        /* Graphics display area */
+        *(scaler->scl0_us2)  = (uint32_t)gr_grc->vs << VDC5_REG_SHIFT_16;
+        *(scaler->scl0_us2) |= (uint32_t)gr_grc->vw;
+        *(scaler->scl0_us3)  = (uint32_t)gr_grc->hs << VDC5_REG_SHIFT_16;
+        *(scaler->scl0_us3) |= (uint32_t)gr_grc->hw;
+
+        *(scaler->scl0_us4)  = (uint32_t)w_read_fb->in_vw << VDC5_REG_SHIFT_16;
+        *(scaler->scl0_us4) |= (uint32_t)w_read_fb->in_hw;
+
+        res_ds_wr_md_tmp    = VDC5_ShrdPrmGetWritingMode();
+        adj_sel_tmp         = VDC5_ShrdPrmGetMeasureFolding(graphics_id);
+        ip_conversion       = VDC5_OFF;
+        if ((gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF))
+        {
+            res_inter_tmp = VDC5_ShrdPrmGetInterlace();
+            if (res_inter_tmp != VDC5_RES_INTER_PROGRESSIVE)
+            {
+                ip_conversion = VDC5_ON;
+            }
+        }
+
+        ln_off_dir = VDC5_ShrdPrmGetLineOfsAddrDir(graphics_id);
+        /* Scaling-up */
+        SetScalingUp(w_read_fb, gr_grc, adj_sel_tmp, ip_conversion, res_ds_wr_md_tmp, ln_off_dir, scaler);
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b8       SCL0_UPDATE
+           b4       SCL0_VEN_B
+           b0       SCL0_VEN_A */
+        *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+    }
+
+    if (gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM)
+    {
+        img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+        /* Frame buffer frame offset address */
+        reg_data                    = *(scaler->scl1_wr4);
+        *(img_synthesizer->gr_flm4) = reg_data;
+
+        /* Graphics register update control register (GRx_UPDATE)
+           b0       GRx_IBUS_VEN */
+        *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+}   /* End of function SetScalerGraphics() */
+
+/**************************************************************************//**
+ * @brief       Gets the amount of data to be skipped through
+ * @param[in]   gr_base                 : Frame buffer base address
+ * @param[in]   gr_format               : Graphics format
+ * @retval      The amount of data to be skipped through
+******************************************************************************/
+static uint32_t DisplayStartPixelSetting (const uint32_t gr_base, const vdc5_gr_format_t gr_format)
+{
+    uint32_t                gr_sta_pos;
+    static const uint32_t   bits_per_pixel[VDC5_GR_FORMAT_NUM] =
+    {
+        VDC5_REG_BIT_PER_PIXEL_RGB565,         /* RGB565 */
+        VDC5_REG_BIT_PER_PIXEL_RGB888,         /* RGB888 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB1555,       /* ARGB1555 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB4444,       /* ARGB4444 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB8888,       /* ARGB8888 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT8,          /* CLUT8 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT4,          /* CLUT4 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT1,          /* CLUT1 */
+        VDC5_REG_BIT_PER_PIXEL_YCBCR422,       /* YCbCr422: In the YCbCr422 format, 32 bits are used for two pixels. */
+        VDC5_REG_BIT_PER_PIXEL_YCBCR444,       /* YCbCr444 */
+        VDC5_REG_BIT_PER_PIXEL_RGBA5551,       /* RGBA5551 */
+        VDC5_REG_BIT_PER_PIXEL_RGBA8888        /* RGBA8888 */
+    };
+
+    gr_sta_pos  = gr_base & (uint32_t)VDC5_REG_MASK_0X00000007;
+    gr_sta_pos *= (uint32_t)VDC5_REG_BIT_PER_PIXEL_VALUE_8;
+    gr_sta_pos /= bits_per_pixel[gr_format];
+    gr_sta_pos &= (uint32_t)VDC5_REG_MASK_0X0000003F;
+
+    return gr_sta_pos;
+}   /* End of function DisplayStartPixelSetting() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the image quality improver
+ * @param[in]   color_space             : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetImgQaImproverColorMtx (const vdc5_color_space_t color_space)
+{
+    vdc5_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    /* Color matrix operating mode */
+    if (color_space == VDC5_COLOR_SPACE_GBR)
+    {
+        mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+    }
+    else
+    {
+        mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+    }
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[VDC5_COLORMTX_ADJ_0]);
+
+}   /* End of function SetImgQaImproverColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for scaler 0
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_0 (const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    volatile uint32_t               dummy_read;
+    uint32_t                        reg_data;
+
+    /* SC0/GR0 writing */
+    scaler = &vdc5_regaddr_scaler;
+
+    if (ability == VDC5_OFF)
+    {   /* SC0 frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcDisable(VDC5_LAYER_ID_0_WR);
+    }
+    else
+    {   /* SC0 frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+        /* Reset and reset cancellation of the pointer buffer with dummy read */
+        *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+        *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+#if(1) /* mbed */
+        (void)dummy_read; /* unused */
+#endif
+
+        VDC5_ShrdPrmSetRwProcEnable(VDC5_LAYER_ID_0_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 0
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_0 (const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* SC0/GR0 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR0];
+
+    if (ability == VDC5_OFF)
+    {   /* GR0 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+
+        VDC5_ShrdPrmSetRwProcDisable(VDC5_LAYER_ID_0_RD);
+    }
+    else
+    {   /* GR0 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(VDC5_LAYER_ID_0_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 2
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_2 (const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR2 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR2];
+
+    if (ability == VDC5_OFF)
+    {   /* GR2 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(VDC5_LAYER_ID_2_RD);
+    }
+    else
+    {   /* GR2 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(VDC5_LAYER_ID_2_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_2() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 3
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_3 (const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR3 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR3];
+
+    if (ability == VDC5_OFF)
+    {   /* GR3 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(VDC5_LAYER_ID_3_RD);
+    }
+    else
+    {   /* GR3 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(VDC5_LAYER_ID_3_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_3() */
+
+/**************************************************************************//**
+ * @brief       Sets register update control register to update the frame buffer
+ *              read and write enable settings.
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+static void SetRegUpdateRwEnable (const vdc5_layer_id_t layer_id)
+{
+    volatile uint32_t * scl1_update_reg;
+    volatile uint32_t * gr_update_reg;
+
+    switch (layer_id)
+    {
+        case VDC5_LAYER_ID_0_WR:        /* Layer 0, write process */
+            scl1_update_reg   = vdc5_regaddr_scaler.scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+        break;
+        case VDC5_LAYER_ID_0_RD:        /* Layer 0, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+        break;
+        case VDC5_LAYER_ID_2_RD:        /* Layer 2, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+        break;
+        case VDC5_LAYER_ID_3_RD:        /* Layer 3, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+        break;
+
+        case VDC5_LAYER_ID_ALL:         /* All */
+            /* Register update control register (SCx_SCL1_UPDATE)
+               b20      SCL1_UPDATE_B
+               b4       SCL1_VEN_B
+               b0       SCL1_VEN_A */
+            scl1_update_reg   = vdc5_regaddr_scaler.scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN
+               b0       GRx_IBUS_VEN */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+        break;
+
+        default:
+            /* DO NOTHING */
+        break;
+    }
+}   /* End of function SetRegUpdateRwEnable() */
+
+/**************************************************************************//**
+ * @brief       Sets graphics display mode
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   gr_disp_sel             : Graphics display mode
+ * @retval      None
+******************************************************************************/
+static void SetGraphicsDisplayMode (const vdc5_layer_id_t layer_id, const vdc5_gr_disp_sel_t * const gr_disp_sel)
+{
+    uint32_t                                graphics_id;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    if (layer_id == VDC5_LAYER_ID_ALL)
+    {
+        for (graphics_id = 0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++)
+        {
+            if (gr_disp_sel[graphics_id] != VDC5_DISPSEL_IGNORED)
+            {
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+                *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+                *(img_synthesizer->gr_ab1) |= (uint32_t)gr_disp_sel[graphics_id];
+                /* Graphics register update control register (GRx_UPDATE)
+                   b4       GRx_P_VEN */
+                *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+            }
+        }
+    }
+    else if ((layer_id == VDC5_LAYER_ID_0_RD) || (layer_id == VDC5_LAYER_ID_2_RD) || (layer_id == VDC5_LAYER_ID_3_RD))
+    {
+        if (*gr_disp_sel != VDC5_DISPSEL_IGNORED)
+        {
+            graphics_id = (uint32_t)(layer_id - VDC5_SC_TYPE_NUM);
+
+            img_synthesizer = &vdc5_regaddr_img_synthesizer[graphics_id];
+
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*gr_disp_sel;
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN */
+            *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+        }
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}   /* End of function SetGraphicsDisplayMode() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix
+ * @param[in]   mtx_mode                : Operating mode
+ * @param[in]   offset                  : Offset (DC) adjustment of Y/G, B, and R signal
+ * @param[in]   gain                    : GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment
+ * @param[in]   color_matrix            : Color matrix registers
+ * @retval      None
+******************************************************************************/
+static void SetColorMatrix (
+    const vdc5_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc5_regaddr_color_matrix_t   * const color_matrix)
+{
+    /* Operating mode */
+    *(color_matrix->mtx_mode) = (uint32_t)mtx_mode;
+
+    /* Offset (DC) adjustment of Y/G, B, and R signal and 
+       GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    *(color_matrix->mtx_yg_adj0)    = (uint32_t)offset[VDC5_COLORMTX_OFFST_YG] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj0)   |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GG];
+    *(color_matrix->mtx_yg_adj1)    = (uint32_t)gain[VDC5_COLORMTX_GAIN_GB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj1)   |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GR];
+    *(color_matrix->mtx_cbb_adj0)   = (uint32_t)offset[VDC5_COLORMTX_OFFST_B] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj0)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BG];
+    *(color_matrix->mtx_cbb_adj1)   = (uint32_t)gain[VDC5_COLORMTX_GAIN_BB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj1)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BR];
+    *(color_matrix->mtx_crr_adj0)   = (uint32_t)offset[VDC5_COLORMTX_OFFST_R] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj0)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RG];
+    *(color_matrix->mtx_crr_adj1)   = (uint32_t)gain[VDC5_COLORMTX_GAIN_RB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj1)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RR];
+
+    /* Register update control register (IMGCNT_UPDATE/ADJx_UPDATE)
+       b0       IMGCNT_VEN/ADJx_VEN */
+    *(color_matrix->mtx_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function SetColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets sharpness
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness ON/OFF setting
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementSharpness (
+    const vdc5_onoff_t                          shp_h_on,
+    const vdc5_enhance_sharp_t          * const sharp_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc5_sharpness_ctrl_t * sharpness_ctrl;
+
+    if (sharp_param != NULL)
+    {
+        /* H1, adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp2)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H2, second adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (sharp_param->shp_h2_lpf_sel == VDC5_OFF)
+        {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)0x00000000u;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)VDC5_REG_BIT16;
+        }
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp3) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp4)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H3, third adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp5) = (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp6)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+    }
+
+    if (shp_h_on == VDC5_OFF)
+    {
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_BIT16;
+    }
+    else
+    {
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)VDC5_REG_BIT16;
+    }
+}   /* End of function SetImageEnhancementSharpness() */
+
+/**************************************************************************//**
+ * @brief       Sets LTI
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementLti (
+    const vdc5_onoff_t                          lti_h_on,
+    const vdc5_enhance_lti_t            * const lti_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc5_lti_ctrl_t * lti_ctrl;
+
+    if (lti_param != NULL)
+    {
+        /* H2, second adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI1];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (lti_param->lti_h2_lpf_sel == VDC5_OFF)
+        {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)0x00000000u;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)VDC5_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)lti_ctrl->lti_core;
+
+        /* H4, fourth adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI2];
+        /* Median filter reference pixel select */
+        if (lti_param->lti_h4_median_tap_sel == VDC5_LTI_MDFIL_SEL_ADJ2)
+        {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)0x00000000u;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)VDC5_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)lti_ctrl->lti_core;
+    }
+
+    if (lti_h_on == VDC5_OFF)
+    {
+        *(img_qlty_imp->adj_enh_lti1) &= (uint32_t)~VDC5_REG_BIT31;
+    }
+    else
+    {
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)VDC5_REG_BIT31;
+    }
+}   /* End of function SetImageEnhancementLti() */
+
+/**************************************************************************//**
+ * @brief       Sets alpha blending area of a rectangle
+ * @param[in]   pd_disp_rect        : Rectangular area for alpha blending
+ * @param[in]   img_synthesizer     : Image synthesizer registers
+ * @retval      None
+******************************************************************************/
+static void SetAlphaRectArea (
+    const vdc5_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc5_regaddr_img_synthesizer_t    * const img_synthesizer)
+{
+    uint32_t v_start;
+    uint32_t h_start;
+
+    if (pd_disp_rect != NULL)
+    {
+        v_start = *(img_synthesizer->gr_ab2) >> VDC5_REG_SHIFT_16;
+        h_start = *(img_synthesizer->gr_ab3) >> VDC5_REG_SHIFT_16;
+
+        v_start += (uint32_t)pd_disp_rect->vs_rel;
+        h_start += (uint32_t)pd_disp_rect->hs_rel;
+        /* If the start position exceeds the maximum bit width, the value should be saturated. */
+        if ((v_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u)
+        {
+            v_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+        }
+        if ((h_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u)
+        {
+            h_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+        }
+
+        *(img_synthesizer->gr_ab4) = (v_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->vw_rel;
+        *(img_synthesizer->gr_ab5) = (h_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->hw_rel;
+    }
+}   /* End of function SetAlphaRectArea() */
+
+/**************************************************************************//**
+ * @brief       Converts the color format from gr_format format into 24-bit RGB888 format
+ * @param[in]   gr_format           : Color format
+ * @param[in]   input_color         : Color data
+ * @retval      RGB888 color data
+******************************************************************************/
+static uint32_t ColorConversion (const vdc5_gr_format_t gr_format, const uint32_t input_color)
+{
+    uint32_t red;
+    uint32_t green;
+    uint32_t blue;
+    uint32_t conv_color;
+
+    conv_color = 0;
+    switch (gr_format)
+    {
+        case VDC5_GR_FORMAT_RGB565:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGB565_R_MASK) >> VDC5_REG_SHIFT_11));
+            green = ColorConversionFrom6to8((uint32_t)((input_color & VDC5_REG_RGB565_G_MASK) >> VDC5_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_RGB565_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+        break;
+        case VDC5_GR_FORMAT_RGB888:
+            conv_color = ColorConversionIntoAgbr(input_color);
+        break;
+        case VDC5_GR_FORMAT_ARGB1555:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_R_MASK) >> VDC5_REG_SHIFT_10));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_G_MASK) >> VDC5_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_ARGB1555_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+        break;
+        case VDC5_GR_FORMAT_ARGB4444:
+            red   = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_R_MASK) >> VDC5_REG_SHIFT_8));
+            green = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_G_MASK) >> VDC5_REG_SHIFT_4));
+            blue  = ColorConversionFrom4to8((uint32_t)(input_color & VDC5_REG_ARGB4444_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+        break;
+        case VDC5_GR_FORMAT_ARGB8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)(input_color & VDC5_REG_RGB_24BIT_MASK));
+        break;
+        case VDC5_GR_FORMAT_RGBA5551:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_R_MASK) >> VDC5_REG_SHIFT_11));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_G_MASK) >> VDC5_REG_SHIFT_6));
+            blue  = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_B_MASK) >> VDC5_REG_SHIFT_1));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+        break;
+        case VDC5_GR_FORMAT_RGBA8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)((input_color >> VDC5_REG_SHIFT_8) & VDC5_REG_RGB_24BIT_MASK));
+        break;
+        default:
+            /* DO NOTHING */
+        break;
+    }
+    return conv_color;
+}   /* End of function ColorConversion() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 4 bits value into 8 bits value
+ * @param[in]   color_value         : 4-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom4to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_4BIT_MASK;
+    color *= (uint32_t)VDC5_REG_EXTENSION_VALUE_17;
+
+    return color;
+}   /* End of function ColorConversionFrom4to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 5 bits value into 8 bits value
+ * @param[in]   color_value         : 5-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom5to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_5BIT_MASK;
+    color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_263 * VDC5_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_32;
+    /* Round off */
+    color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom5to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 6 bits value into 8 bits value
+ * @param[in]   color_value         : 6-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom6to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_6BIT_MASK;
+    color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_259 * VDC5_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_64;
+    /* Round off */
+    color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom6to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from ARGB8888 format into AGBR8888 format
+ * @param[in]   color_value         : ARGB8888 color data
+ * @retval      AGBR8888 color data
+******************************************************************************/
+static uint32_t ColorConversionIntoAgbr (const uint32_t color_value)
+{
+    uint32_t color_bgr;
+    uint32_t color_dat;
+
+    /* Green and blue */
+    color_bgr   = (uint32_t)(color_value << VDC5_REG_SHIFT_8);
+    color_bgr  &= (uint32_t)VDC5_REG_ARGB8888_GB_MASK;
+    /* Alpha */
+    color_dat   = (uint32_t)(color_value & VDC5_REG_ALPHA_8BIT);
+    color_bgr  |= color_dat;
+    /* Red */
+    color_dat   = (uint32_t)((color_value >> VDC5_REG_SHIFT_16) & VDC5_REG_COLOR_8BIT_MASK);
+    color_bgr  |= color_dat;
+
+    return color_bgr;
+}   /* End of function ColorConversionIntoAgbr() */
+
+/**************************************************************************//**
+ * @brief       Sets color lookup table (CLUT)
+ * @param[in]   param               : CLUT parameter
+ * @param[out]  regaddr_clut        : CLUT register top address
+ * @retval      None
+******************************************************************************/
+static void Set_Clut (const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut)
+{
+    uint32_t            data_len;
+    const uint32_t    * clut_tmp;
+
+    clut_tmp = param->clut;
+    for (data_len = 0; data_len < param->color_num; data_len++)
+    {
+        *regaddr_clut = *clut_tmp;
+        regaddr_clut++;
+        clut_tmp++;
+    }
+}   /* End of function Set_Clut() */
+
+/**************************************************************************//**
+ * @brief       Sets start threshold for gamma correction
+ * @param[in]   gam_th          : Start threshold of area 1 to 31
+ * @param[out]  gam_area        : Gamma correction registers for start threshold
+ * @retval      None
+******************************************************************************/
+static void Set_StartThreshold_Gamma (const uint8_t * gam_th, volatile uint32_t * const * const gam_area)
+{
+    uint32_t reg_index;
+
+    if (gam_th != NULL)
+    {
+        *(gam_area[0])  = (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th;
+        gam_th++;
+
+        for (reg_index = 1; reg_index < VDC5_GAM_AREA_REG_NUM; reg_index++)
+        {
+            *(gam_area[reg_index])  = (uint32_t)*gam_th << VDC5_REG_SHIFT_24;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th;
+            gam_th++;
+        }
+    }
+}   /* End of function Set_StartThreshold_Gamma() */
+
+/**************************************************************************//**
+ * @brief       Sets gain adjustment for gamma correction
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31
+ * @param[out]  gam_lut         : Gamma correction registers for gain adjustment
+ * @retval      None
+******************************************************************************/
+static void Set_GainAdjustment_Gamma (const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut)
+{
+    uint32_t reg_index;
+
+    if (gam_gain != NULL)
+    {
+        for (reg_index = 0; reg_index < VDC5_GAM_LUT_REG_NUM; reg_index++)
+        {
+            *(gam_lut[reg_index])  = (uint32_t)*gam_gain << VDC5_REG_SHIFT_16;
+            gam_gain++;
+            *(gam_lut[reg_index]) |= (uint32_t)*gam_gain;
+            gam_gain++;
+        }
+    }
+}   /* End of function Set_GainAdjustment_Gamma() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_register.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,286 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register.h
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDC5_REGISTER_H
+#define R_VDC5_REGISTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_GAM_LUT_REG_NUM    (16u)   /*!< The number of table setting register in gamma correction block */
+#define     VDC5_GAM_AREA_REG_NUM   (8u)    /*!< The number of area setting register in gamma correction block */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDC5 input controller register address list */
+typedef struct
+{
+    volatile uint32_t * inp_update;
+    volatile uint32_t * inp_sel_cnt;
+    volatile uint32_t * inp_ext_sync_cnt;
+    volatile uint32_t * inp_vsync_ph_adj;
+    volatile uint32_t * inp_dly_adj;
+    volatile uint32_t * imgcnt_update;
+    volatile uint32_t * imgcnt_nr_cnt0;
+    volatile uint32_t * imgcnt_nr_cnt1;
+} vdc5_regaddr_input_ctrl_t;
+
+/*! VDC5 scaler register address list */
+typedef struct
+{
+    volatile uint32_t * scl0_update;
+    volatile uint32_t * scl0_frc1;
+    volatile uint32_t * scl0_frc2;
+    volatile uint32_t * scl0_frc3;
+    volatile uint32_t * scl0_frc4;
+    volatile uint32_t * scl0_frc5;
+    volatile uint32_t * scl0_frc6;
+    volatile uint32_t * scl0_frc7;
+    volatile uint32_t * scl0_frc9;
+    volatile uint16_t * scl0_mon0;
+    volatile uint16_t * scl0_int;
+    volatile uint32_t * scl0_ds1;
+    volatile uint32_t * scl0_ds2;
+    volatile uint32_t * scl0_ds3;
+    volatile uint32_t * scl0_ds4;
+    volatile uint32_t * scl0_ds5;
+    volatile uint32_t * scl0_ds6;
+    volatile uint32_t * scl0_ds7;
+    volatile uint32_t * scl0_us1;
+    volatile uint32_t * scl0_us2;
+    volatile uint32_t * scl0_us3;
+    volatile uint32_t * scl0_us4;
+    volatile uint32_t * scl0_us5;
+    volatile uint32_t * scl0_us6;
+    volatile uint32_t * scl0_us7;
+    volatile uint32_t * scl0_us8;
+    volatile uint32_t * scl0_ovr1;
+    volatile uint32_t * scl1_update;
+    volatile uint32_t * scl1_wr1;
+    volatile uint32_t * scl1_wr2;
+    volatile uint32_t * scl1_wr3;
+    volatile uint32_t * scl1_wr4;
+    volatile uint32_t * scl1_wr5;
+    volatile uint32_t * scl1_wr6;
+    volatile uint32_t * scl1_wr7;
+    volatile uint32_t * scl1_wr8;
+    volatile uint32_t * scl1_wr9;
+    volatile uint32_t * scl1_wr10;
+    volatile uint32_t * scl1_wr11;
+    volatile uint32_t * scl1_mon1;
+    volatile uint32_t * scl1_pbuf0;
+    volatile uint32_t * scl1_pbuf1;
+    volatile uint32_t * scl1_pbuf2;
+    volatile uint32_t * scl1_pbuf3;
+    volatile uint32_t * scl1_pbuf_fld;
+    volatile uint32_t * scl1_pbuf_cnt;
+} vdc5_regaddr_scaler_t;
+
+/*! VDC5 image quality improver register address list */
+typedef struct
+{
+    volatile uint32_t * adj_update;
+    volatile uint32_t * adj_bkstr_set;
+    volatile uint32_t * adj_enh_tim1;
+    volatile uint32_t * adj_enh_tim2;
+    volatile uint32_t * adj_enh_tim3;
+    volatile uint32_t * adj_enh_shp1;
+    volatile uint32_t * adj_enh_shp2;
+    volatile uint32_t * adj_enh_shp3;
+    volatile uint32_t * adj_enh_shp4;
+    volatile uint32_t * adj_enh_shp5;
+    volatile uint32_t * adj_enh_shp6;
+    volatile uint32_t * adj_enh_lti1;
+    volatile uint32_t * adj_enh_lti2;
+} vdc5_regaddr_img_qlty_imp_t;
+
+/*! VDC5 color matrix register address list */
+typedef struct
+{
+    volatile uint32_t * mtx_update;
+    volatile uint32_t * mtx_mode;
+    volatile uint32_t * mtx_yg_adj0;
+    volatile uint32_t * mtx_yg_adj1;
+    volatile uint32_t * mtx_cbb_adj0;
+    volatile uint32_t * mtx_cbb_adj1;
+    volatile uint32_t * mtx_crr_adj0;
+    volatile uint32_t * mtx_crr_adj1;
+} vdc5_regaddr_color_matrix_t;
+
+/*! VDC5 image synthesizer register address list */
+typedef struct
+{
+    volatile uint32_t * gr_update;
+    volatile uint32_t * gr_flm_rd;
+    volatile uint32_t * gr_flm1;
+    volatile uint32_t * gr_flm2;
+    volatile uint32_t * gr_flm3;
+    volatile uint32_t * gr_flm4;
+    volatile uint32_t * gr_flm5;
+    volatile uint32_t * gr_flm6;
+    volatile uint32_t * gr_ab1;
+    volatile uint32_t * gr_ab2;
+    volatile uint32_t * gr_ab3;
+    volatile uint32_t * gr_ab4;
+    volatile uint32_t * gr_ab5;
+    volatile uint32_t * gr_ab6;
+    volatile uint32_t * gr_ab7;
+    volatile uint32_t * gr_ab8;
+    volatile uint32_t * gr_ab9;
+    volatile uint32_t * gr_ab10;
+    volatile uint32_t * gr_ab11;
+    volatile uint32_t * gr_base;
+    volatile uint32_t * gr_clut;
+    volatile uint32_t * gr_mon;
+} vdc5_regaddr_img_synthesizer_t;
+
+/*! VDC5 gamma correction register address list */
+typedef struct
+{
+    volatile uint32_t * gam_sw;
+    volatile uint32_t * gam_g_update;
+    volatile uint32_t * gam_g_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_g_area[VDC5_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_b_update;
+    volatile uint32_t * gam_b_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_b_area[VDC5_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_r_update;
+    volatile uint32_t * gam_r_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_r_area[VDC5_GAM_AREA_REG_NUM];
+} vdc5_regaddr_gamma_t;
+
+/*! VDC5 output controller register address list */
+typedef struct
+{
+    volatile uint32_t * tcon_update;
+    volatile uint32_t * tcon_tim;
+    volatile uint32_t * tcon_tim_stva1;
+    volatile uint32_t * tcon_tim_stva2;
+    volatile uint32_t * tcon_tim_stvb1;
+    volatile uint32_t * tcon_tim_stvb2;
+    volatile uint32_t * tcon_tim_sth1;
+    volatile uint32_t * tcon_tim_sth2;
+    volatile uint32_t * tcon_tim_stb1;
+    volatile uint32_t * tcon_tim_stb2;
+    volatile uint32_t * tcon_tim_cpv1;
+    volatile uint32_t * tcon_tim_cpv2;
+    volatile uint32_t * tcon_tim_pola1;
+    volatile uint32_t * tcon_tim_pola2;
+    volatile uint32_t * tcon_tim_polb1;
+    volatile uint32_t * tcon_tim_polb2;
+    volatile uint32_t * tcon_tim_de;
+    volatile uint32_t * out_update;
+    volatile uint32_t * out_set;
+    volatile uint32_t * out_bright1;
+    volatile uint32_t * out_bright2;
+    volatile uint32_t * out_contrast;
+    volatile uint32_t * out_pdtha;
+    volatile uint32_t * out_clk_phase;
+} vdc5_regaddr_output_ctrl_t;
+
+/*! VDC5 system controller register address list */
+typedef struct
+{
+    volatile uint32_t * syscnt_int1;
+    volatile uint32_t * syscnt_int2;
+    volatile uint32_t * syscnt_int4;
+    volatile uint32_t * syscnt_int5;
+    volatile uint16_t * syscnt_panel_clk;
+    volatile uint16_t * syscnt_clut;
+} vdc5_regaddr_system_ctrl_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdc5_regaddr_input_ctrl_t      vdc5_regaddr_input_ctrl;
+extern const vdc5_regaddr_scaler_t          vdc5_regaddr_scaler;
+extern const vdc5_regaddr_img_qlty_imp_t    vdc5_regaddr_img_qlty_imp;
+extern const vdc5_regaddr_color_matrix_t    vdc5_regaddr_color_matrix[VDC5_COLORMTX_NUM];
+extern const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_NUM];
+extern uint32_t                     * const vdc5_regaddr_clut[VDC5_GR_TYPE_NUM];
+extern const vdc5_regaddr_output_ctrl_t     vdc5_regaddr_output_ctrl;
+extern const vdc5_regaddr_gamma_t           vdc5_regaddr_gamma;
+extern const vdc5_regaddr_system_ctrl_t     vdc5_regaddr_system_ctrl;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_Initialize(const vdc5_init_t * const param);
+void VDC5_Terminate(void);
+void VDC5_VideoInput(const vdc5_input_t * const param);
+void VDC5_SyncControl(const vdc5_sync_ctrl_t * const param);
+void VDC5_DisplayOutput(const vdc5_output_t * const param);
+void VDC5_WriteDataControl(const vdc5_write_t * const param);
+void VDC5_ChangeWriteProcess(const vdc5_write_chg_t * const param);
+void VDC5_ReadDataControl(const vdc5_graphics_type_t graphics_id, const vdc5_read_t * const param);
+void VDC5_ChangeReadProcess(const vdc5_graphics_type_t graphics_id, const vdc5_read_chg_t * const param);
+void VDC5_StartProcess(const vdc5_layer_id_t layer_id, const vdc5_start_t * const param);
+void VDC5_StopProcess(const vdc5_layer_id_t layer_id);
+void VDC5_VideoNoiseReduction(const vdc5_onoff_t nr1d_on, const vdc5_noise_reduction_t * const param);
+void VDC5_ImageColorMatrix(const vdc5_color_matrix_t * const param);
+void VDC5_ImageEnhancement(
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area);
+void VDC5_ImageBlackStretch(
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param);
+void VDC5_AlphaBlending(const vdc5_graphics_type_t graphics_id, const vdc5_alpha_blending_t * const param);
+void VDC5_AlphaBlendingRect(
+    const vdc5_graphics_type_t                  graphics_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param);
+void VDC5_Chromakey(
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param);
+void VDC5_CLUT(const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param);
+void VDC5_DisplayCalibration(const vdc5_disp_calibration_t * const param);
+void VDC5_GammaCorrection(const vdc5_onoff_t gam_on, const vdc5_gamma_correction_t * const param);
+
+void VDC5_Int_Disable(void);
+void VDC5_Int_SetInterrupt(const vdc5_int_t * const param);
+
+
+#endif  /* R_VDC5_REGISTER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_register_address.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,378 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register_address.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_CH0_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF6000u)
+#define     VDC5_CH0_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF6800u)
+#define     VDC5_CH0_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF6C00u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDC5 input controller register address list */
+const vdc5_regaddr_input_ctrl_t vdc5_regaddr_input_ctrl =
+{
+    &VDC50.INP_UPDATE,
+    &VDC50.INP_SEL_CNT,
+    &VDC50.INP_EXT_SYNC_CNT,
+    &VDC50.INP_VSYNC_PH_ADJ,
+    &VDC50.INP_DLY_ADJ,
+    &VDC50.IMGCNT_UPDATE,
+    &VDC50.IMGCNT_NR_CNT0,
+    &VDC50.IMGCNT_NR_CNT1
+};
+
+/* VDC5 scaler register address list */
+const vdc5_regaddr_scaler_t vdc5_regaddr_scaler =
+{
+    &VDC50.SC0_SCL0_UPDATE,
+    &VDC50.SC0_SCL0_FRC1,
+    &VDC50.SC0_SCL0_FRC2,
+    &VDC50.SC0_SCL0_FRC3,
+    &VDC50.SC0_SCL0_FRC4,
+    &VDC50.SC0_SCL0_FRC5,
+    &VDC50.SC0_SCL0_FRC6,
+    &VDC50.SC0_SCL0_FRC7,
+    &VDC50.SC0_SCL0_FRC9,
+    &VDC50.SC0_SCL0_MON0,
+    &VDC50.SC0_SCL0_INT,
+    &VDC50.SC0_SCL0_DS1,
+    &VDC50.SC0_SCL0_DS2,
+    &VDC50.SC0_SCL0_DS3,
+    &VDC50.SC0_SCL0_DS4,
+    &VDC50.SC0_SCL0_DS5,
+    &VDC50.SC0_SCL0_DS6,
+    &VDC50.SC0_SCL0_DS7,
+    &VDC50.SC0_SCL0_US1,
+    &VDC50.SC0_SCL0_US2,
+    &VDC50.SC0_SCL0_US3,
+    &VDC50.SC0_SCL0_US4,
+    &VDC50.SC0_SCL0_US5,
+    &VDC50.SC0_SCL0_US6,
+    &VDC50.SC0_SCL0_US7,
+    &VDC50.SC0_SCL0_US8,
+    &VDC50.SC0_SCL0_OVR1,
+    &VDC50.SC0_SCL1_UPDATE,
+    &VDC50.SC0_SCL1_WR1,
+    &VDC50.SC0_SCL1_WR2,
+    &VDC50.SC0_SCL1_WR3,
+    &VDC50.SC0_SCL1_WR4,
+    &VDC50.SC0_SCL1_WR5,
+    &VDC50.SC0_SCL1_WR6,
+    &VDC50.SC0_SCL1_WR7,
+    &VDC50.SC0_SCL1_WR8,
+    &VDC50.SC0_SCL1_WR9,
+    &VDC50.SC0_SCL1_WR10,
+    &VDC50.SC0_SCL1_WR11,
+    &VDC50.SC0_SCL1_MON1,
+    &VDC50.SC0_SCL1_PBUF0,
+    &VDC50.SC0_SCL1_PBUF1,
+    &VDC50.SC0_SCL1_PBUF2,
+    &VDC50.SC0_SCL1_PBUF3,
+    &VDC50.SC0_SCL1_PBUF_FLD,
+    &VDC50.SC0_SCL1_PBUF_CNT
+};
+
+/* VDC5 image quality improver register address list */
+const vdc5_regaddr_img_qlty_imp_t vdc5_regaddr_img_qlty_imp =
+{
+    &VDC50.ADJ0_UPDATE,
+    &VDC50.ADJ0_BKSTR_SET,
+    &VDC50.ADJ0_ENH_TIM1,
+    &VDC50.ADJ0_ENH_TIM2,
+    &VDC50.ADJ0_ENH_TIM3,
+    &VDC50.ADJ0_ENH_SHP1,
+    &VDC50.ADJ0_ENH_SHP2,
+    &VDC50.ADJ0_ENH_SHP3,
+    &VDC50.ADJ0_ENH_SHP4,
+    &VDC50.ADJ0_ENH_SHP5,
+    &VDC50.ADJ0_ENH_SHP6,
+    &VDC50.ADJ0_ENH_LTI1,
+    &VDC50.ADJ0_ENH_LTI2
+};
+
+/* VDC5 color matrix register address list */
+const vdc5_regaddr_color_matrix_t vdc5_regaddr_color_matrix[VDC5_COLORMTX_NUM] =
+{
+    {   /* Input Controller */
+        &VDC50.IMGCNT_UPDATE,
+        &VDC50.IMGCNT_MTX_MODE,
+        &VDC50.IMGCNT_MTX_YG_ADJ0,
+        &VDC50.IMGCNT_MTX_YG_ADJ1,
+        &VDC50.IMGCNT_MTX_CBB_ADJ0,
+        &VDC50.IMGCNT_MTX_CBB_ADJ1,
+        &VDC50.IMGCNT_MTX_CRR_ADJ0,
+        &VDC50.IMGCNT_MTX_CRR_ADJ1
+    },
+    {   /* Image quality improver 0 */
+        &VDC50.ADJ0_UPDATE,
+        &VDC50.ADJ0_MTX_MODE,
+        &VDC50.ADJ0_MTX_YG_ADJ0,
+        &VDC50.ADJ0_MTX_YG_ADJ1,
+        &VDC50.ADJ0_MTX_CBB_ADJ0,
+        &VDC50.ADJ0_MTX_CBB_ADJ1,
+        &VDC50.ADJ0_MTX_CRR_ADJ0,
+        &VDC50.ADJ0_MTX_CRR_ADJ1
+    }
+};
+
+/* VDC5 image synthesizer register address list */
+const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_GR_TYPE_NUM] =
+{
+    {   /* GR0 */
+        &VDC50.GR0_UPDATE,
+        &VDC50.GR0_FLM_RD,
+        &VDC50.GR0_FLM1,
+        &VDC50.GR0_FLM2,
+        &VDC50.GR0_FLM3,
+        &VDC50.GR0_FLM4,
+        &VDC50.GR0_FLM5,
+        &VDC50.GR0_FLM6,
+        &VDC50.GR0_AB1,
+        &VDC50.GR0_AB2,
+        &VDC50.GR0_AB3,
+        NULL,
+        NULL,
+        NULL,
+        &VDC50.GR0_AB7,
+        &VDC50.GR0_AB8,
+        &VDC50.GR0_AB9,
+        &VDC50.GR0_AB10,
+        &VDC50.GR0_AB11,
+        &VDC50.GR0_BASE,
+        &VDC50.GR0_CLUT,
+        NULL
+    },
+    {   /* GR2 */
+        &VDC50.GR2_UPDATE,
+        &VDC50.GR2_FLM_RD,
+        &VDC50.GR2_FLM1,
+        &VDC50.GR2_FLM2,
+        &VDC50.GR2_FLM3,
+        &VDC50.GR2_FLM4,
+        &VDC50.GR2_FLM5,
+        &VDC50.GR2_FLM6,
+        &VDC50.GR2_AB1,
+        &VDC50.GR2_AB2,
+        &VDC50.GR2_AB3,
+        &VDC50.GR2_AB4,
+        &VDC50.GR2_AB5,
+        &VDC50.GR2_AB6,
+        &VDC50.GR2_AB7,
+        &VDC50.GR2_AB8,
+        &VDC50.GR2_AB9,
+        &VDC50.GR2_AB10,
+        &VDC50.GR2_AB11,
+        &VDC50.GR2_BASE,
+        &VDC50.GR2_CLUT,
+        &VDC50.GR2_MON
+    },
+    {   /* GR3 */
+        &VDC50.GR3_UPDATE,
+        &VDC50.GR3_FLM_RD,
+        &VDC50.GR3_FLM1,
+        &VDC50.GR3_FLM2,
+        &VDC50.GR3_FLM3,
+        &VDC50.GR3_FLM4,
+        &VDC50.GR3_FLM5,
+        &VDC50.GR3_FLM6,
+        &VDC50.GR3_AB1,
+        &VDC50.GR3_AB2,
+        &VDC50.GR3_AB3,
+        &VDC50.GR3_AB4,
+        &VDC50.GR3_AB5,
+        &VDC50.GR3_AB6,
+        &VDC50.GR3_AB7,
+        &VDC50.GR3_AB8,
+        &VDC50.GR3_AB9,
+        &VDC50.GR3_AB10,
+        &VDC50.GR3_AB11,
+        &VDC50.GR3_BASE,
+        &VDC50.GR3_CLUT_INT,
+        &VDC50.GR3_MON
+    }
+};
+
+/* VDC5 CLUT register address list */
+uint32_t * const vdc5_regaddr_clut[VDC5_GR_TYPE_NUM] =
+{
+    &VDC5_CH0_GR0_CLUT_TBL,
+    &VDC5_CH0_GR2_CLUT_TBL,
+    &VDC5_CH0_GR3_CLUT_TBL
+};
+
+/* VDC5 output controller register address list */
+const vdc5_regaddr_output_ctrl_t vdc5_regaddr_output_ctrl =
+{
+    &VDC50.TCON_UPDATE,
+    &VDC50.TCON_TIM,
+    &VDC50.TCON_TIM_STVA1,
+    &VDC50.TCON_TIM_STVA2,
+    &VDC50.TCON_TIM_STVB1,
+    &VDC50.TCON_TIM_STVB2,
+    &VDC50.TCON_TIM_STH1,
+    &VDC50.TCON_TIM_STH2,
+    &VDC50.TCON_TIM_STB1,
+    &VDC50.TCON_TIM_STB2,
+    &VDC50.TCON_TIM_CPV1,
+    &VDC50.TCON_TIM_CPV2,
+    &VDC50.TCON_TIM_POLA1,
+    &VDC50.TCON_TIM_POLA2,
+    &VDC50.TCON_TIM_POLB1,
+    &VDC50.TCON_TIM_POLB2,
+    &VDC50.TCON_TIM_DE,
+    &VDC50.OUT_UPDATE,
+    &VDC50.OUT_SET,
+    &VDC50.OUT_BRIGHT1,
+    &VDC50.OUT_BRIGHT2,
+    &VDC50.OUT_CONTRAST,
+    &VDC50.OUT_PDTHA,
+    &VDC50.OUT_CLK_PHASE
+};
+
+/* VDC5 gamma correction register address list */
+const vdc5_regaddr_gamma_t vdc5_regaddr_gamma =
+{
+    &VDC50.GAM_SW,
+    &VDC50.GAM_G_UPDATE,
+    {
+        &VDC50.GAM_G_LUT1,
+        &VDC50.GAM_G_LUT2,
+        &VDC50.GAM_G_LUT3,
+        &VDC50.GAM_G_LUT4,
+        &VDC50.GAM_G_LUT5,
+        &VDC50.GAM_G_LUT6,
+        &VDC50.GAM_G_LUT7,
+        &VDC50.GAM_G_LUT8,
+        &VDC50.GAM_G_LUT9,
+        &VDC50.GAM_G_LUT10,
+        &VDC50.GAM_G_LUT11,
+        &VDC50.GAM_G_LUT12,
+        &VDC50.GAM_G_LUT13,
+        &VDC50.GAM_G_LUT14,
+        &VDC50.GAM_G_LUT15,
+        &VDC50.GAM_G_LUT16
+    },
+    {
+        &VDC50.GAM_G_AREA1,
+        &VDC50.GAM_G_AREA2,
+        &VDC50.GAM_G_AREA3,
+        &VDC50.GAM_G_AREA4,
+        &VDC50.GAM_G_AREA5,
+        &VDC50.GAM_G_AREA6,
+        &VDC50.GAM_G_AREA7,
+        &VDC50.GAM_G_AREA8
+    },
+    &VDC50.GAM_B_UPDATE,
+    {
+        &VDC50.GAM_B_LUT1,
+        &VDC50.GAM_B_LUT2,
+        &VDC50.GAM_B_LUT3,
+        &VDC50.GAM_B_LUT4,
+        &VDC50.GAM_B_LUT5,
+        &VDC50.GAM_B_LUT6,
+        &VDC50.GAM_B_LUT7,
+        &VDC50.GAM_B_LUT8,
+        &VDC50.GAM_B_LUT9,
+        &VDC50.GAM_B_LUT10,
+        &VDC50.GAM_B_LUT11,
+        &VDC50.GAM_B_LUT12,
+        &VDC50.GAM_B_LUT13,
+        &VDC50.GAM_B_LUT14,
+        &VDC50.GAM_B_LUT15,
+        &VDC50.GAM_B_LUT16
+    },
+    {
+        &VDC50.GAM_B_AREA1,
+        &VDC50.GAM_B_AREA2,
+        &VDC50.GAM_B_AREA3,
+        &VDC50.GAM_B_AREA4,
+        &VDC50.GAM_B_AREA5,
+        &VDC50.GAM_B_AREA6,
+        &VDC50.GAM_B_AREA7,
+        &VDC50.GAM_B_AREA8
+    },
+    &VDC50.GAM_R_UPDATE,
+    {
+        &VDC50.GAM_R_LUT1,
+        &VDC50.GAM_R_LUT2,
+        &VDC50.GAM_R_LUT3,
+        &VDC50.GAM_R_LUT4,
+        &VDC50.GAM_R_LUT5,
+        &VDC50.GAM_R_LUT6,
+        &VDC50.GAM_R_LUT7,
+        &VDC50.GAM_R_LUT8,
+        &VDC50.GAM_R_LUT9,
+        &VDC50.GAM_R_LUT10,
+        &VDC50.GAM_R_LUT11,
+        &VDC50.GAM_R_LUT12,
+        &VDC50.GAM_R_LUT13,
+        &VDC50.GAM_R_LUT14,
+        &VDC50.GAM_R_LUT15,
+        &VDC50.GAM_R_LUT16
+    },
+    {
+        &VDC50.GAM_R_AREA1,
+        &VDC50.GAM_R_AREA2,
+        &VDC50.GAM_R_AREA3,
+        &VDC50.GAM_R_AREA4,
+        &VDC50.GAM_R_AREA5,
+        &VDC50.GAM_R_AREA6,
+        &VDC50.GAM_R_AREA7,
+        &VDC50.GAM_R_AREA8
+    }
+};
+
+/* VDC5 system controller register address list */
+const vdc5_regaddr_system_ctrl_t vdc5_regaddr_system_ctrl =
+{
+    &VDC50.SYSCNT_INT1,
+    &VDC50.SYSCNT_INT2,
+    &VDC50.SYSCNT_INT4,
+    &VDC50.SYSCNT_INT5,
+    &VDC50.SYSCNT_PANEL_CLK,
+    &VDC50.SYSCNT_CLUT
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_shared_param.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,785 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_shared_param.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver shared parameter processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Two to the power of eleven */
+#define     TWO_POWER_ELEVEN                (2048)
+
+#define     VDC5_SPARA_DIV_2                (2)
+#define     VDC5_SPARA_DIV_256              (256) 
+
+/* Color Conversion Value */
+#define     VDC5_SPARA_COLOR_CONV_RANGE     (255)
+#define     VDC5_SPARA_COLOR_CONV_OFFSET    (128)
+
+/* Color mask data */
+#define     VDC5_SPARA_COLOR_8BIT_MASK      (0x000000FFu)
+
+/* shift value */
+#define     VDC5_SPARA_SHIFT_16             (16u)
+#define     VDC5_SPARA_SHIFT_8              (8u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct
+{
+    vdc5_color_space_t      color_sp_in;    /*!< Color space of the input video image signal */
+    uint32_t                bg_color_rgb;   /*!< Background color in 24-bit RGB color format */
+    uint32_t                bg_color_crycb; /*!< Background color in 24-bit CrYCb format */
+} vdc5_shared_param_common_t;
+
+typedef struct
+{
+    vdc5_wr_md_t            res_ds_wr_md;   /*!< Frame buffer writing mode for image processing */
+    vdc5_res_inter_t        res_inter;      /*!< Field operating mode select */
+    vdc5_color_space_t      color_sp_fb_wr; /*!< Color space of the frame buffer writing format */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+    vdc5_width_read_fb_t    width_wr_fb;    /*!< Size of the image output by scaling-down control block */
+} vdc5_shared_param_scaling_t;
+
+typedef struct
+{
+    vdc5_gr_ln_off_dir_t    gr_ln_off_dir;      /*!< Line offset address direction of the frame buffer */
+    vdc5_gr_flm_sel_t       gr_flm_sel;         /*!< Frame buffer address setting signal */
+    vdc5_gr_format_t        gr_format;          /*!< Format of the frame buffer read signal */
+    vdc5_color_space_t      color_sp_fb_rd;     /*!< Color space of the frame buffer reading format */
+    vdc5_onoff_t            adj_sel;            /*!< Folding handling (on/off) */
+    vdc5_period_rect_t      gr_grc;             /*!< Graphics display area */
+    vdc5_width_read_fb_t    width_read_fb;      /*!< Size of the frame buffer to be read */
+} vdc5_shared_param_graphics_t;
+
+typedef struct
+{
+    vdc5_resource_state_t   rsrc_panel_clock;
+    vdc5_resource_state_t   rsrc_video_input;
+    vdc5_resource_state_t   rsrc_vsync_signal;
+    vdc5_resource_state_t   rsrc_lcd_panel;
+} vdc5_shared_param_resource_t;
+
+/*! Read/write process state */
+typedef enum
+{
+    VDC5_RW_PROC_STATE_DISABLE   = 0,
+    VDC5_RW_PROC_STATE_ENABLE    = 1
+} vdc5_rw_proc_state_t;
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer(const vdc5_resource_type_t rsrc_type);
+static uint32_t SumProduct(
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset);
+
+static vdc5_shared_param_common_t   param_common;
+static vdc5_shared_param_scaling_t  param_scaling;
+static vdc5_shared_param_graphics_t param_graphics[VDC5_GR_TYPE_NUM];
+
+static vdc5_resource_state_t        layer_resource[VDC5_LAYER_ID_NUM];
+static vdc5_rw_proc_state_t         rw_proc_state[VDC5_LAYER_ID_NUM];
+
+static vdc5_onoff_t                 video_input_flag = VDC5_OFF;
+
+
+/**************************************************************************//**
+ * @brief       Initializes variables of the VDC5 driver
+ * @param[in]   void
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmInit (void)
+{
+    int32_t                         layer_id_num;
+    vdc5_shared_param_common_t    * shared_param_common;
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+    vdc5_graphics_type_t            graphics_id;
+
+    for (layer_id_num = 0; layer_id_num < VDC5_LAYER_ID_NUM; layer_id_num++)
+    {
+        layer_resource[layer_id_num] = VDC5_RESOURCE_ST_INVALID;
+        rw_proc_state[layer_id_num]  = VDC5_RW_PROC_STATE_DISABLE;
+    }
+
+    shared_param_common = &param_common;
+
+    shared_param_common->bg_color_rgb   = (uint32_t)0u;             /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_crycb = (uint32_t)0u;             /* Background color in 24-bit CrYCb format */
+
+    if (video_input_flag == VDC5_OFF)
+    {
+        shared_param_common->color_sp_in    = VDC5_COLOR_SPACE_GBR; /* Color space of the input video image signal */
+    }
+
+    shared_param_scaling = &param_scaling;
+
+    /* Frame buffer writing mode for image processing */
+    shared_param_scaling->res_ds_wr_md      = VDC5_WR_MD_NORMAL;
+    shared_param_scaling->res_inter         = VDC5_RES_INTER_PROGRESSIVE;   /* Field operating mode select */
+    /* Color space of the frame buffer writing format */
+    shared_param_scaling->color_sp_fb_wr    = VDC5_COLOR_SPACE_GBR;
+    /* Frame buffer base address for bottom */
+    shared_param_scaling->btm_base          = NULL;
+    /* Size of the image output by scaling-down control block */
+    shared_param_scaling->width_wr_fb.in_vw = (uint16_t)0;
+    shared_param_scaling->width_wr_fb.in_hw = (uint16_t)0;
+
+    for (graphics_id = VDC5_GR_TYPE_GR0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++)
+    {
+        shared_param_graphics = &param_graphics[graphics_id];
+
+        /* Line offset address direction of the frame buffer */
+        shared_param_graphics->gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC;
+        /* Frame buffer address setting signal */
+        shared_param_graphics->gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM;
+        /* Format of the frame buffer read signal */
+        shared_param_graphics->gr_format = VDC5_GR_FORMAT_RGB565;
+        /* Color space of the frame buffer reading format */
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+        /* Folding handling (on/off) */
+        shared_param_graphics->adj_sel = VDC5_OFF;
+        /* Graphics display area */
+        shared_param_graphics->gr_grc.vs = (uint16_t)0;
+        shared_param_graphics->gr_grc.vw = (uint16_t)0;
+        shared_param_graphics->gr_grc.hs = (uint16_t)0;
+        shared_param_graphics->gr_grc.hw = (uint16_t)0;
+        /* Size of the frame buffer to be read */
+        shared_param_graphics->width_read_fb.in_vw = (uint16_t)0;
+        shared_param_graphics->width_read_fb.in_hw = (uint16_t)0;
+    }
+}   /* End of function VDC5_ShrdPrmInit() */
+
+/**************************************************************************//**
+ * @brief       Sets the video input setup parameter
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetInputParam (const vdc5_input_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    video_input_flag = VDC5_ON;
+
+    shared_param_common = &param_common;
+
+    /* Color space */
+    if ((param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+        (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+        (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB565))
+    {
+        shared_param_common->color_sp_in = VDC5_COLOR_SPACE_GBR;
+    }
+    else
+    {
+        shared_param_common->color_sp_in = VDC5_COLOR_SPACE_YCBCR;
+    }
+}   /* End of function VDC5_ShrdPrmSetInputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the display output configuration parameter
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetOutputParam (const vdc5_output_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+    int32_t                         red;
+    int32_t                         green;
+    int32_t                         blue;
+    uint32_t                        y_val;
+    uint32_t                        cb_val;
+    uint32_t                        cr_val;
+
+    shared_param_common = &param_common;
+
+    /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_rgb = param->bg_color;
+
+    red     = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_16) & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    green   = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_8)  & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    blue    = (int32_t)( param->bg_color                         & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    /* Y */
+    y_val = SumProduct(
+        red,
+        green,
+        blue,
+        (int32_t)VDC5_COLORCONV_Y_R,
+        (int32_t)VDC5_COLORCONV_Y_G,
+        (int32_t)VDC5_COLORCONV_Y_B,
+        0);
+    /* Cb */
+    cb_val = SumProduct(
+        red,
+        green,
+        blue,
+        (int32_t)VDC5_COLORCONV_CB_R,
+        (int32_t)VDC5_COLORCONV_CB_G,
+        (int32_t)VDC5_COLORCONV_CB_B,
+        (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+    /* Cr */
+    cr_val = SumProduct(
+        red,
+        green,
+        blue,
+        (int32_t)VDC5_COLORCONV_CR_R,
+        (int32_t)VDC5_COLORCONV_CR_G,
+        (int32_t)VDC5_COLORCONV_CR_B,
+        (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+    /* Background color in 24-bit CrYCb format */
+    shared_param_common->bg_color_crycb = (uint32_t)((cr_val << VDC5_SPARA_SHIFT_16) | (y_val << VDC5_SPARA_SHIFT_8) | cb_val);
+}   /* End of function VDC5_ShrdPrmSetOutputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write control parameter
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetWriteParam (const vdc5_write_t * const param)
+{
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling;
+
+    /* Frame buffer writing mode for image processing */
+    shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+    /* Field operating mode select */
+    shared_param_scaling->res_inter = param->res_inter;
+
+    /* Color space of the frame buffer */
+    if ((param->res_md == VDC5_RES_MD_YCBCR422) || (param->res_md == VDC5_RES_MD_YCBCR444))
+    {
+        shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_YCBCR;
+    }
+    else
+    {
+        shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_GBR;
+    }
+
+    /* Frame buffer base address for bottom */
+    shared_param_scaling->btm_base = param->btm_base;
+    /* Size of the image output by scaling-down control block */
+    shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+    shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+}   /* End of function VDC5_ShrdPrmSetWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write change parameter
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgWriteParam (const vdc5_write_chg_t * const param)
+{
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling;
+
+    /* Frame buffer writing mode for image processing */
+    shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+    /* Size of the image output by scaling-down control block */
+    shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+    shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+}   /* End of function VDC5_ShrdPrmSetChgWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read control parameter
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetReadParam (const vdc5_graphics_type_t graphics_id, const vdc5_read_t * const param)
+{
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[graphics_id];
+
+    /* Line offset address direction of the frame buffer */
+    shared_param_graphics->gr_ln_off_dir = param->gr_ln_off_dir;
+
+    /* Frame buffer address setting signal */
+    shared_param_graphics->gr_flm_sel = param->gr_flm_sel;
+
+    /* Format of the frame buffer read signal */
+    shared_param_graphics->gr_format = param->gr_format;
+ 
+    /* Color space of the frame buffer */
+    if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444))
+    {
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_YCBCR;
+    }
+    else
+    {
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+    }
+
+    /* Folding handling (on/off) */
+    shared_param_graphics->adj_sel = param->adj_sel;
+
+    /* Graphics display area */
+    shared_param_graphics->gr_grc = param->gr_grc;
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL)
+    {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    }
+    else
+    {   /* If not specified, ... */
+        if (param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM)
+        {   /* The size of the frame buffer to be read is assumed that it is the same as
+               the width of the graphics display area. */
+            shared_param_graphics->width_read_fb.in_vw = param->gr_grc.vw;
+            shared_param_graphics->width_read_fb.in_hw = param->gr_grc.hw;
+        }
+        else
+        {   /* The size of the image output by scaling-down control block is used for the size of the frame buffer
+               to be read when a frame buffer address setting signal links to the video image signals. */
+            shared_param_graphics->width_read_fb = param_scaling.width_wr_fb;
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetReadParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read change parameter
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgReadParam (const vdc5_graphics_type_t graphics_id, const vdc5_read_chg_t * const param)
+{
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[graphics_id];
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL)
+    {
+        shared_param_graphics->gr_grc = *(param->gr_grc);
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL)
+    {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    }
+}   /* End of function VDC5_ShrdPrmSetChgReadParam() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the input video image signal
+ * @param[in]   void
+ * @retval      Color space of the input video image signal
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace (void)
+{
+    return param_common.color_sp_in;
+}   /* End of function VDC5_ShrdPrmGetColorSpace() */
+
+/**************************************************************************//**
+ * @brief       Get the background color
+ * @param[in]   color_space             : Color space
+ * @retval      Background color in 24-bit RGB color format or CrYCb format
+ *****************************************************************************/
+uint32_t VDC5_ShrdPrmGetBgColor (const vdc5_color_space_t color_space)
+{
+    return (color_space == VDC5_COLOR_SPACE_GBR) ? param_common.bg_color_rgb : param_common.bg_color_crycb;
+}   /* End of function VDC5_ShrdPrmGetBgColor() */
+
+/**************************************************************************//**
+ * @brief       Get the frame buffer writing mode for image processing
+ * @param[in]   void
+ * @retval      Frame buffer writing mode for image processing
+ *****************************************************************************/
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode (void)
+{
+    return param_scaling.res_ds_wr_md;
+}   /* End of function VDC5_ShrdPrmGetWritingMode() */
+
+/**************************************************************************//**
+ * @brief       
+ * @param[in]   void
+ * @retval      Field operating mode select
+ *****************************************************************************/
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace (void)
+{
+    return param_scaling.res_inter;
+}   /* End of function VDC5_ShrdPrmGetInterlace() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer writing format
+ * @param[in]   void
+ * @retval      Color space of the frame buffer writing format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr (void)
+{
+    return param_scaling.color_sp_fb_wr;
+}   /* End of function VDC5_ShrdPrmGetColorSpaceFbWr() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer base address for bottom
+ * @param[in]   void
+ * @retval      Frame buffer base address for bottom
+ *****************************************************************************/
+void * VDC5_ShrdPrmGetFrBuffBtm (void)
+{
+    return param_scaling.btm_base;
+}   /* End of function VDC5_ShrdPrmGetFrBuffBtm() */
+
+/**************************************************************************//**
+ * @brief       Gets the line offset address direction of the frame buffer
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Line offset address direction of the frame buffer
+ *****************************************************************************/
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir (const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].gr_ln_off_dir;
+}   /* End of function VDC5_ShrdPrmGetLineOfsAddrDir() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer address setting signal
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Frame buffer address setting signal
+ *****************************************************************************/
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig (const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].gr_flm_sel;
+}   /* End of function VDC5_ShrdPrmGetSelFbAddrSig() */
+
+/**************************************************************************//**
+ * @brief       Gets the format of the frame buffer read signal
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Format of the frame buffer read signal
+ *****************************************************************************/
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat (const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].gr_format;
+}   /* End of function VDC5_ShrdPrmGetGraphicsFormat() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer reading format
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Color space of the frame buffer reading format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd (const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].color_sp_fb_rd;
+}   /* End of function VDC5_ShrdPrmGetColorSpaceFbRd() */
+
+/**************************************************************************//**
+ * @brief       Gets the folding handling
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Folding handling (on/off)
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding (const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].adj_sel;
+}   /* End of function VDC5_ShrdPrmGetMeasureFolding() */
+
+/**************************************************************************//**
+ * @brief       Gets the graphics display area
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Graphics display area
+ *****************************************************************************/
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea (const vdc5_graphics_type_t graphics_id)
+{
+    return &param_graphics[graphics_id].gr_grc;
+}   /* End of function VDC5_ShrdPrmGetDisplayArea() */
+
+/**************************************************************************//**
+ * @brief       Gets the size of the frame buffer to be read
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Size of the frame buffer to be read
+ *****************************************************************************/
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd (const vdc5_graphics_type_t graphics_id)
+{
+    return &param_graphics[graphics_id].width_read_fb;
+}   /* End of function VDC5_ShrdPrmGetFrBuffWidth_Rd() */
+
+/**************************************************************************//**
+ * @brief       Updates the resource state
+ * @param[in]   rsrc_type               : Resource type
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetResource (const vdc5_resource_type_t rsrc_type, const vdc5_resource_state_t rsrc_state)
+{
+    vdc5_resource_state_t * resource_state;
+
+    resource_state = GetResourceStatePointer(rsrc_type);
+    if (resource_state != NULL)
+    {
+        *resource_state = rsrc_state;
+    }
+}   /* End of function VDC5_ShrdPrmSetResource() */
+
+/**************************************************************************//**
+ * @brief       Updates the layer resource state
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetLayerResource (const vdc5_layer_id_t layer_id, const vdc5_resource_state_t rsrc_state)
+{
+    uint32_t layer_id_num;
+
+    if (layer_id != VDC5_LAYER_ID_ALL)
+    {
+        layer_resource[layer_id] = rsrc_state;
+    }
+    else
+    {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++)
+        {
+            if (rw_proc_state[layer_id_num] == VDC5_RW_PROC_STATE_DISABLE)
+            {
+                layer_resource[layer_id_num] = rsrc_state;
+            }
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the resource state
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetResource (const vdc5_resource_type_t rsrc_type)
+{
+    vdc5_resource_state_t * resource_state;
+    vdc5_resource_state_t   rsrc_state;
+
+    rsrc_state = VDC5_RESOURCE_ST_INVALID;
+
+    resource_state = GetResourceStatePointer(rsrc_type);
+    if (resource_state != NULL)
+    {
+        rsrc_state = *resource_state;
+    }
+    return rsrc_state;
+}   /* End of function VDC5_ShrdPrmGetResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the layer resource state
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Layer resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource (const vdc5_layer_id_t layer_id)
+{
+    return layer_resource[layer_id];
+}   /* End of function VDC5_ShrdPrmGetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing enabled
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcEnable (const vdc5_layer_id_t layer_id)
+{
+    if (layer_id != VDC5_LAYER_ID_ALL)
+    {
+        if (layer_resource[layer_id] != VDC5_RESOURCE_ST_INVALID)
+        {
+            rw_proc_state[layer_id] = VDC5_RW_PROC_STATE_ENABLE;
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetRwProcEnable() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing disabled
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcDisable (const vdc5_layer_id_t layer_id)
+{
+    if (layer_id != VDC5_LAYER_ID_ALL)
+    {
+        if (layer_resource[layer_id] != VDC5_RESOURCE_ST_INVALID)
+        {
+            rw_proc_state[layer_id] = VDC5_RW_PROC_STATE_DISABLE;
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetRwProcDisable() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is ready or not
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is disabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The specified layer is not ready.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady (const vdc5_layer_id_t layer_id)
+{
+    vdc5_resource_state_t state;
+
+    if ((layer_resource[layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+        (rw_proc_state[layer_id] == VDC5_RW_PROC_STATE_DISABLE))
+    {
+        state = VDC5_RESOURCE_ST_VALID;
+    }
+    else
+    {
+        state = VDC5_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetRwProcReady() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is already run or not
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is enabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The specified layer is not enabled.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled (const vdc5_layer_id_t layer_id)
+{
+    vdc5_resource_state_t state;
+
+    if ((layer_resource[layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+        (rw_proc_state[layer_id] != VDC5_RW_PROC_STATE_DISABLE))
+    {
+        state = VDC5_RESOURCE_ST_VALID;
+    }
+    else
+    {
+        state = VDC5_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetRwProcEnabled() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Gets the pointer to the resource state
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Pointer to the resource state
+ *****************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer (const vdc5_resource_type_t rsrc_type)
+{
+    vdc5_resource_state_t             * resource_state;
+    static vdc5_shared_param_resource_t param_resource =
+    {
+        VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID
+    };
+
+    switch (rsrc_type)
+    {
+        case VDC5_RESOURCE_PANEL_CLK:
+            resource_state = &param_resource.rsrc_panel_clock;
+        break;
+        case VDC5_RESOURCE_VIDEO_IN:
+            resource_state = &param_resource.rsrc_video_input;
+        break;
+        case VDC5_RESOURCE_VSYNC:
+            resource_state = &param_resource.rsrc_vsync_signal;
+        break;
+        case VDC5_RESOURCE_LCD_PANEL:
+            resource_state = &param_resource.rsrc_lcd_panel;
+        break;
+
+        default:
+            resource_state = NULL;
+        break;
+    }
+    return resource_state;
+}   /* End of function GetResourceStatePointer() */
+
+/**************************************************************************//**
+ * @brief       Product-sum operation
+ * @param[in]   red             : 8 bits for red
+ * @param[in]   green           : 8 bits for green
+ * @param[in]   blue            : 8 bits for blue
+ * @param[in]   coeff_r         : Coefficient value for Cr/R signal gain adjustment
+ * @param[in]   coeff_g         : Coefficient value for Y/G signal gain adjustment
+ * @param[in]   coeff_b         : Coefficient value for Cb/B signal gain adjustment
+ * @param[in]   offset          : Coefficient value for offset adjustment
+ * @retval      Answer
+ *****************************************************************************/
+static uint32_t SumProduct (
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset)
+{
+    int32_t color_val;
+
+    /* Coefficient values are represented in 11-bit two's complement integer. */
+    if (coeff_r >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2))
+    {
+        coeff_r -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_g >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2))
+    {
+        coeff_g -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_b >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2))
+    {
+        coeff_b -= (int32_t)TWO_POWER_ELEVEN;
+    }
+
+    color_val  = (red * coeff_r) + (green * coeff_g) + (blue * coeff_b);
+    color_val /= (int32_t)VDC5_SPARA_DIV_256;
+    color_val += offset;
+    if (color_val < 0)
+    {
+        color_val = 0;
+    }
+    else if (color_val > (int32_t)VDC5_SPARA_COLOR_CONV_RANGE)
+    {
+        color_val = (int32_t)VDC5_SPARA_COLOR_CONV_RANGE;
+    }
+    else
+    {
+    }
+    return (uint32_t)color_val;
+}   /* End of function SumProduct() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/drivers/vdc5/src/r_vdc5_shared_param.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_shared_param.h
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC5 driver shared parameter definitions
+******************************************************************************/
+
+#ifndef R_VDC5_SHARED_PARAM_H
+#define R_VDC5_SHARED_PARAM_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Color space */
+typedef enum
+{
+    VDC5_COLOR_SPACE_GBR    = 0,        /*!< GBR */
+    VDC5_COLOR_SPACE_YCBCR  = 1         /*!< YCbCr */
+} vdc5_color_space_t;
+
+/*! Resource state */
+typedef enum
+{
+    VDC5_RESOURCE_ST_INVALID    = 0,    /*!< Invalid */
+    VDC5_RESOURCE_ST_VALID      = 1     /*!< Valid */
+} vdc5_resource_state_t;
+
+/*! Resource type */
+typedef enum
+{
+    VDC5_RESOURCE_PANEL_CLK = 0,        /*!< Panel clock */
+    VDC5_RESOURCE_VIDEO_IN,             /*!< Input video */
+    VDC5_RESOURCE_VSYNC,                /*!< Vsync signal */
+    VDC5_RESOURCE_LCD_PANEL,            /*!< LCD panel (output video) */
+    VDC5_RESOURCE_NUM
+} vdc5_resource_type_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_ShrdPrmInit(void);
+
+void VDC5_ShrdPrmSetInputParam(const vdc5_input_t * const param);
+void VDC5_ShrdPrmSetOutputParam(const vdc5_output_t * const param);
+void VDC5_ShrdPrmSetWriteParam(const vdc5_write_t * const param);
+void VDC5_ShrdPrmSetChgWriteParam(const vdc5_write_chg_t * const param);
+void VDC5_ShrdPrmSetReadParam(const vdc5_graphics_type_t graphics_id, const vdc5_read_t * const param);
+void VDC5_ShrdPrmSetChgReadParam(const vdc5_graphics_type_t graphics_id, const vdc5_read_chg_t * const param);
+
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace(void);
+uint32_t VDC5_ShrdPrmGetBgColor(const vdc5_color_space_t color_space);
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode(void);
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace(void);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr(void);
+void * VDC5_ShrdPrmGetFrBuffBtm(void);
+
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir(const vdc5_graphics_type_t graphics_id);
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig(const vdc5_graphics_type_t graphics_id);
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat(const vdc5_graphics_type_t graphics_id);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd(const vdc5_graphics_type_t graphics_id);
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding(const vdc5_graphics_type_t graphics_id);
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea(const vdc5_graphics_type_t graphics_id);
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd(const vdc5_graphics_type_t  graphics_id);
+
+void VDC5_ShrdPrmSetResource(const vdc5_resource_type_t rsrc_type, const vdc5_resource_state_t rsrc_state);
+void VDC5_ShrdPrmSetLayerResource(const vdc5_layer_id_t layer_id, const vdc5_resource_state_t rsrc_state);
+vdc5_resource_state_t VDC5_ShrdPrmGetResource(const vdc5_resource_type_t rsrc_type);
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource(const vdc5_layer_id_t layer_id);
+
+void VDC5_ShrdPrmSetRwProcEnable(const vdc5_layer_id_t layer_id);
+void VDC5_ShrdPrmSetRwProcDisable(const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady(const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled(const vdc5_layer_id_t layer_id);
+
+
+#endif  /* R_VDC5_SHARED_PARAM_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/TARGET_RZA1UL/gr_lychee_vdc5.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1283 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         gr_peach_vdc5.c
+* @version
+* $Rev:
+* $Date::
+* @brief        VDC5 driver API wrapper function in C interface
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <string.h>
+
+#include    "r_typedefs.h"
+#include    "r_vdc5.h"
+#include    "gr_board_vdc5.h"
+#include    "r_ceu.h"
+
+#include    "mbed_assert.h"
+#include    "pinmap.h"
+#include    "RZ_A1_Init.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define STP91_BIT   (0x02u)
+#define STP90_BIT   (0x01u)
+#define STBRQ25_BIT (0x20u)
+#define STBAK25_BIT (0x20u)
+#define STBRQ24_BIT (0x10u)
+#define STBAK24_BIT (0x10u)
+#define CLUT8_TABLE_NUM         (256u)
+#define CLUT4_TABLE_NUM         (16u)
+#define CLUT1_TABLE_NUM         (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef enum {
+    VDC5_CH0,
+} VDC5Name;
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+static const PinMap PinMap_DV_INPUT_PIN[] = {
+    {P7_8  , VDC5_CH0, 3}, /* DV0_CLK    */
+    {P7_9  , VDC5_CH0, 3}, /* DV0_VSYNC  */
+    {P7_10 , VDC5_CH0, 3}, /* DV0_HSYNC  */
+    {P1_11 , VDC5_CH0, 4}, /* DV0_DATA7  */
+    {P1_10 , VDC5_CH0, 4}, /* DV0_DATA6  */
+    {P1_9  , VDC5_CH0, 4}, /* DV0_DATA5  */
+    {P1_8  , VDC5_CH0, 4}, /* DV0_DATA4  */
+    {P1_3  , VDC5_CH0, 4}, /* DV0_DATA3  */
+    {P1_2  , VDC5_CH0, 4}, /* DV0_DATA2  */
+    {P1_1  , VDC5_CH0, 4}, /* DV0_DATA1  */
+    {P1_0  , VDC5_CH0, 4}, /* DV0_DATA0  */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_CEU_PIN[] = {
+    {P3_14 , 0, 2}, /* VIO_CLK    */
+    {P4_0  , 0, 2}, /* VIO_VD     */
+    {P4_1  , 0, 2}, /* VIO_HD     */
+    {P1_15 , 0, 4}, /* VIO_D7     */
+    {P1_14 , 0, 4}, /* VIO_D6     */
+    {P1_13 , 0, 4}, /* VIO_D5     */
+    {P1_12 , 0, 4}, /* VIO_D4     */
+    {P1_7  , 0, 4}, /* VIO_D3     */
+    {P1_6  , 0, 4}, /* VIO_D2     */
+    {P1_5  , 0, 4}, /* VIO_D1     */
+    {P1_4  , 0, 4}, /* VIO_D0     */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_LCD_DISP_PIN[] = {
+    {P6_15 , VDC5_CH0, 2}, /* LCD0_DATA23  */
+    {P6_14 , VDC5_CH0, 2}, /* LCD0_DATA22  */
+    {P6_13 , VDC5_CH0, 2}, /* LCD0_DATA21  */
+    {P6_12 , VDC5_CH0, 2}, /* LCD0_DATA20  */
+    {P6_11 , VDC5_CH0, 2}, /* LCD0_DATA19  */
+    {P6_10 , VDC5_CH0, 2}, /* LCD0_DATA18  */
+    {P6_9  , VDC5_CH0, 2}, /* LCD0_DATA17  */
+    {P6_8  , VDC5_CH0, 2}, /* LCD0_DATA16  */
+    {P6_7  , VDC5_CH0, 2}, /* LCD0_DATA15  */
+    {P6_6  , VDC5_CH0, 2}, /* LCD0_DATA14  */
+    {P6_5  , VDC5_CH0, 2}, /* LCD0_DATA13  */
+    {P6_4  , VDC5_CH0, 2}, /* LCD0_DATA12  */
+    {P6_3  , VDC5_CH0, 2}, /* LCD0_DATA11  */
+    {P6_2  , VDC5_CH0, 2}, /* LCD0_DATA10  */
+    {P6_1  , VDC5_CH0, 2}, /* LCD0_DATA9   */
+    {P6_0  , VDC5_CH0, 2}, /* LCD0_DATA8   */
+    {P3_7  , VDC5_CH0, 3}, /* LCD0_DATA7   */
+    {P3_6  , VDC5_CH0, 3}, /* LCD0_DATA6   */
+    {P3_5  , VDC5_CH0, 3}, /* LCD0_DATA5   */
+    {P3_4  , VDC5_CH0, 3}, /* LCD0_DATA4   */
+    {P3_3  , VDC5_CH0, 3}, /* LCD0_DATA3   */
+    {P3_2  , VDC5_CH0, 3}, /* LCD0_DATA2   */
+    {P3_1  , VDC5_CH0, 3}, /* LCD0_DATA1   */
+    {P3_0  , VDC5_CH0, 3}, /* LCD0_DATA0   */
+    {P7_5  , VDC5_CH0, 6}, /* LCD0_TCON4   */
+    {P5_2  , VDC5_CH0, 5}, /* LCD0_TCON2   */
+    {P5_1  , VDC5_CH0, 5}, /* LCD0_TCON1   */
+    {P5_0  , VDC5_CH0, 5}, /* LCD0_TCON0   */
+    {P7_4  , VDC5_CH0, 6}, /* LCD0_CLK     */
+    {NC    , NC   , 0}
+};
+
+static const IRQn_Type vdc5_irq_set_tbl[] = {
+    S0_VI_VSYNC0_IRQn,
+    S0_LO_VSYNC0_IRQn,
+    S0_VSYNCERR0_IRQn,
+    GR3_VLINE0_IRQn,
+    S0_VFIELD0_IRQn,
+    IV1_VBUFERR0_IRQn,
+    IV3_VBUFERR0_IRQn,
+    IV5_VBUFERR0_IRQn,
+    IV6_VBUFERR0_IRQn,
+    S0_WLINE0_IRQn,
+};
+
+static const uint32_t color_table256[CLUT8_TABLE_NUM] = {
+  0xFF000000u, 0xFF010101u, 0xFF020202u, 0xFF030303u, 0xFF040404u, 0xFF050505u, 0xFF060606u, 0xFF070707u, /*   0 -   7 */
+  0xFF080808u, 0xFF090909u, 0xFF0A0A0Au, 0xFF0B0B0Bu, 0xFF0C0C0Cu, 0xFF0D0D0Du, 0xFF0E0E0Eu, 0xFF0F0F0Fu, /*   8 -  15 */
+  0xFF101010u, 0xFF111111u, 0xFF121212u, 0xFF131313u, 0xFF141414u, 0xFF151515u, 0xFF161616u, 0xFF171717u, /*  16 -  23 */
+  0xFF181818u, 0xFF191919u, 0xFF1A1A1Au, 0xFF1B1B1Bu, 0xFF1C1C1Cu, 0xFF1E1E1Eu, 0xFF1E1E1Eu, 0xFF1F1F1Fu, /*  24 -  31 */
+  0xFF202020u, 0xFF212121u, 0xFF222222u, 0xFF232323u, 0xFF242424u, 0xFF252525u, 0xFF262626u, 0xFF272727u, /*  32 -  39 */
+  0xFF282828u, 0xFF292929u, 0xFF2A2A2Au, 0xFF2B2B2Bu, 0xFF2C2C2Cu, 0xFF2E2E2Eu, 0xFF2E2E2Eu, 0xFF2F2F2Fu, /*  40 -  47 */
+  0xFF303030u, 0xFF313131u, 0xFF323232u, 0xFF333333u, 0xFF343434u, 0xFF353535u, 0xFF363636u, 0xFF373737u, /*  48 -  55 */
+  0xFF383838u, 0xFF393939u, 0xFF3A3A3Au, 0xFF3B3B3Bu, 0xFF3C3C3Cu, 0xFF3E3E3Eu, 0xFF3E3E3Eu, 0xFF3F3F3Fu, /*  56 -  63 */
+  0xFF404040u, 0xFF414141u, 0xFF424242u, 0xFF434343u, 0xFF444444u, 0xFF454545u, 0xFF464646u, 0xFF474747u, /*  64 -  71 */
+  0xFF484848u, 0xFF494949u, 0xFF4A4A4Au, 0xFF4B4B4Bu, 0xFF4C4C4Cu, 0xFF4E4E4Eu, 0xFF4E4E4Eu, 0xFF4F4F4Fu, /*  72 -  79 */
+  0xFF505050u, 0xFF515151u, 0xFF525252u, 0xFF535353u, 0xFF545454u, 0xFF555555u, 0xFF565656u, 0xFF575757u, /*  80 -  87 */
+  0xFF585858u, 0xFF595959u, 0xFF5A5A5Au, 0xFF5B5B5Bu, 0xFF5C5C5Cu, 0xFF5E5E5Eu, 0xFF5E5E5Eu, 0xFF5F5F5Fu, /*  88 -  95 */
+  0xFF606060u, 0xFF616161u, 0xFF626262u, 0xFF636363u, 0xFF646464u, 0xFF656565u, 0xFF666666u, 0xFF676767u, /*  96 - 103 */
+  0xFF686868u, 0xFF696969u, 0xFF6A6A6Au, 0xFF6B6B6Bu, 0xFF6C6C6Cu, 0xFF6E6E6Eu, 0xFF6E6E6Eu, 0xFF6F6F6Fu, /* 104 - 111 */
+  0xFF707070u, 0xFF717171u, 0xFF727272u, 0xFF737373u, 0xFF747474u, 0xFF757575u, 0xFF767676u, 0xFF777777u, /* 112 - 119 */
+  0xFF787878u, 0xFF797979u, 0xFF7A7A7Au, 0xFF7B7B7Bu, 0xFF7C7C7Cu, 0xFF7E7E7Eu, 0xFF7E7E7Eu, 0xFF7F7F7Fu, /* 120 - 127 */
+  0xFF808080u, 0xFF818181u, 0xFF828282u, 0xFF838383u, 0xFF848484u, 0xFF858585u, 0xFF868686u, 0xFF878787u, /* 128 - 135 */
+  0xFF888888u, 0xFF898989u, 0xFF8A8A8Au, 0xFF8B8B8Bu, 0xFF8C8C8Cu, 0xFF8E8E8Eu, 0xFF8E8E8Eu, 0xFF8F8F8Fu, /* 136 - 143 */
+  0xFF909090u, 0xFF919191u, 0xFF929292u, 0xFF939393u, 0xFF949494u, 0xFF959595u, 0xFF969696u, 0xFF979797u, /* 144 - 151 */
+  0xFF989898u, 0xFF999999u, 0xFF9A9A9Au, 0xFF9B9B9Bu, 0xFF9C9C9Cu, 0xFF9E9E9Eu, 0xFF9E9E9Eu, 0xFF9F9F9Fu, /* 152 - 159 */
+  0xFFA0A0A0u, 0xFFA1A1A1u, 0xFFA2A2A2u, 0xFFA3A3A3u, 0xFFA4A4A4u, 0xFFA5A5A5u, 0xFFA6A6A6u, 0xFFA7A7A7u, /* 160 - 167 */
+  0xFFA8A8A8u, 0xFFA9A9A9u, 0xFFAAAAAAu, 0xFFABABABu, 0xFFACACACu, 0xFFAEAEAEu, 0xFFAEAEAEu, 0xFFAFAFAFu, /* 168 - 175 */
+  0xFFB0B0B0u, 0xFFB1B1B1u, 0xFFB2B2B2u, 0xFFB3B3B3u, 0xFFB4B4B4u, 0xFFB5B5B5u, 0xFFB6B6B6u, 0xFFB7B7B7u, /* 176 - 183 */
+  0xFFB8B8B8u, 0xFFB9B9B9u, 0xFFBABABAu, 0xFFBBBBBBu, 0xFFBCBCBCu, 0xFFBEBEBEu, 0xFFBEBEBEu, 0xFFBFBFBFu, /* 184 - 191 */
+  0xFFC0C0C0u, 0xFFC1C1C1u, 0xFFC2C2C2u, 0xFFC3C3C3u, 0xFFC4C4C4u, 0xFFC5C5C5u, 0xFFC6C6C6u, 0xFFC7C7C7u, /* 192 - 199 */
+  0xFFC8C8C8u, 0xFFC9C9C9u, 0xFFCACACAu, 0xFFCBCBCBu, 0xFFCCCCCCu, 0xFFCECECEu, 0xFFCECECEu, 0xFFCFCFCFu, /* 200 - 207 */
+  0xFFD0D0D0u, 0xFFD1D1D1u, 0xFFD2D2D2u, 0xFFD3D3D3u, 0xFFD4D4D4u, 0xFFD5D5D5u, 0xFFD6D6D6u, 0xFFD7D7D7u, /* 208 - 215 */
+  0xFFD8D8D8u, 0xFFD9D9D9u, 0xFFDADADAu, 0xFFDBDBDBu, 0xFFDCDCDCu, 0xFFDEDEDEu, 0xFFDEDEDEu, 0xFFDFDFDFu, /* 216 - 223 */
+  0xFFE0E0E0u, 0xFFE1E1E1u, 0xFFE2E2E2u, 0xFFE3E3E3u, 0xFFE4E4E4u, 0xFFE5E5E5u, 0xFFE6E6E6u, 0xFFE7E7E7u, /* 224 - 231 */
+  0xFFE8E8E8u, 0xFFE9E9E9u, 0xFFEAEAEAu, 0xFFEBEBEBu, 0xFFECECECu, 0xFFEEEEEEu, 0xFFEEEEEEu, 0xFFEFEFEFu, /* 232 - 239 */
+  0xFFF0F0F0u, 0xFFF1F1F1u, 0xFFF2F2F2u, 0xFFF3F3F3u, 0xFFF4F4F4u, 0xFFF5F5F5u, 0xFFF6F6F6u, 0xFFF7F7F7u, /* 240 - 247 */
+  0xFFF8F8F8u, 0xFFF9F9F9u, 0xFFFAFAFAu, 0xFFFBFBFBu, 0xFFFCFCFCu, 0xFFFEFEFEu, 0xFFFEFEFEu, 0xFFFFFFFFu  /* 248 - 255 */
+};
+
+static const uint32_t color_table16[CLUT4_TABLE_NUM] = {
+  0xFF000000u, 0xFF111111u, 0xFF222222u, 0xFF333333u, 0xFF444444u, 0xFF555555u, 0xFF666666u, 0xFF777777u, /*   0 -   7 */
+  0xFF888888u, 0xFF999999u, 0xFFAAAAAAu, 0xFFBBBBBBu, 0xFFCCCCCCu, 0xFFDDDDDDu, 0xFFEEEEEEu, 0xFFFFFFFFu  /*   8 -  15 */
+};
+
+static const uint32_t color_table2[CLUT1_TABLE_NUM] = {
+  0xFF000000u, 0xFFFFFFFFu
+};
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static drv_video_input_sel_t _drv_video_input_sel;
+
+static void init_func (const uint32_t user_num);
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable);
+
+/**************************************************************************//**
+ * @brief       User-defined function within R_VDC5_Initialize
+ * @param[in]   user_num                : VDC5 channel
+ * @retval      None
+******************************************************************************/
+static void init_func (const uint32_t user_num)
+{
+    uint32_t            reg_data;
+    volatile uint8_t    dummy_read;
+
+    if ((vdc5_channel_t)user_num == VDC5_CHANNEL_0) {
+
+        /* Standby control register 9 (STBCR9)
+            b1      ------0-;  MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
+        reg_data    = (uint32_t)CPG.STBCR9 & (uint32_t)~STP91_BIT;
+        CPG.STBCR9  = (uint8_t)reg_data;
+        /* In order to reflect the change, a dummy read should be done. */
+        dummy_read = CPG.STBCR9;
+
+        /* Standby Request Register 2 (STBREQ2)
+            b5      --0-----;  STBRQ25 : The standby request to VDC5 channel 0 is invalid. */
+        reg_data    = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ25_BIT;
+        CPG.STBREQ2 = (uint8_t)reg_data;
+        /* Standby Acknowledge Register 2 (STBACK2)
+            b5      --*-----;  STBAK25 : Standby acknowledgement from VDC5 channel 0. */
+        while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK25_BIT) != 0u) {
+            /* Wait for the STBAK25 to be cleared to 0. */
+        }
+
+        /* Standby control register 9 (STBCR9)
+            b0      -------0;  MSTP90 : 0 : Video display controller channel 1 enable */
+        reg_data    = (uint32_t)CPG.STBCR9 & (uint32_t)~(STP91_BIT|STP90_BIT);
+        CPG.STBCR9  = (uint8_t)reg_data;
+        /* In order to reflect the change, a dummy read should be done. */
+        dummy_read = CPG.STBCR9;
+        (void)dummy_read; /* unused */
+
+        /* Standby Request Register 2 (STBREQ2)
+            b4      ---0----;  STBRQ24 : The standby request to VDC5 channel 1 is invalid. */
+        reg_data    = (uint32_t)CPG.STBREQ2 & (uint32_t)~STBRQ24_BIT;
+        CPG.STBREQ2 = (uint8_t)reg_data;
+        /* Standby Acknowledge Register 2 (STBACK2)
+            b4      ---*----;  STBAK24 : Standby acknowledgement from VDC5 channel 1. */
+        while (((uint32_t)CPG.STBACK2 & (uint32_t)STBAK24_BIT) != 0u) {
+            /* Wait for the STBAK24 to be cleared to 0. */
+        }
+    }
+}   /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   enable                  : VDC5 interrupt enable
+ * @retval      None
+******************************************************************************/
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable)
+{
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    IRQn_Type IRQn;
+    IRQHandler handler;
+
+    IRQn = vdc5_irq_set_tbl[irq];
+    handler = R_VDC5_GetISR(ch, irq);
+
+    if (enable) {
+        InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+        GIC_SetPriority(IRQn, 5);
+        GIC_EnableIRQ(IRQn);
+    } else {
+        GIC_DisableIRQ(IRQn);
+    }
+} /* End of function DRV_Graphics_Irq_Set() */
+
+static void (* ceu_callback_func)(vdc5_int_type_t);
+static void Ceu_Irq_Handler_wrapper(ceu_int_type_t ceu_int_type) {
+    if ((ceu_callback_func != NULL) && ((ceu_int_type & CEU_INT_CPEIE) != 0)) {
+        ceu_callback_func(VDC5_INT_TYPE_S0_VFIELD);
+    }
+}
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   num                     : Interrupt line number
+ * @param[in]   * callback              : Interrupt callback function pointer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(
+    vdc5_int_type_t irq,
+    uint16_t num,
+    void (* callback)(vdc5_int_type_t)  )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+
+    if ((_drv_video_input_sel == DRV_INPUT_SEL_CEU) && (irq == VDC5_INT_TYPE_S0_VFIELD)) {
+        /* ceu wrapper */
+        if( callback == NULL ) {
+            R_CEU_InterruptDisable();
+            ceu_callback_func = NULL;
+        } else {
+            ceu_callback_func = callback;
+            R_CEU_InterruptEnable(CEU_INT_CPEIE, &Ceu_Irq_Handler_wrapper);
+        }
+    } else {
+        vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+        vdc5_error_t            error;
+        vdc5_int_t              interrupt;
+
+        if( callback == NULL ) {
+            DRV_Graphics_Irq_Set( irq, 0 );
+        } else {
+            DRV_Graphics_Irq_Set( irq, 1 );
+        }
+
+        /* Interrupt parameter */
+        interrupt.type      = irq;        /* Interrupt type */
+        interrupt.line_num  = num ;       /* Line number */
+
+        /* Interrupt parameter */
+        interrupt.callback = callback;    /* Callback function pointer */
+        /* Set interrupt service routine */
+        error = R_VDC5_CallbackISR(ch, &interrupt);
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error ;
+} /* End of function DRV_Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief       LCD output port initialization processing
+ * @param[in]   pin                     : Pin assign for LCD output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
+        pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       LVDS output port initialization processing
+ * @param[in]   pin                     : Pin assign for LVDS output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    return DRV_GRAPHICS_VDC5_ERR;
+} /* End of function DRV_Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Digital video inpout port initialization processing
+ * @param[in]   pin                     : Pin assign for digital video input port
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
+        pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       CEU inpout port initialization processing
+ * @param[in]   pin                     : Pin assign for digital video input port
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_CEU_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_CEU_PIN);
+        pinmap_pinout(pin[count], PinMap_CEU_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_CEU_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Graphics initialization processing
+ * @param[in]   drv_lcd_config          : LCD configuration
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_init_t             init;
+    double                  InputClock;
+    double                  OutputClock;
+    double                  OutputClock_wk;
+    double                  val;
+    double                  val_last = 200.0;
+    vdc5_panel_clk_dcdr_t   set_pram = VDC5_PANEL_CLKDIV_1_1;
+    int wk_div;
+
+    if (RZ_A1_IsClockMode0() == false) {
+        InputClock = CM1_RENESAS_RZ_A1_P1_CLK / 1000000;
+    } else {
+        InputClock = CM0_RENESAS_RZ_A1_P1_CLK / 1000000;
+    }
+
+    /* Initialization parameter */
+    init.panel_icksel   = VDC5_PANEL_ICKSEL_PERI;      /* Panel clock select */
+    init.lvds           = NULL;                        /* LVDS parameter */
+    OutputClock         = drv_lcd_config->outputClock;
+    init.panel_dcdr     = VDC5_PANEL_CLKDIV_1_1;
+    for (wk_div = 1; wk_div <= 32; wk_div++) {
+        switch (wk_div) {
+            case 1:
+            case 2:
+            case 3:
+            case 4:
+            case 5:
+            case 6:
+            case 7:
+            case 8:
+            case 9:
+            case 12:
+            case 16:
+            case 24:
+            case 32:
+                OutputClock_wk = InputClock / wk_div;
+                if (OutputClock_wk > OutputClock) {
+                    val = OutputClock_wk - OutputClock;
+                } else {
+                    val = OutputClock - OutputClock_wk;
+                }
+                if (val < val_last) {
+                    init.panel_dcdr = set_pram;
+                    val_last = val;
+                }
+                set_pram++;
+                break;
+            default:
+                break;
+        }
+    }
+
+    /* Initialize (Set module clock to VDC5) */
+    error = R_VDC5_Initialize( ch, &init, &init_func, (uint32_t)ch );
+    if (error != VDC5_OK) {
+        drv_error = DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    if ( drv_error == DRV_GRAPHICS_OK ) {
+        vdc5_sync_ctrl_t        sync_ctrl;
+
+        /* Sync signal control */
+        sync_ctrl.res_vs_sel    = VDC5_ON;                              /* Vsync signal output select (free-running Vsync on/off control) */
+        /* Sync signal output and full-screen enable signal select */
+        sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;
+        sync_ctrl.res_fv        = drv_lcd_config->v_toatal_period-1;    /* Free-running Vsync period setting */
+        sync_ctrl.res_fh        = drv_lcd_config->h_toatal_period-1;    /* Hsync period setting */
+        sync_ctrl.res_vsdly     = (uint16_t)0u;                         /* Vsync signal delay control */
+        /* Full-screen enable control */
+        sync_ctrl.res_f.vs      = (drv_lcd_config->v_back_porch);
+        sync_ctrl.res_f.vw      = (drv_lcd_config->v_disp_widht);
+        sync_ctrl.res_f.hs      = (drv_lcd_config->h_back_porch);
+        sync_ctrl.res_f.hw      = (drv_lcd_config->h_disp_widht);
+        sync_ctrl.vsync_cpmpe   = NULL;                                 /* Vsync signal compensation */
+        /* Sync control */
+        error = R_VDC5_SyncControl( ch, &sync_ctrl );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+
+    if ( drv_error == DRV_GRAPHICS_OK ) {
+        vdc5_output_t           output;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_VS;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_VE;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_HS;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_HE;
+        vdc5_lcd_tcon_timing_t  lcd_tcon_timing_DE;
+
+        /* Output parameter */
+        output.tcon_half        = (drv_lcd_config->h_toatal_period-1)/2; /* TCON reference timing, 1/2fH timing */
+        output.tcon_offset      = 0;                                     /* TCON reference timing, offset Hsync signal timing */
+
+        /* LCD TCON timing setting */
+        if( drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_VS.tcon_hsvs   = 0u;
+            lcd_tcon_timing_VS.tcon_hwvw   = (drv_lcd_config->v_sync_width * 2u);
+            lcd_tcon_timing_VS.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_VS.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->v_sync_port_polarity;
+            lcd_tcon_timing_VS.tcon_pin    = (vdc5_lcd_tcon_pin_t)drv_lcd_config->v_sync_port;
+            lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = &lcd_tcon_timing_VS;  /* STVA/VS: Vsync      */
+        } else {
+            output.outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = NULL;                 /* STVA/VS: Vsync      */
+        }
+
+        if( drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_HS.tcon_hsvs   = 0u;
+            lcd_tcon_timing_HS.tcon_hwvw   = drv_lcd_config->h_sync_width;
+            lcd_tcon_timing_HS.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_HS.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->h_sync_port_polarity;
+            lcd_tcon_timing_HS.tcon_pin    = (vdc5_lcd_tcon_pin_t)drv_lcd_config->h_sync_port;
+            lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS]   = &lcd_tcon_timing_HS;  /* STH/SP/HS: Hsync       */
+        } else {
+            output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS]   = NULL;                 /* STH/SP/HS: Hsync       */
+        }
+
+        if( drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_VE.tcon_hsvs   = (drv_lcd_config->v_back_porch * 2u);
+            lcd_tcon_timing_VE.tcon_hwvw   = (drv_lcd_config->v_disp_widht * 2u);
+            lcd_tcon_timing_VE.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_VE.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_VE.tcon_pin    = VDC5_LCD_TCON_PIN_NON;
+            lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = &lcd_tcon_timing_VE;  /* STVB/VE: Not used   */
+
+            lcd_tcon_timing_HE.tcon_hsvs   = drv_lcd_config->h_back_porch;
+            lcd_tcon_timing_HE.tcon_hwvw   = drv_lcd_config->h_disp_widht;
+            lcd_tcon_timing_HE.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_HE.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_HE.tcon_pin    = VDC5_LCD_TCON_PIN_NON;
+            lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE;  /* STB/LP/HE: Not used */
+
+            lcd_tcon_timing_DE.tcon_hsvs   = 0u;
+            lcd_tcon_timing_DE.tcon_hwvw   = 0u;
+            lcd_tcon_timing_DE.tcon_md     = VDC5_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_DE.tcon_inv    = (vdc5_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_DE.tcon_pin    = (vdc5_lcd_tcon_pin_t)drv_lcd_config->de_port;
+            lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING;
+            output.outctrl[VDC5_LCD_TCONSIG_DE]   = &lcd_tcon_timing_DE;  /* DE      */
+        } else {
+            output.outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;            /* STVB/VE: Not used   */
+            output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;            /* STB/LP/HE: Not used */
+            output.outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;            /* DE                  */
+        }
+
+        output.outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;
+        output.outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;
+        output.outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;
+
+        output.outcnt_lcd_edge  = (vdc5_edge_t)drv_lcd_config->lcd_edge;  /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+        output.out_endian_on    = VDC5_OFF;                               /* Bit endian change on/off control */
+        output.out_swap_on      = VDC5_ON;                                /* B/R signal swap on/off control */
+        output.out_format       = (vdc5_lcd_outformat_t)drv_lcd_config->lcd_outformat;    /* Output format select */
+        output.out_frq_sel      = VDC5_LCD_PARALLEL_CLKFRQ_1;             /* Clock frequency control */
+        output.out_dir_sel      = VDC5_LCD_SERIAL_SCAN_FORWARD;           /* Scan direction select */
+        output.out_phase        = VDC5_LCD_SERIAL_CLKPHASE_0;             /* Clock phase adjustment */
+        output.bg_color         = (uint32_t)0x00000000u;                  /* Background color in 24-bit RGB color format */
+        /* Display output */
+        error = R_VDC5_DisplayOutput( ch, &output );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Init() */
+
+/**************************************************************************//**
+ * @brief       Video initialization processing
+ * @param[in]   drv_video_ext_in_config   : Video configuration
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_error_t            error;
+    vdc5_input_t            input;
+    vdc5_ext_in_sig_t       ext_in_sig;
+    vdc5_sync_delay_t       sync_delay;
+
+    if ((drv_video_input_sel != DRV_INPUT_SEL_EXT) && (drv_video_input_sel != DRV_INPUT_SEL_CEU)) {
+        return DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    _drv_video_input_sel = drv_video_input_sel;
+    if( drv_video_input_sel == DRV_INPUT_SEL_EXT ) {
+        input.inp_sel   = (vdc5_input_sel_t)drv_video_input_sel; /* Input select */
+        input.inp_fh50  = (uint16_t)VSYNC_1_2_FH_TIMING;         /* Vsync signal 1/2fH phase timing */
+        input.inp_fh25  = (uint16_t)VSYNC_1_4_FH_TIMING;         /* Vsync signal 1/4fH phase timing */
+
+        ext_in_sig.inp_format     = (vdc5_extin_format_t)drv_video_ext_in_config->inp_format;
+        ext_in_sig.inp_pxd_edge   = (vdc5_edge_t)drv_video_ext_in_config->inp_pxd_edge;
+        ext_in_sig.inp_vs_edge    = (vdc5_edge_t)drv_video_ext_in_config->inp_vs_edge;
+        ext_in_sig.inp_hs_edge    = (vdc5_edge_t)drv_video_ext_in_config->inp_hs_edge;
+        ext_in_sig.inp_endian_on  = (vdc5_onoff_t)drv_video_ext_in_config->inp_endian_on;
+        ext_in_sig.inp_swap_on    = (vdc5_onoff_t)drv_video_ext_in_config->inp_swap_on;
+        ext_in_sig.inp_vs_inv     = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_vs_inv;
+        ext_in_sig.inp_hs_inv     = (vdc5_sig_pol_t)drv_video_ext_in_config->inp_hs_inv;
+        ext_in_sig.inp_h_edge_sel = (vdc5_extin_ref_hsync_t)drv_video_ext_in_config->inp_hs_edge;
+        ext_in_sig.inp_f525_625   = (vdc5_extin_input_line_t)drv_video_ext_in_config->inp_f525_625;
+        ext_in_sig.inp_h_pos      = (vdc5_extin_h_pos_t)drv_video_ext_in_config->inp_h_pos;
+
+        sync_delay.inp_vs_dly_l   = 0u;
+        sync_delay.inp_vs_dly     = 16u;
+        sync_delay.inp_hs_dly     = 16u;
+        sync_delay.inp_fld_dly    = 16u;
+
+        input.dly       = &sync_delay;   /* Sync signal delay adjustment */
+        input.ext_sig   = &ext_in_sig;   /* External input signal        */
+
+        /* Video input 0ch */
+        error = R_VDC5_VideoInput( VDC5_CHANNEL_0, &input );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    } else if (drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Initialize(&R_CEU_OnInitialize, 0);
+        return DRV_GRAPHICS_OK;
+    } else {
+        drv_error = DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    return drv_error;
+}   /* End of function DRV_Video_Init() */
+
+/**************************************************************************//**
+ * @brief       Start the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      drv_graphics_error_t
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_start_t            start;
+    vdc5_gr_disp_sel_t      gr_disp_sel;
+    vdc5_layer_id_t         vdc5_layer_id;
+
+    switch( layer_id ) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id   = VDC5_LAYER_ID_0_RD;
+            gr_disp_sel     = VDC5_DISPSEL_CURRENT;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id   = VDC5_LAYER_ID_2_RD;
+            gr_disp_sel     = VDC5_DISPSEL_BLEND;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id   = VDC5_LAYER_ID_3_RD;
+            gr_disp_sel     = VDC5_DISPSEL_BLEND;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Start process */
+        start.gr_disp_sel = &gr_disp_sel;
+        error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_layer_id_t         vdc5_layer_id;
+
+    switch( layer_id ) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id   = VDC5_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id   = VDC5_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id   = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Stop process */
+        error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief      Start the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    if (_drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Start();
+    } else {
+        vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+        vdc5_error_t            error;
+        vdc5_start_t            start;
+        vdc5_gr_disp_sel_t      gr_disp_sel;
+        vdc5_layer_id_t         vdc5_layer_id;
+
+        if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+            vdc5_layer_id   = VDC5_LAYER_ID_0_WR;
+        } else {
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+        }
+
+        if( drv_error == DRV_GRAPHICS_OK ) {
+            /* Start process */
+            gr_disp_sel         = VDC5_DISPSEL_CURRENT;    /* CURRENT fixed for weave input mode */
+            start.gr_disp_sel   = &gr_disp_sel;
+            error = R_VDC5_StartProcess( ch, vdc5_layer_id, &start );
+            if (error != VDC5_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+
+    if (_drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Stop();
+    } else {
+        vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+        vdc5_error_t            error;
+        vdc5_layer_id_t         vdc5_layer_id;
+
+        switch (video_input_ch) {
+            case DRV_VIDEO_INPUT_CHANNEL_0:
+                vdc5_layer_id   = VDC5_LAYER_ID_0_WR;
+                break;
+            default:
+                drv_error = DRV_GRAPHICS_LAYER_ERR;
+                break;
+        }
+
+        if( drv_error == DRV_GRAPHICS_OK ) {
+            /* Stop process */
+            error = R_VDC5_StopProcess ( ch, vdc5_layer_id );
+            if (error != VDC5_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Stop() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process setting
+ *
+ *              Description:<br>
+ *              This function supports the following 4 image format.
+ *                  YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @param[in]   gr_format               : Format of the frame buffer read signal
+ * @param[in]   gr_rect                 : Graphics display area
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Setting (
+    drv_graphics_layer_t        layer_id,
+    void                      * framebuff,
+    uint32_t                    fb_stride,
+    drv_graphics_format_t       gr_format,
+    drv_wr_rd_swa_t             wr_rd_swa,
+    drv_rect_t                * gr_rect,
+    drv_clut_t                * gr_clut )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_layer_id_t         vdc5_layer_id;
+    vdc5_gr_format_t        vdc5_gr_format;
+    vdc5_read_t             read;
+
+    switch(layer_id) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        switch( gr_format ) {
+            case DRV_GRAPHICS_FORMAT_YCBCR422:
+                vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422;
+                break;
+            case DRV_GRAPHICS_FORMAT_RGB565:
+                vdc5_gr_format = VDC5_GR_FORMAT_RGB565;
+                break;
+            case DRV_GRAPHICS_FORMAT_RGB888:
+                vdc5_gr_format = VDC5_GR_FORMAT_RGB888;
+                break;
+            case DRV_GRAPHICS_FORMAT_ARGB8888:
+                vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888;
+                break;
+            case DRV_GRAPHICS_FORMAT_ARGB4444:
+                vdc5_gr_format = VDC5_GR_FORMAT_ARGB4444;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT8:
+                vdc5_gr_format = VDC5_GR_FORMAT_CLUT8;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT4:
+                vdc5_gr_format = VDC5_GR_FORMAT_CLUT4;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT1:
+                vdc5_gr_format = VDC5_GR_FORMAT_CLUT1;
+                break;
+            default:
+                drv_error = DRV_GRAPHICS_FORMAT_ERR;
+                break;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Read data parameter */
+        read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+        read.gr_flm_sel     = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+        read.gr_imr_flm_inv = VDC5_OFF;                 /* Frame buffer number for distortion correction */
+        read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+        read.gr_base        = framebuff;                /* Frame buffer base address */
+        read.gr_ln_off      = fb_stride;                /* Frame buffer line offset address */
+
+        read.width_read_fb  = NULL;                     /* Width of the image read from frame buffer */
+
+        read.adj_sel        = VDC5_OFF;                 /* Measures to decrease the influence
+                                                           by folding pixels/lines (on/off) */
+        read.gr_format      = vdc5_gr_format;           /* Format of the frame buffer read signal */
+        read.gr_ycc_swap    = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
+                                                           in the YCbCr422 format */
+        read.gr_rdswa       = (vdc5_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
+        /* Display area */
+        read.gr_grc.vs      = gr_rect->vs;
+        read.gr_grc.vw      = gr_rect->vw;
+        read.gr_grc.hs      = gr_rect->hs;
+        read.gr_grc.hw      = gr_rect->hw;
+
+        /* Read data control */
+        error = R_VDC5_ReadDataControl( ch, vdc5_layer_id, &read );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if ((vdc5_gr_format == VDC5_GR_FORMAT_CLUT8)
+         || (vdc5_gr_format == VDC5_GR_FORMAT_CLUT4)
+         || (vdc5_gr_format == VDC5_GR_FORMAT_CLUT1)) {
+            vdc5_clut_t vdc5_clut;
+
+            if (gr_clut != NULL) {
+                vdc5_clut.color_num = gr_clut->color_num;
+                vdc5_clut.clut = gr_clut->clut;
+            } else if (vdc5_gr_format == VDC5_GR_FORMAT_CLUT8) {
+                vdc5_clut.color_num = CLUT8_TABLE_NUM;
+                vdc5_clut.clut = color_table256;
+            } else if (vdc5_gr_format == VDC5_GR_FORMAT_CLUT4) {
+                vdc5_clut.color_num = CLUT4_TABLE_NUM;
+                vdc5_clut.clut = color_table16;
+            } else {
+                vdc5_clut.color_num = CLUT1_TABLE_NUM;
+                vdc5_clut.clut = color_table2;
+            }
+            error = R_VDC5_CLUT(ch, vdc5_layer_id, &vdc5_clut);
+            if (error != VDC5_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+
+    return drv_error;
+}   /* End of function DRV_Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read buffer change process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Change (
+    drv_graphics_layer_t    layer_id,
+    void                 *  framebuff)
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t          ch          = VDC5_CHANNEL_0;
+    vdc5_error_t            error;
+    vdc5_layer_id_t         vdc5_layer_id;
+    vdc5_read_chg_t         read_chg;
+
+    switch(layer_id) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Read data parameter */
+        read_chg.width_read_fb  = NULL;         /* Width of the image read from frame buffer */
+        read_chg.gr_grc         = NULL;         /* Display area */
+        read_chg.gr_disp_sel    = NULL;         /* Graphics display mode */
+        read_chg.gr_base        = framebuff;     /* Frame buffer base address */
+
+        /* Change read process */
+        error = R_VDC5_ChangeReadProcess( ch, vdc5_layer_id, &read_chg );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Read_Change() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting
+ *
+ *              Description:<br>
+ *              This function set the video write process. Input form is weave
+ *              (progressive) mode fixed.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   video_input_ch          : Video input channel
+ * @param[in]   col_sys                 : Analog video signal color system
+ * @param[in]   adc_vinsel              : Video input pin
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   video_adc_vinsel        : Input pin control
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting (
+    drv_video_input_channel_t       video_input_ch,
+    drv_graphics_video_col_sys_t    col_sys,
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_adc_vinsel_t          video_adc_vinsel )
+{
+    return DRV_GRAPHICS_VDC5_ERR;
+}   /* End of function DRV_Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting for digital input
+ *
+ *              Description:<br>
+ *              This function set the video write process for digital input.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   cap_area                : Capture area
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting_Digital (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_rect_t                    * cap_area )
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    vdc5_channel_t              ch          = VDC5_CHANNEL_0;
+    vdc5_error_t                error;
+    vdc5_layer_id_t             vdc5_layer_id;
+    vdc5_write_t                write;
+    vdc5_scalingdown_rot_t    * scldw_rot;
+    vdc5_res_md_t               res_md;
+
+    vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
+            res_md = VDC5_RES_MD_YCBCR422;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
+            res_md = VDC5_RES_MD_RGB888;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
+            res_md = VDC5_RES_MD_RGB565;
+        } else {
+            drv_error = DRV_GRAPHICS_FORMAT_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Scaling-down and rotation parameter */
+        scldw_rot = &write.scalingdown_rot;
+        /* Image area to be captured */
+        scldw_rot->res.vs   = (uint16_t)((uint32_t)cap_area->vs - 1u);
+        scldw_rot->res.vw   = cap_area->vw;
+        scldw_rot->res.hs   = cap_area->hs;
+        scldw_rot->res.hw   = cap_area->hw;
+
+        /* Write data parameter */
+        scldw_rot->res_pfil_sel = VDC5_ON;                   /* Prefilter mode select for brightness signals (on/off) */
+        scldw_rot->res_out_vw   = video_write_buff_vw ;      /* Number of valid lines in vertical direction
+                                                                output by scaling-down control block */
+        scldw_rot->res_out_hw   = video_write_buff_hw;       /* Number of valid horizontal pixels
+                                                                output by scaling-down control block */
+        scldw_rot->adj_sel      = VDC5_ON;                   /* Measures to decrease the influence
+                                                                by lack of last-input line (on/off) */
+        scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL;         /* Frame buffer writing mode */
+        write.res_wrswa     = (vdc5_wr_rd_swa_t)wr_rd_swa;   /* Frame buffer swap setting */
+        write.res_md        = res_md;                        /* Frame buffer video-signal writing format */
+        write.res_bst_md    = VDC5_BST_MD_32BYTE;            /* Transfer burst length for frame buffer */
+        write.res_inter     = VDC5_RES_INTER_PROGRESSIVE;    /* Field operating mode select */
+        write.res_fs_rate   = VDC5_RES_FS_RATE_PER1;         /* Writing rate */
+        write.res_fld_sel   = VDC5_RES_FLD_SEL_TOP;          /* Write field select */
+        write.res_dth_on    = VDC5_ON;                       /* Dither correction on/off */
+        write.base          = framebuff;                     /* Frame buffer base address */
+        write.ln_off        = fb_stride;
+        /* Frame buffer line offset address [byte] */
+        write.flm_num       = (uint32_t)(1u - 1u);           /* Number of frames of buffer (res_flm_num + 1) */
+        /* Frame buffer frame offset address */
+        write.flm_off       = fb_stride * (uint32_t)scldw_rot->res_out_vw;
+        write.btm_base      = NULL;                          /* Frame buffer base address for bottom */
+
+        /* Write data control */
+        error = R_VDC5_WriteDataControl( ch, vdc5_layer_id, &write );
+        if (error != VDC5_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Write_Setting_Digital() */
+
+drv_graphics_error_t DRV_Video_Write_Setting_Ceu (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_ext_in_config_t     * drv_video_ext_in_config)
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    ceu_cap_rect_t              ceu_cap;
+    ceu_config_t                ceu_config;
+
+    if (video_format != DRV_VIDEO_FORMAT_YCBCR422) {
+        return DRV_GRAPHICS_FORMAT_ERR;
+    }
+
+    /* CEU mode */
+    ceu_config.jpg = CEU_DATA_SYNC_MODE;
+
+    /* Capture timing */
+    if (drv_video_ext_in_config->cap_hs_pos <= 100) {
+        ceu_cap.hofst = drv_video_ext_in_config->cap_hs_pos * 4;
+    } else {
+        ceu_cap.hofst = 0;
+    }
+    if (drv_video_ext_in_config->cap_vs_pos >= 10) {
+        ceu_cap.vofst = drv_video_ext_in_config->cap_vs_pos * 4;
+    } else {
+        ceu_cap.vofst = 0;
+    }
+    ceu_cap.hwdth = video_write_buff_hw * 2;
+    ceu_cap.vwdth = video_write_buff_vw;
+    ceu_config.cap = &ceu_cap;
+
+    /* Capture Filter Size (Set this param if Image capture mode.) */
+    ceu_config.clp = NULL;
+
+    /* Data bus */
+    ceu_config.dtif = CEU_8BIT_DATA_PINS; /* Data pin 8bit  */
+
+    /* Write Data Swap */
+    switch (wr_rd_swa) {
+        default:
+        case DRV_WR_RD_WRSWA_NON:               /* Not swapped: 1-2-3-4-5-6-7-8 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_8BIT:              /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_16BIT:             /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_16_8BIT:           /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_32BIT:             /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_32_8BIT:           /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_32_16BIT:          /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_32_16_8BIT:        /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_ON;
+            break;
+    }
+
+    /* input order */
+    switch (drv_video_ext_in_config->inp_h_pos) {
+        default:
+        case DRV_EXTIN_H_POS_CBYCRY:        /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+            ceu_config.dtary = CEU_CB0_Y0_CR0_Y1;
+            if (ceu_config.cows == CEU_ON) {
+                ceu_config.cows = CEU_OFF;
+            } else {
+                ceu_config.cows = CEU_ON;
+            }
+            break;
+        case DRV_EXTIN_H_POS_YCRYCB:        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+            ceu_config.dtary = CEU_Y0_CR0_Y1_CB0;
+            if (ceu_config.cobs == CEU_ON) {
+                ceu_config.cobs = CEU_OFF;
+            } else {
+                ceu_config.cobs = CEU_ON;
+            }
+            if (ceu_config.cows == CEU_ON) {
+                ceu_config.cows = CEU_OFF;
+            } else {
+                ceu_config.cows = CEU_ON;
+            }
+            break;
+        case DRV_EXTIN_H_POS_CRYCBY:        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+            ceu_config.dtary = CEU_CR0_Y0_CB0_Y1;
+            break;
+        case DRV_EXTIN_H_POS_YCBYCR:        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+            ceu_config.dtary = CEU_Y0_CB0_Y1_CR0;
+            if (ceu_config.cobs == CEU_ON) {
+                ceu_config.cobs = CEU_OFF;
+            } else {
+                ceu_config.cobs = CEU_ON;
+            }
+            break;
+    }
+
+    /* Signal polarity */
+    /* Hsync */
+    if (drv_video_ext_in_config->inp_hs_inv == DRV_SIG_POL_NOT_INVERTED) {
+        ceu_config.hdpol = CEU_HIGH_ACTIVE;
+    } else {
+        ceu_config.hdpol = CEU_LOW_ACTIVE;
+    }
+    if (drv_video_ext_in_config->cap_hs_pos >= 100) {
+        /* inverted */
+        if (ceu_config.hdpol == CEU_HIGH_ACTIVE) {
+            ceu_config.hdpol = CEU_LOW_ACTIVE;
+        } else {
+            ceu_config.hdpol = CEU_HIGH_ACTIVE;
+        }
+    }
+
+    /* Vsync */
+    if (drv_video_ext_in_config->inp_vs_inv == DRV_SIG_POL_NOT_INVERTED) {
+        ceu_config.vdpol = CEU_HIGH_ACTIVE;
+    } else {
+        ceu_config.vdpol = CEU_LOW_ACTIVE;
+    }
+
+    R_CEU_Open(&ceu_config);
+    R_CEU_Execute_Setting(framebuff, (void *)NULL, fb_stride, CEU_ON);
+
+    return drv_error;
+}
+
+/**************************************************************************//**
+ * @brief       Video surface write buffer change process
+ * @param[in]   video_input_ch          : Video input channle
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Change (
+    drv_video_input_channel_t     video_input_ch,
+    void                        * framebuff,
+    uint32_t                      fb_stride )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint8_t               * framebuffer_t;
+    uint8_t               * framebuffer_b;
+
+    framebuffer_t = (uint8_t *)((uint32_t)framebuff & ~0x1F);
+    framebuffer_b = &framebuffer_t[fb_stride];
+
+    if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+        VDC50.SC0_SCL1_WR2 = (uint32_t)framebuffer_t;
+        VDC50.SC0_SCL1_WR8 = (uint32_t)framebuffer_b;
+        VDC50.SC0_SCL1_UPDATE = 0x10;
+    } else {
+        drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+    }
+    return drv_error;
+} /* End of function DRV_Video_Write_Change() */
+
+/* End of file */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/drivers/ceu/inc/ceu_iobitmask.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,326 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/ 
+#ifndef CEU_IOBITMASK_H
+#define CEU_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+
+#define CEU_CAPSR_CE                                                           (0x00000001u)
+#define CEU_CAPSR_CE_SHIFT                                                     (0u)
+#define CEU_CAPSR_CPKIL                                                        (0x00010000u)
+#define CEU_CAPSR_CPKIL_SHIFT                                                  (16u)
+#define CEU_CAPCR_CTNCP                                                        (0x00010000u)
+#define CEU_CAPCR_CTNCP_SHIFT                                                  (16u)
+#define CEU_CAPCR_MTCM                                                         (0x00300000u)
+#define CEU_CAPCR_MTCM_SHIFT                                                   (20u)
+#define CEU_CAPCR_FDRP                                                         (0xFF000000u)
+#define CEU_CAPCR_FDRP_SHIFT                                                   (24u)
+#define CEU_CAMCR_HDPOL                                                        (0x00000001u)
+#define CEU_CAMCR_HDPOL_SHIFT                                                  (0u)
+#define CEU_CAMCR_VDPOL                                                        (0x00000002u)
+#define CEU_CAMCR_VDPOL_SHIFT                                                  (1u)
+#define CEU_CAMCR_JPG                                                          (0x00000030u)
+#define CEU_CAMCR_JPG_SHIFT                                                    (4u)
+#define CEU_CAMCR_DTARY                                                        (0x00000300u)
+#define CEU_CAMCR_DTARY_SHIFT                                                  (8u)
+#define CEU_CAMCR_DTIF                                                         (0x00001000u)
+#define CEU_CAMCR_DTIF_SHIFT                                                   (12u)
+#define CEU_CAMCR_FLDPOL                                                       (0x00010000u)
+#define CEU_CAMCR_FLDPOL_SHIFT                                                 (16u)
+#define CEU_CAMCR_DSEL                                                         (0x01000000u)
+#define CEU_CAMCR_DSEL_SHIFT                                                   (24u)
+#define CEU_CAMCR_FLDSEL                                                       (0x02000000u)
+#define CEU_CAMCR_FLDSEL_SHIFT                                                 (25u)
+#define CEU_CAMCR_HDSEL                                                        (0x04000000u)
+#define CEU_CAMCR_HDSEL_SHIFT                                                  (26u)
+#define CEU_CAMCR_VDSEL                                                        (0x08000000u)
+#define CEU_CAMCR_VDSEL_SHIFT                                                  (27u)
+#define CEU_CMCYR_HCYL                                                         (0x00003FFFu)
+#define CEU_CMCYR_HCYL_SHIFT                                                   (0u)
+#define CEU_CMCYR_VCYL                                                         (0x3FFF0000u)
+#define CEU_CMCYR_VCYL_SHIFT                                                   (16u)
+#define CEU_CAMOR_A_HOFST                                                      (0x00001FFFu)
+#define CEU_CAMOR_A_HOFST_SHIFT                                                (0u)
+#define CEU_CAMOR_A_VOFST                                                      (0x0FFF0000u)
+#define CEU_CAMOR_A_VOFST_SHIFT                                                (16u)
+#define CEU_CAPWR_A_HWDTH                                                      (0x00001FFFu)
+#define CEU_CAPWR_A_HWDTH_SHIFT                                                (0u)
+#define CEU_CAPWR_A_VWDTH                                                      (0x0FFF0000u)
+#define CEU_CAPWR_A_VWDTH_SHIFT                                                (16u)
+#define CEU_CAIFR_FCI0                                                         (0x00000001u)
+#define CEU_CAIFR_FCI0_SHIFT                                                   (0u)
+#define CEU_CAIFR_FCI1                                                         (0x00000002u)
+#define CEU_CAIFR_FCI1_SHIFT                                                   (1u)
+#define CEU_CAIFR_CIM                                                          (0x00000010u)
+#define CEU_CAIFR_CIM_SHIFT                                                    (4u)
+#define CEU_CAIFR_IFS                                                          (0x00000100u)
+#define CEU_CAIFR_IFS_SHIFT                                                    (8u)
+#define CEU_CRCNTR_RC                                                          (0x00000001u)
+#define CEU_CRCNTR_RC_SHIFT                                                    (0u)
+#define CEU_CRCNTR_RS                                                          (0x00000002u)
+#define CEU_CRCNTR_RS_SHIFT                                                    (1u)
+#define CEU_CRCNTR_RVS                                                         (0x00000010u)
+#define CEU_CRCNTR_RVS_SHIFT                                                   (4u)
+#define CEU_CRCMPR_RA                                                          (0x00000001u)
+#define CEU_CRCMPR_RA_SHIFT                                                    (0u)
+#define CEU_CFLCR_A_HFRAC                                                      (0x00000FFFu)
+#define CEU_CFLCR_A_HFRAC_SHIFT                                                (0u)
+#define CEU_CFLCR_A_HMANT                                                      (0x0000F000u)
+#define CEU_CFLCR_A_HMANT_SHIFT                                                (12u)
+#define CEU_CFLCR_A_VFRAC                                                      (0x0FFF0000u)
+#define CEU_CFLCR_A_VFRAC_SHIFT                                                (16u)
+#define CEU_CFLCR_A_VMANT                                                      (0xF0000000u)
+#define CEU_CFLCR_A_VMANT_SHIFT                                                (28u)
+#define CEU_CFSZR_A_HFCLP                                                      (0x00000FFFu)
+#define CEU_CFSZR_A_HFCLP_SHIFT                                                (0u)
+#define CEU_CFSZR_A_VFCLP                                                      (0x0FFF0000u)
+#define CEU_CFSZR_A_VFCLP_SHIFT                                                (16u)
+#define CEU_CDWDR_A_CHDW                                                       (0x00001FFFu)
+#define CEU_CDWDR_A_CHDW_SHIFT                                                 (0u)
+#define CEU_CDAYR_A_CAYR                                                       (0xFFFFFFFFu)
+#define CEU_CDAYR_A_CAYR_SHIFT                                                 (0u)
+#define CEU_CDACR_A_CACR                                                       (0xFFFFFFFFu)
+#define CEU_CDACR_A_CACR_SHIFT                                                 (0u)
+#define CEU_CDBYR_A_CBYR                                                       (0xFFFFFFFFu)
+#define CEU_CDBYR_A_CBYR_SHIFT                                                 (0u)
+#define CEU_CDBCR_A_CBCR                                                       (0xFFFFFFFFu)
+#define CEU_CDBCR_A_CBCR_SHIFT                                                 (0u)
+#define CEU_CBDSR_A_CBVS                                                       (0x007FFFFFu)
+#define CEU_CBDSR_A_CBVS_SHIFT                                                 (0u)
+#define CEU_CFWCR_FWE                                                          (0x00000001u)
+#define CEU_CFWCR_FWE_SHIFT                                                    (0u)
+#define CEU_CFWCR_FWV                                                          (0xFFFFFFE0u)
+#define CEU_CFWCR_FWV_SHIFT                                                    (5u)
+#define CEU_CLFCR_A_LPF                                                        (0x00000001u)
+#define CEU_CLFCR_A_LPF_SHIFT                                                  (0u)
+#define CEU_CDOCR_A_COBS                                                       (0x00000001u)
+#define CEU_CDOCR_A_COBS_SHIFT                                                 (0u)
+#define CEU_CDOCR_A_COWS                                                       (0x00000002u)
+#define CEU_CDOCR_A_COWS_SHIFT                                                 (1u)
+#define CEU_CDOCR_A_COLS                                                       (0x00000004u)
+#define CEU_CDOCR_A_COLS_SHIFT                                                 (2u)
+#define CEU_CDOCR_A_CDS                                                        (0x00000010u)
+#define CEU_CDOCR_A_CDS_SHIFT                                                  (4u)
+#define CEU_CDOCR_A_CFXAD                                                      (0x00000100u)
+#define CEU_CDOCR_A_CFXAD_SHIFT                                                (8u)
+#define CEU_CDOCR_A_CBE                                                        (0x00010000u)
+#define CEU_CDOCR_A_CBE_SHIFT                                                  (16u)
+#define CEU_CEIER_CPEIE                                                        (0x00000001u)
+#define CEU_CEIER_CPEIE_SHIFT                                                  (0u)
+#define CEU_CEIER_CFEIE                                                        (0x00000002u)
+#define CEU_CEIER_CFEIE_SHIFT                                                  (1u)
+#define CEU_CEIER_IGRWIE                                                       (0x00000010u)
+#define CEU_CEIER_IGRWIE_SHIFT                                                 (4u)
+#define CEU_CEIER_HDIE                                                         (0x00000100u)
+#define CEU_CEIER_HDIE_SHIFT                                                   (8u)
+#define CEU_CEIER_VDIE                                                         (0x00000200u)
+#define CEU_CEIER_VDIE_SHIFT                                                   (9u)
+#define CEU_CEIER_CPBE1IE                                                      (0x00001000u)
+#define CEU_CEIER_CPBE1IE_SHIFT                                                (12u)
+#define CEU_CEIER_CPBE2IE                                                      (0x00002000u)
+#define CEU_CEIER_CPBE2IE_SHIFT                                                (13u)
+#define CEU_CEIER_CPBE3IE                                                      (0x00004000u)
+#define CEU_CEIER_CPBE3IE_SHIFT                                                (14u)
+#define CEU_CEIER_CPBE4IE                                                      (0x00008000u)
+#define CEU_CEIER_CPBE4IE_SHIFT                                                (15u)
+#define CEU_CEIER_CDTOFIE                                                      (0x00010000u)
+#define CEU_CEIER_CDTOFIE_SHIFT                                                (16u)
+#define CEU_CEIER_IGHSIE                                                       (0x00020000u)
+#define CEU_CEIER_IGHSIE_SHIFT                                                 (17u)
+#define CEU_CEIER_IGVSIE                                                       (0x00040000u)
+#define CEU_CEIER_IGVSIE_SHIFT                                                 (18u)
+#define CEU_CEIER_VBPIE                                                        (0x00100000u)
+#define CEU_CEIER_VBPIE_SHIFT                                                  (20u)
+#define CEU_CEIER_DCOFIE                                                       (0x00400000u)
+#define CEU_CEIER_DCOFIE_SHIFT                                                 (22u)
+#define CEU_CEIER_FWFIE                                                        (0x00800000u)
+#define CEU_CEIER_FWFIE_SHIFT                                                  (23u)
+#define CEU_CEIER_NHDIE                                                        (0x01000000u)
+#define CEU_CEIER_NHDIE_SHIFT                                                  (24u)
+#define CEU_CEIER_NVDIE                                                        (0x02000000u)
+#define CEU_CEIER_NVDIE_SHIFT                                                  (25u)
+#define CEU_CETCR_CPE                                                          (0x00000001u)
+#define CEU_CETCR_CPE_SHIFT                                                    (0u)
+#define CEU_CETCR_CFE                                                          (0x00000002u)
+#define CEU_CETCR_CFE_SHIFT                                                    (1u)
+#define CEU_CETCR_IGRW                                                         (0x00000010u)
+#define CEU_CETCR_IGRW_SHIFT                                                   (4u)
+#define CEU_CETCR_HD                                                           (0x00000100u)
+#define CEU_CETCR_HD_SHIFT                                                     (8u)
+#define CEU_CETCR_VD                                                           (0x00000200u)
+#define CEU_CETCR_VD_SHIFT                                                     (9u)
+#define CEU_CETCR_CPBE1                                                        (0x00001000u)
+#define CEU_CETCR_CPBE1_SHIFT                                                  (12u)
+#define CEU_CETCR_CPBE2                                                        (0x00002000u)
+#define CEU_CETCR_CPBE2_SHIFT                                                  (13u)
+#define CEU_CETCR_CPBE3                                                        (0x00004000u)
+#define CEU_CETCR_CPBE3_SHIFT                                                  (14u)
+#define CEU_CETCR_CPBE4                                                        (0x00008000u)
+#define CEU_CETCR_CPBE4_SHIFT                                                  (15u)
+#define CEU_CETCR_CDTOF                                                        (0x00010000u)
+#define CEU_CETCR_CDTOF_SHIFT                                                  (16u)
+#define CEU_CETCR_IGHS                                                         (0x00020000u)
+#define CEU_CETCR_IGHS_SHIFT                                                   (17u)
+#define CEU_CETCR_IGVS                                                         (0x00040000u)
+#define CEU_CETCR_IGVS_SHIFT                                                   (18u)
+#define CEU_CETCR_VBP                                                          (0x00100000u)
+#define CEU_CETCR_VBP_SHIFT                                                    (20u)
+#define CEU_CETCR_DCOF                                                         (0x00400000u)
+#define CEU_CETCR_DCOF_SHIFT                                                   (22u)
+#define CEU_CETCR_FWF                                                          (0x00800000u)
+#define CEU_CETCR_FWF_SHIFT                                                    (23u)
+#define CEU_CETCR_NHD                                                          (0x01000000u)
+#define CEU_CETCR_NHD_SHIFT                                                    (24u)
+#define CEU_CETCR_NVD                                                          (0x02000000u)
+#define CEU_CETCR_NVD_SHIFT                                                    (25u)
+#define CEU_CSTSR_CPTON                                                        (0x00000001u)
+#define CEU_CSTSR_CPTON_SHIFT                                                  (0u)
+#define CEU_CSTSR_CPACK                                                        (0x00000100u)
+#define CEU_CSTSR_CPACK_SHIFT                                                  (8u)
+#define CEU_CSTSR_CPREQ                                                        (0x00000200u)
+#define CEU_CSTSR_CPREQ_SHIFT                                                  (9u)
+#define CEU_CSTSR_CPFLD                                                        (0x00010000u)
+#define CEU_CSTSR_CPFLD_SHIFT                                                  (16u)
+#define CEU_CSTSR_CRST                                                         (0x01000000u)
+#define CEU_CSTSR_CRST_SHIFT                                                   (24u)
+#define CEU_CDSSR_CDSS                                                         (0xFFFFFFFFu)
+#define CEU_CDSSR_CDSS_SHIFT                                                   (0u)
+#define CEU_CDAYR2_A_CAYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDAYR2_A_CAYR2_SHIFT                                               (0u)
+#define CEU_CDACR2_A_CACR2                                                     (0xFFFFFFFFu)
+#define CEU_CDACR2_A_CACR2_SHIFT                                               (0u)
+#define CEU_CDBYR2_A_CBYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBYR2_A_CBYR2_SHIFT                                               (0u)
+#define CEU_CDBCR2_A_CBCR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBCR2_A_CBCR2_SHIFT                                               (0u)
+#define CEU_CAMOR_B_HOFST                                                      (0x00001FFFu)
+#define CEU_CAMOR_B_HOFST_SHIFT                                                (0u)
+#define CEU_CAMOR_B_VOFST                                                      (0x0FFF0000u)
+#define CEU_CAMOR_B_VOFST_SHIFT                                                (16u)
+#define CEU_CAPWR_B_HWDTH                                                      (0x00001FFFu)
+#define CEU_CAPWR_B_HWDTH_SHIFT                                                (0u)
+#define CEU_CAPWR_B_VWDTH                                                      (0x0FFF0000u)
+#define CEU_CAPWR_B_VWDTH_SHIFT                                                (16u)
+#define CEU_CFLCR_B_HFRAC                                                      (0x00000FFFu)
+#define CEU_CFLCR_B_HFRAC_SHIFT                                                (0u)
+#define CEU_CFLCR_B_HMANT                                                      (0x0000F000u)
+#define CEU_CFLCR_B_HMANT_SHIFT                                                (12u)
+#define CEU_CFLCR_B_VFRAC                                                      (0x0FFF0000u)
+#define CEU_CFLCR_B_VFRAC_SHIFT                                                (16u)
+#define CEU_CFLCR_B_VMANT                                                      (0xF0000000u)
+#define CEU_CFLCR_B_VMANT_SHIFT                                                (28u)
+#define CEU_CFSZR_B_HFCLP                                                      (0x00000FFFu)
+#define CEU_CFSZR_B_HFCLP_SHIFT                                                (0u)
+#define CEU_CFSZR_B_VFCLP                                                      (0x0FFF0000u)
+#define CEU_CFSZR_B_VFCLP_SHIFT                                                (16u)
+#define CEU_CDWDR_B_CHDW                                                       (0x00001FFFu)
+#define CEU_CDWDR_B_CHDW_SHIFT                                                 (0u)
+#define CEU_CDAYR_B_CAYR                                                       (0xFFFFFFFFu)
+#define CEU_CDAYR_B_CAYR_SHIFT                                                 (0u)
+#define CEU_CDACR_B_CACR                                                       (0xFFFFFFFFu)
+#define CEU_CDACR_B_CACR_SHIFT                                                 (0u)
+#define CEU_CDBYR_B_CBYR                                                       (0xFFFFFFFFu)
+#define CEU_CDBYR_B_CBYR_SHIFT                                                 (0u)
+#define CEU_CDBCR_B_CBCR                                                       (0xFFFFFFFFu)
+#define CEU_CDBCR_B_CBCR_SHIFT                                                 (0u)
+#define CEU_CBDSR_B_CBVS                                                       (0x007FFFFFu)
+#define CEU_CBDSR_B_CBVS_SHIFT                                                 (0u)
+#define CEU_CLFCR_B_LPF                                                        (0x00000001u)
+#define CEU_CLFCR_B_LPF_SHIFT                                                  (0u)
+#define CEU_CDOCR_B_COBS                                                       (0x00000001u)
+#define CEU_CDOCR_B_COBS_SHIFT                                                 (0u)
+#define CEU_CDOCR_B_COWS                                                       (0x00000002u)
+#define CEU_CDOCR_B_COWS_SHIFT                                                 (1u)
+#define CEU_CDOCR_B_COLS                                                       (0x00000004u)
+#define CEU_CDOCR_B_COLS_SHIFT                                                 (2u)
+#define CEU_CDOCR_B_CDS                                                        (0x00000010u)
+#define CEU_CDOCR_B_CDS_SHIFT                                                  (4u)
+#define CEU_CDOCR_B_CFXAD                                                      (0x00000100u)
+#define CEU_CDOCR_B_CFXAD_SHIFT                                                (8u)
+#define CEU_CDOCR_B_CBE                                                        (0x00010000u)
+#define CEU_CDOCR_B_CBE_SHIFT                                                  (16u)
+#define CEU_CDAYR2_B_CAYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDAYR2_B_CAYR2_SHIFT                                               (0u)
+#define CEU_CDACR2_B_CACR2                                                     (0xFFFFFFFFu)
+#define CEU_CDACR2_B_CACR2_SHIFT                                               (0u)
+#define CEU_CDBYR2_B_CBYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBYR2_B_CBYR2_SHIFT                                               (0u)
+#define CEU_CDBCR2_B_CBCR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBCR2_B_CBCR2_SHIFT                                               (0u)
+#define CEU_CAMOR_M_HOFST                                                      (0x00001FFFu)
+#define CEU_CAMOR_M_HOFST_SHIFT                                                (0u)
+#define CEU_CAMOR_M_VOFST                                                      (0x0FFF0000u)
+#define CEU_CAMOR_M_VOFST_SHIFT                                                (16u)
+#define CEU_CAPWR_M_HWDTH                                                      (0x00001FFFu)
+#define CEU_CAPWR_M_HWDTH_SHIFT                                                (0u)
+#define CEU_CAPWR_M_VWDTH                                                      (0x0FFF0000u)
+#define CEU_CAPWR_M_VWDTH_SHIFT                                                (16u)
+#define CEU_CFLCR_M_HFRAC                                                      (0x00000FFFu)
+#define CEU_CFLCR_M_HFRAC_SHIFT                                                (0u)
+#define CEU_CFLCR_M_HMANT                                                      (0x0000F000u)
+#define CEU_CFLCR_M_HMANT_SHIFT                                                (12u)
+#define CEU_CFLCR_M_VFRAC                                                      (0x0FFF0000u)
+#define CEU_CFLCR_M_VFRAC_SHIFT                                                (16u)
+#define CEU_CFLCR_M_VMANT                                                      (0xF0000000u)
+#define CEU_CFLCR_M_VMANT_SHIFT                                                (28u)
+#define CEU_CFSZR_M_HFCLP                                                      (0x00000FFFu)
+#define CEU_CFSZR_M_HFCLP_SHIFT                                                (0u)
+#define CEU_CFSZR_M_VFCLP                                                      (0x0FFF0000u)
+#define CEU_CFSZR_M_VFCLP_SHIFT                                                (16u)
+#define CEU_CDWDR_M_CHDW                                                       (0x00001FFFu)
+#define CEU_CDWDR_M_CHDW_SHIFT                                                 (0u)
+#define CEU_CDAYR_M_CAYR                                                       (0xFFFFFFFFu)
+#define CEU_CDAYR_M_CAYR_SHIFT                                                 (0u)
+#define CEU_CDACR_M_CACR                                                       (0xFFFFFFFFu)
+#define CEU_CDACR_M_CACR_SHIFT                                                 (0u)
+#define CEU_CDBYR_M_CBYR                                                       (0xFFFFFFFFu)
+#define CEU_CDBYR_M_CBYR_SHIFT                                                 (0u)
+#define CEU_CDBCR_M_CBCR                                                       (0xFFFFFFFFu)
+#define CEU_CDBCR_M_CBCR_SHIFT                                                 (0u)
+#define CEU_CBDSR_M_CBVS                                                       (0x007FFFFFu)
+#define CEU_CBDSR_M_CBVS_SHIFT                                                 (0u)
+#define CEU_CLFCR_M_LPF                                                        (0x00000001u)
+#define CEU_CLFCR_M_LPF_SHIFT                                                  (0u)
+#define CEU_CDOCR_M_COBS                                                       (0x00000001u)
+#define CEU_CDOCR_M_COBS_SHIFT                                                 (0u)
+#define CEU_CDOCR_M_COWS                                                       (0x00000002u)
+#define CEU_CDOCR_M_COWS_SHIFT                                                 (1u)
+#define CEU_CDOCR_M_COLS                                                       (0x00000004u)
+#define CEU_CDOCR_M_COLS_SHIFT                                                 (2u)
+#define CEU_CDOCR_M_CDS                                                        (0x00000010u)
+#define CEU_CDOCR_M_CDS_SHIFT                                                  (4u)
+#define CEU_CDOCR_M_CFXAD                                                      (0x00000100u)
+#define CEU_CDOCR_M_CFXAD_SHIFT                                                (8u)
+#define CEU_CDOCR_M_CBE                                                        (0x00010000u)
+#define CEU_CDOCR_M_CBE_SHIFT                                                  (16u)
+#define CEU_CDAYR2_M_CAYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDAYR2_M_CAYR2_SHIFT                                               (0u)
+#define CEU_CDACR2_M_CACR2                                                     (0xFFFFFFFFu)
+#define CEU_CDACR2_M_CACR2_SHIFT                                               (0u)
+#define CEU_CDBYR2_M_CBYR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBYR2_M_CBYR2_SHIFT                                               (0u)
+#define CEU_CDBCR2_M_CBCR2                                                     (0xFFFFFFFFu)
+#define CEU_CDBCR2_M_CBCR2_SHIFT                                               (0u)
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/drivers/ceu/inc/r_ceu.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,200 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ *******************************************************************************/
+/**************************************************************************//**
+ * File Name :   r_ceu.h
+ * @file         r_ceu.h
+ * @version      1.00
+ * $Rev: 182 $
+ * $Date:: 2017-05-11 07:35:51 +0900#$
+ * @brief        CEU driver header
+ ******************************************************************************/
+
+#ifndef R_CEU_H
+#define R_CEU_H
+
+/******************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "r_ceu_user.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+ Typedef definitions
+ ******************************************************************************/
+/*! @enum ceu_onoff_t
+ *  @brief On/off
+ */
+typedef enum
+{
+    CEU_OFF = 0, /*!< Off */
+    CEU_ON, /*!< On  */
+} ceu_onoff_t;
+
+/*! @enum ceu_jpg_t
+ *  @brief Select the fetched data type
+ */
+typedef enum
+{
+    CEU_IMAGE_CAPTURE_MODE = 0, /*!< Image capture mode          */
+    CEU_DATA_SYNC_MODE, /*!< Data synchronous fetch mode */
+    CEU_DATA_ENABLE_MODE /*!< Data enable fetch mode      */
+} ceu_jpg_t;
+
+/*! @enum ceu_dtif_t
+ *  @brief The digital image input pins from which data is to be captured
+ */
+typedef enum
+{
+    CEU_8BIT_DATA_PINS = 0, /*!<  8-bit digital image input pins */
+    CEU_16BIT_DATA_PINS /*!< 16-bit digital image input pins */
+} ceu_dtif_t;
+
+/*! @enum ceu_sig_pol_t
+ *  @brief The polarity for detection of the vertical sync signal and the horizontal sync signal.
+ */
+typedef enum
+{
+    CEU_HIGH_ACTIVE = 0, /*!< High active */
+    CEU_LOW_ACTIVE /*!< Low active  */
+} ceu_sig_pol_t;
+
+/*! @enum ceu_dtary_t
+ *  @brief The input order of the luminance component and chrominance component
+ */
+typedef enum
+{
+    CEU_CB0_Y0_CR0_Y1 = 0, /*!< Image input data is fetched in the order of Cb0, Y0, Cr0, and Y1 */
+    CEU_CR0_Y0_CB0_Y1, /*!< Image input data is fetched in the order of Cr0, Y0, Cb0, and Y1 */
+    CEU_Y0_CB0_Y1_CR0, /*!< Image input data is fetched in the order of Y0, Cb0, Y1, and Cr0 */
+    CEU_Y0_CR0_Y1_CB0 /*!< Image input data is fetched in the order of Y0, Cr0, Y1, and Cb0 */
+} ceu_dtary_t;
+
+/*! @enum ceu_int_type_t
+ *  @brief Capture Event Interrupt Enable flag
+ */
+typedef enum
+{
+    CEU_INT_CPEIE = (0x00000001u), /*!< One Frame capture end interrupt */
+    CEU_INT_CFEIE = (0x00000002u), /*!< One Filed capture end interrupt */
+    CEU_INT_IGRWIE = (0x00000010u), /*!< illegal register write interrupt */
+    CEU_INT_HDIE = (0x00000100u), /*!< HD interrupt */
+    CEU_INT_VDIE = (0x00000200u), /*!< VD interrupt */
+    CEU_INT_CPBE1IE = (0x00001000u), /*!< bundle write complete interrupt (TOP field) */
+    CEU_INT_CPBE2IE = (0x00002000u), /*!< bundle write complete interrupt (TOP field2) */
+    CEU_INT_CPBE3IE = (0x00004000u), /*!< bundle write complete interrupt (Bottom field) */
+    CEU_INT_CPBE4IE = (0x00008000u), /*!< bundle write complete interrupt (Bottom field2) */
+    CEU_INT_CDTOFIE = (0x00010000u), /*!< CRAM data overflow interrupt */
+    CEU_INT_IGHSIE = (0x00020000u), /*!< illegal H-Sync interrupt */
+    CEU_INT_IGVSIE = (0x00040000u), /*!< illegal V-Sync interrupt */
+    CEU_INT_VBPIE = (0x00100000u), /*!< insufficient vertical sync front porch interrupt */
+    CEU_INT_FWFIE = (0x00800000u), /*!< FW FAILED interrupt */
+    CEU_INT_NHDIE = (0x01000000u), /*!< Non-HD Interrupt */
+    CEU_INT_NVDIE = (0x02000000u) /*!< Non-VD Interrupt */
+} ceu_int_type_t;
+
+/*! @enum ceu_error_t
+ *  @brief Error codes of the CEU driver
+ */
+typedef enum
+{
+    CEU_OK = 0, /*!< Normal termination        */
+    CEU_ERR_PARAM, /*!< Parameter error           */
+    CEU_ERR_NUM /*!< The number of error codes */
+} ceu_error_t;
+
+/*! @struct ceu_cap_rect_t
+ *  @brief The horizontal/vertical timing of the Capture signals
+ */
+typedef struct
+{
+    uint32_t vofst; /*!< The capture start location in terms of the HD count from a vertical sync signal (1-HD units) */
+    uint32_t vwdth; /*!< The vertical capture period (4-HD units). */
+    uint32_t hofst; /*!< The capture start location in terms of the number of clock cycles from a horizontal sync signal (1-cycle units). */
+    uint32_t hwdth; /*!< The horizontal capture period
+     - Image capture mode( 8-bit)           8 cycle units
+     - Data synchronous fetch mode( 8-bit)  4 cycle units
+     - Image capture mode(16-bit)           4 cycle units
+     - Data synchronous fetch mode(16-bit)  2 cycle units */
+} ceu_cap_rect_t;
+
+/*! @struct ceu_clp_t
+ *  @brief Capture Filter Size (Set this param if Image capture mode.)
+ */
+typedef struct
+{
+    uint32_t vfclp; /*!< Vertical clipping value   (4-pixel unit) */
+    uint32_t hfclp; /*!< Horizontal clipping value (4-pixel unit) */
+} ceu_clp_t;
+
+/*! @struct ceu_config_t
+ *  @brief CEU config
+ */
+typedef struct
+{
+    ceu_jpg_t jpg; /*!< Select the fetched data type */
+    ceu_dtif_t dtif; /*!< Sets the digital image input pins from which data is to be captured  */
+    ceu_sig_pol_t vdpol; /*!< Sets the polarity for detection of the vertical sync signal          */
+    ceu_sig_pol_t hdpol; /*!< Sets the polarity for detection of the horizontal sync signal        */
+    ceu_dtary_t dtary; /*!< Sets the input order of the luminance component and chrominance component */
+    ceu_cap_rect_t * cap; /*!< The horizontal/vertical timing of the Capture signals */
+    ceu_clp_t * clp; /*!< Capture Filter Size (Set this param if Image capture mode.)*/
+    ceu_onoff_t cols; /*!< Controls swapping in 32-bit units for data output */
+    ceu_onoff_t cows; /*!< Controls swapping in 16-bit units for data output */
+    ceu_onoff_t cobs; /*!< Controls swapping in  8-bit units for data output */
+} ceu_config_t;
+
+/******************************************************************************
+ Macro definitions
+ ******************************************************************************/
+
+/******************************************************************************
+ Variable Externs
+ ******************************************************************************/
+
+/******************************************************************************
+ Functions Prototypes
+ ******************************************************************************/
+void R_CEU_Initialize(void (* const init_func)(uint32_t), const uint32_t user_num);
+ceu_error_t R_CEU_Open(const ceu_config_t * const config);
+ceu_error_t R_CEU_Execute(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture);
+ceu_error_t R_CEU_Terminate(void (* const quit_func)(uint32_t), const uint32_t user_num);
+void R_CEU_InterruptEnable(const ceu_int_type_t int_type, void (* const callback)(ceu_int_type_t));
+void R_CEU_InterruptDisable(void);
+void R_CEU_Isr(const uint32_t int_sense);
+ceu_error_t R_CEU_Stop(void);
+#if(1) /* mbed */
+ceu_error_t R_CEU_Execute_Setting(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture);
+ceu_error_t R_CEU_Start(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* R_CEU_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/drivers/ceu/inc/r_ceu_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_ceu_user.h
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L CEU driver user-defined header
+******************************************************************************/
+
+#ifndef R_CEU_USER_H
+#define R_CEU_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+uint32_t R_CEU_CPUVAddrToSysPAddr(uint32_t vaddr);
+void R_CEU_OnInitialize(const uint32_t user_num);
+void R_CEU_OnFinalize(const uint32_t user_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* R_CEU_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/drivers/ceu/src/r_ceu_driver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,836 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ *******************************************************************************/
+/**************************************************************************//**
+ * File Name :   r_ceu_driver.c
+ * @file         r_ceu_driver.c
+ * @version      1.00
+ * $Rev: 200 $
+ * $Date:: 2017-05-17 15:19:00 +0900#$
+ * @brief        CEU driver API functions
+ ******************************************************************************/
+
+/******************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ******************************************************************************/
+#include "r_typedefs.h"
+#include "r_ceu.h"
+
+/******************************************************************************
+ Typedef definitions
+ ******************************************************************************/
+
+/******************************************************************************
+ Macro definitions
+ ******************************************************************************/
+#define CEU_SW_RESET        (0x00010000u)
+#define CAPSR_CPKIL_BIT     (0x00010000u)
+#define CSTSR_CPTON_BIT     (0x00000001u)
+#define CAPSR_CE_BIT        (0x00000001u)
+
+/* Driver is not supported register vale */
+#define CAPCR_FDRP_VALUE    (0u)      /* The frame drop count is 0               */
+#define CAPCR_MTCM_VALUE    (0u)      /* Transferred to the bus in 32-byte units */
+#define CAPCR_CTNCP_VALUE   (0u)      /* One-frame capture                       */
+#define CAIFR_IFS_VALUE     (0u)      /* Progressive */
+#define CAIFR_CIM_VALUE     (0u)      /* Capture of frame image (1 VD) or both-field image (2 VD) */
+#define CAIFR_FC_VALUE      (0u)      /* Capture starts from the VD input immediately after
+                                         the CEU activation regardless of it being a top or bottom field */
+#define CRCNTR_RVS_VALUE    (0u)      /* Switches the register plane every 2 VD */
+#define CRCNTR_RS_VALUE     (0u)      /* Uses plane A of the register */
+#define CRCNTR_RC_VALUE     (0u)      /* Uses the specified register plane in synchronization with VD */
+#define CFLCR_VMANT_VALUE   (0u)      /* Mantissa Part of Vertical Scale-Down Factor */
+#define CFLCR_VFRAC_VALUE   (0u)      /* Fraction Part of Vertical Scale-Down Factor */
+#define CFLCR_HMANT_VALUE   (0u)      /* Mantissa Part of Horizontal Scale-Down Factor */
+#define CFLCR_HFRAC_VALUE   (0u)      /* Fraction Part of Horizontal Scale-Down Factor */
+#define CMCYR_VCYL_VALUE    (0u)      /* Vertical HD Count for illegal VD is 0      */
+#define CMCYR_HCYL_VALUE    (0u)      /* Horizontal Cycle Count for illegal HD is 0 */
+#define CLFCR_LPF_VALUE     (0u)      /* Low-pass filter used (only in the horizontal direction) */
+#define CAMCR_FLDPOL_VALUE  (0u)      /* When the FLD signal is high-active,
+                                         the field is detected as the top field
+                                         and when low-active, the field is detected as the bottom field.  */
+#define CDOCR_CBE_VALUE     (0u)      /* Normal write */
+#define CDOCR_CDS_VALUE     (1u)      /* Outputs data in the YCbCr422 format to the memory without conversion */
+#define CFWCR_FWV_VALUE     (0u)      /* The upper limit of a write address */
+#define CFWCR_FWE_VALUE     (0u)      /* Firewall is not activated */
+
+
+/* Driver check value */
+#define VOFST_MAX_0FFF      (0x00000FFFu)  /* VOFST MAX check   */
+#define HOFST_MAX_1FFF      (0x00001FFFu)  /* HOFST MAX check   */
+#define VWDTH_MAX_1920      (1920u)        /* VWDTH MAX check   */
+/* HWDTH MAX check */
+#define HWDTH_MAX_5120      (5120u)        /* CEU_IMAGE_CAPTURE_MODE & 8bit  */
+#define HWDTH_MAX_2560      (2560u)        /* CEU_DATA_SYNC_MODE     & 8bit  */
+#define HWDTH_MAX_1280      (1280u)        /* CEU_DATA_SYNC_MODE     & 16bit */
+#define CHDW_MAX_1FFF       (0x00001FFFu)  /* CHDW MAX check   */
+#define CHDW_MAX_8188       (8188u)        /* CHDW MAX check   */
+
+#define CEU_SHIFT_VALUE_1   (1u)
+#define CEU_SHIFT_VALUE_2   (2u)
+#define CEU_SHIFT_VALUE_4   (4u)
+#define CEU_SHIFT_VALUE_8   (8u)
+#define CEU_SHIFT_VALUE_12  (12u)
+#define CEU_SHIFT_VALUE_16  (16u)
+#define CEU_SHIFT_VALUE_20  (20u)
+#define CEU_SHIFT_VALUE_24  (24u)
+#define CEU_SHIFT_VALUE_28  (28u)
+
+#define CETCR_CLARE_VALUE   (0x00000000u)
+#define CEIER_CLARE_VALUE   (0x00000000u)
+
+/******************************************************************************
+ Imported global variables and functions (from other files)
+ ******************************************************************************/
+
+/******************************************************************************
+ Exported global variables and functions (to be accessed by other files)
+ ******************************************************************************/
+
+/******************************************************************************
+ Private global variables and functions
+ ******************************************************************************/
+static ceu_error_t ceu_open_check_prm(const ceu_config_t * const config);
+static ceu_error_t ceu_execute_check_prm(const void * cayr, const void * cacr, const uint32_t chdw);
+static int32_t ceu_align_check(const uint32_t value, uint32_t align);
+
+static void (*ceu_int_callback)(ceu_int_type_t interrupt_flag);
+
+static ceu_jpg_t local_jpg;
+static ceu_dtif_t local_dtif;
+static uint32_t local_hwdth;
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Initialize
+ * @brief       CEU initialization processing
+ * @param[in]   init_func       : user func
+ * @param[in]   user_num        : user param
+ * @retval      None
+ ******************************************************************************/
+void R_CEU_Initialize(void (* const init_func)(uint32_t), const uint32_t user_num)
+{
+    /* call back function */
+    if (NULL != init_func)
+    {
+        init_func (user_num);
+    }
+
+    /* init */
+    local_jpg = CEU_IMAGE_CAPTURE_MODE;
+    local_dtif = CEU_8BIT_DATA_PINS;
+    local_hwdth = 0;
+
+    return;
+} /* End of function R_CEU_Initialize() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Open
+ * @brief       CEU config setting
+ * @param[in]   config       : CEU configuration
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Open(const ceu_config_t * const config)
+{
+    ceu_error_t error;
+
+    /* param check */
+    error = ceu_open_check_prm (config);
+
+    if (CEU_OK == error)
+    {
+        local_jpg = config->jpg;
+        local_dtif = config->dtif;
+
+        /* Capture Interface Control Register (CAMCR)
+         * bit16 FLDPOL - Sets the polarity of the field identification signal (FLD) from an external module.
+         * bit12 DTIF - Sets the digital image input pins from which data is to be captured.
+         * bit9-8 DTARY[1:0] - These bits set the input order of the luminance component and chrominance component.
+         * bit5-4 JPG[1:0] - These bits select the fetched data type. : b'01 (Data synchronous fetch mode)
+         * bit1 VDPOL - Sets the polarity for detection of the vertical sync signal input from an external module.
+         * bit0 HDPOL - Sets the polarity for detection of the horizontal sync signal input from an external module.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CAMCR = (uint32_t) (
+                (((((CAMCR_FLDPOL_VALUE << CEU_SHIFT_VALUE_16) | (config->dtif << 12u)) | (config->dtary << 8u))
+                        | (config->jpg << 4u)) | (config->vdpol << 1u)) | config->hdpol);
+
+        if (CEU_DATA_ENABLE_MODE != config->jpg)
+        {
+            if (NULL != config->cap)
+            {
+                local_hwdth = config->cap->hwdth;
+
+                /* Capture Interface Offset Register (CAMOR)
+                 * This register is used, during Data synchronous fetch mode.
+                 */
+                CEU.CAMOR_A = (uint32_t) ((config->cap->vofst << 16u) | config->cap->hofst);
+
+                /* Capture Interface Width Register (CAPWR)
+                 * This register is used, during Data synchronous fetch mode.
+                 */
+                CEU.CAPWR_A = (uint32_t) ((config->cap->vwdth << 16u) | config->cap->hwdth);
+            }
+        }
+
+        {
+            uint32_t vfclp = 0;
+            uint32_t hfclp = 0;
+
+            if (CEU_IMAGE_CAPTURE_MODE == config->jpg)
+            {
+                vfclp = config->clp->vfclp;
+                hfclp = config->clp->hfclp;
+            }
+            else if (CEU_DATA_SYNC_MODE == config->jpg)
+            {
+                if (CEU_8BIT_DATA_PINS == config->dtif)
+                {
+                    vfclp = config->cap->vwdth;
+                    hfclp = config->cap->hwdth / 2;
+                }
+
+                if (CEU_16BIT_DATA_PINS == config->dtif)
+                {
+                    vfclp = config->cap->vwdth;
+                    hfclp = config->cap->hwdth;
+                }
+            }
+            else
+            {
+                vfclp = 0u;
+                hfclp = 0u;
+            }
+
+            /* Capture Filter Size Clip Register (CFSZR)
+             this register used in Data synchronous fetch mode. */
+            CEU.CFSZR_A = ((vfclp << 16) | hfclp);
+        }
+
+        /* Capture Data Output Control Register (CDOCR)
+         * bit16 CBE - Controls the number of lines of captured data to be written to the memory.
+         * bit4  CDS - Sets the image format when outputting the image data captured
+         in the YCbCr 422 format to the memory.
+         * bit2 COLS - Controls swapping in 32-bit units for data output from the CEU.
+         * bit1 COWS - Controls swapping in 16-bit units for data output from the CEU.
+         * bit0 COBS - Controls swapping in 8-bit units for data output from the CEU.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CDOCR_A = (uint32_t) (
+                ((((CDOCR_CBE_VALUE << CEU_SHIFT_VALUE_16) | (CDOCR_CDS_VALUE << CEU_SHIFT_VALUE_4))
+                        | (config->cols << CEU_SHIFT_VALUE_2)) | (config->cows << CEU_SHIFT_VALUE_1)) | config->cobs);
+
+        /* Capture Interface Cycle Register (CMCYR)
+         * Set 0 in all bits of this register, during Data enable fetch mode.
+         */
+        CEU.CMCYR = (uint32_t) ((CMCYR_VCYL_VALUE << 16u) |
+        CMCYR_HCYL_VALUE);
+
+        /* capture control register (CAPCR)
+         * bit31-24 FDRP[7:0] - the frame drop interval in continuous frame capture. : set H'00 (Single Capture mode)
+         * bit21-20 MTCM[1:0] - These bits specify the unit for transferring data to a bus bridge module. : variable.
+         * bit16 CTNCP - Continuous capture bit : b'0 (One-frame capture)
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CAPCR = (uint32_t) (
+                ((CAPCR_FDRP_VALUE << CEU_SHIFT_VALUE_24) | (CAPCR_MTCM_VALUE << CEU_SHIFT_VALUE_20))
+                        | (CAPCR_CTNCP_VALUE << CEU_SHIFT_VALUE_16));
+
+        /* Capture Interface Input Format Register (CAIFR)
+         * this register used in Data synchronous fetch mode.
+         */
+        CEU.CAIFR = (uint32_t) (((CAIFR_IFS_VALUE << CEU_SHIFT_VALUE_8) | (CAIFR_CIM_VALUE << CEU_SHIFT_VALUE_4)) |
+        CAIFR_FC_VALUE);
+
+        /* CEU Register Control Register (CRCNTR)
+         * bit4 RVS - Sets the timing to switch the register plane in both-field capture.
+         * bit1 RS - Specifies which register plane is used by the CEU in synchronization with VD.
+         * bit0 RC - Specifies switching of the register plane used by the CEU in synchronization with VD.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CRCNTR = (uint32_t) (((CRCNTR_RVS_VALUE << CEU_SHIFT_VALUE_4) | (CRCNTR_RS_VALUE << CEU_SHIFT_VALUE_1)) |
+        CRCNTR_RC_VALUE);
+
+        /* Capture Filter Control Register (CFLCR)
+         * In data fetch mode, set CFLCR to 0.
+         */
+        CEU.CFLCR_A = (uint32_t) (
+                (((CFLCR_VMANT_VALUE << CEU_SHIFT_VALUE_28) | (CFLCR_VFRAC_VALUE << CEU_SHIFT_VALUE_16))
+                        | (CFLCR_HMANT_VALUE << CEU_SHIFT_VALUE_12)) |
+                CFLCR_HFRAC_VALUE);
+
+        /* Memory address for Bundle write */
+        CEU.CDBYR_A = 0u;
+        CEU.CDBCR_A = 0u;
+        CEU.CDAYR2_A = 0u;
+        CEU.CDACR2_A = 0u;
+        CEU.CDBYR2_A = 0u;
+        CEU.CDBCR2_A = 0u;
+
+        /* Capture Bundle Destination Size Register (CBDSR)
+         * bit22-0 CBVS[22:0] -
+         These bits select the number of lines or number of bytes for output to the memory in a bundle write.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CBDSR_A = 0u; /* sample program not support bundle write mode */
+
+        /* Capture Low-Pass Filter Control Register (CLFCR)
+         * In data fetch mode, clear the LPF bit to B'0.
+         * bit0 LPF - Enables or disables operation of the low-pass filter. : set b'1
+         */
+        CEU.CLFCR_A = CLFCR_LPF_VALUE;
+
+        /* Firewall Operation Control Register (CFWCR)
+         * bit31-5 FWV[26:0] - These bits specify the upper limit of a write address.
+         Specify the upper 27 bits of the 32-bit address. : set 0
+         * bit0 FWE - FW enable/disable. : set 0 (disable)
+         */
+        CEU.CFWCR = (uint32_t) ((CFWCR_FWV_VALUE << 5u) | CFWCR_FWE_VALUE);
+    }
+
+    return error;
+
+} /* End of function R_CEU_Open() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Execute
+ * @brief       CEU Execute
+ * @param[in]   cayr          : Capture buffer (Y)
+ * @param[in]   cacr          : Capture buffer (CbCr)
+ * @param[in]   chdw          : stride
+ * @param[in]   auto_capture  : ceu_onoff_t
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Execute(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture)
+{
+    ceu_error_t error;
+
+    /* param check */
+    error = ceu_execute_check_prm (cayr, cacr, chdw);
+    if (CEU_OK == error)
+    {
+        CEU.CDAYR_A = R_CEU_CPUVAddrToSysPAddr((uint32_t) cayr);
+        CEU.CDACR_A = R_CEU_CPUVAddrToSysPAddr((uint32_t) cacr);
+
+        /* Capture Destination Width Register (CDWDR)
+         * this register used in Data synchronous fetch mode.
+         */
+        CEU.CDWDR_A = chdw;
+
+        if( CEU_ON == auto_capture )
+        {
+            CEU.CAPCR |= 0x00010000u;
+        }
+        else
+        {
+            CEU.CAPCR &= ~0x00010000u;
+        }
+
+        /* start capture */
+        /* Capture Start Register (CAPSR)
+         * bit0 CE - Capture Enable : set b'1 (Starts capturing)
+         * other bit is not change.
+         */
+        CEU.CAPSR |= CAPSR_CE_BIT;
+    }
+
+    return error;
+
+} /* End of function R_CEU_Execute() */
+
+#if(1) /* mbed */
+/**************************************************************************//**
+ * Function Name: R_CEU_Execute_Setting
+ * @brief       CEU Execute
+ * @param[in]   cayr          : Capture buffer (Y)
+ * @param[in]   cacr          : Capture buffer (CbCr)
+ * @param[in]   chdw          : stride
+ * @param[in]   auto_capture  : ceu_onoff_t
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Execute_Setting(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture)
+{
+    ceu_error_t error;
+
+    /* param check */
+    error = ceu_execute_check_prm (cayr, cacr, chdw);
+    if (CEU_OK == error)
+    {
+        CEU.CDAYR_A = R_CEU_CPUVAddrToSysPAddr((uint32_t) cayr);
+        CEU.CDACR_A = R_CEU_CPUVAddrToSysPAddr((uint32_t) cacr);
+
+        /* Capture Destination Width Register (CDWDR)
+         * this register used in Data synchronous fetch mode.
+         */
+        CEU.CDWDR_A = chdw;
+
+        if( CEU_ON == auto_capture )
+        {
+            CEU.CAPCR |= 0x00010000u;
+        }
+        else
+        {
+            CEU.CAPCR &= ~0x00010000u;
+        }
+    }
+
+    return error;
+
+} /* End of function R_CEU_Execute() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Start
+ * @brief       CEU Execute
+ * @param[in]   None
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Start(void)
+{
+    ceu_error_t error = CEU_OK;
+
+    /* start capture */
+    /* Capture Start Register (CAPSR)
+     * bit0 CE - Capture Enable : set b'1 (Starts capturing)
+     * other bit is not change.
+     */
+    CEU.CAPSR |= CAPSR_CE_BIT;
+
+    return error;
+} /* End of function R_CEU_Start() */
+
+#endif
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Stop
+ * @brief       CEU Execute
+ * @param[in]   None
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Stop(void)
+{
+    ceu_error_t error = CEU_OK;
+
+    CEU.CAPSR &= ~0x00000001;
+
+    return error;
+} /* End of function R_CEU_Stop() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Terminate
+ * @brief       CEU Close
+ * @param[in]   quit_func  : user func
+ * @param[in]   user_num   : user param
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Terminate(void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    ceu_error_t error = CEU_OK;
+
+    /* software reset
+     * bit16 CPKIL : set 1 (Software reset of capturing)
+     * bit0 CE     : set 0 (Stops capturing)
+     */
+    CEU.CAPSR = CEU_SW_RESET;
+
+    /* wait software reset complete
+     * Complete : CSTSR.CPTON = b'0 & CAPSR.CPKIL=b'0
+     * [CSTSR]
+     * bit0 CPTON - Indicates that the CEU is operating.
+     * [CAPSR]
+     * bit16 CPKIL - Write 1 to this bit to perform a software reset of capturing.
+     */
+    while (0u != (CEU.CSTSR & CSTSR_CPTON_BIT))
+    {
+        /* wait state :"Halted" */
+    }
+
+    while (0u != (CEU.CAPSR & CAPSR_CPKIL_BIT))
+    {
+        /* wait state :"Normal" */
+    }
+
+    /* call back function */
+    if (NULL != quit_func)
+    {
+        quit_func (user_num);
+    }
+
+    return error;
+} /* End of function R_CEU_Terminate() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_InterruptEnable
+ * @brief       CEU Interrupt Enable
+ * @param[in]   int_type       : Capture Event Interrupt Enable Register (CEIER)
+ * @param[in]   callback       : Callback func
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+void R_CEU_InterruptEnable(const ceu_int_type_t int_type, void (* const callback)(ceu_int_type_t))
+{
+    /* Callback function pointer */
+    ceu_int_callback = callback;
+
+    /* Capture Event Interrupt Enable Register (CEIER)  */
+    CEU.CEIER = int_type;
+
+} /* End of function R_CEU_InterruptEnable() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_InterruptDisable
+ * @brief       CEU Interrupt Disable
+ * @retval      None
+ ******************************************************************************/
+void R_CEU_InterruptDisable(void)
+{
+    /* Callback function pointer clear */
+    ceu_int_callback = 0;
+
+    /* Capture Event Interrupt Enable Register (CEIER) claer */
+    CEU.CEIER = CEIER_CLARE_VALUE;
+
+} /* End of function R_CEU_InterruptDisable() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Isr
+ * @brief       CEU interrupt handler
+ * @param[in]   int_sense       :
+ * @retval      None
+ ******************************************************************************/
+void R_CEU_Isr(const uint32_t int_sense)
+{
+    uint32_t interrupt_flag;
+
+    /* get interrupt flag */
+    interrupt_flag = CEU.CETCR;
+
+    /* clear interrupt flag
+     * Capture Event Flag Clear Register (CETCR)
+     * To clear the bit corresponding to the interrupt source
+     to be cleared to 0 and retain that state, write 1 to that bit.
+     */
+    CEU.CETCR = CETCR_CLARE_VALUE; /* clear all */
+
+    if (NULL != ceu_int_callback)
+    {
+        /* callback func */
+        ceu_int_callback ((ceu_int_type_t) interrupt_flag);
+    }
+
+} /* End of function R_CEU_Isr() */
+
+/**************************************************************************//**
+ * Function Name: ceu_open_check_prm
+ * @brief       CEU Open check param
+ * @param[in]   config       : CEU configuration
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+static ceu_error_t ceu_open_check_prm(const ceu_config_t * const config)
+{
+    ceu_error_t error = CEU_OK;
+
+    if (NULL != config)
+    {
+        if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) || (CEU_DATA_SYNC_MODE == config->jpg))
+        {
+            if (NULL == config->cap)
+            {
+                error = CEU_ERR_PARAM;
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) || (CEU_DATA_SYNC_MODE == config->jpg))
+            {
+                /* vofst max */
+                if (((uint32_t) config->cap->vofst & (uint32_t) ~VOFST_MAX_0FFF) != 0u)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hofst max */
+                if (((uint32_t) config->cap->hofst & (uint32_t) ~HOFST_MAX_1FFF) != 0u)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) || (CEU_DATA_SYNC_MODE == config->jpg))
+            {
+                /* vwdth max */
+                if (config->cap->vwdth > VWDTH_MAX_1920)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* vwdth align 4 */
+                if (ceu_align_check (config->cap->vwdth, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            /* CEU_IMAGE_CAPTURE_MODE & 8bit */
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) && (CEU_8BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_5120)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 8 */
+                if (ceu_align_check (config->cap->hwdth, 8u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+
+            /* CEU_DATA_SYNC_MODE & 8bit */
+            if ((CEU_DATA_SYNC_MODE == config->jpg) && (CEU_8BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_2560)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 4 */
+                if (ceu_align_check (config->cap->hwdth, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+
+        if (NULL != config)
+        {
+            /* RZ/A1H, M */
+            /* CEU_IMAGE_CAPTURE_MODE & 16bit */
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) && (CEU_16BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_2560)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 4 */
+                if (ceu_align_check (config->cap->hwdth, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+
+        if (NULL != config)
+        {
+            /* CEU_DATA_SYNC_MODE & 16bit */
+            if ((CEU_DATA_SYNC_MODE == config->jpg) && (CEU_16BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_1280)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 2 */
+                if (ceu_align_check (config->cap->hwdth, 2u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if (CEU_IMAGE_CAPTURE_MODE == config->jpg)
+            {
+                if (NULL == config->clp)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if (CEU_IMAGE_CAPTURE_MODE == config->jpg)
+            {
+                /* vfclp align 4 */
+                if (ceu_align_check (config->clp->vfclp, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hfclp align 4 */
+                if (ceu_align_check (config->clp->hfclp, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+    return error;
+} /* End of function ceu_open_check_prm() */
+
+/**************************************************************************//**
+ * Function Name: ceu_execute_check_prm
+ * @brief       CEU Execute check param
+ * @param[in]   cayr       : Capture buffer (Y)
+ * @param[in]   cacr       : Capture buffer (CbCr)
+ * @param[in]   chdw       : stride
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+static ceu_error_t ceu_execute_check_prm(const void * cayr, const void * cacr, const uint32_t chdw)
+{
+    ceu_error_t error = CEU_OK;
+
+    if (CEU_IMAGE_CAPTURE_MODE == local_jpg)
+    {
+        if ((NULL == cayr) || (NULL == cacr))
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* cayr align 4 */
+        if (ceu_align_check ((uint32_t) cayr, 4u) != 0)
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* cacr align 4 */
+        if (ceu_align_check ((uint32_t) cacr, 4u) != 0)
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* chdw max */
+        if (chdw > CHDW_MAX_8188)
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* chdw align 4 */
+        if (ceu_align_check ((uint32_t) chdw, 4u) != 0)
+        {
+            error = CEU_ERR_PARAM;
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (CEU_DATA_SYNC_MODE == local_jpg)
+        {
+            if (NULL == cayr)
+            {
+                error = CEU_ERR_PARAM;
+            }
+
+            /* cayr align 4 */
+            if (ceu_align_check ((uint32_t) cayr, 4u) != 0)
+            {
+                error = CEU_ERR_PARAM;
+            }
+
+            if (CEU_16BIT_DATA_PINS == local_dtif)
+            {
+                if ((local_hwdth * 2) != chdw)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+
+            if (CEU_8BIT_DATA_PINS == local_dtif)
+            {
+                if (local_hwdth != chdw)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (CEU_DATA_ENABLE_MODE == local_jpg)
+        {
+            if (NULL == cayr)
+            {
+                error = CEU_ERR_PARAM;
+            }
+
+            /* cayr align 4 */
+            if (ceu_align_check ((uint32_t) cayr, 32u) != 0)
+            {
+                error = CEU_ERR_PARAM;
+            }
+        }
+    }
+
+    return error;
+} /* End of function ceu_execute_check_prm() */
+
+/**************************************************************************//**
+ * Function Name: ceu_align_check
+ * @brief       align check
+ * @param[in]   value       : check value
+ * @param[in]   align       : align value
+ * @retval      OK(0) NG(-1)
+ ******************************************************************************/
+static int32_t ceu_align_check(const uint32_t value, uint32_t align)
+{
+    int32_t error;
+
+    align -= 1u;
+    if ((value & align) != 0)
+    {
+        error = -1;
+    }
+    else
+    {
+        error = 0;
+    }
+
+    return error;
+} /* End of function ceu_align_check() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A1XX/drivers/ceu/userdef/ceu_userdef.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         ceu_userdef.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L CEU driver user function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis.h"
+#include "ceu_iodefine.h"
+#include "ceu_iobitmask.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "r_ceu.h"
+#include "r_ceu_user.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define STP66_BIT               (0x40u)
+#define STBRQ10_BIT             (0x01u)
+#define STBAK10_BIT             (0x01u)
+
+#define CEU_INTERRUPT_PRIORITY  (5u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/**************************************************************************//**
+ * @brief       Physical address translation
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Get the System Physical address of the given virtual memory address.
+ * @param[in]   vaddr               : virtual address
+ * @retval      physical address
+ *****************************************************************************/
+uint32_t R_CEU_CPUVAddrToSysPAddr(uint32_t vaddr)
+{
+    return vaddr;
+}   /* End of function R_CEU_CPUVAddrToSysPAddr() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_OnInitialize
+ * @brief       CEU User difinistion part Init
+ * @param[in]   user_num          :
+ * @retval      none
+ *****************************************************************************/
+void R_CEU_OnInitialize(const uint32_t user_num)
+{
+    uint32_t reg_data;
+    volatile uint8_t dummy_read;
+
+    /* Standby control register 6 (STBCR6)
+        b6      -0------;  MSTP66 : 0 : CEU enable */
+    reg_data    = (uint32_t)CPG.STBCR6 & (uint32_t)~STP66_BIT;
+    CPG.STBCR6  = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR6;
+    (void)dummy_read;
+
+    /* Standby Request Register 1 (STBREQ1)
+        b0      -------0;  STBRQ10 : The standby request to CEU is invalid. */
+    reg_data    = (uint32_t)CPG.STBREQ1 & (uint32_t)~STBRQ10_BIT;
+    CPG.STBREQ1 = (uint8_t)reg_data;
+    /* Standby Acknowledge Register 1 (STBACK1)
+        b0      -------*;  STBAK10 : Standby acknowledgement from CEU. */
+    while (((uint32_t)CPG.STBACK1 & (uint32_t)STBAK10_BIT) != 0u) {
+        /* Wait for the STBAK10 to be cleared to 0. */
+    }
+
+    InterruptHandlerRegister(CEUI_IRQn, R_CEU_Isr);
+    GIC_SetPriority(CEUI_IRQn, (uint8_t)CEU_INTERRUPT_PRIORITY);
+    GIC_SetConfiguration(CEUI_IRQn, 1);
+    GIC_EnableIRQ(CEUI_IRQn);
+} /* End of function R_CEU_OnInitialize() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_OnFinalize
+ * @brief       CEU User difinistion part final
+ * @param[in]   user_num          :
+ * @retval      none
+ *****************************************************************************/
+void R_CEU_OnFinalize(const uint32_t user_num)
+{
+    uint32_t reg_data;
+    volatile uint8_t dummy_read;
+
+    /* Standby Request Register 1 (STBREQ1)
+        b0      -------1;  STBRQ10 : The standby request to CEU is valid. */
+    reg_data    = (uint32_t)CPG.STBREQ1 | (uint32_t)STBRQ10_BIT;
+    CPG.STBREQ1 = (uint8_t)reg_data;
+    /* Standby Acknowledge Register 1 (STBACK1)
+        b0      -------*;  STBAK10 : Standby acknowledgement from CEU. */
+    while (((uint32_t)CPG.STBACK1 & (uint32_t)STBAK10_BIT) == 0u) {
+        /* Wait for the STBAK10 to be set to 1. */
+    }
+
+    /* Standby control register 6 (STBCR6)
+        b6      -1------;  MSTP56 : 1 : CEU disable */
+    reg_data    = (uint32_t)CPG.STBCR6 | (uint32_t)STP66_BIT;
+    CPG.STBCR6  = (uint8_t)reg_data;
+
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR6;
+    (void)dummy_read;
+
+} /* End of function R_CEU_OnFinalize() */
+
+/* End of File */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/inc/r_spea.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_spea.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver API definitions
+******************************************************************************/
+
+#ifndef R_SPEA_H
+#define R_SPEA_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc.h"
+
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define VIRTUAL_FRAME_BASE_ADD      (0x30000000u)
+#define VIRTUAL_FRAME_STRAID        (8192u)
+
+/*! Error codes of the VDC driver */
+typedef enum
+{
+    SPEA_OK = 0,                /*!< Normal termination */
+    SPEA_ERR_PARAM_LAYER_ID,    /*!< Invalid layer ID error (parameter error): An illegal layer ID is specified. */
+    SPEA_ERR_PARAM_NULL,        /*!< NULL specification error (parameter error):
+                                     NULL is specified for a required parameter. */
+    SPEA_ERR_PARAM,             /*!< Detecting the specification violation. */
+    SPEA_ERR_NUM                /*!< The number of error codes */
+} spea_error_t;
+
+/*! Layer ID */
+typedef enum
+{
+    SPEA_LAYER_ID_0   = 0,   /*!< SPE layer 0 */
+    SPEA_LAYER_ID_1   = 1,   /*!< SPE layer 1 */
+    SPEA_LAYER_ID_NUM = 2    /*!< The number of layer IDs */
+} spea_layer_id_t;
+
+/*! On/off */
+typedef enum
+{
+    SPEA_OFF    = 0,            /*!< Off */
+    SPEA_ON     = 1             /*!< On */
+} spea_onoff_t;
+
+/*! On/off */
+typedef enum
+{
+    RLE_OFF    = 0,            /*!< Off */
+    RLE_ON     = 1             /*!< On */
+} rle_onoff_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************* For R_SPEA_SetWindow       *******************************/
+/*! Window position control parameter for SPEA */
+/*! Error codes of the VDC driver */
+typedef enum
+{
+    WINDOW_00 = 0,
+    WINDOW_01,
+    WINDOW_02,
+    WINDOW_03,
+    WINDOW_04,
+    WINDOW_05,
+    WINDOW_06,
+    WINDOW_07,
+    WINDOW_08,
+    WINDOW_09,
+    WINDOW_10,
+    WINDOW_11,
+    WINDOW_12,
+    WINDOW_13,
+    WINDOW_14,
+    WINDOW_15,
+    WINDOW_NUM
+} spea_window_id_t;
+
+typedef struct
+{
+    int32_t x;                     /*!< Line offset address direction of the frame buffer */
+    int32_t y;                     /*!< Line offset address direction of the frame buffer */
+} spea_skpsm_t;
+
+/*! Window size control parameter for SPEA */
+typedef struct
+{
+	int32_t width;                 /*!< Line offset address direction of the frame buffer */
+	int32_t height;                /*!< Line offset address direction of the frame buffer */
+} spea_sklym_t;
+
+/*! Window control parameter for SPEA */
+typedef struct
+{
+	spea_window_id_t  window_id;   /*! Window ID for SPEA */
+	spea_onoff_t      sken;        /*! Window on/off for SPEA */
+	spea_skpsm_t      pos;         /*! Window position control parameter for SPEA */
+    spea_sklym_t      size;        /*! Window size control parameter for SPEA */
+    const void      * buffer;      /*! Window buffer control parameter for SPEA */
+} spea_window_conf_t;
+
+/******************************* For R_RLE_SetWindow       *******************************/
+/*! RLE Window control parameter */
+typedef struct
+{
+	int32_t rlen;                 /*!< Burst size of the RLE unit next data pre-fetching */
+	int32_t rdth;                 /*!< Pre-fetch timing for FIFO */
+} rle_cfg_t;
+
+/*! targa structure */
+typedef struct
+{
+	uint8_t   id_length;            /*!< Length of the image ID field  */
+	uint8_t   color_map_type;       /*!< Whether a color map is included */
+	uint8_t   image_type;           /*!< Compression and color types */
+	uint8_t   first_entry_index[2]; /*!< index of first color map entry that is included in the file */
+	uint8_t   color_map_length[2];  /*!< number of entries of the color map that are included in the file */
+	uint8_t   color_map_entry_size; /*!< number of bits per pixel */
+	uint8_t   x_origin[2];          /*!< absolute coordinate of lower-left corner for displays
+	                                    where origin is at the lower left  */
+	uint8_t   y_origin[2];          /*!< as for X-origin */
+	uint8_t   image_width[2];       /*!< width in pixels */
+	uint8_t   image_height[2];      /*!< height in pixels */
+	uint8_t   pixel_depth;          /*!< bits per pixel */
+	uint8_t   image_descriptor;     /*!< bits 3-0 give the alpha channel depth, bits 5-4 give direction */
+
+} targa_struct_t;
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+/*--- SPEA function --------------------------------------*/
+
+spea_error_t R_SPEA_SetWindow(
+    const vdc_layer_id_t       layer_id,
+    const spea_window_id_t     window_id,
+    const spea_onoff_t         sken,
+	const spea_sklym_t       * sklym,
+    const spea_skpsm_t       * skpsm,
+	const void               * buffer);
+spea_error_t R_SPEA_WindowOffset(
+    const vdc_layer_id_t       layer_id,
+    const uint16_t             offset_x,
+    const uint16_t             offset_y);
+spea_error_t R_SPEA_WindowUpdate(
+    const vdc_layer_id_t       layer_id);
+
+/*--- RLE function --------------------------------------*/
+
+spea_error_t R_RLE_SetWindow(
+	const vdc_error_t    layer_id,
+    const rle_onoff_t    rbussel,
+	const rle_cfg_t    * rle_cfg,
+	const void         * buffer);
+spea_error_t R_RLE_WindowUpdate(
+    const vdc_layer_id_t   layer_id);
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_SPE_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/inc/r_spea_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_spea_user.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver user-defined header
+******************************************************************************/
+
+#ifndef R_SPEA_USER_H
+#define R_SPEA_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Compilation switch to enable parameter check functions<br>
+    If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_SPEA_CHECK_PARAMETERS
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+uint32_t R_SPEA_CPUVAddrToSysPAddr(uint32_t vaddr);
+
+#endif  /* R_SPEA_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/inc/r_vdc.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1018 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver API definitions
+******************************************************************************/
+
+#ifndef R_VDC_H
+#define R_VDC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc_user.h"
+
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC_GAM_GAIN_ADJ_NUM       (32u)   /*!< The number of the gamma correction gain coefficient */
+#define     VDC_GAM_START_TH_NUM       (31u)   /*!< The number of the gamma correction start threshold */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDC driver */
+typedef enum
+{
+    VDC_OK = 0,                /*!< Normal termination */
+    VDC_ERR_PARAM_CHANNEL,     /*!< Invalid channel error (parameter error): An illegal channel is specified. */
+    VDC_ERR_PARAM_LAYER_ID,    /*!< Invalid layer ID error (parameter error): An illegal layer ID is specified. */
+    VDC_ERR_PARAM_NULL,        /*!< NULL specification error (parameter error):
+                                    NULL is specified for a required parameter. */
+    VDC_ERR_PARAM_BIT_WIDTH,   /*!< Bit width error (parameter error):
+                                    A value exceeding the possible bit width is specified. */
+    VDC_ERR_PARAM_UNDEFINED,   /*!< Undefined parameter error (parameter error):
+                                    A value that is not defined in the specification is specified. */
+    VDC_ERR_PARAM_EXCEED_RANGE,/*!< Out-of-value-range error (parameter error):
+                                    The specified parameter value is beyond the value range defined
+                                    in the specification. */
+    VDC_ERR_PARAM_CONDITION,   /*!< Unauthorized condition error (parameter error):
+                                    A parameter is specified under conditions that are not authorized
+                                    by the specification. */
+    VDC_ERR_IF_CONDITION,      /*!< Interface condition error (interface error):
+                                    An API function is called under unauthorized conditions. */
+    VDC_ERR_RESOURCE_CLK,      /*!< Clock resource error (resource error): No panel clock is set up. */
+    VDC_ERR_RESOURCE_VSYNC,    /*!< Vsync signal resource error (resource error): No Vsync signal is set up. */
+    VDC_ERR_RESOURCE_INPUT,    /*!< Input signal resource error (resource error): No video image input is set up. */
+    VDC_ERR_RESOURCE_OUTPUT,   /*!< Output resource error (resource error): No display output is set up. */
+    VDC_ERR_RESOURCE_LVDS_CLK, /*!< LVDS clock resource error (resource error):
+                                    An attempt is made to use the LVDS clock without setting it up,
+                                    or the LVDS clock is specified when it is already set up. */
+    VDC_ERR_RESOURCE_LAYER,    /*!< Layer resource error (resource error):
+                                    The specified layer is under unavailable conditions. */
+    VDC_ERR_NUM                /*!< The number of error codes */
+} vdc_error_t;
+
+/*! VDC channels */
+typedef enum
+{
+    VDC_CHANNEL_0 = 0,         /*!< Channel 0 */
+    VDC_CHANNEL_NUM            /*!< The number of channels */
+} vdc_channel_t;
+
+/*! On/off */
+typedef enum
+{
+    VDC_OFF    = 0,            /*!< Off */
+    VDC_ON     = 1             /*!< On */
+} vdc_onoff_t;
+/*! Edge of a signal */
+typedef enum
+{
+    VDC_EDGE_RISING    = 0,    /*!< Rising edge */
+    VDC_EDGE_FALLING   = 1     /*!< Falling edge */
+} vdc_edge_t;
+/*! Polarity of a signal */
+typedef enum
+{
+    VDC_SIG_POL_NOT_INVERTED   = 0,    /*!< Not inverted */
+    VDC_SIG_POL_INVERTED       = 1     /*!< Inverted */
+} vdc_sig_pol_t;
+
+/*! Scaling type ID */
+typedef enum
+{
+    VDC_SC_TYPE_SC0 = 0,               /*!< Scaler 0 */
+    VDC_SC_TYPE_NUM                    /*!< The number of scaler types */
+} vdc_scaling_type_t;
+/*! Graphics type ID */
+typedef enum
+{
+    VDC_GR_TYPE_GR0 = 0,               /*!< Graphics 0 */
+    VDC_GR_TYPE_GR2,                   /*!< Graphics 2 */
+    VDC_GR_TYPE_GR3,                   /*!< Graphics 3 */
+    VDC_GR_TYPE_NUM                    /*!< The number of graphics types */
+} vdc_graphics_type_t;
+/*! Layer ID */
+typedef enum
+{
+    VDC_LAYER_ID_ALL       = -1,                                     /*!< All layers */
+    VDC_LAYER_ID_0_WR      = (VDC_SC_TYPE_SC0 + 0),                  /*!< Write process for layer 0 */
+    VDC_LAYER_ID_0_RD      = (VDC_SC_TYPE_NUM + VDC_GR_TYPE_GR0),    /*!< Read process for layer 0 */
+    VDC_LAYER_ID_2_RD      = (VDC_SC_TYPE_NUM + VDC_GR_TYPE_GR2),    /*!< Read process for layer 2 */
+    VDC_LAYER_ID_3_RD      = (VDC_SC_TYPE_NUM + VDC_GR_TYPE_GR3),    /*!< Read process for layer 3 */
+    VDC_LAYER_ID_NUM       = (VDC_SC_TYPE_NUM + VDC_GR_TYPE_NUM)     /*!< The number of layer IDs */
+} vdc_layer_id_t;
+/*! The horizontal/vertical timing of the VDC signals */
+typedef struct
+{
+    uint16_t    vs;                 /*!< Vertical signal start position from the reference signal */
+    uint16_t    vw;                 /*!< Vertical signal width (height) */
+    uint16_t    hs;                 /*!< Horizontal signal start position from the reference signal */
+    uint16_t    hw;                 /*!< Horizontal signal width */
+} vdc_period_rect_t;
+/*! The relative position within the graphics display area */
+typedef struct
+{
+    uint16_t   vs_rel;              /*!< Vertical start position */
+    uint16_t   vw_rel;              /*!< Vertical width (height) */
+    uint16_t   hs_rel;              /*!< Horizontal start position */
+    uint16_t   hw_rel;              /*!< Horizontal width */
+} vdc_pd_disp_rect_t;
+
+/***********************    For R_VDC_Initialize       ***********************/
+/*! Panel clock select */
+typedef enum
+{
+    VDC_PANEL_ICKSEL_IMG_DV = 0,   /*!< Divided video image clock (DV_CLK) */
+    VDC_PANEL_ICKSEL_EXT_0,        /*!< Divided external clock (LCD0_EXTCLK) */
+    VDC_PANEL_ICKSEL_PERI,         /*!< Divided peripheral clock 1 */
+    VDC_PANEL_ICKSEL_LVDS,         /*!< LVDS PLL clock */
+    VDC_PANEL_ICKSEL_LVDS_DIV7,    /*!< LVDS PLL clock divided by 7 */
+    VDC_PANEL_ICKSEL_NUM           /*!< The number of panel clock select settings */
+} vdc_panel_clksel_t;
+/*! Clock frequency division ratio */
+typedef enum
+{
+    VDC_PANEL_CLKDIV_1_1 = 0,      /*!< Division Ratio 1/1 */
+    VDC_PANEL_CLKDIV_1_2,          /*!< Division Ratio 1/2 */
+    VDC_PANEL_CLKDIV_1_3,          /*!< Division Ratio 1/3 */
+    VDC_PANEL_CLKDIV_1_4,          /*!< Division Ratio 1/4 */
+    VDC_PANEL_CLKDIV_1_5,          /*!< Division Ratio 1/5 */
+    VDC_PANEL_CLKDIV_1_6,          /*!< Division Ratio 1/6 */
+    VDC_PANEL_CLKDIV_1_7,          /*!< Division Ratio 1/7 */
+    VDC_PANEL_CLKDIV_1_8,          /*!< Division Ratio 1/8 */
+    VDC_PANEL_CLKDIV_1_9,          /*!< Division Ratio 1/9 */
+    VDC_PANEL_CLKDIV_1_12,         /*!< Division Ratio 1/12 */
+    VDC_PANEL_CLKDIV_1_16,         /*!< Division Ratio 1/16 */
+    VDC_PANEL_CLKDIV_1_24,         /*!< Division Ratio 1/24 */
+    VDC_PANEL_CLKDIV_1_32,         /*!< Division Ratio 1/32 */
+    VDC_PANEL_CLKDIV_NUM           /*!< The number of division ratio settings */
+} vdc_panel_clk_dcdr_t;
+/*! The clock input to frequency divider 1 */
+typedef enum
+{
+//  VDC_LVDS_INCLK_SEL_IMG,        /*!< Video image clock (VIDEO_X1) */
+    VDC_LVDS_INCLK_SEL_DV_0 = 0,   /*!< Video image clock (DV0_CLK) */
+//  VDC_LVDS_INCLK_SEL_DV_1,       /*!< Video image clock (DV1_CLK) */
+    VDC_LVDS_INCLK_SEL_EXT_0,      /*!< External clock (LCD0_EXTCLK) */
+//  VDC_LVDS_INCLK_SEL_EXT_1,      /*!< External clock (LCD1_EXTCLK) */
+    VDC_LVDS_INCLK_SEL_PERI,       /*!< Peripheral clock 1 */
+    VDC_LVDS_INCLK_SEL_NUM
+} vdc_lvds_in_clk_sel_t;
+/*! The frequency dividing value (NIDIV or NODIV) */
+typedef enum
+{
+    VDC_LVDS_NDIV_1 = 0,           /*!< Div 1 */
+    VDC_LVDS_NDIV_2,               /*!< Div 2 */
+    VDC_LVDS_NDIV_4,               /*!< Div 4 */
+    VDC_LVDS_NDIV_NUM
+} vdc_lvds_ndiv_t;
+/*! The frequency dividing value (NOD) for the output frequency */
+typedef enum
+{
+    VDC_LVDS_PLL_NOD_1 = 0,        /*!< Div 1 */
+    VDC_LVDS_PLL_NOD_2,            /*!< Div 2 */
+    VDC_LVDS_PLL_NOD_4,            /*!< Div 4 */
+    VDC_LVDS_PLL_NOD_8,            /*!< Div 8 */
+    VDC_LVDS_PLL_NOD_NUM
+} vdc_lvds_pll_nod_t;
+/*! LVDS parameter */
+typedef struct
+{
+    vdc_lvds_in_clk_sel_t   lvds_in_clk_sel; /*!< The clock input to frequency divider 1 */
+    vdc_lvds_ndiv_t         lvds_idiv_set;   /*!< The frequency dividing value (NIDIV) for frequency divider 1 */
+    uint16_t                lvdspll_tst;     /*!< Internal parameter setting for LVDS PLL */
+    vdc_lvds_ndiv_t         lvds_odiv_set;   /*!< The frequency dividing value (NODIV) for frequency divider 2 */
+    vdc_channel_t           lvds_vdc_sel;    /*!< A channel in VDC whose data is to be output through the LVDS */
+    uint16_t                lvdspll_fd;      /*!< The frequency dividing value (NFD) for the feedback frequency */
+    uint16_t                lvdspll_rd;      /*!< The frequency dividing value (NRD) for the input frequency */
+    vdc_lvds_pll_nod_t      lvdspll_od;      /*!< The frequency dividing value (NOD) for the output frequency */
+} vdc_lvds_t;
+/*! Initialization parameter */
+typedef struct
+{
+    vdc_panel_clksel_t     panel_icksel;   /*!< Panel clock select */
+    vdc_panel_clk_dcdr_t   panel_dcdr;     /*!< Clock frequency division ratio */
+    const vdc_lvds_t     * lvds;           /*!< LVDS-related parameter */
+} vdc_init_t;
+
+/***********************    For R_VDC_VideoInput       ***********************/
+/*! Input select */
+typedef enum
+{
+    VDC_INPUT_SEL_EXT      = 1     /*!< Signals supplied via the external input pins */
+} vdc_input_sel_t;
+/*! Sync signal delay adjustment parameter */
+typedef struct
+{
+    uint16_t    inp_vs_dly_l;       /*!< Number of lines for delaying Vsync signal and field differentiation signal */
+    uint16_t    inp_fld_dly;        /*!< Field differentiation signal delay amount */
+    uint16_t    inp_vs_dly;         /*!< Vsync signal delay amount */
+    uint16_t    inp_hs_dly;         /*!< Hsync signal delay amount */
+} vdc_sync_delay_t;
+/*! External input format select */
+typedef enum
+{
+    VDC_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 */
+    VDC_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+    VDC_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+    VDC_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+    VDC_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+    VDC_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+    VDC_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 */
+    VDC_EXTIN_FORMAT_NUM
+} vdc_extin_format_t;
+/*! Reference select for external input BT.656 Hsync signal */
+typedef enum
+{
+    VDC_EXTIN_REF_H_EAV    = 0,    /*!< EAV */
+    VDC_EXTIN_REF_H_SAV    = 1     /*!< SAV */
+} vdc_extin_ref_hsync_t;
+/*! Number of lines for BT.656 external input */
+typedef enum
+{
+    VDC_EXTIN_LINE_525     = 0,    /*!< 525 lines */
+    VDC_EXTIN_LINE_625     = 1     /*!< 625 lines */
+} vdc_extin_input_line_t;
+/*! Y/Cb/Y/Cr data string start timing */
+typedef enum
+{
+    VDC_EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+    VDC_EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+    VDC_EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+    VDC_EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+    VDC_EXTIN_H_POS_NUM
+} vdc_extin_h_pos_t;
+/*! External input signal parameter */
+typedef struct
+{
+    vdc_extin_format_t     inp_format;     /*!< External input format select */
+    vdc_edge_t             inp_pxd_edge;   /*!< Clock edge select for capturing external input video image signals */
+    vdc_edge_t             inp_vs_edge;    /*!< Clock edge select for capturing external input Vsync signals */
+    vdc_edge_t             inp_hs_edge;    /*!< Clock edge select for capturing external input Hsync signals */
+    vdc_onoff_t            inp_endian_on;  /*!< External input bit endian change on/off control */
+    vdc_onoff_t            inp_swap_on;    /*!< External input B/R signal swap on/off control */
+    vdc_sig_pol_t          inp_vs_inv;     /*!< External input Vsync signal DV_VSYNC inversion control */
+    vdc_sig_pol_t          inp_hs_inv;     /*!< External input Hsync signal DV_HSYNC inversion control */
+    vdc_extin_ref_hsync_t  inp_h_edge_sel; /*!< Reference select for external input BT.656 Hsync signal */
+    vdc_extin_input_line_t inp_f525_625;   /*!< Number of lines for BT.656 external input */
+    vdc_extin_h_pos_t      inp_h_pos;      /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+} vdc_ext_in_sig_t;
+/*! Video input setup parameter */
+typedef struct
+{
+    vdc_input_sel_t             inp_sel;    /*!< Input select */
+    uint16_t                    inp_fh50;   /*!< Vsync signal 1/2fH phase timing */
+    uint16_t                    inp_fh25;   /*!< Vsync signal 1/4fH phase timing */
+    const vdc_sync_delay_t    * dly;        /*!< Sync signal delay adjustment parameter */
+    const vdc_ext_in_sig_t    * ext_sig;    /*!< External input signal parameter */
+} vdc_input_t;
+
+/***********************    For R_VDC_SyncControl      ***********************/
+/*! Horizontal/vertical sync signal output and full-screen enable signal select */
+typedef enum
+{
+    VDC_RES_VS_IN_SEL_SC0  = 0     /*!< Sync signal output and full-screen enable signal from scaler 0 */
+} vdc_res_vs_in_sel_t;
+/*! Vsync signal compensation parameter */
+typedef struct
+{
+    uint16_t        res_vmask;              /*!< Repeated Vsync signal masking period */
+    uint16_t        res_vlack;              /*!< Missing-Sync compensating pulse output wait time */
+} vdc_vsync_cpmpe_t;
+/*! Synchronization control parameter */
+typedef struct
+{
+    vdc_onoff_t                 res_vs_sel;     /*!< Vsync signal output select (free-running Vsync on/off control) */
+    vdc_res_vs_in_sel_t         res_vs_in_sel;  /*!< Horizontal/vertical sync signal output
+                                                     and full-screen enable signal select */
+    uint16_t                    res_fv;         /*!< Free-running Vsync period setting */
+    uint16_t                    res_fh;         /*!< Hsync period setting */
+    uint16_t                    res_vsdly;      /*!< Vsync signal delay control */
+    vdc_period_rect_t           res_f;          /*!< Full-screen enable signal */
+    const vdc_vsync_cpmpe_t   * vsync_cpmpe;    /*!< Vsync signal compensation parameter */
+} vdc_sync_ctrl_t;
+
+/***********************    For R_VDC_DisplayOutput    ***********************/
+/*! POLA/POLB signal generation mode select */
+typedef enum
+{
+    VDC_LCD_TCON_POLMD_NORMAL = 0,         /*!< Normal mode */
+    VDC_LCD_TCON_POLMD_1X1REV,             /*!< 1x1 reverse mode */
+    VDC_LCD_TCON_POLMD_1X2REV,             /*!< 1x2 reverse mode */
+    VDC_LCD_TCON_POLMD_2X2REV,             /*!< 2x2 reverse mode */
+    VDC_LCD_TCON_POLMD_NUM
+} vdc_lcd_tcon_polmode_t;
+/*! Signal operating reference select */
+typedef enum
+{
+    VDC_LCD_TCON_REFSEL_HSYNC      = 0,    /*!< Hsync signal reference */
+    VDC_LCD_TCON_REFSEL_OFFSET_H   = 1     /*!< Offset Hsync signal reference */
+} vdc_lcd_tcon_refsel_t;
+/*! LCD TCON output pin select */
+typedef enum
+{
+    VDC_LCD_TCON_PIN_NON = -1,             /*!< Nothing output */
+    VDC_LCD_TCON_PIN_0,                    /*!< LCD_TCON0 */
+    VDC_LCD_TCON_PIN_1,                    /*!< LCD_TCON1 */
+    VDC_LCD_TCON_PIN_2,                    /*!< LCD_TCON2 */
+    VDC_LCD_TCON_PIN_3,                    /*!< LCD_TCON3 */
+    VDC_LCD_TCON_PIN_4,                    /*!< LCD_TCON4 */
+    VDC_LCD_TCON_PIN_5,                    /*!< LCD_TCON5 */
+    VDC_LCD_TCON_PIN_6,                    /*!< LCD_TCON6 */
+    VDC_LCD_TCON_PIN_NUM
+} vdc_lcd_tcon_pin_t;
+/*! LCD TCON timing signal parameter */
+typedef struct
+{
+    uint16_t                tcon_hsvs;      /*!< Signal pulse start position */
+    uint16_t                tcon_hwvw;      /*!< Pulse width */
+    vdc_lcd_tcon_polmode_t  tcon_md;        /*!< POLA/POLB signal generation mode select */
+    vdc_lcd_tcon_refsel_t   tcon_hs_sel;    /*!< Signal operating reference select */
+    vdc_sig_pol_t           tcon_inv;       /*!< Polarity inversion control of signal */
+    vdc_lcd_tcon_pin_t      tcon_pin;       /*!< LCD TCON output pin select */
+    vdc_edge_t              outcnt_edge;    /*!< Output phase control of signal */
+} vdc_lcd_tcon_timing_t;
+/*! Timing signals for driving the LCD panel */
+typedef enum
+{
+    VDC_LCD_TCONSIG_STVA_VS = 0,            /*!< STVA/VS */
+    VDC_LCD_TCONSIG_STVB_VE,                /*!< STVB/VE */
+    VDC_LCD_TCONSIG_STH_SP_HS,              /*!< STH/SP/HS */
+    VDC_LCD_TCONSIG_STB_LP_HE,              /*!< STB/LP/HE */
+    VDC_LCD_TCONSIG_CPV_GCK,                /*!< CPV/GCK */
+    VDC_LCD_TCONSIG_POLA,                   /*!< POLA */
+    VDC_LCD_TCONSIG_POLB,                   /*!< POLB */
+    VDC_LCD_TCONSIG_DE,                     /*!< DE */
+    VDC_LCD_TCONSIG_NUM
+} vdc_lcd_tcon_sigsel_t;
+/*! Output format select */
+typedef enum
+{
+    VDC_LCD_OUTFORMAT_RGB888 = 0,           /*!< RGB888 */
+    VDC_LCD_OUTFORMAT_RGB666,               /*!< RGB666 */
+    VDC_LCD_OUTFORMAT_RGB565,               /*!< RGB565 */
+    VDC_LCD_OUTFORMAT_SERIAL_RGB,           /*!< Serial RGB */
+    VDC_LCD_OUTFORMAT_NUM
+} vdc_lcd_outformat_t;
+/*! Clock frequency control */
+typedef enum
+{
+    VDC_LCD_PARALLEL_CLKFRQ_1 = 0,          /*!< 100% speed (parallel RGB) */
+    VDC_LCD_SERIAL_CLKFRQ_3,                /*!< Triple speed (serial RGB) */
+    VDC_LCD_SERIAL_CLKFRQ_4,                /*!< Quadruple speed (serial RGB) */
+    VDC_LCD_SERIAL_CLKFRQ_NUM
+} vdc_lcd_clkfreqsel_t;
+/*! Scan direction select */
+typedef enum
+{
+    VDC_LCD_SERIAL_SCAN_FORWARD   = 0,      /*!< Forward scan */
+    VDC_LCD_SERIAL_SCAN_REVERSE   = 1       /*!< Reverse scan */
+} vdc_lcd_scan_t;
+/*! Clock phase adjustment for serial RGB output */
+typedef enum
+{
+    VDC_LCD_SERIAL_CLKPHASE_0 = 0,          /*!< 0[clk] */
+    VDC_LCD_SERIAL_CLKPHASE_1,              /*!< 1[clk] */
+    VDC_LCD_SERIAL_CLKPHASE_2,              /*!< 2[clk] */
+    VDC_LCD_SERIAL_CLKPHASE_3,              /*!< 3[clk] */
+    VDC_LCD_SERIAL_CLKPHASE_NUM
+} vdc_lcd_clkphase_t;
+/*! Display output configuration parameter */
+typedef struct
+{
+    uint16_t                        tcon_half;                      /*!< 1/2fH timing */
+    uint16_t                        tcon_offset;                    /*!< Offset Hsync signal timing */
+    const vdc_lcd_tcon_timing_t   * outctrl[VDC_LCD_TCONSIG_NUM];   /*!< LCD TCON timing signal parameter */
+    vdc_edge_t                      outcnt_lcd_edge;                /*!< Output phase control of LCD_DATA23
+                                                                         to LCD_DATA0 pin */
+    vdc_onoff_t                     out_endian_on;                  /*!< Bit endian change on/off control */
+    vdc_onoff_t                     out_swap_on;                    /*!< B/R signal swap on/off control */
+    vdc_lcd_outformat_t             out_format;                     /*!< Output format select */
+    vdc_lcd_clkfreqsel_t            out_frq_sel;                    /*!< Clock frequency control */
+    vdc_lcd_scan_t                  out_dir_sel;                    /*!< Scan direction select */
+    vdc_lcd_clkphase_t              out_phase;                      /*!< Clock phase adjustment
+                                                                         for serial RGB output */
+    uint32_t                        bg_color;                       /*!< Background color in 24-bit RGB color format */
+} vdc_output_t;
+
+/***********************    For R_VDC_CallbackISR      ***********************/
+/*! VDC interrupt type */
+typedef enum
+{
+    VDC_INT_TYPE_S0_VI_VSYNC = 0,       /*!< Vsync signal input to scaler 0 */
+    VDC_INT_TYPE_S0_LO_VSYNC,           /*!< Vsync signal output from scaler 0 */
+    VDC_INT_TYPE_S0_VSYNCERR,           /*!< Missing Vsync signal for scaler 0 */
+    VDC_INT_TYPE_VLINE,                 /*!< Specified line signal for panel output in graphics 3 */
+    VDC_INT_TYPE_S0_VFIELD,             /*!< Field end signal for recording function in scaler 0 */
+    VDC_INT_TYPE_IV1_VBUFERR,           /*!< Frame buffer write overflow signal for scaler 0 */
+    VDC_INT_TYPE_IV3_VBUFERR,           /*!< Frame buffer read underflow signal for graphics 0 */
+    VDC_INT_TYPE_IV5_VBUFERR,           /*!< Frame buffer read underflow signal for graphics 2 */
+    VDC_INT_TYPE_IV6_VBUFERR,           /*!< Frame buffer read underflow signal for graphics 3 */
+    VDC_INT_TYPE_S0_WLINE,              /*!< Write specification line signal input to scaling-down control block
+                                             in scaler 0 */
+    VDC_INT_TYPE_NUM                    /*!< The number of VDC interrupt types */
+} vdc_int_type_t;
+/*! Interrupt callback setup parameter */
+typedef struct
+{
+    vdc_int_type_t      type;                       /*!< VDC interrupt type */
+    void             (* callback)(vdc_int_type_t);  /*!< Interrupt callback function pointer */
+    uint16_t            line_num;                   /*!< Line interrupt set */
+} vdc_int_t;
+
+/***********************    For R_VDC_WriteDataControl ***********************/
+/*! Frame buffer writing mode for image processing */
+typedef enum
+{
+    VDC_WR_MD_NORMAL = 0,                   /*!< Normal */
+    VDC_WR_MD_MIRROR,                       /*!< Horizontal mirroring */
+    VDC_WR_MD_ROT_90DEG,                    /*!< 90 degree rotation */
+    VDC_WR_MD_ROT_180DEG,                   /*!< 180 degree rotation */
+    VDC_WR_MD_ROT_270DEG,                   /*!< 270 degree rotation */
+    VDC_WR_MD_NUM
+} vdc_wr_md_t;
+/*! Scaling-down and rotation parameter */
+typedef struct
+{
+    vdc_period_rect_t   res;                /*!< Image area to be captured */
+    vdc_onoff_t         res_pfil_sel;       /*!< Prefilter mode select for brightness signals (on/off) */
+    uint16_t            res_out_vw;         /*!< Number of valid lines in vertical direction
+                                                 output by scaling-down control block */
+    uint16_t            res_out_hw;         /*!< Number of valid horizontal pixels
+                                                 output by scaling-down control block */
+    vdc_onoff_t         adj_sel;            /*!< Handling for lack of last-input line (on/off) */
+    vdc_wr_md_t         res_ds_wr_md;       /*!< Frame buffer writing mode for image processing */
+} vdc_scalingdown_rot_t;
+/*! Frame buffer swap setting */
+typedef enum
+{
+    VDC_WR_RD_WRSWA_NON = 0,            /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+    VDC_WR_RD_WRSWA_8BIT,               /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+    VDC_WR_RD_WRSWA_16BIT,              /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+    VDC_WR_RD_WRSWA_16_8BIT,            /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+    VDC_WR_RD_WRSWA_32BIT,              /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+    VDC_WR_RD_WRSWA_32_8BIT,            /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+    VDC_WR_RD_WRSWA_32_16BIT,           /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+    VDC_WR_RD_WRSWA_32_16_8BIT,         /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    VDC_WR_RD_WRSWA_NUM
+} vdc_wr_rd_swa_t;
+/*! Frame buffer video-signal writing format */
+typedef enum
+{
+    VDC_RES_MD_YCBCR422 = 0,                /*!< YCbCr422 */
+    VDC_RES_MD_RGB565,                      /*!< RGB565 */
+    VDC_RES_MD_RGB888,                      /*!< RGB888 */
+    VDC_RES_MD_YCBCR444,                    /*!< YCbCr444 */
+    VDC_RES_MD_NUM
+} vdc_res_md_t;
+/*! Transfer burst length */
+typedef enum
+{
+    VDC_BST_MD_32BYTE = 0,                  /*!< 32-byte transfer (4 bursts) */
+    VDC_BST_MD_128BYTE                      /*!< 128-byte transfer (16 bursts) */
+} vdc_bst_md_t;
+/*! Field operating mode select */
+typedef enum
+{
+    VDC_RES_INTER_PROGRESSIVE  = 0,         /*!< Progressive */
+    VDC_RES_INTER_INTERLACE    = 1          /*!< Interlace */
+} vdc_res_inter_t;
+/*! Writing rate */
+typedef enum
+{
+    VDC_RES_FS_RATE_PER1 = 0,               /* 1/1 an input signal */
+    VDC_RES_FS_RATE_PER2,                   /* 1/2 an input signal */
+    VDC_RES_FS_RATE_PER4,                   /* 1/4 an input signal */
+    VDC_RES_FS_RATE_PER8,                   /* 1/8 an input signal */
+    VDC_RES_FS_RATE_NUM
+} vdc_res_fs_rate_t;
+/*! Write field select */
+typedef enum
+{
+    VDC_RES_FLD_SEL_TOP    = 0,             /*!< Top field */
+    VDC_RES_FLD_SEL_BOTTOM = 1              /*!< Bottom field */
+} vdc_res_fld_sel_t;
+/*! Data write control parameter */
+typedef struct
+{
+    vdc_scalingdown_rot_t   scalingdown_rot;/*!< Scaling-down and rotation parameter */
+    vdc_wr_rd_swa_t         res_wrswa;      /*!< Swap setting in frame buffer writing */
+    vdc_res_md_t            res_md;         /*!< Frame buffer video-signal writing format */
+    vdc_bst_md_t            res_bst_md;     /*!< Transfer burst length for frame buffer writing */
+    vdc_res_inter_t         res_inter;      /*!< Field operating mode select */
+    vdc_res_fs_rate_t       res_fs_rate;    /*!< Writing rate */
+    vdc_res_fld_sel_t       res_fld_sel;    /*!< Write field select */
+    vdc_onoff_t             res_dth_on;     /*!< Dither correction on/off */
+    void                  * base;           /*!< Frame buffer base address */
+    uint32_t                ln_off;         /*!< Frame buffer line offset address [byte] */
+    uint32_t                flm_num;        /*!< Number of frames of buffer to be written to (res_flm_num + 1) */
+    uint32_t                flm_off;        /*!< Frame buffer frame offset address [byte] */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+} vdc_write_t;
+
+/***********************  For R_VDC_ChangeWriteProcess ***********************/
+/*! Data write change parameter */
+typedef struct
+{
+    vdc_scalingdown_rot_t   scalingdown_rot;/*!< Scaling-down and rotation parameter */
+} vdc_write_chg_t;
+
+/***********************  For R_VDC_ReadDataControl    ***********************/
+/*! Line offset address direction of the frame buffer */
+typedef enum
+{
+    VDC_GR_LN_OFF_DIR_INC = 0,              /*!< Increments the address by the line offset address */
+    VDC_GR_LN_OFF_DIR_DEC                   /*!< Decrements the address by the line offset address */
+} vdc_gr_ln_off_dir_t;
+/*! Frame buffer address setting signal */
+typedef enum
+{
+    VDC_GR_FLM_SEL_SCALE_DOWN      = 0,         /*!< Links to scaling-down process */
+    VDC_GR_FLM_SEL_FLM_NUM         = 1,         /*!< Selects frame 0 (graphics display) */
+    VDC_GR_FLM_SEL_DISTORTION      = 2,         /*!< Links to distortion correction */
+    VDC_GR_FLM_SEL_POINTER_BUFF    = 3,         /*!< Links to pointer buffer */
+    VDC_GR_FLM_SEL_NUM
+} vdc_gr_flm_sel_t;
+/*! Size of the frame buffer to be read */
+typedef struct
+{
+    uint16_t                in_vw;          /*!< Number of lines in a frame */
+    uint16_t                in_hw;          /*!< Width of the horizontal valid period */
+} vdc_width_read_fb_t;
+/*! Format of the frame buffer read signal */
+typedef enum
+{
+    VDC_GR_FORMAT_RGB565 = 0,               /*!< RGB565 */
+    VDC_GR_FORMAT_RGB888,                   /*!< RGB888 */
+    VDC_GR_FORMAT_ARGB1555,                 /*!< ARGB1555 */
+    VDC_GR_FORMAT_ARGB4444,                 /*!< ARGB4444 */
+    VDC_GR_FORMAT_ARGB8888,                 /*!< ARGB8888 */
+    VDC_GR_FORMAT_CLUT8,                    /*!< CLUT8 */
+    VDC_GR_FORMAT_CLUT4,                    /*!< CLUT4 */
+    VDC_GR_FORMAT_CLUT1,                    /*!< CLUT1 */
+    VDC_GR_FORMAT_YCBCR422,                 /*!< YCbCr422: This setting is prohibited for the graphics 2 and 3 */
+    VDC_GR_FORMAT_YCBCR444,                 /*!< YCbCr444: This setting is prohibited for the graphics 2 and 3 */
+    VDC_GR_FORMAT_RGBA5551,                 /*!< RGBA5551 */
+    VDC_GR_FORMAT_RGBA8888,                 /*!< RGBA8888 */
+    VDC_GR_FORMAT_NUM                       /*!< The number of signal formats */
+} vdc_gr_format_t;
+/*! Swapping of data read from buffer in the YCbCr422 format */
+typedef enum
+{
+    VDC_GR_YCCSWAP_CBY0CRY1 = 0,
+    VDC_GR_YCCSWAP_Y0CBY1CR,
+    VDC_GR_YCCSWAP_CRY0CBY1,
+    VDC_GR_YCCSWAP_Y0CRY1CB,
+    VDC_GR_YCCSWAP_Y1CRY0CB,
+    VDC_GR_YCCSWAP_CRY1CBY0,
+    VDC_GR_YCCSWAP_Y1CBY0CR,
+    VDC_GR_YCCSWAP_CBY1CRY0,
+    VDC_GR_YCCSWAP_NUM
+} vdc_gr_ycc_swap_t;
+/*! Data read control parameter */
+typedef struct
+{
+    vdc_gr_ln_off_dir_t             gr_ln_off_dir;  /*!< Line offset address direction of the frame buffer */
+    vdc_gr_flm_sel_t                gr_flm_sel;     /*!< Frame buffer address setting signal */
+    vdc_onoff_t                     gr_imr_flm_inv; /*!< Frame buffer number for distortion correction */
+    vdc_bst_md_t                    gr_bst_md;      /*!< Frame buffer burst transfer mode */
+    void                          * gr_base;        /*!< Frame buffer base address */
+    uint32_t                        gr_ln_off;      /*!< Frame buffer line offset address */
+    const vdc_width_read_fb_t     * width_read_fb;  /*!< Size of the frame buffer to be read */
+    vdc_onoff_t                     adj_sel;        /*!< Folding handling (on/off) */
+    vdc_gr_format_t                 gr_format;      /*!< Format of the frame buffer read signal */
+    vdc_gr_ycc_swap_t               gr_ycc_swap;    /*!< Swapping of data read from buffer
+                                                         in the YCbCr422 format */
+    vdc_wr_rd_swa_t                 gr_rdswa;       /*!< Swap setting in frame buffer reading */
+    vdc_period_rect_t               gr_grc;         /*!< Graphics display area */
+} vdc_read_t;
+
+/******************************* For R_VDC_ChangeReadProcess       *******************************/
+/*! The type of graphics display modes */
+typedef enum
+{
+    VDC_DISPSEL_IGNORED    = -1,        /*!< Ignored */
+    VDC_DISPSEL_BACK       = 0,         /*!< Background color display */
+    VDC_DISPSEL_LOWER      = 1,         /*!< Lower-layer graphics display */
+    VDC_DISPSEL_CURRENT    = 2,         /*!< Current graphics display */
+    VDC_DISPSEL_BLEND      = 3,         /*!< Blended display of lower-layer graphics and current graphics */
+    VDC_DISPSEL_NUM        = 4          /*!< The number of graphics display modes */
+} vdc_gr_disp_sel_t;
+/*! Data read change parameter */
+typedef struct
+{
+    void                          * gr_base;        /*!< Frame buffer base address */
+    const vdc_width_read_fb_t     * width_read_fb;  /*!< Size of the frame buffer to be read */
+    const vdc_period_rect_t       * gr_grc;         /*!< Graphics display area */
+    const vdc_gr_disp_sel_t       * gr_disp_sel;    /*!< Graphics display mode */
+} vdc_read_chg_t;
+
+/******************************* For R_VDC_StartProcess            *******************************/
+/*! Data write/read start parameter */
+typedef struct
+{
+    const vdc_gr_disp_sel_t      * gr_disp_sel;    /*!< Graphics display mode */
+} vdc_start_t;
+
+/******************************* For R_VDC_VideoNoiseReduction     *******************************/
+/*! TAP select */
+typedef enum
+{
+    VDC_NR_TAPSEL_1 = 0,            /*!< Adjacent pixel */
+    VDC_NR_TAPSEL_2,                /*!< 2 adjacent pixels */
+    VDC_NR_TAPSEL_3,                /*!< 3 adjacent pixels */
+    VDC_NR_TAPSEL_4,                /*!< 4 adjacent pixels */
+    VDC_NR_TAPSEL_NUM
+} vdc_nr_tap_t;
+/*! Noise reduction gain adjustment */
+typedef enum
+{
+    VDC_NR_GAIN_1_2 = 0,            /*!< 1/2 */
+    VDC_NR_GAIN_1_4,                /*!< 1/4 */
+    VDC_NR_GAIN_1_8,                /*!< 1/8 */
+    VDC_NR_GAIN_1_16,               /*!< 1/16 */
+    VDC_NR_GAIN_NUM
+} vdc_nr_gain_t;
+/*! Noise reduction parameter */
+typedef struct
+{
+    vdc_nr_tap_t    nr1d_tap;       /*!< TAP select */
+    uint32_t        nr1d_th;        /*!< Maximum value of coring (absolute value) */
+    vdc_nr_gain_t   nr1d_gain;      /*!< Noise reduction gain adjustment */
+} vdc_nr_param_t;
+/*! Noise reduction setup parameter */
+typedef struct
+{
+    vdc_nr_param_t     y;           /*!< Y/G signal noise reduction parameter */
+    vdc_nr_param_t     cb;          /*!< Cb/B signal noise reduction parameter */
+    vdc_nr_param_t     cr;          /*!< Cr/R signal noise reduction parameter */
+} vdc_noise_reduction_t;
+
+/******************************* For R_VDC_ImageColorMatrix        *******************************/
+/*! Color matrix module */
+typedef enum
+{
+    VDC_COLORMTX_IMGCNT = 0,            /*!< Input Controller (input video signal) */
+    VDC_COLORMTX_ADJ_0,                 /*!< Image quality improver 0 (scaler 0 output) */
+    VDC_COLORMTX_NUM
+} vdc_colormtx_module_t;
+/*! Operating mode */
+typedef enum
+{
+    VDC_COLORMTX_GBR_GBR = 0,           /*!< GBR to GBR */
+    VDC_COLORMTX_GBR_YCBCR,             /*!< GBR to YCbCr */
+    VDC_COLORMTX_YCBCR_GBR,             /*!< YCbCr to GBR */
+    VDC_COLORMTX_YCBCR_YCBCR,           /*!< YCbCr to YCbCr */
+    VDC_COLORMTX_MODE_NUM               /*!< The number of operating modes */
+} vdc_colormtx_mode_t;
+/*! Color matrix offset (DC) adjustment */
+typedef enum
+{
+    VDC_COLORMTX_OFFST_YG = 0,          /*!< YG */
+    VDC_COLORMTX_OFFST_B,               /*!< B */
+    VDC_COLORMTX_OFFST_R,               /*!< R */
+    VDC_COLORMTX_OFFST_NUM              /*!< The number of the color matrix DC offset values */
+} vdc_colormtx_offset_t;
+/*! Color matrix signal gain adjustment */
+typedef enum
+{
+    VDC_COLORMTX_GAIN_GG = 0,           /*!< GG */
+    VDC_COLORMTX_GAIN_GB,               /*!< GB */
+    VDC_COLORMTX_GAIN_GR,               /*!< GR */
+    VDC_COLORMTX_GAIN_BG,               /*!< BG */
+    VDC_COLORMTX_GAIN_BB,               /*!< BB */
+    VDC_COLORMTX_GAIN_BR,               /*!< BR */
+    VDC_COLORMTX_GAIN_RG,               /*!< RG */
+    VDC_COLORMTX_GAIN_RB,               /*!< RB */
+    VDC_COLORMTX_GAIN_RR,               /*!< RR */
+    VDC_COLORMTX_GAIN_NUM               /*!< The number of the color matrix gain values */
+} vdc_colormtx_gain_t;
+/*! Color matrix setup parameter */
+typedef struct
+{
+    vdc_colormtx_module_t   module;                         /*!< Color matrix module */
+    vdc_colormtx_mode_t     mtx_mode;                       /*!< Operating mode */
+    uint16_t                offset[VDC_COLORMTX_OFFST_NUM]; /*!< Offset (DC) adjustment of Y/G, B, and R signal */
+    uint16_t                gain[VDC_COLORMTX_GAIN_NUM];    /*!< GG, GB, GR, BG, BB, BR, RG, RB, and RR signal
+                                                                 gain adjustment */
+} vdc_color_matrix_t;
+
+/******************************* For R_VDC_ImageEnhancement        *******************************/
+/*! Image quality improver ID */
+typedef enum
+{
+    VDC_IMG_IMPRV_0 = 0,            /*!< Image quality improver 0 */
+    VDC_IMG_IMPRV_NUM               /*!< The number of image quality improvers */
+} vdc_imgimprv_id_t;
+
+/*! Sharpness band */
+typedef enum
+{
+    VDC_IMGENH_SHARP_H1 = 0,        /*!< H1: Adjacent pixel used as reference */
+    VDC_IMGENH_SHARP_H2,            /*!< H2: Second adjacent pixel used as reference */
+    VDC_IMGENH_SHARP_H3,            /*!< H3: Third adjacent pixel used as reference */
+    VDC_IMGENH_SHARP_NUM            /*!< The number of horizontal sharpness bands */
+} vdc_img_enh_sh_t;
+/*! Sharpness control parameter */
+typedef struct
+{
+    uint8_t     shp_clip_o;         /*!< Sharpness correction value clipping (on the overshoot side) */
+    uint8_t     shp_clip_u;         /*!< Sharpness correction value clipping (on the undershoot side) */
+    uint8_t     shp_gain_o;         /*!< Sharpness edge amplitude value gain (on the overshoot side) */
+    uint8_t     shp_gain_u;         /*!< Sharpness edge amplitude value gain (on the undershoot side) */
+    uint8_t     shp_core;           /*!< Active sharpness range */
+} vdc_sharpness_ctrl_t;
+/*! Sharpness setup parameter */
+typedef struct
+{
+    vdc_onoff_t             shp_h2_lpf_sel;                     /*!< LPF selection for folding prevention
+                                                                     before H2 edge detection */
+    vdc_sharpness_ctrl_t    hrz_sharp[VDC_IMGENH_SHARP_NUM];    /*!< Sharpness control parameter (H1, H2, and H3) */
+} vdc_enhance_sharp_t;
+/*! LTI band */
+typedef enum
+{
+    VDC_IMGENH_LTI1 = 0,            /*!< H2: Second adjacent pixel used as reference */
+    VDC_IMGENH_LTI2,                /*!< H4: Fourth adjacent pixel used as reference */
+    VDC_IMGENH_LTI_NUM              /*!< The number of horizontal LTI bands */
+} vdc_img_enh_lti_t;
+/*! Median filter reference pixel select */
+typedef enum
+{
+    VDC_LTI_MDFIL_SEL_ADJ2 = 0,     /*!< Second adjacent pixel selected as reference */
+    VDC_LTI_MDFIL_SEL_ADJ1          /*!< Adjacent pixel selected as reference */
+} vdc_lti_mdfil_sel_t;
+/*! LTI control parameter */
+typedef struct
+{
+    uint8_t     lti_inc_zero;       /*!< Median filter LTI correction threshold */
+    uint8_t     lti_gain;           /*!< LTI edge amplitude value gain */
+    uint8_t     lti_core;           /*!< LTI coring (maximum core value of 255) */
+} vdc_lti_ctrl_t;
+/*! Luminance Transient Improvement setup parameter */
+typedef struct
+{
+    vdc_onoff_t             lti_h2_lpf_sel;             /*!< LPF selection for folding prevention
+                                                             before H2 edge detection */
+    vdc_lti_mdfil_sel_t     lti_h4_median_tap_sel;      /*!< Median filter reference pixel select */
+    vdc_lti_ctrl_t          lti[VDC_IMGENH_LTI_NUM];    /*!< LTI control parameter (H2 and H4) */
+} vdc_enhance_lti_t;
+
+/******************************* For R_VDC_ImageBlackStretch       *******************************/
+/*! Black stretch setup parameter */
+typedef struct
+{
+    uint16_t    bkstr_st;           /*!< Black stretch start point */
+    uint16_t    bkstr_d;            /*!< Black stretch depth */
+    uint16_t    bkstr_t1;           /*!< Black stretch time constant (T1) */
+    uint16_t    bkstr_t2;           /*!< Black stretch time constant (T2) */
+} vdc_black_t;
+
+/******************************* For R_VDC_AlphaBlending           *******************************/
+/*! Alpha signal of the ARGB1555/ARGB5551 format */
+typedef struct
+{
+    uint8_t     gr_a0;                  /*!< Alpha signal when alpha is set to '0' */
+    uint8_t     gr_a1;                  /*!< Alpha signal when alpha is set to '1' */
+} vdc_alpha_argb1555_t;
+/*! Alpha blending in one-pixel units */
+typedef struct
+{
+    vdc_onoff_t    gr_acalc_md;         /*!< Premultiplication processing at alpha blending
+                                             in one-pixel units (on/off) */
+} vdc_alpha_pixel_t;
+/*! Alpha blending setup parameter */
+typedef struct
+{
+    const vdc_alpha_argb1555_t   * alpha_1bit; /*!< Alpha signal of the ARGB1555/ARGB5551 format */
+    const vdc_alpha_pixel_t      * alpha_pixel;/*!< Premultiplication processing at alpha blending in one-pixel */
+} vdc_alpha_blending_t;
+
+/******************************* For R_VDC_AlphaBlendingRect       *******************************/
+/*! Parameter for alpha blending in a rectangular area */
+typedef struct
+{
+    int16_t         gr_arc_coef;        /*!< Alpha coefficient for alpha blending in a rectangular area
+                                             (-255 to 255) */
+    uint8_t         gr_arc_rate;        /*!< Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+    uint8_t         gr_arc_def;         /*!< Initial alpha value for alpha blending in a rectangular area */
+    vdc_onoff_t     gr_arc_mul;         /*!< Multiplication processing with current alpha at alpha blending
+                                             in a rectangular area (on/off) */
+} vdc_alpha_rect_t;
+/*! Selection of lower-layer plane in scaler */
+typedef struct
+{
+    vdc_onoff_t     gr_vin_scl_und_sel; /*!< Selection of lower-layer plane in scaler
+                                             - VDC_OFF:  Selects graphics 0 as lower-layer graphics
+                                                         and graphics 1 as current graphics
+                                             - VDC_ON:  Selects graphics 1 as lower-layer graphics
+                                                        and graphics 0 as current graphics */
+} vdc_scl_und_sel_t;
+/*! Setup parameter for alpha blending in a rectangular area */
+typedef struct
+{
+    const vdc_pd_disp_rect_t  * gr_arc;     /*!< Rectangular area subjected to alpha blending */
+    const vdc_alpha_rect_t    * alpha_rect; /*!< Parameter for alpha blending in a rectangular area */
+    const vdc_scl_und_sel_t   * scl_und_sel;/*!< Selection of lower-layer plane in scaler */
+} vdc_alpha_blending_rect_t;
+
+/******************************* For R_VDC_Chromakey               *******************************/
+/*! Chroma-key setup parameter */
+typedef struct
+{
+    uint32_t    ck_color;       /*!< RGB/CLUT signal for RGB/CLUT-index chroma-key processing */
+    uint32_t    rep_color;      /*!< Replaced ARGB signal after RGB/CLUT-index chroma-key processing */
+    uint8_t     rep_alpha;      /*!< Replaced alpha signal after RGB-index chroma-key processing (in 8 bits) */
+} vdc_chromakey_t;
+
+/******************************* For R_VDC_CLUT                    *******************************/
+/*! CLUT setup parameter */
+typedef struct
+{
+    uint32_t            color_num;  /*!< The number of colors in CLUT */
+    const uint32_t    * clut;       /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
+} vdc_clut_t;
+
+/******************************* For R_VDC_DisplayCalibration      *******************************/
+/*! Correction circuit sequence control */
+typedef enum
+{
+    VDC_CALIBR_ROUTE_BCG = 0,           /*!< Brightness -> contrast -> gamma correction */
+    VDC_CALIBR_ROUTE_GBC                /*!< Gamma correction -> brightness -> contrast */
+} vdc_calibr_route_t;
+/*! Brightness (DC) adjustment parameter */
+typedef struct
+{
+    uint16_t    pbrt_g;                 /*!< Brightness (DC) adjustment of G signal */
+    uint16_t    pbrt_b;                 /*!< Brightness (DC) adjustment of B signal */
+    uint16_t    pbrt_r;                 /*!< Brightness (DC) adjustment of R signal */
+} vdc_calibr_bright_t;
+/*! Contrast (gain) adjustment parameter */
+typedef struct
+{
+    uint8_t     cont_g;                 /*!< Contrast (gain) adjustment of G signal */
+    uint8_t     cont_b;                 /*!< Contrast (gain) adjustment of B signal */
+    uint8_t     cont_r;                 /*!< Contrast (gain) adjustment of R signal */
+} vdc_calibr_contrast_t;
+/*! Panel dither operation mode */
+typedef enum
+{
+    VDC_PDTH_MD_TRU = 0,                /*!< Truncate */
+    VDC_PDTH_MD_RDOF,                   /*!< Round-off */
+    VDC_PDTH_MD_2X2,                    /*!< 2 x 2 pattern dither */
+    VDC_PDTH_MD_RAND,                   /*!< Random pattern dither */
+    VDC_PDTH_MD_NUM
+} vdc_panel_dither_md_t;
+/*! Panel dithering parameter */
+typedef struct
+{
+    vdc_panel_dither_md_t  pdth_sel;    /*!< Panel dither operation mode */
+    uint8_t                 pdth_pa;    /*!< Pattern value (A) of 2x2 pattern dither */
+    uint8_t                 pdth_pb;    /*!< Pattern value (B) of 2x2 pattern dither */
+    uint8_t                 pdth_pc;    /*!< Pattern value (C) of 2x2 pattern dither */
+    uint8_t                 pdth_pd;    /*!< Pattern value (D) of 2x2 pattern dither */
+} vdc_calibr_dither_t;
+/*! Display calibration parameter */
+typedef struct
+{
+    vdc_calibr_route_t              route;          /*!< Correction circuit sequence control */
+    const vdc_calibr_bright_t     * bright;         /*!< Brightness (DC) adjustment parameter */
+    const vdc_calibr_contrast_t   * contrast;       /*!< Contrast (gain) adjustment parameter */
+    const vdc_calibr_dither_t     * panel_dither;   /*!< Panel dithering parameter */
+} vdc_disp_calibration_t;
+
+/******************************* For R_VDC_GammaCorrection         *******************************/
+/*! Gamma correction setup parameter */
+typedef struct
+{
+    const uint16_t    * gam_g_gain;     /*!< Gain adjustment of area 0 to 31 of G signal */
+    const uint8_t     * gam_g_th;       /*!< Start threshold of area 1 to 31 of G signal */
+    const uint16_t    * gam_b_gain;     /*!< Gain adjustment of area 0 to 31 of B signal */
+    const uint8_t     * gam_b_th;       /*!< Start threshold of area 1 to 31 of B signal */
+    const uint16_t    * gam_r_gain;     /*!< Gain adjustment of area 0 to 31 of R signal */
+    const uint8_t     * gam_r_th;       /*!< Start threshold of area 1 to 31 of R signal */
+} vdc_gamma_correction_t;
+
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdc_error_t R_VDC_Initialize(
+    const vdc_channel_t         ch,
+    const vdc_init_t    * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num);
+vdc_error_t R_VDC_Terminate(const vdc_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdc_error_t R_VDC_VideoInput(const vdc_channel_t ch, const vdc_input_t * const param);
+vdc_error_t R_VDC_SyncControl(const vdc_channel_t ch, const vdc_sync_ctrl_t * const param);
+vdc_error_t R_VDC_DisplayOutput(const vdc_channel_t ch, const vdc_output_t * const param);
+vdc_error_t R_VDC_CallbackISR(const vdc_channel_t ch, const vdc_int_t * const param);
+vdc_error_t R_VDC_WriteDataControl(
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_write_t  * const param);
+vdc_error_t R_VDC_ChangeWriteProcess(
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_write_chg_t   * const param);
+vdc_error_t R_VDC_ReadDataControl(
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_read_t   * const param);
+vdc_error_t R_VDC_ChangeReadProcess(
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_read_chg_t   * const param);
+vdc_error_t R_VDC_StartProcess(
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_start_t  * const param);
+vdc_error_t R_VDC_StopProcess(const vdc_channel_t ch, const vdc_layer_id_t layer_id);
+vdc_error_t R_VDC_ReleaseDataControl(const vdc_channel_t ch, const vdc_layer_id_t layer_id);
+vdc_error_t R_VDC_VideoNoiseReduction(
+    const vdc_channel_t                    ch,
+    const vdc_onoff_t                      nr1d_on,
+    const vdc_noise_reduction_t    * const param);
+vdc_error_t R_VDC_ImageColorMatrix(const vdc_channel_t ch, const vdc_color_matrix_t * const param);
+vdc_error_t R_VDC_ImageEnhancement(
+    const vdc_channel_t                ch,
+    const vdc_imgimprv_id_t            imgimprv_id,
+    const vdc_onoff_t                  shp_h_on,
+    const vdc_enhance_sharp_t  * const sharp_param,
+    const vdc_onoff_t                  lti_h_on,
+    const vdc_enhance_lti_t    * const lti_param,
+    const vdc_period_rect_t    * const enh_area);
+vdc_error_t R_VDC_ImageBlackStretch(
+    const vdc_channel_t        ch,
+    const vdc_imgimprv_id_t    imgimprv_id,
+    const vdc_onoff_t          bkstr_on,
+    const vdc_black_t  * const param);
+vdc_error_t R_VDC_AlphaBlending(
+    const vdc_channel_t                ch,
+    const vdc_layer_id_t               layer_id,
+    const vdc_alpha_blending_t * const param);
+vdc_error_t R_VDC_AlphaBlendingRect(
+    const vdc_channel_t                        ch,
+    const vdc_layer_id_t                       layer_id,
+    const vdc_onoff_t                          gr_arc_on,
+    const vdc_alpha_blending_rect_t    * const param);
+vdc_error_t R_VDC_Chromakey(
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_onoff_t              gr_ck_on,
+    const vdc_chromakey_t  * const param);
+vdc_error_t R_VDC_CLUT(const vdc_channel_t ch, const vdc_layer_id_t layer_id, const vdc_clut_t * const param);
+vdc_error_t R_VDC_DisplayCalibration(const vdc_channel_t ch, const vdc_disp_calibration_t * const param);
+vdc_error_t R_VDC_GammaCorrection(
+    const vdc_channel_t                    ch,
+    const vdc_onoff_t                      gam_on,
+    const vdc_gamma_correction_t   * const param);
+
+void (*R_VDC_GetISR(const vdc_channel_t ch, const vdc_int_type_t type))(const uint32_t int_sense);
+
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_VDC_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/inc/r_vdc_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,113 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_user.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver user-defined header
+******************************************************************************/
+
+#ifndef R_VDC_USER_H
+#define R_VDC_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define VDC_INTERRUPT_PRIORITY  (5u)
+
+/*! Compilation switch to enable parameter check functions<br>
+    If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_VDC_CHECK_PARAMETERS
+
+
+/*! GBR to YCbCr conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - Y  =  0.299 * R + 0.587 * G + 0.114 * B
+ *  - Cb = -0.169 * R - 0.331 * G + 0.500 * B
+ *  - Cr =  0.500 * R - 0.419 * G - 0.081 * B
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum
+{
+    VDC_COLORCONV_Y_R  = (77u),
+    VDC_COLORCONV_Y_G  = (150u),
+    VDC_COLORCONV_Y_B  = (29u),
+    VDC_COLORCONV_CB_R = (2005u),
+    VDC_COLORCONV_CB_G = (1963u),
+    VDC_COLORCONV_CB_B = (128u),
+    VDC_COLORCONV_CR_R = (128u),
+    VDC_COLORCONV_CR_G = (1941u),
+    VDC_COLORCONV_CR_B = (2027u)
+} vdc_colcnv_rgb_ycbcr_t;
+
+/*! YCbCr to GBR conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - G = 1.0 * Y - 0.344 * Cb - 0.714 * Cr
+ *  - B = 1.0 * Y + 1.772 * Cb +   0.0 * Cr
+ *  - R = 1.0 * Y +   0.0 * Cb + 1.402 * Cr
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum
+{
+    VDC_COLORCONV_G_Y  = (256u),
+    VDC_COLORCONV_G_CB = (1960u),
+    VDC_COLORCONV_G_CR = (1865u),
+    VDC_COLORCONV_B_Y  = (256u),
+    VDC_COLORCONV_B_CB = (454u),
+    VDC_COLORCONV_B_CR = (0u),
+    VDC_COLORCONV_R_Y  = (256u),
+    VDC_COLORCONV_R_CB = (0u),
+    VDC_COLORCONV_R_CR = (359u)
+} vdc_colcnv_ycbcr_rgb_t;
+
+/*! Color matrix DC offset typical value */
+#define     VDC_COLORCONV_DC_OFFSET        (128u)
+/*! Color matrix coefficient value that represents one times */
+#define     VDC_COLORCONV_1TIMES_GAIN      (256u)
+
+/*! 1usec wait cycle for LVDS PLL */
+#define     VDC_LVDS_PLL_WAIT_CYCLE        (38u)
+/*! 200usec wait counter for LVDS PLL */
+#define     VDC_LVDS_PLL_WAIT_200USEC      (13400u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+uint32_t R_VDC_CPUVAddrToSysPAddr(uint32_t vaddr);
+void R_VDC_OnInitialize (const uint32_t user_num);
+void R_VDC_OnInitialize (const uint32_t user_num);
+
+#endif  /* R_VDC_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_spea.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,273 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_spe.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPE driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_spea.h"
+
+#include    "r_spea_user.h"
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+#include    "r_vdc_register.h"
+#include    "r_vdc_shared_param.h"
+#include    "r_vdc_check_parameter.h"
+
+#include    "r_spea_register.h"
+#include    "r_spea_check_parameter.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control, only layer 0).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   window_id               : SPEA window ID
+ *                                        - S0_WINDOW_00 - S0_WINDOW_15
+ *                                        - S1_WINDOW_00 - S0_WINDOW_15
+ * @param[in]   spea_onoff_t            :
+ * @param[in]   spea_window_conf_t      :
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t R_SPEA_SetWindow(
+    const vdc_layer_id_t       layer_id,
+    const spea_window_id_t     window_id,
+    const spea_onoff_t         sken,
+	const spea_sklym_t       * sklym,
+    const spea_skpsm_t       * skpsm,
+	const void               * buffer)
+
+{
+    spea_error_t    spea_error    = SPEA_OK;
+    spea_layer_id_t spea_layer_id = SPEA_LAYER_ID_0;
+
+#ifdef  R_SPEA_CHECK_PARAMETERS
+    spea_error = SPEA_SetWindowCheckPrm(layer_id, window_id, sken, sklym, skpsm, buffer );
+#endif  /* R_SPEA_CHECK_PARAMETERS */
+
+    if ( SPEA_OK == spea_error )
+    {
+    	if( VDC_LAYER_ID_2_RD == layer_id )
+    	{
+    		spea_layer_id = SPEA_LAYER_ID_0;
+    	}
+    	else
+    	{
+    		spea_layer_id = SPEA_LAYER_ID_1;
+    	}
+    	SPEA_SetWindow(spea_layer_id, window_id, sken, sklym, skpsm, buffer);
+    }
+    else
+    {
+    	spea_error = SPEA_ERR_PARAM;
+    }
+    return spea_error;
+}   /* End of function R_SPEA_SetWindow() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control, only layer 0).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   window_id               : SPEA window ID
+ *                                        - S0_WINDOW_00 - S0_WINDOW_15
+ *                                        - S1_WINDOW_00 - S0_WINDOW_15
+ * @param[in]   spea_onoff_t            :
+ * @param[in]   spea_window_conf_t      :
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t R_SPEA_WindowOffset(
+	    const vdc_layer_id_t       layer_id,
+        const uint16_t             offset_x,
+        const uint16_t             offset_y)
+{
+    spea_error_t    spea_error    = SPEA_OK;
+    spea_layer_id_t spea_layer_id = SPEA_LAYER_ID_0;
+
+#ifdef  R_SPEA_CHECK_PARAMETERS
+    spea_error = SPEA_WindowOffsetCheckPrm( layer_id, offset_x, offset_y );
+#endif  /* R_SPEA_CHECK_PARAMETERS */
+
+    if ( SPEA_OK == spea_error )
+    {
+    	if( VDC_LAYER_ID_2_RD == layer_id )
+    	{
+    		spea_layer_id = SPEA_LAYER_ID_0;
+    	}
+    	else
+    	{
+    		spea_layer_id = SPEA_LAYER_ID_1;
+    	}
+        SPEA_WindowOffset(spea_layer_id, offset_x, offset_y );
+    }
+    else
+    {
+    	spea_error = SPEA_ERR_PARAM;
+    }
+    return spea_error;
+}   /* End of function R_SPEA_WindowOffset() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control, only layer 0).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   window_id               : SPEA window ID
+ *                                        - S0_WINDOW_00 - S0_WINDOW_15
+ *                                        - S1_WINDOW_00 - S0_WINDOW_15
+ * @param[in]   spea_onoff_t            :
+ * @param[in]   spea_window_conf_t      :
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t R_SPEA_WindowUpdate(
+	const vdc_layer_id_t         layer_id)
+{
+    spea_error_t    spea_error    = SPEA_OK;
+    spea_layer_id_t spea_layer_id = SPEA_LAYER_ID_0;
+
+#ifdef  R_SPEA_CHECK_PARAMETERS
+    spea_error = SPEA_CreateSurfaceIDCheckPrm(layer_id);
+#endif  /* R_SPEA_CHECK_PARAMETERS */
+
+    if ( SPEA_OK == spea_error )
+    {
+    	if( VDC_LAYER_ID_2_RD == layer_id )
+    	{
+    		spea_layer_id = SPEA_LAYER_ID_0;
+    	}
+    	else
+    	{
+    		spea_layer_id = SPEA_LAYER_ID_1;
+    	}
+        SPEA_WindowUpdate(spea_layer_id);
+    }
+    else
+    {
+    	spea_error = SPEA_ERR_PARAM;
+    }
+    return spea_error;
+}   /* End of function R_SPEA_WindowUpdate() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control, only layer 0).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   window_id               : SPEA window ID
+ *                                        - S0_WINDOW_00 - S0_WINDOW_15
+ *                                        - S1_WINDOW_00 - S0_WINDOW_15
+ * @param[in]   spea_onoff_t            :
+ * @param[in]   spea_window_conf_t      :
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t R_RLE_SetWindow(
+	const vdc_error_t    layer_id,
+    const rle_onoff_t    sken,
+	const rle_cfg_t    * rle_cfg,
+	const void         * buffer)
+{
+    spea_error_t    spea_error    = SPEA_OK;
+
+#ifdef  R_SPEA_CHECK_PARAMETERS
+    spea_error = RLE_SetWindowCheckPrm(layer_id, rle_cfg, buffer);
+#endif  /* R_SPEA_CHECK_PARAMETERS */
+
+    if ( SPEA_OK == spea_error )
+    {
+    	RLE_SetWindow( sken, rle_cfg, buffer);
+    }
+    else
+    {
+    	spea_error = SPEA_ERR_PARAM;
+    }
+    return spea_error;
+}   /* End of function R_RLE_SetWindow() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control, only layer 0).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   window_id               : SPEA window ID
+ *                                        - S0_WINDOW_00 - S0_WINDOW_15
+ *                                        - S1_WINDOW_00 - S0_WINDOW_15
+ * @param[in]   spea_onoff_t            :
+ * @param[in]   spea_window_conf_t      :
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t R_RLE_WindowUpdate(
+    const vdc_layer_id_t   layer_id)
+{
+    spea_error_t    spea_error    = SPEA_OK;
+#ifdef  R_SPEA_CHECK_PARAMETERS
+    spea_error = RLE_CreateSurfaceIDCheckPrm(layer_id);
+#endif  /* R_SPEA_CHECK_PARAMETERS */
+
+    if ( SPEA_OK == spea_error )
+    {
+        RLE_WindowUpdate();
+    }
+    else
+    {
+    	spea_error = SPEA_ERR_PARAM;
+    }
+    return spea_error;
+}   /* End of function R_RLE_WindowUpdate() */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_spea_check_parameter.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,272 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_spea_check_parameter.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_spea.h"
+#include    "r_spea_user.h"
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+
+#include    "r_vdc_register.h"
+#include    "r_vdc_shared_param.h"
+#include    "r_vdc_check_parameter.h"
+#include    "r_spea_register.h"
+#include    "r_spea_check_parameter.h"
+
+#ifdef      R_SPEA_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       Checks on initialization parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Initialization parameter
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t SPEA_SetWindowCheckPrm (
+	    const vdc_layer_id_t       layer_id,
+	    const spea_window_id_t     window_id,
+	    const spea_onoff_t         sken,
+		const spea_sklym_t       * sklym,
+	    const spea_skpsm_t       * skpsm,
+		const void               * buffer)
+
+{
+    spea_error_t spea_error = SPEA_OK;
+
+    spea_error = SPEA_CreateSurfaceIDCheckPrm(layer_id);
+    if( SPEA_OK != spea_error)
+    {
+        goto END;
+    }
+
+    if( ( WINDOW_NUM <= window_id) || ( WINDOW_00 > window_id) )
+    {
+        spea_error = SPEA_ERR_PARAM;
+        goto END;
+    }
+
+    if( NULL != skpsm )
+    {
+    	int32_t x,y;
+        spea_skpsm_t offset;
+        SPEA_get_offset( layer_id, &offset );
+
+        x = skpsm->x + offset.x;
+        y = skpsm->y + offset.y;
+
+        if( x >= 2048 && 0 > x )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+
+        if( y >= 8192 && 0 > y )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+    }
+
+    if( NULL != sklym )
+    {
+    	int32_t width, height;
+        width  = sklym->width;
+
+        if( width >= 2048 && 0 > width )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+
+        height = sklym->height;
+        if( height >= 8192 && 0 > height )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+    }
+
+    if( NULL != buffer )
+    {
+    	uint32_t address;
+
+        address = (uint32_t)R_SPEA_CPUVAddrToSysPAddr((uint32_t)buffer);
+        if( (address & 0x00000007) != 0 )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+    }
+
+END:
+    return spea_error;
+}   /* End of function SPEA_SetWindowCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on initialization parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Initialization parameter
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t SPEA_WindowOffsetCheckPrm (
+    const vdc_layer_id_t       layer_id,
+    const uint16_t             offset_x,
+    const uint16_t             offset_y)
+{
+    spea_error_t spea_error = SPEA_OK;
+    volatile uint32_t temp_address;
+
+    spea_error = SPEA_CreateSurfaceIDCheckPrm(layer_id);
+    if( SPEA_OK != spea_error)
+    {
+        goto END;
+    }
+
+    if( (1u & offset_x) == 1 )
+    {
+        spea_error = SPEA_ERR_PARAM;
+        goto END;
+    }
+
+    if( (2048-1) < offset_x )
+    {
+        spea_error = SPEA_ERR_PARAM;
+        goto END;
+    }
+
+    if( (8192-1) < offset_y )
+    {
+        spea_error = SPEA_ERR_PARAM;
+        goto END;
+    }
+END:
+    return spea_error;
+}   /* End of function SPEA_WindowOffsetCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on WindowUpdate parameter
+ * @param[in]   layer_id    : SPEA_LAYER_ID_0 or SPEA_LAYER_ID_1
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t SPEA_CreateSurfaceIDCheckPrm (
+    const vdc_layer_id_t      layer_id)
+{
+    spea_error_t spea_error = SPEA_OK;
+
+    if( (VDC_LAYER_ID_2_RD != layer_id) && (VDC_LAYER_ID_3_RD != layer_id) )
+    {
+        spea_error = SPEA_ERR_PARAM_LAYER_ID;
+    }
+    return spea_error;
+}   /* End of function SPEA_CreateSurfaceIDCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on WindowUpdate parameter
+ * @param[in]   layer_id    : SPEA_LAYER_ID_0 or SPEA_LAYER_ID_1
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t RLE_CreateSurfaceIDCheckPrm (
+    const vdc_layer_id_t      layer_id)
+{
+    spea_error_t spea_error = SPEA_OK;
+
+    if( VDC_LAYER_ID_0_RD != layer_id )
+    {
+        spea_error = SPEA_ERR_PARAM_LAYER_ID;
+    }
+    return spea_error;
+}   /* End of function RLE_CreateSurfaceIDCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on WindowUpdate parameter
+ * @param[in]   layer_id    : SPEA_LAYER_ID_0 or SPEA_LAYER_ID_1
+ * @retval      Error code
+ *****************************************************************************/
+spea_error_t RLE_SetWindowCheckPrm(
+	    const vdc_layer_id_t  layer_id,
+		const rle_cfg_t     * rle_cfg,
+		const void          * buffer)
+{
+    spea_error_t spea_error = SPEA_OK;
+
+    spea_error = RLE_CreateSurfaceIDCheckPrm(layer_id);
+    if( SPEA_OK != spea_error)
+    {
+        goto END;
+    }
+    if( NULL != rle_cfg )
+    {
+    	int32_t rlen, rdth;
+    	rlen  = rle_cfg->rlen;
+
+        if( rlen > 7 && 0 > rlen )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+
+    	rdth  = rle_cfg->rdth;
+        if( rdth > 7 && 0 > 0 )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+    }
+
+    if( NULL != buffer )
+    {
+    	uint32_t address;
+
+        address = (uint32_t)R_SPEA_CPUVAddrToSysPAddr((uint32_t)buffer);
+        if( (address & 0x00000007) != 0 )
+        {
+        	spea_error = SPEA_ERR_PARAM;
+            goto END;
+        }
+    }
+
+END:
+	return spea_error;
+}   /* End of function RLE_SetWindowCheckPrm() */
+
+#endif      /* R_VDC_CHECK_PARAMETERS */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_spea_check_parameter.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,86 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_spea_check_parameter.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver parameter check definitions
+******************************************************************************/
+
+#ifndef R_SPEA_CHECK_PARAMETER_H
+#define R_SPEA_CHECK_PARAMETER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_spea.h"
+#include "r_vdc.h"
+
+#ifdef      R_SPEA_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/*--- SPEA function --------------------------------------*/
+
+spea_error_t SPEA_SetWindowCheckPrm (
+	const vdc_layer_id_t       layer_id,
+	const spea_window_id_t     window_id,
+	const spea_onoff_t         sken,
+	const spea_sklym_t       * sklym,
+	const spea_skpsm_t       * skpsm,
+	const void               * buffer);
+
+spea_error_t SPEA_WindowOffsetCheckPrm (
+    const vdc_layer_id_t       layer_id,
+    const uint16_t             offset_x,
+    const uint16_t             offset_y);
+
+spea_error_t SPEA_CreateSurfaceIDCheckPrm (
+    const vdc_layer_id_t      layer_id);
+
+/*--- RLE function --------------------------------------*/
+
+spea_error_t RLE_CreateSurfaceIDCheckPrm (
+    const vdc_layer_id_t      layer_id);
+
+spea_error_t RLE_SetWindowCheckPrm(
+	    const vdc_layer_id_t  layer_id,
+		const rle_cfg_t     * rle_cfg,
+		const void          * buffer);
+
+#endif      /* R_SPEA_CHECK_PARAMETERS */
+
+#endif  /* R_SPEA_CHECK_PARAMETER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_spea_register.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,291 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_spea_register.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_spea.h"
+#include    "r_spea_register.h"
+
+#include    "r_spea.h"
+#include    "r_spea_user.h"
+#include    "r_vdc.h"
+#include    "r_spea_check_parameter.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static int32_t g_offset_x[SPEA_UNIT_NUMBER_INDEX_MAX] = { 0, 0 };
+static int32_t g_offset_y[SPEA_UNIT_NUMBER_INDEX_MAX] = { 0, 0 };
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void SPEA_set_offset(
+    const spea_layer_id_t   layer_id,
+    const spea_skpsm_t    * offset )
+{
+    g_offset_x[layer_id] = offset->x;
+    g_offset_y[layer_id] = offset->y;
+}   /* End of function SPEA_set_offset() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void SPEA_get_offset(
+    const spea_layer_id_t   layer_id,
+          spea_skpsm_t    * offset )
+{
+    offset->x = g_offset_x[layer_id];
+    offset->y = g_offset_y[layer_id];
+}   /* End of function SPEA_get_offset() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void SPEA_SetWindow(
+    const spea_layer_id_t      layer_id,
+    const spea_window_id_t     window_id,
+    const spea_onoff_t         sken,
+	const spea_sklym_t       * sklym,
+    const spea_skpsm_t       * skpsm,
+	const void               * buffer)
+{
+    volatile uint32_t temp;
+
+    if( NULL != buffer )
+    {
+        /* SPEAnSkDAm
+         * **** **** **** **** **** **** **** **** : SPEAnSkDAm[31:0] : dst_address
+         */
+         *spea_regaddr_unit_ctr[layer_id][window_id].dst_address = R_SPEA_CPUVAddrToSysPAddr((uint32_t)buffer);
+    }
+
+    if( NULL != skpsm )
+    {
+        int32_t temp_x;
+        int32_t temp_y;
+        spea_skpsm_t offset;
+
+        SPEA_get_offset( layer_id, &offset );
+        temp_x = skpsm->x + offset.x;
+        temp_y = skpsm->y + offset.y;
+        temp = ( (temp_x << 16u )|(temp_y) );
+
+        /* SPEAnSkPSm
+         * ---- -*** **** **** ---- ---- ---- ---- : SPEAnSkPSXm[9:0]  : x
+         * ---- ---- ---- ---- ---* **** **** **** : SPEAnSkPSYm[12:0] : y
+         */
+        *spea_regaddr_unit_ctr[layer_id][window_id].position = temp;
+    }
+
+    if( NULL != sklym )
+    {
+        /* SPEAnSkLYm
+         * ---- -*** **** **** ---- ---- ---- ---- : SPEAnSkLYWm[9:0]  : width
+         * ---- ---- ---- ---- ---- -*** **** **** : SPEAnSkLYHm[10:0] : height
+         */
+        temp = ( (sklym->width << 16u )|(sklym->height) );
+        *spea_regaddr_unit_ctr[layer_id][window_id].width_hight = temp;
+    }
+
+    if( SPEA_ON == sken )
+    {
+        /* SPEAnSkEN */
+        *spea_regaddr_unit_enable_ctrl[layer_id].enable |= 0x00000001 << window_id;
+    }
+    else
+    {
+        /* SPEAnSkDS */
+        *spea_regaddr_unit_enable_ctrl[layer_id].disable &= ~(0x00000001 << window_id);
+    }
+
+}   /* End of function SPEA_SetWindow() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void SPEA_WindowUpdate(
+    const spea_layer_id_t      layer_id)
+{
+    /* SPEAnSkUP
+     * ---- ---- ---- ---- ---- ---- ---- ---* : SPEAnSkUP0 : 1
+     */
+    *spea_regaddr_unit_update_ctrl[layer_id].update = 0x00000001u;
+
+    /* GR_UPDATE
+     * ---- ---- ---- ---- ---- ---- ---* ---- : GR_P_VEN    : 1
+     * ---- ---- ---- ---- ---- ---- ---- ---* : GR_IBUS_VEN : 1
+     */
+    *spea_regaddr_img_synthesizer[layer_id].gr_update = 0x00000011;
+
+}   /* End of function SPEA_WindowUpdate() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void SPEA_WindowOffset(
+    const spea_layer_id_t      layer_id,
+    const uint16_t             offset_x,
+    const uint16_t             offset_y)
+{
+    volatile uint32_t temp_address;
+    spea_skpsm_t offset;
+
+    temp_address = (uint32_t)(VIRTUAL_FRAME_BASE_ADD + ((VIRTUAL_FRAME_STRAID * offset_y) + (offset_x *4) ));
+    /* GR_FLM2
+     * **** **** **** ****  **** **** **** **** : GR_BASE[31:0]
+     */
+    *spea_regaddr_img_synthesizer[layer_id].gr_flm2 = temp_address;
+
+    /* save off set */
+    offset.x = offset_x;
+    offset.y = offset_y;
+    SPEA_set_offset(layer_id, &offset);
+
+}   /* End of function SPEA_WindowOffset() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void RLE_SetWindow(
+    const rle_onoff_t    rbussel,
+	const rle_cfg_t    * rle_cfg,
+	const void         * buffer)
+{
+    volatile uint32_t temp;
+    volatile uint32_t temp_address;
+
+    if( NULL != buffer )
+    {
+    	temp_address = R_SPEA_CPUVAddrToSysPAddr((uint32_t)buffer);
+        /* SPEAnSTAi
+         * **** **** **** **** **** **** **** **** : SPEAnRSTA[31:0] : start_address
+         */
+    	*rle_regaddr.start_address = temp_address;
+
+    	/* SPEAnPHAi
+         * **** **** **** **** **** **** **** **** : SPEAnRPHA[31:0] : physical_address
+         */
+    	*rle_regaddr.physical_address = temp_address;
+
+    	/* GR_FLM2
+         * **** **** **** ****  **** **** **** **** : GR_BASE[31:0]
+         */
+        *rle_regaddr_img_synthesizer.gr_flm2 = temp_address;
+
+    	/* SPEAnRCMi
+         * ---- ---- ---- ---- ---- ---- ---- --** : SPEAnRCMi[1:0] : color
+         */
+
+//        *rle_regaddr_img_synthesizer.sc0_scl1_wr2 = temp_address;
+
+       	*rle_regaddr.color = 0x00000002;
+    }
+
+    if( NULL != rle_cfg )
+    {
+        /* SPEAnSkLYm
+         * ---- -*** **** **** ---- ---- ---- ---- : SPEAnSkLYWm[9:0]  : width
+         * ---- ---- ---- ---- ---- -*** **** **** : SPEAnSkLYHm[10:0] : height
+         */
+        temp = ( (rle_cfg->rlen << 4u )|(rle_cfg->rdth) );
+        *rle_regaddr.rlen_rdth = temp;
+    }
+
+    if( RLE_ON == rbussel )
+    {
+    	/* SPEAnRLSL
+         * ---- ---- ---- ---- ---- ---- ---- ---* : SPEAnRBUSSEL : enable
+         */
+        *rle_regaddr.enable |= 0x00000001;
+
+        /* GR_FLM1
+         * ---- ---- ---- ---- ---- ---- ---- ---* : GR0_BST_MD
+         */
+//        *rle_regaddr_img_synthesizer.gr_flm1 &= ~(0x00000301);
+        *rle_regaddr_img_synthesizer.gr_flm1 |= 0x00000001;
+    }
+    else
+    {
+    	/* SPEAnRLSL
+         * ---- ---- ---- ---- ---- ---- ---- ---* : SPEAnRBUSSEL : disable
+         */
+        *rle_regaddr.enable &= ~(0x00000001);
+
+        /* GR_FLM1
+         * ---- ---- ---- ---- ---- ---- ---- ---* : GR0_BST_MD
+         */
+        *rle_regaddr_img_synthesizer.gr_flm1 &= ~(0x00000001);
+//        *rle_regaddr_img_synthesizer.gr_flm1 |= 0x00000100;
+    }
+
+}   /* End of function RLE_SetWindow() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void RLE_WindowUpdate(void)
+{
+    /* SPEAnRUP
+     * ---- ---- ---- ---- ---- ---- ---- ---* : SPEAnRUP0 : 1
+     */
+    *rle_regaddr.update = 0x00000001u;
+
+    /* GR_UPDATE
+     * ---- ---- ---- ---- ---- ---- ---* ---- : GR_P_VEN    : 1
+     * ---- ---- ---- ---- ---- ---- ---- ---* : GR_IBUS_VEN : 1
+     */
+    *rle_regaddr_img_synthesizer.gr_update = 0x00000011;
+    *rle_regaddr_img_synthesizer.sc0_scl1_update = 0x00000010;
+
+}   /* End of function RLE_WindowUpdate() */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_spea_register.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,146 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_spea_register.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver register setup definitions
+******************************************************************************/
+
+#ifndef R_SPEA_REGISTER_H
+#define R_SPEA_REGISTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_spea.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define SPEA_UNIT_NUMBER_INDEX_MAX  (2u)
+#define SPEA_INDEX_MAX              (16u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! SPEA Unit enable controller register address list */
+typedef struct
+{
+    volatile uint32_t * enable;
+    volatile uint32_t * disable;
+} spea_regaddr_unit_enable_ctrl_t;
+
+/*! SPEA Unit update controller register address list */
+typedef struct
+{
+    volatile uint32_t * update;
+} spea_regaddr_unit_update_ctrl_t;
+
+/*! SPEA Unit controller register address list */
+typedef struct
+{
+    volatile uint32_t * dst_address;
+    volatile uint32_t * width_hight;
+    volatile uint32_t * position;
+} spea_regaddr_unit_ctrl_t;
+
+/*! VDC image synthesizer register address list for SPEA */
+typedef struct
+{
+    volatile uint32_t * gr_update;
+    volatile uint32_t * gr_flm2;
+} spea_regaddr_img_synthesizer_t;
+
+/*! RLE register address list for SPEA */
+typedef struct
+{
+    volatile uint32_t * enable;
+    volatile uint32_t * start_address;
+    volatile uint32_t * physical_address;
+    volatile uint32_t * color;
+    volatile uint32_t * update;
+    volatile uint32_t * rlen_rdth;
+} rle_regaddr_t;
+
+/*! VDC image synthesizer register address list for RLE */
+typedef struct
+{
+    volatile uint32_t * gr_update;
+    volatile uint32_t * gr_flm1;
+    volatile uint32_t * gr_flm2;
+    volatile uint32_t * sc0_scl1_update;
+    volatile uint32_t * sc0_scl1_wr2;
+} rle_regaddr_img_synthesizer_t;
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const spea_regaddr_unit_enable_ctrl_t spea_regaddr_unit_enable_ctrl[SPEA_UNIT_NUMBER_INDEX_MAX];
+extern const spea_regaddr_unit_update_ctrl_t spea_regaddr_unit_update_ctrl[SPEA_UNIT_NUMBER_INDEX_MAX];
+extern const spea_regaddr_unit_ctrl_t spea_regaddr_unit_ctr[SPEA_UNIT_NUMBER_INDEX_MAX][SPEA_INDEX_MAX];
+extern const spea_regaddr_img_synthesizer_t  spea_regaddr_img_synthesizer[SPEA_UNIT_NUMBER_INDEX_MAX];
+extern const rle_regaddr_t rle_regaddr;
+extern const rle_regaddr_img_synthesizer_t rle_regaddr_img_synthesizer;
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/*--- SPEA function --------------------------------------*/
+
+void SPEA_SetWindow(
+    const spea_layer_id_t      layer_id,
+    const spea_window_id_t     window_id,
+    const spea_onoff_t         sken,
+	const spea_sklym_t       * sklym,
+    const spea_skpsm_t       * skpsm,
+	const void               * buffer);
+
+void SPEA_WindowUpdate(
+    const spea_layer_id_t      layer_id);
+
+void SPEA_WindowOffset(
+    const spea_layer_id_t      layer_id,
+    const uint16_t             offset_x,
+    const uint16_t             offset_y);
+
+void SPEA_set_offset(
+    const spea_layer_id_t   layer_id,
+    const spea_skpsm_t    * offset );
+
+void SPEA_get_offset(
+    const spea_layer_id_t   layer_id,
+          spea_skpsm_t    * offset );
+
+/*--- RLE function --------------------------------------*/
+
+void RLE_SetWindow(
+    const rle_onoff_t    rbussel,
+	const rle_cfg_t    * rle_cfg,
+	const void         * buffer);
+
+void RLE_WindowUpdate(void);
+
+#endif  /* R_SPEA_REGISTER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_spea_register_address.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,278 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_apea_register_address.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+#include    "r_vdc_register.h"
+#include    "r_spea_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/*! SPEA Unit update controller register address list */
+const spea_regaddr_unit_enable_ctrl_t spea_regaddr_unit_enable_ctrl[SPEA_UNIT_NUMBER_INDEX_MAX] =
+{
+    {   /* index 0 */
+        (volatile uint32_t *)&SPRITE.SPEA0S0EN.LONG,  /* SPEAnSkEN: Sprite Unit k enable register  */
+        (volatile uint32_t *)&SPRITE.SPEA0S0DS.LONG,  /* SPEAnSkDS: Sprite Unit k disable register */
+    },
+
+    {   /* index 1 */
+        (volatile uint32_t *)&SPRITE.SPEA0S1EN.LONG,  /* SPEAnSkEN: Sprite Unit k enable register  */
+        (volatile uint32_t *)&SPRITE.SPEA0S1DS.LONG,  /* SPEAnSkDS: Sprite Unit k disable register */
+    },
+};
+
+/*! SPEA Unit update controller register address list */
+const spea_regaddr_unit_update_ctrl_t spea_regaddr_unit_update_ctrl[SPEA_UNIT_NUMBER_INDEX_MAX] =
+{
+    {   /* index 0 */
+        (volatile uint32_t *)&SPRITE.SPEA0S0UP.LONG,  /* SPEAnSkUP: Sprite Unit k update request register */
+    },
+    {   /* index 1 */
+        (volatile uint32_t *)&SPRITE.SPEA0S1UP.LONG,  /* SPEAnSkUP: Sprite Unit k update request register */
+    },
+};
+
+/*! SPEA Unit controller register address list */
+const spea_regaddr_unit_ctrl_t spea_regaddr_unit_ctr[SPEA_UNIT_NUMBER_INDEX_MAX][SPEA_INDEX_MAX] =
+{
+    { /* unit 0 */
+        {   /* index 0 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA0.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY0.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS0.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 1 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA1.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY1.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS1.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 2 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA2.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY2.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS2.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 3 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA3.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY3.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS3.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 4 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA4.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY4.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS4.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 5 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA5.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY5.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS5.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 6 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA6.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY6.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS6.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 7 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA7.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY7.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS7.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 8 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA8.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY8.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS8.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 9 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA9.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY9.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS9.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 10 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA10.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY10.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS10.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 11 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA11.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY11.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS11.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 12 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA12.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY12.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS12.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 13 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA13.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY13.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS13.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 14 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA14.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY14.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS14.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 15 */
+            (volatile uint32_t *)&SPRITE.SPEA0S0DA15.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S0LY15.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S0PS15.LONG   /* SPEAnSkPSm: position    */
+        },
+    },
+
+    {   /* uint 1 */
+        {   /* index 0 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA0.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY0.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS0.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 1 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA1.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY1.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS1.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 2 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA2.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY2.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS2.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 3 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA3.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY3.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS3.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 4 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA4.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY4.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS4.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 5 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA5.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY5.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS5.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 6 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA6.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY6.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS6.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 7 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA7.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY7.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS7.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 8 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA8.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY8.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS8.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 9 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA9.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY9.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS9.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 10 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA10.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY10.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS10.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 11 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA11.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY11.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS11.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 12 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA12.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY12.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS12.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 13 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA13.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY13.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS13.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 14 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA14.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY14.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS14.LONG   /* SPEAnSkPSm: position    */
+        },
+        {   /* index 15 */
+            (volatile uint32_t *)&SPRITE.SPEA0S1DA15.LONG,  /* SPEAnSkDAm: dst_address */
+            (volatile uint32_t *)&SPRITE.SPEA0S1LY15.LONG,  /* SPEAnSkLYm: width_hight */
+            (volatile uint32_t *)&SPRITE.SPEA0S1PS15.LONG   /* SPEAnSkPSm: position    */
+        }
+    }
+};
+
+/*! VDC image synthesizer register address list for SPEA */
+const spea_regaddr_img_synthesizer_t  spea_regaddr_img_synthesizer[SPEA_UNIT_NUMBER_INDEX_MAX] =
+{
+    {
+        (volatile uint32_t *)&VDC6.GR2_UPDATE.LONG,
+        (volatile uint32_t *)&VDC6.GR2_FLM2.LONG,
+    },
+    {
+        (volatile uint32_t *)&VDC6.GR3_UPDATE.LONG,
+        (volatile uint32_t *)&VDC6.GR3_FLM2.LONG,
+    }
+};
+
+/*! RLE register address list for SPEA */
+const rle_regaddr_t rle_regaddr =
+{
+    (volatile uint32_t *)&SPRITE.SPEA0RLSL.LONG,  /* SPEAnRLSL : enable           */
+    (volatile uint32_t *)&SPRITE.SPEA0STA0.LONG,  /* SPEAnSTAi : start_address    */
+    (volatile uint32_t *)&SPRITE.SPEA0PHA0.LONG,  /* SPEAnPHAi : physical_address */
+    (volatile uint32_t *)&SPRITE.SPEA0RCM0.LONG,  /* SPEAnRCMi : color            */
+    (volatile uint32_t *)&SPRITE.SPEA0RUP.LONG,   /* SPEAnRUP  : update           */
+    (volatile uint32_t *)&SPRITE.SPEA0RCFG.LONG,  /* SPEAnRCFG : rlen_rdth        */
+};
+
+/*! VDC image synthesizer register address list for RLE */
+const rle_regaddr_img_synthesizer_t rle_regaddr_img_synthesizer =
+{
+    (volatile uint32_t *)&VDC6.GR0_UPDATE.LONG,
+    (volatile uint32_t *)&VDC6.GR0_FLM1.LONG,
+    (volatile uint32_t *)&VDC6.GR0_FLM2.LONG,
+    (volatile uint32_t *)&VDC6.SC0_SCL1_UPDATE.LONG,
+	(volatile uint32_t *)&VDC6.SC0_SCL1_WR2.LONG,
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1234 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc.h"
+
+#include    "r_vdc_user.h"
+#include    "r_vdc_register.h"
+#include    "r_vdc_shared_param.h"
+#include    "r_vdc_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc_graphics_type_t ConvertRwProcId2GrId(const vdc_layer_id_t layer_id);
+
+
+/**************************************************************************//**
+ * @brief       VDC driver initialization
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Initializes the VDC driver's internal variables.
+ *              - Calls the user-defined function specified in init_func.
+ *              - Sets up and enables the VDC's panel clock.
+ *              - Sets up and enables the LVDS only if LVDS is used.
+ *              - Disables all the VDC interrupts.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   param                   : Initialization parameter
+ * @param[in]   init_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_Initialize (
+    const vdc_channel_t        ch,
+    const vdc_init_t   * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_InitializeCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmInit();
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_LVDS_CLK);
+        if (rsrc_state != VDC_RESOURCE_ST_INVALID)
+        {   /* The LVDS PLL clock has been already set. */
+            if (param->lvds != NULL)
+            {
+                ret = VDC_ERR_RESOURCE_LVDS_CLK;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetInitParam(param);
+
+        /* Callback function */
+        if (init_func != 0)
+        {
+            init_func(user_num);
+        }
+
+        VDC_Initialize(param);
+
+        /* Disable all VDC interrupts */
+        VDC_Int_Disable();
+
+        VDC_ShrdPrmSetResource(VDC_RESOURCE_PANEL_CLK, VDC_RESOURCE_ST_VALID);
+        if (param->lvds != NULL)
+        {
+            VDC_ShrdPrmSetResource(VDC_RESOURCE_LVDS_CLK, VDC_RESOURCE_ST_VALID);
+        }
+    }
+    return ret;
+}   /* End of function R_VDC_Initialize() */
+
+/**************************************************************************//**
+ * @brief       VDC driver termination
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Disables all the VDC interrupts.
+ *              - Disables the VDC panel clock.
+ *              - Disables the LVDS if one is used and becomes unnecessary as the result of calling this function.
+ *              - Calls the user-defined function specified in quit_func.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   quit_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_Terminate (const vdc_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    vdc_error_t    ret;
+    vdc_onoff_t    lvds_ref;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_TerminateCheckPrm(ch);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetTerminate();
+
+        /* Disable all VDC interrupts */
+        VDC_Int_Disable();
+
+        VDC_Terminate();
+
+        VDC_ShrdPrmSetResource(VDC_RESOURCE_PANEL_CLK, VDC_RESOURCE_ST_INVALID);
+
+        lvds_ref = VDC_ShrdPrmGetLvdsClkRef();
+        if (lvds_ref == VDC_OFF)       /* LVDS PLL clock is not referred. */
+        {
+            VDC_ShrdPrmSetResource(VDC_RESOURCE_LVDS_CLK, VDC_RESOURCE_ST_INVALID);
+        }
+
+        /* Callback function */
+        if (quit_func != 0)
+        {
+            quit_func(user_num);
+        }
+    }
+    return ret;
+}   /* End of function R_VDC_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Video input setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the phase timing of the input signals.
+ *              - Performs delay control on the sync signal for the video inputs.
+ *              - Sets up the parameters for the external input video signals.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_VideoInput (const vdc_channel_t ch, const vdc_input_t * const param)
+{
+    vdc_error_t ret;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_VideoInputCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetInputParam(param);
+
+        /* Setting VDC registers */
+        VDC_VideoInput(param);
+
+        VDC_ShrdPrmSetResource(VDC_RESOURCE_VIDEO_IN, VDC_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Synchronization control setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Selects the vertical sync signal.
+ *              - Sets up the period of the sync signal.
+ *              - Sets up the delay of the vertical sync signal.
+ *              - Sets up the full-screen enable signal.
+ *              - Sets up the compensation for the vertical sync signal.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   param                   : Synchronization control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_SyncControl (const vdc_channel_t ch, const vdc_sync_ctrl_t * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_SyncControlCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC_RESOURCE_ST_VALID)
+        {
+            ret = VDC_ERR_RESOURCE_CLK;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        if (param->res_vs_sel == VDC_OFF)
+        {   /* External input Vsync signal is selected. */
+            rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_VIDEO_IN);
+            if (rsrc_state != VDC_RESOURCE_ST_VALID)
+            {
+                ret = VDC_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_SyncControl(param);
+
+        VDC_ShrdPrmSetResource(VDC_RESOURCE_VSYNC, VDC_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Display output setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the timing signals for driving the LCD panel.
+ *              - Sets up the phase, data sequence, and format of the LCD panel output data.
+ *              - Sets up the background color.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_DisplayOutput (const vdc_channel_t ch, const vdc_output_t * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_DisplayOutputCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC_RESOURCE_ST_VALID)
+        {
+            ret = VDC_ERR_RESOURCE_CLK;
+        }
+        else
+        {
+            rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_VSYNC);
+            if (rsrc_state != VDC_RESOURCE_ST_VALID)
+            {
+                ret = VDC_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetOutputParam(param);
+
+        /* Setting VDC registers */
+        VDC_DisplayOutput(param);
+
+        VDC_ShrdPrmSetResource(VDC_RESOURCE_LCD_PANEL, VDC_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_CallbackISR (const vdc_channel_t ch, const vdc_int_t * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_CallbackISRCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC_RESOURCE_ST_VALID)
+        {
+            ret = VDC_ERR_RESOURCE_CLK;
+        }
+        else
+        {
+            rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_VSYNC);
+            if (rsrc_state != VDC_RESOURCE_ST_VALID)
+            {
+                ret = VDC_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_Int_SetInterrupt(param);
+    }
+    return ret;
+}   /* End of function R_VDC_CallbackISR() */
+
+/**************************************************************************//**
+ * @brief       Data write control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the input image area to be captured.
+ *              - Makes input image scale-down/rotation control settings.
+ *              - Makes frame buffer write control settings.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_0_WR
+ * @param[in]   param                   : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_WriteDataControl (
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_write_t  * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_WriteDataControlCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state != VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is already used. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_VIDEO_IN);
+            if (rsrc_state != VDC_RESOURCE_ST_VALID)
+            {
+                ret = VDC_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetWriteParam(param);
+
+        /* Setting VDC registers */
+        VDC_WriteDataControl(param);
+
+        VDC_ShrdPrmSetLayerResource(layer_id, VDC_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data write change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the input image area to be captured.
+ *              - Makes changes with respect to scaling-down/rotation control of the input image.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_0_WR
+ * @param[in]   param                   : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_ChangeWriteProcess (
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_write_chg_t   * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ChangeWriteProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetRwProcEnabled(layer_id);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetChgWriteParam(param);
+
+        /* Setting VDC registers */
+        VDC_ChangeWriteProcess(param);
+    }
+    return ret;
+}   /* End of function R_VDC_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Data read control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the display area for graphics images.
+ *              - Makes image scale-up control settings (only layer 0).
+ *              - Makes frame buffer read control settings.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_0_RD
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @param[in]   param                   : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_ReadDataControl (
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_read_t   * const param)
+{
+    vdc_error_t            ret;
+    vdc_graphics_type_t    graphics_id;
+    vdc_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ReadDataControlCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state != VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is already used. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetReadParam(graphics_id, param);
+
+        /* Setting VDC registers */
+        VDC_ReadDataControl(graphics_id, param);
+
+        VDC_ShrdPrmSetLayerResource(layer_id, VDC_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control, only layer 0).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_0_RD
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @param[in]   param                   : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_ChangeReadProcess (
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_read_chg_t   * const param)
+{
+    vdc_error_t            ret;
+    vdc_graphics_type_t    graphics_id;
+    vdc_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ChangeReadProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetRwProcEnabled(layer_id);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetChgReadParam(graphics_id, param);
+
+        /* Setting VDC registers */
+        VDC_ChangeReadProcess(graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read start processing
+ *
+ *              Description:<br>
+ *              This function performs layer start processing. If the layer ID specified in layer_id
+ *              is VDC_LAYER_ID_ALL, the function starts all the layers that are in the stopped state
+ *              and also enabled. If the layer ID is not VDC_LAYER_ID_ALL, the function starts only
+ *              the specified layer.<br>
+ *              When performing start processing for write, the function starts a write to the frame buffer.
+ *              When performing start processing for read, the function starts a read from the frame buffer
+ *              and sets the graphics display mode to the specified values for each layer.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_ALL
+ *                                        - VDC_LAYER_ID_0_WR
+ *                                        - VDC_LAYER_ID_0_RD
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_StartProcess (
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_start_t  * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_StartProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        if (layer_id != VDC_LAYER_ID_ALL)
+        {
+            rsrc_state = VDC_ShrdPrmGetRwProcReady(layer_id);
+            if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+            {   /* The specified layer is invalid. */
+                ret = VDC_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_StartProcess(layer_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read stop processing
+ *
+ *              Description:<br>
+ *              This function performs layer stop processing. If the layer ID specified in layer_id is
+ *              VDC_LAYER_ID_ALL, the function stops all the layers that are enabled and running.
+ *              If the layer ID is not VDC_LAYER_ID_ALL, the function stops only the specified layer.<br>
+ *              When performing stop processing for write, the function stops the write to the frame buffer.
+ *              When performing stop processing for read, the function stops the read from the frame buffer
+ *              and resets the graphics display mode to the initial values for each of the layers.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_ALL
+ *                                        - VDC_LAYER_ID_0_WR
+ *                                        - VDC_LAYER_ID_0_RD
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_StopProcess (const vdc_channel_t ch, const vdc_layer_id_t layer_id)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_StopProcessCheckPrm(ch, layer_id);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        if (layer_id != VDC_LAYER_ID_ALL)
+        {
+            rsrc_state = VDC_ShrdPrmGetRwProcEnabled(layer_id);
+            if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+            {   /* The specified layer is invalid. */
+                ret = VDC_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_StopProcess(layer_id);
+    }
+    return ret;
+}   /* End of function R_VDC_StopSurface() */
+
+/**************************************************************************//**
+ * @brief       Data write/read control release processing
+ *
+ *              Description:<br>
+ *              If the layer ID specified in layer_id is VDC_LAYER_ID_ALL, the function disables all the layers
+ *              that are not running and also enabled. If the layer ID is not VDC_LAYER_ID_ALL, the function
+ *              disables only the specified layers.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_ALL
+ *                                        - VDC_LAYER_ID_0_WR
+ *                                        - VDC_LAYER_ID_0_RD
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_ReleaseDataControl (const vdc_channel_t ch, const vdc_layer_id_t layer_id)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ReleaseDataControlCheckPrm(ch, layer_id);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        if (layer_id != VDC_LAYER_ID_ALL)
+        {
+            rsrc_state = VDC_ShrdPrmGetRwProcReady(layer_id);
+            if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+            {   /* The specified layer is invalid. */
+                ret = VDC_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        VDC_ShrdPrmSetLayerResource(layer_id, VDC_RESOURCE_ST_INVALID);
+    }
+    return ret;
+}   /* End of function R_VDC_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief       Noise reduction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off noise reduction processing.
+ *              - Sets up the noise reduction parameters for the Y/G, Cb/B, and Cr/R signals.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_VideoNoiseReduction (
+    const vdc_channel_t                    ch,
+    const vdc_onoff_t                      nr1d_on,
+    const vdc_noise_reduction_t    * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_VideoNoiseReductCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_VIDEO_IN);
+        if (rsrc_state != VDC_RESOURCE_ST_VALID)
+        {
+            ret = VDC_ERR_RESOURCE_INPUT;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_VideoNoiseReduction(nr1d_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Color matrix setup
+ *
+ *              Description:<br>
+ *              This function sets up the specified color matrix.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_ImageColorMatrix (const vdc_channel_t ch, const vdc_color_matrix_t * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ImageColorMatrixCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        if (param->module == VDC_COLORMTX_IMGCNT)
+        {
+            rsrc_state = VDC_ShrdPrmGetLayerResource(VDC_LAYER_ID_0_WR);
+        }
+        else    /* VDC_COLORMTX_ADJ_0 */
+        {
+            rsrc_state = VDC_ShrdPrmGetLayerResource(VDC_LAYER_ID_0_RD);
+        }
+
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_ImageColorMatrix(param);
+    }
+    return ret;
+}   /* End of function R_VDC_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Image enhancement processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off sharpness processing.
+ *              - Sets up the sharpness parameter.
+ *              - Turns on and off LTI processing.
+ *              - Sets up the LTI parameter.
+ *              - Sets up the enhancer-enabled area to be subjected to sharpness and LTI processing.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ *                                        - VDC_IMG_IMPRV_0
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_ImageEnhancement (
+    const vdc_channel_t                ch,
+    const vdc_imgimprv_id_t            imgimprv_id,
+    const vdc_onoff_t                  shp_h_on,
+    const vdc_enhance_sharp_t  * const sharp_param,
+    const vdc_onoff_t                  lti_h_on,
+    const vdc_enhance_lti_t    * const lti_param,
+    const vdc_period_rect_t    * const enh_area)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+    vdc_color_space_t      color_space;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ImageEnhancementCheckPrm(ch, imgimprv_id, sharp_param, enh_area);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(VDC_LAYER_ID_0_RD);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            /* Condition checks */
+            color_space = VDC_ShrdPrmGetColorSpaceFbRd(VDC_GR_TYPE_GR0);
+            if (color_space == VDC_COLOR_SPACE_GBR)
+            {   /* The image quality improver does not act on RGB signals. */
+                ret = VDC_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_ImageEnhancement(shp_h_on, sharp_param, lti_h_on, lti_param, enh_area);
+    }
+    return ret;
+}   /* End of function R_VDC_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Black stretch setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off black stretch processing.
+ *              - Sets up the black stretch parameters.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ *                                        - VDC_IMG_IMPRV_0
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_ImageBlackStretch (
+    const vdc_channel_t        ch,
+    const vdc_imgimprv_id_t    imgimprv_id,
+    const vdc_onoff_t          bkstr_on,
+    const vdc_black_t  * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+    vdc_color_space_t      color_space;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ImageBlackStretchCheckPrm(ch, imgimprv_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(VDC_LAYER_ID_0_RD);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            /* Condition checks */
+            color_space = VDC_ShrdPrmGetColorSpaceFbRd(VDC_GR_TYPE_GR0);
+            if (color_space == VDC_COLOR_SPACE_GBR)
+            {   /* The image quality improver does not act on RGB signals. */
+                ret = VDC_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_ImageBlackStretch(bkstr_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the alpha value of the ARGB1555/RGBA5551 formats.
+ *              - Make settings for premultiplication processing at alpha blending in one-pixel.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_AlphaBlending (
+    const vdc_channel_t                ch,
+    const vdc_layer_id_t               layer_id,
+    const vdc_alpha_blending_t * const param)
+{
+    vdc_error_t            ret;
+    vdc_graphics_type_t    graphics_id;
+    vdc_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_AlphaBlendingCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_AlphaBlending(graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Rectangle alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off alpha blending in a rectangular area.
+ *              - Sets up the rectangular area subjected to alpha blending.
+ *              - Sets up the alpha value for alpha blending in a rectangular area.
+ *              - Makes fade-in/-out settings to be applied to rectangle alpha blending.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_AlphaBlendingRect (
+    const vdc_channel_t                        ch,
+    const vdc_layer_id_t                       layer_id,
+    const vdc_onoff_t                          gr_arc_on,
+    const vdc_alpha_blending_rect_t    * const param)
+{
+    vdc_error_t            ret;
+    vdc_graphics_type_t    graphics_id;
+    vdc_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_AlphaBlendingRectCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_AlphaBlendingRect(graphics_id, gr_arc_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC_AlphaBlendingRect() */
+
+/**************************************************************************//**
+ * @brief       Chroma-key setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off the chroma-key processing.
+ *              - Sets up the color signals to be subject to chroma-key processing and
+ *                the color signals after replacement.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_0_RD
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_Chromakey (
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_onoff_t              gr_ck_on,
+    const vdc_chromakey_t  * const param)
+{
+    vdc_error_t            ret;
+    vdc_graphics_type_t    graphics_id;
+    vdc_color_space_t      color_space;
+    vdc_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_ChromakeyCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+        else
+        {
+            /* Condition checks */
+            color_space = VDC_ShrdPrmGetColorSpaceFbRd(graphics_id);
+            if (color_space == VDC_COLOR_SPACE_YCBCR)
+            {   /* Chroma-key processing cannot be used
+                   when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+                ret = VDC_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_Chromakey(graphics_id, gr_ck_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       CLUT setup
+ *
+ *              Description:<br>
+ *              This function sets up CLUT for the specified layer.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC_LAYER_ID_0_RD
+ *                                        - VDC_LAYER_ID_2_RD
+ *                                        - VDC_LAYER_ID_3_RD
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_CLUT (const vdc_channel_t ch, const vdc_layer_id_t layer_id, const vdc_clut_t * const param)
+{
+    vdc_error_t            ret;
+    vdc_graphics_type_t    graphics_id;
+    vdc_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_CLUTCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetLayerResource(layer_id);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The specified layer is invalid. */
+            ret = VDC_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_CLUT(graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC_SetCLUT() */
+
+/**************************************************************************//**
+ * @brief       Display calibration processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up panel brightness adjustment.
+ *              - Sets up contrast adjustment.
+ *              - Sets up panel dithering.
+ *              - Makes control settings for the correction circuit sequence.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_DisplayCalibration (const vdc_channel_t ch, const vdc_disp_calibration_t * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_DisplayCalibrationCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC_RESOURCE_ST_VALID)
+        {
+            ret = VDC_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_DisplayCalibration(param);
+    }
+    return ret;
+}   /* End of function R_VDC_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Gamma correction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off gamma correction processing.
+ *              - Sets up the gamma correction gain adjustment values for the G/B/R signals.
+ *              - Sets up the gamma correction start threshold values for the G/B/R signals.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   gam_on                  : Gamma correction ON/OFF setting
+ * @param[in]   param                   : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t R_VDC_GammaCorrection (
+    const vdc_channel_t                    ch,
+    const vdc_onoff_t                      gam_on,
+    const vdc_gamma_correction_t   * const param)
+{
+    vdc_error_t            ret;
+    vdc_resource_state_t   rsrc_state;
+
+    ret = VDC_OK;
+#ifdef  R_VDC_CHECK_PARAMETERS
+    ret = VDC_GammaCorrectionCheckPrm(ch, param);
+#endif  /* R_VDC_CHECK_PARAMETERS */
+    if (ret == VDC_OK)
+    {
+        /* Resource checks */
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC_RESOURCE_ST_VALID)
+        {
+            ret = VDC_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC_OK)
+    {
+        /* Setting VDC registers */
+        VDC_GammaCorrection(gam_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Convert read/write process ID into graphics type ID
+ *
+ * @param[in]   layer_id              : Layer ID
+ * @retval      Graphics type ID
+ *****************************************************************************/
+static vdc_graphics_type_t ConvertRwProcId2GrId (const vdc_layer_id_t layer_id)
+{
+    vdc_graphics_type_t graphics_id;
+
+    switch (layer_id)
+    {
+        case VDC_LAYER_ID_0_RD:                /* Layer 0, read process */
+            graphics_id = VDC_GR_TYPE_GR0;     /* Graphics 0 */
+        break;
+        case VDC_LAYER_ID_2_RD:                /* Layer 2, read process */
+            graphics_id = VDC_GR_TYPE_GR2;     /* Graphics 2 */
+        break;
+        case VDC_LAYER_ID_3_RD:                /* Layer 3, read process */
+            graphics_id = VDC_GR_TYPE_GR3;     /* Graphics 3 */
+        break;
+        default:                                /* Error */
+            graphics_id = VDC_GR_TYPE_NUM;
+        break;
+    }
+    return graphics_id;
+}   /* End of function ConvertRwProcId2GrId() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_check_parameter.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2152 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_check_parameter.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+#include    "r_vdc_shared_param.h"
+#include    "r_vdc_check_parameter.h"
+
+#ifdef      R_VDC_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDC_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDC_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDC_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDC_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDC_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDC_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDC_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDC_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDC_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDC_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDC_CPARA_RANGE_0X00007FFF (0x00007FFFu)
+#define VDC_CPARA_RANGE_0X0000FFFF (0x0000FFFFu)
+#define VDC_CPARA_RANGE_0X007FFFFF (0x007FFFFFu)
+#define VDC_CPARA_RANGE_0X00FFFFFF (0x00FFFFFFu)
+/* Valid range for signal delay amount */
+#define VDC_CPARA_INP_FLD_DLY_MAX (254u)
+#define VDC_CPARA_INP_VS_DLY_MAX  (254u)
+#define VDC_CPARA_INP_HS_DLY_MAX  (254u)
+/* Valid range for NFS */
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_56 (56u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_24 (24u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_28 (28u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_31 (31u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_37 (37u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_39 (39u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_46 (46u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_47 (47u)
+#define VDC_CPARA_LVDSPLL_FD_LIMIT_55 (55u)
+/* Valid range for HS + HW */
+#define VDC_CPARA_HS_HW_MAX       (2015u)
+/* Valid range for HS */
+#define VDC_CPARA_HS_MIN          (16u)
+/* Valid range for VS + VW */
+#define VDC_CPARA_VS_VW_MAX       (2039u)
+/* Valid range for VS */
+#define VDC_CPARA_VS_MIN          (4u)
+/* The max number of CLUT data values */
+#define VDC_CPARA_CLUT8_NUM       (256u)
+#define VDC_CPARA_CLUT4_NUM       (16u)
+#define VDC_CPARA_CLUT1_NUM       (2u)
+/* Valid range for the alpha coefficient */
+#define VDC_CPARA_GR_ARC_COEF_MIN (-255)
+#define VDC_CPARA_GR_ARC_COEF_MAX (255)
+/* Valid range for HS of enhancer area */
+#define VDC_CPARA_ENH_HS_LIMIT    (4u)
+/* Valid range for VS of enhancer area */
+#define VDC_CPARA_ENH_VS_LIMIT    (2u)
+
+#define VDC_BKSTR_T2_PROHIBITED    (31u)
+
+#define VDC_MULTIPLE_4_MASK        (0x00000003u)
+#define VDC_MULTIPLE_32_MASK       (0x0000001Fu)
+#define VDC_MULTIPLE_128_MASK      (0x0000007Fu)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc_error_t CheckChannel(const vdc_channel_t ch);
+static vdc_error_t CheckLayerId(const vdc_layer_id_t layer_id);
+static vdc_error_t CheckGraphicsTypeLayerId(const vdc_layer_id_t layer_id);
+static vdc_error_t CheckRect(const vdc_period_rect_t * const rect);
+static vdc_error_t CheckTcon_Vertical(const vdc_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc_error_t CheckTcon_Horizontal(const vdc_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc_error_t CheckTcon_HorizontalPol(const vdc_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc_error_t CheckTcon_DataEnable(const vdc_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc_error_t CheckGammaCrct_GainAdjustment(const uint16_t * gam_gain);
+
+
+/**************************************************************************//**
+ * @brief       Checks on initialization parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Initialization parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_InitializeCheckPrm (const vdc_channel_t ch, const vdc_init_t * const param)
+{
+    vdc_error_t error;
+    const vdc_lvds_t     * lvds_tmp;
+    vdc_resource_state_t   rsrc_state;
+    vdc_channel_t          lvds_vdc_sel_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Panel clock select */
+    if (param->panel_icksel >= VDC_PANEL_ICKSEL_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((param->panel_icksel != VDC_PANEL_ICKSEL_LVDS) && (param->panel_icksel != VDC_PANEL_ICKSEL_LVDS_DIV7))
+    {
+        /* Clock frequency division ratio */
+        if (param->panel_dcdr >= VDC_PANEL_CLKDIV_NUM)
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+    /* LVDS-related parameter */
+    lvds_tmp = param->lvds;
+    if (lvds_tmp == NULL)
+    {
+        rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_LVDS_CLK);
+        if (rsrc_state == VDC_RESOURCE_ST_INVALID)
+        {   /* The LVDS PLL clock has not been set yet. */
+            if ((param->panel_icksel == VDC_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC_PANEL_ICKSEL_LVDS_DIV7))
+            {
+                error = VDC_ERR_PARAM_NULL;
+                goto END;
+            }
+        }
+        else
+        {
+            if (param->panel_icksel == VDC_PANEL_ICKSEL_LVDS_DIV7)
+            {
+                lvds_vdc_sel_tmp = VDC_ShrdPrmGetLvdsCh();
+                if (ch != lvds_vdc_sel_tmp)
+                {   /* Channel mismatch error */
+                    error = VDC_ERR_PARAM_CONDITION;
+                    goto END;
+                }
+            }
+        }
+    }
+    else
+    {
+        /* The clock input to frequency divider 1 */
+        if (lvds_tmp->lvds_in_clk_sel >= VDC_LVDS_INCLK_SEL_NUM)
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* The frequency dividing value (NIDIV and NODIV) for frequency divider 1 and 2 */
+        if ((lvds_tmp->lvds_idiv_set >= VDC_LVDS_NDIV_NUM) || (lvds_tmp->lvds_odiv_set >= VDC_LVDS_NDIV_NUM))
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* Internal parameter setting for LVDS PLL */
+        if (((uint32_t)lvds_tmp->lvdspll_tst & (uint32_t)~VDC_CPARA_RANGE_0X0000003F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* A channel in VDC whose data is to be output through the LVDS */
+        if (lvds_tmp->lvds_vdc_sel >= VDC_CHANNEL_NUM)
+        {
+            error = VDC_ERR_PARAM_CHANNEL;
+            goto END;
+        }
+        if (param->panel_icksel != VDC_PANEL_ICKSEL_LVDS_DIV7)
+        {   /* When using the clock output from the LVDS PLL as the clock for the LVDS output interface,
+               both channel number should match. */
+            if (ch != lvds_tmp->lvds_vdc_sel)
+            {   /* Channel mismatch error */
+                error = VDC_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+        /* The frequency dividing value (NFD) for the feedback frequency */
+        if (((uint32_t)lvds_tmp->lvdspll_fd & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+#if 0 //@@@
+        if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_56)
+        {
+            if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_24)
+            {
+                error = VDC_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_28) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_31))
+            {
+                error = VDC_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_37) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_39))
+            {
+                error = VDC_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_46) ||
+                ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_47) ||
+                ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC_CPARA_LVDSPLL_FD_LIMIT_55))
+            {
+                error = VDC_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+#endif
+        /* The frequency dividing value (NRD) for the input frequency */
+        if (((uint32_t)lvds_tmp->lvdspll_rd & (uint32_t)~VDC_CPARA_RANGE_0X0000001F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* The frequency dividing value (NOD) for the output frequency */
+        if (lvds_tmp->lvdspll_od >= VDC_LVDS_PLL_NOD_NUM)
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_InitializeCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC_Terminate
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_TerminateCheckPrm (const vdc_channel_t ch)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_TerminateCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on video input setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_VideoInputCheckPrm (const vdc_channel_t ch, const vdc_input_t * const param)
+{
+    vdc_error_t                error;
+    const vdc_sync_delay_t   * dly_tmp;
+    const vdc_ext_in_sig_t   * ext_sig_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Vsync signal 1/2fH phase timing */
+    if (((uint32_t)param->inp_fh50 & (uint32_t)~VDC_CPARA_RANGE_0X000003FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal 1/4fH phase timing */
+    if (((uint32_t)param->inp_fh25 & (uint32_t)~VDC_CPARA_RANGE_0X000003FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL)
+    {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        if (((uint32_t)dly_tmp->inp_vs_dly_l & (uint32_t)~VDC_CPARA_RANGE_0X00000007) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Field differentiation signal delay amount */
+        if (((uint32_t)dly_tmp->inp_fld_dly & (uint32_t)~VDC_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_fld_dly > (uint32_t)VDC_CPARA_INP_FLD_DLY_MAX)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Vsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_vs_dly & (uint32_t)~VDC_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_vs_dly > (uint32_t)VDC_CPARA_INP_VS_DLY_MAX)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Hsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_hs_dly & (uint32_t)~VDC_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_hs_dly > (uint32_t)VDC_CPARA_INP_HS_DLY_MAX)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* External input format select */
+    if (ext_sig_tmp->inp_format >= VDC_EXTIN_FORMAT_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    if (ext_sig_tmp->inp_h_pos >= VDC_EXTIN_H_POS_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((ext_sig_tmp->inp_h_pos == VDC_EXTIN_H_POS_YCRYCB) || (ext_sig_tmp->inp_h_pos == VDC_EXTIN_H_POS_CRYCBY))
+    {
+        if (ext_sig_tmp->inp_format == VDC_EXTIN_FORMAT_YCBCR422)
+        {
+            error = VDC_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_VideoInputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sync control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Sync control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_SyncControlCheckPrm (const vdc_channel_t ch, const vdc_sync_ctrl_t * const param)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    if (param->res_vs_sel != VDC_OFF)
+    {
+        /* Free-running Vsync period setting */
+        if (((uint32_t)param->res_fv & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Hsync period setting */
+    if (((uint32_t)param->res_fh & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal delay control */
+    if (((uint32_t)param->res_vsdly & (uint32_t)~VDC_CPARA_RANGE_0X000000FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Full-screen enable control */
+    error = CheckRect(&param->res_f);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_SyncControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display output configuration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_DisplayOutputCheckPrm (const vdc_channel_t ch, const vdc_output_t * const param)
+{
+    vdc_error_t                    error;
+    uint32_t                        tcon_sig_index;
+    static vdc_error_t    (* const tcon_function_tbl[VDC_LCD_TCONSIG_NUM])(
+                                        const vdc_lcd_tcon_timing_t * const lcd_tcon_timing) =
+    {
+        &CheckTcon_Vertical,        /* STVA/VS */
+        &CheckTcon_Vertical,        /* STVB/VE */
+        &CheckTcon_Horizontal,      /* STH/HS */
+        &CheckTcon_Horizontal,      /* STB/HE */
+        &CheckTcon_Horizontal,      /* CPV/GCK */
+        &CheckTcon_HorizontalPol,   /* POLA */
+        &CheckTcon_HorizontalPol,   /* POLB */
+        &CheckTcon_DataEnable       /* DE */
+    };
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* 1/2fH timing */
+    if (((uint32_t)param->tcon_half & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Offset Hsync signal timing */
+    if (((uint32_t)param->tcon_offset & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* LCD TCON timing setting */
+    for (tcon_sig_index = 0; tcon_sig_index < VDC_LCD_TCONSIG_NUM; tcon_sig_index++)
+    {
+        if (param->outctrl[tcon_sig_index] != NULL)
+        {
+            error = tcon_function_tbl[tcon_sig_index](param->outctrl[tcon_sig_index]);
+            if (error != VDC_OK)
+            {
+                goto END;
+            }
+        }
+    }
+
+    /* LCD output format select */
+    if (param->out_format >= VDC_LCD_OUTFORMAT_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->out_format == VDC_LCD_OUTFORMAT_SERIAL_RGB)
+    {
+        /* Clock frequency control */
+        if (param->out_frq_sel >= VDC_LCD_SERIAL_CLKFRQ_NUM)
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC_LCD_PARALLEL_CLKFRQ_1)
+        {
+            error = VDC_ERR_PARAM_CONDITION;
+            goto END;
+        }
+        /* Clock phase adjustment */
+        if (param->out_phase >= VDC_LCD_SERIAL_CLKPHASE_NUM)
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC_LCD_SERIAL_CLKFRQ_3)
+        {
+            if (param->out_phase == VDC_LCD_SERIAL_CLKPHASE_3)
+            {
+                error = VDC_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+    /* Background color in 24-bit RGB color format */
+    if ((param->bg_color & (uint32_t)~VDC_CPARA_RANGE_0X00FFFFFF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_DisplayOutputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on interrupt callback setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_CallbackISRCheckPrm (const vdc_channel_t ch, const vdc_int_t * const param)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* VDC interrupt type */
+    if (param->type >= VDC_INT_TYPE_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Interrupt callback function pointer */
+    if (param->callback != 0)
+    {
+        if ((param->type == VDC_INT_TYPE_VLINE) || (param->type == VDC_INT_TYPE_S0_WLINE))
+        {
+            /* Line interrupt set */
+            if (((uint32_t)param->line_num & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_CallbackISRCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_WriteDataControlCheckPrm (
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_write_t  * const param)
+{
+    vdc_error_t                    error;
+    const vdc_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    if (layer_id != VDC_LAYER_ID_0_WR)
+    {
+        error = VDC_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode for image processing */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC_WR_MD_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Swap setting in frame buffer writing */
+    if (param->res_wrswa >= VDC_WR_RD_WRSWA_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer video-signal writing format */
+    if (param->res_md >= VDC_RES_MD_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Writing rate */
+    if (param->res_fs_rate >= VDC_RES_FS_RATE_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer base address */
+    if (param->base == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Frame buffer line offset address [byte] */
+    if ((param->ln_off & (uint32_t)~VDC_CPARA_RANGE_0X00007FFF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->res_bst_md == VDC_BST_MD_32BYTE)
+    {   /* 32-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC_MULTIPLE_32_MASK) != 0u)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else
+    {   /* 128-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC_MULTIPLE_128_MASK) != 0u)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    if ((param->flm_num & (uint32_t)~VDC_CPARA_RANGE_0X000003FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u)
+    {
+        if ((param->flm_off & (uint32_t)~VDC_CPARA_RANGE_0X007FFFFF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (param->res_bst_md == VDC_BST_MD_32BYTE)
+        {   /* 32-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC_MULTIPLE_32_MASK) != 0u)
+            {
+                error = VDC_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+        else
+        {   /* 128-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC_MULTIPLE_128_MASK) != 0u)
+            {
+                error = VDC_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_WriteDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ChangeWriteProcessCheckPrm (
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_write_chg_t  * const param)
+{
+    vdc_error_t                    error;
+    const vdc_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    if (layer_id != VDC_LAYER_ID_0_WR)
+    {
+        error = VDC_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC_MULTIPLE_4_MASK) != 0u)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC_WR_MD_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_ChangeWriteProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ReadDataControlCheckPrm (
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_graphics_type_t  graphics_id,
+    const vdc_read_t   * const param)
+{
+    vdc_error_t            error;
+    void                  * btm_base_tmp;
+    vdc_resource_state_t   rsrc_state;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Frame buffer address setting signal */
+    if (param->gr_flm_sel >= VDC_GR_FLM_SEL_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    btm_base_tmp    = NULL;
+    rsrc_state      = VDC_RESOURCE_ST_INVALID;
+    switch (graphics_id)
+    {
+        case VDC_GR_TYPE_GR0:
+            btm_base_tmp    = VDC_ShrdPrmGetFrBuffBtm();
+            rsrc_state      = VDC_ShrdPrmGetLayerResource(VDC_LAYER_ID_0_WR);
+        break;
+        /* The following two cases are intentionally combined. */
+        case VDC_GR_TYPE_GR2:
+        case VDC_GR_TYPE_GR3:
+            if (param->gr_flm_sel != VDC_GR_FLM_SEL_FLM_NUM)
+            {
+                error = VDC_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        break;
+        default:
+            /* DO NOTHING */
+        break;
+    }
+    if ((btm_base_tmp != NULL) && (rsrc_state != VDC_RESOURCE_ST_INVALID))
+    {   /* btm_base_tmp is valid only when rsrc_state is valid. */
+        if (param->gr_flm_sel == VDC_GR_FLM_SEL_SCALE_DOWN)
+        {
+            error = VDC_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Frame buffer base address */
+    if (param->gr_base == NULL)
+    {
+        if (param->gr_flm_sel != VDC_GR_FLM_SEL_POINTER_BUFF)
+        {
+            error = VDC_ERR_PARAM_NULL;
+            goto END;
+        }
+    }
+    /* Frame buffer line offset address */
+    if ((param->gr_ln_off & (uint32_t)~VDC_CPARA_RANGE_0X00007FFF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->gr_bst_md == VDC_BST_MD_32BYTE)
+    {   /* 32-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC_MULTIPLE_32_MASK) != 0u)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else
+    {   /* 128-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC_MULTIPLE_128_MASK) != 0u)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    if (param->width_read_fb != NULL)
+    {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC_CPARA_RANGE_0X00000003)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Format of the frame buffer read signal */
+    if (param->gr_format >= VDC_GR_FORMAT_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((param->gr_format == VDC_GR_FORMAT_YCBCR422) || (param->gr_format == VDC_GR_FORMAT_YCBCR444))
+    {   /* YCbCr422 and YCbCr444 are supported for the graphics 0 and 1. */
+        if (graphics_id != VDC_GR_TYPE_GR0)
+        {
+            error = VDC_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    if (param->gr_format == VDC_GR_FORMAT_YCBCR422)
+    {   /* Swapping of data read from buffer in the YCbCr422 format */
+        if (param->gr_ycc_swap >= VDC_GR_YCCSWAP_NUM)
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+    /* Swap setting in frame buffer reading */
+    if (param->gr_rdswa >= VDC_WR_RD_WRSWA_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Graphics display area */
+    error = CheckRect(&param->gr_grc);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_ReadDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ChangeReadProcessCheckPrm (
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_read_chg_t   * const param)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Width of the image read from frame buffer */
+    if (param->width_read_fb != NULL)
+    {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC_CPARA_RANGE_0X00000003)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Graphics display area */
+    if (param->gr_grc != NULL)
+    {
+        error = CheckRect(param->gr_grc);
+        if (error != VDC_OK)
+        {
+            goto END;
+        }
+    }
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL)
+    {
+        if ((*(param->gr_disp_sel) < VDC_DISPSEL_IGNORED) || (*(param->gr_disp_sel) >= VDC_DISPSEL_NUM))
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_ChangeReadProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write/read start parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_StartProcessCheckPrm (
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_start_t  * const param)
+{
+    vdc_error_t                error;
+    uint32_t                    graphics_types;
+    const vdc_gr_disp_sel_t  * gr_disp_sel_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    gr_disp_sel_tmp = param->gr_disp_sel;
+    if (gr_disp_sel_tmp == NULL)
+    {
+        error = VDC_OK;
+        goto END;
+    }
+    /* Graphics display mode */
+    if (layer_id == VDC_LAYER_ID_ALL)
+    {
+        for (graphics_types = 0; graphics_types < VDC_GR_TYPE_NUM; graphics_types++)
+        {
+            if ((gr_disp_sel_tmp[graphics_types] < VDC_DISPSEL_IGNORED) ||
+                (gr_disp_sel_tmp[graphics_types] >= VDC_DISPSEL_NUM))
+            {
+                error = VDC_ERR_PARAM_UNDEFINED;
+                goto END;
+            }
+        }
+    }
+    else
+    {
+        if ((*gr_disp_sel_tmp < VDC_DISPSEL_IGNORED) || (*gr_disp_sel_tmp >= VDC_DISPSEL_NUM))
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_StartProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC_StopProcess
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_StopProcessCheckPrm (const vdc_channel_t ch, const vdc_layer_id_t layer_id)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_StopProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC_ReleaseDataControl
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ReleaseDataControlCheckPrm (const vdc_channel_t ch, const vdc_layer_id_t layer_id)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_ReleaseDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on noise reduction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_VideoNoiseReductCheckPrm (const vdc_channel_t ch, const vdc_noise_reduction_t * const param)
+{
+    vdc_error_t            error;
+    const vdc_nr_param_t * nr_param;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_OK;
+        goto END;
+    }
+
+    /* Y/G signal noise reduction parameter */
+    nr_param = &param->y;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC_NR_TAPSEL_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC_CPARA_RANGE_0X0000007F) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC_NR_GAIN_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cb/B signal noise reduction parameter */
+    nr_param = &param->cb;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC_NR_TAPSEL_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC_CPARA_RANGE_0X0000007F) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC_NR_GAIN_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cr/R signal noise reduction parameter */
+    nr_param = &param->cr;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC_NR_TAPSEL_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC_CPARA_RANGE_0X0000007F) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC_NR_GAIN_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_VideoNoiseReductCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on color matrix setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ImageColorMatrixCheckPrm (const vdc_channel_t ch, const vdc_color_matrix_t * const param)
+{
+    vdc_error_t    error;
+    int32_t         colormtx_index;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Color matrix module */
+    if (param->module >= VDC_COLORMTX_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Operating mode */
+    if (param->mtx_mode >= VDC_COLORMTX_MODE_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->module != VDC_COLORMTX_IMGCNT)
+    {
+        if ((param->mtx_mode == VDC_COLORMTX_GBR_YCBCR) || (param->mtx_mode == VDC_COLORMTX_YCBCR_YCBCR))
+        {
+            error = VDC_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Offset (DC) adjustment of Y/G, B, and R signal */
+    for (colormtx_index = 0; colormtx_index < VDC_COLORMTX_OFFST_NUM; colormtx_index++)
+    {
+        if (((uint32_t)param->offset[colormtx_index] & (uint32_t)~VDC_CPARA_RANGE_0X000000FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    for (colormtx_index = 0; colormtx_index < VDC_COLORMTX_GAIN_NUM; colormtx_index++)
+    {
+        if (((uint32_t)param->gain[colormtx_index] & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_ImageColorMatrixCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sharpness setup parameter and enhancer-enabled area setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   sharp_param : Sharpness setup parameter
+ * @param[in]   enh_area    : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ImageEnhancementCheckPrm (
+    const vdc_channel_t                ch,
+    const vdc_imgimprv_id_t            imgimprv_id,
+    const vdc_enhance_sharp_t  * const sharp_param,
+    const vdc_period_rect_t    * const enh_area)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC_IMG_IMPRV_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Sharpness parameter */
+    if (sharp_param != NULL)
+    {
+        /* Sharpness control parameter (H1, H2, and H3) */
+        if (((uint32_t)sharp_param->hrz_sharp[VDC_IMGENH_SHARP_H1].shp_core & (uint32_t)~VDC_CPARA_RANGE_0X0000007F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC_IMGENH_SHARP_H2].shp_core & (uint32_t)~VDC_CPARA_RANGE_0X0000007F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC_IMGENH_SHARP_H3].shp_core & (uint32_t)~VDC_CPARA_RANGE_0X0000007F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Enhancer area */
+    if (enh_area != NULL)
+    {
+        /* Vertical start position */
+        if (((uint32_t)enh_area->vs & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->vs < (uint32_t)VDC_CPARA_ENH_VS_LIMIT)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Height (vertical width) */
+        if (((uint32_t)enh_area->vw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Horizontal start position */
+        if (((uint32_t)enh_area->hs & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->hs < (uint32_t)VDC_CPARA_ENH_HS_LIMIT)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Horizontal width */
+        if (((uint32_t)enh_area->hw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_ImageEnhancementCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on black stretch setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   param       : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ImageBlackStretchCheckPrm (
+    const vdc_channel_t        ch,
+    const vdc_imgimprv_id_t    imgimprv_id,
+    const vdc_black_t  * const param)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC_IMG_IMPRV_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        /* Black stretch start point */
+        if (((uint32_t)param->bkstr_st & (uint32_t)~VDC_CPARA_RANGE_0X0000000F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch depth */
+        if (((uint32_t)param->bkstr_d & (uint32_t)~VDC_CPARA_RANGE_0X0000000F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T1) */
+        if (((uint32_t)param->bkstr_t1 & (uint32_t)~VDC_CPARA_RANGE_0X0000001F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T2) */
+        if (((uint32_t)param->bkstr_t2 & (uint32_t)~VDC_CPARA_RANGE_0X0000001F) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->bkstr_t2 == VDC_BKSTR_T2_PROHIBITED)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+
+    }
+END:
+    return error;
+}   /* End of function VDC_ImageBlackStretchCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on alpha blending setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_AlphaBlendingCheckPrm (
+    const vdc_channel_t                ch,
+    const vdc_layer_id_t               layer_id,
+    const vdc_alpha_blending_t * const param)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    if ((layer_id != VDC_LAYER_ID_2_RD) && (layer_id != VDC_LAYER_ID_3_RD))
+    {
+        error = VDC_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_AlphaBlendingCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on setup parameter for alpha blending in a rectangular area
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_AlphaBlendingRectCheckPrm (
+    const vdc_channel_t                        ch,
+    const vdc_layer_id_t                       layer_id,
+    const vdc_alpha_blending_rect_t    * const param)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    if ((layer_id != VDC_LAYER_ID_2_RD) && (layer_id != VDC_LAYER_ID_3_RD))
+    {
+        error = VDC_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        /* Rectangular area subjected to alpha blending */
+        if (param->gr_arc != NULL)
+        {
+            /* Vertical start position */
+            if (((uint32_t)param->gr_arc->vs_rel & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Height (vertical width) */
+            if (((uint32_t)param->gr_arc->vw_rel & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal start position */
+            if (((uint32_t)param->gr_arc->hs_rel & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal width */
+            if (((uint32_t)param->gr_arc->hw_rel & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+        /* Alpha Blending in a rectangular area */
+        if (param->alpha_rect != NULL)
+        {
+            /* Frame rate for alpha blending in a rectangular area */
+            if ((param->alpha_rect->gr_arc_coef < (int16_t)VDC_CPARA_GR_ARC_COEF_MIN) ||
+                (param->alpha_rect->gr_arc_coef > (int16_t)VDC_CPARA_GR_ARC_COEF_MAX))
+            {
+                error = VDC_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_AlphaBlendingRectCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma-key setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_ChromakeyCheckPrm (
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_graphics_type_t      graphics_id,
+    const vdc_chromakey_t  * const param)
+{
+    vdc_error_t        error;
+    vdc_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        gr_format_tmp = VDC_ShrdPrmGetGraphicsFormat(graphics_id);
+        switch (gr_format_tmp)
+        {
+            /* The following four cases are intentionally combined,
+              since the four types of graphics format are represented as 16 bit unsigned integer. */
+            case VDC_GR_FORMAT_RGB565:
+            case VDC_GR_FORMAT_ARGB1555:
+            case VDC_GR_FORMAT_ARGB4444:
+            case VDC_GR_FORMAT_RGBA5551:
+                if (((param->ck_color & (uint32_t)~VDC_CPARA_RANGE_0X0000FFFF) != 0u) ||
+                    ((param->rep_color & (uint32_t)~VDC_CPARA_RANGE_0X0000FFFF) != 0u))
+                {
+                    error = VDC_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC_GR_FORMAT_RGB888:
+                if (((param->ck_color & (uint32_t)~VDC_CPARA_RANGE_0X00FFFFFF) != 0u) ||
+                    ((param->rep_color & (uint32_t)~VDC_CPARA_RANGE_0X00FFFFFF) != 0u))
+                {
+                    error = VDC_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC_GR_FORMAT_CLUT8:
+                if ((param->ck_color & (uint32_t)~VDC_CPARA_RANGE_0X000000FF) != 0u)
+                {
+                    error = VDC_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC_GR_FORMAT_CLUT4:
+                if ((param->ck_color & (uint32_t)~VDC_CPARA_RANGE_0X0000000F) != 0u)
+                {
+                    error = VDC_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            case VDC_GR_FORMAT_CLUT1:
+                if ((param->ck_color & (uint32_t)~VDC_CPARA_RANGE_0X00000001) != 0u)
+                {
+                    error = VDC_ERR_PARAM_BIT_WIDTH;
+                }
+            break;
+            default:
+                /* DO NOTHING */
+            break;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_ChromakeyCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on CLUT setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_CLUTCheckPrm (
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_graphics_type_t  graphics_id,
+    const vdc_clut_t   * const param)
+{
+    vdc_error_t        error;
+    vdc_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* The number of colors in CLUT */
+    if (param->color_num == 0u)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    gr_format_tmp = VDC_ShrdPrmGetGraphicsFormat(graphics_id);
+    if (gr_format_tmp == VDC_GR_FORMAT_CLUT1)
+    {   /* CLUT1 */
+        if (param->color_num > (uint32_t)VDC_CPARA_CLUT1_NUM)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else if (gr_format_tmp == VDC_GR_FORMAT_CLUT4)
+    {   /* CLUT4 */
+        if (param->color_num > (uint32_t)VDC_CPARA_CLUT4_NUM)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    else
+    {   /* CLUT8 */
+        if (param->color_num > (uint32_t)VDC_CPARA_CLUT8_NUM)
+        {
+            error = VDC_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* Address of the area storing the CLUT data (in ARGB8888 format) */
+    if (param->clut == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC_CLUTCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display calibration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_DisplayCalibrationCheckPrm (const vdc_channel_t ch, const vdc_disp_calibration_t * const param)
+{
+    vdc_error_t                    error;
+    const vdc_calibr_bright_t    * bright_tmp;
+    const vdc_calibr_dither_t    * panel_dither_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param == NULL)
+    {
+        error = VDC_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL)
+    {
+        /* Brightness (DC) adjustment of G signal */
+        if (((uint32_t)bright_tmp->pbrt_g & (uint32_t)~VDC_CPARA_RANGE_0X000003FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of B signal */
+        if (((uint32_t)bright_tmp->pbrt_b & (uint32_t)~VDC_CPARA_RANGE_0X000003FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of R signal */
+        if (((uint32_t)bright_tmp->pbrt_r & (uint32_t)~VDC_CPARA_RANGE_0X000003FF) != 0u)
+        {
+            error = VDC_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL)
+    {
+        /* Panel dither operation mode */
+        if (panel_dither_tmp->pdth_sel >= VDC_PDTH_MD_NUM)
+        {
+            error = VDC_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (panel_dither_tmp->pdth_sel == VDC_PDTH_MD_2X2)
+        {   /* Pattern value (A)-(D) of 2x2 pattern dither */
+            if (((uint32_t)panel_dither_tmp->pdth_pa & (uint32_t)~VDC_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pb & (uint32_t)~VDC_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pc & (uint32_t)~VDC_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pd & (uint32_t)~VDC_CPARA_RANGE_0X00000003) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_DisplayCalibrationCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on gamma correction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc_error_t VDC_GammaCorrectionCheckPrm (const vdc_channel_t ch, const vdc_gamma_correction_t * const param)
+{
+    vdc_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC_OK)
+    {
+        goto END;
+    }
+
+    if (param != NULL)
+    {
+        /* Gain adjustment of area 0 to 31 of G signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_g_gain);
+        if (error != VDC_OK)
+        {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of B signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_b_gain);
+        if (error != VDC_OK)
+        {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of R signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_r_gain);
+        if (error != VDC_OK)
+        {
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC_GammaCorrectionCheckPrm() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Checks on VDC channel
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckChannel (const vdc_channel_t ch)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    if (ch >= VDC_CHANNEL_NUM)
+    {
+        error = VDC_ERR_PARAM_CHANNEL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckChannel() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckLayerId (const vdc_layer_id_t layer_id)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    if ((layer_id < VDC_LAYER_ID_ALL) || (layer_id >= VDC_LAYER_ID_NUM))
+    {
+        error = VDC_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID related to graphics
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckGraphicsTypeLayerId (const vdc_layer_id_t layer_id)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    if ((layer_id != VDC_LAYER_ID_0_RD) && (layer_id != VDC_LAYER_ID_2_RD) && (layer_id != VDC_LAYER_ID_3_RD))
+    {
+        error = VDC_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckGraphicsTypeLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on horizontal/vertical timing of the VDC signals
+ * @param[in]   rect            : Horizontal/vertical timing of the VDC signals
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckRect (const vdc_period_rect_t * const rect)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    /* Vertical start position */
+    if (((uint32_t)rect->vs & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->vs < (uint32_t)VDC_CPARA_VS_MIN)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Height (vertical width) */
+    if (((uint32_t)rect->vw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->vs + (uint32_t)rect->vw) > (uint32_t)VDC_CPARA_VS_VW_MAX)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+
+    /* Horizontal start position */
+    if (((uint32_t)rect->hs & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->hs < (uint32_t)VDC_CPARA_HS_MIN)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Horizontal width */
+    if (((uint32_t)rect->hw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->hs + (uint32_t)rect->hw) > (uint32_t)VDC_CPARA_HS_HW_MAX)
+    {
+        error = VDC_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckRect() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckTcon_Horizontal (const vdc_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC_LCD_TCON_PIN_NUM))
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Horizontal() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal (POLA/POLB)
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckTcon_HorizontalPol (const vdc_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* POLA/POLB signal generation mode select */
+    if (lcd_tcon_timing->tcon_md >= VDC_LCD_TCON_POLMD_NUM)
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC_LCD_TCON_PIN_NUM))
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_HorizontalPol() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for vertical panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckTcon_Vertical (const vdc_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+    {
+        error = VDC_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC_LCD_TCON_PIN_NUM))
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Vertical() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for DE timing signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckTcon_DataEnable (const vdc_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc_error_t error;
+
+    error = VDC_OK;
+
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC_LCD_TCON_PIN_NUM))
+    {
+        error = VDC_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_DataEnable() */
+
+/**************************************************************************//**
+ * @brief       Checks on gain adjustment of area 0 to 31 of G/B/R signal
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31 of G/B/R signal
+ * @retval      Error code
+******************************************************************************/
+static vdc_error_t CheckGammaCrct_GainAdjustment (const uint16_t * gam_gain)
+{
+    uint32_t        gain_index;
+    vdc_error_t    error;
+
+    error = VDC_OK;
+
+    if (gam_gain != NULL)
+    {
+        for (gain_index = 0; gain_index < VDC_GAM_GAIN_ADJ_NUM; gain_index++)
+        {
+            if (((uint32_t)*gam_gain & (uint32_t)~VDC_CPARA_RANGE_0X000007FF) != 0u)
+            {
+                error = VDC_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            gam_gain++;
+        }
+    }
+END:
+    return error;
+}   /* End of function CheckGammaCrct_GainAdjustment() */
+
+#endif      /* R_VDC_CHECK_PARAMETERS */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_check_parameter.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,122 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_check_parameter.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver parameter check definitions
+******************************************************************************/
+
+#ifndef R_VDC_CHECK_PARAMETER_H
+#define R_VDC_CHECK_PARAMETER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc.h"
+#include "r_vdc_user.h"
+
+
+#ifdef      R_VDC_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdc_error_t VDC_InitializeCheckPrm(const vdc_channel_t ch, const vdc_init_t * const param);
+vdc_error_t VDC_TerminateCheckPrm(const vdc_channel_t ch);
+vdc_error_t VDC_VideoInputCheckPrm(const vdc_channel_t ch, const vdc_input_t * const param);
+vdc_error_t VDC_SyncControlCheckPrm(const vdc_channel_t ch, const vdc_sync_ctrl_t * const param);
+vdc_error_t VDC_DisplayOutputCheckPrm(const vdc_channel_t ch, const vdc_output_t * const param);
+vdc_error_t VDC_CallbackISRCheckPrm(const vdc_channel_t ch, const vdc_int_t * const param);
+vdc_error_t VDC_WriteDataControlCheckPrm(
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_write_t  * const param);
+vdc_error_t VDC_ChangeWriteProcessCheckPrm(
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_write_chg_t  * const param);
+vdc_error_t VDC_ReadDataControlCheckPrm(
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_graphics_type_t  graphics_id,
+    const vdc_read_t   * const param);
+vdc_error_t VDC_ChangeReadProcessCheckPrm(
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_read_chg_t   * const param);
+vdc_error_t VDC_StartProcessCheckPrm(
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_start_t  * const param);
+vdc_error_t VDC_StopProcessCheckPrm(const vdc_channel_t ch, const vdc_layer_id_t layer_id);
+vdc_error_t VDC_ReleaseDataControlCheckPrm(const vdc_channel_t ch, const vdc_layer_id_t layer_id);
+vdc_error_t VDC_VideoNoiseReductCheckPrm(const vdc_channel_t ch, const vdc_noise_reduction_t * const param);
+vdc_error_t VDC_ImageColorMatrixCheckPrm(const vdc_channel_t ch, const vdc_color_matrix_t * const param);
+vdc_error_t VDC_ImageEnhancementCheckPrm(
+    const vdc_channel_t                ch,
+    const vdc_imgimprv_id_t            imgimprv_id,
+    const vdc_enhance_sharp_t  * const sharp_param,
+    const vdc_period_rect_t    * const enh_area);
+vdc_error_t VDC_ImageBlackStretchCheckPrm(
+    const vdc_channel_t        ch,
+    const vdc_imgimprv_id_t    imgimprv_id,
+    const vdc_black_t  * const param);
+vdc_error_t VDC_AlphaBlendingCheckPrm(
+    const vdc_channel_t                ch,
+    const vdc_layer_id_t               layer_id,
+    const vdc_alpha_blending_t * const param);
+vdc_error_t VDC_AlphaBlendingRectCheckPrm(
+    const vdc_channel_t                        ch,
+    const vdc_layer_id_t                       layer_id,
+    const vdc_alpha_blending_rect_t    * const param);
+vdc_error_t VDC_ChromakeyCheckPrm(
+    const vdc_channel_t            ch,
+    const vdc_layer_id_t           layer_id,
+    const vdc_graphics_type_t      graphics_id,
+    const vdc_chromakey_t  * const param);
+vdc_error_t VDC_CLUTCheckPrm(
+    const vdc_channel_t        ch,
+    const vdc_layer_id_t       layer_id,
+    const vdc_graphics_type_t  graphics_id,
+    const vdc_clut_t   * const param);
+vdc_error_t VDC_DisplayCalibrationCheckPrm(const vdc_channel_t ch, const vdc_disp_calibration_t * const param);
+vdc_error_t VDC_GammaCorrectionCheckPrm(const vdc_channel_t ch, const vdc_gamma_correction_t * const param);
+
+
+#endif      /* R_VDC_CHECK_PARAMETERS */
+
+#endif  /* R_VDC_CHECK_PARAMETER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_interrupt.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,536 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_interrupt.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver interrupt related processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+#include    "r_vdc_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     UNUSED_PARAM(param)             (void)(param)
+
+#define VDC_INT_BIT_S0_VI_VSYNC    ((uint32_t)0x00000001u)
+#define VDC_INT_BIT_S0_LO_VSYNC    ((uint32_t)0x00000010u)
+#define VDC_INT_BIT_S0_VSYNCERR    ((uint32_t)0x00000100u)
+#define VDC_INT_BIT_VLINE          ((uint32_t)0x00001000u)
+#define VDC_INT_BIT_S0_VFIELD      ((uint32_t)0x00010000u)
+#define VDC_INT_BIT_IV1_VBUFERR    ((uint32_t)0x00100000u)
+#define VDC_INT_BIT_IV3_VBUFERR    ((uint32_t)0x01000000u)
+#define VDC_INT_BIT_IV5_VBUFERR    ((uint32_t)0x10000000u)
+#define VDC_INT_BIT_IV6_VBUFERR    ((uint32_t)0x00000001u)
+#define VDC_INT_BIT_S0_WLINE       ((uint32_t)0x00000010u)
+
+#define VDC_GR_UPDATE_P_VEN_BIT    ((uint32_t)0x00000010u)
+#define VDC_SCL0_UPDATE_VEN_A_BIT  ((uint32_t)0x00000001u)
+
+/* Valid bit range */
+#define VDC_INT_RANGE_0X000007FF   (0x000007FFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void VDC_Ch0_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC_Ch0_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC_Ch0_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC_Ch0_vline_ISR(const uint32_t int_sense);
+static void VDC_Ch0_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC_Ch0_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC_Ch0_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC_Ch0_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC_Ch0_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC_Ch0_s0_wline_ISR(const uint32_t int_sense);
+
+/*! List of the callback function pointers */
+static void (*vdc_int_callback[VDC_INT_TYPE_NUM])(vdc_int_type_t int_type);
+
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ *              It returns a '0' if the channel specified in ch or the interrupt type specified in type
+ *              is found invalid.
+ * @param[in]   ch                      : Channel
+ *                                        - VDC_CHANNEL_0
+ * @param[in]   type                    : VDC interrupt type
+ * @retval      VDC Interrupt service routine
+ *****************************************************************************/
+void (*R_VDC_GetISR (const vdc_channel_t ch, const vdc_int_type_t type))(const uint32_t int_sense)
+{
+    static void (* const isr_table[VDC_INT_TYPE_NUM])(const uint32_t int_sense) =
+    {
+        &VDC_Ch0_s0_vi_vsync_ISR,
+        &VDC_Ch0_s0_lo_vsync_ISR,
+        &VDC_Ch0_s0_vsyncerr_ISR,
+        &VDC_Ch0_vline_ISR,
+        &VDC_Ch0_s0_vfield_ISR,
+        &VDC_Ch0_iv1_vbuferr_ISR,
+        &VDC_Ch0_iv3_vbuferr_ISR,
+        &VDC_Ch0_iv5_vbuferr_ISR,
+        &VDC_Ch0_iv6_vbuferr_ISR,
+        &VDC_Ch0_s0_wline_ISR
+    };
+    void (* isr_function)(const uint32_t int_sense);
+
+    isr_function = isr_table[type];
+
+#ifdef  R_VDC_CHECK_PARAMETERS
+    /* Channel and interrupt type */
+    if ((ch >= VDC_CHANNEL_NUM) || (type >= VDC_INT_TYPE_NUM))
+    {
+        isr_function = 0;
+    }
+#endif  /* R_VDC_CHECK_PARAMETERS */
+
+     return isr_function;
+}   /* End of function R_VDC_GetISR() */
+
+/**************************************************************************//**
+ * @brief       Disables all VDC interrupts
+ * @param[in]   void
+ * @retval      None
+ *****************************************************************************/
+void VDC_Int_Disable (void)
+{
+    const vdc_regaddr_system_ctrl_t  * system_ctrl;
+    int32_t                             int_type;
+
+    system_ctrl = &vdc_regaddr_system_ctrl;
+
+    for (int_type = 0; int_type < VDC_INT_TYPE_NUM; int_type++)
+    {
+        vdc_int_callback[int_type] = 0;
+    }
+    /* Interrupt output off */
+    *(system_ctrl->syscnt_int4) = 0u;
+    *(system_ctrl->syscnt_int5) = 0u;
+
+}   /* End of function VDC_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief       Enables/disables the specified VDC interrupt
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_Int_SetInterrupt (const vdc_int_t * const param)
+{
+    volatile uint32_t     * int_clhd_reg;
+    volatile uint32_t     * int_onoff_reg;
+    volatile uint32_t     * linenum_reg;
+    volatile uint16_t     * linenum16_reg;
+    volatile uint32_t     * linenum_update_reg;
+    uint32_t                mask_bit;
+    uint32_t                reg_data;
+    static const uint32_t   interrupt_bit_table[VDC_INT_TYPE_NUM] =
+    {
+        VDC_INT_BIT_S0_VI_VSYNC,
+        VDC_INT_BIT_S0_LO_VSYNC,
+        VDC_INT_BIT_S0_VSYNCERR,
+        VDC_INT_BIT_VLINE,
+        VDC_INT_BIT_S0_VFIELD,
+        VDC_INT_BIT_IV1_VBUFERR,
+        VDC_INT_BIT_IV3_VBUFERR,
+        VDC_INT_BIT_IV5_VBUFERR,
+        VDC_INT_BIT_IV6_VBUFERR,
+        VDC_INT_BIT_S0_WLINE
+    };
+
+    if (param->type < VDC_INT_TYPE_IV6_VBUFERR)
+    {   /* INT0: VDC_INT_TYPE_S0_VI_VSYNC ~ INT7: VDC_INT_TYPE_IV5_VBUFERR */
+        int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+        int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    }
+    else
+    {   /* INT8: VDC_INT_TYPE_IV6_VBUFERR ~ INT9: VDC_INT_TYPE_S0_WLINE */
+        int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int2;
+        int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int5;
+    }
+    mask_bit = interrupt_bit_table[param->type];
+
+    /* Interrupt callback function pointer */
+    vdc_int_callback[param->type] = param->callback;
+
+    if (param->callback != 0)
+    {   /* ON */
+        if ((*int_onoff_reg & mask_bit) == 0u)
+        {   /* OFF to ON */
+            *int_onoff_reg |= mask_bit;
+            reg_data        = *int_onoff_reg;
+            *int_clhd_reg   = reg_data;
+        }
+
+        if (param->type == VDC_INT_TYPE_VLINE)
+        {   /* Specified line signal for panel output in graphics 3 */
+            linenum_reg         = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR3].gr_clut;
+            linenum_update_reg  = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR3].gr_update;
+            *linenum_reg        &= (uint32_t)~VDC_INT_RANGE_0X000007FF;
+            *linenum_reg        |= (uint32_t)param->line_num;
+            *linenum_update_reg |= VDC_GR_UPDATE_P_VEN_BIT;
+        }
+        else if (param->type == VDC_INT_TYPE_S0_WLINE)
+        {   /* Write specification line signal input to scaling-down control block in scaler 0 */
+            linenum16_reg       = vdc_regaddr_scaler.scl0_int;
+            linenum_update_reg  = vdc_regaddr_scaler.scl0_update;
+            *linenum16_reg       = param->line_num;
+            *linenum_update_reg |= VDC_SCL0_UPDATE_VEN_A_BIT;
+        }
+        else
+        {   /* Do nothing */
+        }
+    }
+    else
+    {   /* OFF */
+        *int_onoff_reg &= (uint32_t)~mask_bit;
+        reg_data        = *int_onoff_reg;
+        *int_clhd_reg   = reg_data;
+    }
+
+}   /* End of function VDC_Int_SetInterrupt() */
+
+/**************************************************************************//**
+ * @brief       VDC S0_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_S0_VI_VSYNC) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_S0_VI_VSYNC;
+
+        if (vdc_int_callback[VDC_INT_TYPE_S0_VI_VSYNC] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_S0_VI_VSYNC](VDC_INT_TYPE_S0_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC S0_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_S0_LO_VSYNC) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_S0_LO_VSYNC;
+
+        if (vdc_int_callback[VDC_INT_TYPE_S0_LO_VSYNC] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_S0_LO_VSYNC](VDC_INT_TYPE_S0_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC S0_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_S0_VSYNCERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_S0_VSYNCERR;
+
+        if (vdc_int_callback[VDC_INT_TYPE_S0_VSYNCERR] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_S0_VSYNCERR](VDC_INT_TYPE_S0_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_VLINE) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_VLINE;
+
+        if (vdc_int_callback[VDC_INT_TYPE_VLINE] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_VLINE](VDC_INT_TYPE_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC S0_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_s0_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_S0_VFIELD) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_S0_VFIELD;
+
+        if (vdc_int_callback[VDC_INT_TYPE_S0_VFIELD] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_S0_VFIELD](VDC_INT_TYPE_S0_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC IV1_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_IV1_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_IV1_VBUFERR;
+
+        if (vdc_int_callback[VDC_INT_TYPE_IV1_VBUFERR] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_IV1_VBUFERR](VDC_INT_TYPE_IV1_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC IV3_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_IV3_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_IV3_VBUFERR;
+
+        if (vdc_int_callback[VDC_INT_TYPE_IV3_VBUFERR] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_IV3_VBUFERR](VDC_INT_TYPE_IV3_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC IV5_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int1;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_IV5_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_IV5_VBUFERR;
+
+        if (vdc_int_callback[VDC_INT_TYPE_IV5_VBUFERR] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_IV5_VBUFERR](VDC_INT_TYPE_IV5_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC IV6_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int2;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_IV6_VBUFERR) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_IV6_VBUFERR;
+
+        if (vdc_int_callback[VDC_INT_TYPE_IV6_VBUFERR] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_IV6_VBUFERR](VDC_INT_TYPE_IV6_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC S0_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC_Ch0_s0_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc_regaddr_system_ctrl.syscnt_int2;
+    int_onoff_reg = vdc_regaddr_system_ctrl.syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC_INT_BIT_S0_WLINE) != 0u))
+    {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC_INT_BIT_S0_WLINE;
+
+        if (vdc_int_callback[VDC_INT_TYPE_S0_WLINE] != 0)
+        {
+            vdc_int_callback[VDC_INT_TYPE_S0_WLINE](VDC_INT_TYPE_S0_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC_Ch0_s0_wline_ISR() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_register.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,3282 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_register.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc_register.h"
+
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+#include    "r_vdc_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     INITIAL_SCALING_PHASE          ((uint32_t)2048u)
+#define     SCALING_RATIO_SAME_SIZE        (4096u)
+/* Vsync signal delay control for OIR */
+#define     OIR_VSYNC_DELAY                 ((uint32_t)1u)
+
+#define     LVDS_LPHYACC_VALUE              ((uint32_t)0x00001111u) //@@@
+
+/* Panel clock frequency division ratio */
+#define     VDC_REG_CLKDIV_1_1            (1u)
+#define     VDC_REG_CLKDIV_1_2            (2u)
+#define     VDC_REG_CLKDIV_1_3            (3u)
+#define     VDC_REG_CLKDIV_1_4            (4u)
+#define     VDC_REG_CLKDIV_1_5            (5u)
+#define     VDC_REG_CLKDIV_1_6            (6u)
+#define     VDC_REG_CLKDIV_1_7            (7u)
+#define     VDC_REG_CLKDIV_1_8            (8u)
+#define     VDC_REG_CLKDIV_1_9            (9u)
+#define     VDC_REG_CLKDIV_1_12           (12u)
+#define     VDC_REG_CLKDIV_1_16           (16u)
+#define     VDC_REG_CLKDIV_1_24           (24u)
+#define     VDC_REG_CLKDIV_1_32           (32u)
+/* Panel clock select */
+#define     VDC_REG_ICKSEL_IMG_DV         (0x0000u)
+#define     VDC_REG_ICKSEL_EXT_0          (0x1000u)
+#define     VDC_REG_ICKSEL_PERI           (0x3000u)
+#define     VDC_REG_ICKSEL_LVDS           (0x0400u)
+#define     VDC_REG_ICKSEL_LVDS_DIV7      (0x0800u)
+/* Output pin edge select */
+#define     VDC_REG_TCON0_EDGE            (0x0040u)
+#define     VDC_REG_TCON1_EDGE            (0x0020u)
+#define     VDC_REG_TCON2_EDGE            (0x0010u)
+#define     VDC_REG_TCON3_EDGE            (0x0008u)
+#define     VDC_REG_TCON4_EDGE            (0x0004u)
+#define     VDC_REG_TCON5_EDGE            (0x0002u)
+#define     VDC_REG_TCON6_EDGE            (0x0001u)
+/* Panel dither output format select */
+#define     VDC_REG_PATH_FORMAT_RGB888    (0x00000000u)
+#define     VDC_REG_PATH_FORMAT_RGB666    (0x00010000u)
+#define     VDC_REG_PATH_FORMAT_RGB565    (0x00020000u)
+#define     VDC_REG_PATH_FORMAT_NON       (0x00000000u)
+/* Calculate scaling ratio use value */
+#define     VDC_REG_FLOAT_1_0 (1.0f)
+#define     VDC_REG_FLOAT_0_5 (0.5f)
+/* bits per pixel */
+#define     VDC_REG_BIT_PER_PIXEL_RGB565    (16u)
+#define     VDC_REG_BIT_PER_PIXEL_RGB888    (32u)
+#define     VDC_REG_BIT_PER_PIXEL_ARGB1555  (16u)
+#define     VDC_REG_BIT_PER_PIXEL_ARGB4444  (16u)
+#define     VDC_REG_BIT_PER_PIXEL_ARGB8888  (32u)
+#define     VDC_REG_BIT_PER_PIXEL_CLUT8     (8u)
+#define     VDC_REG_BIT_PER_PIXEL_CLUT4     (4u)
+#define     VDC_REG_BIT_PER_PIXEL_CLUT1     (1u)
+#define     VDC_REG_BIT_PER_PIXEL_YCBCR422  (32u)
+#define     VDC_REG_BIT_PER_PIXEL_YCBCR444  (32u)
+#define     VDC_REG_BIT_PER_PIXEL_RGBA5551  (16u)
+#define     VDC_REG_BIT_PER_PIXEL_RGBA8888  (32u)
+#define     VDC_REG_BIT_PER_PIXEL_VALUE_8   (8u)
+/* Convert the color data from 4 bits value into 8 bits value */
+#define     VDC_REG_EXTENSION_VALUE_17      (17u)
+/* Convert the color data from 5 bits value into 8 bits value */
+#define     VDC_REG_EXTENSION_VALUE_263     (263u)
+#define     VDC_REG_EXTENSION_VALUE_32      (32u)
+/* Convert the color data from 6 bits value into 8 bits value */
+#define     VDC_REG_EXTENSION_VALUE_259     (259u)
+#define     VDC_REG_EXTENSION_VALUE_64      (64u)
+/* Round off */
+#define     VDC_REG_ROUND_OFF_VALUE_1       (1u)
+#define     VDC_REG_ROUND_OFF_VALUE_2       (2u)
+/* Color mask data */
+#define     VDC_REG_ALPHA_8BIT              (0xFF000000u)
+#define     VDC_REG_RGB_24BIT_MASK          (0x00FFFFFFu)
+#define     VDC_REG_COLOR_8BIT_MASK         (0x000000FFu)
+#define     VDC_REG_COLOR_6BIT_MASK         (0x0000003Fu)
+#define     VDC_REG_COLOR_5BIT_MASK         (0x0000001Fu)
+#define     VDC_REG_COLOR_4BIT_MASK         (0x0000000Fu)
+#define     VDC_REG_ARGB8888_GB_MASK        (0x00FFFF00u)
+
+/* RGB565 bits mask data */
+#define     VDC_REG_RGB565_R_MASK           (0x0000F800u)
+#define     VDC_REG_RGB565_G_MASK           (0x000007E0u)
+#define     VDC_REG_RGB565_B_MASK           (0x0000001Fu)
+/* ARGB4444 bits mask data */
+#define     VDC_REG_ARGB4444_R_MASK         (0x00000F00u)
+#define     VDC_REG_ARGB4444_G_MASK         (0x000000F0u)
+#define     VDC_REG_ARGB4444_B_MASK         (0x0000000Fu)
+/* ARGB1555 bits mask data */
+#define     VDC_REG_ARGB1555_R_MASK         (0x00007C00u)
+#define     VDC_REG_ARGB1555_G_MASK         (0x000003E0u)
+#define     VDC_REG_ARGB1555_B_MASK         (0x0000001Fu)
+/* RGBA5551 bits mask data */
+#define     VDC_REG_RGBA5551_R_MASK         (0x0000F800u)
+#define     VDC_REG_RGBA5551_G_MASK         (0x000007C0u)
+#define     VDC_REG_RGBA5551_B_MASK         (0x0000003Eu)
+
+/* bit pattern */
+#define     VDC_REG_BIT31          (0x80000000u)
+#define     VDC_REG_BIT29          (0x20000000u)
+#define     VDC_REG_BIT28          (0x10000000u)
+#define     VDC_REG_BIT24          (0x01000000u)
+#define     VDC_REG_BIT20          (0x00100000u)
+#define     VDC_REG_BIT16          (0x00010000u)
+#define     VDC_REG_BIT15          (0x00008000u)
+#define     VDC_REG_BIT14          (0x00004000u)
+#define     VDC_REG_BIT13          (0x00002000u)
+#define     VDC_REG_BIT12          (0x00001000u)
+#define     VDC_REG_BIT8           (0x00000100u)
+#define     VDC_REG_BIT4           (0x00000010u)
+#define     VDC_REG_BIT2           (0x00000004u)
+#define     VDC_REG_BIT1           (0x00000002u)
+#define     VDC_REG_BIT0           (0x00000001u)
+
+/* shift value */
+#define     VDC_REG_SHIFT_28       (28u)
+#define     VDC_REG_SHIFT_24       (24u)
+#define     VDC_REG_SHIFT_20       (20u)
+#define     VDC_REG_SHIFT_16       (16u)
+#define     VDC_REG_SHIFT_13       (13u)
+#define     VDC_REG_SHIFT_12       (12u)
+#define     VDC_REG_SHIFT_11       (11u)
+#define     VDC_REG_SHIFT_10       (10u)
+#define     VDC_REG_SHIFT_8        (8u)
+#define     VDC_REG_SHIFT_6        (6u)
+#define     VDC_REG_SHIFT_5        (5u)
+#define     VDC_REG_SHIFT_4        (4u)
+#define     VDC_REG_SHIFT_2        (2u)
+#define     VDC_REG_SHIFT_1        (1u)
+
+/* register set value */
+#define VDC_REG_BIT_0XFFFF0000     (0xFFFF0000u) /* scaler_0->scl0_frc2                     */
+/* register mask value */
+#define VDC_REG_MASK_0XF7FF1C3F    (0xF7FF1C3Fu) /* mask img_synthesizer->gr_flm6           */
+#define VDC_REG_MASK_0X0000D000    (0x0000D000u) /* mask img_synthesizer->gr_ab1            */
+#define VDC_REG_MASK_0X01FF00FF    (0x01FF00FFu) /* mask img_synthesizer->gr_ab6            */
+#define VDC_REG_MASK_0X0000007F    (0x0000007Fu) /* mask output_ctrl->out_clk_phase         */
+#define VDC_REG_MASK_0X11003313    (0x11003313u) /* mask output_ctrl->out_set               */
+#define VDC_REG_MASK_0X00030000    (0x00030000u) /* mask output_ctrl->out_pdtha             */
+#define VDC_REG_MASK_0X0007000D    (0x0007000Du) /* mask scaler->scl1_wr1                   */
+#define VDC_REG_MASK_0X00000300    (0x00000300u) /* mask scaler->scl1_wr5                   */
+#define VDC_REG_MASK_0X0300FF00    (0x0300FF00u) /* mask regaddr_lvds->lclkselr             */
+#define VDC_REG_MASK_0X003F0730    (0x003F0730u) /* mask regaddr_lvds->lpllsetr             */
+#define VDC_REG_MASK_0X00010301    (0x00010301u) /* mask img_synthesizer->gr_flm1           */
+#define VDC_REG_MASK_0X7FFF03FF    (0x7FFF03FFu) /* mask img_synthesizer->gr_flm3           */
+#define VDC_REG_MASK_0X0000E000    (0x0000E000u) /* mask img_synthesizer->gr_flm6           */
+#define VDC_REG_MASK_0X00007F33    (0x00007F33u) /* mask input_ctrl->imgcnt_nr_cnt0         */
+#define VDC_REG_MASK_0X00FF0000    (0x00FF0000u) /* mask img_synthesizer->gr_ab7            */
+#define VDC_REG_MASK_0X00300000    (0x00300000u) /* mask output_ctrl->out_pdtha             */
+#define VDC_REG_MASK_0X00003333    (0x00003333u) /* mask output_ctrl->out_pdtha             */
+#define VDC_REG_MASK_0X00007111    (0x00007111u) /* mask input_ctrl->inp_sel_cnt            */
+#define VDC_REG_MASK_0X11110113    (0x11110113u) /* mask input_ctrl->inp_ext_sync_cnt       */
+#define VDC_REG_MASK_0X000007FF    (0x000007FFu) /* mask img_synthesizer->gr_flm5           */
+#define VDC_REG_MASK_0X0000FFFF    (0x0000FFFFu) /* mask scaler->scl0_ds4                   */
+                                                  /*      caler->scl0_us5                    */
+#define VDC_REG_MASK_0X00000011    (0x00000011u) /* mask scaler->scl0_ds1                   */
+                                                  /*      scaler->scl0_us1                   */
+#define VDC_REG_MASK_0X00000070    (0x00000070u) /* mask scaler->scl1_wr1                   */
+#define VDC_REG_MASK_0X00000080    (0x00000080u) /* mask scaler->scl1_wr1                   */
+#define VDC_REG_MASK_0X00003110    (0x00003110u) /* mask output_ctrl->tcon_tim_pola2        */
+                                                  /*      output_ctrl->tcon_tim_polb2        */
+#define VDC_REG_MASK_0X000000FF    (0x000000FFu) /* mask scaler_0->scl0_frc5                */
+#define VDC_REG_MASK_0X0000003F    (0x0000003Fu) /* mask img_synthesizer->gr_flm6           */
+                                                  /*      img_qlty_imp->adj_enh_shp1         */
+#define VDC_REG_MASK_0XFF000000    (0xFF000000u) /* mask img_synthesizer->gr_ab10           */
+                                                  /*      img_synthesizer->gr_ab11           */
+#define VDC_REG_MASK_0X00000110    (0x00000110u) /* mask output_ctrl->tcon_tim_sth2         */
+                                                  /*      output_ctrl->tcon_tim_stb2         */
+                                                  /*      output_ctrl->tcon_tim_cpv2         */
+#define VDC_REG_MASK_0X00000007    (0x00000007u) /* mask *(output_pin_regaddr[tcon_pin])    */
+                                                  /*      img_synthesizer->gr_flm2           */
+                                                  /*      img_synthesizer->gr_flm2           */
+#define VDC_REG_MASK_0X07FF0000    (0x07FF0000u) /* mask scaler_0->scl0_frc4                */
+                                                  /*      img_synthesizer->gr_flm5           */
+                                                  /*      img_synthesizer->gr_flm6           */
+#define VDC_REG_MASK_0X0FFF0FFF    (0x0FFF0FFFu) /* mask                                    */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+                                                  /*      scaler->scl0_ds5, scaler->scl0_us6 */
+#define VDC_REG_MASK_0X00000003    (0x00000003u) /* mask img_synthesizer->gr_ab1            */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void SetVideoExternalInput(
+    const vdc_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc_regaddr_input_ctrl_t * const input_ctrl);
+static void SetInitialConnection(void);
+static void SetGrapicsBackgroundColor(void);
+static void SetScalerBackgroundColor(const vdc_color_space_t color_space);
+static void SetLcdTcon_STVA_VS(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STVB_VE(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STH_HS(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STB_HE(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_CPV_GCK(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLA(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLB(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_DE(
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetScalingDown(
+    const vdc_scalingdown_rot_t    * const scldw_rot,
+    const vdc_res_inter_t                  res_inter,
+    const vdc_regaddr_scaler_t     * const scaler);
+static void SetScalingUp(
+    const vdc_width_read_fb_t  * const w_read_fb,
+    const vdc_period_rect_t    * const gr_grc,
+    const vdc_onoff_t                  adj_sel,
+    const vdc_onoff_t                  ip_conversion,
+    const vdc_wr_md_t                  res_ds_wr_md,
+    const vdc_gr_ln_off_dir_t          ln_off_dir,
+    const vdc_regaddr_scaler_t * const scaler);
+static uint32_t CalcScalingRatio(
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc_onoff_t  adj_sel,
+    const vdc_onoff_t  round_up);
+static void SetInputCntrlColorMtx(void);
+static vdc_onoff_t ConfirmGraphicsEnlargement(
+    const vdc_graphics_type_t          graphics_id,
+    const vdc_gr_flm_sel_t             gr_flm_sel,
+    const vdc_width_read_fb_t  * const w_read_fb,
+    const vdc_period_rect_t    * const gr_grc);
+static void SetScalerGraphics(
+    const vdc_graphics_type_t          graphics_id,
+    const vdc_width_read_fb_t  * const w_read_fb,
+    const vdc_period_rect_t    * const gr_grc,
+    const vdc_gr_flm_sel_t             gr_flm_sel,
+    const vdc_onoff_t                  gr_enlarge);
+static uint32_t DisplayStartPixelSetting(const uint32_t gr_base, const vdc_gr_format_t gr_format);
+static void SetImgQaImproverColorMtx(const vdc_color_space_t color_space);
+
+static void SetRwProcAbility_Write_0(const vdc_onoff_t ability);
+static void SetRwProcAbility_Read_0(const vdc_onoff_t ability);
+static void SetRwProcAbility_Read_2(const vdc_onoff_t ability);
+static void SetRwProcAbility_Read_3(const vdc_onoff_t ability);
+static void SetRegUpdateRwEnable(const vdc_layer_id_t layer_id);
+
+static void SetGraphicsDisplayMode(const vdc_layer_id_t layer_id, const vdc_gr_disp_sel_t * const gr_disp_sel);
+static void SetColorMatrix(
+    const vdc_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc_regaddr_color_matrix_t   * const color_matrix);
+static void SetImageEnhancementSharpness(
+    const vdc_onoff_t                          shp_h_on,
+    const vdc_enhance_sharp_t          * const sharp_param,
+    const vdc_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetImageEnhancementLti(
+    const vdc_onoff_t                          lti_h_on,
+    const vdc_enhance_lti_t            * const lti_param,
+    const vdc_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetAlphaRectArea(
+    const vdc_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc_regaddr_img_synthesizer_t    * const img_synthesizer);
+static uint32_t ColorConversion(const vdc_gr_format_t gr_format, const uint32_t input_color);
+static uint32_t ColorConversionFrom4to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom5to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom6to8(const uint32_t color_value);
+static uint32_t ColorConversionIntoAgbr(const uint32_t color_value);
+static void Set_Clut(const vdc_clut_t * const param, volatile uint32_t * regaddr_clut);
+static void Set_StartThreshold_Gamma(const uint8_t * gam_th, volatile uint32_t * const * const gam_area);
+static void Set_GainAdjustment_Gamma(const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut);
+static void Wait_200_usec(void);
+
+/*! Color matrix offset (DC) adjustment (YG, B, and R) */
+static const uint16_t colormtx_offset_adj[VDC_COLORMTX_OFFST_NUM] =
+{
+    (uint16_t)VDC_COLORCONV_DC_OFFSET, (uint16_t)VDC_COLORCONV_DC_OFFSET, (uint16_t)VDC_COLORCONV_DC_OFFSET
+};
+/*! Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+static const uint16_t colormtx_gain_adj[VDC_COLORMTX_MODE_NUM][VDC_COLORMTX_GAIN_NUM] =
+{
+    {   /* GBR to GBR */
+        (uint16_t)VDC_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC_COLORCONV_1TIMES_GAIN
+    },
+    {   /* GBR to YCbCr */
+        (uint16_t)VDC_COLORCONV_Y_G,  (uint16_t)VDC_COLORCONV_Y_B,  (uint16_t)VDC_COLORCONV_Y_R,
+        (uint16_t)VDC_COLORCONV_CB_G, (uint16_t)VDC_COLORCONV_CB_B, (uint16_t)VDC_COLORCONV_CB_R,
+        (uint16_t)VDC_COLORCONV_CR_G, (uint16_t)VDC_COLORCONV_CR_B, (uint16_t)VDC_COLORCONV_CR_R
+    },
+    {   /* YCbCr to GBR */
+        (uint16_t)VDC_COLORCONV_G_Y, (uint16_t)VDC_COLORCONV_G_CB, (uint16_t)VDC_COLORCONV_G_CR,
+        (uint16_t)VDC_COLORCONV_B_Y, (uint16_t)VDC_COLORCONV_B_CB, (uint16_t)VDC_COLORCONV_B_CR,
+        (uint16_t)VDC_COLORCONV_R_Y, (uint16_t)VDC_COLORCONV_R_CB, (uint16_t)VDC_COLORCONV_R_CR
+    },
+    {   /* YCbCr to YCbCr */
+        (uint16_t)VDC_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC_COLORCONV_1TIMES_GAIN
+    }
+};
+
+static void (* const rw_proc_function_tbl[VDC_LAYER_ID_NUM])(const vdc_onoff_t ability) =
+{
+    &SetRwProcAbility_Write_0,          /* Write scaler 0 */
+    &SetRwProcAbility_Read_0,           /* Read graphics 0 */
+    &SetRwProcAbility_Read_2,           /* Read graphics 2 */
+    &SetRwProcAbility_Read_3            /* Read graphics 3 */
+};
+
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_Initialize (const vdc_init_t * const param)
+{
+    const vdc_lvds_t         * lvds_tmp;
+    const vdc_regaddr_lvds_t * regaddr_lvds;
+    volatile uint32_t           counter;
+    uint16_t                    syscnt_panel_clk_tmp;
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    volatile uint32_t         * inp_sel_cnt_reg;
+    static const uint16_t       panel_dcdr_tbl[VDC_PANEL_CLKDIV_NUM] =
+    {   /* Panel clock frequency division ratio */
+        (uint16_t)VDC_REG_CLKDIV_1_1, (uint16_t)VDC_REG_CLKDIV_1_2,  (uint16_t)VDC_REG_CLKDIV_1_3,  (uint16_t)VDC_REG_CLKDIV_1_4,
+        (uint16_t)VDC_REG_CLKDIV_1_5, (uint16_t)VDC_REG_CLKDIV_1_6,  (uint16_t)VDC_REG_CLKDIV_1_7,  (uint16_t)VDC_REG_CLKDIV_1_8,
+        (uint16_t)VDC_REG_CLKDIV_1_9, (uint16_t)VDC_REG_CLKDIV_1_12, (uint16_t)VDC_REG_CLKDIV_1_16, (uint16_t)VDC_REG_CLKDIV_1_24,
+        (uint16_t)VDC_REG_CLKDIV_1_32
+    };
+    static const uint16_t       panel_icksel_tbl[VDC_PANEL_ICKSEL_NUM] =
+    {   /* Panel clock select */
+        (uint16_t)VDC_REG_ICKSEL_IMG_DV, (uint16_t)VDC_REG_ICKSEL_EXT_0,
+        (uint16_t)VDC_REG_ICKSEL_PERI, (uint16_t)VDC_REG_ICKSEL_LVDS,   (uint16_t)VDC_REG_ICKSEL_LVDS_DIV7
+    };
+
+    syscnt_panel_clk_reg = vdc_regaddr_system_ctrl.syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+    /* LVDS */
+    lvds_tmp = param->lvds;
+    if (lvds_tmp != NULL)
+    {
+        regaddr_lvds = &vdc_regaddr_lvds;
+
+        /* Output from the LVDS PLL is disabled. */
+        *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC_REG_BIT4;
+        /* Controls power-down for the LVDS PLL: Power-down state */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC_REG_BIT0;
+        for (counter = 0; counter < (uint32_t)VDC_LVDS_PLL_WAIT_CYCLE; counter++)
+        {
+            /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+        }
+
+        /* LPHYACC */
+//        *(regaddr_lvds->lphyacc) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+//        *(regaddr_lvds->lphyacc) |= LVDS_LPHYACC_VALUE;
+        /* LCLKSELR: LVDS clock select register */
+        *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC_REG_MASK_0X0300FF00;
+            /* The clock input to frequency divider 1 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_in_clk_sel << VDC_REG_SHIFT_24;
+            /* The frequency dividing value (NIDIV) for frequency divider 1 */
+//@@@        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_idiv_set << VDC_REG_SHIFT_16;
+            /* Internal parameter setting for LVDS PLL */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvdspll_tst << VDC_REG_SHIFT_10;
+            /* The frequency dividing value (NODIV) for frequency divider 2 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_odiv_set << VDC_REG_SHIFT_8;
+        if (lvds_tmp->lvds_vdc_sel != VDC_CHANNEL_0)
+        {
+            /* A channel in VDC whose data is to be output through the LVDS */
+//@@@            *(regaddr_lvds->lclkselr) |= (uint32_t)VDC_REG_BIT1;
+        }
+
+        /* LPLLSETR: LVDS PLL setting register */
+        *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC_REG_MASK_0X003F0730;
+            /* The frequency dividing value (NFD) for the feedback frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_fd << VDC_REG_SHIFT_16;
+            /* The frequency dividing value (NRD) for the input frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_rd << VDC_REG_SHIFT_8;
+            /* The frequency dividing value (NOD) for the output frequency */
+//@@@        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_od << VDC_REG_SHIFT_4;
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)1u << VDC_REG_SHIFT_4;
+
+        for (counter = 0; counter < (uint32_t)VDC_LVDS_PLL_WAIT_CYCLE; counter++)
+        {
+            /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+        }
+        /* Controls power-down for the LVDS PLL: Normal operation */
+        *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC_REG_BIT0;
+
+        /* Wait for 200 usec. */
+        Wait_200_usec();
+
+        /* Output from the LVDS PLL is enabled. */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)VDC_REG_BIT4;
+    }
+
+    inp_sel_cnt_reg = vdc_regaddr_input_ctrl.inp_sel_cnt;
+    /* Input select */
+    if (param->panel_icksel == VDC_PANEL_ICKSEL_IMG_DV)
+    {
+        *inp_sel_cnt_reg |= (uint32_t)VDC_REG_BIT20;
+    }
+    else
+    {
+        *inp_sel_cnt_reg &= (uint32_t)~VDC_REG_BIT20;
+    }
+    syscnt_panel_clk_tmp    = panel_dcdr_tbl[param->panel_dcdr];
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp |
+                                        (uint32_t)panel_icksel_tbl[param->panel_icksel]);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+    /* Enable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp | VDC_REG_BIT8);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+}   /* End of function VDC_Initialize() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for termination
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void VDC_Terminate (void)
+{
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    uint16_t                    syscnt_panel_clk_tmp;
+    vdc_resource_state_t       rsrc_state;
+    vdc_onoff_t                lvds_ref;
+    const vdc_regaddr_lvds_t * regaddr_lvds;
+    volatile uint32_t           counter;
+
+    syscnt_panel_clk_reg = vdc_regaddr_system_ctrl.syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+    rsrc_state = VDC_ShrdPrmGetResource(VDC_RESOURCE_LVDS_CLK);
+    if (rsrc_state != VDC_RESOURCE_ST_INVALID)         /* LVDS PLL clock is set. */
+    {
+        lvds_ref = VDC_ShrdPrmGetLvdsClkRef();
+        if (lvds_ref == VDC_OFF)       /* LVDS PLL clock is not referred. */
+        {
+            regaddr_lvds = &vdc_regaddr_lvds;
+
+            /* Output from the LVDS PLL is disabled. */
+            *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC_REG_BIT4;
+            /* Controls power-down for the LVDS PLL: Power-down state */
+            *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC_REG_BIT0;
+            for (counter = 0; counter < (uint32_t)VDC_LVDS_PLL_WAIT_CYCLE; counter++)
+            {
+                /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+            }
+        }
+    }
+}   /* End of function VDC_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for video input
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_VideoInput (const vdc_input_t * const param)
+{
+    const vdc_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc_sync_delay_t           * dly_tmp;
+    const vdc_ext_in_sig_t           * ext_sig_tmp;
+
+    input_ctrl = &vdc_regaddr_input_ctrl;
+
+    /* Input select */
+    *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC_REG_BIT20;
+    /* Vsync signal 1/2fH and 1/4fH phase timing */
+    *(input_ctrl->inp_vsync_ph_adj)  = (uint32_t)param->inp_fh50 << VDC_REG_SHIFT_16;
+    *(input_ctrl->inp_vsync_ph_adj) |= (uint32_t)param->inp_fh25;
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL)
+    {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        *(input_ctrl->inp_dly_adj)  = (uint32_t)dly_tmp->inp_vs_dly_l << VDC_REG_SHIFT_24;
+        /* Field differentiation signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_fld_dly << VDC_REG_SHIFT_16;
+        /* Vsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_vs_dly << VDC_REG_SHIFT_8;
+        /* Hsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_hs_dly;
+    }
+
+    /* Horizontal noise reduction operating mode, Y/Cb/Cr mode */
+    *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC_REG_BIT20;
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp != NULL)
+    {
+        /* Setting external input video signal */
+        SetVideoExternalInput(ext_sig_tmp, input_ctrl);
+
+        /* Horizontal noise reduction operating mode, G/B/R mode */
+        if ((ext_sig_tmp->inp_format == VDC_EXTIN_FORMAT_RGB888) ||
+            (ext_sig_tmp->inp_format == VDC_EXTIN_FORMAT_RGB666) ||
+            (ext_sig_tmp->inp_format == VDC_EXTIN_FORMAT_RGB565))
+        {
+            *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC_REG_BIT20;
+        }
+    }
+
+    /* Register update control register (INP_UPDATE)
+       b4       INP_EXT_UPDATE
+       b0       INP_IMG_UPDATE */
+    *(input_ctrl->inp_update) |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC_REG_BIT0;
+}   /* End of function VDC_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for sync control
+ * @param[in]   param                   : Sync signal control parameter
+ * @retval      None
+******************************************************************************/
+void VDC_SyncControl (const vdc_sync_ctrl_t * const param)
+{
+    const vdc_regaddr_scaler_t   * scaler_0;
+    uint32_t                        full_scr;
+
+    scaler_0    = &vdc_regaddr_scaler;
+
+    if (param->vsync_cpmpe != NULL)
+    {
+        /* Frequent Vsync signal masking period */
+        *(scaler_0->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC_REG_SHIFT_16;
+        /* Missing-Sync compensating pulse output wait time */
+        *(scaler_0->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC_REG_SHIFT_16;
+        /* Frequent Vsync signal masking and missing Vsync signal compensation */
+        *(scaler_0->scl0_frc1) |= (uint32_t)VDC_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC_REG_BIT0;
+    }
+    else
+    {   /* Frequent Vsync signal masking and missing Vsync signal compensation are disabled, if unnecessary. */
+        *(scaler_0->scl0_frc1) &= (uint32_t)~VDC_REG_BIT0;
+        *(scaler_0->scl0_frc2) &= (uint32_t)~VDC_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC_REG_BIT_0XFFFF0000;
+    }
+
+    /* Hsync period setting and free-running Vsync period initialization */
+    *(scaler_0->scl0_frc4)      = (uint32_t)param->res_fh;
+    /* Vsync signal output select (free-running Vsync on/off control) */
+    if (param->res_vs_sel == VDC_OFF)
+    {
+        *(scaler_0->scl0_frc3) &= (uint32_t)~VDC_REG_BIT0;
+    }
+    else
+    {
+        *(scaler_0->scl0_frc3) |= (uint32_t)VDC_REG_BIT0;
+        *(scaler_0->scl0_frc4) &= (uint32_t)~VDC_REG_MASK_0X07FF0000;
+        *(scaler_0->scl0_frc4) |= (uint32_t)param->res_fv << VDC_REG_SHIFT_16;
+    }
+
+    /* Vsync signal delay control */
+    *(scaler_0->scl0_frc5) &= (uint32_t)~VDC_REG_MASK_0X000000FF;
+    *(scaler_0->scl0_frc5) |= (uint32_t)param->res_vsdly;
+
+    /* Full-screen enable signal */
+    full_scr  = (uint32_t)param->res_f.vs << VDC_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.vw;
+
+    *(scaler_0->scl0_frc6)   = full_scr;
+
+    full_scr  = (uint32_t)param->res_f.hs << VDC_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.hw;
+
+    *(scaler_0->scl0_frc7)   = full_scr;
+
+    /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+       b8       SCL0_UPDATE
+       b4       SCL0_VEN_B */
+    *(scaler_0->scl0_update)   |= (uint32_t)(VDC_REG_BIT8|VDC_REG_BIT4);
+
+    SetInitialConnection();
+}   /* End of function VDC_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display output
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+******************************************************************************/
+void VDC_DisplayOutput (const vdc_output_t * const param)
+{
+    const vdc_regaddr_output_ctrl_t      * output_ctrl;
+    volatile uint32_t                     * output_pin_regaddr[VDC_LCD_TCON_PIN_NUM];
+    uint32_t                                tcon_sig_index;
+    const vdc_lcd_tcon_timing_t  * const * lcd_tcon_timing;
+    static void                    (* const tcon_function_tbl[VDC_LCD_TCONSIG_NUM])(
+        const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+        const vdc_regaddr_output_ctrl_t    * const output_ctrl) =
+    {
+        &SetLcdTcon_STVA_VS,    /* STVA/VS */
+        &SetLcdTcon_STVB_VE,    /* STVB/VE */
+        &SetLcdTcon_STH_HS,     /* STH_HS */
+        &SetLcdTcon_STB_HE,     /* STB_HE */
+        &SetLcdTcon_CPV_GCK,    /* CPV_GCK */
+        &SetLcdTcon_POLA,       /* POLA */
+        &SetLcdTcon_POLB,       /* POLB */
+        &SetLcdTcon_DE          /* DE */
+    };
+    const uint32_t                      output_pin_edge[VDC_LCD_TCON_PIN_NUM] =
+    {
+       VDC_REG_TCON0_EDGE, VDC_REG_TCON1_EDGE, VDC_REG_TCON2_EDGE, VDC_REG_TCON3_EDGE,
+       VDC_REG_TCON4_EDGE, VDC_REG_TCON5_EDGE, VDC_REG_TCON6_EDGE
+    };
+    vdc_lcd_tcon_pin_t                 tcon_pin_tmp;
+    const vdc_gr_disp_sel_t            gr_disp_sel_tbl[VDC_GR_TYPE_NUM] =
+    {   /* Graphics display mode for initialization */
+        VDC_DISPSEL_BACK,              /* Graphics 0 */
+        VDC_DISPSEL_LOWER,             /* Graphics 2 */
+        VDC_DISPSEL_LOWER              /* Graphics 3 */
+    };
+    const uint32_t                      dither_format[VDC_LCD_OUTFORMAT_NUM] =
+    {   /* Panel dither output format select */
+        VDC_REG_PATH_FORMAT_RGB888, VDC_REG_PATH_FORMAT_RGB666,
+        VDC_REG_PATH_FORMAT_RGB565, VDC_REG_PATH_FORMAT_NON
+    };
+
+    output_ctrl = &vdc_regaddr_output_ctrl;
+
+    /* 1/2fH timing */
+    *(output_ctrl->tcon_tim)  = (uint32_t)param->tcon_half << VDC_REG_SHIFT_16;
+    /* Offset Hsync signal timing */
+    *(output_ctrl->tcon_tim) |= (uint32_t)param->tcon_offset;
+
+    /* Create output pin register address table */
+    output_pin_regaddr[VDC_LCD_TCON_PIN_0] = output_ctrl->tcon_tim_stva2;
+    output_pin_regaddr[VDC_LCD_TCON_PIN_1] = output_ctrl->tcon_tim_stvb2;
+    output_pin_regaddr[VDC_LCD_TCON_PIN_2] = output_ctrl->tcon_tim_sth2;
+    output_pin_regaddr[VDC_LCD_TCON_PIN_3] = output_ctrl->tcon_tim_stb2;
+    output_pin_regaddr[VDC_LCD_TCON_PIN_4] = output_ctrl->tcon_tim_cpv2;
+    output_pin_regaddr[VDC_LCD_TCON_PIN_5] = output_ctrl->tcon_tim_pola2;
+    output_pin_regaddr[VDC_LCD_TCON_PIN_6] = output_ctrl->tcon_tim_polb2;
+
+    /* Clear output phase control of LCT_TCON0~6 pin */
+    *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC_REG_MASK_0X0000007F;
+    /* LCD TCON */
+    lcd_tcon_timing = param->outctrl;
+    for (tcon_sig_index = 0; tcon_sig_index < VDC_LCD_TCONSIG_NUM; tcon_sig_index++)
+    {
+        if (*lcd_tcon_timing != NULL)
+        {
+            /* Setting LCD TCON */
+            tcon_function_tbl[tcon_sig_index](*lcd_tcon_timing, output_ctrl);
+
+            tcon_pin_tmp = (*lcd_tcon_timing)->tcon_pin;
+            if (tcon_pin_tmp != VDC_LCD_TCON_PIN_NON)
+            {   /* LCD TCON output pin select */
+                *(output_pin_regaddr[tcon_pin_tmp]) &= (uint32_t)~VDC_REG_MASK_0X00000007;
+                *(output_pin_regaddr[tcon_pin_tmp]) |= tcon_sig_index;
+                /* Output phase control of LCT_TCON pin */
+                if ((*lcd_tcon_timing)->outcnt_edge != VDC_EDGE_RISING)
+                {
+                    *(output_ctrl->out_clk_phase) |= output_pin_edge[tcon_pin_tmp];
+                }
+            }
+        }
+        lcd_tcon_timing++;
+    }
+
+    *(output_ctrl->out_set) &= (uint32_t)~VDC_REG_MASK_0X11003313;
+    /* Bit endian change ON/OFF control */
+    if (param->out_endian_on != VDC_OFF)
+    {
+        *(output_ctrl->out_set) |= (uint32_t)VDC_REG_BIT28;
+    }
+    /* B/R signal swap ON/OFF control */
+    if (param->out_swap_on != VDC_OFF)
+    {
+        *(output_ctrl->out_set) |= (uint32_t)VDC_REG_BIT24;
+    }
+    /* Output format select */
+    *(output_ctrl->out_set) |= (uint32_t)param->out_format << VDC_REG_SHIFT_12;
+
+    /* Panel dither output format select */
+    *(output_ctrl->out_pdtha) &= (uint32_t)~VDC_REG_MASK_0X00030000;
+    *(output_ctrl->out_pdtha) |= dither_format[param->out_format];
+
+    if (param->out_format == VDC_LCD_OUTFORMAT_SERIAL_RGB)
+    {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_frq_sel << VDC_REG_SHIFT_8;
+        /* Scan direction select */
+        if (param->out_dir_sel != VDC_LCD_SERIAL_SCAN_FORWARD)
+        {
+            *(output_ctrl->out_set) |= (uint32_t)VDC_REG_BIT4;
+        }
+        /* Clock phase adjustment */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_phase;
+    }
+    else
+    {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)VDC_LCD_PARALLEL_CLKFRQ_1 << VDC_REG_SHIFT_8;
+    }
+
+    /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+    if (param->outcnt_lcd_edge == VDC_EDGE_RISING)
+    {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC_REG_BIT8;
+    }
+    else
+    {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC_REG_BIT8;
+    }
+
+    /* Set background color */
+    SetGrapicsBackgroundColor();
+    /* Initialize graphics display mode */
+    SetGraphicsDisplayMode(VDC_LAYER_ID_ALL, gr_disp_sel_tbl);
+
+    /* TCON register update control register (TCON_UPDATE)
+       b0       TCON_VEN */
+    *(output_ctrl->tcon_update) |= (uint32_t)VDC_REG_BIT0;
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC_REG_BIT0;
+
+}   /* End of function VDC_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write control processing
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+******************************************************************************/
+void VDC_WriteDataControl (const vdc_write_t * const param)
+{
+    const vdc_regaddr_scaler_t   * scaler;
+    const vdc_scalingdown_rot_t  * scldw_rot;
+
+    scaler      = &vdc_regaddr_scaler;
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC_REG_MASK_0X0007000D;
+    /* Swap setting in frame buffer writing */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_wrswa << VDC_REG_SHIFT_16;
+    /* Frame buffer video-signal writing format */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_md << VDC_REG_SHIFT_2;
+    /* Transfer burst length for frame buffer writing */
+    if (param->res_bst_md != VDC_BST_MD_32BYTE)
+    {
+        *(scaler->scl1_wr1) |= (uint32_t)VDC_REG_BIT0;
+    }
+
+    /* Frame buffer base address */
+    *(scaler->scl1_wr2) = R_VDC_CPUVAddrToSysPAddr( (uint32_t)param->base) ;
+    /* Frame buffer line offset address[byte] */
+    *(scaler->scl1_wr3) = param->ln_off << VDC_REG_SHIFT_16;
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    *(scaler->scl1_wr3) |= param->flm_num;
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u)
+    {
+        *(scaler->scl1_wr4) = param->flm_off;
+    }
+
+    /* Writing rate */
+    *(scaler->scl1_wr5) &= (uint32_t)~VDC_REG_MASK_0X00000300;
+    *(scaler->scl1_wr5) |= (uint32_t)param->res_fs_rate << VDC_REG_SHIFT_8;
+
+    /* Dither correction on/off */
+    if (param->res_dth_on == VDC_OFF)
+    {
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC_REG_BIT4;
+    }
+    else
+    {
+        *(scaler->scl1_wr6) |= (uint32_t)VDC_REG_BIT4;
+    }
+    /* Bit Reduction */
+    if (param->res_md == VDC_RES_MD_RGB565)
+    {   /* On */
+        *(scaler->scl1_wr6) |= (uint32_t)VDC_REG_BIT0;
+    }
+    else
+    {   /* Off */
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC_REG_BIT0;
+    }
+
+    /* Scaler 0 or 1 */
+    /* Field determination signal delay control */
+    if (param->flm_num == 0u)
+    {   /* Frame buffer: One plane */
+        *(scaler->scl0_frc5) &= (uint32_t)~VDC_REG_BIT8;
+    }
+    else
+    {   /* Frame buffer: Two planes or more */
+        *(scaler->scl0_frc5) |= (uint32_t)VDC_REG_BIT8;
+    }
+
+    /* Horizontal prefilter */
+    if (scldw_rot->res_pfil_sel == VDC_OFF)
+    {
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC_REG_BIT29;
+    }
+    else
+    {
+        *(scaler->scl0_ds4) |= (uint32_t)VDC_REG_BIT29;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC_REG_SHIFT_16;
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+    /* Scaling-down */
+    SetScalingDown(scldw_rot, param->res_inter, scaler);
+
+    /* Frame buffer writing mode for image processing */
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC_REG_MASK_0X00000070;
+    *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC_REG_SHIFT_4;
+
+    /* Field operating mode select */
+    if (param->res_inter == VDC_RES_INTER_PROGRESSIVE)
+    {   /* Progressive */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC_REG_BIT12;
+    }
+    else
+    {   /* Interlace */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC_REG_BIT12;
+    }
+    /* Write field select */
+    if (param->res_fld_sel == VDC_RES_FLD_SEL_TOP)
+    {   /* Top field */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC_REG_BIT4;
+    }
+    else
+    {   /* Bottom field */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC_REG_BIT4;
+    }
+
+    /* Frame buffer for bottom */
+    if (param->btm_base != NULL)
+    {
+        /* SC_RES_TB_ADD_MOD */
+        *(scaler->scl1_wr1) |= (uint32_t)VDC_REG_MASK_0X00000080;
+
+        /* Frame buffer base address */
+        *(scaler->scl1_wr8) = (uint32_t)param->btm_base;
+        /* Frame buffer line offset address[byte] */
+        *(scaler->scl1_wr9)  = param->ln_off << VDC_REG_SHIFT_16;
+        /* The number of frames of buffer (defined by res_flm_num + 1) */
+        *(scaler->scl1_wr9) |= param->flm_num;
+        /* Frame buffer frame offset address */
+        if (param->flm_num != 0u)
+        {
+            *(scaler->scl1_wr10) = param->flm_off;
+        }
+    }
+    else
+    {
+        /* SC_RES_TB_ADD_MOD */
+        *(scaler->scl1_wr1) &= (uint32_t)~VDC_REG_MASK_0X00000080;
+    }
+
+    /* Register update control register (SC0_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC_REG_BIT12 | VDC_REG_BIT4 | VDC_REG_BIT0);
+    /* Register update control register (SC0_SCL1_UPDATE)
+       b16      SCL1_UPDATE_A
+       b4       SCL1_VEN_B
+       b0       SCL1_VEN_A */
+    *(scaler->scl1_update)   |= (uint32_t)(VDC_REG_BIT16 | VDC_REG_BIT4 | VDC_REG_BIT0);
+
+    SetInputCntrlColorMtx();
+}   /* End of function VDC_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write change processing
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+******************************************************************************/
+void VDC_ChangeWriteProcess (const vdc_write_chg_t * const param)
+{
+    const vdc_regaddr_scaler_t   * scaler;
+    const vdc_scalingdown_rot_t  * scldw_rot;
+    vdc_res_inter_t                res_inter_tmp;
+
+    scaler      = &vdc_regaddr_scaler;
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    /* Horizontal prefilter */
+    if (scldw_rot->res_pfil_sel == VDC_OFF)
+    {
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC_REG_BIT29;
+    }
+    else
+    {
+        *(scaler->scl0_ds4) |= (uint32_t)VDC_REG_BIT29;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC_REG_SHIFT_16;
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+    /* Progressive or interlace */
+    res_inter_tmp = VDC_ShrdPrmGetInterlace();
+    /* Scaling-down */
+    SetScalingDown(scldw_rot, res_inter_tmp, scaler);
+
+    /* Frame buffer writing mode for image processing */
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC_REG_MASK_0X00000070;
+    *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC_REG_SHIFT_4;
+
+    /* Register update control register (SC0_SCL1_UPDATE)
+       b4       SCL1_VEN_B
+       b0       SCL1_VEN_A */
+    *(scaler->scl1_update)   |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+
+    /* Register update control register (SC0_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC_REG_BIT12 | VDC_REG_BIT4 | VDC_REG_BIT0);
+
+}   /* End of function VDC_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read control processing
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+******************************************************************************/
+void VDC_ReadDataControl (const vdc_graphics_type_t graphics_id, const vdc_read_t * const param)
+{
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc_regaddr_img_qlty_imp_t     * img_qlty_imp;
+    vdc_width_read_fb_t                  * w_read_fb;
+    vdc_onoff_t                            graphics_enlargement;
+    vdc_color_space_t                      color_space;
+    uint32_t                                reg_data;
+
+    w_read_fb = VDC_ShrdPrmGetFrBuffWidth_Rd(graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, param->gr_flm_sel, w_read_fb, &param->gr_grc);
+
+    if (graphics_id == VDC_GR_TYPE_GR0)
+    {
+        SetScalerGraphics(graphics_id, w_read_fb, &param->gr_grc, param->gr_flm_sel, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+    *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC_REG_MASK_0X00010301;
+    /* Line offset address direction of the frame buffer */
+    if (param->gr_ln_off_dir != VDC_GR_LN_OFF_DIR_INC)
+    {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC_REG_BIT16;
+    }
+    /* Frame buffer address setting signal */
+    *(img_synthesizer->gr_flm1) |= (uint32_t)param->gr_flm_sel << VDC_REG_SHIFT_8;
+    /* Frame buffer burst transfer mode */
+    if (param->gr_bst_md != VDC_BST_MD_32BYTE)
+    {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC_REG_BIT0;
+    }
+    /* Sets the frame buffer number for distortion correction */
+    if (param->gr_flm_sel == VDC_GR_FLM_SEL_DISTORTION)
+    {
+        if (param->gr_imr_flm_inv == VDC_OFF)
+        {
+            *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC_REG_BIT4;
+        }
+        else
+        {
+            *(img_synthesizer->gr_flm1) |= (uint32_t)VDC_REG_BIT4;
+        }
+    }
+
+    /* Frame buffer base address */
+    *(img_synthesizer->gr_flm2) = (uint32_t)(R_VDC_CPUVAddrToSysPAddr((uint32_t)param->gr_base) & (uint32_t)~VDC_REG_MASK_0X00000007);
+
+    /* Frame buffer line offset address[byte] */
+    *(img_synthesizer->gr_flm3) &= (uint32_t)~VDC_REG_MASK_0X7FFF03FF;
+    *(img_synthesizer->gr_flm3) |= param->gr_ln_off << VDC_REG_SHIFT_16;
+
+    /* The number of lines when reading the addresses repeatedly */
+    *(img_synthesizer->gr_flm5) = (uint32_t)VDC_REG_MASK_0X000007FF;
+    /* Number of lines in a frame */
+    *(img_synthesizer->gr_flm5) |= ((uint32_t)w_read_fb->in_vw - 1u) << VDC_REG_SHIFT_16;
+
+    *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC_REG_MASK_0XF7FF1C3F;
+    /* Format of the frame buffer read signal */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_format << VDC_REG_SHIFT_28;
+    /* Width of the horizontal valid period */
+    *(img_synthesizer->gr_flm6) |= ((uint32_t)w_read_fb->in_hw - 1u) << VDC_REG_SHIFT_16;
+    /* Swap setting in frame buffer reading */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_rdswa << VDC_REG_SHIFT_10;
+
+    if ((param->gr_flm_sel == VDC_GR_FLM_SEL_SCALE_DOWN) || (param->gr_flm_sel == VDC_GR_FLM_SEL_FLM_NUM))
+    {   /* Sets the amount of data to be skipped through */
+        *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, param->gr_format);
+    }
+
+    /* Graphics display mode */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+    if (graphics_id == VDC_GR_TYPE_GR0)
+    {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_DISPSEL_BACK;
+    }
+    else
+    {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_DISPSEL_LOWER;
+    }
+
+    /* Graphics display area */
+    *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc.vs << VDC_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc.vw;
+    *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc.hs << VDC_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc.hw;
+
+    /* Initialize alpha blending in a rectangular area */
+    if ((graphics_id == VDC_GR_TYPE_GR2) || (graphics_id == VDC_GR_TYPE_GR3))
+    {
+        /* Turns off alpha blending in a rectangular area */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X0000D000;
+        /* The valid image area for alpha blending in a rectangular area */
+        reg_data                   = *(img_synthesizer->gr_ab2);
+        *(img_synthesizer->gr_ab4) = reg_data;
+        reg_data                   = *(img_synthesizer->gr_ab3);
+        *(img_synthesizer->gr_ab5) = reg_data;
+        /* Disable fade-in and fade-out */
+        *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC_REG_MASK_0X01FF00FF;
+        /* Set the initial alpha value to '255' */
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC_REG_MASK_0X00FF0000;
+    }
+    /* Turns off  chroma-key processing */
+    *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC_REG_BIT0;
+
+    if (graphics_id == VDC_GR_TYPE_GR0)
+    {   /* Alpha value is set to 255. */
+        *(img_synthesizer->gr_ab10) |= (uint32_t)VDC_REG_ALPHA_8BIT;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)VDC_REG_ALPHA_8BIT;
+
+        /* Swapping of data read from buffer in the YCbCr422 format */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC_REG_MASK_0X0000E000;
+        if (param->gr_format == VDC_GR_FORMAT_YCBCR422)
+        {
+            *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_ycc_swap << VDC_REG_SHIFT_13;
+            /* The interpolation mode for YCC422 to YCbCr444 conversion is fixed to average interpolation */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC_REG_BIT8;
+        }
+        else
+        {   /* If the format of the frame buffer read signal is not YCbCr422,
+               initialize the swapping of data read from buffer in the YCbCr422 format. */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC_GR_YCCSWAP_CBY0CRY1 << VDC_REG_SHIFT_13;
+        }
+
+        color_space = VDC_ShrdPrmGetColorSpaceFbRd(graphics_id);
+
+        SetScalerBackgroundColor(color_space);
+        SetImgQaImproverColorMtx(color_space);
+
+        img_qlty_imp = &vdc_regaddr_img_qlty_imp;
+        /* Operating mode */
+        if (color_space == VDC_COLOR_SPACE_GBR)
+        {
+            *(img_qlty_imp->adj_enh_tim1) &= (uint32_t)~VDC_REG_BIT4;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_tim1) |= (uint32_t)VDC_REG_BIT4;
+        }
+        /* Register update control register (ADJx_UPDATE)
+           b0       ADJx_VEN */
+        *(img_qlty_imp->adj_update) |= (uint32_t)VDC_REG_BIT0;
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b8       GRx_UPDATE
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC_REG_BIT8 | VDC_REG_BIT4 | VDC_REG_BIT0);
+
+}   /* End of function VDC_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read change processing
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+******************************************************************************/
+void VDC_ChangeReadProcess (const vdc_graphics_type_t graphics_id, const vdc_read_chg_t * const param)
+{
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+    vdc_gr_flm_sel_t                       gr_flm_sel_tmp;
+    vdc_period_rect_t                    * gr_grc_tmp;
+    vdc_width_read_fb_t                  * w_read_fb;
+    vdc_onoff_t                            graphics_enlargement;
+    vdc_gr_format_t                        gr_format_tmp;
+
+    gr_flm_sel_tmp  = VDC_ShrdPrmGetSelFbAddrSig(graphics_id);
+    gr_grc_tmp      = VDC_ShrdPrmGetDisplayArea(graphics_id);
+    w_read_fb       = VDC_ShrdPrmGetFrBuffWidth_Rd(graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, gr_flm_sel_tmp, w_read_fb, gr_grc_tmp);
+
+    if (graphics_id == VDC_GR_TYPE_GR0)
+    {
+        SetScalerGraphics(graphics_id, w_read_fb, gr_grc_tmp, gr_flm_sel_tmp, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+    /* Frame buffer base address */
+    if (param->gr_base != NULL)
+    {
+        *(img_synthesizer->gr_flm2) = (uint32_t)(R_VDC_CPUVAddrToSysPAddr((uint32_t)param->gr_base) & (uint32_t)~VDC_REG_MASK_0X00000007);
+
+        if ((gr_flm_sel_tmp == VDC_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel_tmp == VDC_GR_FLM_SEL_FLM_NUM))
+        {
+            gr_format_tmp = VDC_ShrdPrmGetGraphicsFormat(graphics_id);
+            /* Sets the amount of data to be skipped through */
+            *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC_REG_MASK_0X0000003F;
+            *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, gr_format_tmp);
+        }
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL)
+    {
+        /* Number of lines in a frame */
+        *(img_synthesizer->gr_flm5) &= (uint32_t)~VDC_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm5) |= ((uint32_t)param->width_read_fb->in_vw - 1u) << VDC_REG_SHIFT_16;
+        /* Width of the horizontal valid period */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm6) |= ((uint32_t)param->width_read_fb->in_hw - 1u) << VDC_REG_SHIFT_16;
+    }
+
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL)
+    {
+        if (*(param->gr_disp_sel) != VDC_DISPSEL_IGNORED)
+        {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*(param->gr_disp_sel);
+        }
+    }
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL)
+    {
+        *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc->vs << VDC_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc->vw;
+        *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc->hs << VDC_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc->hw;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+}   /* End of function VDC_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read start processing
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      None
+******************************************************************************/
+void VDC_StartProcess (const vdc_layer_id_t layer_id, const vdc_start_t * const param)
+{
+    uint32_t                    layer_id_num;
+    vdc_resource_state_t       resource_state;
+
+    if (param->gr_disp_sel != NULL)
+    {   /* Set graphics display mode */
+        SetGraphicsDisplayMode(layer_id, param->gr_disp_sel);
+    }
+
+    if (layer_id != VDC_LAYER_ID_ALL)
+    {
+        rw_proc_function_tbl[layer_id](VDC_ON);
+    }
+    else
+    {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC_LAYER_ID_NUM; layer_id_num++)
+        {
+            resource_state = VDC_ShrdPrmGetRwProcReady((vdc_layer_id_t)layer_id_num);
+            if (resource_state != VDC_RESOURCE_ST_INVALID)
+            {
+                rw_proc_function_tbl[layer_id_num](VDC_ON);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(layer_id);
+}   /* End of function VDC_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read stop processing
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+void VDC_StopProcess (const vdc_layer_id_t layer_id)
+{
+    uint32_t                    layer_id_num;
+    vdc_resource_state_t       resource_state;
+
+    if (layer_id != VDC_LAYER_ID_ALL)
+    {
+        rw_proc_function_tbl[layer_id](VDC_OFF);
+    }
+    else
+    {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC_LAYER_ID_NUM; layer_id_num++)
+        {
+            resource_state = VDC_ShrdPrmGetRwProcEnabled((vdc_layer_id_t)layer_id_num);
+            if (resource_state != VDC_RESOURCE_ST_INVALID)
+            {
+                rw_proc_function_tbl[layer_id_num](VDC_OFF);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(layer_id);
+}   /* End of function VDC_StopProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for noise reduction
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_VideoNoiseReduction (const vdc_onoff_t nr1d_on, const vdc_noise_reduction_t * const param)
+{
+    const vdc_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc_nr_param_t             * nr_param;
+
+    input_ctrl = &vdc_regaddr_input_ctrl;
+
+    if (param != NULL)
+    {
+        /* Y/G signal noise reduction parameter */
+        nr_param = &param->y;
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC_REG_MASK_0X00007F33;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt0) |= nr_param->nr1d_th << VDC_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_tap << VDC_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_gain;
+
+        /* Cb/B signal noise reduction parameter */
+        nr_param = &param->cb;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1)  = nr_param->nr1d_th << VDC_REG_SHIFT_24;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC_REG_SHIFT_20;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain << VDC_REG_SHIFT_16;
+
+        /* Cr/R signal noise reduction parameter */
+        nr_param = &param->cr;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1) |= nr_param->nr1d_th << VDC_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain;
+    }
+
+    if (nr1d_on == VDC_OFF)
+    {
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC_REG_BIT16;
+    }
+    else
+    {
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC_REG_BIT16;
+    }
+
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC_REG_BIT0;
+
+}   /* End of function VDC_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for color matrix
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_ImageColorMatrix (const vdc_color_matrix_t * const param)
+{
+    SetColorMatrix(param->mtx_mode, param->offset, param->gain, &vdc_regaddr_color_matrix[param->module]);
+}   /* End of function VDC_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for image enhancement processing
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_ImageEnhancement (
+    const vdc_onoff_t                  shp_h_on,
+    const vdc_enhance_sharp_t  * const sharp_param,
+    const vdc_onoff_t                  lti_h_on,
+    const vdc_enhance_lti_t    * const lti_param,
+    const vdc_period_rect_t    * const enh_area)
+{
+    const vdc_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc_regaddr_img_qlty_imp;
+
+    /* Sharpness */
+    SetImageEnhancementSharpness(shp_h_on, sharp_param, img_qlty_imp);
+
+    /* LTI */
+    SetImageEnhancementLti(lti_h_on, lti_param, img_qlty_imp);
+
+    /* Enhancer area */
+    if (enh_area != NULL)
+    {
+        *(img_qlty_imp->adj_enh_tim2)  = (uint32_t)enh_area->vs << VDC_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim2) |= (uint32_t)enh_area->vw;
+        *(img_qlty_imp->adj_enh_tim3)  = (uint32_t)enh_area->hs << VDC_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim3) |= (uint32_t)enh_area->hw;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC_REG_BIT0;
+
+}   /* End of function VDC_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for black stretch
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_ImageBlackStretch (
+    const vdc_onoff_t          bkstr_on,
+    const vdc_black_t  * const param)
+{
+    const vdc_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc_regaddr_img_qlty_imp;
+
+    if (param != NULL)
+    {
+        /* Black stretch start point */
+        *(img_qlty_imp->adj_bkstr_set)  = (uint32_t)((uint32_t)param->bkstr_st << VDC_REG_SHIFT_20);
+        /* Black stretch depth */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_d << VDC_REG_SHIFT_16);
+        /* Black stretch time constant (T1) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_t1 << VDC_REG_SHIFT_8);
+        /* Black stretch time constant (T2) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)param->bkstr_t2;
+    }
+
+    if (bkstr_on == VDC_OFF)
+    {
+        *(img_qlty_imp->adj_bkstr_set) &= (uint32_t)~VDC_REG_BIT24;
+    }
+    else
+    {
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)VDC_REG_BIT24;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC_REG_BIT0;
+
+}   /* End of function VDC_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for alpha blending
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_AlphaBlending (const vdc_graphics_type_t graphics_id, const vdc_alpha_blending_t * const param)
+{
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+    /* Alpha signal of the ARGB1555/ARGB5551 format */
+    if (param->alpha_1bit != NULL)
+    {
+        *(img_synthesizer->gr_ab10) &= (uint32_t)~VDC_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab10) |= (uint32_t)param->alpha_1bit->gr_a0 << VDC_REG_SHIFT_24;
+        *(img_synthesizer->gr_ab11) &= (uint32_t)~VDC_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)param->alpha_1bit->gr_a1 << VDC_REG_SHIFT_24;
+    }
+
+    /* Premultiplication processing at alpha blending in one-pixel */
+    if (param->alpha_pixel != NULL)
+    {
+        if (param->alpha_pixel->gr_acalc_md == VDC_OFF)
+        {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_BIT14;
+        }
+        else
+        {
+            *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_REG_BIT14;
+        }
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC_REG_BIT4;
+
+}   /* End of function VDC_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for rectangle alpha blending
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      None
+******************************************************************************/
+void VDC_AlphaBlendingRect (
+    const vdc_graphics_type_t                  graphics_id,
+    const vdc_onoff_t                          gr_arc_on,
+    const vdc_alpha_blending_rect_t    * const param)
+{
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc_alpha_rect_t               * alpha_rect_tmp;
+    uint32_t                                arc_coef;
+
+    img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+    /* Alpha blending on/off control in a rectangular area */
+    if (gr_arc_on == VDC_OFF)
+    {
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_BIT12;
+    }
+    else
+    {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_REG_BIT12;
+    }
+
+    if (param != NULL)
+    {
+        /* Rectangular area subjected to alpha blending */
+        SetAlphaRectArea(param->gr_arc, img_synthesizer);
+
+        /* Alpha blending in a rectangular area */
+        alpha_rect_tmp = param->alpha_rect;
+        if (alpha_rect_tmp != NULL)
+        {
+            /* Multiplication processing with current alpha at alpha blending in a rectangular area (on/off) */
+            if (alpha_rect_tmp->gr_arc_mul == VDC_OFF)
+            {
+                *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_BIT15;
+            }
+            else
+            {
+                *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_REG_BIT15;
+            }
+            /* Alpha coefficient for alpha blending in a rectangular area (-255 to 255) */
+            if (alpha_rect_tmp->gr_arc_coef < 0)
+            {
+                arc_coef = (uint32_t)(alpha_rect_tmp->gr_arc_coef * (-1));  /* Conversion into absolute value */
+                /* Subtraction of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)VDC_REG_BIT24;
+            }
+            else
+            {
+                arc_coef = (uint32_t)alpha_rect_tmp->gr_arc_coef;
+                /* Addition of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)0x00000000u;
+            }
+            *(img_synthesizer->gr_ab6) |= arc_coef << VDC_REG_SHIFT_16;
+            /* Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+            *(img_synthesizer->gr_ab6) |= (uint32_t)alpha_rect_tmp->gr_arc_rate;
+            /* Initial alpha value for alpha blending in a rectangular area */
+            *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC_REG_MASK_0X00FF0000;
+            *(img_synthesizer->gr_ab7) |= (uint32_t)alpha_rect_tmp->gr_arc_def << VDC_REG_SHIFT_16;
+        }
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC_REG_BIT4;
+
+}   /* End of function VDC_AlphaBlendingRect() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma-key
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_Chromakey (
+    const vdc_graphics_type_t      graphics_id,
+    const vdc_onoff_t              gr_ck_on,
+    const vdc_chromakey_t  * const param)
+{
+    vdc_gr_format_t                        gr_format_tmp;
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+    if (param != NULL)
+    {
+        gr_format_tmp = VDC_ShrdPrmGetGraphicsFormat(graphics_id);
+        if ((gr_format_tmp == VDC_GR_FORMAT_CLUT1) ||
+            (gr_format_tmp == VDC_GR_FORMAT_CLUT4) ||
+            (gr_format_tmp == VDC_GR_FORMAT_CLUT8))
+        {
+            *(img_synthesizer->gr_ab8)  = (uint32_t)(param->ck_color << VDC_REG_SHIFT_24);
+            *(img_synthesizer->gr_ab9)  = ColorConversionIntoAgbr(param->rep_color);
+        }
+        else
+        {
+            /* Color conversion from gr_format_tmp into RGB888 format */
+            *(img_synthesizer->gr_ab8)  = ColorConversion(gr_format_tmp, param->ck_color);
+            *(img_synthesizer->gr_ab9)  = ColorConversion(gr_format_tmp, param->rep_color);
+        }
+        if (graphics_id == VDC_GR_TYPE_GR0)
+        {   /* Alpha value is set to 255. */
+            *(img_synthesizer->gr_ab9) |= (uint32_t)VDC_REG_ALPHA_8BIT;
+        }
+        else
+        {
+            *(img_synthesizer->gr_ab9) |= (uint32_t)param->rep_alpha << VDC_REG_SHIFT_24;
+        }
+    }
+
+    if (gr_ck_on == VDC_OFF)
+    {
+        *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC_REG_BIT0;
+    }
+    else
+    {
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC_REG_BIT0;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC_REG_BIT4;
+
+}   /* End of function VDC_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for CLUT
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_CLUT (const vdc_graphics_type_t graphics_id, const vdc_clut_t * const param)
+{
+    vdc_gr_format_t                        gr_format_tmp;
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+    gr_format_tmp = VDC_ShrdPrmGetGraphicsFormat(graphics_id);
+    if (gr_format_tmp == VDC_GR_FORMAT_CLUT1)
+    {
+        if (param->color_num == ((uint32_t)1u))
+        {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            if (graphics_id == VDC_GR_TYPE_GR0)
+            {   /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC_REG_ALPHA_8BIT;
+            }
+        }
+        else
+        {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            *(img_synthesizer->gr_ab11) = ColorConversionIntoAgbr(param->clut[1]);
+            if (graphics_id == VDC_GR_TYPE_GR0)
+            {   /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC_REG_ALPHA_8BIT;
+                *(img_synthesizer->gr_ab11) |= (uint32_t)VDC_REG_ALPHA_8BIT;
+            }
+        }
+    }
+    else        /* CLUT4 or CLUT8 */
+    {
+        Set_Clut(param, vdc_regaddr_clut[graphics_id]);
+        /* dummy read*/
+        {
+            volatile uint32_t wk = *(vdc_regaddr_clut[graphics_id]);
+        }
+        /* CLUT table control register (GRx_CLUT)
+           b16      GRx_CLT_SEL - CLUT table select signal - XOR, flip signal */
+        *(img_synthesizer->gr_clut) ^= (uint32_t)VDC_REG_BIT16;
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC_REG_BIT4;
+
+}   /* End of function VDC_CLUT() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display calibration
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      None
+******************************************************************************/
+void VDC_DisplayCalibration (const vdc_disp_calibration_t * const param)
+{
+    const vdc_calibr_bright_t        * bright_tmp;
+    const vdc_calibr_contrast_t      * contrast_tmp;
+    const vdc_calibr_dither_t        * panel_dither_tmp;
+    const vdc_regaddr_output_ctrl_t  * output_ctrl;
+
+    output_ctrl = &vdc_regaddr_output_ctrl;
+
+    /* Correction circuit sequence control */
+    if (param->route == VDC_CALIBR_ROUTE_BCG)
+    {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC_REG_BIT12;
+    }
+    else
+    {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC_REG_BIT12;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL)
+    {
+        *(output_ctrl->out_bright1)  = (uint32_t)bright_tmp->pbrt_g;
+        *(output_ctrl->out_bright2)  = (uint32_t)bright_tmp->pbrt_b << VDC_REG_SHIFT_16;
+        *(output_ctrl->out_bright2) |= (uint32_t)bright_tmp->pbrt_r;
+    }
+
+    /* Contrast (gain) adjustment */
+    contrast_tmp = param->contrast;
+    if (contrast_tmp != NULL)
+    {
+        *(output_ctrl->out_contrast)  = (uint32_t)contrast_tmp->cont_g << VDC_REG_SHIFT_16;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_b << VDC_REG_SHIFT_8;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_r;
+    }
+
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL)
+    {
+        *(output_ctrl->out_pdtha) &= (uint32_t)~VDC_REG_MASK_0X00300000;
+        *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_sel << VDC_REG_SHIFT_20;
+        if (panel_dither_tmp->pdth_sel == VDC_PDTH_MD_2X2)
+        {
+            *(output_ctrl->out_pdtha) &= (uint32_t)~VDC_REG_MASK_0X00003333;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pa << VDC_REG_SHIFT_12;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pb << VDC_REG_SHIFT_8;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pc << VDC_REG_SHIFT_4;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pd;
+        }
+    }
+
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC_REG_BIT0;
+
+}   /* End of function VDC_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for gamma correction
+ * @param[in]   gam_on      : Gamma correction ON/OFF setting
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC_GammaCorrection (const vdc_onoff_t gam_on, const vdc_gamma_correction_t * const param)
+{
+    const vdc_regaddr_gamma_t  * gamma;
+
+    gamma = &vdc_regaddr_gamma;
+
+    /* Gamma correction on/off control */
+    *(gamma->gam_sw) = (gam_on == VDC_OFF) ? 0x0000u : 0x0001u;
+
+    if (param != NULL)
+    {
+        /* Start threshold of area 1 to 31 of G signal */
+        Set_StartThreshold_Gamma(param->gam_g_th, gamma->gam_g_area);
+        /* Gain adjustment of area 0 to 31 of G signal */
+        Set_GainAdjustment_Gamma(param->gam_g_gain, gamma->gam_g_lut);
+        /* Register update control register G (GAM_G_UPDATE)
+           b0       GAM_G_VEN */
+        *(gamma->gam_g_update) |= (uint32_t)VDC_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of B signal */
+        Set_StartThreshold_Gamma(param->gam_b_th, gamma->gam_b_area);
+        /* Gain adjustment of area 0 to 31 of B signal */
+        Set_GainAdjustment_Gamma(param->gam_b_gain, gamma->gam_b_lut);
+        /* Register update control register B (GAM_B_UPDATE)
+           b0       GAM_B_VEN */
+        *(gamma->gam_b_update) |= (uint32_t)VDC_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of R signal */
+        Set_StartThreshold_Gamma(param->gam_r_th, gamma->gam_r_area);
+        /* Gain adjustment of area 0 to 31 of R signal */
+        Set_GainAdjustment_Gamma(param->gam_r_gain, gamma->gam_r_lut);
+        /* Register update control register R (GAM_R_UPDATE)
+           b0       GAM_R_VEN */
+        *(gamma->gam_r_update) |= (uint32_t)VDC_REG_BIT0;
+    }
+}   /* End of function VDC_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Sets external input video signal
+ * @param[in]   ext_sig_tmp             : External input signal parameter
+ * @param[in]   input_ctrl              : Input controller registers
+ * @retval      None
+******************************************************************************/
+static void SetVideoExternalInput (
+    const vdc_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc_regaddr_input_ctrl_t * const input_ctrl)
+{
+    *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC_REG_MASK_0X00007111;
+    /* External input format select */
+    if (ext_sig_tmp->inp_format == VDC_EXTIN_FORMAT_YCBCR444)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC_EXTIN_FORMAT_RGB888 << VDC_REG_SHIFT_12;
+    }
+    else
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)ext_sig_tmp->inp_format << VDC_REG_SHIFT_12;
+    }
+    /* Clock edge select for capturing external input video image signals */
+    if (ext_sig_tmp->inp_pxd_edge != VDC_EDGE_RISING)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC_REG_BIT8;
+    }
+    /* Clock edge select for capturing external input Vsync signals */
+    if (ext_sig_tmp->inp_vs_edge != VDC_EDGE_RISING)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC_REG_BIT4;
+    }
+    /* Clock edge select for capturing external input Hsync signals */
+    if (ext_sig_tmp->inp_hs_edge != VDC_EDGE_RISING)
+    {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC_REG_BIT0;
+    }
+
+    *(input_ctrl->inp_ext_sync_cnt) &= (uint32_t)~VDC_REG_MASK_0X11110113;
+    /* External input bit endian change on/off control */
+    if (ext_sig_tmp->inp_endian_on != VDC_OFF)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC_REG_BIT28;
+    }
+    /* External input B/R signal swap on/off control */
+    if (ext_sig_tmp->inp_swap_on != VDC_OFF)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC_REG_BIT24;
+    }
+    /* External input Vsync signal DV_VSYNC inversion control */
+    if (ext_sig_tmp->inp_vs_inv != VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC_REG_BIT20;
+    }
+    /* External input Hsync signal DV_HSYNC inversion control */
+    if (ext_sig_tmp->inp_hs_inv != VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC_REG_BIT16;
+    }
+    /* Reference select for external input BT.656 Hsync signal */
+    if (ext_sig_tmp->inp_h_edge_sel != VDC_EXTIN_REF_H_EAV)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC_REG_BIT8;
+    }
+    /* Number of lines for BT.656 external input */
+    if (ext_sig_tmp->inp_f525_625 != VDC_EXTIN_LINE_525)
+    {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC_REG_BIT4;
+    }
+    /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)ext_sig_tmp->inp_h_pos;
+}   /* End of function SetVideoExternalInput() */
+
+/**************************************************************************//**
+ * @brief       Initializes cascaded connection
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void SetInitialConnection (void)
+{
+    volatile uint32_t * vin_gr_update;
+    volatile uint32_t * vin_gr_ab1;
+
+    vin_gr_update   = (volatile uint32_t *) &VDC6.GR_VIN_UPDATE;
+    vin_gr_ab1      = (volatile uint32_t *) &VDC6.GR_VIN_AB1;
+
+    /* Selection of lower-layer plane in scaler: Selects graphics 0 as lower-layer graphics. */
+    *(vin_gr_ab1)  &= (uint32_t)~VDC_REG_BIT2;
+    /* Graphics display mode in VIN */
+    *(vin_gr_ab1)  &= (uint32_t)~VDC_REG_MASK_0X00000003;
+    *(vin_gr_ab1)  |= (uint32_t)VDC_DISPSEL_LOWER;
+    /* Graphics register update control register (GR_VIN_UPDATE)
+       b8       GR_VIN_UPDATE
+       b4       GR_VIN_P_VEN */
+    *(vin_gr_update) |= (uint32_t)(VDC_REG_BIT8|VDC_REG_BIT4);
+
+}   /* End of function SetInitialConnection() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for graphics
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void SetGrapicsBackgroundColor (void)
+{
+    uint32_t                bg_color_tmp;
+    uint32_t                bg_color_conv;
+    volatile uint32_t     * bg_color_reg;
+    volatile uint32_t     * update_reg;
+
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp = VDC_ShrdPrmGetBgColor(VDC_COLOR_SPACE_GBR);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC_REG_RGB_24BIT_MASK;
+
+    /* GR2, GR3 */
+    /* Background color in GBR format (GR2_BASE) */
+    bg_color_reg    = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR2].gr_base;
+    *bg_color_reg   = bg_color_conv;
+    /* Graphics register update control register (GR2_UPDATE)
+       b4       GR2_P_VEN */
+    update_reg      = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR2].gr_update;
+    *update_reg    |= (uint32_t)VDC_REG_BIT4;
+
+    /* Background color in GBR format (GR3_BASE) */
+    bg_color_reg    = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR3].gr_base;
+    *bg_color_reg   = bg_color_conv;
+    /* Graphics register update control register (GR3_UPDATE)
+       b4       GR3_P_VEN */
+    update_reg      = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR3].gr_update;
+    *update_reg    |= (uint32_t)VDC_REG_BIT4;
+}   /* End of function SetGrapicsBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for scaler 0 (graphics 0)
+ *
+ *              Description:<br>
+ *              This function should be called only when graphics 0 is selected.
+ * @param[in]   color_space         : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetScalerBackgroundColor (const vdc_color_space_t color_space)
+{
+    volatile uint32_t * scl0_update_reg;
+    volatile uint32_t * scl0_ovr1_reg;
+    volatile uint32_t * gr_base_reg;
+    volatile uint32_t * gr_update_reg;
+    uint32_t            bg_color_tmp;
+    uint32_t            bg_color_conv;
+
+    scl0_ovr1_reg   = vdc_regaddr_scaler.scl0_ovr1;
+    scl0_update_reg = vdc_regaddr_scaler.scl0_update;
+    gr_base_reg     = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR0].gr_base;
+    gr_update_reg   = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR0].gr_update;
+
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp    = VDC_ShrdPrmGetBgColor(color_space);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC_REG_RGB_24BIT_MASK;
+
+    /* Background color in RGB format or CrYCb format */
+    *scl0_ovr1_reg      = bg_color_tmp;
+    /* Register update control register
+       b4       SCL0_VEN_B */
+    *scl0_update_reg   |= (uint32_t)VDC_REG_BIT4;
+
+    /* Background color in GBR format or YCbCr format */
+    *gr_base_reg        = bg_color_conv;
+    /* Graphics register update control register
+       b4       GRx_P_VEN */
+    *gr_update_reg     |= (uint32_t)VDC_REG_BIT4;
+}   /* End of function SetScalerBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVA/VS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVA_VS (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stva1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stva1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_stva2) &= (uint32_t)~VDC_REG_BIT4;
+    }
+    else
+    {
+        *(output_ctrl->tcon_tim_stva2) |= (uint32_t)VDC_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVA_VS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVB/VE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVB_VE (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stvb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stvb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_stvb2) &= (uint32_t)~VDC_REG_BIT4;
+    }
+    else
+    {
+        *(output_ctrl->tcon_tim_stvb2) |= (uint32_t)VDC_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVB_VE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STH/HS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STH_HS (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_sth1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_sth1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_sth2) &= (uint32_t)~VDC_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STH_HS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STB/HE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STB_HE (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_stb2) &= (uint32_t)~VDC_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STB_HE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - CPV/GCK
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_CPV_GCK (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_cpv1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_cpv1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_cpv2) &= (uint32_t)~VDC_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_CPV_GCK() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLA
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLA (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_pola1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_pola1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_pola2) &= (uint32_t)~VDC_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_pola2) |= (uint32_t)lcd_tcon->tcon_md << VDC_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLA() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLB
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLB (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_polb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_polb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_polb2) &= (uint32_t)~VDC_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_polb2) |= (uint32_t)lcd_tcon->tcon_md << VDC_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC_LCD_TCON_REFSEL_HSYNC)
+    {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC_SIG_POL_NOT_INVERTED)
+    {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLB() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - DE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_DE (
+    const vdc_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Polarity inversion control of signal */
+    *(output_ctrl->tcon_tim_de) = (lcd_tcon->tcon_inv == VDC_SIG_POL_NOT_INVERTED) ? (uint32_t)0u : (uint32_t)1u;
+
+}   /* End of function SetLcdTcon_DE() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-down
+ * @param[in]   scldw_rot               : Scaling-down and rotation parameter
+ * @param[in]   res_inter               : Field operating mode select
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingDown (
+    const vdc_scalingdown_rot_t    * const scldw_rot,
+    const vdc_res_inter_t                  res_inter,
+    const vdc_regaddr_scaler_t     * const scaler)
+{
+    uint32_t    vw_before_scld;    /* Vertical width before scaling-down */
+    uint32_t    hw_before_scld;    /* Horizontal width before scaling-down */
+    uint32_t    vw_after_scld;     /* Vertical width after scaling-down */
+    uint32_t    hw_after_scld;     /* Horizontal width after scaling-down */
+    uint32_t    scaling_ratio;
+
+    vw_before_scld = (uint32_t)scldw_rot->res.vw;
+    hw_before_scld = (uint32_t)scldw_rot->res.hw;
+
+    vw_after_scld = (uint32_t)scldw_rot->res_out_vw;
+    hw_after_scld = (uint32_t)scldw_rot->res_out_hw;
+
+    /* Vertical scaling-down: ON, vertical scaling-up: OFF */
+    *(scaler->scl0_ds1) |= (uint32_t)VDC_REG_BIT4;
+    *(scaler->scl0_us1) &= (uint32_t)~VDC_REG_BIT4;
+    if (vw_before_scld > vw_after_scld)
+    {
+        scaling_ratio = CalcScalingRatio(vw_before_scld, vw_after_scld, scldw_rot->adj_sel, VDC_OFF);
+
+        *(scaler->scl0_ds6) = scaling_ratio;
+    }
+    else
+    {
+        *(scaler->scl0_ds6) = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    }
+
+    /* Horizontal scaling-down */
+    if (hw_before_scld > hw_after_scld)
+    {   /* ON */
+        *(scaler->scl0_ds1) |= (uint32_t)VDC_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(hw_before_scld, hw_after_scld, VDC_ON, VDC_ON);
+
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_ds4) |= scaling_ratio;
+    }
+    else
+    {   /* OFF */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    *(scaler->scl0_ds5) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+    *(scaler->scl0_us6) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+    if (res_inter != VDC_RES_INTER_PROGRESSIVE)
+    {   /* Top */
+        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE << VDC_REG_SHIFT_16;
+    }
+
+}   /* End of function SetScalingDown() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-up
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   adj_sel                 : Folding handling (on/off)
+ * @param[in]   ip_conversion           : IP conversion on/off
+ * @param[in]   res_ds_wr_md            : Frame buffer writing mode for image processing
+ * @param[in]   ln_off_dir              : Line offset address direction of the frame buffer
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingUp (
+    const vdc_width_read_fb_t  * const w_read_fb,
+    const vdc_period_rect_t    * const gr_grc,
+    const vdc_onoff_t                  adj_sel,
+    const vdc_onoff_t                  ip_conversion,
+    const vdc_wr_md_t                  res_ds_wr_md,
+    const vdc_gr_ln_off_dir_t          ln_off_dir,
+    const vdc_regaddr_scaler_t * const scaler)
+{
+    uint32_t            w_before_scl;       /* Width before scaling-up */
+    uint32_t            w_after_scl;        /* Width after scaling-up */
+    uint32_t            scaling_ratio;
+    vdc_onoff_t        vscl_up;            /* Vertical scaling-up */
+
+    vscl_up = VDC_OFF;
+
+    /* Vertical scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_vw;
+    w_after_scl     = (uint32_t)gr_grc->vw;
+    if (w_before_scl < w_after_scl)
+    {
+        /* Vertical scaling-down: OFF, vertical scaling-up: ON */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC_REG_BIT4;
+        *(scaler->scl0_us1) |= (uint32_t)VDC_REG_BIT4;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC_OFF);
+        *(scaler->scl0_ds6) = scaling_ratio;
+
+        vscl_up = VDC_ON;
+    }
+    else
+    {   /* Vertical scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC_REG_BIT4;
+    }
+
+    /* Horizontal scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_hw;
+    w_after_scl     = (uint32_t)gr_grc->hw;
+    if (w_before_scl < w_after_scl)
+    {   /* Horizontal scaling-up: ON */
+        *(scaler->scl0_us1) |= (uint32_t)VDC_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC_OFF);
+
+        *(scaler->scl0_us5) &= (uint32_t)~VDC_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_us5) |= scaling_ratio;
+    }
+    else
+    {   /* Horizontal scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    if (ip_conversion == VDC_OFF)
+    {
+        *(scaler->scl0_ds5) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+        *(scaler->scl0_us6) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+    }
+    else
+    {
+        if (vscl_up != VDC_OFF)
+        {
+            switch (res_ds_wr_md)
+            {
+                case VDC_WR_MD_ROT_90DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                    /* US_HB */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE;
+                break;
+                case VDC_WR_MD_ROT_180DEG:
+                    if (ln_off_dir == VDC_GR_LN_OFF_DIR_INC)
+                    {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                break;
+                case VDC_WR_MD_ROT_270DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                    /* US_HT */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE << VDC_REG_SHIFT_16;
+                break;
+                default:    /* Normal or horizontal mirroring */
+                    if (ln_off_dir == VDC_GR_LN_OFF_DIR_DEC)
+                    {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                break;
+            }
+        }
+    }
+}   /* End of function SetScalingUp() */
+
+/**************************************************************************//**
+ * @brief       Calculates scaling ratio
+ *
+ *              Description:<br>
+ *              In this function, the overflow in calculation is not considered.
+ *              before_scl and after_scl are 11bit width, so the overflow does not occur.
+ * @param[in]   before_scl              : Size before scaling
+ * @param[in]   after_scl               : Size after scaling
+ * @param[in]   adj_sel                 : Handling for lack of last-input pixel/line, or folding handling
+ * @param[in]   round_up                : Round-up on/off
+ * @retval      Scaling ratio
+******************************************************************************/
+static uint32_t CalcScalingRatio (
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc_onoff_t  adj_sel,
+    const vdc_onoff_t  round_up)
+{
+    float32_t   ratio;
+    float32_t   sigma;
+    int32_t     ratio_int;
+    uint32_t    scaling_ratio;
+
+    /* When parameter checking is not performed,
+       following checks are necessary to avoid a division by zero exception and a negative number. */
+    if ((after_scl == 0u) || (after_scl == 1u))
+    {
+        scaling_ratio = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    }
+    else
+    {
+        /* ratio = before_scl * 4096.0 / after_scl */
+        ratio  = (float32_t)before_scl * (float32_t)SCALING_RATIO_SAME_SIZE;
+        ratio /= (float32_t)after_scl;
+
+        if (adj_sel != VDC_OFF)
+        {
+            sigma  = ratio * ((float32_t)after_scl - (float32_t)VDC_REG_FLOAT_1_0);
+            sigma -= ((float32_t)before_scl - (float32_t)VDC_REG_FLOAT_1_0) * (float32_t)SCALING_RATIO_SAME_SIZE;
+            sigma /= ((float32_t)after_scl - (float32_t)VDC_REG_FLOAT_1_0);
+            ratio -= sigma;
+        }
+
+        if (round_up == VDC_OFF)
+        {   /* Round off */
+            ratio    += (float32_t)VDC_REG_FLOAT_0_5;
+            ratio_int = (int32_t)ratio;
+        }
+        else
+        {   /* Round up */
+            ratio_int = (int32_t)ratio;
+            if ((float32_t)ratio_int < ratio)
+            {
+                ratio_int++;
+            }
+        }
+        scaling_ratio = (uint32_t)ratio_int;
+    }
+    return scaling_ratio;
+}   /* End of function CalcScalingRatio() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the input controller
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void SetInputCntrlColorMtx (void)
+{
+    vdc_color_space_t      color_space_input;
+    vdc_color_space_t      color_space_fb;
+    vdc_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    color_space_input   = VDC_ShrdPrmGetColorSpace();
+    color_space_fb      = VDC_ShrdPrmGetColorSpaceFbWr();
+    /* Color matrix operating mode */
+    if (color_space_input == VDC_COLOR_SPACE_GBR)
+    {
+        if (color_space_fb == VDC_COLOR_SPACE_GBR)
+        {   /* GBR to GBR */
+            mtx_mode_tmp = VDC_COLORMTX_GBR_GBR;
+        }
+        else
+        {   /* GBR to YCbCr */
+            mtx_mode_tmp = VDC_COLORMTX_GBR_YCBCR;
+        }
+    }
+    else
+    {
+        if (color_space_fb == VDC_COLOR_SPACE_GBR)
+        {   /* YCbCr to GBR */
+            mtx_mode_tmp = VDC_COLORMTX_YCBCR_GBR;
+        }
+        else
+        {   /* YCbCr to YCbCr */
+            mtx_mode_tmp = VDC_COLORMTX_YCBCR_YCBCR;
+        }
+    }
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc_regaddr_color_matrix[VDC_COLORMTX_IMGCNT]);
+
+}   /* End of function SetInputCntrlColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Confirms whether the graphics enlargement will occur or not
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @retval      Graphics enlargement on/off
+******************************************************************************/
+static vdc_onoff_t ConfirmGraphicsEnlargement (
+    const vdc_graphics_type_t          graphics_id,
+    const vdc_gr_flm_sel_t             gr_flm_sel,
+    const vdc_width_read_fb_t  * const w_read_fb,
+    const vdc_period_rect_t    * const gr_grc)
+{
+    vdc_onoff_t graphics_enlargement;
+
+    graphics_enlargement = VDC_OFF;
+    if (gr_flm_sel == VDC_GR_FLM_SEL_FLM_NUM)
+    {
+        if (graphics_id == VDC_GR_TYPE_GR0)
+        {
+            if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) ||
+                ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw))
+            {
+                graphics_enlargement = VDC_ON;
+            }
+        }
+    }
+    else
+    {
+        if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) || ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw))
+        {
+            graphics_enlargement = VDC_ON;
+        }
+    }
+    return graphics_enlargement;
+}   /* End of function ConfirmGraphicsEnlargement() */
+
+/**************************************************************************//**
+ * @brief       Sets scaler for graphics
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void SetScalerGraphics (
+    const vdc_graphics_type_t          graphics_id,
+    const vdc_width_read_fb_t  * const w_read_fb,
+    const vdc_period_rect_t    * const gr_grc,
+    const vdc_gr_flm_sel_t             gr_flm_sel,
+    const vdc_onoff_t                  gr_enlarge)
+{
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc_regaddr_scaler_t           * scaler;
+    vdc_res_inter_t                        res_inter_tmp;
+    vdc_wr_md_t                            res_ds_wr_md_tmp;
+    vdc_onoff_t                            adj_sel_tmp;
+    vdc_onoff_t                            ip_conversion;
+    uint32_t                                reg_data;
+    vdc_gr_ln_off_dir_t                    ln_off_dir;
+
+    scaler = &vdc_regaddr_scaler;
+
+    if ((gr_flm_sel == VDC_GR_FLM_SEL_FLM_NUM) && (gr_enlarge == VDC_OFF))
+    {   /* Normal graphics display */
+        /* Sync signals from the graphics processing block */
+        *(scaler->scl0_us8) |= (uint32_t)VDC_REG_BIT4;
+
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b4       SCL0_VEN_B */
+        *(scaler->scl0_update) |= (uint32_t)(VDC_REG_BIT13 | VDC_REG_BIT4);
+    }
+    else
+    {   /* Video image or graphics enlargement */
+        /* Sync signals from the scaling-up control block */
+        *(scaler->scl0_us8) &= (uint32_t)~VDC_REG_BIT4;
+
+        /* Graphics display area */
+        *(scaler->scl0_us2)  = (uint32_t)gr_grc->vs << VDC_REG_SHIFT_16;
+        *(scaler->scl0_us2) |= (uint32_t)gr_grc->vw;
+        *(scaler->scl0_us3)  = (uint32_t)gr_grc->hs << VDC_REG_SHIFT_16;
+        *(scaler->scl0_us3) |= (uint32_t)gr_grc->hw;
+
+        *(scaler->scl0_us4)  = (uint32_t)w_read_fb->in_vw << VDC_REG_SHIFT_16;
+        *(scaler->scl0_us4) |= (uint32_t)w_read_fb->in_hw;
+
+        res_ds_wr_md_tmp    = VDC_ShrdPrmGetWritingMode();
+        adj_sel_tmp         = VDC_ShrdPrmGetMeasureFolding(graphics_id);
+        ip_conversion       = VDC_OFF;
+        if ((gr_flm_sel == VDC_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel == VDC_GR_FLM_SEL_POINTER_BUFF))
+        {
+            res_inter_tmp = VDC_ShrdPrmGetInterlace();
+            if (res_inter_tmp != VDC_RES_INTER_PROGRESSIVE)
+            {
+                ip_conversion = VDC_ON;
+            }
+        }
+
+        ln_off_dir = VDC_ShrdPrmGetLineOfsAddrDir(graphics_id);
+        /* Scaling-up */
+        SetScalingUp(w_read_fb, gr_grc, adj_sel_tmp, ip_conversion, res_ds_wr_md_tmp, ln_off_dir, scaler);
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b8       SCL0_UPDATE
+           b4       SCL0_VEN_B
+           b0       SCL0_VEN_A */
+        *(scaler->scl0_update) |= (uint32_t)(VDC_REG_BIT13 | VDC_REG_BIT8 | VDC_REG_BIT4 | VDC_REG_BIT0);
+    }
+
+    if (gr_flm_sel != VDC_GR_FLM_SEL_FLM_NUM)
+    {
+        img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+        /* Frame buffer frame offset address */
+        reg_data                    = *(scaler->scl1_wr4);
+        *(img_synthesizer->gr_flm4) = reg_data;
+
+        /* Graphics register update control register (GRx_UPDATE)
+           b0       GRx_IBUS_VEN */
+        *(img_synthesizer->gr_update) |= (uint32_t)VDC_REG_BIT0;
+    }
+}   /* End of function SetScalerGraphics() */
+
+/**************************************************************************//**
+ * @brief       Gets the amount of data to be skipped through
+ * @param[in]   gr_base                 : Frame buffer base address
+ * @param[in]   gr_format               : Graphics format
+ * @retval      The amount of data to be skipped through
+******************************************************************************/
+static uint32_t DisplayStartPixelSetting (const uint32_t gr_base, const vdc_gr_format_t gr_format)
+{
+    uint32_t                gr_sta_pos;
+    static const uint32_t   bits_per_pixel[VDC_GR_FORMAT_NUM] =
+    {
+        VDC_REG_BIT_PER_PIXEL_RGB565,         /* RGB565 */
+        VDC_REG_BIT_PER_PIXEL_RGB888,         /* RGB888 */
+        VDC_REG_BIT_PER_PIXEL_ARGB1555,       /* ARGB1555 */
+        VDC_REG_BIT_PER_PIXEL_ARGB4444,       /* ARGB4444 */
+        VDC_REG_BIT_PER_PIXEL_ARGB8888,       /* ARGB8888 */
+        VDC_REG_BIT_PER_PIXEL_CLUT8,          /* CLUT8 */
+        VDC_REG_BIT_PER_PIXEL_CLUT4,          /* CLUT4 */
+        VDC_REG_BIT_PER_PIXEL_CLUT1,          /* CLUT1 */
+        VDC_REG_BIT_PER_PIXEL_YCBCR422,       /* YCbCr422: In the YCbCr422 format, 32 bits are used for two pixels. */
+        VDC_REG_BIT_PER_PIXEL_YCBCR444,       /* YCbCr444 */
+        VDC_REG_BIT_PER_PIXEL_RGBA5551,       /* RGBA5551 */
+        VDC_REG_BIT_PER_PIXEL_RGBA8888        /* RGBA8888 */
+    };
+
+    gr_sta_pos  = gr_base & (uint32_t)VDC_REG_MASK_0X00000007;
+    gr_sta_pos *= (uint32_t)VDC_REG_BIT_PER_PIXEL_VALUE_8;
+    gr_sta_pos /= bits_per_pixel[gr_format];
+    gr_sta_pos &= (uint32_t)VDC_REG_MASK_0X0000003F;
+
+    return gr_sta_pos;
+}   /* End of function DisplayStartPixelSetting() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the image quality improver
+ * @param[in]   color_space             : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetImgQaImproverColorMtx (const vdc_color_space_t color_space)
+{
+    vdc_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    /* Color matrix operating mode */
+    if (color_space == VDC_COLOR_SPACE_GBR)
+    {
+        mtx_mode_tmp = VDC_COLORMTX_GBR_GBR;
+    }
+    else
+    {
+        mtx_mode_tmp = VDC_COLORMTX_YCBCR_GBR;
+    }
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc_regaddr_color_matrix[VDC_COLORMTX_ADJ_0]);
+
+}   /* End of function SetImgQaImproverColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for scaler 0
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_0 (const vdc_onoff_t ability)
+{
+    const vdc_regaddr_scaler_t   * scaler;
+    volatile uint32_t               dummy_read;
+    uint32_t                        reg_data;
+
+    /* SC0/GR0 writing */
+    scaler = &vdc_regaddr_scaler;
+
+    if (ability == VDC_OFF)
+    {   /* SC0 frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC_REG_BIT0;
+
+        VDC_ShrdPrmSetRwProcDisable(VDC_LAYER_ID_0_WR);
+    }
+    else
+    {   /* SC0 frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC_REG_BIT0;
+        /* Reset and reset cancellation of the pointer buffer with dummy read */
+        *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+
+        /* Register update control register (SCx_SCL1_UPDATE)
+           b20      SCL1_UPDATE_B */
+        *(scaler->scl1_update) |= (uint32_t)VDC_REG_BIT20;
+
+        *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+
+        VDC_ShrdPrmSetRwProcEnable(VDC_LAYER_ID_0_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 0
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_0 (const vdc_onoff_t ability)
+{
+    const vdc_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* SC0/GR0 reading */
+    img_synthesizer = &vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR0];
+
+    if (ability == VDC_OFF)
+    {   /* GR0 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_DISPSEL_BACK;
+
+        VDC_ShrdPrmSetRwProcDisable(VDC_LAYER_ID_0_RD);
+    }
+    else
+    {   /* GR0 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC_REG_BIT0;
+
+        VDC_ShrdPrmSetRwProcEnable(VDC_LAYER_ID_0_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 2
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_2 (const vdc_onoff_t ability)
+{
+    const vdc_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR2 reading */
+    img_synthesizer = &vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR2];
+
+    if (ability == VDC_OFF)
+    {   /* GR2 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_DISPSEL_LOWER;
+
+        VDC_ShrdPrmSetRwProcDisable(VDC_LAYER_ID_2_RD);
+    }
+    else
+    {   /* GR2 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC_REG_BIT0;
+
+        VDC_ShrdPrmSetRwProcEnable(VDC_LAYER_ID_2_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_2() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 3
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_3 (const vdc_onoff_t ability)
+{
+    const vdc_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR3 reading */
+    img_synthesizer = &vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR3];
+
+    if (ability == VDC_OFF)
+    {   /* GR3 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC_DISPSEL_LOWER;
+
+        VDC_ShrdPrmSetRwProcDisable(VDC_LAYER_ID_3_RD);
+    }
+    else
+    {   /* GR3 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC_REG_BIT0;
+
+        VDC_ShrdPrmSetRwProcEnable(VDC_LAYER_ID_3_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_3() */
+
+/**************************************************************************//**
+ * @brief       Sets register update control register to update the frame buffer
+ *              read and write enable settings.
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+static void SetRegUpdateRwEnable (const vdc_layer_id_t layer_id)
+{
+    volatile uint32_t * scl1_update_reg;
+    volatile uint32_t * gr_update_reg;
+
+    switch (layer_id)
+    {
+        case VDC_LAYER_ID_0_WR:        /* Layer 0, write process */
+            scl1_update_reg   = vdc_regaddr_scaler.scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC_REG_BIT20 | VDC_REG_BIT4 | VDC_REG_BIT0);
+        break;
+        case VDC_LAYER_ID_0_RD:        /* Layer 0, read process */
+            gr_update_reg   = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+        break;
+        case VDC_LAYER_ID_2_RD:        /* Layer 2, read process */
+            gr_update_reg   = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+        break;
+        case VDC_LAYER_ID_3_RD:        /* Layer 3, read process */
+            gr_update_reg   = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+        break;
+
+        case VDC_LAYER_ID_ALL:         /* All */
+            /* Register update control register (SCx_SCL1_UPDATE)
+               b20      SCL1_UPDATE_B
+               b4       SCL1_VEN_B
+               b0       SCL1_VEN_A */
+            scl1_update_reg   = vdc_regaddr_scaler.scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC_REG_BIT20 | VDC_REG_BIT4 | VDC_REG_BIT0);
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN
+               b0       GRx_IBUS_VEN */
+            gr_update_reg   = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+            gr_update_reg   = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+            gr_update_reg   = vdc_regaddr_img_synthesizer[VDC_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC_REG_BIT4|VDC_REG_BIT0);
+        break;
+
+        default:
+            /* DO NOTHING */
+        break;
+    }
+}   /* End of function SetRegUpdateRwEnable() */
+
+/**************************************************************************//**
+ * @brief       Sets graphics display mode
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   gr_disp_sel             : Graphics display mode
+ * @retval      None
+******************************************************************************/
+static void SetGraphicsDisplayMode (const vdc_layer_id_t layer_id, const vdc_gr_disp_sel_t * const gr_disp_sel)
+{
+    uint32_t                                graphics_id;
+    const vdc_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    if (layer_id == VDC_LAYER_ID_ALL)
+    {
+        for (graphics_id = 0; graphics_id < VDC_GR_TYPE_NUM; graphics_id++)
+        {
+            if (gr_disp_sel[graphics_id] != VDC_DISPSEL_IGNORED)
+            {
+                img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+                *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+                *(img_synthesizer->gr_ab1) |= (uint32_t)gr_disp_sel[graphics_id];
+                /* Graphics register update control register (GRx_UPDATE)
+                   b4       GRx_P_VEN */
+                *(img_synthesizer->gr_update) |= (uint32_t)VDC_REG_BIT4;
+            }
+        }
+    }
+    else if ((layer_id == VDC_LAYER_ID_0_RD) || (layer_id == VDC_LAYER_ID_2_RD) || (layer_id == VDC_LAYER_ID_3_RD))
+    {
+        if (*gr_disp_sel != VDC_DISPSEL_IGNORED)
+        {
+            graphics_id = (uint32_t)(layer_id - VDC_SC_TYPE_NUM);
+
+            img_synthesizer = &vdc_regaddr_img_synthesizer[graphics_id];
+
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*gr_disp_sel;
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN */
+            *(img_synthesizer->gr_update) |= (uint32_t)VDC_REG_BIT4;
+        }
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}   /* End of function SetGraphicsDisplayMode() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix
+ * @param[in]   mtx_mode                : Operating mode
+ * @param[in]   offset                  : Offset (DC) adjustment of Y/G, B, and R signal
+ * @param[in]   gain                    : GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment
+ * @param[in]   color_matrix            : Color matrix registers
+ * @retval      None
+******************************************************************************/
+static void SetColorMatrix (
+    const vdc_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc_regaddr_color_matrix_t   * const color_matrix)
+{
+    /* Operating mode */
+    *(color_matrix->mtx_mode) = (uint32_t)mtx_mode;
+
+    /* Offset (DC) adjustment of Y/G, B, and R signal and
+       GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    *(color_matrix->mtx_yg_adj0)    = (uint32_t)offset[VDC_COLORMTX_OFFST_YG] << VDC_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj0)   |= (uint32_t)gain[VDC_COLORMTX_GAIN_GG];
+    *(color_matrix->mtx_yg_adj1)    = (uint32_t)gain[VDC_COLORMTX_GAIN_GB] << VDC_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj1)   |= (uint32_t)gain[VDC_COLORMTX_GAIN_GR];
+    *(color_matrix->mtx_cbb_adj0)   = (uint32_t)offset[VDC_COLORMTX_OFFST_B] << VDC_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj0)  |= (uint32_t)gain[VDC_COLORMTX_GAIN_BG];
+    *(color_matrix->mtx_cbb_adj1)   = (uint32_t)gain[VDC_COLORMTX_GAIN_BB] << VDC_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj1)  |= (uint32_t)gain[VDC_COLORMTX_GAIN_BR];
+    *(color_matrix->mtx_crr_adj0)   = (uint32_t)offset[VDC_COLORMTX_OFFST_R] << VDC_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj0)  |= (uint32_t)gain[VDC_COLORMTX_GAIN_RG];
+    *(color_matrix->mtx_crr_adj1)   = (uint32_t)gain[VDC_COLORMTX_GAIN_RB] << VDC_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj1)  |= (uint32_t)gain[VDC_COLORMTX_GAIN_RR];
+
+    /* Register update control register (IMGCNT_UPDATE/ADJx_UPDATE)
+       b0       IMGCNT_VEN/ADJx_VEN */
+    *(color_matrix->mtx_update) |= (uint32_t)VDC_REG_BIT0;
+
+}   /* End of function SetColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets sharpness
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness ON/OFF setting
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementSharpness (
+    const vdc_onoff_t                          shp_h_on,
+    const vdc_enhance_sharp_t          * const sharp_param,
+    const vdc_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc_sharpness_ctrl_t * sharpness_ctrl;
+
+    if (sharp_param != NULL)
+    {
+        /* H1, adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC_IMGENH_SHARP_H1];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC_REG_MASK_0X0000003F;
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp2)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H2, second adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC_IMGENH_SHARP_H2];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (sharp_param->shp_h2_lpf_sel == VDC_OFF)
+        {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)0x00000000u;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)VDC_REG_BIT16;
+        }
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp3) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp4)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H3, third adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC_IMGENH_SHARP_H3];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp5) = (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp6)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+    }
+
+    if (shp_h_on == VDC_OFF)
+    {
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC_REG_BIT16;
+    }
+    else
+    {
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)VDC_REG_BIT16;
+    }
+}   /* End of function SetImageEnhancementSharpness() */
+
+/**************************************************************************//**
+ * @brief       Sets LTI
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementLti (
+    const vdc_onoff_t                          lti_h_on,
+    const vdc_enhance_lti_t            * const lti_param,
+    const vdc_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc_lti_ctrl_t * lti_ctrl;
+
+    if (lti_param != NULL)
+    {
+        /* H2, second adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC_IMGENH_LTI1];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (lti_param->lti_h2_lpf_sel == VDC_OFF)
+        {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)0x00000000u;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)VDC_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)lti_ctrl->lti_core;
+
+        /* H4, fourth adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC_IMGENH_LTI2];
+        /* Median filter reference pixel select */
+        if (lti_param->lti_h4_median_tap_sel == VDC_LTI_MDFIL_SEL_ADJ2)
+        {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)0x00000000u;
+        }
+        else
+        {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)VDC_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)lti_ctrl->lti_core;
+    }
+
+    if (lti_h_on == VDC_OFF)
+    {
+        *(img_qlty_imp->adj_enh_lti1) &= (uint32_t)~VDC_REG_BIT31;
+    }
+    else
+    {
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)VDC_REG_BIT31;
+    }
+}   /* End of function SetImageEnhancementLti() */
+
+/**************************************************************************//**
+ * @brief       Sets alpha blending area of a rectangle
+ * @param[in]   pd_disp_rect        : Rectangular area for alpha blending
+ * @param[in]   img_synthesizer     : Image synthesizer registers
+ * @retval      None
+******************************************************************************/
+static void SetAlphaRectArea (
+    const vdc_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc_regaddr_img_synthesizer_t    * const img_synthesizer)
+{
+    uint32_t v_start;
+    uint32_t h_start;
+
+    if (pd_disp_rect != NULL)
+    {
+        v_start = *(img_synthesizer->gr_ab2) >> VDC_REG_SHIFT_16;
+        h_start = *(img_synthesizer->gr_ab3) >> VDC_REG_SHIFT_16;
+
+        v_start += (uint32_t)pd_disp_rect->vs_rel;
+        h_start += (uint32_t)pd_disp_rect->hs_rel;
+        /* If the start position exceeds the maximum bit width, the value should be saturated. */
+        if ((v_start & (uint32_t)~VDC_REG_MASK_0X000007FF) != 0u)
+        {
+            v_start = (uint32_t)VDC_REG_MASK_0X000007FF;
+        }
+        if ((h_start & (uint32_t)~VDC_REG_MASK_0X000007FF) != 0u)
+        {
+            h_start = (uint32_t)VDC_REG_MASK_0X000007FF;
+        }
+
+        *(img_synthesizer->gr_ab4) = (v_start << VDC_REG_SHIFT_16) | (uint32_t)pd_disp_rect->vw_rel;
+        *(img_synthesizer->gr_ab5) = (h_start << VDC_REG_SHIFT_16) | (uint32_t)pd_disp_rect->hw_rel;
+    }
+}   /* End of function SetAlphaRectArea() */
+
+/**************************************************************************//**
+ * @brief       Converts the color format from gr_format format into 24-bit RGB888 format
+ * @param[in]   gr_format           : Color format
+ * @param[in]   input_color         : Color data
+ * @retval      RGB888 color data
+******************************************************************************/
+static uint32_t ColorConversion (const vdc_gr_format_t gr_format, const uint32_t input_color)
+{
+    uint32_t red;
+    uint32_t green;
+    uint32_t blue;
+    uint32_t conv_color;
+
+    conv_color = 0;
+    switch (gr_format)
+    {
+        case VDC_GR_FORMAT_RGB565:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC_REG_RGB565_R_MASK) >> VDC_REG_SHIFT_11));
+            green = ColorConversionFrom6to8((uint32_t)((input_color & VDC_REG_RGB565_G_MASK) >> VDC_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC_REG_RGB565_B_MASK));
+            conv_color = (green << VDC_REG_SHIFT_16) | (blue << VDC_REG_SHIFT_8) | red;
+        break;
+        case VDC_GR_FORMAT_RGB888:
+            conv_color = ColorConversionIntoAgbr(input_color);
+        break;
+        case VDC_GR_FORMAT_ARGB1555:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC_REG_ARGB1555_R_MASK) >> VDC_REG_SHIFT_10));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC_REG_ARGB1555_G_MASK) >> VDC_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC_REG_ARGB1555_B_MASK));
+            conv_color = (green << VDC_REG_SHIFT_16) | (blue << VDC_REG_SHIFT_8) | red;
+        break;
+        case VDC_GR_FORMAT_ARGB4444:
+            red   = ColorConversionFrom4to8((uint32_t)((input_color & VDC_REG_ARGB4444_R_MASK) >> VDC_REG_SHIFT_8));
+            green = ColorConversionFrom4to8((uint32_t)((input_color & VDC_REG_ARGB4444_G_MASK) >> VDC_REG_SHIFT_4));
+            blue  = ColorConversionFrom4to8((uint32_t)(input_color & VDC_REG_ARGB4444_B_MASK));
+            conv_color = (green << VDC_REG_SHIFT_16) | (blue << VDC_REG_SHIFT_8) | red;
+        break;
+        case VDC_GR_FORMAT_ARGB8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)(input_color & VDC_REG_RGB_24BIT_MASK));
+        break;
+        case VDC_GR_FORMAT_RGBA5551:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC_REG_RGBA5551_R_MASK) >> VDC_REG_SHIFT_11));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC_REG_RGBA5551_G_MASK) >> VDC_REG_SHIFT_6));
+            blue  = ColorConversionFrom5to8((uint32_t)((input_color & VDC_REG_RGBA5551_B_MASK) >> VDC_REG_SHIFT_1));
+            conv_color = (green << VDC_REG_SHIFT_16) | (blue << VDC_REG_SHIFT_8) | red;
+        break;
+        case VDC_GR_FORMAT_RGBA8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)((input_color >> VDC_REG_SHIFT_8) & VDC_REG_RGB_24BIT_MASK));
+        break;
+        default:
+            /* DO NOTHING */
+        break;
+    }
+    return conv_color;
+}   /* End of function ColorConversion() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 4 bits value into 8 bits value
+ * @param[in]   color_value         : 4-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom4to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC_REG_COLOR_4BIT_MASK;
+    color *= (uint32_t)VDC_REG_EXTENSION_VALUE_17;
+
+    return color;
+}   /* End of function ColorConversionFrom4to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 5 bits value into 8 bits value
+ * @param[in]   color_value         : 5-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom5to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC_REG_COLOR_5BIT_MASK;
+    color *= (uint32_t)(VDC_REG_EXTENSION_VALUE_263 * VDC_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC_REG_EXTENSION_VALUE_32;
+    /* Round off */
+    color += (uint32_t)VDC_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom5to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 6 bits value into 8 bits value
+ * @param[in]   color_value         : 6-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom6to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC_REG_COLOR_6BIT_MASK;
+    color *= (uint32_t)(VDC_REG_EXTENSION_VALUE_259 * VDC_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC_REG_EXTENSION_VALUE_64;
+    /* Round off */
+    color += (uint32_t)VDC_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom6to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from ARGB8888 format into AGBR8888 format
+ * @param[in]   color_value         : ARGB8888 color data
+ * @retval      AGBR8888 color data
+******************************************************************************/
+static uint32_t ColorConversionIntoAgbr (const uint32_t color_value)
+{
+    uint32_t color_bgr;
+    uint32_t color_dat;
+
+    /* Green and blue */
+    color_bgr   = (uint32_t)(color_value << VDC_REG_SHIFT_8);
+    color_bgr  &= (uint32_t)VDC_REG_ARGB8888_GB_MASK;
+    /* Alpha */
+    color_dat   = (uint32_t)(color_value & VDC_REG_ALPHA_8BIT);
+    color_bgr  |= color_dat;
+    /* Red */
+    color_dat   = (uint32_t)((color_value >> VDC_REG_SHIFT_16) & VDC_REG_COLOR_8BIT_MASK);
+    color_bgr  |= color_dat;
+
+    return color_bgr;
+}   /* End of function ColorConversionIntoAgbr() */
+
+/**************************************************************************//**
+ * @brief       Sets color lookup table (CLUT)
+ * @param[in]   param               : CLUT parameter
+ * @param[out]  regaddr_clut        : CLUT register top address
+ * @retval      None
+******************************************************************************/
+static void Set_Clut (const vdc_clut_t * const param, volatile uint32_t * regaddr_clut)
+{
+    uint32_t            data_len;
+    const uint32_t    * clut_tmp;
+
+    clut_tmp = param->clut;
+    for (data_len = 0; data_len < param->color_num; data_len++)
+    {
+        *regaddr_clut = *clut_tmp;
+        regaddr_clut++;
+        clut_tmp++;
+    }
+}   /* End of function Set_Clut() */
+
+/**************************************************************************//**
+ * @brief       Sets start threshold for gamma correction
+ * @param[in]   gam_th          : Start threshold of area 1 to 31
+ * @param[out]  gam_area        : Gamma correction registers for start threshold
+ * @retval      None
+******************************************************************************/
+static void Set_StartThreshold_Gamma (const uint8_t * gam_th, volatile uint32_t * const * const gam_area)
+{
+    uint32_t reg_index;
+
+    if (gam_th != NULL)
+    {
+        *(gam_area[0])  = (uint32_t)*gam_th << VDC_REG_SHIFT_16;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th << VDC_REG_SHIFT_8;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th;
+        gam_th++;
+
+        for (reg_index = 1; reg_index < VDC_GAM_AREA_REG_NUM; reg_index++)
+        {
+            *(gam_area[reg_index])  = (uint32_t)*gam_th << VDC_REG_SHIFT_24;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC_REG_SHIFT_16;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC_REG_SHIFT_8;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th;
+            gam_th++;
+        }
+    }
+}   /* End of function Set_StartThreshold_Gamma() */
+
+/**************************************************************************//**
+ * @brief       Sets gain adjustment for gamma correction
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31
+ * @param[out]  gam_lut         : Gamma correction registers for gain adjustment
+ * @retval      None
+******************************************************************************/
+static void Set_GainAdjustment_Gamma (const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut)
+{
+    uint32_t reg_index;
+
+    if (gam_gain != NULL)
+    {
+        for (reg_index = 0; reg_index < VDC_GAM_LUT_REG_NUM; reg_index++)
+        {
+            *(gam_lut[reg_index])  = (uint32_t)*gam_gain << VDC_REG_SHIFT_16;
+            gam_gain++;
+            *(gam_lut[reg_index]) |= (uint32_t)*gam_gain;
+            gam_gain++;
+        }
+    }
+}   /* End of function Set_GainAdjustment_Gamma() */
+
+/**************************************************************************//**
+ * @brief       Waits for 200 usec
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void Wait_200_usec (void)
+{
+    volatile uint32_t   counter;
+
+    for (counter = 0; counter < (uint32_t)VDC_LVDS_PLL_WAIT_200USEC; counter++)
+    {
+        /* Wait for 200 usec. */
+    }
+}   /* End of function Wait_200_usec() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_register.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,297 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_register.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDC_REGISTER_H
+#define R_VDC_REGISTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc.h"
+#include "r_vdc_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC_GAM_LUT_REG_NUM    (16u)   /*!< The number of table setting register in gamma correction block */
+#define     VDC_GAM_AREA_REG_NUM   (8u)    /*!< The number of area setting register in gamma correction block */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDC input controller register address list */
+typedef struct
+{
+    volatile uint32_t * inp_update;
+    volatile uint32_t * inp_sel_cnt;
+    volatile uint32_t * inp_ext_sync_cnt;
+    volatile uint32_t * inp_vsync_ph_adj;
+    volatile uint32_t * inp_dly_adj;
+    volatile uint32_t * imgcnt_update;
+    volatile uint32_t * imgcnt_nr_cnt0;
+    volatile uint32_t * imgcnt_nr_cnt1;
+} vdc_regaddr_input_ctrl_t;
+
+/*! VDC scaler register address list */
+typedef struct
+{
+    volatile uint32_t * scl0_update;
+    volatile uint32_t * scl0_frc1;
+    volatile uint32_t * scl0_frc2;
+    volatile uint32_t * scl0_frc3;
+    volatile uint32_t * scl0_frc4;
+    volatile uint32_t * scl0_frc5;
+    volatile uint32_t * scl0_frc6;
+    volatile uint32_t * scl0_frc7;
+    volatile uint32_t * scl0_frc9;
+    volatile uint16_t * scl0_mon0;
+    volatile uint16_t * scl0_int;
+    volatile uint32_t * scl0_ds1;
+    volatile uint32_t * scl0_ds2;
+    volatile uint32_t * scl0_ds3;
+    volatile uint32_t * scl0_ds4;
+    volatile uint32_t * scl0_ds5;
+    volatile uint32_t * scl0_ds6;
+    volatile uint32_t * scl0_ds7;
+    volatile uint32_t * scl0_us1;
+    volatile uint32_t * scl0_us2;
+    volatile uint32_t * scl0_us3;
+    volatile uint32_t * scl0_us4;
+    volatile uint32_t * scl0_us5;
+    volatile uint32_t * scl0_us6;
+    volatile uint32_t * scl0_us7;
+    volatile uint32_t * scl0_us8;
+    volatile uint32_t * scl0_ovr1;
+    volatile uint32_t * scl1_update;
+    volatile uint32_t * scl1_wr1;
+    volatile uint32_t * scl1_wr2;
+    volatile uint32_t * scl1_wr3;
+    volatile uint32_t * scl1_wr4;
+    volatile uint32_t * scl1_wr5;
+    volatile uint32_t * scl1_wr6;
+    volatile uint32_t * scl1_wr7;
+    volatile uint32_t * scl1_wr8;
+    volatile uint32_t * scl1_wr9;
+    volatile uint32_t * scl1_wr10;
+    volatile uint32_t * scl1_wr11;
+    volatile uint32_t * scl1_mon1;
+    volatile uint32_t * scl1_pbuf0;
+    volatile uint32_t * scl1_pbuf1;
+    volatile uint32_t * scl1_pbuf2;
+    volatile uint32_t * scl1_pbuf3;
+    volatile uint32_t * scl1_pbuf_fld;
+    volatile uint32_t * scl1_pbuf_cnt;
+} vdc_regaddr_scaler_t;
+
+/*! VDC image quality improver register address list */
+typedef struct
+{
+    volatile uint32_t * adj_update;
+    volatile uint32_t * adj_bkstr_set;
+    volatile uint32_t * adj_enh_tim1;
+    volatile uint32_t * adj_enh_tim2;
+    volatile uint32_t * adj_enh_tim3;
+    volatile uint32_t * adj_enh_shp1;
+    volatile uint32_t * adj_enh_shp2;
+    volatile uint32_t * adj_enh_shp3;
+    volatile uint32_t * adj_enh_shp4;
+    volatile uint32_t * adj_enh_shp5;
+    volatile uint32_t * adj_enh_shp6;
+    volatile uint32_t * adj_enh_lti1;
+    volatile uint32_t * adj_enh_lti2;
+} vdc_regaddr_img_qlty_imp_t;
+
+/*! VDC color matrix register address list */
+typedef struct
+{
+    volatile uint32_t * mtx_update;
+    volatile uint32_t * mtx_mode;
+    volatile uint32_t * mtx_yg_adj0;
+    volatile uint32_t * mtx_yg_adj1;
+    volatile uint32_t * mtx_cbb_adj0;
+    volatile uint32_t * mtx_cbb_adj1;
+    volatile uint32_t * mtx_crr_adj0;
+    volatile uint32_t * mtx_crr_adj1;
+} vdc_regaddr_color_matrix_t;
+
+/*! VDC image synthesizer register address list */
+typedef struct
+{
+    volatile uint32_t * gr_update;
+    volatile uint32_t * gr_flm_rd;
+    volatile uint32_t * gr_flm1;
+    volatile uint32_t * gr_flm2;
+    volatile uint32_t * gr_flm3;
+    volatile uint32_t * gr_flm4;
+    volatile uint32_t * gr_flm5;
+    volatile uint32_t * gr_flm6;
+    volatile uint32_t * gr_ab1;
+    volatile uint32_t * gr_ab2;
+    volatile uint32_t * gr_ab3;
+    volatile uint32_t * gr_ab4;
+    volatile uint32_t * gr_ab5;
+    volatile uint32_t * gr_ab6;
+    volatile uint32_t * gr_ab7;
+    volatile uint32_t * gr_ab8;
+    volatile uint32_t * gr_ab9;
+    volatile uint32_t * gr_ab10;
+    volatile uint32_t * gr_ab11;
+    volatile uint32_t * gr_base;
+    volatile uint32_t * gr_clut;
+    volatile uint32_t * gr_mon;
+} vdc_regaddr_img_synthesizer_t;
+
+/*! VDC gamma correction register address list */
+typedef struct
+{
+    volatile uint32_t * gam_sw;
+    volatile uint32_t * gam_g_update;
+    volatile uint32_t * gam_g_lut[VDC_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_g_area[VDC_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_b_update;
+    volatile uint32_t * gam_b_lut[VDC_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_b_area[VDC_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_r_update;
+    volatile uint32_t * gam_r_lut[VDC_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_r_area[VDC_GAM_AREA_REG_NUM];
+} vdc_regaddr_gamma_t;
+
+/*! VDC output controller register address list */
+typedef struct
+{
+    volatile uint32_t * tcon_update;
+    volatile uint32_t * tcon_tim;
+    volatile uint32_t * tcon_tim_stva1;
+    volatile uint32_t * tcon_tim_stva2;
+    volatile uint32_t * tcon_tim_stvb1;
+    volatile uint32_t * tcon_tim_stvb2;
+    volatile uint32_t * tcon_tim_sth1;
+    volatile uint32_t * tcon_tim_sth2;
+    volatile uint32_t * tcon_tim_stb1;
+    volatile uint32_t * tcon_tim_stb2;
+    volatile uint32_t * tcon_tim_cpv1;
+    volatile uint32_t * tcon_tim_cpv2;
+    volatile uint32_t * tcon_tim_pola1;
+    volatile uint32_t * tcon_tim_pola2;
+    volatile uint32_t * tcon_tim_polb1;
+    volatile uint32_t * tcon_tim_polb2;
+    volatile uint32_t * tcon_tim_de;
+    volatile uint32_t * out_update;
+    volatile uint32_t * out_set;
+    volatile uint32_t * out_bright1;
+    volatile uint32_t * out_bright2;
+    volatile uint32_t * out_contrast;
+    volatile uint32_t * out_pdtha;
+    volatile uint32_t * out_clk_phase;
+} vdc_regaddr_output_ctrl_t;
+
+/*! VDC system controller register address list */
+typedef struct
+{
+    volatile uint32_t * syscnt_int1;
+    volatile uint32_t * syscnt_int2;
+    volatile uint32_t * syscnt_int4;
+    volatile uint32_t * syscnt_int5;
+    volatile uint16_t * syscnt_panel_clk;
+    volatile uint16_t * syscnt_clut;
+} vdc_regaddr_system_ctrl_t;
+
+/*! LVDS register address list */
+typedef struct
+{
+    volatile uint32_t * lvds_update;
+    volatile uint32_t * lvdsfcl;
+    volatile uint32_t * lclkselr;
+    volatile uint32_t * lpllsetr;
+//    volatile uint32_t * lphyacc;
+} vdc_regaddr_lvds_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdc_regaddr_input_ctrl_t      vdc_regaddr_input_ctrl;
+extern const vdc_regaddr_scaler_t          vdc_regaddr_scaler;
+extern const vdc_regaddr_img_qlty_imp_t    vdc_regaddr_img_qlty_imp;
+extern const vdc_regaddr_color_matrix_t    vdc_regaddr_color_matrix[VDC_COLORMTX_NUM];
+extern const vdc_regaddr_img_synthesizer_t vdc_regaddr_img_synthesizer[VDC_GR_TYPE_NUM];
+extern uint32_t                     * const vdc_regaddr_clut[VDC_GR_TYPE_NUM];
+extern const vdc_regaddr_output_ctrl_t     vdc_regaddr_output_ctrl;
+extern const vdc_regaddr_gamma_t           vdc_regaddr_gamma;
+extern const vdc_regaddr_system_ctrl_t     vdc_regaddr_system_ctrl;
+extern const vdc_regaddr_lvds_t            vdc_regaddr_lvds;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC_Initialize(const vdc_init_t * const param);
+void VDC_Terminate(void);
+void VDC_VideoInput(const vdc_input_t * const param);
+void VDC_SyncControl(const vdc_sync_ctrl_t * const param);
+void VDC_DisplayOutput(const vdc_output_t * const param);
+void VDC_WriteDataControl(const vdc_write_t * const param);
+void VDC_ChangeWriteProcess(const vdc_write_chg_t * const param);
+void VDC_ReadDataControl(const vdc_graphics_type_t graphics_id, const vdc_read_t * const param);
+void VDC_ChangeReadProcess(const vdc_graphics_type_t graphics_id, const vdc_read_chg_t * const param);
+void VDC_StartProcess(const vdc_layer_id_t layer_id, const vdc_start_t * const param);
+void VDC_StopProcess(const vdc_layer_id_t layer_id);
+void VDC_VideoNoiseReduction(const vdc_onoff_t nr1d_on, const vdc_noise_reduction_t * const param);
+void VDC_ImageColorMatrix(const vdc_color_matrix_t * const param);
+void VDC_ImageEnhancement(
+    const vdc_onoff_t                  shp_h_on,
+    const vdc_enhance_sharp_t  * const sharp_param,
+    const vdc_onoff_t                  lti_h_on,
+    const vdc_enhance_lti_t    * const lti_param,
+    const vdc_period_rect_t    * const enh_area);
+void VDC_ImageBlackStretch(
+    const vdc_onoff_t          bkstr_on,
+    const vdc_black_t  * const param);
+void VDC_AlphaBlending(const vdc_graphics_type_t graphics_id, const vdc_alpha_blending_t * const param);
+void VDC_AlphaBlendingRect(
+    const vdc_graphics_type_t                  graphics_id,
+    const vdc_onoff_t                          gr_arc_on,
+    const vdc_alpha_blending_rect_t    * const param);
+void VDC_Chromakey(
+    const vdc_graphics_type_t      graphics_id,
+    const vdc_onoff_t              gr_ck_on,
+    const vdc_chromakey_t  * const param);
+void VDC_CLUT(const vdc_graphics_type_t graphics_id, const vdc_clut_t * const param);
+void VDC_DisplayCalibration(const vdc_disp_calibration_t * const param);
+void VDC_GammaCorrection(const vdc_onoff_t gam_on, const vdc_gamma_correction_t * const param);
+
+void VDC_Int_Disable(void);
+void VDC_Int_SetInterrupt(const vdc_int_t * const param);
+
+
+#endif  /* R_VDC_REGISTER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_register_address.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,388 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_register_address.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+#include    "r_vdc_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC6_CH0_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF6000u)
+#define     VDC6_CH0_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF6800u)
+#define     VDC6_CH0_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF6C00u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDC input controller register address list */
+const vdc_regaddr_input_ctrl_t vdc_regaddr_input_ctrl =
+{
+    &VDC6.INP_UPDATE.LONG,
+    &VDC6.INP_SEL_CNT.LONG,
+    &VDC6.INP_EXT_SYNC_CNT.LONG,
+    &VDC6.INP_VSYNC_PH_ADJ.LONG,
+    &VDC6.INP_DLY_ADJ.LONG,
+    &VDC6.IMGCNT_UPDATE.LONG,
+    &VDC6.IMGCNT_NR_CNT0.LONG,
+    &VDC6.IMGCNT_NR_CNT1.LONG
+};
+
+/* VDC scaler register address list */
+const vdc_regaddr_scaler_t vdc_regaddr_scaler =
+{
+    &VDC6.SC0_SCL0_UPDATE.LONG,
+    &VDC6.SC0_SCL0_FRC1.LONG,
+    &VDC6.SC0_SCL0_FRC2.LONG,
+    &VDC6.SC0_SCL0_FRC3.LONG,
+    &VDC6.SC0_SCL0_FRC4.LONG,
+    &VDC6.SC0_SCL0_FRC5.LONG,
+    &VDC6.SC0_SCL0_FRC6.LONG,
+    &VDC6.SC0_SCL0_FRC7.LONG,
+    &VDC6.SC0_SCL0_FRC9.LONG,
+    &VDC6.SC0_SCL0_MON0.WORD,
+    &VDC6.SC0_SCL0_INT.WORD,
+    &VDC6.SC0_SCL0_DS1.LONG,
+    &VDC6.SC0_SCL0_DS2.LONG,
+    &VDC6.SC0_SCL0_DS3.LONG,
+    &VDC6.SC0_SCL0_DS4.LONG,
+    &VDC6.SC0_SCL0_DS5.LONG,
+    &VDC6.SC0_SCL0_DS6.LONG,
+    &VDC6.SC0_SCL0_DS7.LONG,
+    &VDC6.SC0_SCL0_US1.LONG,
+    &VDC6.SC0_SCL0_US2.LONG,
+    &VDC6.SC0_SCL0_US3.LONG,
+    &VDC6.SC0_SCL0_US4.LONG,
+    &VDC6.SC0_SCL0_US5.LONG,
+    &VDC6.SC0_SCL0_US6.LONG,
+    &VDC6.SC0_SCL0_US7.LONG,
+    &VDC6.SC0_SCL0_US8.LONG,
+    &VDC6.SC0_SCL0_OVR1.LONG,
+    &VDC6.SC0_SCL1_UPDATE.LONG,
+    &VDC6.SC0_SCL1_WR1.LONG,
+    &VDC6.SC0_SCL1_WR2.LONG,
+    &VDC6.SC0_SCL1_WR3.LONG,
+    &VDC6.SC0_SCL1_WR4.LONG,
+    &VDC6.SC0_SCL1_WR5.LONG,
+    &VDC6.SC0_SCL1_WR6.LONG,
+    &VDC6.SC0_SCL1_WR7.LONG,
+    &VDC6.SC0_SCL1_WR8.LONG,
+    &VDC6.SC0_SCL1_WR9.LONG,
+    &VDC6.SC0_SCL1_WR10.LONG,
+    &VDC6.SC0_SCL1_WR11.LONG,
+    &VDC6.SC0_SCL1_MON1.LONG,
+    &VDC6.SC0_SCL1_PBUF0.LONG,
+    &VDC6.SC0_SCL1_PBUF1.LONG,
+    &VDC6.SC0_SCL1_PBUF2.LONG,
+    &VDC6.SC0_SCL1_PBUF3.LONG,
+    &VDC6.SC0_SCL1_PBUF_FLD.LONG,
+    &VDC6.SC0_SCL1_PBUF_CNT.LONG
+};
+
+/* VDC image quality improver register address list */
+const vdc_regaddr_img_qlty_imp_t vdc_regaddr_img_qlty_imp =
+{
+    &VDC6.ADJ0_UPDATE.LONG,
+    &VDC6.ADJ0_BKSTR_SET.LONG,
+    &VDC6.ADJ0_ENH_TIM1.LONG,
+    &VDC6.ADJ0_ENH_TIM2.LONG,
+    &VDC6.ADJ0_ENH_TIM3.LONG,
+    &VDC6.ADJ0_ENH_SHP1.LONG,
+    &VDC6.ADJ0_ENH_SHP2.LONG,
+    &VDC6.ADJ0_ENH_SHP3.LONG,
+    &VDC6.ADJ0_ENH_SHP4.LONG,
+    &VDC6.ADJ0_ENH_SHP5.LONG,
+    &VDC6.ADJ0_ENH_SHP6.LONG,
+    &VDC6.ADJ0_ENH_LTI1.LONG,
+    &VDC6.ADJ0_ENH_LTI2.LONG
+};
+
+/* VDC color matrix register address list */
+const vdc_regaddr_color_matrix_t vdc_regaddr_color_matrix[VDC_COLORMTX_NUM] =
+{
+    {   /* Input Controller */
+        &VDC6.IMGCNT_UPDATE.LONG,
+        &VDC6.IMGCNT_MTX_MODE.LONG,
+        &VDC6.IMGCNT_MTX_YG_ADJ0.LONG,
+        &VDC6.IMGCNT_MTX_YG_ADJ1.LONG,
+        &VDC6.IMGCNT_MTX_CBB_ADJ0.LONG,
+        &VDC6.IMGCNT_MTX_CBB_ADJ1.LONG,
+        &VDC6.IMGCNT_MTX_CRR_ADJ0.LONG,
+        &VDC6.IMGCNT_MTX_CRR_ADJ1.LONG
+    },
+    {   /* Image quality improver 0 */
+        &VDC6.ADJ0_UPDATE.LONG,
+        &VDC6.ADJ0_MTX_MODE.LONG,
+        &VDC6.ADJ0_MTX_YG_ADJ0.LONG,
+        &VDC6.ADJ0_MTX_YG_ADJ1.LONG,
+        &VDC6.ADJ0_MTX_CBB_ADJ0.LONG,
+        &VDC6.ADJ0_MTX_CBB_ADJ1.LONG,
+        &VDC6.ADJ0_MTX_CRR_ADJ0.LONG,
+        &VDC6.ADJ0_MTX_CRR_ADJ1.LONG
+    }
+};
+
+/* VDC image synthesizer register address list */
+const vdc_regaddr_img_synthesizer_t vdc_regaddr_img_synthesizer[VDC_GR_TYPE_NUM] =
+{
+    {   /* GR0 */
+        &VDC6.GR0_UPDATE.LONG,
+        &VDC6.GR0_FLM_RD.LONG,
+        &VDC6.GR0_FLM1.LONG,
+        &VDC6.GR0_FLM2.LONG,
+        &VDC6.GR0_FLM3.LONG,
+        &VDC6.GR0_FLM4.LONG,
+        &VDC6.GR0_FLM5.LONG,
+        &VDC6.GR0_FLM6.LONG,
+        &VDC6.GR0_AB1.LONG,
+        &VDC6.GR0_AB2.LONG,
+        &VDC6.GR0_AB3.LONG,
+        NULL,
+        NULL,
+        NULL,
+        &VDC6.GR0_AB7.LONG,
+        &VDC6.GR0_AB8.LONG,
+        &VDC6.GR0_AB9.LONG,
+        &VDC6.GR0_AB10.LONG,
+        &VDC6.GR0_AB11.LONG,
+        &VDC6.GR0_BASE.LONG,
+        &VDC6.GR0_CLUT.LONG,
+        NULL
+    },
+    {   /* GR2 */
+        &VDC6.GR2_UPDATE.LONG,
+        &VDC6.GR2_FLM_RD.LONG,
+        &VDC6.GR2_FLM1.LONG,
+        &VDC6.GR2_FLM2.LONG,
+        &VDC6.GR2_FLM3.LONG,
+        &VDC6.GR2_FLM4.LONG,
+        &VDC6.GR2_FLM5.LONG,
+        &VDC6.GR2_FLM6.LONG,
+        &VDC6.GR2_AB1.LONG,
+        &VDC6.GR2_AB2.LONG,
+        &VDC6.GR2_AB3.LONG,
+        &VDC6.GR2_AB4.LONG,
+        &VDC6.GR2_AB5.LONG,
+        &VDC6.GR2_AB6.LONG,
+        &VDC6.GR2_AB7.LONG,
+        &VDC6.GR2_AB8.LONG,
+        &VDC6.GR2_AB9.LONG,
+        &VDC6.GR2_AB10.LONG,
+        &VDC6.GR2_AB11.LONG,
+        &VDC6.GR2_BASE.LONG,
+        &VDC6.GR2_CLUT.LONG,
+        &VDC6.GR2_MON.LONG
+    },
+    {   /* GR3 */
+        &VDC6.GR3_UPDATE.LONG,
+        &VDC6.GR3_FLM_RD.LONG,
+        &VDC6.GR3_FLM1.LONG,
+        &VDC6.GR3_FLM2.LONG,
+        &VDC6.GR3_FLM3.LONG,
+        &VDC6.GR3_FLM4.LONG,
+        &VDC6.GR3_FLM5.LONG,
+        &VDC6.GR3_FLM6.LONG,
+        &VDC6.GR3_AB1.LONG,
+        &VDC6.GR3_AB2.LONG,
+        &VDC6.GR3_AB3.LONG,
+        &VDC6.GR3_AB4.LONG,
+        &VDC6.GR3_AB5.LONG,
+        &VDC6.GR3_AB6.LONG,
+        &VDC6.GR3_AB7.LONG,
+        &VDC6.GR3_AB8.LONG,
+        &VDC6.GR3_AB9.LONG,
+        &VDC6.GR3_AB10.LONG,
+        &VDC6.GR3_AB11.LONG,
+        &VDC6.GR3_BASE.LONG,
+        &VDC6.GR3_CLUT_INT.LONG,
+        &VDC6.GR3_MON.LONG
+    }
+};
+
+/* VDC CLUT register address list */
+uint32_t * const vdc_regaddr_clut[VDC_GR_TYPE_NUM] =
+{
+    &VDC6_CH0_GR0_CLUT_TBL,
+    &VDC6_CH0_GR2_CLUT_TBL,
+    &VDC6_CH0_GR3_CLUT_TBL
+};
+
+/* VDC output controller register address list */
+const vdc_regaddr_output_ctrl_t vdc_regaddr_output_ctrl =
+{
+    &VDC6.TCON_UPDATE.LONG,
+    &VDC6.TCON_TIM.LONG,
+    &VDC6.TCON_TIM_STVA1.LONG,
+    &VDC6.TCON_TIM_STVA2.LONG,
+    &VDC6.TCON_TIM_STVB1.LONG,
+    &VDC6.TCON_TIM_STVB2.LONG,
+    &VDC6.TCON_TIM_STH1.LONG,
+    &VDC6.TCON_TIM_STH2.LONG,
+    &VDC6.TCON_TIM_STB1.LONG,
+    &VDC6.TCON_TIM_STB2.LONG,
+    &VDC6.TCON_TIM_CPV1.LONG,
+    &VDC6.TCON_TIM_CPV2.LONG,
+    &VDC6.TCON_TIM_POLA1.LONG,
+    &VDC6.TCON_TIM_POLA2.LONG,
+    &VDC6.TCON_TIM_POLB1.LONG,
+    &VDC6.TCON_TIM_POLB2.LONG,
+    &VDC6.TCON_TIM_DE.LONG,
+    &VDC6.OUT_UPDATE.LONG,
+    &VDC6.OUT_SET.LONG,
+    &VDC6.OUT_BRIGHT1.LONG,
+    &VDC6.OUT_BRIGHT2.LONG,
+    &VDC6.OUT_CONTRAST.LONG,
+    &VDC6.OUT_PDTHA.LONG,
+    &VDC6.OUT_CLK_PHASE.LONG
+};
+
+/* VDC gamma correction register address list */
+const vdc_regaddr_gamma_t vdc_regaddr_gamma =
+{
+    &VDC6.GAM_SW.LONG,
+    &VDC6.GAM_G_UPDATE.LONG,
+    {
+        &VDC6.GAM_G_LUT1.LONG,
+        &VDC6.GAM_G_LUT2.LONG,
+        &VDC6.GAM_G_LUT3.LONG,
+        &VDC6.GAM_G_LUT4.LONG,
+        &VDC6.GAM_G_LUT5.LONG,
+        &VDC6.GAM_G_LUT6.LONG,
+        &VDC6.GAM_G_LUT7.LONG,
+        &VDC6.GAM_G_LUT8.LONG,
+        &VDC6.GAM_G_LUT9.LONG,
+        &VDC6.GAM_G_LUT10.LONG,
+        &VDC6.GAM_G_LUT11.LONG,
+        &VDC6.GAM_G_LUT12.LONG,
+        &VDC6.GAM_G_LUT13.LONG,
+        &VDC6.GAM_G_LUT14.LONG,
+        &VDC6.GAM_G_LUT15.LONG,
+        &VDC6.GAM_G_LUT16.LONG
+    },
+    {
+        &VDC6.GAM_G_AREA1.LONG,
+        &VDC6.GAM_G_AREA2.LONG,
+        &VDC6.GAM_G_AREA3.LONG,
+        &VDC6.GAM_G_AREA4.LONG,
+        &VDC6.GAM_G_AREA5.LONG,
+        &VDC6.GAM_G_AREA6.LONG,
+        &VDC6.GAM_G_AREA7.LONG,
+        &VDC6.GAM_G_AREA8.LONG
+    },
+    &VDC6.GAM_B_UPDATE.LONG,
+    {
+        &VDC6.GAM_B_LUT1.LONG,
+        &VDC6.GAM_B_LUT2.LONG,
+        &VDC6.GAM_B_LUT3.LONG,
+        &VDC6.GAM_B_LUT4.LONG,
+        &VDC6.GAM_B_LUT5.LONG,
+        &VDC6.GAM_B_LUT6.LONG,
+        &VDC6.GAM_B_LUT7.LONG,
+        &VDC6.GAM_B_LUT8.LONG,
+        &VDC6.GAM_B_LUT9.LONG,
+        &VDC6.GAM_B_LUT10.LONG,
+        &VDC6.GAM_B_LUT11.LONG,
+        &VDC6.GAM_B_LUT12.LONG,
+        &VDC6.GAM_B_LUT13.LONG,
+        &VDC6.GAM_B_LUT14.LONG,
+        &VDC6.GAM_B_LUT15.LONG,
+        &VDC6.GAM_B_LUT16.LONG
+    },
+    {
+        &VDC6.GAM_B_AREA1.LONG,
+        &VDC6.GAM_B_AREA2.LONG,
+        &VDC6.GAM_B_AREA3.LONG,
+        &VDC6.GAM_B_AREA4.LONG,
+        &VDC6.GAM_B_AREA5.LONG,
+        &VDC6.GAM_B_AREA6.LONG,
+        &VDC6.GAM_B_AREA7.LONG,
+        &VDC6.GAM_B_AREA8.LONG
+    },
+    &VDC6.GAM_R_UPDATE.LONG,
+    {
+        &VDC6.GAM_R_LUT1.LONG,
+        &VDC6.GAM_R_LUT2.LONG,
+        &VDC6.GAM_R_LUT3.LONG,
+        &VDC6.GAM_R_LUT4.LONG,
+        &VDC6.GAM_R_LUT5.LONG,
+        &VDC6.GAM_R_LUT6.LONG,
+        &VDC6.GAM_R_LUT7.LONG,
+        &VDC6.GAM_R_LUT8.LONG,
+        &VDC6.GAM_R_LUT9.LONG,
+        &VDC6.GAM_R_LUT10.LONG,
+        &VDC6.GAM_R_LUT11.LONG,
+        &VDC6.GAM_R_LUT12.LONG,
+        &VDC6.GAM_R_LUT13.LONG,
+        &VDC6.GAM_R_LUT14.LONG,
+        &VDC6.GAM_R_LUT15.LONG,
+        &VDC6.GAM_R_LUT16.LONG
+    },
+    {
+        &VDC6.GAM_R_AREA1.LONG,
+        &VDC6.GAM_R_AREA2.LONG,
+        &VDC6.GAM_R_AREA3.LONG,
+        &VDC6.GAM_R_AREA4.LONG,
+        &VDC6.GAM_R_AREA5.LONG,
+        &VDC6.GAM_R_AREA6.LONG,
+        &VDC6.GAM_R_AREA7.LONG,
+        &VDC6.GAM_R_AREA8.LONG
+    }
+};
+
+/* VDC system controller register address list */
+const vdc_regaddr_system_ctrl_t vdc_regaddr_system_ctrl =
+{
+    &VDC6.SYSCNT_INT1.LONG,
+    &VDC6.SYSCNT_INT2.LONG,
+    &VDC6.SYSCNT_INT4.LONG,
+    &VDC6.SYSCNT_INT5.LONG,
+    &VDC6.SYSCNT_PANEL_CLK.WORD,
+    &VDC6.SYSCNT_CLUT.WORD
+};
+
+/* LVDS register address list */
+const vdc_regaddr_lvds_t vdc_regaddr_lvds =
+{
+    &LVDS.LVDS_UPDATE.LONG,
+    &LVDS.LVDSFCL.LONG,
+    &LVDS.LCLKSELR.LONG,
+    &LVDS.LPLLSETR.LONG,
+//    &LVDS.LPHYACC.LONG
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_shared_param.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,867 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_shared_param.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver shared parameter processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_vdc_shared_param.h"
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Two to the power of eleven */
+#define     TWO_POWER_ELEVEN                (2048)
+
+#define     VDC_SPARA_DIV_2                (2)
+#define     VDC_SPARA_DIV_256              (256)
+
+/* Color Conversion Value */
+#define     VDC_SPARA_COLOR_CONV_RANGE     (255)
+#define     VDC_SPARA_COLOR_CONV_OFFSET    (128)
+
+/* Color mask data */
+#define     VDC_SPARA_COLOR_8BIT_MASK      (0x000000FFu)
+
+/* shift value */
+#define     VDC_SPARA_SHIFT_16             (16u)
+#define     VDC_SPARA_SHIFT_8              (8u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct
+{
+    vdc_panel_clksel_t     panel_icksel;   /*!< Panel clock select */
+    vdc_onoff_t            lvds_ref;       /*!< Reference to the LVDS PLL clock */
+    vdc_color_space_t      color_sp_in;    /*!< Color space of the input video image signal */
+    uint32_t                bg_color_rgb;   /*!< Background color in 24-bit RGB color format */
+    uint32_t                bg_color_crycb; /*!< Background color in 24-bit CrYCb format */
+} vdc_shared_param_common_t;
+
+typedef struct
+{
+    vdc_wr_md_t            res_ds_wr_md;   /*!< Frame buffer writing mode for image processing */
+    vdc_res_inter_t        res_inter;      /*!< Field operating mode select */
+    vdc_color_space_t      color_sp_fb_wr; /*!< Color space of the frame buffer writing format */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+    vdc_width_read_fb_t    width_wr_fb;    /*!< Size of the image output by scaling-down control block */
+} vdc_shared_param_scaling_t;
+
+typedef struct
+{
+    vdc_gr_ln_off_dir_t    gr_ln_off_dir;      /*!< Line offset address direction of the frame buffer */
+    vdc_gr_flm_sel_t       gr_flm_sel;         /*!< Frame buffer address setting signal */
+    vdc_gr_format_t        gr_format;          /*!< Format of the frame buffer read signal */
+    vdc_color_space_t      color_sp_fb_rd;     /*!< Color space of the frame buffer reading format */
+    vdc_onoff_t            adj_sel;            /*!< Folding handling (on/off) */
+    vdc_period_rect_t      gr_grc;             /*!< Graphics display area */
+    vdc_width_read_fb_t    width_read_fb;      /*!< Size of the frame buffer to be read */
+} vdc_shared_param_graphics_t;
+
+typedef struct
+{
+    vdc_resource_state_t   rsrc_panel_clock;
+    vdc_resource_state_t   rsrc_video_input;
+    vdc_resource_state_t   rsrc_vsync_signal;
+    vdc_resource_state_t   rsrc_lcd_panel;
+} vdc_shared_param_resource_t;
+
+/*! Read/write process state */
+typedef enum
+{
+    VDC_RW_PROC_STATE_DISABLE   = 0,
+    VDC_RW_PROC_STATE_ENABLE    = 1
+} vdc_rw_proc_state_t;
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc_resource_state_t * GetResourceStatePointer(const vdc_resource_type_t rsrc_type);
+static uint32_t SumProduct(
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset);
+
+static vdc_shared_param_common_t   param_common;
+static vdc_shared_param_scaling_t  param_scaling;
+static vdc_shared_param_graphics_t param_graphics[VDC_GR_TYPE_NUM];
+/*! A channel in VDC whose data is to be output through the LVDS */
+static vdc_channel_t               lvds_vdc_sel_ch;
+
+static vdc_resource_state_t        layer_resource[VDC_LAYER_ID_NUM];
+static vdc_rw_proc_state_t         rw_proc_state[VDC_LAYER_ID_NUM];
+
+static vdc_onoff_t                 video_input_flag = VDC_OFF;
+
+
+/**************************************************************************//**
+ * @brief       Initializes variables of the VDC driver
+ * @param[in]   void
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmInit (void)
+{
+    int32_t                         layer_id_num;
+    vdc_shared_param_common_t    * shared_param_common;
+    vdc_shared_param_scaling_t   * shared_param_scaling;
+    vdc_shared_param_graphics_t  * shared_param_graphics;
+    vdc_graphics_type_t            graphics_id;
+
+    for (layer_id_num = 0; layer_id_num < VDC_LAYER_ID_NUM; layer_id_num++)
+    {
+        layer_resource[layer_id_num] = VDC_RESOURCE_ST_INVALID;
+        rw_proc_state[layer_id_num]  = VDC_RW_PROC_STATE_DISABLE;
+    }
+
+    shared_param_common = &param_common;
+
+    shared_param_common->panel_icksel   = VDC_PANEL_ICKSEL_PERI;   /* Panel clock select */
+    shared_param_common->lvds_ref       = VDC_OFF;                 /* Reference to the LVDS PLL clock */
+    shared_param_common->bg_color_rgb   = (uint32_t)0u;             /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_crycb = (uint32_t)0u;             /* Background color in 24-bit CrYCb format */
+
+    if (video_input_flag == VDC_OFF)
+    {
+        shared_param_common->color_sp_in    = VDC_COLOR_SPACE_GBR; /* Color space of the input video image signal */
+    }
+
+    shared_param_scaling = &param_scaling;
+
+    /* Frame buffer writing mode for image processing */
+    shared_param_scaling->res_ds_wr_md      = VDC_WR_MD_NORMAL;
+    shared_param_scaling->res_inter         = VDC_RES_INTER_PROGRESSIVE;   /* Field operating mode select */
+    /* Color space of the frame buffer writing format */
+    shared_param_scaling->color_sp_fb_wr    = VDC_COLOR_SPACE_GBR;
+    /* Frame buffer base address for bottom */
+    shared_param_scaling->btm_base          = NULL;
+    /* Size of the image output by scaling-down control block */
+    shared_param_scaling->width_wr_fb.in_vw = (uint16_t)0;
+    shared_param_scaling->width_wr_fb.in_hw = (uint16_t)0;
+
+    for (graphics_id = VDC_GR_TYPE_GR0; graphics_id < VDC_GR_TYPE_NUM; graphics_id++)
+    {
+        shared_param_graphics = &param_graphics[graphics_id];
+
+        /* Line offset address direction of the frame buffer */
+        shared_param_graphics->gr_ln_off_dir = VDC_GR_LN_OFF_DIR_INC;
+        /* Frame buffer address setting signal */
+        shared_param_graphics->gr_flm_sel = VDC_GR_FLM_SEL_FLM_NUM;
+        /* Format of the frame buffer read signal */
+        shared_param_graphics->gr_format = VDC_GR_FORMAT_RGB565;
+        /* Color space of the frame buffer reading format */
+        shared_param_graphics->color_sp_fb_rd = VDC_COLOR_SPACE_GBR;
+        /* Folding handling (on/off) */
+        shared_param_graphics->adj_sel = VDC_OFF;
+        /* Graphics display area */
+        shared_param_graphics->gr_grc.vs = (uint16_t)0;
+        shared_param_graphics->gr_grc.vw = (uint16_t)0;
+        shared_param_graphics->gr_grc.hs = (uint16_t)0;
+        shared_param_graphics->gr_grc.hw = (uint16_t)0;
+        /* Size of the frame buffer to be read */
+        shared_param_graphics->width_read_fb.in_vw = (uint16_t)0;
+        shared_param_graphics->width_read_fb.in_hw = (uint16_t)0;
+    }
+    /* A channel in VDC whose data is to be output through the LVDS */
+    lvds_vdc_sel_ch = VDC_CHANNEL_NUM;     /* Initialized with invalid channel */
+}   /* End of function VDC_ShrdPrmInit() */
+
+/**************************************************************************//**
+ * @brief       Sets the initialization parameter
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetInitParam (const vdc_init_t * const param)
+{
+    vdc_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common;
+
+    /* Panel clock select */
+    shared_param_common->panel_icksel = param->panel_icksel;
+    /* Reference to the LVDS PLL clock */
+    if ((param->panel_icksel == VDC_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC_PANEL_ICKSEL_LVDS_DIV7))
+    {
+        shared_param_common->lvds_ref = VDC_ON;
+    }
+    if (param->lvds != NULL)
+    {   /* A channel in VDC whose data is to be output through the LVDS */
+        lvds_vdc_sel_ch = param->lvds->lvds_vdc_sel;
+    }
+}   /* End of function VDC_ShrdPrmSetInitParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the termination parameter
+ * @param[in]   None
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetTerminate (void)
+{
+    vdc_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common;
+
+    /* Reference to the LVDS PLL clock */
+    shared_param_common->lvds_ref = VDC_OFF;
+}   /* End of function VDC_ShrdPrmSetTerminate() */
+
+/**************************************************************************//**
+ * @brief       Sets the video input setup parameter
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetInputParam (const vdc_input_t * const param)
+{
+    vdc_shared_param_common_t    * shared_param_common;
+
+    video_input_flag = VDC_ON;
+
+    shared_param_common = &param_common;
+
+    /* Color space */
+    if ((param->ext_sig->inp_format == VDC_EXTIN_FORMAT_RGB888) ||
+        (param->ext_sig->inp_format == VDC_EXTIN_FORMAT_RGB666) ||
+        (param->ext_sig->inp_format == VDC_EXTIN_FORMAT_RGB565))
+    {
+        shared_param_common->color_sp_in = VDC_COLOR_SPACE_GBR;
+    }
+    else
+    {
+        shared_param_common->color_sp_in = VDC_COLOR_SPACE_YCBCR;
+    }
+}   /* End of function VDC_ShrdPrmSetInputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the display output configuration parameter
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetOutputParam (const vdc_output_t * const param)
+{
+    vdc_shared_param_common_t    * shared_param_common;
+    int32_t                         red;
+    int32_t                         green;
+    int32_t                         blue;
+    uint32_t                        y_val;
+    uint32_t                        cb_val;
+    uint32_t                        cr_val;
+
+    shared_param_common = &param_common;
+
+    /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_rgb = param->bg_color;
+
+    red     = (int32_t)((param->bg_color >> VDC_SPARA_SHIFT_16) & (uint32_t)VDC_SPARA_COLOR_8BIT_MASK);
+    green   = (int32_t)((param->bg_color >> VDC_SPARA_SHIFT_8)  & (uint32_t)VDC_SPARA_COLOR_8BIT_MASK);
+    blue    = (int32_t)( param->bg_color                         & (uint32_t)VDC_SPARA_COLOR_8BIT_MASK);
+    /* Y */
+    y_val = SumProduct(
+        red,
+        green,
+        blue,
+        (int32_t)VDC_COLORCONV_Y_R,
+        (int32_t)VDC_COLORCONV_Y_G,
+        (int32_t)VDC_COLORCONV_Y_B,
+        0);
+    /* Cb */
+    cb_val = SumProduct(
+        red,
+        green,
+        blue,
+        (int32_t)VDC_COLORCONV_CB_R,
+        (int32_t)VDC_COLORCONV_CB_G,
+        (int32_t)VDC_COLORCONV_CB_B,
+        (int32_t)VDC_SPARA_COLOR_CONV_OFFSET);
+    /* Cr */
+    cr_val = SumProduct(
+        red,
+        green,
+        blue,
+        (int32_t)VDC_COLORCONV_CR_R,
+        (int32_t)VDC_COLORCONV_CR_G,
+        (int32_t)VDC_COLORCONV_CR_B,
+        (int32_t)VDC_SPARA_COLOR_CONV_OFFSET);
+    /* Background color in 24-bit CrYCb format */
+    shared_param_common->bg_color_crycb = (uint32_t)((cr_val << VDC_SPARA_SHIFT_16) | (y_val << VDC_SPARA_SHIFT_8) | cb_val);
+}   /* End of function VDC_ShrdPrmSetOutputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write control parameter
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetWriteParam (const vdc_write_t * const param)
+{
+    vdc_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling;
+
+    /* Frame buffer writing mode for image processing */
+    shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+    /* Field operating mode select */
+    shared_param_scaling->res_inter = param->res_inter;
+
+    /* Color space of the frame buffer */
+    if ((param->res_md == VDC_RES_MD_YCBCR422) || (param->res_md == VDC_RES_MD_YCBCR444))
+    {
+        shared_param_scaling->color_sp_fb_wr = VDC_COLOR_SPACE_YCBCR;
+    }
+    else
+    {
+        shared_param_scaling->color_sp_fb_wr = VDC_COLOR_SPACE_GBR;
+    }
+
+    /* Frame buffer base address for bottom */
+    shared_param_scaling->btm_base = param->btm_base;
+    /* Size of the image output by scaling-down control block */
+    shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+    shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+}   /* End of function VDC_ShrdPrmSetWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write change parameter
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetChgWriteParam (const vdc_write_chg_t * const param)
+{
+    vdc_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling;
+
+    /* Frame buffer writing mode for image processing */
+    shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+    /* Size of the image output by scaling-down control block */
+    shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+    shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+}   /* End of function VDC_ShrdPrmSetChgWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read control parameter
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetReadParam (const vdc_graphics_type_t graphics_id, const vdc_read_t * const param)
+{
+    vdc_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[graphics_id];
+
+    /* Line offset address direction of the frame buffer */
+    shared_param_graphics->gr_ln_off_dir = param->gr_ln_off_dir;
+
+    /* Frame buffer address setting signal */
+    shared_param_graphics->gr_flm_sel = param->gr_flm_sel;
+
+    /* Format of the frame buffer read signal */
+    shared_param_graphics->gr_format = param->gr_format;
+
+    /* Color space of the frame buffer */
+    if ((param->gr_format == VDC_GR_FORMAT_YCBCR422) || (param->gr_format == VDC_GR_FORMAT_YCBCR444))
+    {
+        shared_param_graphics->color_sp_fb_rd = VDC_COLOR_SPACE_YCBCR;
+    }
+    else
+    {
+        shared_param_graphics->color_sp_fb_rd = VDC_COLOR_SPACE_GBR;
+    }
+
+    /* Folding handling (on/off) */
+    shared_param_graphics->adj_sel = param->adj_sel;
+
+    /* Graphics display area */
+    shared_param_graphics->gr_grc = param->gr_grc;
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL)
+    {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    }
+    else
+    {   /* If not specified, ... */
+        if (param->gr_flm_sel == VDC_GR_FLM_SEL_FLM_NUM)
+        {   /* The size of the frame buffer to be read is assumed that it is the same as
+               the width of the graphics display area. */
+            shared_param_graphics->width_read_fb.in_vw = param->gr_grc.vw;
+            shared_param_graphics->width_read_fb.in_hw = param->gr_grc.hw;
+        }
+        else
+        {   /* The size of the image output by scaling-down control block is used for the size of the frame buffer
+               to be read when a frame buffer address setting signal links to the video image signals. */
+            shared_param_graphics->width_read_fb = param_scaling.width_wr_fb;
+        }
+    }
+}   /* End of function VDC_ShrdPrmSetReadParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read change parameter
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetChgReadParam (const vdc_graphics_type_t graphics_id, const vdc_read_chg_t * const param)
+{
+    vdc_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[graphics_id];
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL)
+    {
+        shared_param_graphics->gr_grc = *(param->gr_grc);
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL)
+    {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    }
+}   /* End of function VDC_ShrdPrmSetChgReadParam() */
+
+/**************************************************************************//**
+ * @brief       Gets the reference to the LVDS PLL clock
+ * @param[in]   void
+ * @retval      Reference to the LVDS PLL clock
+ *****************************************************************************/
+vdc_onoff_t VDC_ShrdPrmGetLvdsClkRef (void)
+{
+    vdc_onoff_t onoff;
+
+    if (param_common.lvds_ref == VDC_OFF)
+    {
+        onoff = VDC_OFF;
+    }
+    else
+    {
+        onoff = VDC_ON;
+    }
+    return onoff;
+}   /* End of function VDC_ShrdPrmGetLvdsClkRef() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the input video image signal
+ * @param[in]   void
+ * @retval      Color space of the input video image signal
+ *****************************************************************************/
+vdc_color_space_t VDC_ShrdPrmGetColorSpace (void)
+{
+    return param_common.color_sp_in;
+}   /* End of function VDC_ShrdPrmGetColorSpace() */
+
+/**************************************************************************//**
+ * @brief       Get the background color
+ * @param[in]   color_space             : Color space
+ * @retval      Background color in 24-bit RGB color format or CrYCb format
+ *****************************************************************************/
+uint32_t VDC_ShrdPrmGetBgColor (const vdc_color_space_t color_space)
+{
+    return (color_space == VDC_COLOR_SPACE_GBR) ? param_common.bg_color_rgb : param_common.bg_color_crycb;
+}   /* End of function VDC_ShrdPrmGetBgColor() */
+
+/**************************************************************************//**
+ * @brief       Get the frame buffer writing mode for image processing
+ * @param[in]   void
+ * @retval      Frame buffer writing mode for image processing
+ *****************************************************************************/
+vdc_wr_md_t VDC_ShrdPrmGetWritingMode (void)
+{
+    return param_scaling.res_ds_wr_md;
+}   /* End of function VDC_ShrdPrmGetWritingMode() */
+
+/**************************************************************************//**
+ * @brief
+ * @param[in]   void
+ * @retval      Field operating mode select
+ *****************************************************************************/
+vdc_res_inter_t VDC_ShrdPrmGetInterlace (void)
+{
+    return param_scaling.res_inter;
+}   /* End of function VDC_ShrdPrmGetInterlace() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer writing format
+ * @param[in]   void
+ * @retval      Color space of the frame buffer writing format
+ *****************************************************************************/
+vdc_color_space_t VDC_ShrdPrmGetColorSpaceFbWr (void)
+{
+    return param_scaling.color_sp_fb_wr;
+}   /* End of function VDC_ShrdPrmGetColorSpaceFbWr() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer base address for bottom
+ * @param[in]   void
+ * @retval      Frame buffer base address for bottom
+ *****************************************************************************/
+void * VDC_ShrdPrmGetFrBuffBtm (void)
+{
+    return param_scaling.btm_base;
+}   /* End of function VDC_ShrdPrmGetFrBuffBtm() */
+
+/**************************************************************************//**
+ * @brief       Gets the line offset address direction of the frame buffer
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Line offset address direction of the frame buffer
+ *****************************************************************************/
+vdc_gr_ln_off_dir_t VDC_ShrdPrmGetLineOfsAddrDir (const vdc_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].gr_ln_off_dir;
+}   /* End of function VDC_ShrdPrmGetLineOfsAddrDir() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer address setting signal
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Frame buffer address setting signal
+ *****************************************************************************/
+vdc_gr_flm_sel_t VDC_ShrdPrmGetSelFbAddrSig (const vdc_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].gr_flm_sel;
+}   /* End of function VDC_ShrdPrmGetSelFbAddrSig() */
+
+/**************************************************************************//**
+ * @brief       Gets the format of the frame buffer read signal
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Format of the frame buffer read signal
+ *****************************************************************************/
+vdc_gr_format_t VDC_ShrdPrmGetGraphicsFormat (const vdc_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].gr_format;
+}   /* End of function VDC_ShrdPrmGetGraphicsFormat() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer reading format
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Color space of the frame buffer reading format
+ *****************************************************************************/
+vdc_color_space_t VDC_ShrdPrmGetColorSpaceFbRd (const vdc_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].color_sp_fb_rd;
+}   /* End of function VDC_ShrdPrmGetColorSpaceFbRd() */
+
+/**************************************************************************//**
+ * @brief       Gets the folding handling
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Folding handling (on/off)
+ *****************************************************************************/
+vdc_onoff_t VDC_ShrdPrmGetMeasureFolding (const vdc_graphics_type_t graphics_id)
+{
+    return param_graphics[graphics_id].adj_sel;
+}   /* End of function VDC_ShrdPrmGetMeasureFolding() */
+
+/**************************************************************************//**
+ * @brief       Gets the graphics display area
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Graphics display area
+ *****************************************************************************/
+vdc_period_rect_t * VDC_ShrdPrmGetDisplayArea (const vdc_graphics_type_t graphics_id)
+{
+    return &param_graphics[graphics_id].gr_grc;
+}   /* End of function VDC_ShrdPrmGetDisplayArea() */
+
+/**************************************************************************//**
+ * @brief       Gets the size of the frame buffer to be read
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Size of the frame buffer to be read
+ *****************************************************************************/
+vdc_width_read_fb_t * VDC_ShrdPrmGetFrBuffWidth_Rd (const vdc_graphics_type_t graphics_id)
+{
+    return &param_graphics[graphics_id].width_read_fb;
+}   /* End of function VDC_ShrdPrmGetFrBuffWidth_Rd() */
+
+/**************************************************************************//**
+ * @brief       Gets the VDC channel whose data is to be output through the LVDS
+ * @param[in]   void
+ * @retval      A channel in VDC whose data is to be output through the LVDS
+ *****************************************************************************/
+vdc_channel_t VDC_ShrdPrmGetLvdsCh (void)
+{
+    /* This value is valid only when LVDS PLL clock resource (VDC_RESOURCE_LVDS_CLK) is valid. */
+    return lvds_vdc_sel_ch;
+}   /* End of function VDC_ShrdPrmGetLvdsCh() */
+
+/**************************************************************************//**
+ * @brief       Updates the resource state
+ * @param[in]   rsrc_type               : Resource type
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetResource (const vdc_resource_type_t rsrc_type, const vdc_resource_state_t rsrc_state)
+{
+    vdc_resource_state_t * resource_state;
+
+    resource_state = GetResourceStatePointer(rsrc_type);
+    if (resource_state != NULL)
+    {
+        *resource_state = rsrc_state;
+    }
+}   /* End of function VDC_ShrdPrmSetResource() */
+
+/**************************************************************************//**
+ * @brief       Updates the layer resource state
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetLayerResource (const vdc_layer_id_t layer_id, const vdc_resource_state_t rsrc_state)
+{
+    uint32_t layer_id_num;
+
+    if (layer_id != VDC_LAYER_ID_ALL)
+    {
+        layer_resource[layer_id] = rsrc_state;
+    }
+    else
+    {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC_LAYER_ID_NUM; layer_id_num++)
+        {
+            if (rw_proc_state[layer_id_num] == VDC_RW_PROC_STATE_DISABLE)
+            {
+                layer_resource[layer_id_num] = rsrc_state;
+            }
+        }
+    }
+}   /* End of function VDC_ShrdPrmSetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the resource state
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Resource state
+ *****************************************************************************/
+vdc_resource_state_t VDC_ShrdPrmGetResource (const vdc_resource_type_t rsrc_type)
+{
+    vdc_resource_state_t * resource_state;
+    vdc_resource_state_t   rsrc_state;
+
+    rsrc_state = VDC_RESOURCE_ST_INVALID;
+
+    resource_state = GetResourceStatePointer(rsrc_type);
+    if (resource_state != NULL)
+    {
+        rsrc_state = *resource_state;
+    }
+    return rsrc_state;
+}   /* End of function VDC_ShrdPrmGetResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the layer resource state
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Layer resource state
+ *****************************************************************************/
+vdc_resource_state_t VDC_ShrdPrmGetLayerResource (const vdc_layer_id_t layer_id)
+{
+    return layer_resource[layer_id];
+}   /* End of function VDC_ShrdPrmGetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing enabled
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetRwProcEnable (const vdc_layer_id_t layer_id)
+{
+    if (layer_id != VDC_LAYER_ID_ALL)
+    {
+        if (layer_resource[layer_id] != VDC_RESOURCE_ST_INVALID)
+        {
+            rw_proc_state[layer_id] = VDC_RW_PROC_STATE_ENABLE;
+        }
+    }
+}   /* End of function VDC_ShrdPrmSetRwProcEnable() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing disabled
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC_ShrdPrmSetRwProcDisable (const vdc_layer_id_t layer_id)
+{
+    if (layer_id != VDC_LAYER_ID_ALL)
+    {
+        if (layer_resource[layer_id] != VDC_RESOURCE_ST_INVALID)
+        {
+            rw_proc_state[layer_id] = VDC_RW_PROC_STATE_DISABLE;
+        }
+    }
+}   /* End of function VDC_ShrdPrmSetRwProcDisable() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is ready or not
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is disabled.
+ *              - VDC_RESOURCE_ST_INVALID: The specified layer is not ready.
+ *****************************************************************************/
+vdc_resource_state_t VDC_ShrdPrmGetRwProcReady (const vdc_layer_id_t layer_id)
+{
+    vdc_resource_state_t state;
+
+    if ((layer_resource[layer_id] != VDC_RESOURCE_ST_INVALID) &&
+        (rw_proc_state[layer_id] == VDC_RW_PROC_STATE_DISABLE))
+    {
+        state = VDC_RESOURCE_ST_VALID;
+    }
+    else
+    {
+        state = VDC_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC_ShrdPrmGetRwProcReady() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is already run or not
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is enabled.
+ *              - VDC_RESOURCE_ST_INVALID: The specified layer is not enabled.
+ *****************************************************************************/
+vdc_resource_state_t VDC_ShrdPrmGetRwProcEnabled (const vdc_layer_id_t layer_id)
+{
+    vdc_resource_state_t state;
+
+    if ((layer_resource[layer_id] != VDC_RESOURCE_ST_INVALID) &&
+        (rw_proc_state[layer_id] != VDC_RW_PROC_STATE_DISABLE))
+    {
+        state = VDC_RESOURCE_ST_VALID;
+    }
+    else
+    {
+        state = VDC_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC_ShrdPrmGetRwProcEnabled() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Gets the pointer to the resource state
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Pointer to the resource state
+ *****************************************************************************/
+static vdc_resource_state_t * GetResourceStatePointer (const vdc_resource_type_t rsrc_type)
+{
+    vdc_resource_state_t             * resource_state;
+    static vdc_shared_param_resource_t param_resource =
+    {
+        VDC_RESOURCE_ST_INVALID, VDC_RESOURCE_ST_INVALID, VDC_RESOURCE_ST_INVALID, VDC_RESOURCE_ST_INVALID
+    };
+    static vdc_resource_state_t        lvds_resource = VDC_RESOURCE_ST_INVALID;
+
+    switch (rsrc_type)
+    {
+        case VDC_RESOURCE_PANEL_CLK:
+            resource_state = &param_resource.rsrc_panel_clock;
+        break;
+        case VDC_RESOURCE_VIDEO_IN:
+            resource_state = &param_resource.rsrc_video_input;
+        break;
+        case VDC_RESOURCE_VSYNC:
+            resource_state = &param_resource.rsrc_vsync_signal;
+        break;
+        case VDC_RESOURCE_LCD_PANEL:
+            resource_state = &param_resource.rsrc_lcd_panel;
+        break;
+        case VDC_RESOURCE_LVDS_CLK:
+            resource_state = &lvds_resource;
+        break;
+
+        default:
+            resource_state = NULL;
+        break;
+    }
+    return resource_state;
+}   /* End of function GetResourceStatePointer() */
+
+/**************************************************************************//**
+ * @brief       Product-sum operation
+ * @param[in]   red             : 8 bits for red
+ * @param[in]   green           : 8 bits for green
+ * @param[in]   blue            : 8 bits for blue
+ * @param[in]   coeff_r         : Coefficient value for Cr/R signal gain adjustment
+ * @param[in]   coeff_g         : Coefficient value for Y/G signal gain adjustment
+ * @param[in]   coeff_b         : Coefficient value for Cb/B signal gain adjustment
+ * @param[in]   offset          : Coefficient value for offset adjustment
+ * @retval      Answer
+ *****************************************************************************/
+static uint32_t SumProduct (
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset)
+{
+    int32_t color_val;
+
+    /* Coefficient values are represented in 11-bit two's complement integer. */
+    if (coeff_r >= (TWO_POWER_ELEVEN / VDC_SPARA_DIV_2))
+    {
+        coeff_r -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_g >= (TWO_POWER_ELEVEN / VDC_SPARA_DIV_2))
+    {
+        coeff_g -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_b >= (TWO_POWER_ELEVEN / VDC_SPARA_DIV_2))
+    {
+        coeff_b -= (int32_t)TWO_POWER_ELEVEN;
+    }
+
+    color_val  = (red * coeff_r) + (green * coeff_g) + (blue * coeff_b);
+    color_val /= (int32_t)VDC_SPARA_DIV_256;
+    color_val += offset;
+    if (color_val < 0)
+    {
+        color_val = 0;
+    }
+    else if (color_val > (int32_t)VDC_SPARA_COLOR_CONV_RANGE)
+    {
+        color_val = (int32_t)VDC_SPARA_COLOR_CONV_RANGE;
+    }
+    else
+    {
+    }
+    return (uint32_t)color_val;
+}   /* End of function SumProduct() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/src/r_vdc_shared_param.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,117 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc_shared_param.h
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M VDC driver shared parameter definitions
+******************************************************************************/
+
+#ifndef R_VDC_SHARED_PARAM_H
+#define R_VDC_SHARED_PARAM_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_vdc.h"
+#include "r_vdc_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Color space */
+typedef enum
+{
+    VDC_COLOR_SPACE_GBR    = 0,        /*!< GBR */
+    VDC_COLOR_SPACE_YCBCR  = 1         /*!< YCbCr */
+} vdc_color_space_t;
+
+/*! Resource state */
+typedef enum
+{
+    VDC_RESOURCE_ST_INVALID    = 0,    /*!< Invalid */
+    VDC_RESOURCE_ST_VALID      = 1     /*!< Valid */
+} vdc_resource_state_t;
+
+/*! Resource type */
+typedef enum
+{
+    VDC_RESOURCE_PANEL_CLK = 0,        /*!< Panel clock */
+    VDC_RESOURCE_VIDEO_IN,             /*!< Input video */
+    VDC_RESOURCE_VSYNC,                /*!< Vsync signal */
+    VDC_RESOURCE_LCD_PANEL,            /*!< LCD panel (output video) */
+    VDC_RESOURCE_LVDS_CLK,             /*!< LVDS PLL clock */
+    VDC_RESOURCE_NUM
+} vdc_resource_type_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC_ShrdPrmInit(void);
+
+void VDC_ShrdPrmSetInitParam(const vdc_init_t * const param);
+void VDC_ShrdPrmSetTerminate(void);
+void VDC_ShrdPrmSetInputParam(const vdc_input_t * const param);
+void VDC_ShrdPrmSetOutputParam(const vdc_output_t * const param);
+void VDC_ShrdPrmSetWriteParam(const vdc_write_t * const param);
+void VDC_ShrdPrmSetChgWriteParam(const vdc_write_chg_t * const param);
+void VDC_ShrdPrmSetReadParam(const vdc_graphics_type_t graphics_id, const vdc_read_t * const param);
+void VDC_ShrdPrmSetChgReadParam(const vdc_graphics_type_t graphics_id, const vdc_read_chg_t * const param);
+
+vdc_onoff_t VDC_ShrdPrmGetLvdsClkRef(void);
+vdc_color_space_t VDC_ShrdPrmGetColorSpace(void);
+uint32_t VDC_ShrdPrmGetBgColor(const vdc_color_space_t color_space);
+vdc_wr_md_t VDC_ShrdPrmGetWritingMode(void);
+vdc_res_inter_t VDC_ShrdPrmGetInterlace(void);
+vdc_color_space_t VDC_ShrdPrmGetColorSpaceFbWr(void);
+void * VDC_ShrdPrmGetFrBuffBtm(void);
+
+vdc_gr_ln_off_dir_t VDC_ShrdPrmGetLineOfsAddrDir(const vdc_graphics_type_t graphics_id);
+vdc_gr_flm_sel_t VDC_ShrdPrmGetSelFbAddrSig(const vdc_graphics_type_t graphics_id);
+vdc_gr_format_t VDC_ShrdPrmGetGraphicsFormat(const vdc_graphics_type_t graphics_id);
+vdc_color_space_t VDC_ShrdPrmGetColorSpaceFbRd(const vdc_graphics_type_t graphics_id);
+vdc_onoff_t VDC_ShrdPrmGetMeasureFolding(const vdc_graphics_type_t graphics_id);
+vdc_period_rect_t * VDC_ShrdPrmGetDisplayArea(const vdc_graphics_type_t graphics_id);
+vdc_width_read_fb_t * VDC_ShrdPrmGetFrBuffWidth_Rd(const vdc_graphics_type_t  graphics_id);
+
+void VDC_ShrdPrmSetResource(const vdc_resource_type_t rsrc_type, const vdc_resource_state_t rsrc_state);
+void VDC_ShrdPrmSetLayerResource(const vdc_layer_id_t layer_id, const vdc_resource_state_t rsrc_state);
+vdc_resource_state_t VDC_ShrdPrmGetResource(const vdc_resource_type_t rsrc_type);
+vdc_resource_state_t VDC_ShrdPrmGetLayerResource(const vdc_layer_id_t layer_id);
+
+void VDC_ShrdPrmSetRwProcEnable(const vdc_layer_id_t layer_id);
+void VDC_ShrdPrmSetRwProcDisable(const vdc_layer_id_t layer_id);
+vdc_resource_state_t VDC_ShrdPrmGetRwProcReady(const vdc_layer_id_t layer_id);
+vdc_resource_state_t VDC_ShrdPrmGetRwProcEnabled(const vdc_layer_id_t layer_id);
+vdc_channel_t VDC_ShrdPrmGetLvdsCh(void);
+
+
+#endif  /* R_VDC_SHARED_PARAM_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/userdef/spea_userdef.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         spea_userdef.c
+* @version      0.01
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A2M SPEA driver user function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "mmu_init.h"
+#include    "r_spea.h"
+#include    "r_spea_user.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/**************************************************************************//**
+ * @brief       Physical address translation
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Get the System Physical address of the given virtual memory address.
+ * @param[in]   vaddr               : virtual address
+ * @retval      physical address
+ *****************************************************************************/
+uint32_t R_SPEA_CPUVAddrToSysPAddr(uint32_t vaddr)
+{
+    uint32_t ret;
+
+    ret = R_MMU_VAtoPA(vaddr);
+    return ret;
+}   /* End of function R_SPEA_CPUVAddrToSysPAddr() */
+
+
+/* End of File */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/drivers/vdc/userdef/vdc_userdef.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         vdc6_userdef.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L VDC6 driver user function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc.h"
+#include    "r_vdc_user.h"
+#include    "mmu_init.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/**************************************************************************//**
+ * @brief       Physical address translation
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Get the System Physical address of the given virtual memory address.
+ * @param[in]   vaddr               : virtual address
+ * @retval      physical address
+ *****************************************************************************/
+uint32_t R_VDC_CPUVAddrToSysPAddr(uint32_t vaddr)
+{
+    uint32_t ret;
+
+    ret = R_MMU_VAtoPA(vaddr);
+    return ret;
+}   /* End of function R_VDC_CPUVAddrToSysPAddr() */
+
+
+/* End of File */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/lvds/lvds_pll_data.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,75 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         lvds_pll_data.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        lvds pll for vdc5 channel 0 data
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <stdlib.h>
+
+
+/******************************************************************************
+Variables
+******************************************************************************/
+const double dcdr_data[] = {
+    1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 12.0, 16.0, 24.0, 32.0,
+    0.0
+};
+
+const double NIDIV_data[] = {
+    1.0,
+    0.0
+};
+
+const double NRD_data[] = {
+    1.0,    2.0,    3.0,    4.0,    5.0,    6.0,    7.0,    8.0,
+    0.0
+};
+
+const double NFD_data[] = {
+                      23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0,
+    30.0, 31.0, 32.0, 33.0, 34.0, 35.0, 36.0, 37.0, 38.0, 39.0,
+    40.0, 41.0, 42.0, 43.0, 44.0, 45.0, 46.0, 47.0, 48.0, 49.0,
+    50.0, 51.0, 52.0, 53.0, 54.0, 55.0, 56.0, 57.0, 58.0, 59.0,
+    60.0, 61.0, 62.0, 63.0,
+    0.0
+};
+
+const double NOD_data[] = {
+    2.0,
+    0.0
+};
+
+const double NODIV_data[] = {
+    1.0,    2.0,    4.0,
+    0.0
+};
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/lvds/lvds_pll_main.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,234 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lvds_pll_main.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        lvds pll setting value
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <stdlib.h>
+#include    <math.h>
+
+#include    "r_typedefs.h"
+#include    "lvds_pll_calc.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* FIN: LVDS PLL input frequency */
+#define     FIN_MIN             (9.6)           /*!< The lower limit of the FIN */
+#define     FIN_MAX             (87.0)          /*!< The upper limit of the FIN */
+/* FREF */
+#define     FREF_MIN            (9.6)           /*!< The lower limit of the FREF */
+#define     FREF_MAX            (13.0)          /*!< The upper limit of the FREF */
+/* FVCO: VCO output frequency */
+#define     FVCO_MIN            (580.0)         /*!< The lower limit of the FVCO */
+#define     FVCO_MAX            (1250.0)        /*!< The upper limit of the FVCO */
+/* FOUT: LVDS PLL output frequency */
+#define     FOUT_MIN            (290.0)         /*!< The lower limit of the FOUT */
+#define     FOUT_MAX            (609.0)         /*!< The upper limit of the FOUT */
+
+#define     DIVIDER_3           (7.0)           /*!< The frequency dividing value for frequency divider 3 */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const double dcdr_data[];
+extern const double NIDIV_data[];
+extern const double NRD_data[];
+extern const double NFD_data[];
+extern const double NOD_data[];
+extern const double NODIV_data[];
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static double   InputClock;
+static double   OutputClock;
+static int      LvdsUsed;
+
+
+
+/**************************************************************************//**
+ * @brief
+ * @param       [in,out]param
+ * @param       [in]fout
+ * @retval      int
+ *****************************************************************************/
+static int compare_nodiv (pll_parameter_t * param, double fout)
+{
+    int             change;
+    const double  * nodiv_list;
+    double          diff_freq;
+
+    change      = 0;
+    nodiv_list  = NODIV_data;
+    while (*nodiv_list != 0.0) {
+        diff_freq   = fabs(OutputClock - (fout / *nodiv_list));
+        if (param->comparison_freq > diff_freq) {
+            param->comparison_freq  = diff_freq;
+            param->output_freq      = fout / *nodiv_list;
+            param->nodiv            = *nodiv_list;
+            change                  = 1;
+        }
+        nodiv_list++;
+    }
+    return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param       [in,out]param
+ * @param       [in]fout
+ * @retval      int
+ *****************************************************************************/
+static int compare_div3 (pll_parameter_t * param, double fout)
+{
+    double  diff_freq;
+    int     change;
+
+    change      = 0;
+    diff_freq   = fabs(OutputClock - (fout / DIVIDER_3));
+
+    if (param->comparison_freq > diff_freq) {
+        param->comparison_freq  = diff_freq;
+        param->output_freq      = fout / DIVIDER_3;
+        change                  = 1;
+    }
+    return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param       [out]param
+ * @retval      None
+ *****************************************************************************/
+static void SeekValue (pll_parameter_t * param)
+{
+    const double  * dcdr_list;
+    const double  * nidiv_list;
+    const double  * nrd_list;
+    const double  * nfd_list;
+
+    double  fnrdin;
+    double  fin;
+    double  fref;
+    double  fvco;
+    double  fout;
+    int     ret;
+
+    dcdr_list = dcdr_data;
+    while (*dcdr_list != 0.0) {
+        fnrdin = InputClock / *dcdr_list;
+
+        nidiv_list = NIDIV_data;
+        while (*nidiv_list != 0.0) {
+            fin = fnrdin / *nidiv_list;
+            if ((fin < FIN_MIN) || (FIN_MAX < fin)) {
+                nidiv_list++;
+                continue;
+            }
+            nrd_list = NRD_data;
+            while (*nrd_list != 0.0) {
+                fref = fin / *nrd_list;
+                if ((fref < FREF_MIN) || (FREF_MAX < fref)) {
+                    nrd_list++;
+                    continue;
+                }
+                nfd_list = NFD_data;
+                while (*nfd_list != 0.0) {
+                    fvco = fin * (*nfd_list) * NOD_data[0] / (*nrd_list);
+                    if ((fvco < FVCO_MIN) || (FVCO_MAX < fvco)) {
+                        nfd_list++;
+                        continue;
+                    }
+
+                    fout = fin * (*nfd_list) / (*nrd_list);
+                    if ((fout < FOUT_MIN) || (FOUT_MAX < fout)) {
+                        nfd_list++;
+                        continue;
+                    }
+                    if (LvdsUsed == 0) {
+                        ret = compare_nodiv(param, fout);
+                    } else {
+                        ret = compare_div3(param, fout);
+                    }
+                    if (ret != 0) {
+                        param->nidiv = *nidiv_list;
+                        param->nrd = *nrd_list;
+                        param->nfd = *nfd_list;
+                        param->dcdr = *dcdr_list;
+                    }
+                    nfd_list++;
+                }
+                nrd_list++;
+            }
+            nidiv_list++;
+        }
+        dcdr_list++;
+    }
+}
+/**************************************************************************//**
+ * @brief       PLL value Calculation function
+ * @param[in]   InClock     : Input clock frequency [MHz]
+ * @param[in]   OuClock     : Output clock frequency [MHz]
+ * @param[in]   Lvds        : The LVDS output interface is used (=1) or not (=0)
+ * @param[out]  result      : pll_parameter_t
+ * @retval      error (-1)
+******************************************************************************/
+int32_t lvds_pll_calc(
+    const double      InClock,
+    const double      OuClock,
+    const uint32_t    Lvds,
+    pll_parameter_t * result  )
+{
+    result->comparison_freq  = 1000.0;
+    result->output_freq      = 0.0;
+    result->dcdr             = 0.0;
+    result->nidiv            = 0.0;
+    result->nrd              = 0.0;
+    result->nfd              = 0.0;
+    result->nodiv            = 0.0;
+
+    InputClock   = InClock;
+    OutputClock  = OuClock;
+    LvdsUsed     = Lvds;
+
+    /* Calculation */
+    SeekValue(result);
+
+    return 0;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/lvds_pll_calc.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lvds_pll_calc.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Debug function header
+******************************************************************************/
+
+#ifndef LVDS_PLL_CALC_H
+#define LVDS_PLL_CALC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+typedef struct {
+    double comparison_freq;
+    double output_freq;
+    double dcdr;
+    double nidiv;
+    double nrd;
+    double nfd;
+    double nodiv;
+} pll_parameter_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+#define LVDS_IF_NOT_USE (0u)
+#define LVDS_IF_USE     (1u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+extern int32_t lvds_pll_calc(
+    const double      InClock,
+    const double      OuClock,
+    const uint32_t    Lvds,
+    pll_parameter_t * result  );
+
+#endif  /* LVDS_PLL_CALC_H */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/TARGET_RZA2M/rz_a2m_evb_vdc.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1398 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         misano_vdc.c
+* @version
+* $Rev:
+* $Date::
+* @brief        VDC driver API wrapper function in C interface
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <string.h>
+#include    <math.h>
+
+#if(1) /* mbed */
+#else
+#include    "r_typedefs.h"
+#endif
+#include    "r_vdc.h"
+#include    "lvds_pll_calc.h"
+#include    "gr_board_vdc5.h"
+#include    "r_ceu.h"
+#include    "r_mipi_api.h"
+
+#include    "mbed_assert.h"
+#include    "pinmap.h"
+#include    "RZ_A2_Init.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define STP81_BIT               (0x02u)
+#define STBRQ25_BIT             (0x20u)
+#define STBAK25_BIT             (0x20u)
+#define CLUT8_TABLE_NUM         (256u)
+#define CLUT4_TABLE_NUM         (16u)
+#define CLUT1_TABLE_NUM         (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+static const PinMap PinMap_DV_INPUT_PIN[] = {
+    {P7_2  , 0, 2}, /* DV0_CLK    */
+    {P7_6  , 0, 2}, /* DV0_VSYNC  */
+    {P7_7  , 0, 2}, /* DV0_HSYNC  */
+    {PA_6  , 0, 2}, /* DV0_DATA7  */
+    {PA_7  , 0, 2}, /* DV0_DATA6  */
+    {PB_0  , 0, 2}, /* DV0_DATA5  */
+    {PB_1  , 0, 2}, /* DV0_DATA4  */
+    {PB_2  , 0, 2}, /* DV0_DATA3  */
+    {PB_3  , 0, 2}, /* DV0_DATA2  */
+    {PB_4  , 0, 2}, /* DV0_DATA1  */
+    {PB_5  , 0, 2}, /* DV0_DATA0  */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_CEU_PIN[] = {
+    {P6_1  , 0, 2}, /* VIO_CLK    */
+    {P6_2  , 0, 2}, /* VIO_VD     */
+    {P6_3  , 0, 2}, /* VIO_HD     */
+    {PE_1  , 0, 2}, /* VIO_D7     */
+    {PE_2  , 0, 2}, /* VIO_D6     */
+    {PE_3  , 0, 2}, /* VIO_D5     */
+    {PE_4  , 0, 2}, /* VIO_D4     */
+    {PE_5  , 0, 2}, /* VIO_D3     */
+    {PE_6  , 0, 2}, /* VIO_D2     */
+    {PH_0  , 0, 2}, /* VIO_D1     */
+    {PH_1  , 0, 2}, /* VIO_D0     */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_LCD_DISP_PIN[] = {
+    {PB_5  , 0, 3}, /* LCD0_DATA23  */
+    {PB_4  , 0, 3}, /* LCD0_DATA22  */
+    {PB_3  , 0, 3}, /* LCD0_DATA21  */
+    {PB_2  , 0, 3}, /* LCD0_DATA20  */
+    {PB_1  , 0, 3}, /* LCD0_DATA19  */
+    {PB_0  , 0, 3}, /* LCD0_DATA18  */
+    {PA_7  , 0, 3}, /* LCD0_DATA17  */
+    {PA_6  , 0, 3}, /* LCD0_DATA16  */
+    {PA_5  , 0, 3}, /* LCD0_DATA15  */
+    {PA_4  , 0, 3}, /* LCD0_DATA14  */
+    {PA_3  , 0, 3}, /* LCD0_DATA13  */
+    {PA_2  , 0, 3}, /* LCD0_DATA12  */
+    {PA_1  , 0, 3}, /* LCD0_DATA11  */
+    {PA_0  , 0, 3}, /* LCD0_DATA10  */
+    {P8_0  , 0, 3}, /* LCD0_DATA9   */
+    {PF_0  , 0, 3}, /* LCD0_DATA8   */
+    {PF_1  , 0, 3}, /* LCD0_DATA7   */
+    {PF_2  , 0, 3}, /* LCD0_DATA6   */
+    {PF_3  , 0, 3}, /* LCD0_DATA5   */
+    {PF_4  , 0, 3}, /* LCD0_DATA4   */
+    {PF_5  , 0, 3}, /* LCD0_DATA3   */
+    {PF_6  , 0, 3}, /* LCD0_DATA2   */
+    {PH_2  , 0, 3}, /* LCD0_DATA1   */
+    {PF_7  , 0, 3}, /* LCD0_DATA0   */
+    {PC_3  , 0, 5}, /* LCD0_TCON4   */
+    {PC_4  , 0, 5}, /* LCD0_TCON3   */
+    {P7_7  , 0, 3}, /* LCD0_TCON0   */
+    {PJ_6  , 0, 3}, /* LCD0_CLK     */
+    {PJ_7  , 0, 3}, /* LCD0_EXTCLK  */
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_LVDS_DISP_PIN[] = {
+    {P4_0  , 0, 2}, /* TXOUT0P   */
+    {P4_1  , 0, 2}, /* TXOUT0M   */
+    {P4_2  , 0, 2}, /* TXOUT1P   */
+    {P4_3  , 0, 2}, /* TXOUT1M   */
+    {P4_4  , 0, 2}, /* TXOUT2P   */
+    {P4_5  , 0, 2}, /* TXOUT2P   */
+    {P4_6  , 0, 2}, /* TXCLKOUTP */
+    {P4_7  , 0, 2}, /* TXCLKOUTM */
+    {NC    , NC   , 0}
+};
+
+static const IRQn_Type vdc_irq_set_tbl[] = {
+    S0_VI_VSYNC0_IRQn,
+    S0_LO_VSYNC0_IRQn,
+    S0_VSYNCERR0_IRQn,
+    GR3_VLINE0_IRQn,
+    S0_VFIELD0_IRQn,
+    IV1_VBUFERR0_IRQn,
+    IV3_VBUFERR0_IRQn,
+    IV5_VBUFERR0_IRQn,
+    IV6_VBUFERR0_IRQn,
+    S0_WLINE0_IRQn,
+};
+
+static const uint32_t color_table256[CLUT8_TABLE_NUM] = {
+  0xFF000000u, 0xFF010101u, 0xFF020202u, 0xFF030303u, 0xFF040404u, 0xFF050505u, 0xFF060606u, 0xFF070707u, /*   0 -   7 */
+  0xFF080808u, 0xFF090909u, 0xFF0A0A0Au, 0xFF0B0B0Bu, 0xFF0C0C0Cu, 0xFF0D0D0Du, 0xFF0E0E0Eu, 0xFF0F0F0Fu, /*   8 -  15 */
+  0xFF101010u, 0xFF111111u, 0xFF121212u, 0xFF131313u, 0xFF141414u, 0xFF151515u, 0xFF161616u, 0xFF171717u, /*  16 -  23 */
+  0xFF181818u, 0xFF191919u, 0xFF1A1A1Au, 0xFF1B1B1Bu, 0xFF1C1C1Cu, 0xFF1E1E1Eu, 0xFF1E1E1Eu, 0xFF1F1F1Fu, /*  24 -  31 */
+  0xFF202020u, 0xFF212121u, 0xFF222222u, 0xFF232323u, 0xFF242424u, 0xFF252525u, 0xFF262626u, 0xFF272727u, /*  32 -  39 */
+  0xFF282828u, 0xFF292929u, 0xFF2A2A2Au, 0xFF2B2B2Bu, 0xFF2C2C2Cu, 0xFF2E2E2Eu, 0xFF2E2E2Eu, 0xFF2F2F2Fu, /*  40 -  47 */
+  0xFF303030u, 0xFF313131u, 0xFF323232u, 0xFF333333u, 0xFF343434u, 0xFF353535u, 0xFF363636u, 0xFF373737u, /*  48 -  55 */
+  0xFF383838u, 0xFF393939u, 0xFF3A3A3Au, 0xFF3B3B3Bu, 0xFF3C3C3Cu, 0xFF3E3E3Eu, 0xFF3E3E3Eu, 0xFF3F3F3Fu, /*  56 -  63 */
+  0xFF404040u, 0xFF414141u, 0xFF424242u, 0xFF434343u, 0xFF444444u, 0xFF454545u, 0xFF464646u, 0xFF474747u, /*  64 -  71 */
+  0xFF484848u, 0xFF494949u, 0xFF4A4A4Au, 0xFF4B4B4Bu, 0xFF4C4C4Cu, 0xFF4E4E4Eu, 0xFF4E4E4Eu, 0xFF4F4F4Fu, /*  72 -  79 */
+  0xFF505050u, 0xFF515151u, 0xFF525252u, 0xFF535353u, 0xFF545454u, 0xFF555555u, 0xFF565656u, 0xFF575757u, /*  80 -  87 */
+  0xFF585858u, 0xFF595959u, 0xFF5A5A5Au, 0xFF5B5B5Bu, 0xFF5C5C5Cu, 0xFF5E5E5Eu, 0xFF5E5E5Eu, 0xFF5F5F5Fu, /*  88 -  95 */
+  0xFF606060u, 0xFF616161u, 0xFF626262u, 0xFF636363u, 0xFF646464u, 0xFF656565u, 0xFF666666u, 0xFF676767u, /*  96 - 103 */
+  0xFF686868u, 0xFF696969u, 0xFF6A6A6Au, 0xFF6B6B6Bu, 0xFF6C6C6Cu, 0xFF6E6E6Eu, 0xFF6E6E6Eu, 0xFF6F6F6Fu, /* 104 - 111 */
+  0xFF707070u, 0xFF717171u, 0xFF727272u, 0xFF737373u, 0xFF747474u, 0xFF757575u, 0xFF767676u, 0xFF777777u, /* 112 - 119 */
+  0xFF787878u, 0xFF797979u, 0xFF7A7A7Au, 0xFF7B7B7Bu, 0xFF7C7C7Cu, 0xFF7E7E7Eu, 0xFF7E7E7Eu, 0xFF7F7F7Fu, /* 120 - 127 */
+  0xFF808080u, 0xFF818181u, 0xFF828282u, 0xFF838383u, 0xFF848484u, 0xFF858585u, 0xFF868686u, 0xFF878787u, /* 128 - 135 */
+  0xFF888888u, 0xFF898989u, 0xFF8A8A8Au, 0xFF8B8B8Bu, 0xFF8C8C8Cu, 0xFF8E8E8Eu, 0xFF8E8E8Eu, 0xFF8F8F8Fu, /* 136 - 143 */
+  0xFF909090u, 0xFF919191u, 0xFF929292u, 0xFF939393u, 0xFF949494u, 0xFF959595u, 0xFF969696u, 0xFF979797u, /* 144 - 151 */
+  0xFF989898u, 0xFF999999u, 0xFF9A9A9Au, 0xFF9B9B9Bu, 0xFF9C9C9Cu, 0xFF9E9E9Eu, 0xFF9E9E9Eu, 0xFF9F9F9Fu, /* 152 - 159 */
+  0xFFA0A0A0u, 0xFFA1A1A1u, 0xFFA2A2A2u, 0xFFA3A3A3u, 0xFFA4A4A4u, 0xFFA5A5A5u, 0xFFA6A6A6u, 0xFFA7A7A7u, /* 160 - 167 */
+  0xFFA8A8A8u, 0xFFA9A9A9u, 0xFFAAAAAAu, 0xFFABABABu, 0xFFACACACu, 0xFFAEAEAEu, 0xFFAEAEAEu, 0xFFAFAFAFu, /* 168 - 175 */
+  0xFFB0B0B0u, 0xFFB1B1B1u, 0xFFB2B2B2u, 0xFFB3B3B3u, 0xFFB4B4B4u, 0xFFB5B5B5u, 0xFFB6B6B6u, 0xFFB7B7B7u, /* 176 - 183 */
+  0xFFB8B8B8u, 0xFFB9B9B9u, 0xFFBABABAu, 0xFFBBBBBBu, 0xFFBCBCBCu, 0xFFBEBEBEu, 0xFFBEBEBEu, 0xFFBFBFBFu, /* 184 - 191 */
+  0xFFC0C0C0u, 0xFFC1C1C1u, 0xFFC2C2C2u, 0xFFC3C3C3u, 0xFFC4C4C4u, 0xFFC5C5C5u, 0xFFC6C6C6u, 0xFFC7C7C7u, /* 192 - 199 */
+  0xFFC8C8C8u, 0xFFC9C9C9u, 0xFFCACACAu, 0xFFCBCBCBu, 0xFFCCCCCCu, 0xFFCECECEu, 0xFFCECECEu, 0xFFCFCFCFu, /* 200 - 207 */
+  0xFFD0D0D0u, 0xFFD1D1D1u, 0xFFD2D2D2u, 0xFFD3D3D3u, 0xFFD4D4D4u, 0xFFD5D5D5u, 0xFFD6D6D6u, 0xFFD7D7D7u, /* 208 - 215 */
+  0xFFD8D8D8u, 0xFFD9D9D9u, 0xFFDADADAu, 0xFFDBDBDBu, 0xFFDCDCDCu, 0xFFDEDEDEu, 0xFFDEDEDEu, 0xFFDFDFDFu, /* 216 - 223 */
+  0xFFE0E0E0u, 0xFFE1E1E1u, 0xFFE2E2E2u, 0xFFE3E3E3u, 0xFFE4E4E4u, 0xFFE5E5E5u, 0xFFE6E6E6u, 0xFFE7E7E7u, /* 224 - 231 */
+  0xFFE8E8E8u, 0xFFE9E9E9u, 0xFFEAEAEAu, 0xFFEBEBEBu, 0xFFECECECu, 0xFFEEEEEEu, 0xFFEEEEEEu, 0xFFEFEFEFu, /* 232 - 239 */
+  0xFFF0F0F0u, 0xFFF1F1F1u, 0xFFF2F2F2u, 0xFFF3F3F3u, 0xFFF4F4F4u, 0xFFF5F5F5u, 0xFFF6F6F6u, 0xFFF7F7F7u, /* 240 - 247 */
+  0xFFF8F8F8u, 0xFFF9F9F9u, 0xFFFAFAFAu, 0xFFFBFBFBu, 0xFFFCFCFCu, 0xFFFEFEFEu, 0xFFFEFEFEu, 0xFFFFFFFFu  /* 248 - 255 */
+};
+
+static const uint32_t color_table16[CLUT4_TABLE_NUM] = {
+  0xFF000000u, 0xFF111111u, 0xFF222222u, 0xFF333333u, 0xFF444444u, 0xFF555555u, 0xFF666666u, 0xFF777777u, /*   0 -   7 */
+  0xFF888888u, 0xFF999999u, 0xFFAAAAAAu, 0xFFBBBBBBu, 0xFFCCCCCCu, 0xFFDDDDDDu, 0xFFEEEEEEu, 0xFFFFFFFFu  /*   8 -  15 */
+};
+
+static const uint32_t color_table2[CLUT1_TABLE_NUM] = {
+  0xFF000000u, 0xFFFFFFFFu
+};
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static drv_video_input_sel_t _drv_video_input_sel;
+
+static void init_func (const uint32_t user_num);
+static void DRV_Graphics_Irq_Set(vdc_int_type_t irq, uint32_t enable);
+
+/**************************************************************************//**
+ * @brief       User-defined function within R_VDC_Initialize
+ * @param[in]   user_num                : VDC5 channel
+ * @retval      None
+******************************************************************************/
+static void init_func (const uint32_t user_num)
+{
+    uint32_t            reg_data;
+    volatile uint8_t    dummy_read;
+
+    if ((vdc_channel_t)user_num == VDC_CHANNEL_0)
+    {
+        /* Standby control register 8 (STBCR8)
+            b1      ------0-;  MSTP81 : 0 : Video display controller channel 0 & LVDS enable */
+        reg_data    = (uint32_t)CPG.STBCR8.BYTE & (uint32_t)~STP81_BIT;
+        CPG.STBCR8.BYTE  = (uint8_t)reg_data;
+        /* In order to reflect the change, a dummy read should be done. */
+        dummy_read = CPG.STBCR8.BYTE;
+        (void)dummy_read;
+
+        /* Standby Request Register 2 (STBREQ2)
+            b5      --0-----;  STBRQ25 : The standby request to VDC channel 0 is invalid. */
+        reg_data    = (uint32_t)CPG.STBREQ2.BYTE & (uint32_t)~STBRQ25_BIT;
+        CPG.STBREQ2.BYTE = (uint8_t)reg_data;
+        /* Standby Acknowledge Register 2 (STBACK2)
+            b5      --*-----;  STBAK25 : Standby acknowledgment from VDC channel 0. */
+        while (((uint32_t)CPG.STBACK2.BYTE & (uint32_t)STBAK25_BIT) != 0u)
+        {
+            /* Wait for the STBAK25 to be cleared to 0. */
+        }
+    }
+}   /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   enable                  : VDC5 interrupt enable
+ * @retval      None
+******************************************************************************/
+static void DRV_Graphics_Irq_Set(vdc_int_type_t irq, uint32_t enable)
+{
+    vdc_channel_t          ch          = VDC_CHANNEL_0;
+    IRQn_Type IRQn;
+    IRQHandler handler;
+
+    IRQn = vdc_irq_set_tbl[irq];
+    handler = R_VDC_GetISR(ch, irq);
+
+    if (enable) {
+        InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+        GIC_SetPriority(IRQn, 5);
+        GIC_EnableIRQ(IRQn);
+    } else {
+        GIC_DisableIRQ(IRQn);
+    }
+} /* End of function DRV_Graphics_Irq_Set() */
+
+static void (* ceu_callback_func)(vdc5_int_type_t);
+static void Ceu_Irq_Handler_wrapper(ceu_int_type_t ceu_int_type) {
+    if ((ceu_callback_func != NULL) && ((ceu_int_type & CEU_INT_CPEIE) != 0)) {
+        ceu_callback_func(VDC_INT_TYPE_S0_VFIELD);
+    }
+}
+
+static void (* mipi_callback_func)(vdc5_int_type_t);
+static void Mipi_Irq_Handler_wrapper(e_mipi_interrupt_type_t mipi_int_type) {
+    if ((mipi_callback_func != NULL) && ((mipi_int_type & VIN_INT_VSYNC_FALL) != 0)) {
+        mipi_callback_func(VDC_INT_TYPE_S0_VFIELD);
+    }
+}
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   num                     : Interrupt line number
+ * @param[in]   * callback              : Interrupt callback function pointer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(
+    vdc5_int_type_t irq,
+    uint16_t num,
+    void (* callback)(vdc5_int_type_t)  )
+{
+    drv_graphics_error_t   drv_error   = DRV_GRAPHICS_OK;
+
+    if ((_drv_video_input_sel == DRV_INPUT_SEL_CEU) && (irq == VDC_INT_TYPE_S0_VFIELD)) {
+        /* ceu wrapper */
+        if (callback == NULL) {
+            R_CEU_InterruptDisable();
+            ceu_callback_func = NULL;
+        } else {
+            ceu_callback_func = callback;
+            R_CEU_InterruptEnable(CEU_INT_CPEIE, &Ceu_Irq_Handler_wrapper);
+        }
+    } else if ((_drv_video_input_sel == DRV_INPUT_SEL_MIPI) && (irq == VDC_INT_TYPE_S0_VFIELD)) {
+        /* mipi wrapper */
+        if (callback == NULL) {
+            R_MIPI_InterruptDisable();
+            mipi_callback_func = NULL;
+        } else {
+            st_mipi_int_t config;
+
+            mipi_callback_func = callback;
+            config.type           = VIN_INT_VSYNC_FALL;
+            config.p_mipiCallback = NULL;
+            config.p_vinCallback  = Mipi_Irq_Handler_wrapper;
+            config.line_num       = num;
+            R_MIPI_InterruptEnable(&config);
+        }
+    } else {
+        vdc_channel_t          ch          = VDC_CHANNEL_0;
+        vdc_error_t            error;
+        vdc_int_t              interrupt;
+
+        if( callback == NULL ) {
+            DRV_Graphics_Irq_Set( irq, 0 );
+        } else {
+            DRV_Graphics_Irq_Set( irq, 1 );
+        }
+
+        /* Interrupt parameter */
+        interrupt.type      = irq;        /* Interrupt type */
+        interrupt.line_num  = num ;       /* Line number */
+
+        /* Interrupt parameter */
+        interrupt.callback = callback;    /* Callback function pointer */
+        /* Set interrupt service routine */
+        error = R_VDC_CallbackISR(ch, &interrupt);
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error ;
+} /* End of function DRV_Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief       LCD output port initialization processing
+ * @param[in]   pin                     : Pin assign for LCD output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
+        pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
+        if (pin[count] == PJ_6) {
+            PORTJ.DSCR.BIT.DSCR6 = 0x3; /* PJ_6/LCD0_CLK 8mA */
+        }
+    }
+
+    return drv_error;
+} /* End of function DRV_Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       LVDS output port initialization processing
+ * @param[in]   pin                     : Pin assign for LVDS output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN);
+        pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Digital video inpout port initialization processing
+ * @param[in]   pin                     : Pin assign for digital video input port
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
+        pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       CEU inpout port initialization processing
+ * @param[in]   pin                     : Pin assign for digital video input port
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_CEU_Port_Init( PinName *pin, uint32_t pin_count )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint32_t count;
+
+    for( count = 0 ; count < pin_count ; count++ ) {
+        pinmap_peripheral(pin[count], PinMap_CEU_PIN);
+        pinmap_pinout(pin[count], PinMap_CEU_PIN);
+    }
+    return drv_error;
+} /* End of function DRV_Graphics_CEU_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Graphics initialization processing
+ * @param[in]   drv_lcd_config          : LCD configuration
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc_channel_t           ch          = VDC_CHANNEL_0;
+    vdc_error_t             error;
+    vdc_init_t              init;
+    double                  InputClock;
+    double                  OutputClock;
+    double                  diff_freq;
+    double                  non_pll_diff_freq = 200.0;
+    double                  pll_diff_freq;
+    int pll_dcdr = 0;
+    const int dcdr_tbl[] = {
+        1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 16, 24, 32
+    };
+    vdc_lvds_t              vdc_lvds;
+    pll_parameter_t         pll_parameter;
+    uint32_t                LvdsUsed;
+    vdc_panel_clksel_t      pll_panel_clksel;
+
+    if (RZ_A2_IsClockMode0() == false) {
+        InputClock = CM1_RENESAS_RZ_A2_P1_CLK / 1000000;
+    } else {
+        InputClock = CM0_RENESAS_RZ_A2_P1_CLK / 1000000;
+    }
+    OutputClock = drv_lcd_config->outputClock;
+
+    /* LVDS PLL Setting Calculation */
+    if( drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS ) {
+        LvdsUsed = LVDS_IF_USE;
+        pll_panel_clksel   = VDC_PANEL_ICKSEL_LVDS_DIV7;
+    } else {
+        LvdsUsed = LVDS_IF_NOT_USE;
+        pll_panel_clksel   = VDC_PANEL_ICKSEL_LVDS;
+
+        for (uint32_t i = 0; i < sizeof(dcdr_tbl); i++) {
+            diff_freq = fabs(OutputClock - (InputClock / dcdr_tbl[i]));
+            if (diff_freq < non_pll_diff_freq) {
+                pll_dcdr = dcdr_tbl[i];
+                non_pll_diff_freq = diff_freq;
+            }
+        }
+    }
+
+    lvds_pll_calc(InputClock, OutputClock, LvdsUsed, &pll_parameter);
+    pll_diff_freq = fabs(OutputClock - pll_parameter.output_freq);
+
+    if ((LvdsUsed == LVDS_IF_NOT_USE) && (non_pll_diff_freq <= pll_diff_freq)) {
+        init.panel_icksel   = VDC_PANEL_ICKSEL_PERI;      /* Panel clock select */
+        init.lvds           = NULL;                       /* LVDS parameter */
+    } else {
+        init.panel_icksel   = pll_panel_clksel;
+        vdc_lvds.lvds_in_clk_sel  = VDC_LVDS_INCLK_SEL_PERI; /* P1 */
+        vdc_lvds.lvds_idiv_set    = VDC_LVDS_NDIV_1;
+        vdc_lvds.lvdspll_tst      = 0u;
+        vdc_lvds.lvds_odiv_set    = (vdc_lvds_ndiv_t)((int)pll_parameter.nodiv / 2);
+        vdc_lvds.lvds_vdc_sel     = ch;
+        vdc_lvds.lvdspll_fd       = pll_parameter.nfd - 1;
+        vdc_lvds.lvdspll_rd       = pll_parameter.nrd - 1;
+        vdc_lvds.lvdspll_od       = VDC_LVDS_PLL_NOD_1;
+        pll_dcdr                  = (int)pll_parameter.dcdr;
+        init.lvds                 = &vdc_lvds;               /* LVDS parameter */
+    }
+
+    switch (pll_dcdr) {
+        case 1:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_1;  break;
+        case 2:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_2;  break;
+        case 3:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_3;  break;
+        case 4:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_4;  break;
+        case 5:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_5;  break;
+        case 6:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_6;  break;
+        case 7:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_7;  break;
+        case 8:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_8;  break;
+        case 9:  init.panel_dcdr = VDC_PANEL_CLKDIV_1_9;  break;
+        case 12: init.panel_dcdr = VDC_PANEL_CLKDIV_1_12; break;
+        case 16: init.panel_dcdr = VDC_PANEL_CLKDIV_1_16; break;
+        case 24: init.panel_dcdr = VDC_PANEL_CLKDIV_1_24; break;
+        case 32: init.panel_dcdr = VDC_PANEL_CLKDIV_1_32; break;
+        default: init.panel_dcdr = VDC_PANEL_CLKDIV_NUM;  break;
+    }
+
+    /* Initialize (Set module clock to VDC) */
+    error = R_VDC_Initialize( ch, &init, &init_func, (uint32_t)ch );
+    if (error != VDC_OK) {
+        drv_error = DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    if ( drv_error == DRV_GRAPHICS_OK ) {
+        vdc_sync_ctrl_t        sync_ctrl;
+
+        /* Sync signal control */
+        sync_ctrl.res_vs_sel    = VDC_ON;                              /* Vsync signal output select (free-running Vsync on/off control) */
+        /* Sync signal output and full-screen enable signal select */
+        sync_ctrl.res_vs_in_sel = VDC_RES_VS_IN_SEL_SC0;
+        sync_ctrl.res_fv        = drv_lcd_config->v_toatal_period-1;    /* Free-running Vsync period setting */
+        sync_ctrl.res_fh        = drv_lcd_config->h_toatal_period-1;    /* Hsync period setting */
+        sync_ctrl.res_vsdly     = (uint16_t)0u;                         /* Vsync signal delay control */
+        /* Full-screen enable control */
+        sync_ctrl.res_f.vs      = (drv_lcd_config->v_back_porch);
+        sync_ctrl.res_f.vw      = (drv_lcd_config->v_disp_widht);
+        sync_ctrl.res_f.hs      = (drv_lcd_config->h_back_porch);
+        sync_ctrl.res_f.hw      = (drv_lcd_config->h_disp_widht);
+        sync_ctrl.vsync_cpmpe   = NULL;                                 /* Vsync signal compensation */
+        /* Sync control */
+        error = R_VDC_SyncControl( ch, &sync_ctrl );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+
+    if ( drv_error == DRV_GRAPHICS_OK ) {
+        vdc_output_t           output;
+        vdc_lcd_tcon_timing_t  lcd_tcon_timing_VS;
+        vdc_lcd_tcon_timing_t  lcd_tcon_timing_VE;
+        vdc_lcd_tcon_timing_t  lcd_tcon_timing_HS;
+        vdc_lcd_tcon_timing_t  lcd_tcon_timing_HE;
+        vdc_lcd_tcon_timing_t  lcd_tcon_timing_DE;
+
+        /* Output parameter */
+        output.tcon_half        = (drv_lcd_config->h_toatal_period-1)/2; /* TCON reference timing, 1/2fH timing */
+        output.tcon_offset      = 0;                                     /* TCON reference timing, offset Hsync signal timing */
+
+        /* LCD TCON timing setting */
+        if( drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_VS.tcon_hsvs   = 0u;
+            lcd_tcon_timing_VS.tcon_hwvw   = (drv_lcd_config->v_sync_width * 2u);
+            lcd_tcon_timing_VS.tcon_md     = VDC_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_VS.tcon_hs_sel = VDC_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_VS.tcon_inv    = (vdc_sig_pol_t)drv_lcd_config->v_sync_port_polarity;
+            lcd_tcon_timing_VS.tcon_pin    = (vdc_lcd_tcon_pin_t)drv_lcd_config->v_sync_port;
+            lcd_tcon_timing_VS.outcnt_edge = VDC_EDGE_FALLING;
+            output.outctrl[VDC_LCD_TCONSIG_STVA_VS]   = &lcd_tcon_timing_VS;  /* STVA/VS: Vsync      */
+        } else {
+            output.outctrl[VDC_LCD_TCONSIG_STVA_VS]   = NULL;                 /* STVA/VS: Vsync      */
+        }
+
+        if( drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_HS.tcon_hsvs   = 0u;
+            lcd_tcon_timing_HS.tcon_hwvw   = drv_lcd_config->h_sync_width;
+            lcd_tcon_timing_HS.tcon_md     = VDC_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_HS.tcon_hs_sel = VDC_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_HS.tcon_inv    = (vdc_sig_pol_t)drv_lcd_config->h_sync_port_polarity;
+            lcd_tcon_timing_HS.tcon_pin    = (vdc_lcd_tcon_pin_t)drv_lcd_config->h_sync_port;
+            lcd_tcon_timing_HS.outcnt_edge = VDC_EDGE_FALLING;
+            output.outctrl[VDC_LCD_TCONSIG_STH_SP_HS]   = &lcd_tcon_timing_HS;  /* STH/SP/HS: Hsync       */
+        } else {
+            output.outctrl[VDC_LCD_TCONSIG_STH_SP_HS]   = NULL;                 /* STH/SP/HS: Hsync       */
+        }
+
+        if( drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON ) {
+            lcd_tcon_timing_VE.tcon_hsvs   = (drv_lcd_config->v_back_porch * 2u);
+            lcd_tcon_timing_VE.tcon_hwvw   = (drv_lcd_config->v_disp_widht * 2u);
+            lcd_tcon_timing_VE.tcon_md     = VDC_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_VE.tcon_hs_sel = VDC_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_VE.tcon_inv    = (vdc_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_VE.tcon_pin    = VDC_LCD_TCON_PIN_NON;
+            lcd_tcon_timing_VE.outcnt_edge = VDC_EDGE_FALLING;
+            output.outctrl[VDC_LCD_TCONSIG_STVB_VE]   = &lcd_tcon_timing_VE;  /* STVB/VE: Not used   */
+
+            lcd_tcon_timing_HE.tcon_hsvs   = drv_lcd_config->h_back_porch;
+            lcd_tcon_timing_HE.tcon_hwvw   = drv_lcd_config->h_disp_widht;
+            lcd_tcon_timing_HE.tcon_md     = VDC_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_HE.tcon_hs_sel = VDC_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_HE.tcon_inv    = (vdc_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_HE.tcon_pin    = VDC_LCD_TCON_PIN_NON;
+            lcd_tcon_timing_HE.outcnt_edge = VDC_EDGE_FALLING;
+            output.outctrl[VDC_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE;  /* STB/LP/HE: Not used */
+
+            lcd_tcon_timing_DE.tcon_hsvs   = 0u;
+            lcd_tcon_timing_DE.tcon_hwvw   = 0u;
+            lcd_tcon_timing_DE.tcon_md     = VDC_LCD_TCON_POLMD_NORMAL;
+            lcd_tcon_timing_DE.tcon_hs_sel = VDC_LCD_TCON_REFSEL_HSYNC;
+            lcd_tcon_timing_DE.tcon_inv    = (vdc_sig_pol_t)drv_lcd_config->de_port_polarity;
+            lcd_tcon_timing_DE.tcon_pin    = (vdc_lcd_tcon_pin_t)drv_lcd_config->de_port;
+            lcd_tcon_timing_DE.outcnt_edge = VDC_EDGE_FALLING;
+            output.outctrl[VDC_LCD_TCONSIG_DE]   = &lcd_tcon_timing_DE;  /* DE      */
+        } else {
+            output.outctrl[VDC_LCD_TCONSIG_STVB_VE]   = NULL;            /* STVB/VE: Not used   */
+            output.outctrl[VDC_LCD_TCONSIG_STB_LP_HE] = NULL;            /* STB/LP/HE: Not used */
+            output.outctrl[VDC_LCD_TCONSIG_DE]        = NULL;            /* DE                  */
+        }
+
+        output.outctrl[VDC_LCD_TCONSIG_CPV_GCK]   = NULL;
+        output.outctrl[VDC_LCD_TCONSIG_POLA]      = NULL;
+        output.outctrl[VDC_LCD_TCONSIG_POLB]      = NULL;
+
+        output.outcnt_lcd_edge  = (vdc_edge_t)drv_lcd_config->lcd_edge;  /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+        output.out_endian_on    = VDC_OFF;                               /* Bit endian change on/off control */
+        output.out_swap_on      = VDC_OFF;                               /* B/R signal swap on/off control */
+        output.out_format       = (vdc_lcd_outformat_t)drv_lcd_config->lcd_outformat;    /* Output format select */
+        output.out_frq_sel      = VDC_LCD_PARALLEL_CLKFRQ_1;             /* Clock frequency control */
+        output.out_dir_sel      = VDC_LCD_SERIAL_SCAN_FORWARD;           /* Scan direction select */
+        output.out_phase        = VDC_LCD_SERIAL_CLKPHASE_0;             /* Clock phase adjustment */
+        output.bg_color         = (uint32_t)0x00000000u;                  /* Background color in 24-bit RGB color format */
+        /* Display output */
+        error = R_VDC_DisplayOutput( ch, &output );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Init() */
+
+/**************************************************************************//**
+ * @brief       Video initialization processing
+ * @param[in]   drv_video_ext_in_config   : Video configuration
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc_error_t            error;
+    vdc_input_t            input;
+    vdc_ext_in_sig_t       ext_in_sig;
+    vdc_sync_delay_t       sync_delay;
+
+    if ((drv_video_input_sel != DRV_INPUT_SEL_EXT)
+     && (drv_video_input_sel != DRV_INPUT_SEL_CEU)
+     && (drv_video_input_sel != DRV_INPUT_SEL_MIPI)) {
+        return DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    _drv_video_input_sel = drv_video_input_sel;
+    if( drv_video_input_sel == DRV_INPUT_SEL_EXT ) {
+        input.inp_sel   = (vdc_input_sel_t)drv_video_input_sel; /* Input select */
+        input.inp_fh50  = (uint16_t)VSYNC_1_2_FH_TIMING;         /* Vsync signal 1/2fH phase timing */
+        input.inp_fh25  = (uint16_t)VSYNC_1_4_FH_TIMING;         /* Vsync signal 1/4fH phase timing */
+
+        ext_in_sig.inp_format     = (vdc_extin_format_t)drv_video_ext_in_config->inp_format;
+        ext_in_sig.inp_pxd_edge   = (vdc_edge_t)drv_video_ext_in_config->inp_pxd_edge;
+        ext_in_sig.inp_vs_edge    = (vdc_edge_t)drv_video_ext_in_config->inp_vs_edge;
+        ext_in_sig.inp_hs_edge    = (vdc_edge_t)drv_video_ext_in_config->inp_hs_edge;
+        ext_in_sig.inp_endian_on  = (vdc_onoff_t)drv_video_ext_in_config->inp_endian_on;
+        ext_in_sig.inp_swap_on    = (vdc_onoff_t)drv_video_ext_in_config->inp_swap_on;
+        ext_in_sig.inp_vs_inv     = (vdc_sig_pol_t)drv_video_ext_in_config->inp_vs_inv;
+        ext_in_sig.inp_hs_inv     = (vdc_sig_pol_t)drv_video_ext_in_config->inp_hs_inv;
+        ext_in_sig.inp_h_edge_sel = (vdc_extin_ref_hsync_t)drv_video_ext_in_config->inp_hs_edge;
+        ext_in_sig.inp_f525_625   = (vdc_extin_input_line_t)drv_video_ext_in_config->inp_f525_625;
+        ext_in_sig.inp_h_pos      = (vdc_extin_h_pos_t)drv_video_ext_in_config->inp_h_pos;
+
+        sync_delay.inp_vs_dly_l   = 0u;
+        sync_delay.inp_vs_dly     = 16u;
+        sync_delay.inp_hs_dly     = 16u;
+        sync_delay.inp_fld_dly    = 16u;
+
+        input.dly       = &sync_delay;   /* Sync signal delay adjustment */
+        input.ext_sig   = &ext_in_sig;   /* External input signal        */
+
+        /* Video input 0ch */
+        error = R_VDC_VideoInput( VDC_CHANNEL_0, &input );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    } else if (drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Initialize(&R_CEU_OnInitialize, 0);
+    } else if (drv_video_input_sel == DRV_INPUT_SEL_MIPI) {
+        R_MIPI_Initialize(&R_MIPI_OnInitialize, 0);
+    } else {
+        drv_error = DRV_GRAPHICS_VDC5_ERR;
+    }
+
+    return drv_error;
+}   /* End of function DRV_Video_Init() */
+
+/**************************************************************************//**
+ * @brief       Start the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      drv_graphics_error_t
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc_channel_t          ch          = VDC_CHANNEL_0;
+    vdc_error_t            error;
+    vdc_start_t            start;
+    vdc_gr_disp_sel_t      gr_disp_sel;
+    vdc_layer_id_t         vdc_layer_id;
+
+    switch( layer_id ) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc_layer_id   = VDC_LAYER_ID_0_RD;
+            gr_disp_sel     = VDC_DISPSEL_CURRENT;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc_layer_id   = VDC_LAYER_ID_2_RD;
+            gr_disp_sel     = VDC_DISPSEL_BLEND;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc_layer_id   = VDC_LAYER_ID_3_RD;
+            gr_disp_sel     = VDC_DISPSEL_BLEND;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Start process */
+        start.gr_disp_sel = &gr_disp_sel;
+        error = R_VDC_StartProcess( ch, vdc_layer_id, &start );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc_channel_t          ch          = VDC_CHANNEL_0;
+    vdc_error_t            error;
+    vdc_layer_id_t         vdc_layer_id;
+
+    switch( layer_id ) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc_layer_id   = VDC_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc_layer_id   = VDC_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc_layer_id   = VDC_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Stop process */
+        error = R_VDC_StopProcess ( ch, vdc_layer_id );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief      Start the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+
+    if (_drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Start();
+    } else if (_drv_video_input_sel == DRV_INPUT_SEL_MIPI) {
+        e_mipi_error_t mipi_error;
+        mipi_error = R_MIPI_CaptureStart(MIPI_CONTINUOUS_MODE);
+        if (mipi_error != MIPI_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    } else {
+        vdc_channel_t          ch          = VDC_CHANNEL_0;
+        vdc_error_t            error;
+        vdc_start_t            start;
+        vdc_gr_disp_sel_t      gr_disp_sel;
+        vdc_layer_id_t         vdc_layer_id;
+
+        if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+            vdc_layer_id   = VDC_LAYER_ID_0_WR;
+        } else {
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+        }
+
+        if( drv_error == DRV_GRAPHICS_OK ) {
+            /* Start process */
+            gr_disp_sel         = VDC_DISPSEL_CURRENT;    /* CURRENT fixed for weave input mode */
+            start.gr_disp_sel   = &gr_disp_sel;
+            error = R_VDC_StartProcess( ch, vdc_layer_id, &start );
+            if (error != VDC_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+	}
+    return drv_error;
+}   /* End of function DRV_Video_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+
+    if (_drv_video_input_sel == DRV_INPUT_SEL_CEU) {
+        R_CEU_Stop();
+    } else if (_drv_video_input_sel == DRV_INPUT_SEL_MIPI) {
+        R_MIPI_CaptureStop();
+    } else {
+        vdc_channel_t          ch          = VDC_CHANNEL_0;
+        vdc_error_t            error;
+        vdc_layer_id_t         vdc_layer_id;
+
+        switch (video_input_ch) {
+            case DRV_VIDEO_INPUT_CHANNEL_0:
+                vdc_layer_id   = VDC_LAYER_ID_0_WR;
+                break;
+            default:
+                drv_error = DRV_GRAPHICS_LAYER_ERR;
+                break;
+        }
+
+        if( drv_error == DRV_GRAPHICS_OK ) {
+            /* Stop process */
+            error = R_VDC_StopProcess ( ch, vdc_layer_id );
+            if (error != VDC_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Stop() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process setting
+ *
+ *              Description:<br>
+ *              This function supports the following 4 image format.
+ *                  YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @param[in]   gr_format               : Format of the frame buffer read signal
+ * @param[in]   gr_rect                 : Graphics display area
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Setting (
+    drv_graphics_layer_t        layer_id,
+    void                      * framebuff,
+    uint32_t                    fb_stride,
+    drv_graphics_format_t       gr_format,
+    drv_wr_rd_swa_t             wr_rd_swa,
+    drv_rect_t                * gr_rect,
+    drv_clut_t                * gr_clut )
+
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc_channel_t          ch          = VDC_CHANNEL_0;
+    vdc_error_t            error;
+    vdc_layer_id_t         vdc_layer_id;
+    vdc_gr_format_t        vdc_gr_format;
+    vdc_read_t             read;
+
+    switch(layer_id) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc_layer_id = VDC_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc_layer_id = VDC_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc_layer_id = VDC_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        switch( gr_format ) {
+            case DRV_GRAPHICS_FORMAT_YCBCR422:
+                vdc_gr_format = VDC_GR_FORMAT_YCBCR422;
+                break;
+            case DRV_GRAPHICS_FORMAT_RGB565:
+                vdc_gr_format = VDC_GR_FORMAT_RGB565;
+                break;
+            case DRV_GRAPHICS_FORMAT_RGB888:
+                vdc_gr_format = VDC_GR_FORMAT_RGB888;
+                break;
+            case DRV_GRAPHICS_FORMAT_ARGB8888:
+                vdc_gr_format = VDC_GR_FORMAT_ARGB8888;
+                break;
+            case DRV_GRAPHICS_FORMAT_ARGB4444:
+                vdc_gr_format = VDC_GR_FORMAT_ARGB4444;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT8:
+                vdc_gr_format = VDC_GR_FORMAT_CLUT8;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT4:
+                vdc_gr_format = VDC_GR_FORMAT_CLUT4;
+                break;
+            case DRV_GRAPHICS_FORMAT_CLUT1:
+                vdc_gr_format = VDC_GR_FORMAT_CLUT1;
+                break;
+            default:
+                drv_error = DRV_GRAPHICS_FORMAT_ERR;
+                break;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Read data parameter */
+        read.gr_ln_off_dir  = VDC_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+        read.gr_flm_sel     = VDC_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+        read.gr_imr_flm_inv = VDC_OFF;                 /* Frame buffer number for distortion correction */
+        read.gr_bst_md      = VDC_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+        read.gr_base        = framebuff;                /* Frame buffer base address */
+        read.gr_ln_off      = fb_stride;                /* Frame buffer line offset address */
+
+        read.width_read_fb  = NULL;                     /* Width of the image read from frame buffer */
+
+        read.adj_sel        = VDC_OFF;                 /* Measures to decrease the influence
+                                                           by folding pixels/lines (on/off) */
+        read.gr_format      = vdc_gr_format;           /* Format of the frame buffer read signal */
+        read.gr_ycc_swap    = VDC_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
+                                                           in the YCbCr422 format */
+        read.gr_rdswa       = (vdc_wr_rd_swa_t)wr_rd_swa; /* Frame buffer swap setting */
+        /* Display area */
+        read.gr_grc.vs      = gr_rect->vs;
+        read.gr_grc.vw      = gr_rect->vw;
+        read.gr_grc.hs      = gr_rect->hs;
+        read.gr_grc.hw      = gr_rect->hw;
+
+        /* Read data control */
+        error = R_VDC_ReadDataControl( ch, vdc_layer_id, &read );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if ((vdc_gr_format == VDC_GR_FORMAT_CLUT8)
+         || (vdc_gr_format == VDC_GR_FORMAT_CLUT4)
+         || (vdc_gr_format == VDC_GR_FORMAT_CLUT1)) {
+            vdc_clut_t vdc_clut;
+
+            if (gr_clut != NULL) {
+                vdc_clut.color_num = gr_clut->color_num;
+                vdc_clut.clut = gr_clut->clut;
+            } else if (vdc_gr_format == VDC_GR_FORMAT_CLUT8) {
+                vdc_clut.color_num = CLUT8_TABLE_NUM;
+                vdc_clut.clut = color_table256;
+            } else if (vdc_gr_format == VDC_GR_FORMAT_CLUT4) {
+                vdc_clut.color_num = CLUT4_TABLE_NUM;
+                vdc_clut.clut = color_table16;
+            } else {
+                vdc_clut.color_num = CLUT1_TABLE_NUM;
+                vdc_clut.clut = color_table2;
+            }
+            error = R_VDC_CLUT(ch, vdc_layer_id, &vdc_clut);
+            if (error != VDC_OK) {
+                drv_error = DRV_GRAPHICS_VDC5_ERR;
+            }
+        }
+    }
+
+    return drv_error;
+}   /* End of function DRV_Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read buffer change process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Change (
+    drv_graphics_layer_t    layer_id,
+    void                 *  framebuff)
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    vdc_channel_t          ch          = VDC_CHANNEL_0;
+    vdc_error_t            error;
+    vdc_layer_id_t         vdc_layer_id;
+    vdc_read_chg_t         read_chg;
+
+    switch(layer_id) {
+        case DRV_GRAPHICS_LAYER_0:
+            vdc_layer_id = VDC_LAYER_ID_0_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_2:
+            vdc_layer_id = VDC_LAYER_ID_2_RD;
+            break;
+        case DRV_GRAPHICS_LAYER_3:
+            vdc_layer_id = VDC_LAYER_ID_3_RD;
+            break;
+        default:
+            drv_error = DRV_GRAPHICS_LAYER_ERR;
+            break;
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Read data parameter */
+        read_chg.width_read_fb  = NULL;         /* Width of the image read from frame buffer */
+        read_chg.gr_grc         = NULL;         /* Display area */
+        read_chg.gr_disp_sel    = NULL;         /* Graphics display mode */
+        read_chg.gr_base        = framebuff;     /* Frame buffer base address */
+
+        /* Change read process */
+        error = R_VDC_ChangeReadProcess( ch, vdc_layer_id, &read_chg );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Graphics_Read_Change() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting
+ *
+ *              Description:<br>
+ *              This function set the video write process. Input form is weave
+ *              (progressive) mode fixed.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   video_input_ch          : Video input channel
+ * @param[in]   col_sys                 : Analog video signal color system
+ * @param[in]   adc_vinsel              : Video input pin
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   video_adc_vinsel        : Input pin control
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting (
+    drv_video_input_channel_t       video_input_ch,
+    drv_graphics_video_col_sys_t    col_sys,
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_adc_vinsel_t          video_adc_vinsel )
+{
+    return DRV_GRAPHICS_VDC5_ERR;
+}   /* End of function DRV_Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting for digital input
+ *
+ *              Description:<br>
+ *              This function set the video write process for digital input.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   cap_area                : Capture area
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting_Digital (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_rect_t                    * cap_area )
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    vdc_channel_t              ch          = VDC_CHANNEL_0;
+    vdc_error_t                error;
+    vdc_layer_id_t             vdc_layer_id;
+    vdc_write_t                write;
+    vdc_scalingdown_rot_t    * scldw_rot;
+    vdc_res_md_t               res_md;
+
+    vdc_layer_id = VDC_LAYER_ID_0_WR;
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        if( video_format == DRV_VIDEO_FORMAT_YCBCR422 ) {
+            res_md = VDC_RES_MD_YCBCR422;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB888 ) {
+            res_md = VDC_RES_MD_RGB888;
+        } else if( video_format == DRV_VIDEO_FORMAT_RGB565 ) {
+            res_md = VDC_RES_MD_RGB565;
+        } else {
+            drv_error = DRV_GRAPHICS_FORMAT_ERR;
+        }
+    }
+
+    if( drv_error == DRV_GRAPHICS_OK ) {
+        /* Scaling-down and rotation parameter */
+        scldw_rot = &write.scalingdown_rot;
+        /* Image area to be captured */
+        scldw_rot->res.vs   = (uint16_t)((uint32_t)cap_area->vs - 1u);
+        scldw_rot->res.vw   = cap_area->vw;
+        scldw_rot->res.hs   = cap_area->hs;
+        scldw_rot->res.hw   = cap_area->hw;
+
+        /* Write data parameter */
+        scldw_rot->res_pfil_sel = VDC_ON;                   /* Prefilter mode select for brightness signals (on/off) */
+        scldw_rot->res_out_vw   = video_write_buff_vw ;      /* Number of valid lines in vertical direction
+                                                                output by scaling-down control block */
+        scldw_rot->res_out_hw   = video_write_buff_hw;       /* Number of valid horizontal pixels
+                                                                output by scaling-down control block */
+        scldw_rot->adj_sel      = VDC_ON;                   /* Measures to decrease the influence
+                                                                by lack of last-input line (on/off) */
+        scldw_rot->res_ds_wr_md = VDC_WR_MD_NORMAL;         /* Frame buffer writing mode */
+        write.res_wrswa     = (vdc_wr_rd_swa_t)wr_rd_swa;   /* Frame buffer swap setting */
+        write.res_md        = res_md;                        /* Frame buffer video-signal writing format */
+        write.res_bst_md    = VDC_BST_MD_32BYTE;            /* Transfer burst length for frame buffer */
+        write.res_inter     = VDC_RES_INTER_PROGRESSIVE;    /* Field operating mode select */
+        write.res_fs_rate   = VDC_RES_FS_RATE_PER1;         /* Writing rate */
+        write.res_fld_sel   = VDC_RES_FLD_SEL_TOP;          /* Write field select */
+        write.res_dth_on    = VDC_ON;                       /* Dither correction on/off */
+        write.base          = framebuff;                     /* Frame buffer base address */
+        write.ln_off        = fb_stride;
+        /* Frame buffer line offset address [byte] */
+        write.flm_num       = (uint32_t)(1u - 1u);           /* Number of frames of buffer (res_flm_num + 1) */
+        /* Frame buffer frame offset address */
+        write.flm_off       = fb_stride * (uint32_t)scldw_rot->res_out_vw;
+        write.btm_base      = NULL;                          /* Frame buffer base address for bottom */
+
+        /* Write data control */
+        error = R_VDC_WriteDataControl( ch, vdc_layer_id, &write );
+        if (error != VDC_OK) {
+            drv_error = DRV_GRAPHICS_VDC5_ERR;
+        }
+    }
+    return drv_error;
+}   /* End of function DRV_Video_Write_Setting_Digital() */
+
+drv_graphics_error_t DRV_Video_Write_Setting_Ceu (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_ext_in_config_t     * drv_video_ext_in_config)
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    ceu_cap_rect_t              ceu_cap;
+    ceu_config_t                ceu_config;
+
+    if (video_format != DRV_VIDEO_FORMAT_YCBCR422) {
+        return DRV_GRAPHICS_FORMAT_ERR;
+    }
+
+    /* CEU mode */
+    ceu_config.jpg = CEU_DATA_SYNC_MODE;
+
+    /* Capture timing */
+    if (drv_video_ext_in_config->cap_hs_pos <= 100) {
+        ceu_cap.hofst = drv_video_ext_in_config->cap_hs_pos * 4;
+    } else {
+        ceu_cap.hofst = 0;
+    }
+    if (drv_video_ext_in_config->cap_vs_pos >= 10) {
+        ceu_cap.vofst = drv_video_ext_in_config->cap_vs_pos * 4;
+    } else {
+        ceu_cap.vofst = 0;
+    }
+    ceu_cap.hwdth = video_write_buff_hw * 2;
+    ceu_cap.vwdth = video_write_buff_vw;
+    ceu_config.cap = &ceu_cap;
+
+    /* Capture Filter Size (Set this param if Image capture mode.) */
+    ceu_config.clp = NULL;
+
+    /* Data bus */
+    ceu_config.dtif = CEU_8BIT_DATA_PINS; /* Data pin 8bit  */
+
+    /* Write Data Swap */
+    switch (wr_rd_swa) {
+        default:
+        case DRV_WR_RD_WRSWA_NON:               /* Not swapped: 1-2-3-4-5-6-7-8 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_8BIT:              /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_16BIT:             /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_16_8BIT:           /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+            ceu_config.cols = CEU_OFF;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_32BIT:             /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_32_8BIT:           /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_OFF;
+            ceu_config.cobs = CEU_ON;
+            break;
+        case DRV_WR_RD_WRSWA_32_16BIT:          /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_OFF;
+            break;
+        case DRV_WR_RD_WRSWA_32_16_8BIT:        /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+            ceu_config.cols = CEU_ON;
+            ceu_config.cows = CEU_ON;
+            ceu_config.cobs = CEU_ON;
+            break;
+    }
+
+    /* input order */
+    switch (drv_video_ext_in_config->inp_h_pos) {
+        default:
+        case DRV_EXTIN_H_POS_CBYCRY:        /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+            ceu_config.dtary = CEU_CB0_Y0_CR0_Y1;
+            if (ceu_config.cows == CEU_ON) {
+                ceu_config.cows = CEU_OFF;
+            } else {
+                ceu_config.cows = CEU_ON;
+            }
+            break;
+        case DRV_EXTIN_H_POS_YCRYCB:        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+            ceu_config.dtary = CEU_Y0_CR0_Y1_CB0;
+            if (ceu_config.cobs == CEU_ON) {
+                ceu_config.cobs = CEU_OFF;
+            } else {
+                ceu_config.cobs = CEU_ON;
+            }
+            if (ceu_config.cows == CEU_ON) {
+                ceu_config.cows = CEU_OFF;
+            } else {
+                ceu_config.cows = CEU_ON;
+            }
+            break;
+        case DRV_EXTIN_H_POS_CRYCBY:        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+            ceu_config.dtary = CEU_CR0_Y0_CB0_Y1;
+            break;
+        case DRV_EXTIN_H_POS_YCBYCR:        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+            ceu_config.dtary = CEU_Y0_CB0_Y1_CR0;
+            if (ceu_config.cobs == CEU_ON) {
+                ceu_config.cobs = CEU_OFF;
+            } else {
+                ceu_config.cobs = CEU_ON;
+            }
+            break;
+    }
+
+    /* Signal polarity */
+    /* Hsync */
+    if (drv_video_ext_in_config->inp_hs_inv == DRV_SIG_POL_NOT_INVERTED) {
+        ceu_config.hdpol = CEU_HIGH_ACTIVE;
+    } else {
+        ceu_config.hdpol = CEU_LOW_ACTIVE;
+    }
+    if (drv_video_ext_in_config->cap_hs_pos >= 100) {
+        /* inverted */
+        if (ceu_config.hdpol == CEU_HIGH_ACTIVE) {
+            ceu_config.hdpol = CEU_LOW_ACTIVE;
+        } else {
+            ceu_config.hdpol = CEU_HIGH_ACTIVE;
+        }
+    }
+
+    /* Vsync */
+    if (drv_video_ext_in_config->inp_vs_inv == DRV_SIG_POL_NOT_INVERTED) {
+        ceu_config.vdpol = CEU_HIGH_ACTIVE;
+    } else {
+        ceu_config.vdpol = CEU_LOW_ACTIVE;
+    }
+
+    R_CEU_Open(&ceu_config);
+    R_CEU_Execute_Setting(framebuff, (void *)NULL, fb_stride, CEU_ON);
+
+    return drv_error;
+}
+
+drv_graphics_error_t DRV_Video_Write_Setting_Mipi (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_mipi_param_t              * mipi_data,
+    drv_vin_setup_t               * vin_setup)
+{
+    drv_graphics_error_t        drv_error   = DRV_GRAPHICS_OK;
+    e_mipi_error_t result;
+    int i;
+
+    /* Initial setting of MIPI / VIN */
+    R_MIPI_Open((st_mipi_param_t *)mipi_data);
+
+    drv_vin_setup_t wk_vin_setup = *vin_setup;
+    wk_vin_setup.vin_preclip.vin_preclip_endy = vin_setup->vin_preclip.vin_preclip_starty + video_write_buff_vw - 1;
+    wk_vin_setup.vin_preclip.vin_preclip_endx = vin_setup->vin_preclip.vin_preclip_startx + video_write_buff_hw - 1;
+    wk_vin_setup.vin_stride = fb_stride;
+
+    switch (video_format) {
+        case DRV_VIDEO_FORMAT_YCBCR422:
+            wk_vin_setup.vin_outputformat = VIN_OUTPUT_YCBCR422_8;
+            break;
+        case DRV_VIDEO_FORMAT_RGB565:
+            wk_vin_setup.vin_outputformat = VIN_OUTPUT_RGB565;
+            break;
+        case DRV_VIDEO_FORMAT_RGB888:
+            wk_vin_setup.vin_outputformat = VIN_OUTPUT_ARGB8888;
+            break;
+        case DRV_VIDEO_FORMAT_RAW8:
+            wk_vin_setup.vin_outputformat = VIN_OUTPUT_RAW8;
+            break;
+    }
+
+    result = R_MIPI_Setup((st_vin_setup_t *)&wk_vin_setup);
+    if (result != MIPI_OK) {
+        drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR;
+    }
+
+    for (i = 0 ; i < 3; i++) {
+        R_MIPI_SetBufferAdr(i, (uint8_t *)framebuff);
+    }
+
+    return drv_error;
+}
+
+/**************************************************************************//**
+ * @brief       Video surface write buffer change process
+ * @param[in]   video_input_ch          : Video input channle
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Change (
+    drv_video_input_channel_t     video_input_ch,
+    void                        * framebuff,
+    uint32_t                      fb_stride )
+{
+    drv_graphics_error_t    drv_error   = DRV_GRAPHICS_OK;
+    uint8_t               * framebuffer_t;
+    uint8_t               * framebuffer_b;
+
+    framebuffer_t = (uint8_t *)((uint32_t)framebuff & ~0x1F);
+    framebuffer_b = &framebuffer_t[fb_stride];
+
+    if( video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0 ) {
+        VDC6.SC0_SCL1_WR2.LONG = (uint32_t)framebuffer_t;
+        VDC6.SC0_SCL1_WR8.LONG = (uint32_t)framebuffer_b;
+        VDC6.SC0_SCL1_UPDATE.LONG = 0x10;
+    } else {
+        drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+    }
+    return drv_error;
+} /* End of function DRV_Video_Write_Change() */
+
+/* End of file */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/ceu/inc/r_ceu.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,200 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ *******************************************************************************/
+/**************************************************************************//**
+ * File Name :   r_ceu.h
+ * @file         r_ceu.h
+ * @version      1.00
+ * $Rev: 182 $
+ * $Date:: 2017-05-11 07:35:51 +0900#$
+ * @brief        CEU driver header
+ ******************************************************************************/
+
+#ifndef R_CEU_H
+#define R_CEU_H
+
+/******************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "r_ceu_user.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+ Typedef definitions
+ ******************************************************************************/
+/*! @enum ceu_onoff_t
+ *  @brief On/off
+ */
+typedef enum
+{
+    CEU_OFF = 0, /*!< Off */
+    CEU_ON, /*!< On  */
+} ceu_onoff_t;
+
+/*! @enum ceu_jpg_t
+ *  @brief Select the fetched data type
+ */
+typedef enum
+{
+    CEU_IMAGE_CAPTURE_MODE = 0, /*!< Image capture mode          */
+    CEU_DATA_SYNC_MODE, /*!< Data synchronous fetch mode */
+    CEU_DATA_ENABLE_MODE /*!< Data enable fetch mode      */
+} ceu_jpg_t;
+
+/*! @enum ceu_dtif_t
+ *  @brief The digital image input pins from which data is to be captured
+ */
+typedef enum
+{
+    CEU_8BIT_DATA_PINS = 0, /*!<  8-bit digital image input pins */
+    CEU_16BIT_DATA_PINS /*!< 16-bit digital image input pins */
+} ceu_dtif_t;
+
+/*! @enum ceu_sig_pol_t
+ *  @brief The polarity for detection of the vertical sync signal and the horizontal sync signal.
+ */
+typedef enum
+{
+    CEU_HIGH_ACTIVE = 0, /*!< High active */
+    CEU_LOW_ACTIVE /*!< Low active  */
+} ceu_sig_pol_t;
+
+/*! @enum ceu_dtary_t
+ *  @brief The input order of the luminance component and chrominance component
+ */
+typedef enum
+{
+    CEU_CB0_Y0_CR0_Y1 = 0, /*!< Image input data is fetched in the order of Cb0, Y0, Cr0, and Y1 */
+    CEU_CR0_Y0_CB0_Y1, /*!< Image input data is fetched in the order of Cr0, Y0, Cb0, and Y1 */
+    CEU_Y0_CB0_Y1_CR0, /*!< Image input data is fetched in the order of Y0, Cb0, Y1, and Cr0 */
+    CEU_Y0_CR0_Y1_CB0 /*!< Image input data is fetched in the order of Y0, Cr0, Y1, and Cb0 */
+} ceu_dtary_t;
+
+/*! @enum ceu_int_type_t
+ *  @brief Capture Event Interrupt Enable flag
+ */
+typedef enum
+{
+    CEU_INT_CPEIE = (0x00000001u), /*!< One Frame capture end interrupt */
+    CEU_INT_CFEIE = (0x00000002u), /*!< One Filed capture end interrupt */
+    CEU_INT_IGRWIE = (0x00000010u), /*!< illegal register write interrupt */
+    CEU_INT_HDIE = (0x00000100u), /*!< HD interrupt */
+    CEU_INT_VDIE = (0x00000200u), /*!< VD interrupt */
+    CEU_INT_CPBE1IE = (0x00001000u), /*!< bundle write complete interrupt (TOP field) */
+    CEU_INT_CPBE2IE = (0x00002000u), /*!< bundle write complete interrupt (TOP field2) */
+    CEU_INT_CPBE3IE = (0x00004000u), /*!< bundle write complete interrupt (Bottom field) */
+    CEU_INT_CPBE4IE = (0x00008000u), /*!< bundle write complete interrupt (Bottom field2) */
+    CEU_INT_CDTOFIE = (0x00010000u), /*!< CRAM data overflow interrupt */
+    CEU_INT_IGHSIE = (0x00020000u), /*!< illegal H-Sync interrupt */
+    CEU_INT_IGVSIE = (0x00040000u), /*!< illegal V-Sync interrupt */
+    CEU_INT_VBPIE = (0x00100000u), /*!< insufficient vertical sync front porch interrupt */
+    CEU_INT_FWFIE = (0x00800000u), /*!< FW FAILED interrupt */
+    CEU_INT_NHDIE = (0x01000000u), /*!< Non-HD Interrupt */
+    CEU_INT_NVDIE = (0x02000000u) /*!< Non-VD Interrupt */
+} ceu_int_type_t;
+
+/*! @enum ceu_error_t
+ *  @brief Error codes of the CEU driver
+ */
+typedef enum
+{
+    CEU_OK = 0, /*!< Normal termination        */
+    CEU_ERR_PARAM, /*!< Parameter error           */
+    CEU_ERR_NUM /*!< The number of error codes */
+} ceu_error_t;
+
+/*! @struct ceu_cap_rect_t
+ *  @brief The horizontal/vertical timing of the Capture signals
+ */
+typedef struct
+{
+    uint32_t vofst; /*!< The capture start location in terms of the HD count from a vertical sync signal (1-HD units) */
+    uint32_t vwdth; /*!< The vertical capture period (4-HD units). */
+    uint32_t hofst; /*!< The capture start location in terms of the number of clock cycles from a horizontal sync signal (1-cycle units). */
+    uint32_t hwdth; /*!< The horizontal capture period
+     - Image capture mode( 8-bit)           8 cycle units
+     - Data synchronous fetch mode( 8-bit)  4 cycle units
+     - Image capture mode(16-bit)           4 cycle units
+     - Data synchronous fetch mode(16-bit)  2 cycle units */
+} ceu_cap_rect_t;
+
+/*! @struct ceu_clp_t
+ *  @brief Capture Filter Size (Set this param if Image capture mode.)
+ */
+typedef struct
+{
+    uint32_t vfclp; /*!< Vertical clipping value   (4-pixel unit) */
+    uint32_t hfclp; /*!< Horizontal clipping value (4-pixel unit) */
+} ceu_clp_t;
+
+/*! @struct ceu_config_t
+ *  @brief CEU config
+ */
+typedef struct
+{
+    ceu_jpg_t jpg; /*!< Select the fetched data type */
+    ceu_dtif_t dtif; /*!< Sets the digital image input pins from which data is to be captured  */
+    ceu_sig_pol_t vdpol; /*!< Sets the polarity for detection of the vertical sync signal          */
+    ceu_sig_pol_t hdpol; /*!< Sets the polarity for detection of the horizontal sync signal        */
+    ceu_dtary_t dtary; /*!< Sets the input order of the luminance component and chrominance component */
+    ceu_cap_rect_t * cap; /*!< The horizontal/vertical timing of the Capture signals */
+    ceu_clp_t * clp; /*!< Capture Filter Size (Set this param if Image capture mode.)*/
+    ceu_onoff_t cols; /*!< Controls swapping in 32-bit units for data output */
+    ceu_onoff_t cows; /*!< Controls swapping in 16-bit units for data output */
+    ceu_onoff_t cobs; /*!< Controls swapping in  8-bit units for data output */
+} ceu_config_t;
+
+/******************************************************************************
+ Macro definitions
+ ******************************************************************************/
+
+/******************************************************************************
+ Variable Externs
+ ******************************************************************************/
+
+/******************************************************************************
+ Functions Prototypes
+ ******************************************************************************/
+void R_CEU_Initialize(void (* const init_func)(uint32_t), const uint32_t user_num);
+ceu_error_t R_CEU_Open(const ceu_config_t * const config);
+ceu_error_t R_CEU_Execute(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture);
+ceu_error_t R_CEU_Terminate(void (* const quit_func)(uint32_t), const uint32_t user_num);
+void R_CEU_InterruptEnable(const ceu_int_type_t int_type, void (* const callback)(ceu_int_type_t));
+void R_CEU_InterruptDisable(void);
+void R_CEU_Isr(const uint32_t int_sense);
+ceu_error_t R_CEU_Stop(void);
+#if(1) /* mbed */
+ceu_error_t R_CEU_Execute_Setting(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture);
+ceu_error_t R_CEU_Start(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* R_CEU_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/ceu/inc/r_ceu_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_ceu_user.h
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L CEU driver user-defined header
+******************************************************************************/
+
+#ifndef R_CEU_USER_H
+#define R_CEU_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+uint32_t R_CEU_CPUVAddrToSysPAddr(uint32_t vaddr);
+void R_CEU_OnInitialize(const uint32_t user_num);
+void R_CEU_OnFinalize(const uint32_t user_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* R_CEU_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/ceu/src/r_ceu_driver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,835 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+ *******************************************************************************/
+/**************************************************************************//**
+ * File Name :   r_ceu_driver.c
+ * @file         r_ceu_driver.c
+ * @version      1.00
+ * $Rev: 200 $
+ * $Date:: 2017-05-17 15:19:00 +0900#$
+ * @brief        CEU driver API functions
+ ******************************************************************************/
+
+/******************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ******************************************************************************/
+#include "r_typedefs.h"
+#include "r_ceu.h"
+
+/******************************************************************************
+ Typedef definitions
+ ******************************************************************************/
+
+/******************************************************************************
+ Macro definitions
+ ******************************************************************************/
+#define CEU_SW_RESET        (0x00010000u)
+#define CAPSR_CPKIL_BIT     (0x00010000u)
+#define CSTSR_CPTON_BIT     (0x00000001u)
+#define CAPSR_CE_BIT        (0x00000001u)
+
+/* Driver is not supported register vale */
+#define CAPCR_FDRP_VALUE    (0u)      /* The frame drop count is 0               */
+#define CAPCR_MTCM_VALUE    (0u)      /* Transferred to the bus in 32-byte units */
+#define CAPCR_CTNCP_VALUE   (0u)      /* One-frame capture                       */
+#define CAIFR_IFS_VALUE     (0u)      /* Progressive */
+#define CAIFR_CIM_VALUE     (0u)      /* Capture of frame image (1 VD) or both-field image (2 VD) */
+#define CAIFR_FC_VALUE      (0u)      /* Capture starts from the VD input immediately after
+                                         the CEU activation regardless of it being a top or bottom field */
+#define CRCNTR_RVS_VALUE    (0u)      /* Switches the register plane every 2 VD */
+#define CRCNTR_RS_VALUE     (0u)      /* Uses plane A of the register */
+#define CRCNTR_RC_VALUE     (0u)      /* Uses the specified register plane in synchronization with VD */
+#define CFLCR_VMANT_VALUE   (0u)      /* Mantissa Part of Vertical Scale-Down Factor */
+#define CFLCR_VFRAC_VALUE   (0u)      /* Fraction Part of Vertical Scale-Down Factor */
+#define CFLCR_HMANT_VALUE   (0u)      /* Mantissa Part of Horizontal Scale-Down Factor */
+#define CFLCR_HFRAC_VALUE   (0u)      /* Fraction Part of Horizontal Scale-Down Factor */
+#define CMCYR_VCYL_VALUE    (0u)      /* Vertical HD Count for illegal VD is 0      */
+#define CMCYR_HCYL_VALUE    (0u)      /* Horizontal Cycle Count for illegal HD is 0 */
+#define CLFCR_LPF_VALUE     (0u)      /* Low-pass filter used (only in the horizontal direction) */
+#define CAMCR_FLDPOL_VALUE  (0u)      /* When the FLD signal is high-active,
+                                         the field is detected as the top field
+                                         and when low-active, the field is detected as the bottom field.  */
+#define CDOCR_CBE_VALUE     (0u)      /* Normal write */
+#define CDOCR_CDS_VALUE     (1u)      /* Outputs data in the YCbCr422 format to the memory without conversion */
+#define CFWCR_FWV_VALUE     (0u)      /* The upper limit of a write address */
+#define CFWCR_FWE_VALUE     (0u)      /* Firewall is not activated */
+
+
+/* Driver check value */
+#define VOFST_MAX_0FFF      (0x00000FFFu)  /* VOFST MAX check   */
+#define HOFST_MAX_1FFF      (0x00001FFFu)  /* HOFST MAX check   */
+#define VWDTH_MAX_1920      (1920u)        /* VWDTH MAX check   */
+/* HWDTH MAX check */
+#define HWDTH_MAX_5120      (5120u)        /* CEU_IMAGE_CAPTURE_MODE & 8bit  */
+#define HWDTH_MAX_2560      (2560u)        /* CEU_DATA_SYNC_MODE     & 8bit  */
+#define HWDTH_MAX_1280      (1280u)        /* CEU_DATA_SYNC_MODE     & 16bit */
+#define CHDW_MAX_1FFF       (0x00001FFFu)  /* CHDW MAX check   */
+#define CHDW_MAX_8188       (8188u)        /* CHDW MAX check   */
+
+#define CEU_SHIFT_VALUE_1   (1u)
+#define CEU_SHIFT_VALUE_2   (2u)
+#define CEU_SHIFT_VALUE_4   (4u)
+#define CEU_SHIFT_VALUE_8   (8u)
+#define CEU_SHIFT_VALUE_12  (12u)
+#define CEU_SHIFT_VALUE_16  (16u)
+#define CEU_SHIFT_VALUE_20  (20u)
+#define CEU_SHIFT_VALUE_24  (24u)
+#define CEU_SHIFT_VALUE_28  (28u)
+
+#define CETCR_CLARE_VALUE   (0x00000000u)
+#define CEIER_CLARE_VALUE   (0x00000000u)
+
+/******************************************************************************
+ Imported global variables and functions (from other files)
+ ******************************************************************************/
+
+/******************************************************************************
+ Exported global variables and functions (to be accessed by other files)
+ ******************************************************************************/
+
+/******************************************************************************
+ Private global variables and functions
+ ******************************************************************************/
+static ceu_error_t ceu_open_check_prm(const ceu_config_t * const config);
+static ceu_error_t ceu_execute_check_prm(const void * cayr, const void * cacr, const uint32_t chdw);
+static int32_t ceu_align_check(const uint32_t value, uint32_t align);
+
+static void (*ceu_int_callback)(ceu_int_type_t interrupt_flag);
+
+static ceu_jpg_t local_jpg;
+static ceu_dtif_t local_dtif;
+static uint32_t local_hwdth;
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Initialize
+ * @brief       CEU initialization processing
+ * @param[in]   init_func       : user func
+ * @param[in]   user_num        : user param
+ * @retval      None
+ ******************************************************************************/
+void R_CEU_Initialize(void (* const init_func)(uint32_t), const uint32_t user_num)
+{
+    /* call back function */
+    if (NULL != init_func)
+    {
+        init_func (user_num);
+    }
+
+    /* init */
+    local_jpg = CEU_IMAGE_CAPTURE_MODE;
+    local_dtif = CEU_8BIT_DATA_PINS;
+    local_hwdth = 0;
+
+    return;
+} /* End of function R_CEU_Initialize() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Open
+ * @brief       CEU config setting
+ * @param[in]   config       : CEU configuration
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Open(const ceu_config_t * const config)
+{
+    ceu_error_t error;
+
+    /* param check */
+    error = ceu_open_check_prm (config);
+
+    if (CEU_OK == error)
+    {
+        local_jpg = config->jpg;
+        local_dtif = config->dtif;
+
+        /* Capture Interface Control Register (CAMCR)
+         * bit16 FLDPOL - Sets the polarity of the field identification signal (FLD) from an external module.
+         * bit12 DTIF - Sets the digital image input pins from which data is to be captured.
+         * bit9-8 DTARY[1:0] - These bits set the input order of the luminance component and chrominance component.
+         * bit5-4 JPG[1:0] - These bits select the fetched data type. : b'01 (Data synchronous fetch mode)
+         * bit1 VDPOL - Sets the polarity for detection of the vertical sync signal input from an external module.
+         * bit0 HDPOL - Sets the polarity for detection of the horizontal sync signal input from an external module.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CAMCR.LONG = (uint32_t) (
+                (((((CAMCR_FLDPOL_VALUE << CEU_SHIFT_VALUE_16) | (config->dtif << 12u)) | (config->dtary << 8u))
+                        | (config->jpg << 4u)) | (config->vdpol << 1u)) | config->hdpol);
+
+        if (CEU_DATA_ENABLE_MODE != config->jpg)
+        {
+            if (NULL != config->cap)
+            {
+                local_hwdth = config->cap->hwdth;
+
+                /* Capture Interface Offset Register (CAMOR)
+                 * This register is used, during Data synchronous fetch mode.
+                 */
+                CEU.CAMOR_A.LONG = (uint32_t) ((config->cap->vofst << 16u) | config->cap->hofst);
+
+                /* Capture Interface Width Register (CAPWR)
+                 * This register is used, during Data synchronous fetch mode.
+                 */
+                CEU.CAPWR_A.LONG = (uint32_t) ((config->cap->vwdth << 16u) | config->cap->hwdth);
+            }
+        }
+
+        {
+            uint32_t vfclp = 0;
+            uint32_t hfclp = 0;
+
+            if (CEU_IMAGE_CAPTURE_MODE == config->jpg)
+            {
+                vfclp = config->clp->vfclp;
+                hfclp = config->clp->hfclp;
+            }
+            else if (CEU_DATA_SYNC_MODE == config->jpg)
+            {
+                if (CEU_8BIT_DATA_PINS == config->dtif)
+                {
+                    vfclp = config->cap->vwdth;
+                    hfclp = config->cap->hwdth / 2;
+                }
+
+                if (CEU_16BIT_DATA_PINS == config->dtif)
+                {
+                    vfclp = config->cap->vwdth;
+                    hfclp = config->cap->hwdth;
+                }
+            }
+            else
+            {
+                vfclp = 0u;
+                hfclp = 0u;
+            }
+
+            /* Capture Filter Size Clip Register (CFSZR)
+             this register used in Data synchronous fetch mode. */
+            CEU.CFSZR_A.LONG = ((vfclp << 16) | hfclp);
+        }
+
+        /* Capture Data Output Control Register (CDOCR)
+         * bit16 CBE - Controls the number of lines of captured data to be written to the memory.
+         * bit4  CDS - Sets the image format when outputting the image data captured
+         in the YCbCr 422 format to the memory.
+         * bit2 COLS - Controls swapping in 32-bit units for data output from the CEU.
+         * bit1 COWS - Controls swapping in 16-bit units for data output from the CEU.
+         * bit0 COBS - Controls swapping in 8-bit units for data output from the CEU.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CDOCR_A.LONG = (uint32_t) (
+                ((((CDOCR_CBE_VALUE << CEU_SHIFT_VALUE_16) | (CDOCR_CDS_VALUE << CEU_SHIFT_VALUE_4))
+                        | (config->cols << CEU_SHIFT_VALUE_2)) | (config->cows << CEU_SHIFT_VALUE_1)) | config->cobs);
+
+        /* Capture Interface Cycle Register (CMCYR)
+         * Set 0 in all bits of this register, during Data enable fetch mode.
+         */
+        CEU.CMCYR.LONG = (uint32_t) ((CMCYR_VCYL_VALUE << 16u) |
+        CMCYR_HCYL_VALUE);
+
+        /* capture control register (CAPCR)
+         * bit31-24 FDRP[7:0] - the frame drop interval in continuous frame capture. : set H'00 (Single Capture mode)
+         * bit21-20 MTCM[1:0] - These bits specify the unit for transferring data to a bus bridge module. : variable.
+         * bit16 CTNCP - Continuous capture bit : b'0 (One-frame capture)
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CAPCR.LONG = (uint32_t) (
+                ((CAPCR_FDRP_VALUE << CEU_SHIFT_VALUE_24) | (CAPCR_MTCM_VALUE << CEU_SHIFT_VALUE_20))
+                        | (CAPCR_CTNCP_VALUE << CEU_SHIFT_VALUE_16));
+
+        /* Capture Interface Input Format Register (CAIFR)
+         * this register used in Data synchronous fetch mode.
+         */
+        CEU.CAIFR.LONG = (uint32_t) (((CAIFR_IFS_VALUE << CEU_SHIFT_VALUE_8) | (CAIFR_CIM_VALUE << CEU_SHIFT_VALUE_4)) |
+        CAIFR_FC_VALUE);
+
+        /* CEU Register Control Register (CRCNTR)
+         * bit4 RVS - Sets the timing to switch the register plane in both-field capture.
+         * bit1 RS - Specifies which register plane is used by the CEU in synchronization with VD.
+         * bit0 RC - Specifies switching of the register plane used by the CEU in synchronization with VD.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CRCNTR.LONG = (uint32_t) (((CRCNTR_RVS_VALUE << CEU_SHIFT_VALUE_4) | (CRCNTR_RS_VALUE << CEU_SHIFT_VALUE_1)) |
+        CRCNTR_RC_VALUE);
+
+        /* Capture Filter Control Register (CFLCR)
+         * In data fetch mode, set CFLCR to 0.
+         */
+        CEU.CFLCR_A.LONG = (uint32_t) (
+                (((CFLCR_VMANT_VALUE << CEU_SHIFT_VALUE_28) | (CFLCR_VFRAC_VALUE << CEU_SHIFT_VALUE_16))
+                        | (CFLCR_HMANT_VALUE << CEU_SHIFT_VALUE_12)) |
+                CFLCR_HFRAC_VALUE);
+
+        /* Memory address for Bundle write */
+        CEU.CDBYR_A.LONG = 0u;
+        CEU.CDBCR_A.LONG = 0u;
+        CEU.CDAYR2_A.LONG = 0u;
+        CEU.CDACR2_A.LONG = 0u;
+        CEU.CDBYR2_A.LONG = 0u;
+        CEU.CDBCR2_A.LONG = 0u;
+
+        /* Capture Bundle Destination Size Register (CBDSR)
+         * bit22-0 CBVS[22:0] -
+         These bits select the number of lines or number of bytes for output to the memory in a bundle write.
+         * other bit is reserved    : write value should always be 0.
+         */
+        CEU.CBDSR_A.LONG = 0u; /* sample program not support bundle write mode */
+
+        /* Capture Low-Pass Filter Control Register (CLFCR)
+         * In data fetch mode, clear the LPF bit to B'0.
+         * bit0 LPF - Enables or disables operation of the low-pass filter. : set b'1
+         */
+        CEU.CLFCR_A.LONG = CLFCR_LPF_VALUE;
+
+        /* Firewall Operation Control Register (CFWCR)
+         * bit31-5 FWV[26:0] - These bits specify the upper limit of a write address.
+         Specify the upper 27 bits of the 32-bit address. : set 0
+         * bit0 FWE - FW enable/disable. : set 0 (disable)
+         */
+        CEU.CFWCR.LONG = (uint32_t) ((CFWCR_FWV_VALUE << 5u) | CFWCR_FWE_VALUE);
+    }
+
+    return error;
+
+} /* End of function R_CEU_Open() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Execute
+ * @brief       CEU Execute
+ * @param[in]   cayr          : Capture buffer (Y)
+ * @param[in]   cacr          : Capture buffer (CbCr)
+ * @param[in]   chdw          : stride
+ * @param[in]   auto_capture  : ceu_onoff_t
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Execute(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture)
+{
+    ceu_error_t error;
+
+    /* param check */
+    error = ceu_execute_check_prm (cayr, cacr, chdw);
+    if (CEU_OK == error)
+    {
+        CEU.CDAYR_A.LONG = R_CEU_CPUVAddrToSysPAddr((uint32_t) cayr);
+        CEU.CDACR_A.LONG = R_CEU_CPUVAddrToSysPAddr((uint32_t) cacr);
+
+        /* Capture Destination Width Register (CDWDR)
+         * this register used in Data synchronous fetch mode.
+         */
+        CEU.CDWDR_A.LONG = chdw;
+
+        if( CEU_ON == auto_capture )
+        {
+            CEU.CAPCR.LONG |= 0x00010000u;
+        }
+        else
+        {
+            CEU.CAPCR.LONG &= ~0x00010000u;
+        }
+
+        /* start capture */
+        /* Capture Start Register (CAPSR)
+         * bit0 CE - Capture Enable : set b'1 (Starts capturing)
+         * other bit is not change.
+         */
+        CEU.CAPSR.LONG |= CAPSR_CE_BIT;
+    }
+
+    return error;
+
+} /* End of function R_CEU_Execute() */
+
+#if(1) /* mbed */
+/**************************************************************************//**
+ * Function Name: R_CEU_Execute_Setting
+ * @brief       CEU Execute
+ * @param[in]   cayr          : Capture buffer (Y)
+ * @param[in]   cacr          : Capture buffer (CbCr)
+ * @param[in]   chdw          : stride
+ * @param[in]   auto_capture  : ceu_onoff_t
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Execute_Setting(const void * cayr, const void * cacr, const uint32_t chdw, ceu_onoff_t auto_capture)
+{
+    ceu_error_t error;
+
+    /* param check */
+    error = ceu_execute_check_prm (cayr, cacr, chdw);
+    if (CEU_OK == error)
+    {
+        CEU.CDAYR_A.LONG = R_CEU_CPUVAddrToSysPAddr((uint32_t) cayr);
+        CEU.CDACR_A.LONG = R_CEU_CPUVAddrToSysPAddr((uint32_t) cacr);
+
+        /* Capture Destination Width Register (CDWDR)
+         * this register used in Data synchronous fetch mode.
+         */
+        CEU.CDWDR_A.LONG = chdw;
+
+        if( CEU_ON == auto_capture )
+        {
+            CEU.CAPCR.LONG |= 0x00010000u;
+        }
+        else
+        {
+            CEU.CAPCR.LONG &= ~0x00010000u;
+        }
+    }
+
+    return error;
+
+} /* End of function R_CEU_Execute() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Start
+ * @brief       CEU Execute
+ * @param[in]   None
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Start(void)
+{
+    ceu_error_t error = CEU_OK;
+
+    /* start capture */
+    /* Capture Start Register (CAPSR)
+     * bit0 CE - Capture Enable : set b'1 (Starts capturing)
+     * other bit is not change.
+     */
+    CEU.CAPSR.LONG |= CAPSR_CE_BIT;
+
+    return error;
+} /* End of function R_CEU_Start() */
+#endif
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Stop
+ * @brief       CEU Execute
+ * @param[in]   None
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Stop(void)
+{
+    ceu_error_t error = CEU_OK;
+
+    CEU.CAPSR.LONG &= ~0x00000001;
+
+    return error;
+} /* End of function R_CEU_Stop() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Terminate
+ * @brief       CEU Close
+ * @param[in]   quit_func  : user func
+ * @param[in]   user_num   : user param
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+ceu_error_t R_CEU_Terminate(void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    ceu_error_t error = CEU_OK;
+
+    /* software reset
+     * bit16 CPKIL : set 1 (Software reset of capturing)
+     * bit0 CE     : set 0 (Stops capturing)
+     */
+    CEU.CAPSR.LONG = CEU_SW_RESET;
+
+    /* wait software reset complete
+     * Complete : CSTSR.CPTON = b'0 & CAPSR.CPKIL=b'0
+     * [CSTSR]
+     * bit0 CPTON - Indicates that the CEU is operating.
+     * [CAPSR]
+     * bit16 CPKIL - Write 1 to this bit to perform a software reset of capturing.
+     */
+    while (0u != (CEU.CSTSR.LONG & CSTSR_CPTON_BIT))
+    {
+        /* wait state :"Halted" */
+    }
+
+    while (0u != (CEU.CAPSR.LONG & CAPSR_CPKIL_BIT))
+    {
+        /* wait state :"Normal" */
+    }
+
+    /* call back function */
+    if (NULL != quit_func)
+    {
+        quit_func (user_num);
+    }
+
+    return error;
+} /* End of function R_CEU_Terminate() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_InterruptEnable
+ * @brief       CEU Interrupt Enable
+ * @param[in]   int_type       : Capture Event Interrupt Enable Register (CEIER)
+ * @param[in]   callback       : Callback func
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+void R_CEU_InterruptEnable(const ceu_int_type_t int_type, void (* const callback)(ceu_int_type_t))
+{
+    /* Callback function pointer */
+    ceu_int_callback = callback;
+
+    /* Capture Event Interrupt Enable Register (CEIER)  */
+    CEU.CEIER.LONG = int_type;
+
+} /* End of function R_CEU_InterruptEnable() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_InterruptDisable
+ * @brief       CEU Interrupt Disable
+ * @retval      None
+ ******************************************************************************/
+void R_CEU_InterruptDisable(void)
+{
+    /* Callback function pointer clear */
+    ceu_int_callback = 0;
+
+    /* Capture Event Interrupt Enable Register (CEIER) claer */
+    CEU.CEIER.LONG = CEIER_CLARE_VALUE;
+
+} /* End of function R_CEU_InterruptDisable() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_Isr
+ * @brief       CEU interrupt handler
+ * @param[in]   int_sense       :
+ * @retval      None
+ ******************************************************************************/
+void R_CEU_Isr(const uint32_t int_sense)
+{
+    uint32_t interrupt_flag;
+
+    /* get interrupt flag */
+    interrupt_flag = CEU.CETCR.LONG;
+
+    /* clear interrupt flag
+     * Capture Event Flag Clear Register (CETCR)
+     * To clear the bit corresponding to the interrupt source
+     to be cleared to 0 and retain that state, write 1 to that bit.
+     */
+    CEU.CETCR.LONG = CETCR_CLARE_VALUE; /* clear all */
+
+    if (NULL != ceu_int_callback)
+    {
+        /* callback func */
+        ceu_int_callback ((ceu_int_type_t) interrupt_flag);
+    }
+
+} /* End of function R_CEU_Isr() */
+
+/**************************************************************************//**
+ * Function Name: ceu_open_check_prm
+ * @brief       CEU Open check param
+ * @param[in]   config       : CEU configuration
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+static ceu_error_t ceu_open_check_prm(const ceu_config_t * const config)
+{
+    ceu_error_t error = CEU_OK;
+
+    if (NULL != config)
+    {
+        if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) || (CEU_DATA_SYNC_MODE == config->jpg))
+        {
+            if (NULL == config->cap)
+            {
+                error = CEU_ERR_PARAM;
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) || (CEU_DATA_SYNC_MODE == config->jpg))
+            {
+                /* vofst max */
+                if (((uint32_t) config->cap->vofst & (uint32_t) ~VOFST_MAX_0FFF) != 0u)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hofst max */
+                if (((uint32_t) config->cap->hofst & (uint32_t) ~HOFST_MAX_1FFF) != 0u)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) || (CEU_DATA_SYNC_MODE == config->jpg))
+            {
+                /* vwdth max */
+                if (config->cap->vwdth > VWDTH_MAX_1920)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* vwdth align 4 */
+                if (ceu_align_check (config->cap->vwdth, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            /* CEU_IMAGE_CAPTURE_MODE & 8bit */
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) && (CEU_8BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_5120)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 8 */
+                if (ceu_align_check (config->cap->hwdth, 8u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+
+            /* CEU_DATA_SYNC_MODE & 8bit */
+            if ((CEU_DATA_SYNC_MODE == config->jpg) && (CEU_8BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_2560)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 4 */
+                if (ceu_align_check (config->cap->hwdth, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+
+        if (NULL != config)
+        {
+            /* RZ/A1H, M */
+            /* CEU_IMAGE_CAPTURE_MODE & 16bit */
+            if ((CEU_IMAGE_CAPTURE_MODE == config->jpg) && (CEU_16BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_2560)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 4 */
+                if (ceu_align_check (config->cap->hwdth, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+
+        if (NULL != config)
+        {
+            /* CEU_DATA_SYNC_MODE & 16bit */
+            if ((CEU_DATA_SYNC_MODE == config->jpg) && (CEU_16BIT_DATA_PINS == config->dtif))
+            {
+                /* hwdth max */
+                if (config->cap->hwdth > HWDTH_MAX_1280)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hwdth align 2 */
+                if (ceu_align_check (config->cap->hwdth, 2u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if (CEU_IMAGE_CAPTURE_MODE == config->jpg)
+            {
+                if (NULL == config->clp)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (NULL != config)
+        {
+            if (CEU_IMAGE_CAPTURE_MODE == config->jpg)
+            {
+                /* vfclp align 4 */
+                if (ceu_align_check (config->clp->vfclp, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+
+                /* hfclp align 4 */
+                if (ceu_align_check (config->clp->hfclp, 4u) != 0)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+    return error;
+} /* End of function ceu_open_check_prm() */
+
+/**************************************************************************//**
+ * Function Name: ceu_execute_check_prm
+ * @brief       CEU Execute check param
+ * @param[in]   cayr       : Capture buffer (Y)
+ * @param[in]   cacr       : Capture buffer (CbCr)
+ * @param[in]   chdw       : stride
+ * @retval      Error codes of the CEU driver
+ ******************************************************************************/
+static ceu_error_t ceu_execute_check_prm(const void * cayr, const void * cacr, const uint32_t chdw)
+{
+    ceu_error_t error = CEU_OK;
+
+    if (CEU_IMAGE_CAPTURE_MODE == local_jpg)
+    {
+        if ((NULL == cayr) || (NULL == cacr))
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* cayr align 4 */
+        if (ceu_align_check ((uint32_t) cayr, 4u) != 0)
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* cacr align 4 */
+        if (ceu_align_check ((uint32_t) cacr, 4u) != 0)
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* chdw max */
+        if (chdw > CHDW_MAX_8188)
+        {
+            error = CEU_ERR_PARAM;
+        }
+
+        /* chdw align 4 */
+        if (ceu_align_check ((uint32_t) chdw, 4u) != 0)
+        {
+            error = CEU_ERR_PARAM;
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (CEU_DATA_SYNC_MODE == local_jpg)
+        {
+            if (NULL == cayr)
+            {
+                error = CEU_ERR_PARAM;
+            }
+
+            /* cayr align 4 */
+            if (ceu_align_check ((uint32_t) cayr, 4u) != 0)
+            {
+                error = CEU_ERR_PARAM;
+            }
+
+            if (CEU_16BIT_DATA_PINS == local_dtif)
+            {
+                if ((local_hwdth * 2) != chdw)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+
+            if (CEU_8BIT_DATA_PINS == local_dtif)
+            {
+                if (local_hwdth != chdw)
+                {
+                    error = CEU_ERR_PARAM;
+                }
+            }
+        }
+    }
+
+    if (CEU_OK == error)
+    {
+        if (CEU_DATA_ENABLE_MODE == local_jpg)
+        {
+            if (NULL == cayr)
+            {
+                error = CEU_ERR_PARAM;
+            }
+
+            /* cayr align 4 */
+            if (ceu_align_check ((uint32_t) cayr, 32u) != 0)
+            {
+                error = CEU_ERR_PARAM;
+            }
+        }
+    }
+
+    return error;
+} /* End of function ceu_execute_check_prm() */
+
+/**************************************************************************//**
+ * Function Name: ceu_align_check
+ * @brief       align check
+ * @param[in]   value       : check value
+ * @param[in]   align       : align value
+ * @retval      OK(0) NG(-1)
+ ******************************************************************************/
+static int32_t ceu_align_check(const uint32_t value, uint32_t align)
+{
+    int32_t error;
+
+    align -= 1u;
+    if ((value & align) != 0)
+    {
+        error = -1;
+    }
+    else
+    {
+        error = 0;
+    }
+
+    return error;
+} /* End of function ceu_align_check() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/ceu/userdef/ceu_userdef.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,145 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         ceu_userdef.c
+* @version      0.06
+* $Rev: 18 $
+* $Date:: 2014-05-29 11:11:38 +0900#$
+* @brief        RZ/A1L CEU driver user function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "r_ceu.h"
+#include "r_ceu_user.h"
+#include "mmu_init.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define STP56_BIT               (0x40u)
+#define STBRQ10_BIT             (0x01u)
+#define STBAK10_BIT             (0x01u)
+
+#define CEU_INTERRUPT_PRIORITY  (5u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/**************************************************************************//**
+ * @brief       Physical address translation
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Get the System Physical address of the given virtual memory address.
+ * @param[in]   vaddr               : virtual address
+ * @retval      physical address
+ *****************************************************************************/
+uint32_t R_CEU_CPUVAddrToSysPAddr(uint32_t vaddr)
+{
+    uint32_t ret;
+
+    ret = R_MMU_VAtoPA(vaddr);
+    return ret;
+}   /* End of function R_CEU_CPUVAddrToSysPAddr() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_OnInitialize
+ * @brief       CEU User difinistion part Init
+ * @param[in]   user_num          :
+ * @retval      none
+ *****************************************************************************/
+void R_CEU_OnInitialize(const uint32_t user_num)
+{
+    uint32_t reg_data;
+    volatile uint8_t dummy_read;
+
+    /* Standby control register 5 (STBCR5)
+        b6      -0------;  MSTP56 : 0 : CEU enable */
+    reg_data    = (uint32_t)CPG.STBCR5.BYTE & (uint32_t)~STP56_BIT;
+    CPG.STBCR5.BYTE  = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR5.BYTE;
+    (void)dummy_read;
+
+    /* Standby Request Register 1 (STBREQ1)
+        b0      -------0;  STBRQ10 : The standby request to CEU is invalid. */
+    reg_data    = (uint32_t)CPG.STBREQ1.BYTE & (uint32_t)~STBRQ10_BIT;
+    CPG.STBREQ1.BYTE = (uint8_t)reg_data;
+    /* Standby Acknowledge Register 1 (STBACK1)
+        b0      -------*;  STBAK10 : Standby acknowledgement from CEU. */
+    while (((uint32_t)CPG.STBACK1.BYTE & (uint32_t)STBAK10_BIT) != 0u) {
+        /* Wait for the STBAK10 to be cleared to 0. */
+    }
+
+    InterruptHandlerRegister(CEUI_IRQn, R_CEU_Isr);
+    GIC_SetPriority(CEUI_IRQn, (uint8_t)CEU_INTERRUPT_PRIORITY);
+    GIC_SetConfiguration(CEUI_IRQn, 1);
+    GIC_EnableIRQ(CEUI_IRQn);
+} /* End of function R_CEU_OnInitialize() */
+
+/**************************************************************************//**
+ * Function Name: R_CEU_OnFinalize
+ * @brief       CEU User difinistion part final
+ * @param[in]   user_num          :
+ * @retval      none
+ *****************************************************************************/
+void R_CEU_OnFinalize(const uint32_t user_num)
+{
+    uint32_t reg_data;
+    volatile uint8_t dummy_read;
+
+    /* Standby Request Register 1 (STBREQ1)
+        b0      -------1;  STBRQ10 : The standby request to CEU is valid. */
+    reg_data    = (uint32_t)CPG.STBREQ1.BYTE | (uint32_t)STBRQ10_BIT;
+    CPG.STBREQ1.BYTE = (uint8_t)reg_data;
+    /* Standby Acknowledge Register 1 (STBACK1)
+        b0      -------*;  STBAK10 : Standby acknowledgement from CEU. */
+    while (((uint32_t)CPG.STBACK1.BYTE & (uint32_t)STBAK10_BIT) == 0u) {
+        /* Wait for the STBAK10 to be set to 1. */
+    }
+
+    /* Standby control register 5 (STBCR5)
+        b6      -1------;  MSTP56 : 1 : CEU disable */
+    reg_data    = (uint32_t)CPG.STBCR5.BYTE | (uint32_t)STP56_BIT;
+    CPG.STBCR5.BYTE  = (uint8_t)reg_data;
+
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR5.BYTE;
+    (void)dummy_read;
+
+} /* End of function R_CEU_OnFinalize() */
+
+/* End of File */
+

Binary file mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/r_mipi/doc/r01an4481ej0110-rza2m-mipi-driver-gcc.pdf has changed

Binary file mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/r_mipi/doc/r01an4481jj0110-rza2m-mipi-driver-gcc.pdf has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/r_mipi/inc/r_mipi_api.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,466 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/**************************************************************************
+* File Name : r_mipi_api.h
+* Version : 1.11
+* Description : RZ/A2M MIPI driver API definitions
+**************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_mipi_user.h"
+
+#ifndef R_MIPI_H
+#define R_MIPI_H
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Mipi Driver Status ( for "Mipi_State" ) */
+typedef enum
+{
+    MIPI_POWOFF,    /*!< Reset Status(Clock Driven) */
+    MIPI_STOP,      /*!< Capture Stopped */
+    MIPI_CAPTURE,   /*!< Capturing */
+} e_mipi_state_t;
+
+/*! Mipi Capture Mode */
+typedef enum
+{
+    MIPI_SINGLE_MODE = 0,   /*!< Single Capture Mode */
+    MIPI_CONTINUOUS_MODE,   /*!< Continuous Capture Mode */
+} e_mipi_capture_mode_t;
+
+/*! Interlace or Progressive (for "Mipi_Param_t.Mipi_Interlace" ) */
+typedef enum
+{
+    MIPI_PROGRESSIVE = 0,   /*!< Capture Progressive Data */
+    MIPI_INTERLACE,         /*!< Capture Interlace Data */
+} e_mipi_inter_t;
+
+/*! YUV Range Clip Parameter (Not supported) */
+typedef enum
+{
+    VIN_CLIP_C_16_240 = 0, /*!< Not supported parameter (Clip C, Between 16 and 240) */
+    VIN_CLIP_YC_16_240,    /*!< Not supported parameter (Clip YC, Between 16 and 240) */
+    VIN_CLIP_C_128_128,    /*!< Not supported parameter (Clip C, Between 16 and 240 ( if Out of Range, Set to 128 )) */
+    VIN_CLIP_NONE,         /*!< Not supported parameter (No Clip) */
+} e_vin_yuv_clip_t;
+
+/*! LUT Conversion On or OFF (Not supported) */
+typedef enum
+{
+    VIN_LUT_OFF = 0,    /*!< Not supported parameter (No LUT Conversion) */
+    VIN_LUT_ON,         /*!< Not supported parameter (LUT Conversion) */
+} e_vin_lut_t;
+
+/*! Input Image Format */
+typedef enum
+{
+    VIN_INPUT_YCBCR422_8 = 0,   /*!< YUV(=YCbCr422 8bit) */
+    VIN_INPUT_YCBCR422_8I,      /*!< UYVY */
+    VIN_INPUT_YCBCR422_10,      /*!< Not supported parameter (YCbCr422 10bit) */
+    VIN_INPUT_RGB888,           /*!< Not supported parameter (RGB888) */
+    VIN_INPUT_RAW8,             /*!< RAW8 */
+} e_vin_inputformat_t;
+
+/*! Output Image Format */
+typedef enum
+{
+    VIN_OUTPUT_YCBCR422_8  = (0x00),    /*!< YUV(=YCbCr422 8bit) */
+    VIN_OUTPUT_YCBCR422_10 = (0x01),    /*!< Not supported parameter (YUV(=YCbCr422 10bit) */
+    VIN_OUTPUT_Y8_CbCr8    = (0x02),    /*!< YC separate output, Y=8bit, C=8bit */
+    VIN_OUTPUT_Y8          = (0x03),    /*!< 8bit Gray scale */
+    VIN_OUTPUT_Y10_CbCr10  = (0x04),    /*!< Not supported parameter (YC separate output, Y=10bit, C=10bit) */
+    VIN_OUTPUT_Y10         = (0x05),    /*!< Not supported parameter (10bit Gray scale) */
+    VIN_OUTPUT_Y10_CbCr8   = (0x06),    /*!< Not supported parameter (YC separate output, Y=10bit, C=8bit) */
+    VIN_OUTPUT_ARGB8888    = (0x10),    /*!< Not supported parameter (ARGB8888) */
+    VIN_OUTPUT_XRGB8888    = (0x11),    /*!< Not supported parameter (XRGB8888) */
+    VIN_OUTPUT_ARGB1555    = (0x12),    /*!< Not supported parameter (ARGB1555) */
+    VIN_OUTPUT_RGB565      = (0x13),    /*!< Not supported parameter (RGB565) */
+    VIN_OUTPUT_RAW8        = (0x20),    /*!< RAW8 */
+} e_vin_outputformat_t;
+
+/*! Output Image Endian */
+typedef enum
+{
+    VIN_OUTPUT_EN_LITTLE = 0,   /*!< Little Endian */
+    VIN_OUTPUT_EN_BIG,          /*!< Big Endian */
+} e_vin_outputendian_t;
+
+/*! Output Data Dithering On or Off (Not supported) */
+typedef enum
+{
+    VIN_DITHER_CUMULATIVE = 0,  /*!< Not supported parameter (Cumulative Mode) */
+    VIN_DITHER_ORDERED,         /*!< Not supported parameter (Ordered Mode) */
+} e_vin_dither_t;
+
+/*! Capture Method */
+typedef enum
+{
+    VIN_INTERLACE_ODD = 0,  /*!< Capture Odd field of Interlace data */
+    VIN_INTERLACE_EVEN,     /*!< Capture Even field of Interlace data */
+    VIN_INTERLACE_BOTH,     /*!< Capture Both field of Interlace data */
+    VIN_PROGRESSIVE,        /*!< Capture Progressive data */
+} e_vin_interlace_t;
+
+/*! Scaling On or OFF (Not supported) */
+typedef enum
+{
+    VIN_SCALE_OFF = 0,  /*!< Not supported parameter (Scaling is Valid) */
+    VIN_SCALE_ON,       /*!< Not supported parameter (Scaling is Invalid) */
+} e_vin_scaleon_t;
+
+/*! Scaling Interpolation (Not supported) */
+typedef enum
+{
+    VIN_BILINEAR = 0,   /*!< Not supported parameter (Bilinear interpolation) */
+    VIN_NEAREST,        /*!< Not supported parameter (Nearest interpolation) */
+    VIN_MULTITAPS,      /*!< Not supported parameter (Multi taps interpolation) */
+} e_vin_interpolation_t;
+
+/*! YCbCr422 input data alignment */
+typedef enum
+{
+    VIN_Y_UPPER = 0,  /*!< Upper bit is Y, lower bit is CbCr */
+    VIN_CB_UPPER,     /*!< Upper bit is CbCr, lower bit is Y */
+} e_vin_input_align_t;
+
+/*! Output data byte swap mode */
+typedef enum
+{
+    VIN_SWAP_OFF = 0,   /*!< Not swap */
+    VIN_SWAP_ON,        /*!< Swap */
+} e_vin_output_swap_t;
+
+/*! MIPI Interrupt Factor */
+typedef enum
+{
+    MIPI_INT_LESS_THAN_WC    = 0x00000001,  /*!< Error interrupt that is generated when the length of payload data
+                                                 of a long packet is less than the WC value. */
+    MIPI_INT_AFIFO_OF        = 0x00000002,  /*!< Error Interrupt that is generated by an overflow of
+                                                 the asynchronous FIFO, which stores the HS data sent from the PHY.*/
+    MIPI_INT_VD_START        = 0x00000004,  /*!< Frame start interrupt.*/
+    MIPI_INT_VD_END          = 0x00000008,  /*!< Frame end interrupt).*/
+    MIPI_INT_SHP_STB         = 0x00000010,  /*!< Short packet reception interrupt. */
+    MIPI_INT_FSFE            = 0x00000020,  /*!< Frame packet reception interrupt. */
+    MIPI_INT_LNP_STB         = 0x00000040,  /*!< Long packet reception interrupt.*/
+    MIPI_INT_CRC_ERR         = 0x00000080,  /*!< CRC error interrupt.*/
+    MIPI_INT_HD_WC_ZERO      = 0x00000100,  /*!< WC (word count) zero interrupt.*/
+    MIPI_INT_FRM_SEQ_ERR1    = 0x00000200,  /*!< Frame sequence error 1 interrupt. */
+    MIPI_INT_FRM_SEQ_ERR0    = 0x00000400,  /*!< Frame sequence error 0 interrupt. */
+    MIPI_INT_ECC_ERR         = 0x00000800,  /*!< ECC error interrupt. */
+    MIPI_INT_ECC_CRCT_ERR    = 0x00001000,  /*!< ECC 1-bit correction interrupt. */
+    MIPI_INT_ULPS_START      = 0x00002000,  /*!< Ultra-low power data transfer start interrupt. */
+    MIPI_INT_ULPS_END        = 0x00004000,  /*!< Ultra-low power data transfer end interrupt. */
+    MIPI_INT_ERRSOTHS        = 0x00008000,  /*!< Synchronized SOT (start of transfer) error interrupt
+                                                 during HS reception. */
+    MIPI_INT_ERRSOTSYNCHS    = 0x00010000,  /*!< Non-synchronizable SOT (start of transfer) error
+                                                 interrupt during HS reception. */
+    MIPI_INT_ERRESC          = 0x00020000,  /*!< Escape mode entry error interrupt. */
+    MIPI_INT_ERRCONTROL      = 0x00040000,  /*!< PHY control error interrupt. */
+    VIN_INT_FIELD2           = 0x00100000,  /*!< Field interrupts. */
+    VIN_INT_VSYNC_FALL       = 0x00200000,  /*!< VSYNC Falling Edge Detect Interrupt. */
+    VIN_INT_VSYNC_RISE       = 0x00400000,  /*!< VSYNC Rising Edge Detect Interrupt. */
+    VIN_INT_FIELD            = 0x00800000,  /*!< Field switching Interrupt.*/
+    VIN_INT_SCANLINE         = 0x01000000,  /*!< Scan line interrupt. */
+    VIN_INT_FRAME            = 0x02000000,  /*!< End of frame interrupt. */
+    VIN_INT_FIFO_OF          = 0x04000000   /*!< FIFO overflow interrupt. */
+} e_mipi_interrupt_type_t;
+
+/*! MIPI Error Factor */
+typedef enum
+{
+    MIPI_OK             = 0x0000,   /*!< Normal termination. */
+    MIPI_STATUS_ERR     = 0x0001,   /*!< An API function is called under unauthorized conditions. */
+    MIPI_PARAM_ERR      = 0x0002,   /*!< A parameter is specified under conditions that
+                                         are not authorized by the specification. */
+} e_mipi_error_t;
+
+/***********************    For R_VDC_VideoInput       ***********************/
+/*! mipi phy timing struct */
+typedef struct
+{
+    uint16_t mipi_ths_prepare;  /*!< Setting of the duration of the LP-00 state
+                                     (immediately before entry to the HS-0 state) */
+    uint16_t mipi_ths_settle;   /*!< Setting of the period in which a transition to the HS state is
+                                     ignored after the TTHS_PREPARE period begins */
+    uint16_t mipi_tclk_prepare; /*!< Setting of the duration of the LP-00 state
+                                     (immediately before entry to the HS-0) */
+    uint16_t mipi_tclk_settle;  /*!< Setting of the period in which a transition to the HS state is
+                                     ignored after the TCLK_PREPARE period begins */
+    uint16_t mipi_tclk_miss;    /*!< Setting of the period in which the absence of the clock is detected,
+                                     and the HS-RX is disabled */
+    uint16_t mipi_t_init_slave; /*!< Minimum duration of the INIT state */
+} st_mipi_phy_timing_t;
+
+/*! mipi parameter struct */
+typedef struct
+{
+    uint8_t  mipi_lanenum;                 /*!< Mipi Lane Num */
+    uint8_t  mipi_vc;                      /*!< Mipi Virtual Channel */
+    uint8_t  mipi_interlace;               /*!< Interlace or Progressive */
+    uint8_t  mipi_laneswap;                /*!< Mipi Lane Swap Setting */
+    uint16_t mipi_frametop;                /*!< (for Interlace)Top Field Packet ID */
+    uint16_t mipi_outputrate;              /*!< Mipi Data Send Speed(Mbit per sec) */
+    st_mipi_phy_timing_t mipi_phy_timing;  /*!< Mipi D-PHY timing settings */
+} st_mipi_param_t;
+
+/*! mipi interrupt callback setup parameter */
+typedef struct
+{
+    e_mipi_interrupt_type_t type;                                      /*!< MIPI interrupt type */
+    void (* p_mipiCallback) (e_mipi_interrupt_type_t interrupt_flag);  /*!< Interrupt callback function pointer */
+    void (* p_vinCallback)  (e_mipi_interrupt_type_t interrupt_flag);  /*!< Interrupt callback function pointer */
+    uint32_t line_num;                                                 /*!< Line interrupt set */
+} st_mipi_int_t;
+
+/*! Vin parameter Struct */
+typedef struct
+{
+    uint16_t vin_preclip_starty;    /*!< Pre Area Clip Start Line */
+    uint16_t vin_preclip_endy;      /*!< Pre Area Clip End Line */
+    uint16_t vin_preclip_startx;    /*!< Pre Area Clip Start Column */
+    uint16_t vin_preclip_endx;      /*!< Pre Area Clip End Column */
+} st_vin_preclip_t;
+
+typedef struct
+{
+    uint8_t  vin_scaleon;           /*!< Not supported parameter (Scaling On or OFF) */
+    uint8_t  vin_interpolation;     /*!< Not supported parameter (Scaling Interpolation) */
+    uint16_t vin_scale_h;           /*!< Not supported parameter (Horizontal multiple) */
+    uint16_t vin_scale_v;           /*!< Not supported parameter (vertical multiple) */
+} st_vin_scale_t;
+
+typedef struct
+{
+    uint16_t vin_afterclip_size_x;  /*!< Not supported parameter (After Area Clip horizontal size) */
+    uint16_t vin_afterclip_size_y;  /*!< Not supported parameter (After Area Clip vertical size) */
+} st_vin_afterclip_t;
+
+typedef struct
+{
+    st_vin_preclip_t   vin_preclip;        /*!< Pre Area Clip Parameter */
+    st_vin_scale_t     vin_scale;          /*!< Not supported parameter */
+    st_vin_afterclip_t vin_afterclip;      /*!< Not supported parameter */
+    uint8_t            vin_yuv_clip;       /*!< Not supported parameter */
+    uint8_t            vin_lut;            /*!< Not supported parameter */
+    uint8_t            vin_inputformat;    /*!< Input Image Format */
+    uint8_t            vin_outputformat;   /*!< Output Image Format */
+    uint8_t            vin_outputendian;   /*!< Output Data Endian*/
+    uint8_t            vin_dither;         /*!< Not supported parameter */
+    uint8_t            vin_interlace;      /*!< (for Interlace input)Capture Method */
+    uint8_t            vin_alpha_val8;     /*!< Not supported parameter */
+    uint8_t            vin_alpha_val1;     /*!< Not supported parameter */
+    uint16_t           vin_stride;         /*!< Stride (byte) */
+    uint32_t           vin_ycoffset;       /*!< (for YC separate output)Address Offset Value */
+    e_vin_input_align_t  vin_input_align;  /*!< YCbCr422 input data alignment */
+    e_vin_output_swap_t  vin_output_swap;  /*!< Output data byte swap mode */
+} st_vin_setup_t;
+
+/* Vin Information Struct */
+typedef struct
+{
+    uint16_t vin_nowcaptureline; /*!< Line Num Captured Now */
+    uint8_t vin_nowcapturefield; /*!< Field Captured Now */
+    uint8_t vin_nowcapturebase;  /*!< Base Captured Now */
+} st_vin_info_type_t;
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+ * @fn          R_MIPI_Initialize
+ * @brief       MIPI driver initialize
+ *
+ *              Description:<br>
+ *              MIPI driver initialization processing
+ * @param[in]   init_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      None
+ *****************************************************************************/
+void R_MIPI_Initialize(void (* const init_func)(uint32_t), const uint32_t user_num);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_Open
+ * @brief       MIPI driver open
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Parameter check.
+ *              - MIPI sw reset.
+ *              - Initialization of PHY register.
+ * @param[in]   mipi_data               : MIPI setting parameter
+ * @retval      Error code
+ *****************************************************************************/
+e_mipi_error_t R_MIPI_Open(const st_mipi_param_t * const mipi_data);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_Close
+ * @brief       MIPI driver close
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Check MIPI state.
+ *              - MIPI interruput all disable.
+ *              - VIN capture stop.
+ *              - MIPI sw-reset.
+ *              - Calls the user-defined function specified in finalize_func.
+ * @param[in]   finalize_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+e_mipi_error_t R_MIPI_Close(void (* const finalize_func)(uint32_t), const uint32_t user_num);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_Setup
+ * @brief       MIPI driver VIN setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Parameter check.
+ *              - Initialization of VIN register.
+ *              - VIN scaling setting.
+ *              - VIN clipping setting.
+ * @param[in]   vin_setup               : VIN setting parameter
+ * @retval      Error code
+ *****************************************************************************/
+e_mipi_error_t R_MIPI_Setup(const st_vin_setup_t * const vin_setup );
+
+/**************************************************************************//**
+ * @fn          R_MIPI_SetBufferAdr
+ * @brief       MIPI driver VIN set buffer
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Parameter check.
+ *              - VIN setting buffer address.
+ * @param[in]   buffer_no               : Select buffer base (MB1, MB2, MB3)
+ * @param[in]   bufferBase              : Buffer base address
+ * @retval      Error code
+ *****************************************************************************/
+e_mipi_error_t R_MIPI_SetBufferAdr(const uint8_t buffer_no, const uint8_t * const bufferBase);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_InterruptEnable
+ * @brief       MIPI driver interruput enable (MIPI and VIN).
+ *
+ *              Description:<br>
+ *              Set the interrupt enable register of MIPI and VIN
+ * @param[in]   param                   : Interrupt settings
+ * @retval      None
+ *****************************************************************************/
+void R_MIPI_InterruptEnable(const st_mipi_int_t * const param );
+
+/**************************************************************************//**
+ * @fn          R_MIPI_InterruptDisable
+ * @brief       MIPI driver interruput disable (MIPI and VIN).
+ *
+ *              Description:<br>
+ *              Clear the interrupt enable register of MIPI and VIN
+ * @param[in]   None
+ * @retval      None
+ *****************************************************************************/
+void R_MIPI_InterruptDisable(void);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_GetInfo
+ * @brief       MIPI driver getting registers status.
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Getting registers status (Line Count/Field Status/Frame Buffer Status).
+ * @param[out]  infoType       : registers status
+ * @retval      Error code
+ *****************************************************************************/
+e_mipi_error_t R_MIPI_GetInfo(st_vin_info_type_t * infoType);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_CaptureStart
+ * @brief       MIPI driver capture start.
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Setting capture mode( Single or Continuous ).
+ *              - Capture start.
+ * @param[in]  captureMode      : Single or Continuous
+ * @retval      Error code
+ *****************************************************************************/
+e_mipi_error_t R_MIPI_CaptureStart(const e_mipi_capture_mode_t captureMode);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_CaptureStop
+ * @brief       MIPI driver capture stop.
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Capture stop.
+ * @param[in]   None
+ * @retval      Error code
+ *****************************************************************************/
+e_mipi_error_t R_MIPI_CaptureStop(void);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_InterruptHandler
+ * @brief       MIPI driver interrupt handler for MIPI.
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Check MIPI interrupt type.
+ *              - Call the callback funtion.
+ * @param[in]   int_sense   : sense
+ * @retval      None
+ *****************************************************************************/
+void R_MIPI_InterruptHandler( uint32_t int_sense );
+
+/**************************************************************************//**
+ * @fn          R_VIN_InterruptHandler
+ * @brief       MIPI driver interrupt handler for VIN.
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Call the callback funtion.
+ * @param[in]   int_sense   : sense
+ * @retval      None
+ *****************************************************************************/
+void R_VIN_InterruptHandler( uint32_t int_sense );
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_MIPI_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/r_mipi/inc/r_mipi_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,90 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/**************************************************************************
+* File Name : r_mipi_user.h
+* Version : 1.11
+* Description : RZ/A2M MIPI and VIN driver user-defined header
+**************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+#ifndef R_MIPI_USER_H
+#define R_MIPI_USER_H
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Version Number of API */
+#define MIPI_RZA2_VERSION_MAJOR (1)
+#define MIPI_RZA2_VERSION_MINOR (11)
+
+/* Interrupt priority */
+#define MIPI_INTERRUPT_PRIORITY  (28u)
+#define VIN_INTERRUPT_PRIORITY   (28u)
+
+/* For wait processing */
+#define MIPI_1US_WAIT        (528u)    /* CPU Clock = 528MHz, 528 clock is needed to wait 1us */
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+ * @fn            R_MIPI_CPUVAddrToSysPAddr
+ * @brief       Physical address translation
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Get the System Physical address of the given virtual memory address.
+ * @param[in]   vaddr               : virtual address
+ * @retval      physical address
+ *****************************************************************************/
+uint32_t R_MIPI_CPUVAddrToSysPAddr(uint32_t vaddr);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_OnInitialize
+ * @brief       MIPI and VIN User definition part of initialize
+ * @param[in]   user_num          :user specify argument
+ * @retval      none
+ *****************************************************************************/
+void R_MIPI_OnInitialize (const uint32_t user_num);
+
+/**************************************************************************//**
+ * @fn          R_MIPI_OnFinalize
+ * @brief       MIPI and VIN  User definition part of finalize
+ * @param[in]   user_num          :user specify argument
+ * @retval      none
+******************************************************************************/
+void R_MIPI_OnFinalize( const uint32_t user_num );
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* R_MIPI_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/r_mipi/src/r_mipi_api.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1107 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/**************************************************************************
+* File Name : r_mipi_api.c
+* Version : 1.11
+* Description : RZ/A2M MIPI driver API function
+**************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <iodefine.h>
+
+#include    "r_mipi_api.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Interrupt table management */
+#define MIPI_INTERRUPT_TYPE_NUM  (19u)
+#define VIN_INTERRUPT_TYPE_NUM   (7u)
+#define INTERRUPT_REGBIT         (0u)
+#define INTERRUPT_FLAG           (1u)
+
+/* Interrupt Register Settings */
+#define INTEN_MASK_ALL_SET       (0x181FFCDDu)
+#define INTEN_ALL_CLEAR          (0x00000000u)
+#define VOIE_ALL_CLEAR           (0x00000000u)
+#define VNSI_WRITE_MASK          (0x000007FFu)
+
+/* For stride pixel size check */
+#define VIN_OUTPUT_FORMAT_NUM    ( 4u)
+#define OUTPUT_FORMAT_ENUM       ( 0u)
+#define STRIDE_ALIGN_SIZE        ( 1u)
+#define PIXEL_ALIGN_32           ( 31u) /* 0x1F is used for align check */
+#define PIXEL_ALIGN_64           ( 63u) /* 0x3F is used for align check */
+#define PIXEL_ALIGN_128          (127u) /* 0x7F is used for align check */
+
+/* For output data mode */
+#define VIN_YMODE_YC_ASIS        ( 0u)    /* Y and C are outputed to memory as is */
+#define VIN_YMODE_Y_8BIT         ( 1u)    /* Only Y is outputed to memory as 8bit */
+#define VIN_YMODE_YC_8BIT        ( 2u)    /* Y and C are outputed to memory, C is converted from 10bit to 8bit */
+#define VIN_YMODE_Y_10BIT        ( 3u)    /* Only Y is outputed to memory as 10bit */
+#define VIN_DTMD_NOT_CONVERT     ( 0u)    /* Do not separate Y and C */
+#define VIN_DTMD_YC_SEPARATE     ( 2u)    /* Separate Y and C */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* Bit definition of MIPI register (INTEN, INTCLOSE, INTSTATE) */
+typedef enum
+{
+    REGBIT_MIPI_INT_LESS_THAN_WC    = 0x10000000,
+    REGBIT_MIPI_INT_AFIFO_OF        = 0x08000000,
+    REGBIT_MIPI_INT_VD_START        = 0x00100000,
+    REGBIT_MIPI_INT_VD_END          = 0x00080000,
+    REGBIT_MIPI_INT_SHP_STB         = 0x00040000,
+    REGBIT_MIPI_INT_FSFE            = 0x00020000,
+    REGBIT_MIPI_INT_LNP_STB         = 0x00010000,
+    REGBIT_MIPI_INT_CRC_ERR         = 0x00008000,
+    REGBIT_MIPI_INT_HD_WC_ZERO      = 0x00004000,
+    REGBIT_MIPI_INT_FRM_SEQ_ERR1    = 0x00002000,
+    REGBIT_MIPI_INT_FRM_SEQ_ERR0    = 0x00001000,
+    REGBIT_MIPI_INT_ECC_ERR         = 0x00000800,
+    REGBIT_MIPI_INT_ECC_CRCT_ERR    = 0x00000400,
+    REGBIT_MIPI_INT_ULPS_START      = 0x00000080,
+    REGBIT_MIPI_INT_ULPS_END        = 0x00000040,
+    REGBIT_MIPI_INT_ERRSOTHS        = 0x00000010,
+    REGBIT_MIPI_INT_ERRSOTSYNCHS    = 0x00000008,
+    REGBIT_MIPI_INT_ERRESC          = 0x00000004,
+    REGBIT_MIPI_INT_ERRCONTROL      = 0x00000001,
+} e_bit_mipi_int_type_t;
+
+/* Bit definition of VIN register (VnIE, VnINTS) */
+typedef enum
+{
+    REGBIT_VIN_INT_FIELD2           = 0x80000000,
+    REGBIT_VIN_INT_VSYNC_FALL       = 0x00020000,
+    REGBIT_VIN_INT_VSYNC_RISE       = 0x00010000,
+    REGBIT_VIN_INT_FIELD            = 0x00000010,
+    REGBIT_VIN_INT_SCANLINE         = 0x00000004,
+    REGBIT_VIN_INT_FRAME            = 0x00000002,
+    REGBIT_VIN_INT_FIFO_OF          = 0x00000001
+} e_bit_vin_int_type_t;
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+/* Static functions */
+static uint8_t calc_scale_passband(uint16_t scale_int, uint16_t scale_fra);
+
+/* Mipi Driver Status */
+static uint8_t gs_mipi_state;
+
+/* Mipi Callback Function */
+static void (* Mipi_Callback  )( e_mipi_interrupt_type_t interrupt_flag);
+
+/* Vin Callback Function */
+static void (* Vin_Callback )( e_mipi_interrupt_type_t interrupt_flag);
+
+/* Mipi Error Bit */
+static const uint32_t gs_tbl_mipi_interrupt_bit[MIPI_INTERRUPT_TYPE_NUM][2] = {
+    { REGBIT_MIPI_INT_LESS_THAN_WC, MIPI_INT_LESS_THAN_WC }, /* INT_LESS_THAN_WC */
+    { REGBIT_MIPI_INT_AFIFO_OF    , MIPI_INT_AFIFO_OF     }, /* INT_AFIFO_OF */
+    { REGBIT_MIPI_INT_VD_START    , MIPI_INT_VD_START     }, /* INT_VD_START */
+    { REGBIT_MIPI_INT_VD_END      , MIPI_INT_VD_END       }, /* INT_VD_END */
+    { REGBIT_MIPI_INT_SHP_STB     , MIPI_INT_SHP_STB      }, /* INT_SHP_STB */
+    { REGBIT_MIPI_INT_FSFE        , MIPI_INT_FSFE         }, /* INT_FSFE */
+    { REGBIT_MIPI_INT_LNP_STB     , MIPI_INT_LNP_STB      }, /* INT_LNP_STB */
+    { REGBIT_MIPI_INT_CRC_ERR     , MIPI_INT_CRC_ERR      }, /* INT_CRC_ERR */
+    { REGBIT_MIPI_INT_HD_WC_ZERO  , MIPI_INT_HD_WC_ZERO   }, /* INT_HD_WC_ZERO */
+    { REGBIT_MIPI_INT_FRM_SEQ_ERR1, MIPI_INT_FRM_SEQ_ERR1 }, /* INT_FRM_SEQ_ERR1 */
+    { REGBIT_MIPI_INT_FRM_SEQ_ERR0, MIPI_INT_FRM_SEQ_ERR0 }, /* INT_FRM_SEQ_ERR0 */
+    { REGBIT_MIPI_INT_ECC_ERR     , MIPI_INT_ECC_ERR      }, /* INT_ECC_ERR */
+    { REGBIT_MIPI_INT_ECC_CRCT_ERR, MIPI_INT_ECC_CRCT_ERR }, /* INT_ECC_CRCT_ERR */
+    { REGBIT_MIPI_INT_ULPS_START  , MIPI_INT_ULPS_START   }, /* INT_ULPS_START */
+    { REGBIT_MIPI_INT_ULPS_END    , MIPI_INT_ULPS_END     }, /* INT_ULPS_END */
+    { REGBIT_MIPI_INT_ERRSOTHS    , MIPI_INT_ERRSOTHS     }, /* INT_ERRSOTHS */
+    { REGBIT_MIPI_INT_ERRSOTSYNCHS, MIPI_INT_ERRSOTSYNCHS }, /* INT_ERRSOTSYNCHS */
+    { REGBIT_MIPI_INT_ERRESC      , MIPI_INT_ERRESC       }, /* INT_ERRESC */
+    { REGBIT_MIPI_INT_ERRCONTROL  , MIPI_INT_ERRCONTROL   }  /* INT_ERRCONTROL */
+};
+
+/* Vin Error Bit */
+static const uint32_t gs_tbl_vin_interrupt_bit[VIN_INTERRUPT_TYPE_NUM][2] = {
+    { REGBIT_VIN_INT_FIELD2    , VIN_INT_FIELD2     }, /* INT_VIN_FIELD2 */
+    { REGBIT_VIN_INT_VSYNC_FALL, VIN_INT_VSYNC_FALL }, /* INT_VIN_VSYNC_FALL */
+    { REGBIT_VIN_INT_VSYNC_RISE, VIN_INT_VSYNC_RISE }, /* INT_VIN_VSYNC_RISE */
+    { REGBIT_VIN_INT_FIELD     , VIN_INT_FIELD      }, /* INT_VIN_FIELD */
+    { REGBIT_VIN_INT_SCANLINE  , VIN_INT_SCANLINE   }, /* INT_VIN_SCANLINC */
+    { REGBIT_VIN_INT_FRAME     , VIN_INT_FRAME      }, /* INT_VIN_FRAME */
+    { REGBIT_VIN_INT_FIFO_OF   , VIN_INT_FIFO_OF    }  /* INT_VIN_FIFO_OF */
+};
+
+static const char_t gs_cnvtbl_inputformat_toinf[5] = {
+    0x01,       /* INPUT_YCBCR422_8 */
+    0x01,       /* INPUT_YCBCR422_8I */
+    0x03,       /* INPUT_YCBCR422_10 */
+    0x06,       /* INPUT_RGB888 */
+    0x04        /* INPUT_RAW8 */
+};
+
+static const char_t gs_cnvtbl_interlace_toim[4] = {
+    0x00,       /* INTERLACE_ODD */
+    0x02,       /* INTERLACE_EVEN */
+    0x01,       /* INTERLACE_BOTH */
+    0x01        /* PROGRESSIVE */
+};
+
+/* Table for stride pixel size checking */
+static const uint32_t gs_tbl_vin_stride_check[VIN_OUTPUT_FORMAT_NUM][2] = {
+    { VIN_OUTPUT_YCBCR422_8 , PIXEL_ALIGN_64     },
+    { VIN_OUTPUT_Y8_CbCr8   , PIXEL_ALIGN_128    },
+    { VIN_OUTPUT_Y8         , PIXEL_ALIGN_128    },
+    { VIN_OUTPUT_RAW8       , PIXEL_ALIGN_64     }
+};
+
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_Initialize
+* Description :  MIPI driver initialization processing
+* Arguments :    none
+* Return Value : none
+**********************************************************************/
+void R_MIPI_Initialize(void (* const init_func)(uint32_t),  // @suppress("Non-API function naming")
+        const uint32_t user_num)
+{
+    /* call back function */
+    if (NULL != init_func)
+    {
+        init_func (user_num);
+    }
+
+    /* Mipi driver internal status initialize */
+    gs_mipi_state = MIPI_POWOFF;
+
+    return;
+}   /* End of function R_MIPI_Initialize() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_Open
+* Description :  This function performs the following processing
+*                - Parameter check.
+*                - MIPI sw reset.
+*                - Initialization of PHY register.
+* Arguments :    mipi_data : MIPI setting parameter
+* Return Value : Error code
+**********************************************************************/
+e_mipi_error_t R_MIPI_Open(const st_mipi_param_t * const mipi_data) // @suppress("Non-API function naming")
+{
+    e_mipi_error_t merr = MIPI_OK;
+    uint32_t cnt;
+
+    /* Check MIPI State */
+    if (gs_mipi_state != MIPI_POWOFF)
+    {
+        merr = MIPI_STATUS_ERR;
+    }
+
+    /* Check Parameter */
+    if (merr == MIPI_OK)
+    {
+        /* This implicit casting is valid because either values are pointer */
+        if (mipi_data == NULL)
+        {
+            /* NULL CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if ((mipi_data->mipi_lanenum != 1) && (mipi_data->mipi_lanenum != 2))
+        {
+            /* Lane Num == 1 or 2 ? */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if (mipi_data->mipi_vc > 3)
+        {
+            /* Virtual Channel == 0 to 3 ? */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if ((mipi_data->mipi_interlace != MIPI_PROGRESSIVE) && (mipi_data->mipi_interlace != MIPI_INTERLACE))
+        {
+            /* Interlace or Progressive ? */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if (mipi_data->mipi_laneswap > 1)
+        {
+            /* Mipi Lane Swap Setting ? */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if (mipi_data->mipi_outputrate > (mipi_data->mipi_lanenum * 1000))
+        {
+            /* Mipi Data Send Speed ? */
+            merr = MIPI_PARAM_ERR;
+        }
+        else
+        {
+            /* Do Nothing */
+            ;
+        }
+    }
+
+    if (merr == MIPI_OK)
+    {
+        /* MIPI SW-Reset */
+        CSI2LINK.TREF.BIT.TREF = 1;
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.SRST.BIT.SRST = 1;
+        for (cnt = (MIPI_1US_WAIT * 5); cnt > 0; cnt--)
+        {
+            /* Do nothing 5us wait */
+            ;
+        }
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.SRST.BIT.SRST = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        /* MIPI D-PHY Tths_prepare parameter */
+        CSI2LINK.PHYTIM3.BIT.THS_PREPARE  = mipi_data->mipi_phy_timing.mipi_ths_prepare;
+
+        /* MIPI D-PHY Tths_settle parameter */
+        CSI2LINK.PHYTIM3.BIT.THS_SETTLE   = mipi_data->mipi_phy_timing.mipi_ths_settle;
+
+        /* MIPI D-PHY Tclk_prepare parameter */
+        CSI2LINK.PHYTIM2.BIT.TCLK_PREPARE = mipi_data->mipi_phy_timing.mipi_tclk_prepare;
+
+        /* MIPI D-PHY Tclk_settle parameter */
+        CSI2LINK.PHYTIM2.BIT.TCLK_SETTLE  = mipi_data->mipi_phy_timing.mipi_tclk_settle;
+
+        /* MIPI D-PHY Tclk_miss parameter */
+        CSI2LINK.PHYTIM2.BIT.TCLK_MISS    = mipi_data->mipi_phy_timing.mipi_tclk_miss;
+
+        /* MIPI D-PHY Tint parameter */
+        CSI2LINK.PHYTIM1.BIT.T_INIT_SLAVE = mipi_data->mipi_phy_timing.mipi_t_init_slave;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.FLD.BIT.FLD_NUM     = mipi_data->mipi_frametop;
+
+        /* Top frame */
+        CSI2LINK.FLD.BIT.FLD_DET_SEL = 0;
+
+        if (mipi_data->mipi_interlace == MIPI_INTERLACE)
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            CSI2LINK.FLD.BIT.FLD_EN = 1; /* Top frame detectable */
+        }
+        else
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            CSI2LINK.FLD.BIT.FLD_EN = 0; /* Top frame undetectable */
+        }
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.CHKSUM.BIT.CRC_EN            = 1;      /* CRC Checkable */
+        CSI2LINK.CHKSUM.BIT.ECC_EN            = 1;      /* ECC error correctable */
+        CSI2LINK.VCDT.BIT.VCDT_EN             = 1;      /* Channel Setting */
+        CSI2LINK.VCDT.BIT.SEL_VC              = mipi_data->mipi_vc;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.VCDT.BIT.SEL_DT_ON           = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.VCDT.BIT.SEL_DT              = 0x2A;   /* RAW8 */
+        CSI2LINK.FRDT.BIT.DT_FS               = 0;      /* Frame type setting */
+        CSI2LINK.FRDT.BIT.DT_FE               = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.LINKCNT.BIT.REG_MONI_PACT_EN = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.LINKCNT.BIT.MONITOR_EN       = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.PHYCNT.BIT.SHUTDOWNZ         = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.PHYCNT.BIT.RSTZ              = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.PHYCNT.BIT.ENABLECLK         = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.PHYCNT.BIT.ENABLE_0          = 1;
+
+        if (mipi_data->mipi_lanenum == 2)
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            CSI2LINK.PHYCNT.BIT.ENABLE_1      = 1;
+        }
+        else
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            CSI2LINK.PHYCNT.BIT.ENABLE_1      = 0;
+        }
+
+        for (cnt = (MIPI_1US_WAIT * 25); cnt > 0; cnt--)
+        {
+            /* Do nothing (25us wait) */
+            ;
+        }
+
+        /* MIPI State Update */
+        gs_mipi_state = MIPI_STOP;
+    }
+
+    return merr;
+}   /* End of function R_MIPI_Open() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_Close
+* Description :  This function performs the following processing
+*                - Check MIPI state.
+*                - MIPI interruput all disable.
+*                - VIN capture stop.
+*                - MIPI sw-reset.
+*                - Calls the user-defined function specified in finalize_func.
+* Arguments :    finalize_func : Pointer to a user-defined function
+*                user_num  : User defined number
+* Return Value : Error code
+**********************************************************************/
+e_mipi_error_t R_MIPI_Close(void (* const finalize_func)(uint32_t),  // @suppress("Non-API function naming")
+        const uint32_t user_num)
+{
+    e_mipi_error_t merr = MIPI_OK;
+
+    /* Check MIPI State */
+    if( ( gs_mipi_state != MIPI_STOP ) && ( gs_mipi_state != MIPI_CAPTURE ) )
+    {
+        merr = MIPI_STATUS_ERR;
+    }
+
+    if( merr == MIPI_OK )
+    {
+        /* Interrupt Disable and Mask */
+        CSI2LINK.INTEN.LONG    = INTEN_ALL_CLEAR;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.INTCLOSE.LONG = INTEN_MASK_ALL_SET;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0IE.LONG          = VOIE_ALL_CLEAR;
+
+        /* Capture Stop */
+        VIN.V0MC.BIT.ME = 0;    /* VIN Stop */
+        VIN.V0FC.BIT.SC = 0;    /* Capture mode off */
+        VIN.V0FC.BIT.CC = 0;
+
+        /* MIPI Reset */
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.PHYCNT.BIT.SHUTDOWNZ = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.PHYCNT.BIT.RSTZ      = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.SRST.BIT.SRST        = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        CSI2LINK.SRST.BIT.SRST        = 0;
+
+        /* MIPI State Update */
+        gs_mipi_state = MIPI_POWOFF;
+
+        /* Callback function */
+        if (finalize_func != 0)
+        {
+            finalize_func(user_num);
+        }
+    }
+
+    return merr;
+}   /* End of function R_MIPI_Close() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_Setup
+* Description :  This function performs the following processing
+*                - Parameter check.
+*                - Initialization of VIN register.
+*                - VIN scaling setting.
+*                - VIN clipping setting.
+* Arguments :    vin_setup : VIN setting parameter
+* Return Value : Error code
+**********************************************************************/
+e_mipi_error_t R_MIPI_Setup(const st_vin_setup_t * const vin_setup ) // @suppress("Non-API function naming")
+{
+    e_mipi_error_t merr = MIPI_OK;
+    uint8_t scale_enable;
+
+    /* Check MIPI State */
+    if( gs_mipi_state != MIPI_STOP )
+    {
+        merr = MIPI_STATUS_ERR;
+    }
+
+    /* Check Parameter */
+    if( merr == MIPI_OK )
+    {
+        /* This implicit casting is valid because either values are pointer */
+        if (vin_setup == NULL)
+        {
+            /* NULL CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if (vin_setup->vin_inputformat > VIN_INPUT_RAW8)
+        {
+            /* RANGE CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if (vin_setup->vin_outputformat > VIN_OUTPUT_RAW8)
+        {
+            /* RANGE CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if (vin_setup->vin_outputendian > VIN_OUTPUT_EN_BIG)
+        {
+            /* RANGE CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if (vin_setup->vin_interlace > VIN_PROGRESSIVE)
+        {
+            /* RANGE CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if ((vin_setup->vin_ycoffset & 0x7F) != 0)
+        {
+            /* CHECK MULTIPLE of 128 */
+            merr = MIPI_PARAM_ERR;
+        }
+        else
+        {
+            /* Check stride size */
+            if (vin_setup->vin_stride <
+                (vin_setup->vin_preclip.vin_preclip_endx - vin_setup->vin_preclip.vin_preclip_startx))
+            {
+                /* Minimal than pre-clip horizontal size in case of scale off */
+                merr = MIPI_PARAM_ERR;
+            }
+            else
+            {
+                uint32_t count;
+                for (count = 0; count < VIN_OUTPUT_FORMAT_NUM; count++)
+                {
+                    if ((vin_setup->vin_outputformat == gs_tbl_vin_stride_check[count][OUTPUT_FORMAT_ENUM]) &&
+                        ((vin_setup->vin_stride & gs_tbl_vin_stride_check[count][STRIDE_ALIGN_SIZE]) != 0))
+                    {
+                        /* Stride size is not aligned with target output format specification */
+                        merr = MIPI_PARAM_ERR;
+                    }
+                }
+            }
+        }
+    }
+
+    if (merr == MIPI_OK)
+    {
+        /* Check PreClip Parameter */
+        if ((vin_setup->vin_preclip.vin_preclip_starty > vin_setup->vin_preclip.vin_preclip_endy) ||
+            ((vin_setup->vin_preclip.vin_preclip_endy - vin_setup->vin_preclip.vin_preclip_starty) < 1))
+        {
+            /* RANGE CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else if ((vin_setup->vin_preclip.vin_preclip_startx > vin_setup->vin_preclip.vin_preclip_endx) ||
+            ((vin_setup->vin_preclip.vin_preclip_endx - vin_setup->vin_preclip.vin_preclip_startx) < 6) ||
+            ((vin_setup->vin_preclip.vin_preclip_startx % 2) != 0) ||
+            (((vin_setup->vin_preclip.vin_preclip_endx - vin_setup->vin_preclip.vin_preclip_startx) % 2) == 0))
+        {
+            /* RANGE CHECK */
+            merr = MIPI_PARAM_ERR;
+        }
+        else
+        {
+            /* Do Nothing */
+            ;
+        }
+    }
+
+    if( merr == MIPI_OK )
+    {
+        /* VIN Initial Setting */
+        VIN.V0MC.BIT.CLP   = 0;          /* YUV Clip default setting */
+        VIN.V0MC.BIT.SCLE  = 0;          /* Scaling Off */
+        VIN.V0MC.BIT.LUTE  = 0;          /* LUT conversion Off */
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.YCAL  = vin_setup->vin_input_align;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.INF   = gs_cnvtbl_inputformat_toinf[vin_setup->vin_inputformat];
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.DC    = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.EN    = vin_setup->vin_outputendian;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.IM    = gs_cnvtbl_interlace_toim[vin_setup->vin_interlace];
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.BPS        = 1;   /* Do not convert */
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.ME         = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0CSI_IFMD.BIT.DES0 = 1;                                  /* Eexpand bit to '0' (8 or 10bit -> 12bit) */
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR2.BIT.FTEV     = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR2.BIT.VLV      = 1;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR2.BIT.FTEH     = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR2.BIT.HLV      = 0;
+
+        if (vin_setup->vin_outputformat == VIN_OUTPUT_RAW8)
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            VIN.V0IS.LONG           = (vin_setup->vin_stride / 2);
+        }
+        else
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            VIN.V0IS.LONG           = vin_setup->vin_stride;
+        }
+
+        /* Pre Clip Setting */
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0SLPrC.LONG        = vin_setup->vin_preclip.vin_preclip_starty;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0ELPrC.LONG        = vin_setup->vin_preclip.vin_preclip_endy;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0SPPrC.LONG        = vin_setup->vin_preclip.vin_preclip_startx;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0EPPrC.LONG        = vin_setup->vin_preclip.vin_preclip_endx;
+
+        /* Scaling Setting */
+        VIN.V0UDS_CTRL.BIT.AMD    = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_CTRL.BIT.BC     = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_CTRL.BIT.NE_RCR = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_CTRL.BIT.NE_BCB = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_CTRL.BIT.NE_GY  = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_SCALE.LONG = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_PASS_BWIDTH.BIT.BWIDTH_H = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_PASS_BWIDTH.BIT.BWIDTH_V = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_CLIP_SIZE.BIT.CL_HSIZE = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UDS_CLIP_SIZE.BIT.CL_VSIZE = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR.BIT.A8BIT              = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR.BIT.EVA                = 0;
+
+        switch (vin_setup->vin_inputformat)
+        {
+            case VIN_INPUT_YCBCR422_8:
+            case VIN_INPUT_YCBCR422_8I:
+                if (vin_setup->vin_outputformat == VIN_OUTPUT_Y8_CbCr8)
+                {
+                    /* Output Y and C, and those are separated */
+                    VIN.V0DMR.BIT.YMODE = VIN_YMODE_YC_ASIS;    /* Both of Y and C are outputed to memory */
+                    VIN.V0DMR.BIT.DTMD  = VIN_DTMD_YC_SEPARATE; /* Separate Y and C */
+                }
+                else if (vin_setup->vin_outputformat == VIN_OUTPUT_Y8)
+                {
+                    /* Output only Y */
+                    VIN.V0DMR.BIT.YMODE = VIN_YMODE_Y_8BIT;     /* Only Y is outputed to memory as 8bit data */
+                    VIN.V0DMR.BIT.DTMD  = VIN_DTMD_YC_SEPARATE; /* Separate Y and C */
+                }
+                else if (vin_setup->vin_outputformat == VIN_OUTPUT_YCBCR422_8)
+                {
+                    /* Output Y and C, and those are not separated */
+                    VIN.V0DMR.BIT.YMODE = VIN_YMODE_YC_ASIS;    /* Both of Y and C are outputed to memory */
+                    VIN.V0DMR.BIT.DTMD  = VIN_DTMD_NOT_CONVERT; /* Do not separate Y and C */
+                }
+                else
+                {
+                    /* This driver do not support other format conversion */
+                    merr = MIPI_PARAM_ERR;
+                }
+            break;
+            case VIN_INPUT_RAW8:
+
+                /* Set as default */
+                VIN.V0DMR.BIT.YMODE = VIN_YMODE_YC_ASIS;    /* Both of Y and C are outputed to memory */
+                VIN.V0DMR.BIT.DTMD  = VIN_DTMD_NOT_CONVERT; /* Do not separate Y and C */
+            break;
+            case VIN_INPUT_YCBCR422_10:
+            case VIN_INPUT_RGB888:
+            default:
+
+                /* Not support */
+                merr = MIPI_PARAM_ERR;
+            break;
+        }
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR.BIT.EXRGB   = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR.BIT.BPSM    = vin_setup->vin_output_swap;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0DMR.BIT.ABIT    = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0UVAOF.BIT.UVAOF = vin_setup->vin_ycoffset;
+    }
+
+    return merr;
+}   /* End of function R_MIPI_Setup() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_SetBufferAdr
+* Description :  This function performs the following processing
+*                - Parameter check.
+*                - VIN setting buffer address.
+* Arguments :    buffer_no  : Select buffer base (MB1, MB2, MB3)
+*                bufferBase : Buffer base address
+* Return Value : Error code
+**********************************************************************/
+e_mipi_error_t R_MIPI_SetBufferAdr(const uint8_t buffer_no,  // @suppress("Non-API function naming")
+        const uint8_t * const bufferBase)
+{
+    e_mipi_error_t merr  = MIPI_OK;
+
+    /* This casting is valid because uint32_t and unsigned long is same byte length */
+    uint32_t vin_intf  = VIN.V0IE.LONG;
+
+    /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+    uint32_t mipi_intf = CSI2LINK.INTCLOSE.LONG;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    VIN.V0IE.LONG          = 0;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    CSI2LINK.INTCLOSE.LONG = INTEN_MASK_ALL_SET;
+
+    /* Check MIPI State */
+    if( ( gs_mipi_state != MIPI_STOP ) && ( gs_mipi_state != MIPI_CAPTURE ) )
+    {
+        merr = MIPI_STATUS_ERR;
+    }
+
+    /* Check Parameter */
+    if( merr == MIPI_OK )
+    {
+        if( buffer_no > 2 )
+        {
+            merr = MIPI_PARAM_ERR;
+        }
+        /* This implicit casting(right side statement) is valid because either values are pointer */
+        else if(bufferBase == NULL)
+        {
+            merr = MIPI_PARAM_ERR;
+        }
+        /* This casting is valid because this processing just checking address as value */
+        else if( ( ((uint32_t)bufferBase) & 0x7FUL ) != 0 )
+        {
+            merr = MIPI_PARAM_ERR;
+        }
+    }
+
+    if( merr == MIPI_OK )
+    {
+        if( buffer_no == 0 )
+        {
+            /* This casting is valid because this function required to hand the pointer as value */
+            VIN.V0MB1.LONG = R_MIPI_CPUVAddrToSysPAddr((uint32_t)bufferBase);
+        }
+        else if( buffer_no == 1 )
+        {
+            /* This casting is valid because this function required to hand the pointer as value */
+            VIN.V0MB2.LONG = R_MIPI_CPUVAddrToSysPAddr((uint32_t)bufferBase);
+        }
+        else
+        {
+            /* This casting is valid because this function required to hand the pointer as value */
+            VIN.V0MB3.LONG = R_MIPI_CPUVAddrToSysPAddr((uint32_t)bufferBase);
+        }
+    }
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    VIN.V0IE.LONG          = vin_intf;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    CSI2LINK.INTCLOSE.LONG = mipi_intf;
+
+    return merr;
+}   /* End of function R_MIPI_SetBufferAdr() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_InterruptEnable
+* Description :  Set the interrupt enable register of MIPI and VIN
+* Arguments :    param : Interrupt settings
+* Return Value : none
+**********************************************************************/
+void R_MIPI_InterruptEnable(const st_mipi_int_t * const param) // @suppress("Non-API function naming")
+{
+    uint32_t int_type      = param->type;
+    uint32_t mipi_int_type = 0;
+    uint32_t vin_int_type  = 0;
+    uint32_t count;
+
+    /* At first, mask all interrupt */
+    VIN.V0IE.LONG          = VOIE_ALL_CLEAR;      /* Set all VIN interrupt disable at once */
+    CSI2LINK.INTEN.LONG    = INTEN_ALL_CLEAR;     /* Set all MIPI interrupt disable at once */
+    CSI2LINK.INTCLOSE.LONG = INTEN_MASK_ALL_SET;  /* Mask all MIPI interrupt at once  */
+
+    /* Callback function pointer */
+    Mipi_Callback = param->p_mipiCallback;
+    Vin_Callback  = param->p_vinCallback;
+
+    /* check interrupt type of MIPI */
+    for (count = 0; count < MIPI_INTERRUPT_TYPE_NUM; count++)
+    {
+        if((int_type & gs_tbl_mipi_interrupt_bit[count][INTERRUPT_FLAG]) ==
+            gs_tbl_mipi_interrupt_bit[count][INTERRUPT_FLAG])
+        {
+            mipi_int_type |= gs_tbl_mipi_interrupt_bit[count][INTERRUPT_REGBIT];
+        }
+    }
+
+    /* check interrupt type of VIN */
+    for (count = 0; count < VIN_INTERRUPT_TYPE_NUM; count++)
+    {
+        if((int_type & gs_tbl_vin_interrupt_bit[count][INTERRUPT_FLAG]) ==
+            gs_tbl_vin_interrupt_bit[count][INTERRUPT_FLAG])
+        {
+            vin_int_type |= gs_tbl_vin_interrupt_bit[count][INTERRUPT_REGBIT];
+            if (gs_tbl_vin_interrupt_bit[count][1] == VIN_INT_SCANLINE)
+            {
+                /* This implicit casting is valid because unsigned long is acceptable the value */
+                VIN.V0SI.BIT.SI = (param->line_num & VNSI_WRITE_MASK);
+            }
+        }
+    }
+
+    /* Interrupt Enable */
+    CSI2LINK.INTSTATE.LONG |=  mipi_int_type;  /* Clear all MIPI interrupt state */
+    VIN.V0INTS.LONG        |=  vin_int_type;   /* Clear all VIN  interrupt state */
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    CSI2LINK.INTEN.LONG    |=  mipi_int_type;                         /* Set MIPI interrupt enable */
+    CSI2LINK.INTCLOSE.LONG  =  (INTEN_MASK_ALL_SET - mipi_int_type);  /* Mask unused interrupt */
+    VIN.V0IE.LONG          |=  vin_int_type;                          /* Set VIN interrupt enable */
+}   /* End of function R_MIPI_InterruptEnable() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_InterruptDisable
+* Description :  Clear the interrupt enable register of MIPI and VIN
+* Arguments :    none
+* Return Value : none
+**********************************************************************/
+void R_MIPI_InterruptDisable(void) // @suppress("Non-API function naming")
+{
+    /* Callback function pointer clear */
+    Mipi_Callback = 0;
+    Vin_Callback  = 0;
+
+    /* Interrupt Enable Register claer */
+    VIN.V0IE.LONG          = VOIE_ALL_CLEAR;      /* Set all VIN interrupt disable */
+    CSI2LINK.INTEN.LONG    = INTEN_ALL_CLEAR;     /* Set all MIPI interrupt disable */
+    CSI2LINK.INTCLOSE.LONG = INTEN_MASK_ALL_SET;  /* Mask all MIPI interrupt */
+}   /* End of function R_MIPI_InterruptDisable() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_GetInfo
+* Description :  This function performs the following processing
+*                - Getting registers status (Line Count/Field Status/Frame Buffer Status).
+* Arguments :    infoType : registers status
+* Return Value : Error code
+**********************************************************************/
+e_mipi_error_t R_MIPI_GetInfo(st_vin_info_type_t * infoType) // @suppress("Non-API function naming")
+{
+    e_mipi_error_t merr = MIPI_OK;
+
+    /* Check MIPI State */
+    if( ( gs_mipi_state != MIPI_STOP ) && ( gs_mipi_state != MIPI_CAPTURE ) ){
+        merr = MIPI_STATUS_ERR;
+    }
+
+    /* Set Status */
+    infoType->vin_nowcaptureline  = VIN.V0LC.BIT.LC; /* Line Count */
+    infoType->vin_nowcapturefield = VIN.V0MS.BIT.FS; /* Field Status */
+    infoType->vin_nowcapturebase  = VIN.V0MS.BIT.FBS;/* Frame Buffer Status */
+
+    return merr;
+}   /* End of function R_MIPI_GetInfo() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_CaptureStart
+* Description :  This function performs the following processing
+*                - Setting capture mode( Single or Continuous ).
+*                - Capture start.
+* Arguments :    captureMode : Single or Continuous
+* Return Value : Error code
+**********************************************************************/
+e_mipi_error_t R_MIPI_CaptureStart(const e_mipi_capture_mode_t captureMode) // @suppress("Non-API function naming")
+{
+    e_mipi_error_t merr = MIPI_OK;
+    uint32_t intstate;
+
+    /* This casting is valid because uint32_t and unsigned long is same byte length */
+    uint32_t vin_intf = VIN.V0IE.LONG;
+
+    /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+    uint32_t mipi_intf = CSI2LINK.INTCLOSE.LONG;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    VIN.V0IE.LONG = 0;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    CSI2LINK.INTCLOSE.LONG = INTEN_MASK_ALL_SET;
+
+    /* Check MIPI State */
+    if( ( gs_mipi_state != MIPI_STOP ) && ( gs_mipi_state != MIPI_CAPTURE ) )
+    {
+        merr = MIPI_STATUS_ERR;
+    }
+
+    if( merr == MIPI_OK )
+    {
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0FC.BIT.CC = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0FC.BIT.SC = 0;
+
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.ME = 1; /* Capture Enable */
+
+        if (captureMode == MIPI_SINGLE_MODE)
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            VIN.V0FC.BIT.SC = 1; /* Single Capture Mode */
+        }
+        else
+        {
+            /* This implicit casting is valid because unsigned long is acceptable the value */
+            VIN.V0FC.BIT.CC = 1;
+        }
+
+        /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+        intstate               = CSI2LINK.INTSTATE.LONG;
+
+        /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+        CSI2LINK.INTSTATE.LONG = intstate;
+
+        /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+        intstate               = VIN.V0INTS.LONG;
+
+        /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+        VIN.V0INTS.LONG        = intstate;
+        gs_mipi_state             = MIPI_CAPTURE;
+    }
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    VIN.V0IE.LONG          = vin_intf;
+
+    /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+    CSI2LINK.INTCLOSE.LONG = mipi_intf;
+
+    return merr;
+}   /* End of function R_MIPI_CaptureStart() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_CaptureStop
+* Description :  This function performs the following processing
+*                - Capture stop.
+* Arguments :    none
+* Return Value : Error code
+**********************************************************************/
+e_mipi_error_t R_MIPI_CaptureStop(void) // @suppress("Non-API function naming")
+{
+    e_mipi_error_t merr      = MIPI_OK;
+
+    /* This casting is valid because uint32_t and unsigned long is same byte length */
+    uint32_t     vin_intf  = VIN.V0IE.LONG;
+
+    /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+    uint32_t     mipi_intf = CSI2LINK.INTCLOSE.LONG;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    VIN.V0IE.LONG          = 0;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    CSI2LINK.INTCLOSE.LONG = INTEN_MASK_ALL_SET;
+
+    /* Check MIPI State */
+    if( gs_mipi_state != MIPI_CAPTURE )
+    {
+        merr = MIPI_STATUS_ERR;
+    }
+
+    if( merr == MIPI_OK )
+    {
+        /* This implicit casting is valid because unsigned long is acceptable the value */
+        VIN.V0MC.BIT.ME = 0;         /* Capture Disable */
+        gs_mipi_state      = MIPI_STOP;
+    }
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    VIN.V0IE.LONG          = vin_intf;
+
+    /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+    CSI2LINK.INTCLOSE.LONG = mipi_intf;
+
+    return merr;
+}   /* End of function R_MIPI_CaptureStop() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_InterruptHandler
+* Description :  This function performs the following processing
+*                - Check MIPI interrupt type.
+*                - Call the callback funtion.
+* Arguments :    int_sense   : sense
+* Return Value : none
+**********************************************************************/
+void R_MIPI_InterruptHandler( uint32_t int_sense ) // @suppress("Non-API function naming")
+{
+    volatile uint32_t intdata;
+    uint32_t          mipi_cnt;
+    uint32_t          mipi_int_type = 0;
+
+    /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+    intdata                = CSI2LINK.INTSTATE.LONG;
+
+    /* This implicit casting is valid because uint32_t and unsigned long is same 1byte length */
+    CSI2LINK.INTSTATE.LONG = intdata;    /* Clear interrupt status */
+
+    /* check interrupt type of MIPI */
+    for (mipi_cnt = 0; mipi_cnt < MIPI_INTERRUPT_TYPE_NUM; mipi_cnt++)
+    {
+        if((intdata & gs_tbl_mipi_interrupt_bit[mipi_cnt][INTERRUPT_REGBIT]) ==
+            gs_tbl_mipi_interrupt_bit[mipi_cnt][INTERRUPT_REGBIT])
+        {
+            mipi_int_type |= gs_tbl_mipi_interrupt_bit[mipi_cnt][INTERRUPT_FLAG];
+        }
+    }
+
+    /* If callback function is set, call it */
+    if (Mipi_Callback != NULL)
+    {
+        /* This casting is valid because the value never out of range of e_mipi_interrupt_type_t */
+        Mipi_Callback((e_mipi_interrupt_type_t)mipi_int_type);
+    }
+}   /* End of function R_MIPI_InterruptHandler() */
+
+/**********************************************************************
+*
+* Function Name: R_VIN_InterruptHandler
+* Description :  This function performs the following processing
+*                - Check VIN interrupt type.
+*                - Call the callback funtion.
+* Arguments :    int_sense   : sense
+* Return Value : none
+**********************************************************************/
+void R_VIN_InterruptHandler( uint32_t int_sense ) // @suppress("Non-API function naming")
+{
+    volatile uint32_t intdata;
+    uint32_t          vin_cnt;
+    uint32_t          vin_int_type = 0;
+
+    /* This casting is valid because uint32_t and unsigned long is same byte length */
+    intdata         = VIN.V0INTS.LONG;
+
+    /* This implicit casting is valid because unsigned long is acceptable the value */
+    VIN.V0INTS.LONG = intdata;   /* Clear interrupt status */
+
+    /* check interrupt type of VIN */
+    for (vin_cnt = 0; vin_cnt < VIN_INTERRUPT_TYPE_NUM; vin_cnt++)
+    {
+        if((intdata & gs_tbl_vin_interrupt_bit[vin_cnt][INTERRUPT_REGBIT]) ==
+            gs_tbl_vin_interrupt_bit[vin_cnt][INTERRUPT_REGBIT])
+        {
+            vin_int_type |= gs_tbl_vin_interrupt_bit[vin_cnt][INTERRUPT_FLAG];
+        }
+    }
+
+    /* If callback function is set, call it */
+    if (Vin_Callback != NULL)
+    {
+        /* This casting is valid because the value never out of range of e_mipi_interrupt_type_t */
+        Vin_Callback((e_mipi_interrupt_type_t)vin_int_type);
+    }
+}   /* End of function R_VIN_InterruptHandler() */
+
+/**********************************************************************
+*
+* Function Name: calc_scale_passband
+* Description :  This function calculate video passband width
+* Arguments :    scale_int   : integral part of scaling factor
+*                scale_fra   : fractional part of scaling factor
+* Return Value : pass band width
+**********************************************************************/
+static uint8_t calc_scale_passband(uint16_t scale_int, uint16_t scale_fra)
+{
+    uint8_t mulm;
+    uint8_t width;
+
+    mulm = 1;
+    if (scale_int >= 8)
+    {
+        mulm = 4;
+    }
+    else if (scale_int >= 4)
+    {
+        mulm = 2;
+    }
+    /****** Calculate passband width ******/
+    width = (uint8_t) ((64 * (4096 * mulm)) / ((4096 * scale_int) + scale_fra));
+
+    return width;
+}   /* End of function calc_scale_passband() */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GR-PEACH_video/targets/TARGET_RZ_A2XX/drivers/r_mipi/userdef/r_mipi_userdef_api.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,178 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************
+* File Name : r_mipi_userdef_api.c
+* Version : 0.01
+* Description : RZ/A2M MIPI driver user function
+**************************************************************************/
+/***************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 23.08.2018 0.01 pre version created
+**************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "r_mipi_api.h"
+#include "r_mipi_user.h"
+#include "mmu_init.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* For MIPI */
+#define MSTP75_BIT              (0x20u)
+/* For VIN */
+#define MSTP66_BIT              (0x40u)
+#define STBRQ27_BIT             (0x80u)
+#define STBAK27_BIT             (0x80u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_CPUVAddrToSysPAddr
+* Description :  This function performs the following processing:
+*                - Get the System Physical address of the given virtual memory address.
+* Arguments :    vaddr : virtual address
+* Return Value : physical address
+**********************************************************************/
+uint32_t R_MIPI_CPUVAddrToSysPAddr(uint32_t vaddr)
+{
+    uint32_t ret;
+
+    ret = R_MMU_VAtoPA(vaddr);
+    return ret;
+}   /* End of function R_MIPI_CPUVAddrToSysPAddr() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_OnInitialize
+* Description :  MIPI and VIN User definition part of initialize
+* Arguments :    user_num : user specify argument
+* Return Value : none
+**********************************************************************/
+void R_MIPI_OnInitialize (const uint32_t user_num)
+{
+    uint32_t            reg_data;
+    volatile uint8_t    dummy_read;
+
+    /* MIPI */
+    /* Standby control register 7 (STBCR7)
+        b5      --0-----;  MSTP75 : 0 : MIPI enable */
+    reg_data    = (uint32_t)CPG.STBCR7.BYTE & (uint32_t)~MSTP75_BIT;
+    /* This casting is valid because uint8_t and unsigned char is same 1byte length */
+    CPG.STBCR7.BYTE  = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR7.BYTE;
+
+    /* VIN */
+    /* Standby control register 6 (STBCR6)
+        b6      -0------;  MSTP66 : 0 : VIN enable */
+    reg_data    = (uint32_t)CPG.STBCR6.BYTE & (uint32_t)~MSTP66_BIT;
+    /* This casting is valid because uint8_t and unsigned char is same 1byte length */
+    CPG.STBCR6.BYTE  = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR6.BYTE;
+    (void)dummy_read;
+
+    /* Standby Request Register 2 (STBREQ2)
+        b7      0--------;  STBRQ27 : The standby request to VIN is invalid. */
+    reg_data    = (uint32_t)CPG.STBREQ2.BYTE & (uint32_t)~STBRQ27_BIT;
+    /* This casting is valid because uint8_t and unsigned char is same 1byte length */
+    CPG.STBREQ2.BYTE = (uint8_t)reg_data;
+    /* Standby Acknowledge Register 2 (STBACK2)
+        b5      --*-----;  STBAK27 : Standby acknowledgment from VIN. */
+    while (((uint32_t)CPG.STBACK2.BYTE & (uint32_t)STBAK27_BIT) != 0u) {
+        /* Wait for the STBAK27 to be cleared to 0. */
+    }
+
+    InterruptHandlerRegister(CSII_IRQn, R_MIPI_InterruptHandler);
+    GIC_SetPriority(CSII_IRQn, (uint8_t)MIPI_INTERRUPT_PRIORITY);
+    GIC_SetConfiguration(CSII_IRQn, 1);
+    GIC_EnableIRQ(CSII_IRQn);
+
+    InterruptHandlerRegister(VINI_IRQn, R_VIN_InterruptHandler);
+    GIC_SetPriority(VINI_IRQn, (uint8_t)VIN_INTERRUPT_PRIORITY);
+    GIC_SetConfiguration(VINI_IRQn, 1);
+    GIC_EnableIRQ(VINI_IRQn);
+
+}   /* End of function R_MIPI_OnInitialize() */
+
+/**********************************************************************
+*
+* Function Name: R_MIPI_OnFinalize
+* Description :  MIPI User definition part of finalize
+* Arguments :    user_num : user specify argument
+* Return Value : none
+**********************************************************************/
+void R_MIPI_OnFinalize( const uint32_t user_num )
+{
+    uint32_t            reg_data;
+    volatile uint8_t    dummy_read;
+
+    /* VIN */
+    /* Standby Request Register 2 (STBREQ2)
+        b7      1-------;  STBRQ27 : The standby request to VIN is valid. */
+    reg_data    = (uint32_t)CPG.STBREQ2.BYTE | (uint32_t)STBRQ27_BIT;
+    /* This casting is valid because uint8_t and unsigned char is same 1byte length */
+    CPG.STBREQ2.BYTE = (uint8_t)reg_data;
+
+    /* Standby Acknowledge Register 2 (STBACK2)
+        b5      *-------;  STBAK27 : Standby acknowledgment from VIN. */
+    while (((uint32_t)CPG.STBACK2.BYTE & (uint32_t)STBAK27_BIT) == 0u) {
+        /* Wait for the STBAK27 to be set to 1. */
+    }
+
+    /* Standby control register 6 (STBCR6)
+        b5      -1------;  MSTP66 : 0 : VIN disable */
+    reg_data    = (uint32_t)CPG.STBCR6.BYTE | (uint32_t)MSTP66_BIT;
+    /* This casting is valid because uint8_t and unsigned char is same 1byte length */
+    CPG.STBCR6.BYTE  = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR6.BYTE;
+
+    /* MIPI */
+    /* Standby control register 7 (STBCR7)
+        b5      --1-----;  MSTP75 : 0 : MIPI disable */
+    reg_data    = (uint32_t)CPG.STBCR7.BYTE | (uint32_t)MSTP75_BIT;
+    /* This casting is valid because uint8_t and unsigned char is same 1byte length */
+    CPG.STBCR7.BYTE  = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR7.BYTE;
+    (void)dummy_read;
+
+}   /* End of function R_MIPI_OnFinalize() */
+
+/* End of File */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/LICENSE.txt	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,40 @@
+END USER LICENSE AGREEMENT
+
+This End User License Agreement (this "EULA") is between you, on behalf of yourself and the company or other entity on whose behalf you are acting (together, "you" and "your") and Renesas Electronics Corporation, a Japanese corporation, with a principal place of business at 2-24 Toyosu 3-chome, koutou-Ku, Tokyo, Japan ("Renesas") and is effective from the date on which you download or import. In consideration of the mutual promises and covenants herein, you and Renesas hereby agree as follows: 
+
+
+1. Definitions.
+
+
+1.1."Open Source Code" means certain free or open source software and other components incorporated into or bundled with the Software which is subject to the Open Source Terms. 
+1.2."Open Source Terms" means the terms and conditions that are applicable to a given piece of Open Source Code. 
+1.3."Software" means, collectively, the software in source code, binary or library form, including all contents thereof, downloaded by you in connection with this EULA, including all upgrades, modifications and updates provided to you, if any, and all derivative works of software ("Derivatives"), and any materials, related to the Software made available by Renesas or its affiliates, in all cases, other than the Open Source Code. 
+
+2. License.
+ Subject to the terms and conditions hereof, Renesas, on behalf of itself and its subsidiaries, hereby grants to you a personal, non-exclusive, non-transferable, revocable license (without the right to sublicense) during the term hereof under Renesas' and its subsidiaries' intellectual property rights (excluding patent rights) in and to the Software to (1) use the Software for the purpose of internally evaluating and testing Renesas products ("Renesas Products"), (2) copy and modify the Software for the purpose of developing your system-level products that incorporate Renesas Products ("Customer Product"), (3) compile a binary version of the Software (including, for clarity, Software modified in accordance with the foregoing subsection (2)) and make (or have its contract manufacturer that is bound in writing by confidentiality and use restrictions no less restrictive than those set forth herein make) copies of such binary version solely as necessary to incorporate such binary version into a Renesas Product or Customer Product, and (4) distribute binary versions of such Software only as incorporated into Customer Products or Renesas Products. You acknowledge and agree that the Software may be bundled with or incorporate Open Source Code. This Open Source Code must be used in accordance with the applicable Open Source Terms in additional to the terms and conditions set forth in this EULA related to the Open Source Code. You hereby agree to fully comply with all such Open Source Terms. After downloading the Software, you may be required to agree to additional terms or conditions prior to accessing all or a portion of the Software ("Additional Terms"). To the extent the Software includes such Additional Terms, such Additional Terms shall supersede this EULA and the license terms set forth in this Section 2 shall not have any force or effect with respect to the applicable portion of the Software.
+
+
+3.Intellectual Property Ownership, Copyright Protection.
+ The Software and any authorized copies are the intellectual property of owned by Renesas. The structure, organization and code of the Software are the valuable copyrights, trade secrets and confidential information of Renesas. The Software that may be developed or created by you are protected by law, including without limitation, the copyright laws of Japan and other countries and by international treaty provisions. Renesas will retain all right, title and interest in and to all intellectual property rights related to the Software. If any intellectual property rights related to the Derivatives do not automatically inure to Renesas, you hereby irrevocably assign to Renesas, without additional consideration, all right, title and interest in and to all Derivatives, whether currently existing or created or developed later. Except as expressly stated herein, this EULA does not grant you any intellectual property rights related to the Software, and all rights not expressly granted are reserved by Renesas.
+
+4.Restrictions. 
+ You acknowledge that the Software is a valuable proprietary asset of Renesas. You will not: (a) disclose the Software, directly or indirectly, to any other person or entity that is not a party to this EULA except for those employees, contractors, and representatives of you on a strictly need-to-know basis who are subject to confidentiality obligations (and you will maintain the confidentiality of the Software with at least the same degree of care you use to protect your own confidential information, and no less than reasonable care); (b) make use of the Software except as expressly permitted hereunder; (c) decompile, decipher, disassemble, reverse engineer, or otherwise determine the source code contained in any non-source code versions (e.g., object code or binary versions) of the Software; or (d) except with the express prior written consent of Renesas, use the Software together with any open source code or otherwise take any action or fail to take any action that would cause the Software to be subject to any open source or other third party software terms or conditions.
+
+5.NO WARRANTY.
+ THE SOFTWARE IS DELIVERED TO YOU "AS IS," WHERE IS, AND WITH ALL FAULTS AND RENESAS, ITS SUBSIDIARIES, AND AFFILIATES, AND ITS AND THEIR EMPLOYEES, DIRECTORS, OFFICERS, CONSULTANTS, CUSTOMERS, SUPPLIERS, AND REPRESENTATIVES (COLLECTIVELY, THE "RENESAS PARTIES"), WHETHER EXPLICITLY OR IMPLICITLY, MAKE NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE SOFTWARE, INCLUDING AS TO THEIR USE AND PERFORMANCE. TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, THE RENESAS PARTIES HEREBY EXPRESSLY DISCLAIM ALL WARRANTIES OF ANY KIND, EXPLICIT OR IMPLIED, WITH RESPECT TO THE SOFTWARE, INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, SATISFACTORY QUALITY, ACCURACY, TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS, INTEGRATION, AND ANY WARRANTIES THAT MAY ARISE BY LAW OR OUT OF COURSE OF PERFORMANCE, COURSE OF DEALING OR USAGE OF TRADE. RENESAS DOES NOT WARRANT THAT THE SOFTWARE WILL MEET ANY REQUIREMENTS OR THAT THE USE THEREOF WILL BE ERROR FREE.
+
+6.LIMITATION OF LIABILITY AND INDEMNITY.
+ TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL ANY RENESAS PARTY BE LIABLE TO YOU UNDER OR IN CONNECTION WITH THIS EULA OR THE SOFTWARE (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU OR UNDER THIS EULA) FOR ANY LOSS, DAMAGES, CLAIMS OR COSTS WHATSOEVER, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, REVENUE, BUSINESS, SAVINGS, DATA, OR USE; OR ANY COST OF SUBSTITUTE PROCUREMENT, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY AS A RESULT OF BREACH OF ANY TERM OF THIS EULA, IN EACH CASE, WHETHER IN AN ACTION IN CONTRACT OR TORT, AND EVEN IF SUCH RENESAS PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF, HAD OTHER REASON TO KNOW, OR IN FACT KNEW OF THE POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. You shall indemnify, defend and hold the Renesas Parties harmless from and against any and all claims, actions, damages, demands, liabilities, costs and expenses, including without limitation reasonable attorneys' fees and expenses, resulting from the use of the Software by you or any other party acting, directly or indirectly, from or through you or resulting from any breach, default or other violation hereof by you.
+
+7.Export Control.
+ You hereby represent and warrant that you shall not use the Software for the purpose of disturbing international peace and security, including (i) the design, development, production, stockpiling or use of weapons of mass destruction such as nuclear, chemical or biological weapons or missiles, (ii) other military activities, or (iii) any use supporting these activities. You also hereby represent and warrant that you shall not sell, export, dispose of, license, rent, transfer, disclose or otherwise provide the Software to any third party, whether directly or indirectly, with knowledge or reason to know that the third party or any other party will engage in the activities described above. Furthermore, you hereby represent and warrant that you shall not directly or indirectly, export, re-export, transship or otherwise transfer the Software in violation of any applicable export control laws or regulations promulgated and administered by the governments of the countries asserting jurisdiction over the parties or their transactions.
+
+8.Term and Termination.
+ This EULA is effective until it is terminated. This EULA will terminate automatically if you fail to comply with any terms and conditions provided herein. You may also terminate this EULA at any time by uninstalling and destroying the Software (including, for clarity, the Derivatives) and any copies thereof. Upon termination hereof, you shall stop all use of the Software (including, for clarity, the Derivatives) and any copies thereof and destroy the Software (including, for clarity, the Derivatives) and any copies thereof , and the rights and licensed granted to you hereunder shall terminate. Section 1 and Sections 3 through 10 hereof shall survive any termination or expiration hereof. 
+
+9.Governing Law and Venue.
+ This EULA will be governed by and construed in accordance with the laws of Japan without regard to conflicts of laws rules. The Tokyo District Court in Japan shall have exclusive jurisdiction over all disputes relating to this EULA. Each of the parties hereby irrevocably waives any objection they may now or hereafter have as to the venue of any such action or proceeding brought in such court including but not limited to any objection that such court is an inconvenient forum. If any action at law or in equity is brought to enforce or interpret the provisions hereof, the prevailing party shall be entitled to recover all costs of litigation, including actual attorneys' fees, related incidental expenses, and court costs.
+
+10.General Provisions. 
+ If any part hereof is found void or unenforceable, it will not affect the validity of the balance hereof, which shall remain valid and enforceable according to its terms. This EULA may only be modified by a writing signed by an authorized officer of you and Renesas. Updates may be licensed to you by Renesas with additional or different terms. The failure of a party to enforce any provision hereof shall not constitute a waiver of such provision or the right of such party to enforce such provision or any other provision. This is the entire agreement between Renesas and you relating to the Software and the Derivatives and it supersedes any prior or contemporaneous representations, discussions, undertakings, communications or advertising relating to the Software, and the Derivatives. In the event of any conflict between any term or condition of this EULA and any term or condition of any applicable Additional Terms, the applicable term or condition of the Additional Terms shall apply and take precedence. With respect to the Open Source Code, in the event of any conflict between any term or condition of this EULA and any term or condition of any applicable Open Source Terms, the applicable term or condition of the Open Source Terms shall apply and take precedence. You may not assign this EULA or your rights or obligations hereunder to a third party without the consent of Renesas. Renesas may assign this EULA or any rights or obligations hereunder to a third party without your consent.
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGA.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: RGA.h $
+* $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+* Description:
+******************************************************************************/
+
+
+/* This is MAIN header file */
+
+#ifndef  RGA_H
+#define  RGA_H
+
+#include  "Project_Config.h"
+
+
+#ifdef _MSC_VER
+	#include  "PC/RGA_Sub_PC.h"
+	#include  "sub/bitblt_alpha.h"
+	#include  "PC/RGA_PC.h"
+#endif
+#ifdef _SH
+	#include  "SH7269/RGA_Sub_SH7269.h"
+	#include  "sub/bitblt_alpha.h"
+	#include  "SH7269/RGA_SH.h"
+#endif
+#ifdef R_ARM
+	#include  "r_ospl.h"
+	#include  "r_typedefs.h"
+	#include  "RGA_Port.h"
+#endif
+
+#include  "RGA_API.h"
+#ifdef  __cplusplus
+	#include  "RGA_Cpp.h"
+#endif
+
+
+/* Sample window surfaces library */
+#ifdef _MSC_VER
+	#include  <PC/RGA_SampleLib_RZ_A1H.h>
+#endif
+#ifdef _SH
+	#include  <SH7269/RGA_SampleLib_RZ_A1H.h>
+#endif
+#ifdef R_ARM
+	#include  "RGA_raw_image.h"
+	#include  "window_surfaces.h"
+	#include  "RGA_Port.h"
+#endif
+
+
+#endif  /* RGA_H */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_debug.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,81 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG debug header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.21
+*          - Added debugging messase function.
+*          2012.08.22
+*          - Updated coding format.
+*          - Added debug macro.
+*            - NCG_DEBUG_MAKE_MSG
+*            - NCG_DEBUG_PRINT_MSG
+*          2013.01.08
+*            - Fixed release code.
+*
+*******************************************************************************/
+
+#ifndef NCG_DEBUG_H
+#define NCG_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------------------------------*/
+#ifdef NCG_DEBUG
+/*-----------------------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#define NCG_ASSERT(EXPR)                            if (!(EXPR)) { NCGSYS_Abort(__FILE__, __LINE__, #EXPR); }
+
+#define NCG_DEBUG_MAKE_MSG_START( buff, format )    sprintf( (buff), format
+#define NCG_DEBUG_MAKE_MSG_PARAMETER( param )           , (param)
+#define NCG_DEBUG_MAKE_MSG_END(  )                  )
+#define NCG_DEBUG_PRINT_MSG( msg )                  printf( msg )
+
+#ifdef NCG_DEBUG_API_LOG
+
+#define NCG_DEBUG_PRINT_STRING( msg )               printf( "%s%s", (msg), NCG_CRLF )
+
+#else /* #ifdef NCG_DEBUG_API_LOG */
+
+#define NCG_DEBUG_PRINT_STRING( msg )               /* No process */
+
+#endif /* #ifdef NCG_DEBUG_API_LOG */
+
+#define NCG_DEBUG_MSG_BUFFER_SIZE                   512
+
+#define NCG_CRLF                                    "\n"
+
+extern void NCGSYS_Abort(const NCGchar *filename, NCGint32 line, const NCGchar *condition);
+
+extern char NCG_G_MASSAGE_BUFF[NCG_DEBUG_MSG_BUFFER_SIZE];
+
+/*-----------------------------------------------------------------------------------*/
+#else   /* NCG_DEBUG */
+/*-----------------------------------------------------------------------------------*/
+
+#define NCG_ASSERT(EXPR)                                /* No process */
+#define NCG_DEBUG_MAKE_MSG_START( buff, format )        /* No process */
+#define NCG_DEBUG_MAKE_MSG_PARAMETER( param )           /* No process */
+#define NCG_DEBUG_MAKE_MSG_END(  )                      /* No process */
+#define NCG_DEBUG_PRINT_MSG( msg )                      /* No process */
+
+#define NCG_DEBUG_PRINT_STRING( msg )                   /* No process */
+
+/*-----------------------------------------------------------------------------------*/
+#endif  /* NCG_DEBUG */
+/*-----------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_DEBUG_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_defs.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,113 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG Type Definitions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2011.03.04
+*          - Added the type of NCGfp.
+*          2012.08.22
+*          - Updated coding format.
+*          2012.11.14
+*          - Added the definition for Multi-Display.
+*             NCGDU_CH1
+*             NCGDU_CH2
+*          - Modified the type of NCGISRfp to NCGDUISRfp and NCGVGISRfp.
+*
+*******************************************************************************/
+
+#ifndef NCG_DEFS_H
+#define NCG_DEFS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+#define NCG_NULL    0
+#else
+#define NCG_NULL    ((void *)0)
+#endif
+
+#define NCG_FALSE   0
+#define NCG_TRUE    1
+
+#define NCG_UINT32_MAX (0xffffffffU)
+
+#define NCG_TIMEOUT_INFINITE NCG_UINT32_MAX
+#define NCG_INVALID_TLSINDEX NCG_UINT32_MAX
+
+/* Display chanel */
+#define NCGDU_CH1                   (0x00000001U)
+#define NCGDU_CH2                   (0x00000002U)
+
+
+#if !defined(NCG_UNREFERENCED_PARAMETER)
+#define NCG_UNREFERENCED_PARAMETER   R_UNREFERENCED_VARIABLE
+#endif
+
+/*
+ *  Error codes
+ */
+
+#define NCG_FIRST_ERROR (-255)
+enum
+{
+    NCG_no_err = 0,
+    NCG_err_unknown                 = NCG_FIRST_ERROR,
+    NCG_err_not_implemented         = NCG_FIRST_ERROR+ 1,
+    NCG_err_bad_parameter           = NCG_FIRST_ERROR+ 2,
+    NCG_err_no_host_mem             = NCG_FIRST_ERROR+ 3,
+    NCG_err_lost_host_mem           = NCG_FIRST_ERROR+ 4,
+    NCG_err_no_frame_mem            = NCG_FIRST_ERROR+ 5,
+    NCG_err_lost_frame_mem          = NCG_FIRST_ERROR+ 6,
+    NCG_err_already_created         = NCG_FIRST_ERROR+ 7,
+    NCG_err_isr_management_failed   = NCG_FIRST_ERROR+ 8,
+    NCG_err_wait_timeout            = NCG_FIRST_ERROR+ 9,
+    NCG_err_device_in_use           = NCG_FIRST_ERROR+10,
+    NCG_err_not_found               = NCG_FIRST_ERROR+11,
+    NCG_err_invalid_handle          = NCG_FIRST_ERROR+12,
+    NCG_err_resource_exceeded       = NCG_FIRST_ERROR+13,
+    NCG_last_err                    = NCG_FIRST_ERROR+14,
+};
+
+
+/*
+ *  NCG data type definitions
+ */
+
+typedef void                    NCGvoid;
+typedef unsigned int            NCGenum;
+typedef unsigned int            NCGboolean;
+typedef unsigned int            NCGbitfield;
+
+typedef char                    NCGchar;
+typedef signed char             NCGint8;
+typedef short                   NCGint16;
+typedef int                     NCGint32;
+typedef long long               NCGint64;
+typedef unsigned char           NCGuint8;
+typedef unsigned short          NCGuint16;
+typedef unsigned int            NCGuint32;
+typedef unsigned long long      NCGuint64;
+typedef float                   NCGfloat32;
+typedef double                  NCGfloat64;
+
+typedef int                     NCGsizei;
+typedef float                   NCGclampf;
+typedef long                    NCGfixed;
+
+typedef NCGuint32 (*NCGDUISRfp)(NCGbitfield uiDisplay);
+typedef NCGuint32 (*NCGVGISRfp)(void);
+typedef NCGvoid (*NCGfp)(NCGvoid *);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_DEFS_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_memory.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,55 @@
+/******************************************************************************
+* Copyright(c) 2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : Sample code of NCG memory operation functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2013.06.25
+*          - Changed for RGAH
+*          2013.01.08
+*          - Created new code.
+*
+******************************************************************************/
+
+#ifndef NCG_MEMORY_H
+#define NCG_MEMORY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ * Host memory management
+ */
+
+NCGvoid
+NCGSYS_PurgeCPUOperandCache (
+    void
+);
+
+NCGuint32
+NCGSYS_CPUVAddrToSysPAddr (
+    NCGuint32   ui32CPUAddr
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_MEMORY_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_register.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,66 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG register read/write header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*
+*******************************************************************************/
+
+#ifndef NCG_REGISTER_H
+#define NCG_REGISTER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  Register read/write
+ */
+NCGuint32
+NCGSYS_ReadReg (
+    NCGuint32   ui32RegBase,
+    NCGuint32   ui32Offset
+);
+
+NCGvoid
+NCGSYS_WriteReg (
+    NCGuint32   ui32RegBase,
+    NCGuint32   ui32Offset,
+    NCGuint32   ui32Value
+);
+
+NCGuint32
+NCGSYS_ModifyReg (
+    NCGuint32   ui32RegBase,
+    NCGuint32   ui32Offset,
+    NCGuint32   ui32Mask,
+    NCGuint32   ui32Value
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_REGISTER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_state.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,109 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG state variable control functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*
+*******************************************************************************/
+
+#ifndef NCG_STATE_H
+#define NCG_STATE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+/*
+ *  Mode Flags
+ */
+
+#define NCGSYS_STATE_CALL_MASK       (0x00000003U)
+#define NCGSYS_STATE_CALL_NORMAL     (0x00000000U)
+#define NCGSYS_STATE_CALL_INTERRUPT  (0x00000001U)
+#define NCGSYS_STATE_CALL_CALLBACK   (0x00000002U)
+
+#define NCGSYS_STATE_WAIT_MASK       (0x00000004U)
+#define NCGSYS_STATE_WAIT_OR         (0x00000004U)
+#define NCGSYS_STATE_WAIT_AND        (0x00000000U)
+
+#define NCGSYS_STATE_SET_MASK        (0x00000018U)
+#define NCGSYS_STATE_SET_AND         (0x00000000U)
+#define NCGSYS_STATE_SET_OR          (0x00000008U)
+#define NCGSYS_STATE_SET_SET         (0x00000010U)
+
+#define NCGSYS_STATE_OR             NCGSYS_STATE_SET_OR
+#define NCGSYS_STATE_SET            NCGSYS_STATE_SET_SET
+#define NCGSYS_STATE_CLEAR          NCGSYS_STATE_SET_AND
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  State control
+ */
+
+NCGint32
+NCGSYS_CreateState (
+    NCGvoid     **ppObj,
+    NCGuint32   ui32StateID
+);
+
+NCGint32
+NCGSYS_DestroyState (
+    NCGvoid     *pObj
+);
+
+NCGint32
+NCGSYS_SetState (
+    NCGvoid     *pObj,
+    NCGuint32   ui32State,
+    NCGuint32   ui32Flags
+);
+
+NCGuint32
+NCGSYS_GetState (
+    NCGvoid     *pObj,
+    NCGuint32   ui32Flags
+);
+
+NCGint32
+NCGSYS_WaitState (
+    NCGvoid     *pObj,
+    NCGuint32   ui32State,
+    NCGuint32   ui32Flags,
+    NCGuint32   ui32Timeout
+);
+
+NCGvoid
+NCGSYS_SetStateEventValue (
+    NCGvoid    *pObj,
+    NCGuint32   ui32EventValue
+);
+
+NCGvoid *
+NCGSYS_GetLastCreatedState(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_STATE_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_time.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,64 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG time and delay control functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*
+*******************************************************************************/
+
+#ifndef NCG_TIME_H
+#define NCG_TIME_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  Delay control
+ */
+NCGint32
+NCGSYS_Sleep (
+    NCGuint32   ui32MilliSeconds
+);
+
+/*
+ *  Time acquisition
+ */
+
+NCGint32
+NCGSYS_StartTickCount (
+    void
+);
+
+NCGuint32
+NCGSYS_GetTickCount (
+    void
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NCG_TIME_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_vg.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/******************************************************************************
+* Copyright(c) 2010-2013 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : R-GPVG Functions header
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2011.01.12
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*          2013.05.13
+*          - Added function of initialization.
+*          - Added function of finalization.
+*
+*******************************************************************************/
+
+#ifndef NCG_VG_H
+#define NCG_VG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ncg_defs.h"
+/*=============================================================================
+ * Definitions
+ */
+
+/* VGINFO */
+typedef struct VGINFO_TAG {
+    NCGuint32   ui32Flags;
+} NCGVGINFO, * PNCGVGINFO;
+
+/* RGPINFO */
+typedef struct RGPINFO_TAG {
+    NCGuint32   ui32WorkBufferStride;       /* Work Buffer Stride */
+    NCGuint32   ui32WorkBufferHeight;       /* Work Buffer Height */
+    NCGuint32   ui32StreamBuffer0Size;      /* Stream Buffer 0 Size */
+    NCGuint32   ui32StreamBuffer1Size;      /* Stream Buffer 1 Size */
+    NCGuint32   ui32DisplayListBufferSize;  /* Display List Buffer Size */
+} NCGRGPINFO, * PNCGRGPINFO;
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  VG initialization / finalization
+ */
+NCGvoid
+NCGVG_Init (
+    PNCGVGINFO      pVGInfo
+);
+
+NCGvoid
+NCGVG_DeInit (
+    PNCGVGINFO      pVGInfo
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_VG_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/inc/ncg_vg_isr.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,68 @@
+/******************************************************************************
+* Copyright(c) 2010-2013 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG R-GPVG interrupt handling functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*          2013.01.08
+*          - Applied to R-GPVG2 for Aragon.
+*          2013.02.21
+*          - Modified the value of NCGVG_INT_LEVEL.
+*
+*******************************************************************************/
+
+#ifndef NCG_VG_ISR_H
+#define NCG_VG_ISR_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+#define NCGVG_INT0_VECT     (130)
+#define NCGVG_INT1_VECT     (131)
+#define NCGVG_INT2_VECT     (132)
+#define NCGVG_INT3_VECT     (133)
+
+#define NCGVG_INT_LEVEL     (5)               /* interrupt level */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ * VG interrupt handling
+ */
+
+NCGint32
+NCGVG_Attach_ISR (
+    NCGVGISRfp pfnInterrupt
+);
+
+NCGint32
+NCGVG_Detach_ISR (
+    NCGVGISRfp pfnInterrupt
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_VG_ISR_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/src/ncg_memory.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,53 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG memory operation functions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2013.06.25
+*          - Changed for RGAH
+*          2010.10.08
+*          - Created the initial code.
+*          2012.08.23
+*          - Created the initial code.
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include "ncg_defs.h"
+#include "ncg_memory.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_CPUVAddrToSysPAddr
+ FUNCTION   : Get the system physical address of the given host memory block.
+ PARAMETERS : ui32CPUAddr  : [IN ] The address of the host memory area.
+ RETURN     : Phy.
+------------------------------------------------------------------------------*/
+NCGuint32
+NCGSYS_CPUVAddrToSysPAddr (
+    NCGuint32   ui32CPUAddr )
+{
+    NCGuint32   ui32Ret_addr;
+
+    ui32Ret_addr = ui32CPUAddr;
+
+    return ui32Ret_addr;
+}
+
+
+#endif
+/* -- end of file -- */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/src/ncg_register.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,85 @@
+/******************************************************************************
+* Copyright (c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG register read/write Functions
+*
+* author : Renesas Electronics Corporation.
+*
+* history: 2013.06.25
+*          - Changed for RGAH
+*          2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include "ncg_defs.h"
+#include "ncg_register.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_ReadReg
+ FUNCTION   : Read a hardware register.
+ PARAMETERS : ui32RegBase : [IN ] Base address.
+              ui32Offset  : [IN ] Address offset.
+ RETURN     : Register value.
+------------------------------------------------------------------------------*/
+NCGuint32
+NCGSYS_ReadReg (
+    NCGuint32       ui32RegBase,
+    NCGuint32       ui32Offset )
+{
+    NCGuint32 ui32RegVal;
+
+    ui32RegVal = *(((volatile NCGuint32 *)ui32RegBase) + (ui32Offset>>2));
+
+    return ui32RegVal;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_WriteReg
+ FUNCTION   : Write a hardware register.
+ PARAMETERS : ui32RegBase : [IN ] Base address.
+              ui32Offset  : [IN ] Address offset.
+              ui32Value   : [IN ] Register value.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGSYS_WriteReg (
+    NCGuint32       ui32RegBase,
+    NCGuint32       ui32Offset,
+    NCGuint32       ui32Value )
+{
+    *(((volatile NCGuint32 *)ui32RegBase) + (ui32Offset>>2)) = ui32Value;
+}
+
+#endif
+/* -- end of file -- */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/src/ncg_state.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,499 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG State variable control functions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2013.05.20
+*          - Applied to CMSIS-RTOS RTX.
+*          2014.12.10
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+#include "Project_Config.h"
+#include "r_ospl.h"
+
+#include    "ncg_defs.h"
+#include    "ncg_debug.h"
+#include    "ncg_state.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+#define     NCG_MAX_STATE_OBJECTS   (1U)
+#define     NCG_MAX_THREAD_ID       (1U)
+
+struct NCG_STATE_T {
+    r_ospl_thread_id_t  id[NCG_MAX_THREAD_ID];
+    NCGboolean      bInUse;
+    int32_t         flgbit;
+    NCGuint32       ui32State;
+} ;
+
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+
+static NCGint32 ncg_init_states( void ) ;
+static NCGuint32 ncg_state_search( NCGvoid *pObj );
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+
+volatile static struct NCG_STATE_T tStates[NCG_MAX_STATE_OBJECTS];
+
+static NCGboolean ncg_state_initialized = NCG_FALSE ;
+static struct NCG_STATE_T *ncg_last_created_state;
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_CreateState
+ FUNCTION   : Create a state control object.
+ PARAMETERS : ppObj       : [OUT] The pointer to the created state control object.
+              ui32StateID : [IN ] The identifier of the state variable.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_CreateState(
+    NCGvoid         **ppObj,
+    NCGuint32       ui32StateID )
+{
+    struct NCG_STATE_T  *p_state;
+    NCGuint32           state_idx;
+    NCGuint32           thread_idx;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_CreateState" );
+
+    NCG_UNREFERENCED_PARAMETER(ui32StateID);
+
+    if( ppObj == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_CreateState(1) invalid ppObj.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_invalid_handle ;
+    }
+
+    if( ncg_state_initialized == NCG_FALSE ) {
+        ncg_init_states();
+    }
+
+    p_state = NULL;
+    for ( state_idx = 0 ; state_idx < NCG_MAX_STATE_OBJECTS ; state_idx++ ) {
+        if ( tStates[state_idx].bInUse == NCG_FALSE ) {
+            p_state = (struct NCG_STATE_T *)&tStates[state_idx];
+            break ;
+        }
+    }
+    if ( p_state == NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_CreateState(2) Object over flow.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_resource_exceeded ;
+    }
+
+    /* set initial value */
+    for ( thread_idx = 1U ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        p_state->id[thread_idx] = NULL;
+    }
+    p_state->id[0]     = R_OSPL_THREAD_GetCurrentId();    /* [0] is current thread id */
+    p_state->bInUse    = NCG_TRUE ;
+    p_state->ui32State = 0U ;
+
+    *ppObj = ( NCGvoid *)p_state ;
+    ncg_last_created_state = p_state;
+
+    return NCG_no_err ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_DestroyState
+ FUNCTION   : Destroy the given state control object.
+ PARAMETERS : pObj : [IN ] The pointer to the state control object.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_DestroyState(
+    NCGvoid *pObj )
+{
+    volatile struct NCG_STATE_T *p_state;
+    NCGuint32                   state_idx;
+    NCGuint32                   thread_idx;
+    NCGboolean bDestroyFlg ;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_DestroyState" );
+
+    p_state = (struct NCG_STATE_T *)pObj;
+    if( p_state == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_DestroyState(1) Failed: pObj is NULL.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_invalid_handle ;
+    }
+
+    state_idx = ncg_state_search( pObj );
+    if ( state_idx >= NCG_MAX_STATE_OBJECTS ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_DestroyState(2) Failed: pObj is not found.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_not_found ;
+    }
+
+    if( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_DestroyState(3) Failed: pObj is not used.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_bad_parameter ;
+    }
+
+    /* clear status parameters */
+    for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        p_state->id[thread_idx] = NULL;
+    }
+    p_state->bInUse    = NCG_FALSE;
+    p_state->ui32State = 0U;
+
+    bDestroyFlg = NCG_TRUE ;
+    for ( state_idx = 0 ; state_idx < NCG_MAX_STATE_OBJECTS ; state_idx++ ) {
+        if ( tStates[state_idx].bInUse != NCG_FALSE ) {
+            bDestroyFlg = NCG_FALSE ;
+            break ;
+        }
+    }
+    if ( bDestroyFlg != NCG_FALSE ) {
+        ncg_state_initialized = NCG_FALSE ;
+    }
+    return NCG_no_err ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_SetState
+ FUNCTION   : Set the state control object into the given state.
+ PARAMETERS : pObj      : [IN ] The pointer to the state control object.
+              ui32State : [IN ] The state value to set.
+              ui32Flags : [IN ] Flags.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_SetState(
+    NCGvoid         *pObj,
+    NCGuint32       ui32State,
+    NCGuint32       ui32Flags )
+{
+    volatile struct NCG_STATE_T *p_state = (volatile struct NCG_STATE_T *)pObj ;
+
+    NCGuint32                   uiSetMask;
+    NCGuint32                   thread_idx;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_SetState" );
+
+    if( pObj == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(1) Failed:pObj is NULL.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+
+    if ( ncg_state_search( pObj ) >= NCG_MAX_STATE_OBJECTS ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(2) Failed: pObj is not found.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_not_found ;
+    }
+
+    p_state = (volatile struct NCG_STATE_T *)pObj;
+    if ( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(3) Failed: pObj is not used.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_bad_parameter ;
+    }
+
+    uiSetMask = ui32Flags & NCGSYS_STATE_SET_MASK;
+    switch( uiSetMask ) {
+        case NCGSYS_STATE_SET_AND :
+            p_state->ui32State &= ui32State ;
+            break ;
+
+        case NCGSYS_STATE_SET_OR :
+            p_state->ui32State |= ui32State ;
+            break ;
+
+        case NCGSYS_STATE_SET_SET :
+            p_state->ui32State = ui32State ;
+            break ;
+
+        default :
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(5) Failed:ui32Flags (0x%08x).%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( ui32Flags )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+            return NCG_err_bad_parameter ;
+    }
+
+    if ( uiSetMask == NCGSYS_STATE_SET_AND ) {
+        for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+            if ( p_state->id[thread_idx] != NULL ) {
+                r_ospl_thread_id_t  thread = p_state->id[thread_idx];  /* ICCARM Pa082 : volatile's order */
+                R_OSPL_EVENT_Clear( thread, p_state->flgbit );
+            }
+        }
+    } else {
+        for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+            if ( p_state->id[thread_idx] != NULL ) {
+                r_ospl_thread_id_t  thread = p_state->id[thread_idx];  /* ICCARM Pa082 : volatile's order */
+                R_OSPL_EVENT_Set( thread, p_state->flgbit );
+            }
+        }
+    }
+
+    return NCG_no_err ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_GetState
+ FUNCTION   : Get the current state value from the state control object.
+ PARAMETERS : pObj       : [IN ] The pointer to the state control object.
+              ui32Flags  : [IN ] Flags.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGuint32
+NCGSYS_GetState(
+    NCGvoid         *pObj,
+    NCGuint32       ui32Flags )
+{
+    volatile struct NCG_STATE_T *p_state;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_GetState" );
+
+    NCG_UNREFERENCED_PARAMETER(ui32Flags);
+
+    if ( pObj == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_GetState(1) Failed: pObj.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return (NCGuint32)NCG_err_unknown ;
+    }
+
+    if ( ncg_state_search( pObj ) >= NCG_MAX_STATE_OBJECTS ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_GetState(2) Failed: pObj is not found.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return (NCGuint32)NCG_err_not_found ;
+    }
+
+    p_state = (volatile struct NCG_STATE_T *)pObj;
+    if( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_GetState(3) Failed: pObj is not used.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return (NCGuint32)NCG_err_bad_parameter ;
+    }
+    return ( NCGuint32 )p_state->ui32State ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_WaitState
+ FUNCTION   : Wait for the state control object to be in the given state.
+ PARAMETERS : pObj        : [IN ] The pointer to the state control object.
+              ui32State   : [IN ] The state value to wait for.
+              ui32Flags   : [IN ] Flags.
+              ui32Timeout : [IN ] Timeout value in milli seconds.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_WaitState(
+    NCGvoid         *pObj,
+    NCGuint32       ui32State,
+    NCGuint32       ui32Flags,
+    NCGuint32       ui32Timeout )
+{
+    volatile struct NCG_STATE_T     *p_state;
+    NCGuint32                       wait_mode;
+    NCGuint32                       thread_idx;
+    NCGint32                        func_ret;
+    uint32_t                        time_out;
+    errnum_t                        e;
+
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_WaitState" );
+
+    p_state    = (volatile struct NCG_STATE_T *)pObj;
+    wait_mode = (ui32Flags & NCGSYS_STATE_WAIT_MASK);
+
+    if ( p_state == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_WaitState(1) Failed: pObj is NULL.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+    if ( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_WaitState(2) Failed: pObj.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+    if (( ui32Timeout != NCG_TIMEOUT_INFINITE ) && ( ui32Timeout > 0x7fffffffU )) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_WaitState(3) Failed: ui32Timeout.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+
+    if ( ui32Timeout == NCG_TIMEOUT_INFINITE ) {
+        time_out = R_OSPL_INFINITE;
+    } else {
+        time_out = ui32Timeout;
+    }
+
+    for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        if ( p_state->id[thread_idx] == R_OSPL_THREAD_GetCurrentId() ) {
+            break;
+        }
+        if ( p_state->id[thread_idx] == NULL ) {
+            /* add thread ID */
+            p_state->id[thread_idx] = R_OSPL_THREAD_GetCurrentId();
+            break;
+        }
+    }
+
+    while (1) {
+        if ( wait_mode == NCGSYS_STATE_WAIT_OR ) {
+            if ( (p_state->ui32State & ui32State) != 0 ) {
+                func_ret = NCG_no_err;
+                break;
+            }
+        } else {
+            /* wait_mode == NCGSYS_STATE_WAIT_AND */
+            if ( (p_state->ui32State & ui32State) == ui32State ) {
+                func_ret = NCG_no_err;
+                break;
+            }
+        }
+        e = R_OSPL_EVENT_Wait( p_state->flgbit, NULL, time_out );
+        IF ( e != 0 ) {
+            func_ret = NCG_err_unknown;
+            break;
+        }
+    }
+
+    for ( thread_idx = 1 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        p_state->id[thread_idx] = NULL;
+    }
+
+    return func_ret;
+}
+
+
+/*=============================================================================
+ *  Internal functions
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : ncg_init_states
+ FUNCTION   : Initialize global variable in NCG state.
+ PARAMETERS : None.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+static NCGint32
+ncg_init_states( void )
+{
+    NCGuint32   i ;
+    NCGuint32   thread_idx;
+
+    for( i = 0 ; i < NCG_MAX_STATE_OBJECTS ; i++ ) {
+        for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+            tStates[i].id[thread_idx] = NULL;
+        }
+        tStates[i].bInUse    = NCG_FALSE ;
+        tStates[i].flgbit    = (int32_t)(1 << i) ;
+        tStates[ i ].ui32State = 0U ;
+    }
+    ncg_state_initialized = NCG_TRUE ;
+
+    return NCG_no_err;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : ncg_state_search
+ FUNCTION   : Search status object.
+ PARAMETERS : pObj :[IN ] Handle to the status object.
+ RETURN     : Index of the status object.
+------------------------------------------------------------------------------*/
+static NCGuint32 ncg_state_search(
+    NCGvoid     *pObj
+)
+{
+    NCGuint32               state_idx;
+
+    for ( state_idx = 0U ; state_idx < NCG_MAX_STATE_OBJECTS ; state_idx++ ) {
+        if ( pObj == &tStates[state_idx] ) {
+            break;
+        }
+    }
+
+    return state_idx;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_SetStateEventValue
+ FUNCTION   : Set the value of thread attached event.
+ PARAMETERS : pObj           : [IN ] The pointer to the state control object.
+              ui32EventValue : [IN ] The value of thread attached event.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGSYS_SetStateEventValue(
+    NCGvoid         *pObj,
+    NCGuint32       ui32EventValue )
+{
+    volatile struct NCG_STATE_T *p_state = (volatile struct NCG_STATE_T *)pObj ;
+
+    p_state->flgbit = ui32EventValue;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_GetLastCreatedState
+ FUNCTION   : GetLastCreatedState.
+ PARAMETERS : None.
+ RETURN     : LastCreatedState.
+------------------------------------------------------------------------------*/
+NCGvoid *
+NCGSYS_GetLastCreatedState(void)
+{
+    return  (NCGvoid *) ncg_last_created_state;
+}
+
+#endif
+/* -- end of file -- */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/src/ncg_vg.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,161 @@
+/******************************************************************************
+* Copyright(c) 2010-2014 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : R-GPVG control functions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2011.01.20
+*          - Created the initial code.
+*          2012.08.22
+*          - Added return value to "NCGVG_InitResourceSize"
+*          2013.05.13
+*          - Added function of initialization.
+*          - Added function of finalization.
+*          2013.06.10
+*          - Applied to new VDC5 driver (Version 0.03.0046).
+*          2013.11.07
+*          - Modified value of NCG_VG_SBO1_SIZE to (4U) from (0U).
+*          2014.02.13
+*          - Modified the value of definitions.
+*              NCG_VG_WB_STRIDE
+*              NCG_VG_WB_HEIGHT
+*              NCG_VG_SBO0_SIZE
+*              NCG_VG_DLB_SIZE
+*          2014.03.25
+*          - Modified NCGVG_Init() and NCGVG_DeInit().
+*          2014.05.16
+*          - Modified NCGVG_Init() and NCGVG_DeInit().
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include "ncg_defs.h"
+#include "ncg_debug.h"
+#include "r_ospl.h"
+
+#include "ncg_vg.h"
+
+/* Depending on the build environment */
+#include "r_typedefs.h"
+
+#include "iodefine.h"
+#include "iobitmasks/cpg_iobitmask.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+/* TODO:
+    Please change these parameters in accordance with your system.
+ */
+#define NCG_VG_WB_STRIDE    (256U)
+#define NCG_VG_WB_HEIGHT    (480U)
+
+#define NCG_VG_SBO0_SIZE    (16384U)
+#define NCG_VG_SBO1_SIZE    (4U)
+#define NCG_VG_DLB_SIZE     (5120U)
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_Init
+ FUNCTION   : Initialize R-GPVG.
+ PARAMETERS : pVGInfo : [IN ] The pointer to the initialization information struct.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGVG_Init (
+    PNCGVGINFO pVGInfo)
+{
+    /* Depending on the build environment */
+    volatile uint8_t    reg_value;
+
+    NCG_UNREFERENCED_PARAMETER( pVGInfo );
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_Init" );
+
+    reg_value = CPG.STBCR10;
+    if ( CPG.STBCR10 & CPG_STBCR10_MSTP100 ) {
+        /* Standby control register 10 (STBCR10) : 0 : R-GPVG enable */
+        CPG.STBCR10 &= ~CPG_STBCR10_MSTP100;
+        /* dummy read */
+        reg_value = CPG.STBCR10;
+
+        if ( CPG.STBREQ2 & CPG_STBREQ2_STBRQ20 ) {
+            CPG.SWRSTCR3 |=  CPG_SWRSTCR3_SRST32;
+            /* dummy read */
+            reg_value = CPG.SWRSTCR3;
+
+            CPG.SWRSTCR3 &= ~CPG_SWRSTCR3_SRST32;
+            /* dummy read */
+            reg_value = CPG.SWRSTCR3;
+
+            CPG.STBREQ2 &= ~CPG_STBREQ2_STBRQ20;
+            /* dummy read */
+            reg_value = CPG.STBREQ2;
+            while ( (CPG.STBACK2 & CPG_STBACK2_STBAK20) != 0  ) ;
+        }
+    }
+
+    NCG_UNREFERENCED_PARAMETER( reg_value );  /* Avoid warning of "unused-but-set-variable" of GCC_ARM */
+
+    return ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_DeInit
+ FUNCTION   : Finalize R-GPVG.
+ PARAMETERS : pVGInfo : [IN ] The pointer to the finalization information struct.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGVG_DeInit (
+    PNCGVGINFO      pVGInfo )
+{
+    /* Depending on the build environment */
+    volatile uint8_t    reg_value;
+
+    NCG_UNREFERENCED_PARAMETER(pVGInfo);
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_DeInit" );
+
+    if ( (CPG.STBCR10 & CPG_STBCR10_MSTP100) != CPG_STBCR10_MSTP100 ) {
+        CPG.STBREQ2 |= CPG_STBREQ2_STBRQ20;
+        /* dummy read */
+        reg_value = CPG.STBREQ2;
+        while ( (CPG.STBACK2 & CPG_STBACK2_STBAK20) == 0  ) ;
+
+        /* Standby control register 10 (STBCR10) : 0 : R-GPVG disable */
+        CPG.STBCR10 |= CPG_STBCR10_MSTP100;
+        /* dummy read */
+        reg_value = CPG.STBCR10;
+    }
+
+    NCG_UNREFERENCED_PARAMETER( reg_value );  /* Avoid warning of "unused-but-set-variable" of GCC_ARM */
+
+    return ;
+}
+
+#endif
+/* -- end of file -- */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/RGPNCG/src/ncg_vg_isr.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,349 @@
+/******************************************************************************
+* Copyright(c) 2010-2015 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : R-GPVG control functions
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2011.03.07
+*          - Fixed bug : NCGVG_Detach_ISR / [R-GPVG_common_P_033]
+*          2012.08.22
+*          - Moved definition to "ncg_vg_isr.h".
+*            - RGPVG_INT_LEVEL
+*          - Moved definition to "ncg_register.h".
+*            - RTIP_VG_BASE
+*            - VG_REG_VG_ISR
+*          2012.08.22
+*          - Added error message in the debug mode.
+*          - Update all comments
+*          2013.02.21
+*          - Modified the argument of the NCGVG_RGPVG_ISR.
+*          - Modified the call to R_INTC_RegistIntFunc function
+*            by NCGVG_Attach_ISR.
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include    "ncg_defs.h"
+#include    "ncg_debug.h"
+#include    "ncg_vg_isr.h"
+#include    "RGA.h"
+
+/* Depending on the build environment */
+#include    "r_typedefs.h"
+#include    "r_ospl.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+static void NCGVG_RGPVG_ISR(void) ;
+static void NCGVG_RGPVG_ISR_0(void) ;
+static void NCGVG_RGPVG_ISR_1(void) ;
+static void NCGVG_RGPVG_ISR_2(void) ;
+static void NCGVG_RGPVG_ISR_3(void) ;
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+static NCGboolean NCGVG_ISR_Initialized  = NCG_FALSE ;
+static NCGVGISRfp NCGVG_pRGPVG_Interrupt = NCG_NULL ;
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_Attach_ISR
+ FUNCTION   : Attach the function pointer of OpenVG ISR.
+ PARAMETERS : pfnInterrupt : [IN ] The pointer to the function of OpenVG ISR.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGVG_Attach_ISR(
+    NCGVGISRfp      pfnInterrupt )
+{
+    NCGint32        rc_val = NCG_no_err;
+    bsp_int_err_t   eb;
+    errnum_t        e;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_Attach_ISR" );
+
+    NCG_ASSERT(pfnInterrupt != NCG_NULL);
+
+    if( NCGVG_ISR_Initialized != NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_Attach_ISR(1) Initialized.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        rc_val = NCG_err_isr_management_failed ;
+    } else {
+        NCGVG_ISR_Initialized  = NCG_TRUE ;
+        NCGVG_pRGPVG_Interrupt = pfnInterrupt ;
+
+        /* Regist function */
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT0, NCGVG_RGPVG_ISR_0 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT1, NCGVG_RGPVG_ISR_1 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT2, NCGVG_RGPVG_ISR_2 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT3, NCGVG_RGPVG_ISR_3 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+
+        /* set priority */
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT0, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT1, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT2, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT3, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+
+        /* Enable interrupt from Renesas OpenVG library */
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT0, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT1, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT2, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT3, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+    }
+
+fin:
+    return rc_val;
+}
+
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_Detach_ISR
+ FUNCTION   : Detach the function pointer of OpenVG ISR.
+ PARAMETERS : pfnInterrupt : [IN ] The pointer to the function of OpenVG ISR.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGVG_Detach_ISR(
+    NCGVGISRfp      pfnInterrupt )
+{
+    NCGint32        rc_val = NCG_no_err;
+    bsp_int_err_t   eb;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_Detach_ISR" );
+
+    NCG_ASSERT(pfnInterrupt != NCG_NULL);
+
+    if ( NCGVG_ISR_Initialized == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_Detach_ISR(1) Not initialized.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        rc_val = NCG_err_isr_management_failed;
+    } else {
+        NCGVG_ISR_Initialized = NCG_FALSE ;
+
+        if( pfnInterrupt == NCGVG_pRGPVG_Interrupt ) {
+            /* Disable interrupt from Renesas OpenVG library */
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT3, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT2, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT1, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT0, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+
+            /* Unregist function */
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT3, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT2, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT1, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT0, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+
+            NCGVG_pRGPVG_Interrupt = NCG_NULL ;
+        } else {
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_Detach_ISR(2) Miss match function pointer.%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+            rc_val = NCG_err_isr_management_failed;
+        }
+    }
+
+fin:
+    return rc_val;
+}
+
+
+/*=============================================================================
+ *  Internal functions
+ */
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR(void)
+{
+    NCGuint32 ret ;
+    errnum_t  e;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_RGPVG_ISR" );
+
+    if( NCGVG_pRGPVG_Interrupt == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][INFO]NCGVG_RGPVG_ISR Not initialized.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+    } else {
+        ret = NCGVG_pRGPVG_Interrupt() ;
+        if ( ret != 0 ) {
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_RGPVG_ISR(0x%08x)%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( ret )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        }
+
+        e= R_GRAPHICS_OnInterrupting();
+        if ( e != 0 ) {
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_RGPVG_ISR(e=0x%08x)%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( e )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        }
+    }
+
+    return ;
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_0
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_0(void)
+{
+    NCGVG_RGPVG_ISR();
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_1
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_1(void)
+{
+    NCGVG_RGPVG_ISR();
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_2
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_2(void)
+{
+    NCGVG_RGPVG_ISR();
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_3
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_3(void)
+{
+    NCGVG_RGPVG_ISR();
+}
+
+#endif
+/* -- end of file -- */

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_ARM_STD/libPNG_Zip.ar has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_ARM_STD/libRGA.ar has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_ARM_STD/libRGAH.ar has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_GCC_ARM/libPNG_Zip.a has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_GCC_ARM/libRGA.a has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_GCC_ARM/libRGAH.a has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_IAR/libPNG_Zip.a has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_IAR/libRGA.a has changed

Binary file mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/TOOLCHAIN_IAR/libRGAH.a has changed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_API.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,222 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_API.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_API_H
+#define  RGA_API_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_API_typedef.h"
+#include  "frame_buffer_typedef.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* Functions: R_RGA
+************************************************************************/
+bool_t  R_RGA_IsSupportedPixelFormatForRGAH( pixel_format_t pixel_format );
+
+
+/***********************************************************************
+* Class: graphics_image_t
+************************************************************************/
+errnum_t  R_GRAPHICS_IMAGE_InitR8G8B8A8(
+    graphics_image_t *self, void *ImageDataArray, size_t ImageDataArraySize,
+    int_fast32_t width, int_fast32_t height );
+errnum_t  R_GRAPHICS_IMAGE_InitSameSizeR8G8B8A8(
+    graphics_image_t *self, void *ImageDataArray, size_t ImageDataArraySize,
+    graphics_image_t *SameSizeImage );
+errnum_t  R_GRAPHICS_IMAGE_InitCopyFrameBufferR8G8B8A8(
+    graphics_image_t *self, void *ImageDataArray, size_t ImageDataArraySize,
+    graphics_t *Context, int_fast32_t MinX,  int_fast32_t MinY,  int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_IMAGE_InitByShareFrameBuffer( graphics_image_t *self, frame_buffer_t *frame_buffer );
+errnum_t  R_GRAPHICS_IMAGE_GetProperties( const graphics_image_t *self, graphics_image_properties_t *out_Properties );
+errnum_t  R_GRAPHICS_IMAGE_GetImageFormat( const graphics_image_t *self, pixel_format_t *out_Format );
+
+
+/***********************************************************************
+* Class: graphics_pattern_t
+************************************************************************/
+errnum_t  R_GRAPHICS_PATTERN_Initialize( graphics_pattern_t *self,
+        const graphics_image_t *image,  repetition_t repetition,  graphics_t *Context );
+
+
+/***********************************************************************
+* Class: graphics_t
+************************************************************************/
+void      R_GRAPHICS_InitConst( graphics_t *self );
+errnum_t  R_GRAPHICS_Initialize( graphics_t *self, graphics_config_t *Config );
+errnum_t  R_GRAPHICS_Finalize( graphics_t *self, errnum_t e );
+
+errnum_t  R_GRAPHICS_SetFrameBuffer( graphics_t *self, frame_buffer_t *frame_buffer );
+errnum_t  R_GRAPHICS_GetFrameBuffer( graphics_t *self, frame_buffer_t **out_frame_buffer );
+errnum_t  R_GRAPHICS_Finish( graphics_t *self );
+errnum_t  R_GRAPHICS_FinishStart( graphics_t *self, r_ospl_async_t *Async );
+errnum_t  R_GRAPHICS_GetAsyncStatus( graphics_t *self, const graphics_async_status_t **out_Status );
+errnum_t  R_GRAPHICS_OnInterrupting(void);
+
+errnum_t  R_GRAPHICS_Save( graphics_t *self, graphics_status_t *out_Status );
+errnum_t  R_GRAPHICS_Restore( graphics_t *self, graphics_status_t *Status, errnum_t e );
+
+errnum_t  R_GRAPHICS_ResetMatrix( graphics_t *self );
+errnum_t  R_GRAPHICS_SetMatrix_2x3( graphics_t *self,  graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                                    graphics_matrix_float_t kx,  graphics_matrix_float_t sy,  graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+errnum_t  R_GRAPHICS_SetMatrix_3x3( graphics_t *self,  graphics_matrix_float_t *Matrix );
+errnum_t  R_GRAPHICS_GetMatrix_3x3( graphics_t *self,  graphics_matrix_float_t *out_Matrix );
+errnum_t  R_GRAPHICS_TranslateMatrixI( graphics_t *self, int_fast32_t tx, int_fast32_t ty );
+errnum_t  R_GRAPHICS_TranslateMatrix( graphics_t *self, graphics_matrix_float_t tx, graphics_matrix_float_t ty );
+errnum_t  R_GRAPHICS_ScaleMatrix( graphics_t *self, graphics_matrix_float_t sx, graphics_matrix_float_t sy );
+errnum_t  R_GRAPHICS_RotateMatrixDegree( graphics_t *self, graphics_matrix_float_t degree );
+errnum_t  R_GRAPHICS_ShearMatrix( graphics_t *self, graphics_matrix_float_t shx, graphics_matrix_float_t shy );
+errnum_t  R_GRAPHICS_TransformMatrix( graphics_t *self,  graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                                      graphics_matrix_float_t kx,  graphics_matrix_float_t sy,  graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+errnum_t  R_GRAPHICS_MultiplyMatrix( graphics_t *self,  graphics_matrix_float_t *Matrix );
+errnum_t  R_GRAPHICS_GetProjectiveMatrix(
+    graphics_matrix_float_t SourceTopLeftX,           graphics_matrix_float_t SourceTopLeftY,
+    graphics_matrix_float_t SourceTopRightX,          graphics_matrix_float_t SourceTopRightY,
+    graphics_matrix_float_t SourceBottomLeftX,        graphics_matrix_float_t SourceBottomLeftY,
+    graphics_matrix_float_t SourceBottomRightX,       graphics_matrix_float_t SourceBottomRightY,
+    graphics_matrix_float_t DestinationTopLeftX,      graphics_matrix_float_t DestinationTopLeftY,
+    graphics_matrix_float_t DestinationTopRightX,     graphics_matrix_float_t DestinationTopRightY,
+    graphics_matrix_float_t DestinationBottomLeftX,   graphics_matrix_float_t DestinationBottomLeftY,
+    graphics_matrix_float_t DestinationBottomRightX,  graphics_matrix_float_t DestinationBottomRightY,
+    graphics_matrix_float_t *out_Matrix );
+
+errnum_t  R_GRAPHICS_SetBackgroundColor( graphics_t *self, r8g8b8a8_t Color );
+errnum_t  R_GRAPHICS_GetBackgroundColor( graphics_t *self, r8g8b8a8_t *out_Color );
+errnum_t  R_GRAPHICS_GetClearColor( graphics_t *self, r8g8b8a8_t *out_Color );
+errnum_t  R_GRAPHICS_Clear( graphics_t *self,
+                            int_fast32_t MinX, int_fast32_t MinY, int_fast32_t width, int_fast32_t height );
+
+errnum_t  R_GRAPHICS_DrawImage( graphics_t *self,  const graphics_image_t *image,
+                                int_fast32_t MinX,  int_fast32_t MinY );
+errnum_t  R_GRAPHICS_DrawImageResized( graphics_t *self,  const graphics_image_t *image,
+                                       int_fast32_t MinX,  int_fast32_t MinY,  int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_DrawImageChild( graphics_t *self,  const graphics_image_t *image,
+                                     int_fast32_t SourceMinX,        int_fast32_t SourceMinY,
+                                     int_fast32_t SourceWidth,       int_fast32_t SourceHeight,
+                                     int_fast32_t DestinationMinX,   int_fast32_t DestinationMinY,
+                                     int_fast32_t DestinationWidth,  int_fast32_t DestinationHeight );
+
+errnum_t  R_GRAPHICS_FillRect( graphics_t *self,  int_fast32_t MinX,  int_fast32_t MinY,
+                               int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_SetFillColor( graphics_t *self, r8g8b8a8_t Color );
+errnum_t  R_GRAPHICS_SetFillPattern( graphics_t *self, graphics_pattern_t *Pattern );
+
+errnum_t  R_GRAPHICS_StrokeRect( graphics_t *self,  int_fast32_t MinX,  int_fast32_t MinY,
+                                 int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_SetStrokeColor( graphics_t *self, r8g8b8a8_t Color );
+
+errnum_t  R_GRAPHICS_BeginPath( graphics_t *self );
+errnum_t  R_GRAPHICS_Rect( graphics_t *self,  int_t MinX,  int_t MinY,
+                           int_t width,  int_t height );
+errnum_t  R_GRAPHICS_Cilp( graphics_t *self );
+
+errnum_t  R_GRAPHICS_SetGlobalAlpha( graphics_t *self, uint8_t AlphaValue );
+errnum_t  R_GRAPHICS_GetGlobalAlpha( graphics_t *self, uint8_t *out_AlphaValue );
+errnum_t  R_GRAPHICS_SetGlobalCompositeOperation( graphics_t *self,
+        graphics_composite_operation_t CompositeOperation );
+errnum_t  R_GRAPHICS_GetGlobalCompositeOperation( graphics_t *self,
+        graphics_composite_operation_t *out_CompositeOperation );
+
+errnum_t  R_GRAPHICS_SetQualityFlags( graphics_t *self,
+                                      graphics_quality_flags_t Qualities );
+errnum_t  R_GRAPHICS_GetQualityFlags( graphics_t *self,
+                                      graphics_quality_flags_t *out_Qualities );
+
+
+/***********************************************************************
+* Class: graphics_static_t
+************************************************************************/
+graphics_static_t  *get_graphics_static(void);
+errnum_t  R_GRAPHICS_STATIC_GetVersion( uint32_t *out_Version );
+errnum_t  R_GRAPHICS_STATIC_OnInitializeDefault( graphics_t *self, graphics_config_t *in_out_Config,
+        void **out_CalleeDefined );
+errnum_t  R_GRAPHICS_STATIC_OnFinalizeDefault( graphics_t *self, void *CalleeDefined, errnum_t e );
+errnum_t  R_GRAPHICS_STATIC_SetOnInitialize(
+    R_GRAPHICS_OnInitialize_FuncType CallbackFunction );
+errnum_t  R_GRAPHICS_STATIC_SetOnFinalize(
+    R_GRAPHICS_OnFinalize_FuncType CallbackFunction );
+
+
+/***********************************************************************
+* Class: RGA_SHS
+*    Synchronize hardware and software rendering
+************************************************************************/
+errnum_t  R_GRAPHICS_BeginSoftwareRendering( graphics_t *self );
+errnum_t  R_GRAPHICS_BeginSoftwareRendering2( graphics_t *self );
+errnum_t  R_GRAPHICS_BeginSoftwareRenderingA( graphics_t *self, void *Address );
+errnum_t  R_GRAPHICS_EndSoftwareRendering( graphics_t *self );
+errnum_t  R_GRAPHICS_EndRenderingInFin( graphics_t *self, errnum_t e );
+
+
+/***********************************************************************
+* Class: animation_timing_function_t
+************************************************************************/
+errnum_t  R_Get_AnimationTimingFunction( char_t *TimingName,
+        animation_timing_function_t **out_Timing );
+
+float32_t  R_ANIMATION_TIMING_FUNCTION_GetValue( animation_timing_function_t *self,
+        float32_t ClampTime, float32_t ValueOfPreviousKeyFrame, float32_t ValueOfNextKeyFrame );
+
+
+/***********************************************************************
+* Functions: Self_Test_for_Package
+************************************************************************/
+errnum_t  R_RGA_CheckStructSize( size_t SizeOf_GraphicsClass, size_t SizeOf_GraphicsStatusClass,
+                                 size_t Zero );
+
+
+#ifdef  __cplusplus
+}  /* extern "C" */
+#endif
+
+#endif  /* RGA_API_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_API_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,323 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_API_typedef.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_API_TYPEDEF_H
+#define  RGA_API_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_ospl_typedef.h"
+#include  "locking_typedef.h"
+#include  "clib_drivers_typedef.h"
+#include  "frame_buffer_typedef.h"
+#include  "RGA_raw_image_typedef.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   graphics_quality_flag_t
+* @brief  graphics_quality_flag_t
+*/
+typedef enum {
+    /* Set to "ON" */
+    GRAPHICS_RENDERING_QUALITY_ANTIALIASED     = 0x0001,
+    GRAPHICS_IMAGE_QUALITY_ANTIALIASED         = 0x0002,
+
+    /* Set to "OFF" */
+    GRAPHICS_RENDERING_QUALITY_NONANTIALIASED  = GRAPHICS_RENDERING_QUALITY_ANTIALIASED << 16,
+    GRAPHICS_IMAGE_QUALITY_NONANTIALIASED      = GRAPHICS_IMAGE_QUALITY_ANTIALIASED << 16
+}
+        graphics_quality_flag_t;
+
+
+/**
+* @enum   graphics_jpeg_decoder_t
+* @brief  graphics_jpeg_decoder_t
+*/
+typedef enum {
+    GRAPHICS_JPEG_DECODER_NONE = 0,
+    GRAPHICS_JPEG_DECODER_HARD = 1
+} graphics_jpeg_decoder_t;
+
+
+/**
+* @typedef  graphics_quality_flags_t
+* @brief  graphics_quality_flags_t
+*/
+typedef bit_flags_fast32_t /*<graphics_quality_flag_t>*/  graphics_quality_flags_t;
+
+
+/**
+* @struct  graphics_config_t
+* @brief  graphics_config_t
+*/
+typedef struct _GraphicsConfigClass  graphics_config_t;
+struct _GraphicsConfigClass {
+    bit_flags32_t    flags;
+    frame_buffer_t  *frame_buffer;  /* F_GRAPHICS_FRAME_BUFFER */
+
+    /* for RGAH/RGAS hardware renderer */
+    void   *work_buffer_address;         /* F_GRAPHICS_WORK_BUFFER_ADDRESS */
+    size_t  work_buffer_size;            /* F_GRAPHICS_WORK_BUFFER_SIZE */
+    int_fast32_t  max_width_of_frame_buffer;   /* F_GRAPHICS_MAX_WIDTH_OF_FRAME_BUFFER */
+    int_fast32_t  max_height_of_frame_buffer;  /* F_GRAPHICS_MAX_HEIGHT_OF_FRAME_BUFFER */
+
+    /* for any */
+    graphics_quality_flags_t  quality_flags;         /* F_GRAPHICS_QUALITY_FLAGS */
+    r8g8b8a8_t                background_color;      /* F_GRAPHICS_BACK_GROUND_COLOR */
+    bool_t                    is_fast_manual_flush;  /* F_GRAPHICS_IS_FAST_MANUAL_FLUSH */
+
+    /* work buffer B */
+    void   *work_buffer_b_address;       /* F_GRAPHICS_WORK_BUFFER_B_ADDRESS */
+    size_t  work_buffer_b_size;          /* F_GRAPHICS_WORK_BUFFER_B_SIZE */
+
+    /* JPEG */
+    graphics_jpeg_decoder_t  jpeg_decoder;  /* F_GRAPHICS_JPEG_DECODER */
+
+    /* PNG */
+    size_t  work_size_for_libPNG;  /* F_GRAPHICS_WORK_SIZE_FOR_LIBPNG */
+
+    /* Asynchronous call */
+    bit_flags32_t  internal_event_value;  /* F_GRAPHICS_INTERNAL_EVENT_VALUE : 16bit */
+
+    /* Thread safe */
+    BSP_CFG_USER_LOCKING_TYPE  *lock_object;  /* F_GRAPHICS_LOCK_OBJECT */
+
+    /* for RGAS */
+    int_fast32_t  channel_of_DMAC_1;      /* F_GRAPHICS_CHANNEL_OF_DMAC_1 */
+    int_fast32_t  channel_of_DMAC_2;      /* F_GRAPHICS_CHANNEL_OF_DMAC_2 */
+    int_fast32_t  event_value_of_DMAC_1;  /* F_GRAPHICS_EVENT_VALUE_OF_DMAC_1 */
+    int_fast32_t  event_value_of_DMAC_2;  /* F_GRAPHICS_EVENT_VALUE_OF_DMAC_2 */
+};
+enum {
+    F_GRAPHICS_FRAME_BUFFER               = 0x0001,
+    F_GRAPHICS_WORK_BUFFER_ADDRESS        = 0x0002,
+    F_GRAPHICS_WORK_BUFFER_SIZE           = 0x0004,
+    F_GRAPHICS_MAX_HEIGHT_OF_FRAME_BUFFER = 0x0008,
+    F_GRAPHICS_MAX_WIDTH_OF_FRAME_BUFFER  = 0x0080,
+    F_GRAPHICS_QUALITY_FLAGS              = 0x0010,
+    F_GRAPHICS_BACK_GROUND_COLOR          = 0x0020,
+    F_GRAPHICS_IS_FAST_MANUAL_FLUSH       = 0x0040,
+    F_GRAPHICS_WORK_BUFFER_B_ADDRESS      = 0x0100,
+    F_GRAPHICS_WORK_BUFFER_B_SIZE         = 0x0200,
+    F_GRAPHICS_JPEG_DECODER               = 0x1000,
+    F_GRAPHICS_WORK_SIZE_FOR_LIBPNG       = 0x8000,
+    F_GRAPHICS_INTERNAL_EVENT_VALUE       = 0x2000,
+    F_GRAPHICS_LOCK_OBJECT                = 0x4000,
+    F_GRAPHICS_CHANNEL_OF_DMAC_1          = 0x0400,
+    F_GRAPHICS_CHANNEL_OF_DMAC_2          = 0x0800,
+    F_GRAPHICS_EVENT_VALUE_OF_DMAC_1    = 0x040000,
+    F_GRAPHICS_EVENT_VALUE_OF_DMAC_2    = 0x080000
+};
+
+
+/**
+* @typedef  graphics_matrix_float_t
+* @brief  graphics_matrix_float_t
+*/
+typedef  float  graphics_matrix_float_t;
+
+
+/**
+* @struct  graphics_matrix3x3_t
+* @brief  graphics_matrix3x3_t
+*/
+typedef union {
+    graphics_matrix_float_t   xy[3][3];  /* [x][y] */
+    graphics_matrix_float_t   array[9];  /* { sx, shy, w0, shx, sy, w1, tx, ty, w2 } */
+} graphics_matrix3x3_t;
+
+
+/**
+* @struct  graphics_image_properties_t
+* @brief  graphics_image_properties_t
+*/
+#if  IS_SUPPORT_SAME_TYPEDEF  || ! defined( graphics_image_properties_t )
+typedef struct _GraphicsImagePropertiesClass  graphics_image_properties_t;
+#define         graphics_image_properties_t   graphics_image_properties_t
+#endif
+struct _GraphicsImagePropertiesClass {
+    int_fast32_t     width;
+    int_fast32_t     height;
+    uint8_t         *data;    /* NULL, if pixelFormat != PIXEL_FORMAT_R8G8B8A8 */
+    void            *pixels;  /* Same as "data" but not NULL */
+    pixel_format_t   pixelFormat;
+    uint32_t        *CLUT;
+    int_fast32_t     CLUT_count;
+};
+
+
+/**
+* @enum   repetition_t
+* @brief  repetition_t
+*/
+typedef enum st_repetition_t {
+    GRAPHICS_REPEAT = 1
+} repetition_t;
+
+
+/**
+* @struct  graphics_pattern_t
+* @brief  graphics_pattern_t
+*/
+typedef struct st_graphics_pattern_t  graphics_pattern_t;
+struct st_graphics_pattern_t {
+    graphics_image_t *image;
+    repetition_t      repetition;
+};
+
+
+/**
+* @enum   graphics_composite_operation_t
+* @brief  graphics_composite_operation_t
+*/
+typedef enum st_graphics_composite_operation_t {
+    GRAPHICS_SOURCE_OVER = 1,
+    GRAPHICS_DESTINATION_OUT = 7,
+    GRAPHICS_COPY = 0
+} graphics_composite_operation_t;
+
+
+/**
+* @struct  graphics_status_t
+* @brief  graphics_status_t
+*/
+typedef struct st_graphics_status_t  graphics_status_t;
+struct st_graphics_status_t {
+    uint8_t  __Members[0x30];
+};
+
+
+/**
+* @struct  graphics_hard_status_t
+* @brief  graphics_hard_status_t
+*/
+#ifdef  RGAH_VERSION
+typedef struct st_graphics_hard_status_t  graphics_hard_status_t;
+struct st_graphics_hard_status_t {
+    volatile bool_t  IsRenderingCompleted;
+};
+#endif
+
+
+/**
+* @struct  graphics_async_status_t
+* @brief  graphics_async_status_t
+*/
+typedef struct st_graphics_async_status_t  graphics_async_status_t;
+struct st_graphics_async_status_t {
+    volatile r_ospl_async_state_t  State;
+    r_ospl_async_t *volatile       Async;
+    BSP_CFG_USER_LOCKING_TYPE     *CLock;
+    r_ospl_thread_id_t             LockedThread;
+#ifdef  RGAH_VERSION
+    const graphics_hard_status_t  *Hardware;
+#endif
+};
+
+
+/**
+* @struct  graphics_t
+* @brief  graphics_t
+*/
+#if  IS_SUPPORT_SAME_TYPEDEF  || ! defined( graphics_t )
+typedef struct st_graphics_t  graphics_t;
+#endif
+struct st_graphics_t {
+    uint8_t  __Members[0x118];
+};
+
+
+/**
+* @brief   R_GRAPHICS_OnInitialize_FuncType
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+typedef  errnum_t  (*R_GRAPHICS_OnInitialize_FuncType)(
+    graphics_t *self, graphics_config_t *in_out_Config, void **out_CalleeDefined );
+
+/**
+* @brief   R_GRAPHICS_OnFinalize_FuncType
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+typedef  errnum_t  (*R_GRAPHICS_OnFinalize_FuncType)(
+    graphics_t *self, void *CalleeDefined, errnum_t e );
+
+
+/**
+* @struct  graphics_static_t
+* @brief  graphics_static_t
+*/
+typedef struct st_graphics_static_t  graphics_static_t;
+struct st_graphics_static_t {
+    R_GRAPHICS_OnInitialize_FuncType  OnInitialize;
+    R_GRAPHICS_OnFinalize_FuncType    OnFinalize;
+    graphics_t                       *Contexts[1];
+};
+
+
+/**
+* @struct  animation_timing_function_t
+* @brief  animation_timing_function_t
+*/
+typedef struct _CSS_animation_timing_function_Class  animation_timing_function_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+#ifdef  __cplusplus
+}  /* extern "C" */
+#endif
+
+#endif  /* RGA_API_TYPEDEF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_Config.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,154 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Config.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+
+/* This file is included from "Project_Config.h" */
+
+
+#ifndef  RGA_CONFIG_H
+#define  RGA_CONFIG_H
+
+
+/**
+* @def  RGA_VERSION
+* @brief  RGA_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  RGA_VERSION  120
+
+
+/**
+* @def  RGA_VERSION_STRING
+* @brief  RGA_VERSION_STRING
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  RGA_VERSION_STRING  "1.20"
+
+
+/**
+* @def  GSCE_VERSION
+* @brief  GSCE_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  GSCE_VERSION  402
+
+
+/**
+* @def  RGAH_VERSION
+* @brief  RGAH_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+/**
+* @def  RGAS_VERSION
+* @brief  RGAS_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+
+#ifdef R_ARM
+#define  IS_RGAH_ARM_VERSION
+/* #define  IS_RGAS_ARM_VERSION */
+#endif
+
+#ifdef _SH
+#define  IS_RGAH_SH_VERSION
+/* #define  IS_RGAS_SH_VERSION */
+#endif
+
+#ifdef _MSC_VER
+/* #define  IS_RGAH_PC_VERSION */
+#define  IS_RGAS_PC_VERSION
+#endif
+
+#if defined( IS_RGAH_ARM_VERSION ) || defined( IS_RGAH_SH_VERSION ) || defined( IS_RGAH_PC_VERSION )
+#define  RGAH_VERSION  103
+#endif
+
+#if defined( IS_RGAS_ARM_VERSION ) || defined( IS_RGAS_SH_VERSION ) || defined( IS_RGAS_PC_VERSION )
+#define  RGAS_VERSION  203
+#endif
+
+#undef  IS_RGAS_ARM_VERSION
+#undef  IS_RGAH_ARM_VERSION
+#undef  IS_RGAS_SH_VERSION
+#undef  IS_RGAH_SH_VERSION
+#undef  IS_RGAS_PC_VERSION
+#undef  IS_RGAH_PC_VERSION
+/* Use "R_ARM" or "RGAH_VERSION" */
+
+
+/**
+* @def  IS_WINDOW_SURFACES_EX
+* @brief  define or not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_WINDOW_SURFACES_EX
+
+
+/***********************************************************************
+* Macros: RGA_LIMITATION_*
+*    0 or 1
+************************************************************************/
+#ifdef  RGAH_VERSION
+#define  RGA_LIMITATION_01_MATRIXED_IMAGE_STRIDE  1
+#define  RGA_LIMITATION_02_XRGB8888_BLEND         0
+#define  RGA_LIMITATION_03_INIT_BMP               1
+#define  RGA_LIMITATION_04_AYNCHRONOOUS_JCU       1
+#define  RGA_LIMITATION_06_COLOR_LITTLE_ERROR     1
+#define  RGA_LIMITATION_07_DRAWIMAGE_VERTEX_ERR   1
+#define  RGA_LIMITATION_08_OPTIMIZATION_ERR       0
+#define  RGA_LIMITATION_09_RGAH_BITBLT_CLIP       1
+#define  RGA_LIMITATION_11_SOURCE_FLUSH_B         0
+#else
+#define  RGA_LIMITATION_01_MATRIXED_IMAGE_STRIDE  0
+#define  RGA_LIMITATION_02_XRGB8888_BLEND         0
+#define  RGA_LIMITATION_03_INIT_BMP               0
+#define  RGA_LIMITATION_04_AYNCHRONOOUS_JCU       1
+#define  RGA_LIMITATION_06_COLOR_LITTLE_ERROR     0
+#define  RGA_LIMITATION_07_DRAWIMAGE_VERTEX_ERR   1
+#define  RGA_LIMITATION_08_OPTIMIZATION_ERR       0
+#define  RGA_LIMITATION_09_RGAH_BITBLT_CLIP       0
+#define  RGA_LIMITATION_11_SOURCE_FLUSH_B         0
+#endif
+
+
+#endif  /* __RGA_CONFIG_H */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_Cpp.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,516 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Cpp.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_CPP_H
+#define  RGA_CPP_H
+
+#ifndef __cplusplus
+#error C++ only
+#endif
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+typedef float  graphics_matrix_float_t;
+typedef double graphics_matrix_other_float_t;
+
+
+/***********************************************************************
+* Class: ObjectHandleClass
+************************************************************************/
+class  ObjectHandleClass
+{
+public:
+    void  *Entity;
+
+    ObjectHandleClass() {
+        this->Entity = NULL;
+    }
+};
+
+bool_t  operator == ( ObjectHandleClass Left, ObjectHandleClass Right );
+
+
+/** undefined */
+#define  undefined  get_undefined()
+extern ObjectHandleClass  get_undefined();
+
+
+/***********************************************************************
+* Class: saveList_st
+************************************************************************/
+struct saveList_st {
+    saveList_st       *beforePoint;
+    graphics_status_t  saveData;
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ImageEntityClass
+************************************************************************/
+class Canvas2D_ImageEntityClass
+{
+public:
+    graphics_image_t  *C_Image;
+    bool_t               isImageDataComposition;
+
+    Canvas2D_ImageEntityClass( bool_t composition ) {
+        this->C_Image = NULL;
+        this->isImageDataComposition = composition;
+    }
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ImageClass
+************************************************************************/
+class  Canvas2D_ImageClass
+{
+public:
+    Canvas2D_ImageEntityClass  *Entity;
+
+    Canvas2D_ImageClass() {
+        this->Entity = NULL;
+    }
+
+    operator ObjectHandleClass () {
+        return  *(ObjectHandleClass *) this;
+    }
+
+    Canvas2D_ImageClass &operator = ( ObjectHandleClass Right ) {
+        this->Entity = (Canvas2D_ImageEntityClass *) Right.Entity;
+        return  *this;
+    }
+
+
+    void  set_imageClass( graphics_image_t *imageClass );
+    inline void  operator= ( graphics_image_t *imageClass ) {
+        this->set_imageClass( imageClass );
+    }
+
+    inline operator graphics_image_t *() {
+        return  this->Entity->C_Image;
+    }
+
+
+    void destroy();
+
+
+    /* "width" property */
+    class  widthProperty
+    {
+    public:
+        inline operator int_t() {
+            graphics_image_properties_t  prop;
+            errnum_t e;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, width ) );
+            e = R_GRAPHICS_IMAGE_GetProperties( parent->Entity->C_Image, &prop );
+            if( e ) {
+                R_OSPL_SetErrNum( e );
+                prop.width = 0;
+            }
+            return  prop.width;
+        }
+    } width;
+
+    /* "height" property */
+    class  heightProperty
+    {
+    public:
+        inline operator int_t() {
+            graphics_image_properties_t  prop;
+            errnum_t e;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, height ) );
+            e = R_GRAPHICS_IMAGE_GetProperties( parent->Entity->C_Image, &prop );
+            if( e ) {
+                R_OSPL_SetErrNum( e );
+                prop.height = 0;
+            }
+            return  prop.height;
+        }
+    } height;
+
+    /* "data" property */
+    class  dataProperty
+    {
+    public:
+        inline operator uint8_t *() {
+            graphics_image_properties_t  prop;
+            errnum_t e;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, data ) );
+            e = R_GRAPHICS_IMAGE_GetProperties( parent->Entity->C_Image, &prop );
+            if( e ) {
+                R_OSPL_SetErrNum( e );
+                prop.data = NULL;
+            }
+            return  prop.data;
+        }
+
+        inline operator r8g8b8a8_t *() {
+            return  (r8g8b8a8_t *)(uint8_t *) *this;
+        }
+
+        inline operator void *() {
+            return  (void *)(uint8_t *) *this;
+        }
+
+        inline uint8_t  &operator[]( int Index ) {
+            return  ( (uint8_t *) *this )[ Index ];
+        }
+
+        inline uint8_t  *operator+( int Index ) {
+            return  ( (uint8_t *) *this ) + Index;
+        }
+    } data;
+
+    /* "src" property */
+    class  srcProperty
+    {
+    public:
+        inline void  operator= ( const graphics_image_t *imageClass ) {
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, src ) );
+
+            parent->set_imageClass( (graphics_image_t *)imageClass );
+        }
+        inline operator graphics_image_t *() {
+            graphics_image_t *outData = NULL;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, src ) );
+
+            if( parent->Entity != NULL ) {
+                outData = parent->Entity->C_Image;
+            }
+            return outData;
+        }
+    } src;
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_PatternClass
+************************************************************************/
+class  Canvas2D_PatternClass
+{
+public:
+    graphics_pattern_t  *Entity;
+
+    Canvas2D_PatternClass() {
+        this->Entity = NULL;
+    }
+
+    operator ObjectHandleClass () {
+        return  *(ObjectHandleClass *) this;
+    }
+
+    Canvas2D_PatternClass &operator = ( ObjectHandleClass Right ) {
+        this->Entity = (graphics_pattern_t *) Right.Entity;
+        return  *this;
+    }
+
+    void destroy();
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ContextEntityClass
+************************************************************************/
+class Canvas2D_ContextEntityClass
+{
+public:
+    graphics_t  *C_Graphics;
+    saveList_st    *LastSavePoint;
+
+    Canvas2D_ContextEntityClass() {
+        this->C_Graphics = NULL;
+        this->LastSavePoint = NULL;
+    }
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ContextClass
+************************************************************************/
+class  Canvas2D_ContextClass
+{
+public:
+    Canvas2D_ContextEntityClass  *Entity;
+
+    Canvas2D_ContextClass() {
+        this->Entity = NULL;
+    }
+
+    operator ObjectHandleClass () {
+        return  *(ObjectHandleClass *) this;
+    }
+
+    Canvas2D_ContextClass &operator = ( ObjectHandleClass Right ) {
+        this->Entity = (Canvas2D_ContextEntityClass *) Right.Entity;
+        return  *this;
+    }
+
+    void  destroy();
+    void  clearRect( int x, int y, int w, int h );
+    void  save();
+    void  restore();
+    void  drawImage( const graphics_image_t *image, int_t minX, int_t minY );
+    void  drawImage( const graphics_image_t *image, int_t minX, int_t minY , int_t width, int_t height );
+    void  drawImage( const graphics_image_t *image, int_t srcMinX,  int_t srcMinY,  int_t srcWidth,   int_t srcHeight,
+                     int_t destMinx, int_t destMinY, int_t destWidth , int_t destHeight );
+    Canvas2D_ImageClass  createImageData( Canvas2D_ImageClass image );
+    Canvas2D_ImageClass  createImageData( int_t width, int_t height );
+    Canvas2D_ImageClass  getImageData( int_t minX, int_t minY, int_t width, int_t height );
+    void  putImageData( Canvas2D_ImageClass imageData, int_t minX, int_t minY );
+    void  putImageData ( Canvas2D_ImageClass imageData, int_t minX, int_t minY, int_t dirtyX, int_t dirtyY, int_t dirtyWidth, int_t dirtyHeight );
+    void  fillRect( int x, int y, int w, int h );
+    Canvas2D_PatternClass  createPattern( const graphics_image_t *image, const char *repetition );
+    void  beginPath();
+    void  rect( int_t minX, int_t minY, int_t width, int_t height );
+    void  clip();
+
+    void  setTransform( graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                        graphics_matrix_float_t kx,  graphics_matrix_float_t sy,
+                        graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+    void  setTransform( graphics_matrix_other_float_t sx,  graphics_matrix_other_float_t ky,
+                        graphics_matrix_other_float_t kx,  graphics_matrix_other_float_t sy,
+                        graphics_matrix_other_float_t tx,  graphics_matrix_other_float_t ty ) {
+        setTransform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                      (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                      (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+    void  setTransform( int_t sx,  int_t ky, int_t kx,  int_t sy, int_t tx,  int_t ty ) {
+        setTransform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                      (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                      (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+
+    void  translate( graphics_matrix_float_t tx, graphics_matrix_float_t ty );
+    void  translate( graphics_matrix_other_float_t tx, graphics_matrix_other_float_t ty ) {
+        translate( (graphics_matrix_float_t) tx, (graphics_matrix_float_t) ty );
+    }
+    void  translate( graphics_matrix_float_t tx, graphics_matrix_other_float_t ty ) {
+        translate( tx, (graphics_matrix_float_t) ty );
+    }
+    void  translate( graphics_matrix_other_float_t tx, graphics_matrix_float_t ty ) {
+        translate( (graphics_matrix_float_t) tx, ty );
+    }
+    void  translate( int_t tx, int_t ty ) {
+        translate( (graphics_matrix_float_t) tx, (graphics_matrix_float_t) ty );
+    }
+
+    void  scale( graphics_matrix_float_t sx, graphics_matrix_float_t sy );
+    void  scale( graphics_matrix_other_float_t sx, graphics_matrix_other_float_t sy ) {
+        scale( (graphics_matrix_float_t) sx, (graphics_matrix_float_t) sy );
+    }
+    void  scale( graphics_matrix_float_t sx, graphics_matrix_other_float_t sy ) {
+        scale( sx, (graphics_matrix_float_t) sy );
+    }
+    void  scale( graphics_matrix_other_float_t sx, graphics_matrix_float_t sy ) {
+        scale( (graphics_matrix_float_t) sx, sy );
+    }
+    void  scale( int_t sx, int_t sy ) {
+        scale( (graphics_matrix_float_t) sx, (graphics_matrix_float_t) sy );
+    }
+
+    void  rotate( graphics_matrix_float_t angle );
+    void  rotate( graphics_matrix_other_float_t angle ) {
+        rotate( (graphics_matrix_float_t) angle );
+    }
+
+    void  transform( graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                     graphics_matrix_float_t kx,  graphics_matrix_float_t sy,
+                     graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+    void  transform( graphics_matrix_other_float_t sx,  graphics_matrix_other_float_t ky,
+                     graphics_matrix_other_float_t kx,  graphics_matrix_other_float_t sy,
+                     graphics_matrix_other_float_t tx,  graphics_matrix_other_float_t ty ) {
+        transform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                   (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                   (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+    void  transform( int_t sx,  int_t ky,  int_t kx,  int_t sy,  int_t tx,  int_t ty ) {
+        transform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                   (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                   (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+
+
+    /* "fillStyle" property */
+    void  Set_fillStyle( const char *Color );
+    void  Set_fillStyle( r8g8b8a8_t Color );
+    void  Set_fillStylePattern( const Canvas2D_PatternClass Pattern );
+#if 0
+    void  Set_fillStyleGradient( const Canvas2D_GradientClass Gradient );
+#endif
+    class  fillStyleProperty
+    {
+    public:
+        inline void  operator= ( const char *Color ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStyle( Color );
+        }
+        inline void  operator= ( r8g8b8a8_t Color ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStyle( Color );
+        }
+        inline void  operator= ( const Canvas2D_PatternClass Pattern ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStylePattern( Pattern );
+        }
+#if 0
+        inline void  operator= ( const Canvas2D_GradientClass Gradient ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStyleGradient( Gradient );
+        }
+#endif
+    } fillStyle;
+
+
+    /* "c_LanguageContext" property */
+    class  c_LanguageContextProperty
+    {
+        inline graphics_t  *get_c_LanguageContext() {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, c_LanguageContext ) );
+
+            return  parent->Entity->C_Graphics;
+        }
+    public:
+
+        inline operator graphics_t *() {
+            return  get_c_LanguageContext();
+        }
+        inline graphics_t *operator->() {
+            return  get_c_LanguageContext();
+        }
+    } c_LanguageContext;
+
+
+    /* "globalAlpha" property */
+    void set_globalAlpha( const float32_t alpha );
+    float32_t get_globalAlpha();
+    class  globalAlphaProperty
+    {
+    public:
+        inline void  operator= ( const float32_t alpha ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalAlpha ) );
+
+            parent->set_globalAlpha( alpha );
+        }
+        inline void  operator= ( const float64_t alpha ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalAlpha ) );
+
+            parent->set_globalAlpha( (float32_t) alpha );
+        }
+        inline operator float32_t() {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalAlpha ) );
+
+            return parent->get_globalAlpha();
+        }
+    } globalAlpha;
+
+
+    /* "globalCompositeOperation" property */
+    void set_globalCompositeOperation( const char *operation );
+    char *get_globalCompositeOperation();
+    class  globalCompositeOperationProperty
+    {
+    public:
+        inline void  operator= ( const char *operation ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalCompositeOperation ) );
+
+            parent->set_globalCompositeOperation( operation );
+        }
+        inline operator char *() {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalCompositeOperation ) );
+
+            return parent->get_globalCompositeOperation();
+        }
+    } globalCompositeOperation;
+
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ContextConfigClass
+************************************************************************/
+struct  Canvas2D_ContextConfigClass {
+    frame_buffer_t  *frame_buffer;
+    bool_t           is_fast_manual_flush;
+
+    Canvas2D_ContextConfigClass() {
+        frame_buffer = NULL;
+        is_fast_manual_flush = false;
+    }
+};
+
+
+/***********************************************************************
+* Functions: Canvas2D_Constructers
+************************************************************************/
+Canvas2D_ContextClass  R_RGA_New_Canvas2D_ContextClass( frame_buffer_t *frame_buffer );
+Canvas2D_ContextClass  R_RGA_New_Canvas2D_ContextClass( Canvas2D_ContextConfigClass &in_out_Config );
+Canvas2D_ImageClass  R_RGA_New_Canvas2D_ImageClass();
+
+#endif  // RGA_CPP_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_Port.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,134 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: RGA_Port.h $
+* $Module: RGA $ $PublicVersion: 1.03 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+* Description:
+******************************************************************************/
+
+#ifndef  RGA_PORT_H
+#define  RGA_PORT_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_API_typedef.h"
+#include  "RGA_Port_typedef.h"
+#include  "clib_drivers_typedef.h"  /* "R_CEIL_8U" in "R_RGA_CalcWorkBufferSize" */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+errnum_t  drawCLUTImage( uint8_t *SrcAddress, const graphics_image_t *image, frame_buffer_t *frame );
+
+
+/***********************************************************************
+* Class: vram_ex_stack_t
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Initialize( vram_ex_stack_t *self, void *NullConfig );
+errnum_t  R_VRAM_EX_STACK_Alloc( vram_ex_stack_t *self, frame_buffer_t *in_out_FrameBuffer );
+errnum_t  R_VRAM_EX_STACK_Free( vram_ex_stack_t *self, frame_buffer_t *frame_buffer );
+
+
+/* Section: Global */
+/**
+* @brief   Calculate size of hardware work buffer
+*
+* @param   max_height_of_frame_buffer int
+* @return  size of hardware work buffer
+*/
+#ifdef  RGAH_VERSION
+
+#define  R_RGA_CalcWorkBufferSize( max_height_of_frame_buffer ) \
+	( (size_t)( RGA_WORK_BUFFER_MAX_DISPLAY_LIST + \
+		RGA_WORK_BUFFER_STRIDE * R_CEIL_8U( max_height_of_frame_buffer ) * 4 * 2 ) )
+R_STATIC_ASSERT_GLOBAL( RGA_WORK_BUFFER_HEIGHT_ALIGNMENT == 8, "" );  /* check of R_CEIL_8U */
+
+#endif
+
+
+/**
+* @brief   Calculate size of hardware work buffer
+*
+* @param   max_width_of_frame_buffer int
+* @param   max_height_of_frame_buffer int
+* @return  size of hardware work buffer
+*/
+#ifdef  RGAH_VERSION
+
+#define  R_RGA_CalcWorkBufferSize2( max_width_of_frame_buffer, max_height_of_frame_buffer ) \
+	R_RGA_CalcWorkBufferSize( max_height_of_frame_buffer )
+#else
+
+#define  R_RGA_CalcWorkBufferSize2( max_width_of_frame_buffer, max_height_of_frame_buffer ) \
+	( (size_t)( (max_width_of_frame_buffer) * RGA_WORK_BUFFER_DMAC_LM_WIDTH_BYTE + \
+		(max_height_of_frame_buffer) * RGA_WORK_BUFFER_DMAC_LM_HEIGHT_BYTE ) )
+#endif
+
+
+/**
+* @brief   Calculate size of hardware work buffer B
+*
+* @param   MaxWidthOfJPEG int
+* @param   MaxHeightOfJPEG int
+* @param   MaxBytePerPixelOfFrameBuffer int
+* @return  size of hardware work buffer B
+*/
+#define  R_RGA_CalcWorkBufferB_Size( MaxWidthOfJPEG, MaxHeightOfJPEG, MaxBytePerPixelOfFrameBuffer ) \
+	( R_CEIL_16U( MaxWidthOfJPEG ) * R_CEIL_16U( MaxHeightOfJPEG ) * (MaxBytePerPixelOfFrameBuffer) )
+R_STATIC_ASSERT_GLOBAL( RGA_JPEG_MAX_WIDTH_ALIGNMENT  == 16, "" );  /* check of R_CEIL_16U */
+R_STATIC_ASSERT_GLOBAL( RGA_JPEG_MAX_HEIGHT_ALIGNMENT == 16, "" );  /* check of R_CEIL_16U */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+/* Inline Functions */
+#include  "RGA_Port_inline.h"
+
+#endif  /* RGA_PORT_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_Port_inline.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,445 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: RGA_Port_inline.h $
+* $Module: RGA $ $PublicVersion: 1.03 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+* Description:
+******************************************************************************/
+
+
+/* This file is included from "RGA_Port.h" */
+
+
+#ifndef  RGA_PORT_INLINE_H
+#define  RGA_PORT_INLINE_H
+#ifndef  NOT_DEFINE_INLINE_FUNCTION
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "clib_drivers.h"
+#include  "frame_buffer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   SwapEndian to 2Byte
+*
+* @param   in_out_2byteVariable Address to 2 byte
+* @return  None
+*/
+INLINE void  SwapEndian2Byte( void *in_out_2byteVariable )
+{
+    byte_t   buffer[2];
+    byte_t  *data = (byte_t *) in_out_2byteVariable;
+
+    buffer[0] = data[0];
+    buffer[1] = data[1];
+
+    data[0] = buffer[1];
+    data[1] = buffer[0];
+}
+
+
+/**
+* @brief   SwapEndian to 4Byte
+*
+* @param   in_out_2byteVariable Address to 4 byte
+* @return  None
+*/
+INLINE void  SwapEndian4Byte( void *in_out_4byteVariable )
+{
+    byte_t   buffer[4];
+    byte_t  *data = (byte_t *) in_out_4byteVariable;
+
+    buffer[0] = data[0];
+    buffer[1] = data[1];
+    buffer[2] = data[2];
+    buffer[3] = data[3];
+
+    data[0] = buffer[3];
+    data[1] = buffer[2];
+    data[2] = buffer[1];
+    data[3] = buffer[0];
+}
+
+
+/**
+* @brief   Sets the value to the address not aligned 4byte
+*
+* @param   out_Variable <uint32_not_aligned_t>
+* @param   Value Set value
+* @return  None
+*/
+INLINE void  uint32_not_aligned_t_set( uint32_not_aligned_t *out_Variable,  uint32_t Value )
+{
+#if BYTE_ENDIAN == BYTE_LITTLE_ENDIAN
+    out_Variable->byte[0] = (byte_t)( ( Value & 0x000000FF ) );
+    out_Variable->byte[1] = (byte_t)( ( Value & 0x0000FF00 ) >>  8 );
+    out_Variable->byte[2] = (byte_t)( ( Value & 0x00FF0000 ) >> 16 );
+    out_Variable->byte[3] = (byte_t)( ( Value & 0xFF000000 ) >> 24 );
+#else
+    out_Variable->byte[0] = (byte_t)( ( Value & 0xFF000000 ) >> 24 );
+    out_Variable->byte[1] = (byte_t)( ( Value & 0x00FF0000 ) >> 16 );
+    out_Variable->byte[2] = (byte_t)( ( Value & 0x0000FF00 ) >>  8 );
+    out_Variable->byte[3] = (byte_t)( ( Value & 0x000000FF ) );
+#endif
+}
+
+
+/***********************************************************************
+* Class: byte_per_pixel_t
+************************************************************************/
+
+
+/**
+* @brief   R_RGA_BitPerPixelType_To_BytePerPixelType
+*
+* @param   BitPerPixel Input
+* @return  byte_per_pixel_t
+*/
+INLINE byte_per_pixel_t  R_RGA_BitPerPixelType_To_BytePerPixelType( int_fast32_t BitPerPixel )
+{
+    if ( R_Mod_8s( BitPerPixel ) == 0 )  {
+        return  (byte_per_pixel_t)( (uint_fast32_t) BitPerPixel / 8 );
+    } else                                 {
+        return  BitPerPixel << R_BYTE_PER_PIXEL_SHIFT;
+    }
+}
+
+
+/**
+* @brief   R_RGA_BytePerPixelType_To_BitPerPixelType
+*
+* @param   BytePerPixel byte_per_pixel_t
+* @return  BitPerPixel
+*/
+INLINE int_fast32_t  R_RGA_BytePerPixelType_To_BitPerPixelType( byte_per_pixel_t  BytePerPixel )
+{
+    return  ( ( BytePerPixel & R_BYTE_PER_PIXEL_MASK ) * 8 ) |
+            ( BytePerPixel >> R_BYTE_PER_PIXEL_SHIFT );
+}
+
+
+/**
+* @brief   R_BYTE_PER_PIXEL_IsInteger
+*
+* @param   BytePerPixel byte_per_pixel_t
+* @return  Whether "BytePerPixel" is integer type.
+*/
+INLINE bool_t  R_BYTE_PER_PIXEL_IsInteger( byte_per_pixel_t BytePerPixel )
+{
+    return  ( BytePerPixel & R_BYTE_PER_PIXEL_MASK ) != 0;
+}
+
+
+/* Section: Global */
+/**
+* @brief   argb8888_t_to_rgb565_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  rgb565_t  argb8888_t_to_rgb565_t( argb8888_t Color )
+{
+    rgb565_t  ret = {0};
+    /* Warning: C4017W: ret may be used before being set */
+    /* This warning is not correct */
+
+    ret.Value = (uint16_t)(
+                    ( ( Color.Value & 0x00F80000 ) >> 8 ) |
+                    ( ( Color.Value & 0x0000FC00 ) >> 5 ) |
+                    ( ( Color.Value & 0x000000F8 ) >> 3 ) );
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb8888_t_to_argb1555_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb1555_t  argb8888_t_to_argb1555_t( argb8888_t Color )
+{
+    argb1555_t  ret = {0};
+    /* Warning: C4017W: ret may be used before being set */
+    /* This warning is not correct */
+
+    ret.Value = (uint16_t)(
+                    ( ( Color.Value & 0x80000000 ) >> 16 ) |  /* A */
+                    ( ( Color.Value & 0x00F80000 ) >>  9 ) |  /* R */
+                    ( ( Color.Value & 0x0000F800 ) >>  6 ) |  /* G */
+                    ( ( Color.Value & 0x000000F8 ) >>  3 ) ); /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb8888_t_to_argb4444_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb4444_t  argb8888_t_to_argb4444_t( argb8888_t Color )
+{
+    argb4444_t  ret = {0};
+    /* Warning: C4017W: ret may be used before being set */
+    /* This warning is not correct */
+
+    ret.Value = (uint16_t)(
+                    ( ( Color.Value & 0xF0000000 ) >> 16 ) |
+                    ( ( Color.Value & 0x00F00000 ) >> 12 ) |
+                    ( ( Color.Value & 0x0000F000 ) >>  8 ) |
+                    ( ( Color.Value & 0x000000F0 ) >>  4 ) );
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb8888_t_to_r8g8b8a8_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  r8g8b8a8_t  argb8888_t_to_r8g8b8a8_t( argb8888_t Color )
+{
+    r8g8b8a8_t  ret;
+    ret.Value = 0;  /* Avoid Warning: C4017W: ret may be used before being set */
+
+    ret.u.Red   = Color.u.Red;
+    ret.u.Green = Color.u.Green;
+    ret.u.Blue  = Color.u.Blue;
+    ret.u.Alpha = Color.u.Alpha;
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgb565_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  rgb565_t_to_argb8888_t( rgb565_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value = 0xFF000000 | /* A */
+                ( ( Color.Value & 0xF800 ) << 8 ) | ( ( Color.Value & 0xE000 ) << 3 ) |  /* R */
+                ( ( Color.Value & 0x07E0 ) << 5 ) | ( ( Color.Value & 0x0600 ) >> 1 ) |  /* G */
+                ( ( Color.Value & 0x001F ) << 3 ) | ( ( Color.Value & 0x001C ) >> 2 );   /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb1555_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  argb1555_t_to_argb8888_t( argb1555_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value =
+        ( ( Color.Value & 0x7C00 ) << 9 ) | ( ( Color.Value & 0x7000 ) << 4 ) |  /* R */
+        ( ( Color.Value & 0x03E0 ) << 6 ) | ( ( Color.Value & 0x0380 ) << 1 ) |  /* G */
+        ( ( Color.Value & 0x001F ) << 3 ) | ( ( Color.Value & 0x001C ) >> 2 );   /* B */
+
+    if ( Color.u.Alpha ) {
+        ret.Value |= 0xFF000000;    /* A */
+    }
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb4444_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  argb4444_t_to_argb8888_t( argb4444_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value =
+        ( ( Color.Value & 0xF000 ) << 16 ) | ( ( Color.Value & 0xF000 ) << 12 ) |  /* A */
+        ( ( Color.Value & 0x0F00 ) << 12 ) | ( ( Color.Value & 0x0F00 ) <<  8 ) |  /* R */
+        ( ( Color.Value & 0x00F0 ) <<  8 ) | ( ( Color.Value & 0x00F0 ) <<  4 ) |  /* G */
+        ( ( Color.Value & 0x000F ) <<  4 ) | ( ( Color.Value & 0x000F )       );   /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_rgb565_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE rgb565_t  rgba8888_t_to_rgb565_t( rgba8888_t Color )
+{
+    rgb565_t  ret;
+
+    ret.Value = (uint16_t) (
+                    ( ( Color.Value & 0xF8000000 ) >> 16 ) |  /* R */
+                    ( ( Color.Value & 0x00FC0000 ) >> 13 ) |  /* G */
+                    ( ( Color.Value & 0x0000F800 ) >> 11 ) ); /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_argb1555_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE argb1555_t  rgba8888_t_to_argb1555_t( rgba8888_t Color )
+{
+    argb1555_t  ret;
+
+    ret.Value = (uint16_t) (
+                    ( ( Color.Value & 0xF8000000 ) >> 17 ) |  /* R */
+                    ( ( Color.Value & 0x00F80000 ) >> 14 ) |  /* G */
+                    ( ( Color.Value & 0x0000F800 ) >> 11 ) |  /* B */
+                    ( ( Color.Value & 0x00000080 ) <<  8 ) ); /* A */
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_argb4444_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE argb4444_t  rgba8888_t_to_argb4444_t( rgba8888_t Color )
+{
+    argb4444_t  ret;
+
+    ret.Value = (uint16_t) (
+                    ( ( Color.Value & 0xF0000000 ) >> 20 ) |  /* R */
+                    ( ( Color.Value & 0x00F00000 ) >> 16 ) |  /* G */
+                    ( ( Color.Value & 0x0000F000 ) >> 12 ) |  /* B */
+                    ( ( Color.Value & 0x000000F0 ) <<  8 ) ); /* A */
+
+    return  ret;
+}
+
+
+/**
+* @brief   r8g8b8a8_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  r8g8b8a8_t_to_argb8888_t( r8g8b8a8_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value =
+        ( Color.u.Alpha << 24 ) |
+        ( Color.u.Red   << 16 ) |
+        ( Color.u.Green <<  8 ) |
+        ( Color.u.Blue );
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE argb8888_t  rgba8888_t_to_argb8888_t( rgba8888_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value = (
+                    ( ( Color.Value & 0xFF000000 ) >>  8 ) |  /* R */
+                    ( ( Color.Value & 0x00FF0000 ) >>  8 ) |  /* G */
+                    ( ( Color.Value & 0x0000FF00 ) >>  8 ) |  /* B */
+                    ( ( Color.Value & 0x000000FF ) << 24 ) ); /* A */
+
+    return  ret;
+}
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* NOT_DEFINE_INLINE_FUNCTION */
+#endif  /* RGA_PORT_INLINE_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_Port_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,192 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Port_typedef.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_PORT_TYPEDEF_H
+#define  RGA_PORT_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "clib_drivers.h"  /* ceil_8 */
+#include  "RGA_Port_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  uint16_not_aligned_t
+* @brief  uint16_not_aligned_t
+*/
+#pragma pack (push,1)
+/* uint16_not_aligned_t* variable raises warning, when it was passed to uint16_t* argument. */
+typedef struct _uint16_not_aligned_t {
+    uint8_t  byte[2];
+} uint16_not_aligned_t;
+#pragma pack (pop)
+
+
+/**
+* @struct  uint32_not_aligned_t
+* @brief  uint32_not_aligned_t
+*/
+#pragma pack (push,1)
+/* uint32_not_aligned_t* variable raises warning, when it was passed to uint32_t* argument. */
+typedef struct _uint32_not_aligned_t {
+    uint8_t  byte[4];
+} uint32_not_aligned_t;
+#pragma pack (pop)
+
+
+/**
+* @struct  BITMAPFILEHEADER
+* @brief  BITMAPFILEHEADER
+*/
+#pragma pack (push,1)
+typedef struct tagBITMAPFILEHEADER {
+    uint16_t  bfType;
+    uint32_t  bfSize;
+    uint16_t  bfReserved1;
+    uint16_t  bfReserved2;
+    uint32_t  bfOffBits;
+} BITMAPFILEHEADER;
+#pragma pack (pop)
+
+
+/**
+* @struct  BITMAPINFOHEADER
+* @brief  BITMAPINFOHEADER
+*/
+#pragma pack (push,1)
+typedef struct tagBITMAPINFOHEADER {
+    uint32_t  biSize;
+    int32_t   biWidth;
+    int32_t   biHeight;
+    uint16_t  biPlanes;
+    uint16_t  biBitCount;
+    uint32_t  biCompression;
+    uint32_t  biSizeImage;
+    int32_t   biXPelsPerMeter;
+    int32_t   biYPelsPerMeter;
+    uint32_t  biClrUsed;
+    uint32_t  biClrImportant;
+} BITMAPINFOHEADER;
+#pragma pack (pop)
+
+
+/**
+* @def  BI_BITFIELDS
+* @brief  BI_BITFIELDS
+*/
+enum { BI_BITFIELDS = 3 };
+
+
+/**
+* @struct  vram_ex_stack_t
+* @brief  vram_ex_stack_t
+*/
+typedef struct _vram_ex_stack_t  vram_ex_stack_t;
+struct _vram_ex_stack_t {
+    uint8_t  *Start;
+    uint8_t  *Over;
+    uint8_t  *StackPointer;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#ifdef  RGAH_VERSION
+#define  RGA_FRAME_BUFFER_ADDRESS_ALIGNMENT   32  /* byte */
+#define  RGA_SOURCE_IMAGE_STRIDE_ALIGNMENT    32  /* byte */
+#define  RGA_DESTINATION_STRIDE_ALIGNMENT     32  /* byte */
+#define  RGA_JPEG_ADDRESS_ALIGNMENT            8  /* byte */
+#define  RGA_JPEG_MAX_WIDTH_ALIGNMENT         16  /* pixel. Max of width_of_MCU */
+#define  RGA_JPEG_MAX_HEIGHT_ALIGNMENT        16  /* pixel. Max of height_of_MCU */
+#define  RGA_VDC5_BUFFER_ADDRESS_ALIGNMENT    64  /* byte */
+#define  RGA_WORK_BUFFER_MAX_DISPLAY_LIST    184  /* Constant value */
+#define  RGA_WORK_BUFFER_STRIDE               64  /* Constant value. This is not width of frame buffer */
+#define  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT    64  /* byte */
+#define  RGA_WORK_BUFFER_HEIGHT_ALIGNMENT      8  /* pixel */
+#define  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT  32  /* byte */
+/* RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT : RGA_RGAH_initBmp_ForSourceImage( colorBuffer ) */
+#endif
+#ifdef  RGAS_VERSION
+#define  RGA_FRAME_BUFFER_ADDRESS_ALIGNMENT    4  /* byte */
+#define  RGA_SOURCE_IMAGE_STRIDE_ALIGNMENT     4  /* byte */
+#define  RGA_DESTINATION_STRIDE_ALIGNMENT      4  /* byte */
+#define  RGA_JPEG_ADDRESS_ALIGNMENT            4  /* byte */
+#define  RGA_JPEG_MAX_WIDTH_ALIGNMENT         16  /* pixel. Max of width_of_MCU */
+#define  RGA_JPEG_MAX_HEIGHT_ALIGNMENT        16  /* pixel. Max of height_of_MCU */
+#define  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT     4  /* byte */
+#define  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT   4  /* byte */
+#endif
+#define  RGA_VDC5_BUFFER_ADDRESS_ALIGNMENT    64  /* byte */
+
+#define  RGA_MAX_WORK_SIZE_FOR_LIB_PNG_DEFAULT   0x40000 /* byte */ /* "work_size_for_libPNG" */
+
+#define  RGA_WORK_BUFFER_DMAC_LM_WIDTH_BYTE    4  /* byte */
+#define  RGA_WORK_BUFFER_DMAC_LM_HEIGHT_BYTE  32  /* byte */
+
+/**
+* @def  R_RGA_DEFAULT_CLEAR_COLOR
+* @brief  R_RGA_DEFAULT_CLEAR_COLOR
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_RGA_DEFAULT_CLEAR_COLOR  R_RGA_Get_R8G8B8A8( 255, 255, 255, 255 )
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* RGA_PORT_TYPEDEF_H */
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_raw_image.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,67 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_raw_image.h
+* @brief   $Module: RGA_Image $ $PublicVersion: 0.91 $ (=RGA_IMAGE_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  RGA_RAW_IMAGE_H
+#define  RGA_RAW_IMAGE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_raw_image_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "RGA_raw_image_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "RGA_raw_image_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "RGA_raw_image_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/RGA_raw_image_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,109 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_raw_image_typedef.h
+* @brief   $Module: RGA_Image $ $PublicVersion: 0.91 $ (=RGA_IMAGE_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  RGA_RAW_IMAGE_TYPEDEF_H
+#define  RGA_RAW_IMAGE_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  graphics_image_t
+* @brief  Raw image format of RGA and ImagePackager.
+*/
+typedef struct st_graphics_image_t  graphics_image_t;
+struct st_graphics_image_t {
+
+    /** flags */
+    uint32_t    flags;
+
+    /** offset_to_image */
+    uint32_t    offset_to_image;
+
+    /** offset_to_alpha */
+    uint32_t    offset_to_alpha;
+
+    /** width */
+    uint16_t    width;
+
+    /** height */
+    uint16_t    height;
+
+    /** type */
+    uint8_t     type;
+
+    /** type2 */
+    uint8_t     type2;
+
+    /** color */
+    uint32_t    color;
+};
+
+enum { /* graphics_image_t::flags */
+    F_T_IMAGE_INF_RAW_MASK    = 0x01,
+    F_T_IMAGE_INF_RAW_ADDRESS = 0x00,  /* T_IMAGE_INF::image and Alpha are pointers */
+    F_T_IMAGE_INF_RAW_OFFSET  = 0x01,  /* T_IMAGE_INF::image and Alpha are offsets */
+
+    F_T_IMAGE_INF_PREMULTIPLIED_ALPHA  = 0x04,  /* Premultiplied alpha */
+
+    F_T_IMAGE_INF_LINE_OFFSET = 0x08,  /* Color member variable is line offset */
+
+    F_T_IMAGE_INF_USED_MASK = 0x0000000F
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "RGA_raw_image.h" */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/frame_buffer.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,66 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  frame_buffer.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  FRAME_BUFFER_H
+#define  FRAME_BUFFER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "frame_buffer_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/frame_buffer_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,457 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  frame_buffer_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  FRAME_BUFFER_TYPEDEF_H
+#define  FRAME_BUFFER_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  byte_per_pixel_t
+* @brief  This can have shift value, if byte per pixel is less than 1
+*/
+typedef int  byte_per_pixel_t;
+#ifdef  IS_WINDOW_SURFACES_EX
+enum {
+    R_BYTE_PER_PIXEL_MASK  = 0xFF,  /*[R_BYTE_PER_PIXEL_MASK]*/
+    R_BYTE_PER_PIXEL_SHIFT = 8      /*[R_BYTE_PER_PIXEL_SHIFT]*/
+};
+#endif
+
+
+/**
+* @typedef  frame_buffer_delegate_t
+* @brief  This is user defined variable. Library does not access it.
+*/
+typedef void  frame_buffer_delegate_t;
+enum { /* int_fast32_t */  frame_buffer_t_max_buffer_count = 3 };
+
+
+/**
+* @enum   pixel_format_t
+* @brief  pixel_format_t
+*
+*    - PIXEL_FORMAT_UNKNOWN - 0,              0x00
+*    - PIXEL_FORMAT_ARGB8888 - 1,              0x01
+*    - PIXEL_FORMAT_RGB565 - 3,              0x03
+*    - PIXEL_FORMAT_ARGB4444 - 5,              0x05
+*    - PIXEL_FORMAT_A8 - 11,              0x0B
+*    - PIXEL_FORMAT_A4 - 14,              0x0E
+*    - PIXEL_FORMAT_A1 - 13,              0x0D
+*    - PIXEL_FORMAT_RGB888 - 15,              0x0F
+*    - PIXEL_FORMAT_R8G8B8A8 - 6 | (1 << 4),   0x16
+*    - PIXEL_FORMAT_XRGB8888 - 0 | (1 << 6),   0x40
+*    - PIXEL_FORMAT_ARGB1555 - 4 | (1 << 6),   0x10002
+*    - PIXEL_FORMAT_YCbCr422 - 2 | (1 << 16),  0x10002
+*    - PIXEL_FORMAT_YUV422 - 2 | (1 << 16),  0x10002
+*    - PIXEL_FORMAT_YUV422_GRAY_SCALE_IS_0x80 - 2 | (1 << 16),  0x10002
+*    - PIXEL_FORMAT_JPEG - 12 | (2 << 8),    0x20C
+*    - PIXEL_FORMAT_PNG - 12 | (3 << 8),    0x30C
+*    - PIXEL_FORMAT_GIF - 12 | (4 << 8),    0x40C
+*    - PIXEL_FORMAT_CLUT1 - 12 | (1 << 12),  0x100C
+*    - PIXEL_FORMAT_CLUT4 - 12 | (4 << 12),  0x400C
+*    - PIXEL_FORMAT_CLUT8 - 12 | (8 << 12)   0x800C
+*/
+enum _pixel_format_t {
+    PIXEL_FORMAT_UNKNOWN  =  0,
+    PIXEL_FORMAT_ARGB8888 =  1,
+    PIXEL_FORMAT_RGB565   =  3,
+    PIXEL_FORMAT_ARGB4444 =  5,
+    PIXEL_FORMAT_A8       = 11,
+    PIXEL_FORMAT_A4       = 14,
+    PIXEL_FORMAT_A1       = 13,
+    PIXEL_FORMAT_RGB888   = 15,
+    PIXEL_FORMAT_R8G8B8A8 =  6 | (1 << 4),
+    PIXEL_FORMAT_XRGB8888 =  0 | (1 << 6),
+    PIXEL_FORMAT_ARGB1555 =  4 | (1 << 6),
+    PIXEL_FORMAT_YCbCr422 =  2 | (1 << 16),
+    PIXEL_FORMAT_YUV422   =  2 | (1 << 16),
+    PIXEL_FORMAT_YUV422_GRAY_SCALE_IS_0x80  = 2 | (1 << 16),
+    PIXEL_FORMAT_JPEG     = 12 | (2 << 8),
+    PIXEL_FORMAT_PNG      = 12 | (3 << 8),
+    PIXEL_FORMAT_GIF      = 12 | (4 << 8),
+    PIXEL_FORMAT_CLUT1    = 12 | (1 << 12),
+    PIXEL_FORMAT_CLUT4    = 12 | (4 << 12),
+    PIXEL_FORMAT_CLUT8    = 12 | (8 << 12)
+};
+typedef enum _pixel_format_t  pixel_format_t;
+
+
+/**
+* @struct  frame_buffer_t
+* @brief  frame_buffer_t
+*/
+typedef struct st_frame_buffer_t  frame_buffer_t;
+struct st_frame_buffer_t {
+
+    /** Cached address, [2] is Reserved */
+    uint8_t          *buffer_address[ frame_buffer_t_max_buffer_count ];
+
+    /** max is 2 */
+    int_fast32_t      buffer_count;
+
+    /** Index of "buffer_address" */
+    int_fast32_t      show_buffer_index;
+
+    /** Index of "buffer_address" */
+    int_fast32_t      draw_buffer_index;
+
+    /** width */
+    int_fast32_t      width;
+
+    /** check Stride and PixelFormat */
+    byte_per_pixel_t  byte_per_pixel;
+
+    /** byte to next bottom line */
+    int_fast32_t      stride;
+
+    /** height */
+    int_fast32_t      height;
+
+    /** pixel_format */
+    pixel_format_t    pixel_format;
+
+    /** delegate */
+    frame_buffer_delegate_t  *delegate;
+};
+
+
+/**
+* @struct  r8g8b8a8_t
+* @brief  One of color type
+*/
+#define  r8g8b8a8_t  r8g8b8a8_t
+typedef union st_r8g8b8a8_t  r8g8b8a8_t;
+union st_r8g8b8a8_t {
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** u */
+        uint8_t  Red;
+
+        /** u */
+        uint8_t  Green;
+
+        /** u */
+        uint8_t  Blue;
+
+        /** u */
+        uint8_t  Alpha;
+#else
+        uint8_t  Alpha;
+        uint8_t  Blue;
+        uint8_t  Green;
+        uint8_t  Red;
+#endif
+    } u;  /* 1st member "u" can be used by initializer */
+
+    /** Value */
+    uint32_t  Value;  /* This is depend on CPU endian. Use only copy or compare */
+};
+
+
+/**
+* @struct  argb8888_t
+* @brief  One of color type
+*/
+#define        argb8888_t  argb8888_t
+typedef union _ARGB8888Type  argb8888_t;
+union _ARGB8888Type {
+    uint32_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if BYTE_ENDIAN == BYTE_LITTLE_ENDIAN
+
+        /** Blue is Value & 0x000000FF */
+        uint8_t  Blue;
+
+        /** u */
+        uint8_t  Green;
+
+        /** u */
+        uint8_t  Red;
+
+        /** u */
+        uint8_t  Alpha;
+#else
+        uint8_t  Alpha;
+        uint8_t  Red;
+        uint8_t  Green;
+        uint8_t  Blue;   /* Blue is Value & 0x000000FF */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  xrgb8888_t
+* @brief  One of color type
+*/
+#define        xrgb8888_t  xrgb8888_t
+typedef union _XRGB8888Type  xrgb8888_t;
+union _XRGB8888Type {
+    uint32_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if BYTE_ENDIAN == BYTE_LITTLE_ENDIAN
+
+        /** Blue is Value & 0x000000FF */
+        uint8_t  Blue;
+
+        /** u */
+        uint8_t  Green;
+
+        /** u */
+        uint8_t  Red;
+
+        /** u */
+        uint8_t  X;      /* zero */
+#else
+        uint8_t  X;      /* zero */
+        uint8_t  Red;
+        uint8_t  Green;
+        uint8_t  Blue;   /* Blue is Value & 0x000000FF */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  rgb565_t
+* @brief  One of color type
+*/
+#define        rgb565_t  rgb565_t
+typedef union _RGB565Type  rgb565_t;
+union _RGB565Type {
+    uint16_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Blue is at LSB */
+        unsigned  Blue  : 5;
+
+        /** u */
+        unsigned  Green : 6;
+
+        /** u */
+        unsigned  Red   : 5;
+#else
+        unsigned  Red   : 5;
+        unsigned  Green : 6;
+        unsigned  Blue  : 5;  /* Blue is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  argb1555_t
+* @brief  One of color type
+*/
+#define        argb1555_t  argb1555_t
+typedef union _ARGB1555Type  argb1555_t;
+union _ARGB1555Type {
+    uint16_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Blue is at LSB */
+        unsigned  Blue  : 5;
+
+        /** u */
+        unsigned  Green : 5;
+
+        /** u */
+        unsigned  Red   : 5;
+
+        /** u */
+        unsigned  Alpha : 1;
+#else
+        unsigned  Alpha : 1;
+        unsigned  Red   : 5;
+        unsigned  Green : 5;
+        unsigned  Blue  : 5;  /* Blue is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  argb4444_t
+* @brief  One of color type
+*/
+#define        argb4444_t  argb4444_t
+typedef union _ARGB4444Type  argb4444_t;
+union _ARGB4444Type {
+    uint16_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Blue is at LSB */
+        unsigned  Blue  : 4;
+
+        /** u */
+        unsigned  Green : 4;
+
+        /** u */
+        unsigned  Red   : 4;
+
+        /** u */
+        unsigned  Alpha : 4;
+#else
+        unsigned  Alpha : 4;
+        unsigned  Red   : 4;
+        unsigned  Green : 4;
+        unsigned  Blue  : 4;  /* Blue is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  rgba8888_t
+* @brief  One of color type
+*/
+#define        rgba8888_t  rgba8888_t
+typedef union _RGBA8888Type  rgba8888_t;
+union _RGBA8888Type {
+    uint32_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Alpha is at LSB */
+        unsigned  Alpha : 8;
+
+        /** u */
+        unsigned  Blue  : 8;
+
+        /** u */
+        unsigned  Green : 8;
+
+        /** u */
+        unsigned  Red   : 8;
+#else
+        unsigned  Red   : 8;
+        unsigned  Green : 8;
+        unsigned  Blue  : 8;
+        unsigned  Alpha : 8;  /* Alpha is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  y_cb_cr_422_t
+* @brief  Same as <yuv422_t>
+*/
+/**
+* @struct  yuv422_t
+* @brief  One of color type
+*/
+#define          y_cb_cr_422_t  y_cb_cr_422_t
+typedef union st_y_cb_cr_422_t  y_cb_cr_422_t;
+#define          yuv422_t       yuv422_t
+typedef union st_y_cb_cr_422_t  yuv422_t;
+union st_y_cb_cr_422_t {
+    struct {
+        /** U */
+        uint8_t  Cb_01;
+
+        /** u */
+        uint8_t  Y_0;
+
+        /** V */
+        uint8_t  Cr_01;
+
+        /** u */
+        uint8_t  Y_1;
+
+    } u;  /* 1st member "u" can be used by initializer */
+
+    struct {
+        /** uu */
+        uint8_t  U_01;
+
+        /** uu */
+        uint8_t  Y_0;
+
+        /** uu */
+        uint8_t  V_01;
+
+        /** uu */
+        uint8_t  Y_1;
+    } uu;
+
+    uint32_t  Value;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Section: Global */
+/**
+* @enum   E_CATEGORY_PIXEL_FORMAT
+* @brief  E_CATEGORY_PIXEL_FORMAT
+*
+*    - E_NOT_SUPPORTED_PIXEL_FORMAT - E_CATEGORY_PIXEL_FORMAT | 0x01
+*/
+#ifndef  E_CATEGORY_PIXEL_FORMAT
+#define  E_CATEGORY_PIXEL_FORMAT  E_CATEGORY_PIXEL_FORMAT
+enum {   E_CATEGORY_PIXEL_FORMAT = 0x00009400 };
+#endif
+enum { E_NOT_SUPPORTED_PIXEL_FORMAT  = E_CATEGORY_PIXEL_FORMAT | 0x01 }; /* 0x9401 = 37889 */
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "frame_buffer.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/video_input.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,103 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: V-Sync porting layer
+*/
+
+#ifndef  VIDEO_INPUT_H
+#define  VIDEO_INPUT_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "video_input_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "video_input_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "video_input_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "video_input_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   R_VIDEO_INPUT_InitConst
+*
+* @param   self video_input_t
+* @return  None
+*/
+void  R_VIDEO_INPUT_InitConst( video_input_t *const  self );
+
+
+/**
+* @brief   R_VIDEO_INPUT_Initialize
+*
+* @param   self video_input_t
+* @param   in_out_Config Configuration
+* @return  Error Code. 0=No Error.
+*
+* @par Description
+*    "R_WINDOW_SURFACES_SwapBuffers" must be called after calling this
+*    function for showing video layer.
+*    Set "window_surfaces_config_t::background_mode" = "BACKGROUND_MODE_VIDEO_INTERLACE"
+*/
+errnum_t  R_VIDEO_INPUT_Initialize( video_input_t *const  self,
+                                    video_input_config_t *in_out_Config );
+
+
+/**
+* @brief   R_VIDEO_INPUT_Finalize
+*
+* @param   self video_input_t
+* @param   e Errors that have occurred. No error = 0
+* @return  Error code or e, 0 = successful and input e=0
+*/
+errnum_t  R_VIDEO_INPUT_Finalize( video_input_t *const  self, errnum_t e );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/video_input.hpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input.hpp
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: Video Input for mbed style C++ API
+*/
+
+#ifndef  VIDEO_INPUT_HPP
+#define  VIDEO_INPUT_HPP
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "video_input_typedef.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+class  VideoInputConfig;
+
+
+/***********************************************************************
+* Class: VideoInput
+*    mbed style C++ version of <video_input_t>
+************************************************************************/
+class  VideoInput {
+public:
+	/**
+* @brief   VideoInput
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	VideoInput();
+	~VideoInput();
+
+	/**
+* @brief   initialize
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  initialize( VideoInputConfig& in_out_Config );
+
+	/**
+* @brief   destroy
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	void  destroy();
+
+private:
+	video_input_t*  _self;
+};
+
+
+/***********************************************************************
+* Class: VideoInputConfig
+*    mbed style C++ version of <video_input_config_t>
+************************************************************************/
+class  VideoInputConfig : public video_input_config_t {
+public:
+	/**
+* @brief   VideoInputConfig
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	VideoInputConfig();
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/video_input_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,190 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input_typedef.h
+* @brief   $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+#ifndef  VIDEO_INPUT_TYPEDEF_H
+#define  VIDEO_INPUT_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_vdc5.h"
+#include  "r_vdec.h"
+#include  "frame_buffer_typedef.h"
+#include  "r_ospl_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/***********************************************************************
+* Macros: INTERRUPT_FUNCTION_TYPE
+*    INTERRUPT_FUNCTION_TYPE
+*
+*    : INTERRUPT_FUNCTION_TYPE_OS_RTX  - RTX
+*    : INTERRUPT_FUNCTION_TYPE_OS_LESS - OS less
+************************************************************************/
+#if R_OSPL_IS_PREEMPTION
+#define  INTERRUPT_FUNCTION_TYPE  INTERRUPT_FUNCTION_TYPE_OS_RTX
+#else
+#define  INTERRUPT_FUNCTION_TYPE  INTERRUPT_FUNCTION_TYPE_OS_LESS
+#endif
+#define  INTERRUPT_FUNCTION_TYPE_OS_LESS  0
+#define  INTERRUPT_FUNCTION_TYPE_OS_RTX   1
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   video_input_channel_enum_t
+* @brief  Special integer value
+*
+*    - VIDEO_INPUT_NOT_DISPLAY - 0xFF
+*/
+enum st_video_input_channel_enum_t {
+    VIDEO_INPUT_NOT_DISPLAY = 0xFF
+};
+typedef enum st_video_input_channel_enum_t  video_input_channel_enum_t;
+/* "typedef" must be after "enum". Because GCC_ARM raises an error */
+
+
+/**
+* @struct  video_input_t
+* @brief  video_input_t
+*
+* @par Description
+*    Member variables can not be accessed by user.
+*/
+typedef struct st_video_input_t  video_input_t;
+struct st_video_input_t {
+
+    /*-----------------------------------------------------------*/
+    /* Group: Cannel */
+
+    /** video_input_channel */
+    vdc5_channel_t      video_input_channel;
+
+    /** video_input_select */
+    vdec_adc_vinsel_t   video_input_select;
+
+    /** is_data_control */
+    bool_t              is_data_control;
+
+    /** data_control_ID */
+    vdc5_layer_id_t     data_control_ID;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Interrupt */
+
+    /** is_vsync_interrupt_registered */
+    bool_t              is_vsync_interrupt_registered[3];
+
+    /** interrupt_for_VDC5 */
+    vdc5_int_t          interrupt_for_VDC5;
+
+    /** interrupt_ID */
+    bsp_int_src_t       interrupt_ID;
+
+    /** interrupt_vector */
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+    bsp_int_cb_t        interrupt_vector;
+#endif
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Buffer */
+
+    /** frame_buffer */
+    frame_buffer_t      frame_buffer;
+
+    /** captured_buffer_index */
+    int_fast32_t        captured_buffer_index;
+
+    /** captured_count */
+    int_fast32_t        captured_count;
+
+    /** captured_async */
+    r_ospl_async_t     *captured_async;
+};
+
+
+/**
+* @struct  video_input_config_t
+* @brief  Parameters of <R_VIDEO_INPUT_Initialize>
+*/
+typedef struct st_video_input_config_t  video_input_config_t;
+struct st_video_input_config_t {
+
+    /** 0 | VIDEO_INPUT_CONFIG_T_layer_ID | ... */
+    bit_flags_fast32_t  flags;
+
+
+    /** 0=ch0.VIN1, 1=ch1.VIN1, 2=ch0.VIN2, 3=ch1.VIN2 */
+    int_fast32_t        video_input_channel_num;
+
+    /** 0, 1 or VIDEO_INPUT_NOT_DISPLAY */
+    int_fast32_t        display_channel_num;
+
+    /** -1 or VIDEO_INPUT_NOT_DISPLAY */
+    int_fast32_t        display_layer_num;
+
+    /** frame_buffer */
+    frame_buffer_t     *frame_buffer;
+
+    /** captured_async */
+    r_ospl_async_t     *captured_async;
+};
+/* video_input_config_t::flags */
+#define  VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM  0x0001
+#define  VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM      0x0002
+#define  VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM        0x0004
+#define  VIDEO_INPUT_CONFIG_T_FRAME_BUFFER             0x0008
+#define  VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC           0x0010
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "video_input.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/vsync.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,138 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  VSYNC_H
+#define  VSYNC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "vsync_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "vsync_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "vsync_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "vsync_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Initialize V-Sync object of specified channel number
+*
+* @param   ChannelNum ChannelNum
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_Initialize( int_fast32_t const  ChannelNum );
+
+
+/**
+* @brief   R_V_SYNC_Finalize
+*
+* @param   ChannelNum ChannelNum
+* @param   e Errors that have occurred. No error = 0
+* @return  Error code or e, 0 = successful and input e=0
+*/
+errnum_t  R_V_SYNC_Finalize( int_fast32_t const  ChannelNum,  errnum_t e );
+
+
+/**
+* @brief   Wait for V-Sync
+*
+* @param   ChannelNum ChannelNum
+* @param   SwapInterval If 1=60fps Then 2=30fps, 3=20fps
+* @param   Is1VSyncAtMinimum false = It is possible to return soon
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_Wait( int_fast32_t const  ChannelNum,
+                         int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum );
+
+
+/**
+* @brief   Asynchronous function of <R_V_SYNC_Wait>
+*
+* @param   ChannelNum ChannelNum
+* @param   SwapInterval If 1=60fps Then 2=30fps, 3=20fps
+* @param   Is1VSyncAtMinimum false = It is possible to set event soon
+* @param   Async r_ospl_async_t
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_WaitStart( int_fast32_t const  ChannelNum,
+                              int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum,
+                              r_ospl_async_t *const  Async );
+
+
+/**
+* @brief   Receive interrupt information.
+*
+* @param   InterruptSource r_ospl_interrupt_t
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource );
+
+
+/**
+* @brief   Get <r_v_sync_async_status_t>
+*
+* @param   ChannelNum ChannelNum
+* @param   out_Status AsyncStatus
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_GetAsyncStatus( int_fast32_t const  ChannelNum,
+                                   const r_v_sync_async_status_t **const  out_Status );
+
+
+/* Following functions can not be called from Application. */
+void      R_V_SYNC_EnableInterrupt( int_fast32_t const  ChannelNum );
+bool_t    R_V_SYNC_DisableInterrupt( int_fast32_t const  ChannelNum );
+/* It is not necessary: R_V_SYNC_FinalizeAsync(), R_V_SYNC_OnInterrupted() */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/vsync_pl.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync_pl.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+* - Description: V-Sync porting layer
+*/
+
+#ifndef  WINDOW_SURFACES_PL_H
+#define  WINDOW_SURFACES_PL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "vsync_typedef.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+    /******************************************************************************
+    Typedef definitions
+    ******************************************************************************/
+
+    /******************************************************************************
+    Macro definitions
+    ******************************************************************************/
+
+    /******************************************************************************
+    Variable Externs
+    ******************************************************************************/
+
+    /******************************************************************************
+    Functions Prototypes
+    ******************************************************************************/
+
+
+    /**
+    * @brief   Set default <r_ospl_async_t>
+    *
+    * @param   in_out_Async Async parameters
+    * @param   AsyncType r_ospl_async_type_t
+    * @return  None
+    */
+    void  R_V_SYNC_SetDefaultAsync( r_ospl_async_t *const  in_out_Async,  r_ospl_async_type_t AsyncType );
+
+
+    /**
+    * @brief   Called from <R_V_SYNC_Initialize>
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_OnInitialize( int_fast32_t const  ChannelNum );
+
+
+    /**
+    * @brief   Called from <R_V_SYNC_Finalize>
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_OnFinalize( int_fast32_t const  ChannelNum,  errnum_t e );
+
+
+    /**
+    * @brief   Send <r_ospl_caller_t> to porting layer
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @param   Caller r_ospl_caller_t
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_SetInterruptCallbackCaller( int_fast32_t const  ChannelNum,
+            const r_ospl_caller_t *const  Caller );
+
+
+    /**
+    * @brief   Enable interrupt lines
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @param   Enables <r_v_sync_interrupt_lines_t>. 1=Enable, 0=NotChange
+    * @return  Error Code. 0=No Error.
+    */
+    void   R_V_SYNC_OnEnableInterrupt( int_fast32_t const  ChannelNum,
+                                       r_v_sync_interrupt_lines_t const  Enables );
+
+
+    /**
+    * @brief   Disable interrupt lines
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @param   Disables <r_v_sync_interrupt_lines_t>. 1=Disable, 0=NotChange
+    * @return  Error Code. 0=No Error.
+    */
+    void      R_V_SYNC_OnDisableInterrupt( int_fast32_t const  ChannelNum,
+                                           r_v_sync_interrupt_lines_t const  Disables );
+
+
+    /**
+    * @brief   Default interrupt callback function
+    *
+    * @param   InterruptSource r_ospl_interrupt_t
+    * @param   Caller r_ospl_caller_t
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                           const r_ospl_caller_t *const  Caller );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/vsync_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,107 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  VSYNC_TYPEDEF_H
+#define  VSYNC_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_ospl_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  r_v_sync_interrupt_line_t
+* @brief  r_v_sync_interrupt_line_t
+*/
+typedef uint_fast32_t  r_v_sync_interrupt_line_t;
+#define  R_V_SYNC_INTERRUPT_LINE_V_LINE  0x00000001u
+
+
+/**
+* @typedef  r_v_sync_interrupt_lines_t
+* @brief  r_v_sync_interrupt_lines_t
+*/
+typedef bit_flags_fast32_t /*<r_v_sync_interrupt_line_t>*/  r_v_sync_interrupt_lines_t;
+
+
+/**
+* @def  R_V_SYNC_INTERRUPT_LINE_ALL
+* @brief  All bits of <r_v_sync_interrupt_lines_t>
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_V_SYNC_INTERRUPT_LINE_ALL  ( R_V_SYNC_INTERRUPT_LINE_V_LINE )
+
+
+/**
+* @typedef  r_v_sync_async_status_t
+* @brief  r_v_sync_async_status_t
+*/
+typedef struct st_r_ospl_async_status_t  r_v_sync_async_status_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_V_SYNC_CHANNEL_COUNT
+* @brief  VDC5 channel count
+* @par Parameters
+*    None
+* @return  None.
+*/
+enum { R_V_SYNC_CHANNEL_COUNT = 2 };
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "vsync.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/window_surfaces.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,185 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: window_surfaces.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* Description: Sample API
+*******************************************************************************/
+
+#ifndef  WINDOW_SURFACES_H
+#define  WINDOW_SURFACES_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "clib_drivers_typedef.h"
+#include  "window_surfaces_typedef.h"
+#include  "r_multi_compiler_typedef.h"
+#include  "window_surfaces_inline.h"
+#ifdef  IS_WINDOW_SURFACES_EX
+#include  "window_surfaces_ex.h"
+#include  "RGA_API_typedef.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   R_WINDOW_SURFACES_InitConst
+*
+* @param   self window_surfaces_t
+* @return  None
+*/
+void      R_WINDOW_SURFACES_InitConst( window_surfaces_t *const  self );
+
+
+/**
+* @brief   R_WINDOW_SURFACES_Initialize
+*
+* @param   self window_surfaces_t
+* @param   in_out_config window_surfaces_config_t
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_Initialize( window_surfaces_t *const  self,
+                                        window_surfaces_config_t *in_out_config );
+
+
+/**
+* @brief   R_WINDOW_SURFACES_Finalize
+*
+* @param   self window_surfaces_t
+* @param   e Errors that have occurred. No error = 0
+* @return  Error code or e, 0 = successful and input e=0
+*/
+errnum_t  R_WINDOW_SURFACES_Finalize( window_surfaces_t *const  self, errnum_t e );
+
+
+/**
+* @brief   Get <frame_buffer_t>* of specified layer number
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @param   out_frame_buffer out_frame_buffer
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_GetLayerFrameBuffer( const window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  frame_buffer_t **const  out_frame_buffer );
+
+
+/**
+* @brief   R_WINDOW_SURFACES_SwapBuffers
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @param   context Graphics context or NULL
+* @return  Error code, 0=No error
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  R_WINDOW_SURFACES_SwapBuffers( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  graphics_t *const  context );
+#else
+errnum_t  R_WINDOW_SURFACES_SwapBuffers( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  const void *const  null_context );
+#endif
+
+
+/**
+* @brief   Asynchronous function of <R_WINDOW_SURFACES_SwapBuffers>
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @param   async r_ospl_async_t
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_SwapBuffersStart( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  r_ospl_async_t *async );
+
+
+/**
+* @brief   Wait for V-Sync
+*
+* @param   swap_interval If 1=60fps Then 2=30fps, 3=20fps
+* @param   is_1_v_sync_at_minimum false = It is possible to return soon
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_WINDOW_SURFACES_WaitForVSync( window_surfaces_t *const  self,
+        int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum );
+
+
+/**
+* @brief   Allocate offscreen from stack
+*
+* @param   self window_surfaces_t
+* @param   in_out_frame_buffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - (input) - >stride, ->height, ->buffer_count
+*    - (output) - >buffer_address[(all)]
+*/
+errnum_t  R_WINDOW_SURFACES_AllocOffscreenStack( window_surfaces_t *const  self,
+        frame_buffer_t *const  in_out_frame_buffer );
+
+
+/**
+* @brief   Free offscreen to stack
+*
+* @param   self window_surfaces_t
+* @param   frame_buffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - If frame_buffer - >buffer_count == 0, do nothing.
+*/
+errnum_t  R_WINDOW_SURFACES_FreeOffscreenStack( window_surfaces_t *const  self,
+        const frame_buffer_t *const  frame_buffer );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/window_surfaces.hpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,218 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces.hpp
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.20 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: Window Surfaces for mbed style C++ API
+*/
+
+#ifndef  WINDOW_SURFACES_HPP
+#define  WINDOW_SURFACES_HPP
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "window_surfaces_typedef.h"
+#include  "RGA.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+class  WindowSurfacesConfigClass;
+#ifdef  IS_WINDOW_SURFACES_EX
+class  GraphicsClass;
+class  LayerAttributes;
+#endif
+
+
+/***********************************************************************
+* Class: WindowSurfacesClass
+*    mbed style C++ version of <window_surfaces_t>
+************************************************************************/
+class  WindowSurfacesClass {
+public:
+	/**
+* @brief   WindowSurfacesClass
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	WindowSurfacesClass();
+	~WindowSurfacesClass();
+
+	/**
+* @brief   initialize
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  initialize( WindowSurfacesConfigClass& in_out_config );
+
+	/**
+* @brief   destroy
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	void  destroy();
+
+	/**
+* @brief   get_layer_frame_buffer
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  get_layer_frame_buffer( int_fast32_t const  layer_num,  frame_buffer_t** const  out_frame_buffer );
+
+	/**
+* @brief   swap_buffers
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	#ifdef  IS_WINDOW_SURFACES_EX
+	errnum_t  swap_buffers( int_fast32_t const  layer_num,  Canvas2D_ContextClass&  context );
+	#else
+	errnum_t  swap_buffers( int_fast32_t const  layer_num,  const void* const  null_context );
+	#endif
+
+	/**
+* @brief   swap_buffers_start
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  swap_buffers_start( int_fast32_t const  layer_num,  r_ospl_async_t* async );
+
+	/**
+* @brief   wait_for_v_sync
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  wait_for_v_sync( int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum );
+
+	/**
+* @brief   alloc_offscreen_stack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  alloc_offscreen_stack( frame_buffer_t* const  in_out_frame_buffer );
+
+	/**
+* @brief   free_offscreen_stack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  free_offscreen_stack( const frame_buffer_t* const  frame_buffer );
+
+#ifdef  IS_WINDOW_SURFACES_EX
+	/**
+* @brief   do_message_loop
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  do_message_loop();
+
+	/**
+* @brief   access_layer_attributes
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  access_layer_attributes( LayerAttributes& in_out_Attributes );
+#endif
+
+private:
+	window_surfaces_t*  _self;
+};
+
+
+/***********************************************************************
+* Class: WindowSurfacesConfigClass
+*    mbed style C++ version of <window_surfaces_config_t>
+************************************************************************/
+class  WindowSurfacesConfigClass : public window_surfaces_config_t {
+public:
+	/**
+* @brief   WindowSurfacesConfigClass
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	WindowSurfacesConfigClass();
+};
+
+
+/***********************************************************************
+* Class: LayerAttributes
+*    mbed style C++ version of <layer_attributes_t>
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+class  LayerAttributes : public layer_attributes_t {
+public:
+	/**
+* @brief   LayerAttributes
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	LayerAttributes();
+};
+#endif
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif  /* WINDOW_SURFACES_HPP */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/window_surfaces_ex.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,133 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_ex.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+#ifndef  WINDOW_SURFACES_EX_H
+#define  WINDOW_SURFACES_EX_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "window_surfaces_ex_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* Class: window_surfaces_t
+*    Extra methods of <window_surfaces_t>
+************************************************************************/
+
+/**
+* @brief   Emulate message loop function.
+*
+* @param   self window_surfaces_t
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_DoMessageLoop( window_surfaces_t *self );
+
+
+/**
+* @brief   Set or get by <layer_attributes_t>
+*
+* @param   self window_surfaces_t
+* @param   in_out_Attributes <layer_attributes_t>
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_AccessLayerAttributes( window_surfaces_t *self,
+        layer_attributes_t *in_out_Attributes );
+
+
+/***********************************************************************
+* Class: vram_ex_stack_t
+*    VRAM stack in external RAM
+************************************************************************/
+
+/**
+* @brief   R_VRAM_EX_STACK_Initialize
+*
+* @param   self vram_ex_stack_t
+* @param   NullConfig NULL
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_VRAM_EX_STACK_Initialize( vram_ex_stack_t *self, void *NullConfig );
+
+
+/**
+* @brief   Allocate VRAM from external RAM
+*
+* @param   self vram_ex_stack_t
+* @param   in_out_FrameBuffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - (input) - >stride, ->height, ->buffer_count
+*    - (output) - >buffer_address[(all)]
+*/
+errnum_t  R_VRAM_EX_STACK_Alloc( vram_ex_stack_t *self, frame_buffer_t *in_out_FrameBuffer );
+
+
+/**
+* @brief   Free VRAM to external RAM
+*
+* @param   self vram_ex_stack_t
+* @param   frame_buffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - If frame_buffer - >buffer_count == 0, do nothing.
+*/
+errnum_t  R_VRAM_EX_STACK_Free( vram_ex_stack_t *self, frame_buffer_t *frame_buffer );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/window_surfaces_ex_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,189 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_ex_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+#ifndef  WINDOW_SURFACES_EX_TYPEDEF_H
+#define  WINDOW_SURFACES_EX_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/**
+* @struct  window_surfaces_attribute_t
+* @brief  Type of <window_surfaces_t>::attributes.
+*/
+typedef  struct st_window_surfaces_attribute_t  window_surfaces_attribute_t;
+struct st_window_surfaces_attribute_t {
+
+    /** X */
+    int_fast32_t  X;
+
+    /** Y */
+    int_fast32_t  Y;
+
+    /** Width */
+    int_fast32_t  Width;
+
+    /** Height */
+    int_fast32_t  Height;
+
+    /** OffsetX */
+    int_fast32_t  OffsetX;
+
+    /** OffsetY */
+    int_fast32_t  OffsetY;
+
+    /** OffsetByte */
+    int_fast32_t  OffsetByte;
+};
+
+
+/* Section: Global */
+/**
+* @enum   access_t
+* @brief  access_t
+*    - ACCESS_READ - 1
+*    - ACCESS_WRITE - 2
+*    - ACCESS_READ_WRITE - 3
+*    - ACCESS_PLUS - 4
+*/
+enum st_access_t {
+    ACCESS_READ  = 1,
+    ACCESS_WRITE = 2,
+    ACCESS_READ_WRITE = ( 1 | 2 ),
+    ACCESS_PLUS  = 4,
+
+    ACCESS_ALL_MASK = ACCESS_READ | ACCESS_WRITE | ACCESS_READ_WRITE | ACCESS_PLUS
+};
+typedef  enum st_access_t  access_t;
+
+
+/**
+* @struct  layer_attributes_t
+* @brief  Parameters of <R_WINDOW_SURFACES_AccessLayerAttributes>.
+*/
+typedef  struct st_layer_attributes_t  layer_attributes_t;
+struct st_layer_attributes_t {
+
+    /** access */
+    access_t      access;
+
+    /** 0 | F_LAYER_IS_SHOW | ... */
+    bit_flags_fast32_t  flags;
+
+    /** id */
+    int_fast32_t  id;
+
+    /** priority */
+    int_fast32_t  priority;
+
+    /** is_show */
+    bool_t        is_show;
+
+    /** is_color_key */
+    bool_t        is_color_key;
+
+    /** color_key */
+    r8g8b8a8_t    color_key;
+
+    /** layer_color */
+    r8g8b8a8_t    layer_color;
+
+    /** x */
+    int_fast32_t  x;
+
+    /** y */
+    int_fast32_t  y;
+
+    /** width */
+    int_fast32_t  width;
+
+    /** height */
+    int_fast32_t  height;
+
+    /** offset_x */
+    int_fast32_t  offset_x;
+
+    /** offset_y */
+    int_fast32_t  offset_y;
+
+    /** CLUT (Color Look Up Table) */
+    uint32_t     *CLUT;
+
+    /** CLUT (Color Look Up Table) count */
+    int_fast32_t  CLUT_count;
+};
+
+enum {
+    F_LAYER_ID           = 0x0001,
+    F_LAYER_PRIORITY     = 0x0002,
+    F_LAYER_IS_SHOW      = 0x0004,
+    F_LAYER_IS_COLOR_KEY = 0x0008,
+    F_LAYER_COLOR_KEY    = 0x0010,
+    F_LAYER_LAYER_COLOR  = 0x0020,
+    F_LAYER_X            = 0x0040,
+    F_LAYER_Y            = 0x0080,
+    F_LAYER_WIDTH        = 0x0100,
+    F_LAYER_HEIGHT       = 0x0200,
+    F_LAYER_OFFSET_X     = 0x0400,
+    F_LAYER_OFFSET_Y     = 0x0800,
+    F_LAYER_CLUT         = 0x1000,
+    F_LAYER_CLUT_COUNT   = 0x2000
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "window_surfaces_ex.h" */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/window_surfaces_inline.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,101 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_inline.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+
+/* This file is included from "window_surfaces.h" */
+
+
+#ifndef  WINDOW_SURFACES_INLINE_H
+#define  WINDOW_SURFACES_INLINE_H
+#ifndef  NOT_DEFINE_INLINE_FUNCTION
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  <stdint.h>
+#include  "clib_drivers_typedef.h"
+#include  "frame_buffer_typedef.h"
+#include  "r_multi_compiler_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   Get color
+*
+* @param   Red Red.
+* @param   Green Green.
+* @param   Blue Blue.
+* @param   Alpha Alpha.
+* @return  Color code as "r8g8b8a8_t"
+*/
+INLINE r8g8b8a8_t  R_RGA_Get_R8G8B8A8( int_fast32_t const  Red,
+                                       int_fast32_t const  Green,
+                                       int_fast32_t const  Blue,
+                                       int_fast32_t const  Alpha )
+{
+    r8g8b8a8_t  color_;  /* _ is for MISRA 5.6 */
+
+    /* ->QAC 3198 */
+    color_.Value = DUMMY_INITIAL_VALUE;  /* for avoid ARMCC warning C4017W */
+    /* <-QAC 3198 */
+    color_.u.Red   = (uint8_t) Red;
+    color_.u.Green = (uint8_t) Green;
+    color_.u.Blue  = (uint8_t) Blue;
+    color_.u.Alpha = (uint8_t) Alpha;
+
+    return  color_;
+}
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* NOT_DEFINE_INLINE_FUNCTION */
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/window_surfaces_private.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: window_surfaces_private.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* Description  : Sample API
+*******************************************************************************/
+
+#ifndef  WINDOW_SURFACES_PRIVATE_H
+#define  WINDOW_SURFACES_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_Port_typedef.h"
+#include  "r_ospl_typedef.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  RGA_STACK_ADDRESS_ALIGNMENT  64
+R_STATIC_ASSERT_GLOBAL( RGA_STACK_ADDRESS_ALIGNMENT >= RGA_SOURCE_IMAGE_STRIDE_ALIGNMENT, "" );
+R_STATIC_ASSERT_GLOBAL( RGA_STACK_ADDRESS_ALIGNMENT >= RGA_VDC5_BUFFER_ADDRESS_ALIGNMENT, "" );
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+errnum_t  R_EXRAM_GetBigMemory( void * /*<type**>*/ out_Address, size_t *out_Size );
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* WINDOW_SURFACES_PRIVATE_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/inc/window_surfaces_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,228 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+#ifndef  WINDOW_SURFACES_TYPEDEF_H
+#define  WINDOW_SURFACES_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_vdc5.h"
+#include  "frame_buffer_typedef.h"
+#include  "RGA_Port_typedef.h"
+#ifdef  IS_WINDOW_SURFACES_EX
+#include  "window_surfaces_ex_typedef.h"
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   background_format_t
+* @brief  background_format_t
+*
+*    - BACKGROUND_FORMAT_SOLID_COLOR - 0
+*    - BACKGROUND_FORMAT_VIDEO_INTERLACE - 1
+*/
+enum st_background_format_t {
+    BACKGROUND_FORMAT_SOLID_COLOR,
+    BACKGROUND_FORMAT_VIDEO_INTERLACE
+};
+typedef enum st_background_format_t  background_format_t;
+/* "typedef" must be after "enum". Because GCC_ARM raises an error */
+
+
+/**
+* @struct  window_surfaces_vdc5_layer_t
+* @brief  VDC5 layer
+*/
+typedef struct st_window_surfaces_vdc5_layer_t  window_surfaces_vdc5_layer_t;
+struct st_window_surfaces_vdc5_layer_t {
+
+    /*-----------------------------------------------------------*/
+    /* Group: Layer */
+
+    /** layer_num */
+    int8_t  layer_num;
+
+    /** graphics_layer_ID */
+    vdc5_graphics_type_t  graphics_layer_ID;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Data Control */
+
+    /** is_data_control */
+    bool_t  is_data_control;
+
+    /** data_control_ID */
+    vdc5_layer_id_t  data_control_ID;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Color Format */
+
+    /** vdc5_format */
+    vdc5_gr_format_t  vdc5_format;
+
+    /** layer_color */
+    r8g8b8a8_t  layer_color;
+};
+
+
+/**
+* @struct  window_surfaces_t
+* @brief  window_surfaces_t
+*/
+typedef struct st_window_surfaces_t  window_surfaces_t;
+#define   WINDOW_SURFACES_T_MAX_LAYERS_COUNT   3
+
+struct st_window_surfaces_t {
+    /** Index is 0 .. (layer_num_max + background_frame_count) */
+    frame_buffer_t  frame_buffers[ WINDOW_SURFACES_T_MAX_LAYERS_COUNT ];
+
+    /** screen_channel */
+    vdc5_channel_t  screen_channel;
+
+    /** layer_num_min */
+    int8_t  layer_num_min;
+
+    /** layer_num_max */
+    int8_t  layer_num_max;
+
+    /** layers */
+    window_surfaces_vdc5_layer_t  layers[ WINDOW_SURFACES_T_MAX_LAYERS_COUNT ];
+
+    /** attributes */
+#ifdef  IS_WINDOW_SURFACES_EX
+    window_surfaces_attribute_t   attributes[ WINDOW_SURFACES_T_MAX_LAYERS_COUNT ];
+#endif
+
+    /** vdc5_disp_sel_array */
+    vdc5_gr_disp_sel_t   vdc5_disp_sel_array[ VDC5_GR_TYPE_NUM ];
+
+    /** background_format */
+    background_format_t  background_format;
+
+    /** background_frame_count */
+    int_fast32_t   background_frame_count;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: VRAM */
+
+    /** start_of_VRAM */
+    uint8_t  *start_of_VRAM;
+
+    /** over_of_VRAM */
+    uint8_t  *over_of_VRAM;
+
+    /** stack_pointer_of_VRAM */
+    uint8_t  *stack_pointer_of_VRAM;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: State */
+
+    /** is_initialized */
+    bool_t  is_initialized;  /* For reduce loading */
+};
+
+
+/**
+* @struct  window_surfaces_config_t
+* @brief  window_surfaces_config_t
+*/
+typedef struct st_window_surfaces_config_t  window_surfaces_config_t;
+struct st_window_surfaces_config_t {
+    /** 0 | F_WINDOW_SURFACES_PIXEL_FORMAT | ... */
+    bit_flags_fast32_t  flags;
+
+    /** pixel_format */
+    pixel_format_t  pixel_format;
+
+    /** layer_count */
+    int_fast32_t  layer_count;
+
+    /** buffer_height */
+    int_fast32_t  buffer_height;
+
+    /** background_color */
+    r8g8b8a8_t  background_color;
+
+    /** background_format */
+    background_format_t  background_format;
+};
+enum  /* "window_surfaces_config_t::flags" */
+{
+    F_WINDOW_SURFACES_PIXEL_FORMAT      = 0x08,
+    F_WINDOW_SURFACES_LAYER_COUNT       = 0x20,
+#define  F_WINDOW_SURFACES_BACKGROUND_COLOR    0x40u
+    F_WINDOW_SURFACES_BUFFER_HEIGHT     = 0x80,
+    F_WINDOW_SURFACES_BACKGROUND_FORMAT = 0x100
+};
+
+
+/***********************************************************************
+* Section: Global
+************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  WINDOW_SURFACES_DEFAULT_CHANNEL
+* @brief  0 or 1
+*/
+#define  WINDOW_SURFACES_DEFAULT_CHANNEL  0
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "frame_buffer.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/porting/RGA_Callback.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,258 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Callback.c
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#include  <string.h>
+#include  "RGA.h"
+#include  "RGA_Callback_private.h"
+#include  "clib_drivers.h"
+
+
+
+/** gs_WorkBufferMemory */
+static uint8_t  *gs_WorkBufferMemory;
+static size_t    gs_WorkBufferMemory_Size;
+static uint8_t  *gs_WorkBufferB_Memory;
+static size_t    gs_WorkBufferB_Memory_Size;
+
+
+/**
+* @struct  GraphicsDefaultSubClass
+* @brief  GraphicsDefaultSubClass
+*/
+typedef struct _GraphicsDefaultSubClass  GraphicsDefaultSubClass;
+struct _GraphicsDefaultSubClass {
+    uint8_t  *WorkBufferMemory;
+    size_t    work_buffer_size;
+    bool_t    IsUsedWorkBuffer;
+    uint8_t  *WorkBufferB_Memory;
+    size_t    work_buffer_b_size;
+    bool_t    IsUsedWorkBufferB;
+};
+
+
+/* Section: Global */
+/** gs_GraphicsDefaultSub */
+static  GraphicsDefaultSubClass  gs_GraphicsDefaultSub = {
+    NULL,      /* WorkBufferMemory */
+    0,         /* work_buffer_size */
+    false,     /* IsUsedWorkBuffer */
+    NULL,      /* WorkBufferB_Memory */
+    0,         /* work_buffer_b_size */
+    false,     /* IsUsedWorkBufferB */
+};
+
+
+
+/**
+* @brief   R_GRAPHICS_STATIC_OnInitializeDefault
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_GRAPHICS_STATIC_OnInitializeDefault( graphics_t *self, graphics_config_t *in_out_Config,
+        void **out_CalleeDefined )
+{
+    enum { work_buffer_flags =
+               F_GRAPHICS_WORK_BUFFER_ADDRESS |
+               F_GRAPHICS_WORK_BUFFER_SIZE |
+               F_GRAPHICS_MAX_WIDTH_OF_FRAME_BUFFER |
+               F_GRAPHICS_MAX_HEIGHT_OF_FRAME_BUFFER
+         };
+
+    enum { work_buffer_B_flags =
+               F_GRAPHICS_WORK_BUFFER_B_ADDRESS |
+               F_GRAPHICS_WORK_BUFFER_B_SIZE
+         };
+
+    static r_ospl_c_lock_t  gs_c_lock_object;
+
+    errnum_t  e;
+
+    GraphicsDefaultSubClass  *sub = &gs_GraphicsDefaultSub;
+
+    R_UNREFERENCED_VARIABLE_2( self, out_CalleeDefined );
+
+    R_MEMORY_SECTION_GetMemory_RGA_WorkBuffer( &gs_WorkBufferMemory, &gs_WorkBufferMemory_Size,
+            &gs_WorkBufferB_Memory, &gs_WorkBufferB_Memory_Size );
+
+
+    /* Set default configuration */
+
+    /* Use work buffer */
+    if ( IS_ANY_BITS_NOT_SET( in_out_Config->flags, work_buffer_flags ) ) {
+        ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Config->flags, work_buffer_flags ),  e=E_OTHERS; goto fin );
+        ASSERT_R( ! sub->IsUsedWorkBuffer,  e=E_OTHERS; goto fin );
+
+#if  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT == 64  /* Check of "R_Ceil_64u" */
+        sub->WorkBufferMemory = (uint8_t *) R_Ceil_64u( (uintptr_t) gs_WorkBufferMemory );
+#elif  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT == 4  /* Check of "R_Ceil_4u" */
+        sub->WorkBufferMemory = (uint8_t *) R_Ceil_4u( (uintptr_t) gs_WorkBufferMemory );
+#else
+#error
+#endif
+        sub->work_buffer_size = gs_WorkBufferMemory_Size - ( sub->WorkBufferMemory - gs_WorkBufferMemory );
+
+        in_out_Config->flags |= work_buffer_flags;
+        in_out_Config->work_buffer_address = sub->WorkBufferMemory;
+        in_out_Config->work_buffer_size    = sub->work_buffer_size;
+        in_out_Config->max_width_of_frame_buffer = MAX_WIDTH_OF_FRAME_BUFFER;
+        in_out_Config->max_height_of_frame_buffer = MAX_HEIGHT_OF_FRAME_BUFFER;
+
+        sub->IsUsedWorkBuffer = true;
+    }
+
+    /* Use work buffer B */
+    if ( IS_ANY_BITS_NOT_SET( in_out_Config->flags, work_buffer_B_flags ) ) {
+        ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Config->flags, work_buffer_B_flags ),  e=E_OTHERS; goto fin );
+        ASSERT_R( ! sub->IsUsedWorkBufferB,  e=E_OTHERS; goto fin );
+
+#if  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT == 32  /* Check of "R_Ceil_32u" */
+        sub->WorkBufferB_Memory = (uint8_t *) R_Ceil_32u( (uintptr_t) gs_WorkBufferB_Memory );
+#elif  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT == 4  /* Check of "R_Ceil_4u" */
+        sub->WorkBufferB_Memory = (uint8_t *) R_Ceil_4u( (uintptr_t) gs_WorkBufferB_Memory );
+#else
+#error
+#endif
+        sub->work_buffer_b_size = gs_WorkBufferB_Memory_Size - ( sub->WorkBufferB_Memory - gs_WorkBufferB_Memory );
+
+        in_out_Config->flags |= work_buffer_B_flags;
+        in_out_Config->work_buffer_b_address = sub->WorkBufferB_Memory;
+        in_out_Config->work_buffer_b_size    = sub->work_buffer_b_size;
+
+        sub->IsUsedWorkBufferB = true;
+    }
+
+#ifdef  WORK_SIZE_FOR_LIB_PNG
+    in_out_Config->flags |= F_GRAPHICS_WORK_SIZE_FOR_LIBPNG;
+    in_out_Config->work_size_for_libPNG = WORK_SIZE_FOR_LIB_PNG;
+#endif
+
+    R_OSPL_MEMORY_Flush( R_OSPL_FLUSH_WRITEBACK_INVALIDATE );
+    /* Avoid write back by initialization to global variables of buffers */
+
+    /* Lock object */
+    in_out_Config->flags |= F_GRAPHICS_LOCK_OBJECT;
+    in_out_Config->lock_object = &gs_c_lock_object;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+
+/**
+* @brief   R_GRAPHICS_STATIC_OnFinalizeDefault
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_GRAPHICS_STATIC_OnFinalizeDefault( graphics_t *self, void *CalleeDefined, errnum_t e )
+{
+    GraphicsDefaultSubClass  *sub = &gs_GraphicsDefaultSub;
+
+    R_UNREFERENCED_VARIABLE_2( self, CalleeDefined );
+    sub->IsUsedWorkBuffer  = false;
+    sub->IsUsedWorkBufferB = false;
+    return  e;
+}
+
+
+/**
+* @brief   drawCLUTImage
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t drawCLUTImage( uint8_t *SrcAddress, const graphics_image_t *image, frame_buffer_t *frame )
+{
+    errnum_t e;
+    int_t image_w;
+    int i;
+    uint32_t ImageWidthPoint;
+    uint8_t *DestAddress;
+    graphics_image_properties_t  image_prop;
+
+    DestAddress = frame->buffer_address[ frame->draw_buffer_index ];
+
+    switch( frame->pixel_format ) {
+        case PIXEL_FORMAT_CLUT8:
+            ImageWidthPoint = 1;
+            break;
+        case PIXEL_FORMAT_CLUT4:
+            ImageWidthPoint = 2;
+            break;
+        case PIXEL_FORMAT_CLUT1:
+            ImageWidthPoint = 8;
+            break;
+        default:
+            /* never comes here */
+            ImageWidthPoint = 1;
+            break;
+    }
+
+    e = R_GRAPHICS_IMAGE_GetProperties( image, &image_prop );
+    IF(e)goto fin;
+    ASSERT_R( image_prop.pixelFormat == frame->pixel_format , e=E_NOT_SUPPORTED_PIXEL_FORMAT; goto fin );
+    ASSERT_R( ( image->width % ImageWidthPoint ) == 0 , e=E_OTHERS; goto fin );
+    ASSERT_R( image->width <= frame->width , e=E_OTHERS; goto fin );
+    ASSERT_R( image->height <= frame->height , e=E_OTHERS; goto fin );
+    ASSERT_R( frame->stride % 32 == 0 , e=E_OTHERS; goto fin );
+
+    image_w = image_prop.width;
+    switch( frame->pixel_format ) {
+        case PIXEL_FORMAT_CLUT8:
+            SrcAddress += sizeof( uint32_t ) * 256;
+            break;
+        case PIXEL_FORMAT_CLUT4:
+            image_w = image_w / 2;
+            SrcAddress += sizeof( uint32_t ) * 16;
+            break;
+        case PIXEL_FORMAT_CLUT1:
+            image_w = image_w / 8;
+            SrcAddress += sizeof( uint32_t ) * 2;
+            break;
+        default:
+            e=E_OTHERS;
+            goto fin;
+    }
+    for( i = 0; i < image->height ; i++ ) {
+        memcpy(( void *) DestAddress, ( void *)SrcAddress, (size_t)image_w );
+        DestAddress += frame->stride;
+        SrcAddress += image_w;
+    }
+    e = 0;
+fin:
+    return e;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/porting/RGA_Callback_WorkBuf.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,75 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Callback_WorkBuf.c
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#include  <string.h>
+#include  "RGA.h"
+#include  "RGA_Callback_private.h"
+
+
+/** gs_WorkBufferMemory */
+
+/* <MapSection attribute="Uncachable"/> */
+/* .WORK_SECTION1 is for only R_REE_INIT. This is ignored in other environments. */
+#if defined(__ICCARM__)
+R_OSPL_ALIGNMENT( 16,
+                  R_OSPL_SECTION_FOR_ZERO_INIT( ".mirrorram",
+                          static uint8_t  gs_WorkBufferMemory[ WORK_BUFFER_SIZE ] ));
+#else
+R_OSPL_ALIGNMENT( RGA_WORK_BUFFER_ADDRESS_ALIGNMENT,
+                  R_OSPL_SECTION_FOR_ZERO_INIT( "NC_BSS",
+                          static uint8_t  gs_WorkBufferMemory[ WORK_BUFFER_SIZE ] ));
+#endif
+
+
+/** gs_WorkBufferB_Memory */
+
+R_OSPL_ALIGNMENT( RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT,
+                  static uint8_t  gs_WorkBufferB_Memory[ WORK_BUFFER_B_SIZE ] );
+
+
+/**
+* @brief   Get Memory of RGA WorkBuffer
+*
+* @param   out_WorkBufferAddress uint8_t*
+* @param   out_WorkBufferSize size_t
+* @param   out_WorkBufferB_Address uint8_t*
+* @param   out_WorkBufferB_Size size_t
+* @return  None
+*/
+void  R_MEMORY_SECTION_GetMemory_RGA_WorkBuffer(
+    uint8_t **out_WorkBufferAddress,  size_t *out_WorkBufferSize,
+    uint8_t **out_WorkBufferB_Address,  size_t *out_WorkBufferB_Size )
+{
+    *out_WorkBufferAddress = gs_WorkBufferMemory;
+    *out_WorkBufferSize = sizeof( gs_WorkBufferMemory );
+    *out_WorkBufferB_Address = gs_WorkBufferB_Memory;
+    *out_WorkBufferB_Size = sizeof( gs_WorkBufferB_Memory );
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/porting/RGA_Callback_private.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,66 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Callback_private.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#include  "r_typedefs.h"
+#include  "RGA_Port_typedef.h"
+#if MBED_CONF_APP_EASY_ATTACH_LINK
+#include  "EasyAttach_CameraAndLCD.h"
+#endif
+
+#ifdef  RZ_A1L  /* Reduce working buffer size for LibPNG */
+#define  WORK_SIZE_FOR_LIB_PNG   0x10000
+#endif
+
+enum {
+#if MBED_CONF_APP_EASY_ATTACH_LINK
+    MAX_WIDTH_OF_FRAME_BUFFER  = LCD_PIXEL_WIDTH,
+    MAX_HEIGHT_OF_FRAME_BUFFER = LCD_PIXEL_HEIGHT,
+#else
+    MAX_WIDTH_OF_FRAME_BUFFER  = 1280,
+    MAX_HEIGHT_OF_FRAME_BUFFER = 720,
+#endif
+
+    WORK_BUFFER_SIZE = R_RGA_CalcWorkBufferSize2(
+                           MAX_WIDTH_OF_FRAME_BUFFER, MAX_HEIGHT_OF_FRAME_BUFFER ),
+
+#ifdef  WORK_SIZE_FOR_LIB_PNG
+    WORK_BUFFER_B_SIZE = R_RGA_CalcWorkBufferB_Size(
+                             MAX_WIDTH_OF_FRAME_BUFFER, MAX_HEIGHT_OF_FRAME_BUFFER, 4 ) +
+                         WORK_SIZE_FOR_LIB_PNG
+#else
+    WORK_BUFFER_B_SIZE = R_RGA_CalcWorkBufferB_Size(
+                             MAX_WIDTH_OF_FRAME_BUFFER, MAX_HEIGHT_OF_FRAME_BUFFER, 4 ) +
+                         RGA_MAX_WORK_SIZE_FOR_LIB_PNG_DEFAULT
+#endif
+};
+
+void  R_MEMORY_SECTION_GetMemory_RGA_WorkBuffer(
+    uint8_t **out_WorkBufferAddress,  size_t *out_WorkBufferSize,
+    uint8_t **out_WorkBufferB_Address,  size_t *out_WorkBufferB_Size );
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/porting/RGA_VRAM.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,74 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: RGA_VRAM.c $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 40 $
+* $Date:: 2013-12-18 20:02:45 +0900#$
+* Description : Sample functions
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+#if ! IS_VDC_SAMPLE_VRAM_USED
+
+/* <MapSection attribute="Uncached"/> */
+R_OSPL_SECTION_FOR_ZERO_INIT( "VRAM",
+                              static uint8_t gs_FrameBufferMemory[ 0x00300000 ] );
+
+void  R_MEMORY_SECTION_GetMemory_ClibSamplesC( uint8_t **out_Address,  size_t *out_Size )
+{
+    *out_Address = gs_FrameBufferMemory;
+    *out_Size = sizeof( gs_FrameBufferMemory );
+}
+
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/porting/RGA_VRAM_EX.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,82 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_VRAM_EX.c
+* @brief   External VRAM Area
+*
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "window_surfaces_private.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/** gs_VRAM_Ex */
+/* <MapSection attribute="SDRAM_Cached"/> */
+R_OSPL_ALIGNMENT( RGA_STACK_ADDRESS_ALIGNMENT,
+                  R_OSPL_SECTION_FOR_ZERO_INIT( "VRAM_EX",
+                          static uint8_t gs_VRAM_Ex[ 0x00500000 ] ));
+
+
+/**
+* @brief   R_EXRAM_GetBigMemory
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_EXRAM_GetBigMemory( void * /*<type**>*/ out_Address,  size_t *out_Size )
+{
+    *(void **) out_Address = gs_VRAM_Ex;
+    *out_Size = sizeof( gs_VRAM_Ex );
+    return  0;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/porting/vsync_pl.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,410 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync_pl.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 44 $
+* $Date:: 2013-12-20 11:20:00 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "r_ospl.h"
+#include  "r_vdc5.h"
+#include  "vsync.h"
+#include  "vsync_pl.h"
+
+#if ! R_OSPL_IS_PREEMPTION
+#include  "dev_drv.h"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+typedef void (* gs_rtx_interrupt_t )(void);  /* RTX */
+typedef void (* gs_cint_interrupt_t )( uint32_t int_sense );  /* OS less INTC */
+typedef void (* gs_vdc_interrupt_t )( vdc5_int_type_t int_type );
+
+typedef struct st_r_v_sync_pl_channel_t  r_v_sync_pl_channel_t;
+struct st_r_v_sync_pl_channel_t {
+    const r_ospl_caller_t             *InterruptCallbackCaller;
+    bool_t                             IsVDC5_Callback;
+};
+
+static r_v_sync_pl_channel_t  gs_v_sync_pl_channel[ R_V_SYNC_CHANNEL_COUNT ];
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  GS_VSYNC_INTERRUPT_PRIORITY
+* @brief  GS_VSYNC_INTERRUPT_PRIORITY
+* @par Parameters
+*    None
+* @return  None.
+*/
+enum { GS_VSYNC_INTERRUPT_PRIORITY = 7 };
+
+
+/**
+* @def  GS_INTERRUPT_FUNCTION_TYPE
+* @brief  GS_INTERRUPT_FUNCTION_TYPE
+* @par Parameters
+*    None
+* @return  None.
+*
+*    - 0 : RTX
+*    - 1 : INTC
+*/
+#if R_OSPL_IS_PREEMPTION
+#define  GS_INTERRUPT_FUNCTION_TYPE  0
+#else
+#define  GS_INTERRUPT_FUNCTION_TYPE  1
+#endif
+
+
+/**
+* @typedef  gs_interrupt_t
+* @brief  Interrupt callback function type
+*/
+#if  GS_INTERRUPT_FUNCTION_TYPE == 0
+#define  gs_interrupt_t  gs_rtx_interrupt_t
+#else
+#define  gs_interrupt_t  gs_cint_interrupt_t
+#endif
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void  R_V_SYNC_IRQ_HandlerN( int_fast32_t const  ChannelNum );
+static void  R_V_SYNC_IRQ_Handler0( vdc5_int_type_t const  int_type );
+static void  R_V_SYNC_IRQ_Handler1( vdc5_int_type_t const  int_type );
+#if  GS_INTERRUPT_FUNCTION_TYPE != 1
+static gs_cint_interrupt_t  gs_cint_vdc5_interrupt_handler[2];
+static void  R_V_SYNC_IRQ_HandlerRoot0(void);
+static void  R_V_SYNC_IRQ_HandlerRoot1(void);
+#endif
+
+
+/** Table of interrupt line to channel number */
+static const r_ospl_interrupt_t  gs_array_of_i_context[ R_V_SYNC_CHANNEL_COUNT ] = {
+    { BSP_INT_SRC_GR3_VLINE0,  0 },
+    { BSP_INT_SRC_GR3_VLINE1,  1 }
+};
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_SetDefaultAsync
+************************************************************************/
+void  R_V_SYNC_SetDefaultAsync( r_ospl_async_t *const  Async,  r_ospl_async_type_t AsyncType )
+{
+    R_UNREFERENCED_VARIABLE( AsyncType );
+
+    IF_DQ( Async == NULL ) {
+        goto fin;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_Thread ) ) {
+        Async->A_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_EventValue ) ) {
+        Async->A_EventValue = R_OSPL_A_FLAG;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_Thread ) ) {
+        Async->I_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_EventValue ) ) {
+        Async->I_EventValue = R_OSPL_I_FLAG;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_InterruptCallback ) ) {
+        Async->InterruptCallback = (r_ospl_callback_t)&( R_V_SYNC_OnInterruptDefault );
+    }
+    /* MISRA 16.9 */
+
+    Async->Flags = R_F_OSPL_A_Thread | R_F_OSPL_A_EventValue |
+                   R_F_OSPL_I_Thread | R_F_OSPL_I_EventValue |
+                   R_F_OSPL_InterruptCallback | R_F_OSPL_Delegate;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnInitialize
+************************************************************************/
+errnum_t  R_V_SYNC_OnInitialize( int_fast32_t const  ChannelNum )
+{
+#if GS_INTERRUPT_FUNCTION_TYPE == 1
+    bsp_int_cb_t    handler;
+#endif
+    errnum_t       e;
+    vdc5_error_t   er;
+    bsp_int_err_t  eb;
+    bsp_int_src_t  int_id;
+    vdc5_int_t     interrupt;
+    r_v_sync_pl_channel_t *const     self = &gs_v_sync_pl_channel[ ChannelNum ];
+    const r_ospl_interrupt_t *const  i_context = &gs_array_of_i_context[ ChannelNum ];
+
+    /*[gs_IRQHandlers]*/
+    static const gs_vdc_interrupt_t  gs_IRQHandlers[ R_V_SYNC_CHANNEL_COUNT ] = {
+        &( R_V_SYNC_IRQ_Handler0 ), /* MISRA 16.9 */
+        &( R_V_SYNC_IRQ_Handler1 )
+    };
+
+#if  GS_INTERRUPT_FUNCTION_TYPE != 1
+    /*[gs_IRQHandlerRoots]*/
+    static const gs_interrupt_t  gs_IRQHandlerRoots[ R_V_SYNC_CHANNEL_COUNT ] = {
+        &( R_V_SYNC_IRQ_HandlerRoot0 ), /* MISRA 16.9 */
+        &( R_V_SYNC_IRQ_HandlerRoot1 )
+    };
+#endif
+
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->InterruptCallbackCaller = NULL;
+
+    int_id  = i_context->IRQ_Num;
+#if GS_INTERRUPT_FUNCTION_TYPE == 1
+    handler = R_VDC5_GetISR( (vdc5_channel_t) ChannelNum, VDC5_INT_TYPE_VLINE );
+    eb= R_BSP_InterruptWrite( int_id, handler );
+#else
+    gs_cint_vdc5_interrupt_handler[ChannelNum] = R_VDC5_GetISR(
+                (vdc5_channel_t) ChannelNum, VDC5_INT_TYPE_VLINE );
+    eb= R_BSP_InterruptWrite( int_id, gs_IRQHandlerRoots[ChannelNum] );
+#endif
+    IF ( eb != BSP_INT_SUCCESS ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_OSPL_SetInterruptPriority( int_id, GS_VSYNC_INTERRUPT_PRIORITY );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+    interrupt.type     = VDC5_INT_TYPE_VLINE;
+    interrupt.callback = gs_IRQHandlers[ ChannelNum ];
+    interrupt.line_num = (uint16_t) 0;
+
+    er = R_VDC5_CallbackISR( (vdc5_channel_t) ChannelNum, &interrupt );
+    IF ( er != VDC5_OK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->IsVDC5_Callback = true;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnFinalize
+************************************************************************/
+errnum_t  R_V_SYNC_OnFinalize( int_fast32_t const  ChannelNum,  errnum_t e )
+{
+    r_v_sync_pl_channel_t *const  self = &gs_v_sync_pl_channel[ ChannelNum ];
+
+    if ( (ChannelNum >= 0) && (ChannelNum < R_V_SYNC_CHANNEL_COUNT) ) {
+        if ( IS( self->IsVDC5_Callback ) ) {
+            vdc5_error_t  er;
+            vdc5_int_t    interrupt;
+
+            interrupt.type     = VDC5_INT_TYPE_VLINE;
+            interrupt.callback = NULL;
+            interrupt.line_num = (uint16_t) 0;
+
+            er = R_VDC5_CallbackISR( (vdc5_channel_t) ChannelNum, &interrupt );
+            IF ( (er != VDC5_OK) && (e == 0) ) {
+                e=E_OTHERS;
+            }
+
+            self->IsVDC5_Callback = false;
+        }
+    }
+
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_SetInterruptCallbackCaller
+************************************************************************/
+errnum_t  R_V_SYNC_SetInterruptCallbackCaller( int_fast32_t const  ChannelNum,
+        const r_ospl_caller_t *const  Caller )
+{
+    r_v_sync_pl_channel_t *const  self = &gs_v_sync_pl_channel[ ChannelNum ];
+
+    self->InterruptCallbackCaller = Caller;
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnEnableInterrupt
+************************************************************************/
+void  R_V_SYNC_OnEnableInterrupt( int_fast32_t const  ChannelNum,
+                                  r_v_sync_interrupt_lines_t const  Enables )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Enables, R_V_SYNC_INTERRUPT_LINE_V_LINE ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_array_of_i_context[ ChannelNum ].IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnDisableInterrupt
+************************************************************************/
+void  R_V_SYNC_OnDisableInterrupt( int_fast32_t const  ChannelNum,
+                                   r_v_sync_interrupt_lines_t const  Disables1 )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Disables1, R_V_SYNC_INTERRUPT_LINE_V_LINE ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_array_of_i_context[ ChannelNum ].IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnInterruptDefault
+************************************************************************/
+errnum_t  R_V_SYNC_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                       const r_ospl_caller_t *const  Caller )
+{
+    R_UNREFERENCED_VARIABLE( Caller );
+
+    return  R_V_SYNC_OnInterrupting( InterruptSource );
+}
+
+
+/**
+* @brief   Interrupt service routine for all channels
+*
+* @param   ChannelNum ChannelNum
+* @return  None
+*/
+static void  R_V_SYNC_IRQ_HandlerN( int_fast32_t const  ChannelNum )
+{
+    r_v_sync_pl_channel_t *const     self = &gs_v_sync_pl_channel[ ChannelNum ];
+    const r_ospl_interrupt_t *const  i_context = &gs_array_of_i_context[ ChannelNum ];
+
+    /* V-Sync interrupt always be enabled. Because clear interrupt status */
+
+    if ( self->InterruptCallbackCaller != NULL ) {
+        R_OSPL_CallInterruptCallback( self->InterruptCallbackCaller, i_context );
+    }
+}
+
+
+/**
+* @brief   Interrupt service routine for INTC channel 0
+*
+* @param   int_type ignored
+* @return  None
+*/
+static void  R_V_SYNC_IRQ_Handler0( vdc5_int_type_t const  int_type )
+{
+    R_UNREFERENCED_VARIABLE( int_type );
+    R_V_SYNC_IRQ_HandlerN( 0 );
+}
+
+
+/**
+* @brief   Interrupt service routine for INTC channel 1
+*
+* @param   int_type ignored
+* @return  None
+*/
+static void  R_V_SYNC_IRQ_Handler1( vdc5_int_type_t const  int_type )
+{
+    R_UNREFERENCED_VARIABLE( int_type );
+    R_V_SYNC_IRQ_HandlerN( 1 );
+}
+
+
+/**
+* @brief   Interrupt service routine for RTX channel 0
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+#if GS_INTERRUPT_FUNCTION_TYPE != 1
+static void  R_V_SYNC_IRQ_HandlerRoot0(void)
+{
+    gs_cint_vdc5_interrupt_handler[0]( 0 );
+}
+#endif
+
+
+/**
+* @brief   Interrupt service routine for RTX channel 1
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+#if GS_INTERRUPT_FUNCTION_TYPE != 1
+static void  R_V_SYNC_IRQ_HandlerRoot1(void)
+{
+    gs_cint_vdc5_interrupt_handler[1]( 0 );
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/src/video_input.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,901 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input.c
+* @brief   $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+#include  "video_input.h"
+#include  "video_decoder.h"
+#include  "window_surfaces_typedef.h"  /* WINDOW_SURFACES_DEFAULT_CHANNEL */
+#ifndef R_OSPL_NDEBUG
+#include  <stdio.h>
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  video_input_vdc5_layer_t
+* @brief  video_input_vdc5_layer_t
+*/
+typedef struct st_video_input_vdc5_layer_t  video_input_vdc5_layer_t;
+struct st_video_input_vdc5_layer_t {
+    bool_t                is_data_control;
+    vdc5_layer_id_t       data_control_ID;
+};
+
+
+/**
+* @typedef  vdc5_int_cb_t
+* @brief  vdc5_int_cb_t
+*/
+typedef  void (* vdc5_int_cb_t )( const uint32_t );
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define VSYNC_1_2_FH_TIMING  (858u) /* Vsync signal 1/2fH phase timing */
+#define VSYNC_1_4_FH_TIMING  (429u) /* Vsync signal 1/4fH phase timing */
+
+#define     IMGCAP_SIZE_NTSC_HS         (122u * 2u)
+#define     IMGCAP_SIZE_NTSC_HW         (720u * 2u)
+#define     IMGCAP_SIZE_NTSC_VS         (16u)
+#define     IMGCAP_SIZE_NTSC_VW         (480u/2u)
+
+#define     IMGCAP_SIZE_PAL_HS          (132u * 2u)
+#define     IMGCAP_SIZE_PAL_HW          (720u * 2u)
+#define     IMGCAP_SIZE_PAL_VS          (19u)
+#define     IMGCAP_SIZE_PAL_VW          (560u/2u)
+
+#define     VIDEO_FORMAT                (VDC5_RES_MD_YCBCR422)
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void  R_VIDEO_INPUT_OnVideoInVSync( vdc5_channel_t  video_input_channel,  vdc5_int_type_t int_type );
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch0( vdc5_int_type_t int_type );
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch1( vdc5_int_type_t int_type );
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S0_VI_VSYNC0(void);
+static void  InterruptCallbackVector_S0_VI_VSYNC1(void);
+static void  InterruptCallbackVector_S1_VI_VSYNC0(void);
+static void  InterruptCallbackVector_S1_VI_VSYNC1(void);
+vdc5_int_cb_t  gs_VDC5_ISR_S0_VI_VSYNC0;
+vdc5_int_cb_t  gs_VDC5_ISR_S0_VI_VSYNC1;
+vdc5_int_cb_t  gs_VDC5_ISR_S1_VI_VSYNC0;
+vdc5_int_cb_t  gs_VDC5_ISR_S1_VI_VSYNC1;
+#endif
+
+static video_input_t  *gs_InterruptToSelf[ 2 /* video_input_channel */ ][ 2 /* data_control_ID */ ];
+
+static errnum_t  R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self );
+static errnum_t  R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self );
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfPointer(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t ***  out_self_pp );
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_int_type_t  in_interrupt,
+    video_input_t  **out_self );
+
+
+/**
+* @brief   Initializes by constant data.
+*
+* @param   self video_input_t.
+* @return  None.
+*/
+void  R_VIDEO_INPUT_InitConst( video_input_t *const  self )
+{
+    self->is_data_control = false;
+    self->is_vsync_interrupt_registered[0] = false;
+    self->is_vsync_interrupt_registered[1] = false;
+    self->is_vsync_interrupt_registered[2] = false;
+}
+
+
+/***********************************************************************
+* Implement: R_VIDEO_INPUT_Initialize
+************************************************************************/
+errnum_t  R_VIDEO_INPUT_Initialize( video_input_t *const  self,
+                                    video_input_config_t *in_out_Config )
+{
+    errnum_t         e;
+    vdc5_error_t     e_vdc5;
+#ifdef  IS_MBED_USED
+    vdec_error_t     e_vdec;
+#endif
+    vdc5_write_t     writing_config;
+    frame_buffer_t  *frame;
+    uintptr_t        frame_physical_address[ R_COUNT_OF( frame->buffer_address ) ];
+
+
+    /* Initialize by constant */
+    ASSERT_R( ! self->is_data_control,  e=E_STATE; goto fin );
+    ASSERT_R( ! self->is_vsync_interrupt_registered[0],  e=E_STATE; goto fin );
+    ASSERT_R( ! self->is_vsync_interrupt_registered[1],  e=E_STATE; goto fin );
+    ASSERT_R( ! self->is_vsync_interrupt_registered[2],  e=E_STATE; goto fin );
+    self->captured_count = 0;
+
+
+    /* Check necessary flags */
+    {
+        enum { necessary_flags =
+                   VIDEO_INPUT_CONFIG_T_FRAME_BUFFER
+             };
+
+        ASSERT_R( IS_ALL_BITS_SET( in_out_Config->flags, necessary_flags ),
+                  e=E_OTHERS; goto fin );
+    }
+
+
+    /* Set "frame" */
+    {
+        int_fast32_t  i;
+
+        frame = in_out_Config->frame_buffer;
+        ASSERT_R( frame->buffer_count == 2,  e=E_OTHERS; goto fin );
+        self->frame_buffer = *frame;
+
+        for ( i = 0;  i < frame->buffer_count;  i += 1 ) {
+            e= R_OSPL_ToPhysicalAddress( frame->buffer_address[ i ],
+                                         &frame_physical_address[ i ] );
+            IF(e!=0) {
+                goto fin;
+            }
+        }
+    }
+
+
+    /* Set default "in_out_Config->video_input_channel_num" */
+    if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM ) ) {
+        in_out_Config->video_input_channel_num = WINDOW_SURFACES_DEFAULT_CHANNEL;
+    }
+
+
+    /* Set from "in_out_Config->video_input_channel_num" */
+    switch ( in_out_Config->video_input_channel_num ) {
+        case  0:
+            self->video_input_channel = VDC5_CHANNEL_0;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN1;
+            break;
+        case  1:
+            self->video_input_channel = VDC5_CHANNEL_1;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN1;
+            break;
+        case  2:
+            self->video_input_channel = VDC5_CHANNEL_0;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN2;
+            break;
+        case  3:
+            self->video_input_channel = VDC5_CHANNEL_1;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN2;
+            break;
+        default:
+            ASSERT_R( false,  e=E_OTHERS; goto fin );
+    }
+
+
+    /* Set default "in_out_Config->display_channel_num" */
+    if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM ) ) {
+        if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM ) ) {
+            in_out_Config->display_channel_num = VIDEO_INPUT_NOT_DISPLAY;
+        } else {
+            in_out_Config->display_channel_num = WINDOW_SURFACES_DEFAULT_CHANNEL;
+        }
+    }
+
+
+    /* Set default "in_out_Config->display_layer_num" */
+    if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM ) ) {
+        if ( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY ) {
+            in_out_Config->display_layer_num = VIDEO_INPUT_NOT_DISPLAY;
+        } else {
+            in_out_Config->display_layer_num = -1;
+        }
+    }
+    ASSERT_D( in_out_Config->display_layer_num == VIDEO_INPUT_NOT_DISPLAY  ||
+              in_out_Config->display_layer_num <= -1,  e=E_OTHERS; goto fin );
+    ASSERT_D(
+        ( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY  &&
+          in_out_Config->display_layer_num   == VIDEO_INPUT_NOT_DISPLAY ) ||
+        ( in_out_Config->display_channel_num != VIDEO_INPUT_NOT_DISPLAY  &&
+          in_out_Config->display_layer_num   != VIDEO_INPUT_NOT_DISPLAY ),
+        e=E_OTHERS; goto fin );
+
+
+    /* Set "self->data_control_ID" : No care of "display_layer_num" */
+    if ( in_out_Config->display_channel_num == 0 ) {
+        if ( self->video_input_channel == 0 ) {
+            self->data_control_ID = VDC5_LAYER_ID_0_WR;
+        } else {
+            self->data_control_ID = VDC5_LAYER_ID_1_WR;
+        }
+    } else if ( in_out_Config->display_channel_num == 1 ) {
+        if ( self->video_input_channel == 0 ) {
+            self->data_control_ID = VDC5_LAYER_ID_1_WR;
+        } else {
+            self->data_control_ID = VDC5_LAYER_ID_0_WR;
+        }
+    } else {
+        ASSERT_D( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY,
+                  e=E_OTHERS; goto fin );
+
+        self->data_control_ID = VDC5_LAYER_ID_0_WR;
+    }
+
+
+    /* Set "self->captured_async" */
+    self->captured_async = NULL;
+    if ( IS_BIT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC ) ) {
+        self->captured_async = in_out_Config->captured_async;
+    }
+
+
+    /* From GRPDRV_Init() */
+    {
+        vdc5_input_t      input;
+
+        /* Input parameter */
+        input.inp_sel   = VDC5_INPUT_SEL_VDEC;           /* Input select */
+        input.inp_fh50  = (uint16_t)VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
+        input.inp_fh25  = (uint16_t)VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
+        input.dly       = NULL;                          /* Sync signal delay adjustment */
+        input.ext_sig   = NULL;                          /* External input signal */
+        e_vdc5 = R_VDC5_VideoInput( self->video_input_channel, &input );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+    }
+
+
+    /* ... */
+    {
+        vdec_channel_t           vdec_channel;  /* video decoder channel */
+#ifdef  IS_MBED_USED
+        graphics_col_sys_t       color_system = GRPH_COL_SYS_NTSC_358;
+#else
+        graphics_col_sys_t       color_system;
+#endif
+        vdc5_scalingdown_rot_t  *writing_scale = &writing_config.scalingdown_rot;
+
+
+        /* From SetVideoDecoder() */
+
+        if ( self->video_input_channel == VDC5_CHANNEL_0 ) {
+            vdec_channel = VDEC_CHANNEL_0;
+        } else {
+            ASSERT_R( self->video_input_channel == VDC5_CHANNEL_1,  e=E_OTHERS; goto fin );
+            vdec_channel = VDEC_CHANNEL_1;
+        }
+#ifdef  IS_MBED_USED
+        e_vdec = GRAPHICS_VideoDecoderInit( self->video_input_select, vdec_channel, color_system );
+        IF ( e_vdec != VDEC_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+#else
+        color_system = GRAPHICS_VideoDecoderInit( self->video_input_select, vdec_channel );
+        if ( color_system == GRPH_COL_SYS_UNKNOWN ) {
+            color_system = GRPH_COL_SYS_NTSC_358;
+        }
+#endif
+
+
+        /* From GRPDRV_VideoCreateNonDispSurface() */
+
+        /* Image area to be captured */
+#if  VIDEO_FORMAT_TYPE == VIDEO_FORMAT_TYPE_NTSC
+        ASSERT_R( (color_system == GRPH_COL_SYS_NTSC_358) ||
+                  (color_system == GRPH_COL_SYS_NTSC_443),
+                  e=E_OTHERS; goto fin );
+
+        writing_scale->res.vs = (uint16_t)( IMGCAP_SIZE_NTSC_VS - 1 );
+        writing_scale->res.vw = (uint16_t)IMGCAP_SIZE_NTSC_VW;
+        writing_scale->res.hs = (uint16_t)IMGCAP_SIZE_NTSC_HS;
+        writing_scale->res.hw = (uint16_t)IMGCAP_SIZE_NTSC_HW;
+        /* v = vertical, h = horizontal, s = start, w = width */
+#elif  VIDEO_FORMAT_TYPE == VIDEO_FORMAT_TYPE_PAL
+        ASSERT_R( (color_system != GRPH_COL_SYS_NTSC_358) &&
+                  (color_system != GRPH_COL_SYS_NTSC_443),
+                  e=E_OTHERS; goto fin );
+
+        writing_scale->res.vs = (uint16_t)( IMGCAP_SIZE_PAL_VS - 1 );
+        writing_scale->res.vw = (uint16_t)IMGCAP_SIZE_PAL_VW;
+        writing_scale->res.hs = (uint16_t)IMGCAP_SIZE_PAL_HS;
+        writing_scale->res.hw = (uint16_t)IMGCAP_SIZE_PAL_HW;
+#else
+#error
+#endif
+
+
+        /* Write data parameter */
+        writing_scale->res_pfil_sel = VDC5_ON;
+        /* Prefilter mode select for brightness signals (on/off) */
+
+        writing_scale->res_out_vw   = frame->height / 2;
+        /* Number of valid lines in vertical direction */
+        /* output by scaling-down control block */
+
+        writing_scale->res_out_hw   = frame->width;
+        /* Number of valid horizontal pixels */
+        /* output by scaling-down control block */
+
+        writing_scale->adj_sel      = VDC5_ON;
+        /* Measures to decrease the influence */
+        /* by lack of last-input line (on/off) */
+
+        writing_scale->res_ds_wr_md = VDC5_WR_MD_NORMAL;
+        /* Frame buffer writing mode */
+    }
+
+
+    /* From GRPDRV_VideoCreateNonDispSurface() */
+    {
+        writing_config.res_wrswa     = VDC5_WR_RD_WRSWA_16BIT;
+        /* Frame buffer swap setting */
+
+        writing_config.res_md        = VIDEO_FORMAT;
+        /* Frame buffer video-signal writing format */
+
+        writing_config.res_bst_md    = VDC5_BST_MD_32BYTE;
+        /* Transfer burst length for frame buffer */
+
+        writing_config.res_inter     = VDC5_RES_INTER_INTERLACE;
+        /* Field operating mode select */
+
+        writing_config.res_fs_rate   = VDC5_RES_FS_RATE_PER1;
+        /* Writing rate */
+
+        writing_config.res_fld_sel   = VDC5_RES_FLD_SEL_TOP;
+        /* Write field select */
+
+        writing_config.res_dth_on    = VDC5_ON;
+        /* Dither correction on/off */
+
+        writing_config.base          = (void *) frame_physical_address[0];
+        /* Frame buffer base address */
+
+        writing_config.ln_off        = frame->stride;
+        /* Frame buffer line offset address [byte] */
+
+        writing_config.flm_num       = (uint32_t)( frame->buffer_count - 1u );
+        /* Number of frames of buffer (res_flm_num + 1) */
+
+        writing_config.flm_off       = frame_physical_address[1] - frame_physical_address[0];
+
+        writing_config.btm_base      = NULL;
+        /* Frame buffer base address for bottom */
+
+
+        e_vdc5 = R_VDC5_WriteDataControl( self->video_input_channel,
+                                          self->data_control_ID,  &writing_config );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+
+        self->is_data_control = true;
+    }
+
+
+    {
+        vdc5_start_t  start;
+
+        e_vdc5 = R_VDC5_StartProcess( self->video_input_channel, self->data_control_ID, &start );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e = E_OTHERS;
+            goto fin;
+        }
+
+        /* This module does not call "R_VDC5_StartProcess" function for reading (showing). */
+    }
+
+
+    {
+        vdc5_int_t     *config = &self->interrupt_for_VDC5;
+        bsp_int_err_t   ret_b;
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+        vdc5_int_cb_t  *p_VDC5_ISR;
+#endif
+
+        e= R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
+               self->video_input_channel, self->data_control_ID, self );
+        IF(e) {
+            goto fin;
+        }
+
+        self->is_vsync_interrupt_registered[2] = true;
+
+
+        if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
+            config->type = VDC5_INT_TYPE_S0_VI_VSYNC;
+        } else {
+            config->type = VDC5_INT_TYPE_S1_VI_VSYNC;
+        }
+        if ( self->video_input_channel == 0 ) {
+            config->callback = R_VIDEO_INPUT_OnVideoInVSync_Ch0;
+
+            if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
+                self->interrupt_ID = BSP_INT_SRC_S0_VI_VSYNC0;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S0_VI_VSYNC0;
+                self->interrupt_vector = InterruptCallbackVector_S0_VI_VSYNC0;
+#endif
+            } else {
+                self->interrupt_ID = BSP_INT_SRC_S1_VI_VSYNC0;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S1_VI_VSYNC0;
+                self->interrupt_vector = InterruptCallbackVector_S1_VI_VSYNC0;
+#endif
+            }
+        } else {
+            config->callback = R_VIDEO_INPUT_OnVideoInVSync_Ch1;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+            if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
+                self->interrupt_ID = BSP_INT_SRC_S0_VI_VSYNC1;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S0_VI_VSYNC1;
+                self->interrupt_vector = InterruptCallbackVector_S0_VI_VSYNC1;
+#endif
+            } else {
+                self->interrupt_ID = BSP_INT_SRC_S1_VI_VSYNC1;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S1_VI_VSYNC1;
+                self->interrupt_vector = InterruptCallbackVector_S1_VI_VSYNC1;
+#endif
+            }
+#endif
+        }
+        config->line_num = 0;
+
+        e_vdc5 = R_VDC5_CallbackISR( self->video_input_channel, config );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+
+        self->is_vsync_interrupt_registered[1] = true;
+
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_LESS
+        {
+            vdc5_int_cb_t  a_VDC5_ISR;
+
+            a_VDC5_ISR = R_VDC5_GetISR( self->video_input_channel, config->type );
+            ret_b = R_BSP_InterruptWrite( self->interrupt_ID, a_VDC5_ISR );
+            IF ( ret_b != BSP_INT_SUCCESS ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+#else
+        *p_VDC5_ISR = R_VDC5_GetISR( self->video_input_channel, config->type );
+        ret_b = R_BSP_InterruptWrite( self->interrupt_ID, self->interrupt_vector );
+        IF ( ret_b != BSP_INT_SUCCESS ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+#endif
+
+        self->is_vsync_interrupt_registered[0] = true;
+    }
+
+
+#ifndef R_OSPL_NDEBUG
+    printf( "VideoInput %dx%dx%dx%d stride=%d \n address[0]=0x%08X address[1]=0x%08X\n",
+            frame->buffer_count, frame->width, frame->height, frame->byte_per_pixel,
+            frame->stride,
+            (uintptr_t) frame->buffer_address[0],
+            (uintptr_t) frame->buffer_address[1] );
+    /* Cast of "uintptr_t" is for avoiding "format" warning of GNU_ARM */
+#endif
+
+
+    e=0;
+fin:
+    if ( e != 0 ) {
+        e= R_VIDEO_INPUT_Finalize( self, e );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_VIDEO_INPUT_Finalize
+************************************************************************/
+errnum_t  R_VIDEO_INPUT_Finalize( video_input_t *const  self, errnum_t e )
+{
+    errnum_t       ee;
+    vdc5_error_t   e_vdc5;
+    bsp_int_err_t  ret_b;
+
+    if ( self->is_vsync_interrupt_registered[0] ) {
+        ret_b = R_BSP_InterruptWrite( self->interrupt_ID, FIT_NO_FUNC );
+        IF ( ret_b != BSP_INT_SUCCESS ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        self->is_vsync_interrupt_registered[0] = false;
+    }
+
+
+    if ( self->is_vsync_interrupt_registered[1] ) {
+        vdc5_int_t  *config = &self->interrupt_for_VDC5;
+
+        config->callback = NULL;
+        config->line_num = 0;
+
+        e_vdc5 = R_VDC5_CallbackISR( self->video_input_channel, config );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        config->type = VDC5_INT_TYPE_NUM;  /* Not Used interrupt type */
+
+        self->is_vsync_interrupt_registered[1] = false;
+    }
+
+
+    if ( self->is_vsync_interrupt_registered[2] ) {
+        ee= R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
+                self->video_input_channel, self->data_control_ID, self );
+        e= R_OSPL_MergeErrNum( e, ee );
+
+        self->is_vsync_interrupt_registered[2] = false;
+    }
+
+
+    if ( self->is_data_control ) {
+        e_vdc5 = R_VDC5_StopProcess( self->video_input_channel,
+                                     self->data_control_ID );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        e_vdc5 = R_VDC5_ReleaseDataControl( self->video_input_channel,
+                                            self->data_control_ID );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        self->is_data_control = false;
+    }
+
+    return  e;
+}
+
+
+/**
+* @brief   Video input V-Sync interrupt handler.
+*
+* @param   channel_num channel_num.
+* @param   int_type vdc5_int_type_t.
+* @return  None.
+*/
+static void  R_VIDEO_INPUT_OnVideoInVSync( vdc5_channel_t  video_input_channel,  vdc5_int_type_t int_type )
+{
+    errnum_t        e;
+    video_input_t  *self = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt( video_input_channel,  int_type,  &self );
+    IF(e) {
+        R_NOOP();
+    }
+    else if (
+        int_type == VDC5_INT_TYPE_S0_VI_VSYNC  ||
+        int_type == VDC5_INT_TYPE_S1_VI_VSYNC  ||
+        int_type == VDC5_INT_TYPE_S0_WLINE  ||
+        int_type == VDC5_INT_TYPE_S1_WLINE ) {
+        if ( IS_BIT_SET( VDC51.SC0_SCL1_WR7, 0x00000001u ) ) {
+            self->captured_buffer_index = 0;
+        } else {
+            self->captured_buffer_index = 1;
+        }
+
+        self->captured_count += 1;
+
+        if ( self->captured_async != NULL ) {
+            R_OSPL_EVENT_Set(
+                self->captured_async->A_Thread,
+                self->captured_async->A_EventValue );
+        }
+    }
+
+    R_DEBUG_BREAK_IF_ERROR();
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_OnVideoInVSync_Ch0
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch0( vdc5_int_type_t int_type )
+{
+    R_VIDEO_INPUT_OnVideoInVSync( VDC5_CHANNEL_0, int_type );
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_OnVideoInVSync_Ch1
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch1( vdc5_int_type_t int_type )
+{
+    R_VIDEO_INPUT_OnVideoInVSync( VDC5_CHANNEL_1, int_type );
+}
+
+
+/**
+* @brief   InterruptCallbackVector_S0_VI_VSYNC0
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S0_VI_VSYNC0(void)
+{
+    gs_VDC5_ISR_S0_VI_VSYNC0(0);
+}
+#endif
+
+
+/**
+* @brief   InterruptCallbackVector_S0_VI_VSYNC1
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S0_VI_VSYNC1(void)
+{
+    gs_VDC5_ISR_S0_VI_VSYNC1(0);
+}
+#endif
+
+
+/**
+* @brief   InterruptCallbackVector_S1_VI_VSYNC0
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S1_VI_VSYNC0(void)
+{
+    gs_VDC5_ISR_S1_VI_VSYNC0(0);
+}
+#endif
+
+
+/**
+* @brief   InterruptCallbackVector_S1_VI_VSYNC1
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S1_VI_VSYNC1(void)
+{
+    gs_VDC5_ISR_S1_VI_VSYNC1(0);
+}
+#endif
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt
+*
+* @param   in_video_input_channel vdc5_channel_t.
+* @param   in_data_control_ID vdc5_layer_id_t.
+* @param   in_self video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self )
+{
+    errnum_t         e;
+    video_input_t  **self_pp = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
+           in_video_input_channel,  in_data_control_ID,
+           &self_pp );
+    IF(e) {
+        goto fin;
+    }
+
+    ASSERT_R( *self_pp == NULL,  e=E_OTHERS; goto fin );
+
+    *self_pp = in_self;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt
+*
+* @param   in_video_input_channel vdc5_channel_t.
+* @param   in_data_control_ID vdc5_layer_id_t.
+* @param   in_self video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self )
+{
+    errnum_t         e;
+    video_input_t  **self_pp = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
+           in_video_input_channel,  in_data_control_ID,
+           &self_pp );
+    IF(e) {
+        goto fin;
+    }
+
+    ASSERT_R( *self_pp == in_self,  e=E_OTHERS; goto fin );
+
+    *self_pp = NULL;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt
+*
+* @param   in_interrupt vdc5_int_type_t.
+* @param   in_self video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_int_type_t  in_interrupt,
+    video_input_t  **out_self )
+{
+    errnum_t         e;
+    vdc5_layer_id_t  data_control_ID = VDC5_LAYER_ID_0_WR;
+    /* VDC5_LAYER_ID_0_WR is for avoiding warning C4017W of mbed cloud compiler */
+    video_input_t  **self_pp = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+
+    switch ( in_interrupt ) {
+        case  VDC5_INT_TYPE_S0_VI_VSYNC:
+            data_control_ID = VDC5_LAYER_ID_0_WR;
+            break;
+
+        case  VDC5_INT_TYPE_S1_VI_VSYNC:
+            data_control_ID = VDC5_LAYER_ID_1_WR;
+            break;
+
+        default:
+            ASSERT_R( false,  e=E_OTHERS;  goto fin );
+    }
+
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
+           in_video_input_channel,  data_control_ID,  &self_pp );
+    IF(e) {
+        goto fin;
+    }
+
+    *out_self = *self_pp;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_GetSelfPointer
+*
+* @param   in_video_input_channel vdc5_channel_t.
+* @param   in_data_control_ID vdc5_layer_id_t.
+* @param   out_self_pp video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfPointer(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t ***  out_self_pp )
+{
+    errnum_t      e;
+    int_fast32_t  video_input_index;
+    int_fast32_t  data_control_index;
+
+
+    if ( in_video_input_channel == VDC5_CHANNEL_0 ) {
+        video_input_index = 0;
+    } else {
+        ASSERT_D( in_video_input_channel == VDC5_CHANNEL_1,  e=E_OTHERS; goto fin );
+
+        video_input_index = 1;
+    }
+
+    if ( in_data_control_ID == VDC5_LAYER_ID_0_WR ) {
+        data_control_index = 0;
+    } else {
+        ASSERT_D( in_data_control_ID == VDC5_LAYER_ID_1_WR,  e=E_OTHERS; goto fin );
+
+        data_control_index = 1;
+    }
+
+    *out_self_pp = &gs_InterruptToSelf[ video_input_index ][ data_control_index ];
+
+    e=0;
+#ifndef  R_OSPL_NDEBUG
+fin:
+#endif
+    return  e;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/src/video_input_cpp.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,146 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input_cpp.cpp
+* @brief   $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "video_input.hpp"
+#include  "video_input.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  GS_DEFAULT_INT_VALUE  -1
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/***********************************************************************
+* ClassImplement: VideoInput
+************************************************************************/
+
+/***********************************************************************
+* Implement: VideoInput
+************************************************************************/
+VideoInput::VideoInput()
+{
+    this->_self = NULL;
+}
+
+
+/***********************************************************************
+* Implement: ~VideoInput
+************************************************************************/
+VideoInput::~VideoInput()
+{
+    this->destroy();
+}
+
+
+/***********************************************************************
+* Implement: initialize
+************************************************************************/
+errnum_t  VideoInput::initialize( VideoInputConfig &in_out_config )
+{
+    this->_self = new  video_input_t;
+    ASSERT_R( this->_self != NULL,  return  E_FEW_MEMORY );
+
+    in_out_config.flags =
+        VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM |
+        VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM |
+        VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM |
+        VIDEO_INPUT_CONFIG_T_FRAME_BUFFER |
+        VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC;
+
+    if ( in_out_config.video_input_channel_num == GS_DEFAULT_INT_VALUE ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM;
+    }
+    if ( in_out_config.display_channel_num == GS_DEFAULT_INT_VALUE ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM;
+    }
+    if ( in_out_config.display_layer_num == GS_DEFAULT_INT_VALUE ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM;
+    }
+    if ( in_out_config.frame_buffer == NULL ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_FRAME_BUFFER;
+    }
+    if ( in_out_config.captured_async == NULL ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC;
+    }
+
+    return  R_VIDEO_INPUT_Initialize( this->_self,  (video_input_config_t *) &in_out_config );
+}
+
+
+/***********************************************************************
+* Implement: destroy
+************************************************************************/
+void  VideoInput::destroy()
+{
+    if ( this->_self != NULL ) {
+        errnum_t  e = R_VIDEO_INPUT_Finalize( this->_self,  0 );
+        ASSERT_R( e == 0,  R_NOOP() );
+    }
+}
+
+
+/***********************************************************************
+* ClassImplement: VideoInputConfig
+************************************************************************/
+
+/***********************************************************************
+* Implement: VideoInputConfig
+************************************************************************/
+VideoInputConfig::VideoInputConfig()
+{
+    this->flags = 0;
+    this->video_input_channel_num = GS_DEFAULT_INT_VALUE;
+    this->display_channel_num = GS_DEFAULT_INT_VALUE;
+    this->display_layer_num = GS_DEFAULT_INT_VALUE;
+    this->frame_buffer = NULL;
+    this->captured_async = NULL;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/src/vsync.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,536 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "vsync.h"
+#include  "vsync_pl.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_v_sync_i_lock_t
+* @brief  I-Lock
+*/
+typedef struct st_r_v_sync_i_lock_t  r_v_sync_i_lock_t;
+struct st_r_v_sync_i_lock_t {
+    /** is_lock */
+    bool_t  is_lock;
+
+    /** channel_num */
+    int_fast32_t  channel_num;
+};
+
+
+/**
+* @struct  r_v_sync_channel_t
+* @brief  V-Sync context
+*/
+typedef struct st_r_v_sync_channel_t  r_v_sync_channel_t;
+struct st_r_v_sync_channel_t {
+    /*-----------------------------------------------------------*/
+    /* Group: Count */
+
+    /** VSync_FrameCount */
+    volatile int_fast32_t  VSync_FrameCount;
+
+    /** VSync_PreviousFrameCount */
+    volatile int_fast32_t  VSync_PreviousFrameCount;
+
+    /** VSync_TargetCount */
+    volatile int_fast32_t  VSync_TargetCount;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Interrupt */
+
+    /** AsyncStatus */
+    r_v_sync_async_status_t  AsyncStatus;
+
+    /** InterruptCallbackCaller */
+    r_ospl_caller_t    InterruptCallbackCaller;
+
+    /** InterruptFlag */
+    r_ospl_flag32_t    InterruptFlag;
+
+    /** IsEnabledInterrupt */
+    bool_t             IsEnabledInterrupt;
+
+    /** InterruptEnables */
+    r_ospl_flag32_t    InterruptEnables;
+
+    /** I_Lock */
+    r_v_sync_i_lock_t  I_Lock;
+};
+
+
+/* Section: Global */
+/** V-Sync context */
+static r_v_sync_channel_t  gs_v_sync_channel[ R_V_SYNC_CHANNEL_COUNT ];
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void   R_V_SYNC_I_LOCK_Reset( r_v_sync_i_lock_t *const  self );
+static bool_t R_V_SYNC_I_LOCK_Lock( r_v_sync_i_lock_t *const  self );
+static void   R_V_SYNC_I_LOCK_Unlock( r_v_sync_i_lock_t *const  self );
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_Initialize
+************************************************************************/
+errnum_t  R_V_SYNC_Initialize( int_fast32_t const  ChannelNum )
+{
+    errnum_t  e;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->I_Lock.channel_num = ChannelNum;
+    R_V_SYNC_I_LOCK_Reset( &self->I_Lock );
+
+    ASSERT_R( self->AsyncStatus.State == R_OSPL_UNINITIALIZED,  e=E_STATE; goto fin );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.InterruptFlags );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.CancelFlags );
+
+    e= R_V_SYNC_OnInitialize( ChannelNum );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    self->IsEnabledInterrupt = true;
+    R_OSPL_FLAG32_InitConst( &self->InterruptEnables );
+    self->AsyncStatus.State = R_OSPL_RUNNABLE;
+
+    R_OSPL_FLAG32_Set( &self->InterruptEnables, R_V_SYNC_INTERRUPT_LINE_V_LINE );
+    /* V-Sync interrupt always be enabled. Because clear interrupt status */
+
+    e=0;
+fin:
+    if ( e != 0 ) {
+        e= R_V_SYNC_Finalize( ChannelNum, e );
+        R_UNREFERENCED_VARIABLE( e );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_Finalize
+************************************************************************/
+errnum_t  R_V_SYNC_Finalize( int_fast32_t const  ChannelNum,  errnum_t e )
+{
+    bool_t                     was_enabled; /* = false; */ /* QAC 3197 */
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    was_enabled = R_V_SYNC_I_LOCK_Lock( &self->I_Lock );
+
+    if ( ! ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) ) {
+        if ( self->AsyncStatus.State != R_OSPL_UNINITIALIZED ) {
+            R_OSPL_FLAG32_Clear( &self->InterruptEnables, R_V_SYNC_INTERRUPT_LINE_V_LINE );
+
+            R_OSPL_FLAG32_Set( &self->AsyncStatus.CancelFlags,
+                               R_OSPL_CANNEL_REQUEST | R_OSPL_CANNELING | R_OSPL_CANNELED |
+                               R_OSPL_FINALIZE_REQUEST | R_OSPL_FINALIZING );
+
+            e= R_V_SYNC_OnFinalize( ChannelNum, e );
+
+            R_OSPL_FLAG32_Set( &self->AsyncStatus.CancelFlags, R_OSPL_FINALIZED );
+            R_OSPL_FLAG32_Clear( &self->AsyncStatus.CancelFlags, R_OSPL_FLAG32_ALL_BITS );
+            self->AsyncStatus.State = R_OSPL_UNINITIALIZED;
+        }
+    }
+
+    if ( IS( was_enabled ) ) {
+        R_V_SYNC_I_LOCK_Unlock( &self->I_Lock );
+    }
+    R_V_SYNC_I_LOCK_Reset( &self->I_Lock );
+
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_Wait
+************************************************************************/
+errnum_t  R_V_SYNC_Wait( int_fast32_t const  ChannelNum,
+                         int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum )
+{
+    errnum_t        e;
+    r_ospl_async_t  async;
+    bit_flags32_t   got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    e= R_V_SYNC_WaitStart( ChannelNum, SwapInterval, Is1VSyncAtMinimum, &async );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_WaitStart
+************************************************************************/
+errnum_t  R_V_SYNC_WaitStart( int_fast32_t const  ChannelNum,
+                              int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum,
+                              r_ospl_async_t *const  Async )
+{
+    errnum_t                   e;
+    bool_t                     was_enabled = false;
+    int_fast32_t               target_count;
+    int_fast32_t               operand1;
+    int_fast32_t               operand2;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF ( Async == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    R_V_SYNC_SetDefaultAsync( Async, R_OSPL_ASYNC_TYPE_NORMAL );
+    Async->ReturnValue = 0;
+    ASSERT_R( Async->I_Thread == NULL,  e=E_OTHERS; goto fin );
+
+    was_enabled = R_V_SYNC_I_LOCK_Lock( &self->I_Lock );
+
+    ASSERT_R( self->AsyncStatus.State == R_OSPL_RUNNABLE, e=E_STATE; goto fin );
+
+
+    /* Set "self->VSync_TargetCount" */
+    target_count = self->VSync_PreviousFrameCount + SwapInterval;
+    if ( (Is1VSyncAtMinimum) && (target_count < (self->VSync_FrameCount + 1)) ) {
+        target_count = self->VSync_FrameCount + 1;
+    }
+    self->VSync_TargetCount = target_count;
+
+
+    /* If already target count */
+    operand1 = self->VSync_TargetCount;  /* SEC R3.6.2 */
+    operand2 = self->VSync_FrameCount;   /* SEC R3.6.2 */
+    if ( (operand1 - operand2) <= 0 ) {
+        operand1 = self->VSync_FrameCount;  /* SEC R3.6.2 */
+        self->VSync_PreviousFrameCount = operand1;
+
+        /* Set application event */
+        R_OSPL_EVENT_Set( Async->A_Thread, Async->A_EventValue );
+    } else {
+        /* Change state to waiting */
+        self->AsyncStatus.State = R_OSPL_RUNNING;
+
+        /* Clear application event */
+        R_OSPL_EVENT_Clear( Async->A_Thread, Async->A_EventValue );
+
+        /* Attach "Async" to interrupt */
+        /* ->MISRA 11.4 : Not too big "enum" is same bit count as "int" */ /* ->SEC R2.7.1 */
+        R_OSPL_CALLER_Initialize( &self->InterruptCallbackCaller,
+                                  Async, (volatile int_t *) &self->AsyncStatus.State, R_OSPL_INTERRUPTING, NULL, NULL );
+        /* <-MISRA 11.4 */ /* <-SEC R2.7.1 */
+        e= R_V_SYNC_SetInterruptCallbackCaller( ChannelNum,
+                                                &self->InterruptCallbackCaller );
+        IF(e!=0) {
+            goto fin;
+        }
+    }
+
+    e=0;
+fin:
+    if ( IS( was_enabled ) ) {
+        R_V_SYNC_I_LOCK_Unlock( &self->I_Lock );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnInterrupting
+************************************************************************/
+errnum_t  R_V_SYNC_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource )
+{
+    errnum_t      e;
+    bool_t        was_enabled  = false;
+    int_fast32_t  operand1;
+    int_fast32_t  operand2;
+    int_fast32_t  channel_num_;
+    r_v_sync_channel_t  *self;
+    r_ospl_async_t      *notify_async = NULL;
+
+    IF_DQ( InterruptSource == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    channel_num_ = InterruptSource->ChannelNum;
+    self = &gs_v_sync_channel[ channel_num_ ];
+
+    if ( self->AsyncStatus.State != R_OSPL_INTERRUPTING ) {
+        e=0;
+        goto fin;
+    }
+
+    self->AsyncStatus.State = R_OSPL_INTERRUPTED;
+
+
+    /* Operate like R_V_SYNC_OnInterrupted() */
+    was_enabled = R_V_SYNC_I_LOCK_Lock( &self->I_Lock );
+
+    self->VSync_FrameCount += 1;
+
+
+    operand1 = self->VSync_TargetCount;  /* SEC R3.6.2 */
+    operand2 = self->VSync_FrameCount;   /* SEC R3.6.2 */
+    if ( (operand1 - operand2) <= 0 ) {
+        operand1 = self->VSync_FrameCount;  /* SEC R3.6.2 */
+        self->VSync_PreviousFrameCount = operand1;
+
+        e= R_V_SYNC_SetInterruptCallbackCaller( channel_num_, NULL );
+
+        self->AsyncStatus.State = R_OSPL_RUNNABLE;
+        notify_async = self->InterruptCallbackCaller.Async;
+    } else {
+        self->AsyncStatus.State = R_OSPL_RUNNING;
+    }
+
+
+    e=0;
+fin:
+    if ( IS( was_enabled ) ) {
+        /* ->QAC 3353 : "self" is always assigned, if "was_enabled" is true */
+        IF_DQ( self == NULL ) {}  /* QAC 3353 raises SEC R3.2.2 */
+        else {
+            R_V_SYNC_I_LOCK_Unlock( &self->I_Lock );
+        }
+        /* <-QAC 3353 */
+        /* This is for disabling interrupt by R_V_SYNC_I_LOCK_Disable() */
+    }
+
+    if ( notify_async != NULL ) {
+        R_OSPL_EVENT_Set( notify_async->A_Thread, notify_async->A_EventValue );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_GetAsyncStatus
+************************************************************************/
+errnum_t  R_V_SYNC_GetAsyncStatus( int_fast32_t const  ChannelNum,
+                                   const r_v_sync_async_status_t **const  out_Status )
+{
+    errnum_t  e;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF_DQ( out_Status == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    *out_Status = &self->AsyncStatus;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Enable interrupt API
+*
+* @param   ChannelNum ChannelNum
+* @return  None
+*/
+void  R_V_SYNC_EnableInterrupt( int_fast32_t const  ChannelNum )
+{
+    errnum_t  e;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    R_V_SYNC_OnEnableInterrupt( ChannelNum, self->InterruptEnables.Flags );
+    self->IsEnabledInterrupt = true;
+
+    e=0;
+fin:
+    R_UNREFERENCED_VARIABLE( e );
+}
+
+
+/**
+* @brief   Disable interrupt API
+*
+* @param   ChannelNum ChannelNum
+* @return  None
+*/
+bool_t  R_V_SYNC_DisableInterrupt( int_fast32_t const  ChannelNum )
+{
+    errnum_t  e;
+    bool_t    was_interrupted = false;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    was_interrupted = self->IsEnabledInterrupt;
+    self->IsEnabledInterrupt = false;
+
+    R_V_SYNC_OnDisableInterrupt( ChannelNum, self->InterruptEnables.Flags );
+
+    e=0;
+fin:
+    R_UNREFERENCED_VARIABLE( e );
+    return  was_interrupted;
+}
+
+
+/**
+* @brief   Reset I-Lock (Interrupt Lock)
+*
+* @param   self r_v_sync_i_lock_t
+* @return  None
+*/
+static void  R_V_SYNC_I_LOCK_Reset( r_v_sync_i_lock_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->is_lock = false;
+    R_V_SYNC_OnDisableInterrupt( self->channel_num, R_V_SYNC_INTERRUPT_LINE_ALL );
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Lock
+*
+* @param   self r_v_sync_i_lock_t
+* @return  Was interrupt enabled
+*/
+static bool_t  R_V_SYNC_I_LOCK_Lock( r_v_sync_i_lock_t *const  self )
+{
+    bool_t  is_locked;
+    bool_t  b;
+
+    IF_DQ( self == NULL ) {
+        is_locked = true;
+        goto fin;
+    }
+
+    R_OSPL_DisableAllInterrupt();
+
+    is_locked = self->is_lock;
+    if ( ! is_locked ) {
+        b= R_V_SYNC_DisableInterrupt( self->channel_num );
+        R_UNREFERENCED_VARIABLE( b );  /* QAC 3200 : This is not error information */
+        self->is_lock = true;
+    }
+
+    R_OSPL_EnableAllInterrupt();
+
+fin:
+    return  ! is_locked;
+}
+
+
+/**
+* @brief   Unlock
+*
+* @param   self r_v_sync_i_lock_t
+* @return  None
+*/
+static void  R_V_SYNC_I_LOCK_Unlock( r_v_sync_i_lock_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    R_OSPL_DisableAllInterrupt();
+
+    R_V_SYNC_EnableInterrupt( self->channel_num );
+    self->is_lock = false;
+
+    R_OSPL_EnableAllInterrupt();
+fin:
+    return;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/src/window_surfaces.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2167 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "r_typedefs.h"
+#include  "lcd_panel.h"
+#include  "r_ospl.h"
+#include  "clib_registers.h"
+#include  "clib_drivers.h"
+#include  "clib_samples.h"
+#include  "window_surfaces.h"
+#include  "vsync.h"
+#include  "window_surfaces_private.h"
+#include  "RGA.h"
+#include  "RGA_Port.h"
+#if  USE_LCD
+#include  "lcd_if.h"
+#endif
+#include  <stdio.h>  /* in R_WINDOW_SURFACES_DoMessageLoop */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  gs_frame_width_height_t
+* @brief  gs_frame_width_height_t
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+typedef struct st_gs_frame_width_height_t  gs_frame_width_height_t;
+struct st_gs_frame_width_height_t {
+    int_fast32_t  Width;
+    int_fast32_t  Height;
+};
+#endif
+
+
+/**
+* @typedef  gs_rectangle_t
+* @brief  gs_rectangle_t
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+typedef struct st_gs_rectangle_t  gs_rectangle_t;
+struct st_gs_rectangle_t {
+    int_fast32_t  Left;
+    int_fast32_t  Top;
+    int_fast32_t  Right;   /* include right  bound pixel */
+    int_fast32_t  Bottom;  /* include bottom bound pixel */ /* Top < Bottom */
+};
+#endif
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* GS_ : global static */
+/* VDC5_CHANNEL_0 = LCD_VDC5_CH0_PANEL = ... */
+/* VDC5_CHANNEL_1 = LCD_VDC5_CH1_PANEL = ... */
+#if WINDOW_SURFACES_DEFAULT_CHANNEL
+#define   GS_CHANNEL_n              VDC5_CHANNEL_1
+#define   GS_LCD_CHn_SIG_FV         LCD_CH1_SIG_FV
+#define   GS_LCD_CHn_SIG_FH         LCD_CH1_SIG_FH
+#define   GS_LCD_CHn_DISP_VS        LCD_CH1_DISP_VS
+#define   GS_LCD_CHn_DISP_VW        LCD_CH1_DISP_VW
+#define   GS_LCD_CHn_DISP_HS        LCD_CH1_DISP_HS
+#define   GS_LCD_CHn_DISP_HW        LCD_CH1_DISP_HW
+#define   GS_LCD_CHn_TCON_HALF      LCD_CH1_TCON_HALF
+#define   GS_LCD_CHn_TCON_OFFSET    LCD_CH1_TCON_OFFSET
+#define   GS_LCD_CHn_OUT_EDGE       LCD_CH1_OUT_EDGE
+#define   GS_LCD_CHn_OUT_FORMAT     LCD_CH1_OUT_FORMAT
+#define   GS_LCD_CHn_PANEL_CLK      LCD_CH1_PANEL_CLK
+#define   GS_LCD_CHn_PANEL_CLK_DIV  LCD_CH1_PANEL_CLK_DIV
+#define   GS_DISPLAY_CH             1   /* 1 or 0 */
+#else
+#define   GS_CHANNEL_n              VDC5_CHANNEL_0
+#define   GS_LCD_CHn_SIG_FV         LCD_CH0_SIG_FV
+#define   GS_LCD_CHn_SIG_FH         LCD_CH0_SIG_FH
+#define   GS_LCD_CHn_DISP_VS        LCD_CH0_DISP_VS
+#define   GS_LCD_CHn_DISP_VW        LCD_CH0_DISP_VW
+#define   GS_LCD_CHn_DISP_HS        LCD_CH0_DISP_HS
+#define   GS_LCD_CHn_DISP_HW        LCD_CH0_DISP_HW
+#define   GS_LCD_CHn_TCON_HALF      LCD_CH0_TCON_HALF
+#define   GS_LCD_CHn_TCON_OFFSET    LCD_CH0_TCON_OFFSET
+#define   GS_LCD_CHn_OUT_EDGE       LCD_CH0_OUT_EDGE
+#define   GS_LCD_CHn_OUT_FORMAT     LCD_CH0_OUT_FORMAT
+#define   GS_LCD_CHn_PANEL_CLK      LCD_CH0_PANEL_CLK
+#define   GS_LCD_CHn_PANEL_CLK_DIV  LCD_CH0_PANEL_CLK_DIV
+#define   GS_DISPLAY_CH             0   /* 1 or 0 */
+#endif
+
+#if  1
+#define   GS_BUFFER_WIDTH           800
+#define   GS_BUFFER_HEIGHT          480
+#else
+#define   GS_BUFFER_WIDTH           GS_LCD_CHn_DISP_HW
+#define   GS_BUFFER_HEIGHT          GS_LCD_CHn_DISP_VW
+#endif
+
+#define   GS_MEASURE_GPU_LOAD       0
+
+#define  GS_DEFAULT_CLEAR_COLOR  R_RGA_DEFAULT_CLEAR_COLOR
+
+#ifdef  R_REE_INIT
+#define  GRAPHICS_GetLvdsParam        Graphics_GetLvdsParam
+#define  GRAPHICS_SetLcdTconSettings  Graphics_SetLcdTconSettings
+#define  GRAPHICS_SetLcdPanel         Graphics_SetLcdPanel
+#endif
+#ifdef  RZ_A1L
+#define  GRAPHICS_GetLvdsParam( ch )                 NULL
+#define  GRAPHICS_SetLcdTconSettings( ch, setting )  GRAPHICS_L_SetLcdTconSettings( setting )
+#define  GRAPHICS_SetLcdPanel( ch )                  GRAPHICS_L_SetLcdPanel()
+#endif
+
+/**
+* @def  GS_OFFSET_BYTE_NOT_SHOW
+* @brief  GS_OFFSET_BYTE_NOT_SHOW
+*/
+enum { GS_OFFSET_BYTE_NOT_SHOW = -1 };
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static errnum_t  R_WINDOW_SURFACES_SwapBuffers_Sub( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num );
+
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  GS_ToInFrame(
+    gs_frame_width_height_t *SourceFrameBuffer,
+    gs_frame_width_height_t *DestinationFrameBuffer,
+    gs_rectangle_t *SourceRect,
+    gs_rectangle_t *DestinationRect );
+#endif
+
+
+/**
+* @brief   alloc_VRAM_stack_sub
+*
+* @param   in_out_StackPointer in_out_StackPointer
+* @param   OverOfVRAM OverOfVRAM
+* @param   in_out_FrameBuffer in_out_FrameBuffer
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - (input) - >stride, ->height, ->buffer_count
+*    - (output) - >buffer_address[(all)]
+*/
+static errnum_t  alloc_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                       const uint8_t *const  OverOfVRAM,
+                                       frame_buffer_t *const  in_out_FrameBuffer ); /* QAC-3450 */
+static errnum_t  alloc_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                       const uint8_t *const  OverOfVRAM,
+                                       frame_buffer_t *const  in_out_FrameBuffer )
+{
+    errnum_t      e;
+    int_fast32_t  size_1;
+    int_fast32_t  size_all;
+    int_fast32_t  buffer_num;
+    uint8_t      *stack_pointer;
+
+
+    IF_DQ( in_out_StackPointer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( in_out_FrameBuffer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    stack_pointer = *in_out_StackPointer;
+
+
+    /* Set "size_1" */
+    size_1 = in_out_FrameBuffer->stride * in_out_FrameBuffer->height;
+    size_1 = ( R_Ceil_64s( size_1 ) );
+
+
+    /* Set "size_all" */
+    size_all = in_out_FrameBuffer->buffer_count * size_1;
+
+
+    /* Check */
+    /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+    IF ( (stack_pointer + size_all) > OverOfVRAM ) {
+        in_out_FrameBuffer->buffer_count = 0;
+        e=E_FEW_ARRAY;
+        goto fin;
+    }
+    /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+
+    IF ( in_out_FrameBuffer->buffer_count >
+         (int_fast32_t) R_COUNT_OF( in_out_FrameBuffer->buffer_address ) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    /* Set "in_out_FrameBuffer->buffer_address" */
+    for ( buffer_num = 0;
+            buffer_num < in_out_FrameBuffer->buffer_count;
+            buffer_num += 1 ) {
+        in_out_FrameBuffer->buffer_address[ buffer_num ] = stack_pointer;
+
+        /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+        stack_pointer += size_1;  /* MISRA 17.4: Bound check is done by "OverOfVRAM" */
+        /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+    }
+    for ( /* buffer_num */;
+                          buffer_num < (int_fast32_t) R_COUNT_OF( in_out_FrameBuffer->buffer_address );
+                          buffer_num += 1 ) {
+        in_out_FrameBuffer->buffer_address[ buffer_num ] = NULL;
+    }
+
+    *in_out_StackPointer = stack_pointer;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   free_VRAM_stack_sub
+*
+* @param   in_out_StackPointer in_out_StackPointer
+* @param   frame_buffer frame_buffer
+* @param   StartOfVRAM StartOfVRAM
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - If frame_buffer - >buffer_count == 0, do nothing.
+*/
+static errnum_t  free_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                      const frame_buffer_t *const  frame_buffer,
+                                      const uint8_t *const  StartOfVRAM ); /* QAC-3450 */
+static errnum_t  free_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                      const frame_buffer_t *const  frame_buffer,
+                                      const uint8_t *const  StartOfVRAM )
+{
+    errnum_t      e;
+    int_fast32_t  size_1;
+    int_fast32_t  size_all;
+    int_fast32_t  buffer_num;
+    uint8_t      *next_stack_pointer;
+
+
+    IF_DQ( frame_buffer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( in_out_StackPointer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    /* Set "size_1" */
+    size_1 = frame_buffer->stride * frame_buffer->height;
+    size_1 = ( R_Ceil_64s( size_1 ) );
+    R_STATIC_ASSERT( RGA_STACK_ADDRESS_ALIGNMENT == 64, "" );  /* check of ceil_xx */
+
+
+    /* Set "size_all" */
+    size_all = frame_buffer->buffer_count * size_1;
+
+
+    /* Set "next_stack_pointer" */
+    /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+    next_stack_pointer = *in_out_StackPointer - size_all;
+    /* MISRA 17.4: Bound check is done by "StartOfVRAM" */
+    /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+
+
+    /* Check */
+    IF ( next_stack_pointer < StartOfVRAM ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    IF ( frame_buffer->buffer_count > (int_fast32_t) R_COUNT_OF( frame_buffer->buffer_address ) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    for ( buffer_num = frame_buffer->buffer_count - 1;  buffer_num >= 0;  buffer_num -= 1 ) {
+        /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+        IF ( frame_buffer->buffer_address[ buffer_num ] !=
+             (next_stack_pointer + (size_1 * buffer_num)) ) {
+            e=E_ACCESS_DENIED;
+            goto fin;
+        }
+        /* MISRA 17.4: Bound check is done by "size_all" */
+        /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+    }
+
+
+    /* Set "*in_out_StackPointer" */
+    *in_out_StackPointer = next_stack_pointer;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/*-------------------------------------------------------------------------*/
+/* <<<< ### (window_surfaces_vdc5_layer_t) Class implement >>>> */
+/*-------------------------------------------------------------------------*/
+
+/**
+* @brief   Initialize <window_surfaces_vdc5_layer_t>
+*
+* @param   self window_surfaces_vdc5_layer_t
+* @param   layer_num layer_num
+* @param   graphics_layer_ID graphics_layer_ID
+* @return  Error code, 0=No error
+*/
+static errnum_t  window_surfaces_vdc5_layer_t__initialize(
+    window_surfaces_vdc5_layer_t *const  self,
+    int_fast32_t const  layer_num,
+    vdc5_graphics_type_t const  graphics_layer_ID ); /* QAC-3450 */
+
+static errnum_t  window_surfaces_vdc5_layer_t__initialize(
+    window_surfaces_vdc5_layer_t *const  self,
+    int_fast32_t const  layer_num,
+    vdc5_graphics_type_t const  graphics_layer_ID )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_int_t_to_int8_t( layer_num, &self->layer_num );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    self->graphics_layer_ID = graphics_layer_ID;
+
+    self->is_data_control = false;
+
+    self->layer_color = GS_DEFAULT_CLEAR_COLOR;
+
+    switch ( graphics_layer_ID ) {
+        case  VDC5_GR_TYPE_GR0:
+            self->data_control_ID = VDC5_LAYER_ID_0_RD;
+            break;
+#ifndef  RZ_A1L
+        case  VDC5_GR_TYPE_GR1:
+            self->data_control_ID = VDC5_LAYER_ID_1_RD;
+            break;
+#endif
+        case  VDC5_GR_TYPE_GR2:
+            self->data_control_ID = VDC5_LAYER_ID_2_RD;
+            break;
+        case  VDC5_GR_TYPE_GR3:
+            self->data_control_ID = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            e=E_OTHERS;
+            goto fin; /* Bad "graphics_layer_ID" */
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+
+/*-------------------------------------------------------------------------*/
+/* <<<< ### (window_surfaces_t) Class implement >>>> */
+/*-------------------------------------------------------------------------*/
+
+/**
+* @brief   Get <window_surfaces_vdc5_layer_t>
+*
+* @param   self window_surfaces_t
+* @param   in_LayerNum in_LayerNum
+* @param   out_Layer out_Layer
+* @return  Error code, 0=No error
+*/
+STATIC_INLINE errnum_t  window_surfaces_t__get_layer( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_vdc5_layer_t **const  out_Layer );  /* QAC-3450 */
+/* ->MISRA 16.7 : "self" can not "const", because "out_Layer" is not "const" */
+/* ->SEC M1.11.1 */
+STATIC_INLINE errnum_t  window_surfaces_t__get_layer( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_vdc5_layer_t **const  out_Layer )
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+{
+    errnum_t       e;
+    uint_fast32_t  index;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Layer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    index = in_LayerNum - self->layer_num_min;
+
+    IF ( index >= R_COUNT_OF( self->layers ) ) {
+        e = E_OTHERS;
+        goto fin;
+    }
+
+    *out_Layer = &self->layers[ index ];
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Get <window_surfaces_attribute_t>
+*
+* @param   self window_surfaces_t
+* @param   in_LayerNum in_LayerNum
+* @param   out_Attribute out_Attribute
+* @return  Error code, 0=No error
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+STATIC_INLINE errnum_t  window_surfaces_t__get_attribute( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_attribute_t **const  out_Attribute );  /* QAC-3450 */
+/* ->MISRA 16.7 : "self" can not "const", because "out_Attribute" is not "const" */
+/* ->SEC M1.11.1 */
+STATIC_INLINE errnum_t  window_surfaces_t__get_attribute( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_attribute_t **const  out_Attribute )
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+{
+    errnum_t       e;
+    uint_fast32_t  index;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Attribute == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    index = in_LayerNum - self->layer_num_min;
+
+    IF ( index >= R_COUNT_OF( self->layers ) ) {
+        e = E_OTHERS;
+        goto fin;
+    }
+
+    *out_Attribute = &self->attributes[ index ];
+
+    e=0;
+fin:
+    return  e;
+}
+#endif
+
+
+/***********************************************************************
+* Class: window_surfaces_t
+************************************************************************/
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_InitConst
+************************************************************************/
+
+static bool_t  gs_window_surfaces_t_is_init = false;
+
+void  R_WINDOW_SURFACES_InitConst( window_surfaces_t *const  self )
+{
+    int_fast32_t  i;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    for ( i = 0;  i < (ssize_t) R_COUNT_OF( self->frame_buffers );  i += 1 ) {
+        self->frame_buffers[i].buffer_address[0] = NULL;
+    }
+    self->is_initialized = gs_window_surfaces_t_is_init;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_Initialize
+************************************************************************/
+
+static void  vdc5_init_func( uint32_t user_num );
+
+errnum_t  R_WINDOW_SURFACES_Initialize( window_surfaces_t *const  self,
+                                        window_surfaces_config_t  *in_out_config )
+{
+    errnum_t                  e;
+    errnum_t                  ee;
+    vdc5_error_t              error_vdc;
+    window_surfaces_config_t  default_config;
+    int_fast32_t              layer_num;
+    window_surfaces_vdc5_layer_t  *main_layer[ R_COUNT_OF( self->frame_buffers ) ];
+    window_surfaces_vdc5_layer_t  *back_layer;
+
+    enum { num_2 = 2,  num_4 = 4 };
+
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->screen_channel = GS_CHANNEL_n;
+
+
+    /* Set default configuration */
+    if ( in_out_config == NULL ) {
+        in_out_config = &default_config;
+        in_out_config->flags = 0;
+    }
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_PIXEL_FORMAT ) ) {
+        in_out_config->pixel_format = PIXEL_FORMAT_ARGB8888;
+        in_out_config->flags |= F_WINDOW_SURFACES_PIXEL_FORMAT;
+    }
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_LAYER_COUNT ) ) {
+        in_out_config->layer_count = 1;
+        in_out_config->flags |= F_WINDOW_SURFACES_LAYER_COUNT;
+    }
+    ASSERT_D( in_out_config->layer_count >= 1  &&  in_out_config->layer_count <= 2,
+              e=E_OTHERS; goto fin );
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_BUFFER_HEIGHT ) ) {
+        in_out_config->buffer_height = R_ToSigned( GS_BUFFER_HEIGHT );
+        in_out_config->flags |= F_WINDOW_SURFACES_BUFFER_HEIGHT;
+    }
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_BACKGROUND_COLOR ) ) {
+        in_out_config->background_color = GS_DEFAULT_CLEAR_COLOR;
+        in_out_config->flags |= F_WINDOW_SURFACES_BACKGROUND_COLOR;
+    }
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_BACKGROUND_FORMAT ) ) {
+        in_out_config->background_format = BACKGROUND_FORMAT_SOLID_COLOR;
+        in_out_config->flags |= F_WINDOW_SURFACES_BACKGROUND_FORMAT;
+    }
+
+
+    /* Set layers */
+#ifndef  RZ_A1L  /* RZ/A1H */
+    self->layer_num_min = -1;
+    self->layer_num_max =  in_out_config->layer_count - 1;
+    ASSERT_D( (ssize_t) R_COUNT_OF( self->layers ) >= self->layer_num_max - self->layer_num_min + 1,
+              e=E_OTHERS; goto fin );
+    e= window_surfaces_vdc5_layer_t__initialize( &self->layers[0], -1, VDC5_GR_TYPE_GR0 );
+    IF(e!=0) {
+        goto fin;
+    }
+    e= window_surfaces_vdc5_layer_t__initialize( &self->layers[1],  0, VDC5_GR_TYPE_GR1 );
+    IF(e!=0) {
+        goto fin;
+    }
+    e= window_surfaces_vdc5_layer_t__initialize( &self->layers[2],  1, VDC5_GR_TYPE_GR2 );
+    IF(e!=0) {
+        goto fin;
+    }
+#else
+    if ( in_out_config->pixel_format != PIXEL_FORMAT_YUV422 ) {
+        self->layer_num_min = -1;
+        self->layer_num_max =  in_out_config->layer_count - 1;
+        ASSERT_D( R_COUNT_OF( self->layers ) >= self->layer_num_max - self->layer_num_min + 1,
+                  e=E_OTHERS; goto fin );
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[0], -1, VDC5_GR_TYPE_GR0 );
+        IF(e!=0) {
+            goto fin;
+        }
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[1],  0, VDC5_GR_TYPE_GR2 );
+        IF(e!=0) {
+            goto fin;
+        }
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[2],  1, VDC5_GR_TYPE_GR3 );
+        IF(e!=0) {
+            goto fin;
+        }
+    } else { /* PIXEL_FORMAT_YUV422 */
+        self->layer_num_min = 0;
+        self->layer_num_max = in_out_config->layer_count - 1;
+        ASSERT_D( R_COUNT_OF( self->layers ) >= self->layer_num_max - self->layer_num_min + 1,
+                  e=E_OTHERS; goto fin );
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[0],  0, VDC5_GR_TYPE_GR0 );
+        IF(e!=0) {
+            goto fin;
+        }
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[1],  1, VDC5_GR_TYPE_GR2 );
+        IF(e!=0) {
+            goto fin;
+        }
+    }
+#endif
+
+
+    /* Set "main_layer", "back_layer" */
+    for ( layer_num = 0;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+        e= window_surfaces_t__get_layer( self,  layer_num,  &main_layer[ layer_num ] );
+        IF(e!=0) {
+            goto fin;
+        }
+        IF_DQ( main_layer[ layer_num ] == NULL ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+    }
+
+    self->background_format = in_out_config->background_format;
+    if ( self->layer_num_min >= 0 ) {
+        back_layer = NULL;
+        self->background_frame_count = 0;
+    } else {
+        back_layer = NULL;
+        /* NULL is for avoiding warning C417W of mbed cloud compiler */
+        e= window_surfaces_t__get_layer( self, -1, &back_layer );
+        IF(e!=0) {
+            goto fin;
+        }
+        IF_DQ( back_layer == NULL ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+
+        if ( in_out_config->background_format != BACKGROUND_FORMAT_SOLID_COLOR ) {
+            self->background_frame_count = 1;
+        } else {
+            self->background_frame_count = 0;
+        }
+    }
+
+
+    {
+        uint8_t   *memory_address;
+        size_t     memory_size;
+
+
+        /* Set "physical_address", ... */
+        e= R_Sample_GetBigMemory( &memory_address,  &memory_size );
+        IF ( e != 0 ) {
+            goto fin;
+        }
+        /* 64byte alignment */
+        ASSERT_R( R_Mod_64u( (uintptr_t) memory_address ) == 0,  e=E_OTHERS; goto fin );
+
+
+        /* Set "self->start_of_VRAM", ... */
+        self->start_of_VRAM = memory_address;
+        /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+        self->over_of_VRAM  = self->start_of_VRAM + memory_size;  /* MISRA 17.4: This is a bound */
+        /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+        self->stack_pointer_of_VRAM = self->start_of_VRAM;
+    }
+
+
+    for ( layer_num = -self->background_frame_count;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+        frame_buffer_t  *frame;
+        window_surfaces_vdc5_layer_t  *layer = main_layer[ layer_num ];
+        pixel_format_t  pixel_format;
+
+        e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+        IF(e) {
+            goto fin;
+        }
+
+        if ( layer_num <= -1  &&  in_out_config->background_format != BACKGROUND_FORMAT_SOLID_COLOR ) {
+            pixel_format = PIXEL_FORMAT_YUV422;
+        } else if ( layer_num >= 1  &&  in_out_config->pixel_format == PIXEL_FORMAT_YUV422 ) {
+            pixel_format = PIXEL_FORMAT_ARGB4444;
+        } else {
+            pixel_format = in_out_config->pixel_format;
+        }
+
+
+        /* Set "self->frame_buffers" */
+        frame->buffer_count      = num_2;
+        frame->show_buffer_index = 0;
+        frame->draw_buffer_index = 0;
+        frame->width             = R_ToSigned( GS_BUFFER_WIDTH );
+        frame->height            = in_out_config->buffer_height;
+        frame->pixel_format      = pixel_format;
+        frame->delegate          = NULL;
+
+        switch ( frame->pixel_format ) {
+            case PIXEL_FORMAT_ARGB8888:
+                frame->buffer_count      = 1;
+                frame->draw_buffer_index = 0;
+                frame->byte_per_pixel    = num_4;
+                layer->vdc5_format = VDC5_GR_FORMAT_ARGB8888;
+                break;
+
+            case PIXEL_FORMAT_XRGB8888:
+                frame->buffer_count      = 1;
+                frame->draw_buffer_index = 0;
+                frame->byte_per_pixel    = num_4;
+                layer->vdc5_format = VDC5_GR_FORMAT_RGB888;
+                break;
+
+            case PIXEL_FORMAT_RGB565:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_RGB565;
+                break;
+
+            case PIXEL_FORMAT_ARGB1555:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_ARGB1555;
+                break;
+
+            case PIXEL_FORMAT_ARGB4444:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_ARGB4444;
+                break;
+
+            case PIXEL_FORMAT_YUV422:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_YCBCR422;
+                break;
+
+            case PIXEL_FORMAT_CLUT8:
+                frame->buffer_count      = 2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = R_RGA_BitPerPixelType_To_BytePerPixelType( 8 );
+                layer->vdc5_format = VDC5_GR_FORMAT_CLUT8;
+                break;
+
+            case PIXEL_FORMAT_CLUT4:
+                frame->buffer_count      = 2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = R_RGA_BitPerPixelType_To_BytePerPixelType( 4 );
+                layer->vdc5_format = VDC5_GR_FORMAT_CLUT4;
+                break;
+
+            case PIXEL_FORMAT_CLUT1:
+                frame->buffer_count      = 2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = R_RGA_BitPerPixelType_To_BytePerPixelType( 1 );
+                layer->vdc5_format = VDC5_GR_FORMAT_CLUT1;
+                break;
+
+            default:
+                layer->vdc5_format = VDC5_GR_FORMAT_NUM;  /* dummy data */
+                break;
+        }
+        if( R_BYTE_PER_PIXEL_IsInteger( frame->byte_per_pixel ) ) {
+            frame->stride = frame->width * frame->byte_per_pixel;
+        } else {
+            frame->stride = R_Ceil_8s( frame->width *
+                                       R_RGA_BytePerPixelType_To_BitPerPixelType( frame->byte_per_pixel ) ) / 8;
+            frame->stride = R_Ceil_32s( frame->stride );
+        }
+        e= alloc_VRAM_stack_sub( &self->stack_pointer_of_VRAM,
+                                 self->over_of_VRAM, frame );
+        IF(e!=0) {
+            goto fin;
+        }
+
+#ifndef R_OSPL_NDEBUG
+        printf( "Screen %dx%dx%dx%d vdc5_format=%d stride=%d \n address[0]=0x%08X address[1]=0x%08X\n",
+                frame->buffer_count, frame->width, frame->height, frame->byte_per_pixel,
+                layer->vdc5_format, frame->stride,
+                (uintptr_t) frame->buffer_address[0], (uintptr_t) frame->buffer_address[1] );
+        /* Cast of "uintptr_t" is for avoiding "format" warning of GNU_ARM */
+#endif
+    }
+
+
+    if ( ! self->is_initialized ) {
+
+        /* Call "R_VDC5_Initialize" */
+        {
+            vdc5_init_t  init;
+
+            init.panel_icksel = GS_LCD_CHn_PANEL_CLK;
+            init.panel_dcdr   = GS_LCD_CHn_PANEL_CLK_DIV;
+            init.lvds = GRAPHICS_GetLvdsParam( self->screen_channel );
+
+            error_vdc = R_VDC5_Initialize( self->screen_channel, &init,
+                                           &vdc5_init_func, (uint32_t) self->screen_channel );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+
+
+        /* Call "R_VDC5_SyncControl" */
+        {
+            vdc5_sync_ctrl_t  sync_ctrl;
+
+            sync_ctrl.res_vs_sel    = VDC5_ON;                      /* Free-running Vsync ON/OFF */
+            sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;       /* SC_RES_VS_IN_SEL */
+            sync_ctrl.res_fv        = (uint16_t)GS_LCD_CHn_SIG_FV;     /* Free-running Vsync period setting */
+            sync_ctrl.res_fh        = (uint16_t)GS_LCD_CHn_SIG_FH;     /* Hsync period setting */
+            sync_ctrl.res_vsdly     = (uint16_t)0u;                 /* Vsync signal delay control */
+            /* Full-screen enable control */
+            sync_ctrl.res_f.vs      = (uint16_t)GS_LCD_CHn_DISP_VS;
+            sync_ctrl.res_f.vw      = (uint16_t)GS_LCD_CHn_DISP_VW;
+            sync_ctrl.res_f.hs      = (uint16_t)GS_LCD_CHn_DISP_HS;
+            sync_ctrl.res_f.hw      = (uint16_t)GS_LCD_CHn_DISP_HW;
+            sync_ctrl.vsync_cpmpe   = NULL;                         /* Vsync signal compensation */
+
+            error_vdc = R_VDC5_SyncControl( self->screen_channel, &sync_ctrl );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+
+
+        /* Call "R_VDC5_DisplayOutput" */
+        {
+            vdc5_output_t  output;
+            argb8888_t     background_color_;  /* _ is for MISRA 5.6 */
+
+            /* ->QAC 3198 */
+            background_color_.Value = DUMMY_INITIAL_VALUE;  /* for avoid ARMCC warning C4017W */
+            /* <-QAC 3198 */
+            background_color_.u.Alpha = 0;
+            background_color_.u.Red   = in_out_config->background_color.u.Red;
+            background_color_.u.Green = in_out_config->background_color.u.Green;
+            background_color_.u.Blue  = in_out_config->background_color.u.Blue;
+
+
+            output.tcon_half        = (uint16_t)GS_LCD_CHn_TCON_HALF;  /* TCON reference timing, 1/2fH timing */
+            output.tcon_offset      = (uint16_t)GS_LCD_CHn_TCON_OFFSET;/* TCON reference timing, offset Hsync signal timing */
+            /* LCD TCON timing setting */
+            GRAPHICS_SetLcdTconSettings( self->screen_channel, output.outctrl );
+            output.outcnt_lcd_edge  = GS_LCD_CHn_OUT_EDGE;          /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+            output.out_endian_on    = VDC5_OFF;                     /* Bit endian change ON/OFF control */
+            output.out_swap_on      = VDC5_OFF;                     /* B/R signal swap ON/OFF control */
+            output.out_format       = GS_LCD_CHn_OUT_FORMAT;        /* LCD output format select */
+            output.out_frq_sel      = VDC5_LCD_PARALLEL_CLKFRQ_1;   /* Clock frequency control */
+            output.out_dir_sel      = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
+            output.out_phase        = VDC5_LCD_SERIAL_CLKPHASE_0;   /* Clock phase adjustment */
+            output.bg_color         = background_color_.Value;
+
+            error_vdc = R_VDC5_DisplayOutput( self->screen_channel, &output );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+
+            if ( back_layer != NULL ) {
+                back_layer->layer_color = in_out_config->background_color;
+            }
+        }
+
+        self->is_initialized = true;
+    }
+
+
+    /* Call "R_VDC5_ReadDataControl" */
+    {
+        vdc5_read_t           read;
+        vdc5_width_read_fb_t  read_area;
+
+
+        for ( layer_num = 0;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+            int_fast32_t     bit_per_pixel;
+            frame_buffer_t  *frame;
+            window_surfaces_vdc5_layer_t  *layer = main_layer[ layer_num ];
+
+            e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+            IF(e) {
+                goto fin;
+            }
+
+
+            /* Read data parameter */
+            read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+            read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+            read.gr_imr_flm_inv = VDC5_OFF;                 /* Sets the frame buffer number for distortion correction */
+            read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+            /* ->QAC 0306 */
+            read.gr_base        = (void *) frame->buffer_address[ frame->show_buffer_index ]; /* Frame buffer base address */
+            /* <-QAC 0306 */
+            read.gr_ln_off      = (uint32_t) frame->stride; /* Frame buffer line offset address */
+            read.width_read_fb = NULL;             /* width of the image read from frame buffer */
+            read.adj_sel = VDC5_OFF;                /* Measures to decrease the influence
+		                                                   by folding pixels/lines (ON/OFF) */
+            read.gr_format      = layer->vdc5_format;       /* Graphics format of the frame buffer read signal */
+            read.gr_ycc_swap = VDC5_GR_YCCSWAP_Y1CRY0CB;
+            /* Controls swapping of data read from buffer in the YCbCr422 format */
+
+            bit_per_pixel = R_RGA_BytePerPixelType_To_BitPerPixelType( frame->byte_per_pixel );
+            if ( (bit_per_pixel == 32) || (frame->pixel_format == PIXEL_FORMAT_YCbCr422) ) {
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_32BIT;
+            } else if ( bit_per_pixel == 16 ) {
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_32_16BIT;
+            } else if ( bit_per_pixel <= 8 ) {
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_32_16_8BIT;
+            }
+            /* Display area */
+            read.gr_grc.hs      = (uint16_t) GS_LCD_CHn_DISP_HS;
+            read.gr_grc.hw      = (uint16_t) GS_LCD_CHn_DISP_HW;
+            read.gr_grc.vs      = (uint16_t) GS_LCD_CHn_DISP_VS;
+            if ( GS_BUFFER_HEIGHT < GS_LCD_CHn_DISP_VW ) {
+                read.gr_grc.vw      = (uint16_t) GS_BUFFER_HEIGHT;
+            } else {
+                read.gr_grc.vw      = (uint16_t) GS_LCD_CHn_DISP_VW;
+            }
+
+            error_vdc = R_VDC5_ReadDataControl( self->screen_channel, layer->data_control_ID, &read );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+            layer->is_data_control = true;
+        }
+
+        if ( back_layer != NULL ) {
+            if ( self->background_format == BACKGROUND_FORMAT_SOLID_COLOR ) {
+
+                /* Set display area for back ground */
+                /* "read.gr_base", ... are ignored */
+
+                error_vdc = R_VDC5_ReadDataControl( self->screen_channel, back_layer->data_control_ID, &read );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+            } else {
+                frame_buffer_t                *frame;
+                window_surfaces_vdc5_layer_t  *layer = back_layer;
+
+                e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, -1, &frame );
+                IF(e) {
+                    goto fin;
+                }
+
+
+                /* Read data parameter */
+                read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+                read.gr_flm_sel     = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+                read.gr_imr_flm_inv = VDC5_OFF;                 /* Sets the frame buffer number for distortion correction */
+                read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+                /* ->QAC 0306 */
+                read.gr_base        = (void *) frame->buffer_address[ frame->show_buffer_index ]; /* Frame buffer base address */
+                /* <-QAC 0306 */
+                read.gr_ln_off      = (uint32_t) frame->stride; /* Frame buffer line offset address */
+                read_area.in_hw     = frame->width;
+                read_area.in_vw     = frame->height / 2;
+                read.width_read_fb  = &read_area;
+                read.adj_sel        = VDC5_ON;
+                read.gr_format      = layer->vdc5_format;       /* Graphics format of the frame buffer read signal */
+                read.gr_ycc_swap    = VDC5_GR_YCCSWAP_CBY0CRY1;
+                /* Controls swapping of data read from buffer in the YCbCr422 format */
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_16BIT;
+
+                /* Display area */
+                read.gr_grc.hs      = (uint16_t) GS_LCD_CHn_DISP_HS;
+                read.gr_grc.hw      = (uint16_t) GS_LCD_CHn_DISP_HW;
+                read.gr_grc.vs      = (uint16_t) GS_LCD_CHn_DISP_VS;
+                if ( GS_BUFFER_HEIGHT < GS_LCD_CHn_DISP_VW ) {
+                    read.gr_grc.vw = (uint16_t) GS_BUFFER_HEIGHT;
+                } else {
+                    read.gr_grc.vw = (uint16_t) GS_LCD_CHn_DISP_VW;
+                }
+
+                error_vdc = R_VDC5_ReadDataControl( self->screen_channel, layer->data_control_ID, &read );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+            }
+            back_layer->is_data_control = true;
+        }
+    }
+
+
+    /* Call "R_VDC5_AlphaBlending" for ARGB1555 */
+    for ( layer_num = 0;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+        frame_buffer_t  *frame;
+
+        e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+        IF(e) {
+            goto fin;
+        }
+
+        if ( frame->pixel_format == PIXEL_FORMAT_ARGB1555 ) {
+            static vdc5_alpha_argb1555_t  alpha_for_argb1555 = { 0x00, U8_255 };
+            static vdc5_alpha_blending_t  blend = { &alpha_for_argb1555, NULL };
+
+            error_vdc = R_VDC5_AlphaBlending( self->screen_channel,
+                                              main_layer[ layer_num ]->data_control_ID,
+                                              &blend );
+            IF( error_vdc != VDC5_OK ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+
+    /* Call "R_V_SYNC_Initialize" */
+    e= R_V_SYNC_Initialize( (int_fast32_t) self->screen_channel );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+
+    /* Wait for avoiding LCD filled white (LCD-KIT-B01) */
+    e= R_OSPL_Delay( 80 );
+    IF(e) {
+        goto fin;
+    }
+
+
+    /* Set graphics display mode */
+    {
+        vdc5_start_t  start;
+        int_fast32_t  i;
+
+        for ( i = 0;  i < (int_fast32_t) R_COUNT_OF( self->vdc5_disp_sel_array );  i += 1 ) {
+            self->vdc5_disp_sel_array[ i ] = VDC5_DISPSEL_LOWER;  /* Reset */
+        }
+        self->vdc5_disp_sel_array[ VDC5_GR_TYPE_GR0 ] = VDC5_DISPSEL_BACK;
+
+        start.gr_disp_sel = self->vdc5_disp_sel_array;
+        error_vdc = R_VDC5_StartProcess( self->screen_channel, VDC5_LAYER_ID_ALL, &start );
+        IF ( error_vdc != VDC5_OK ) {
+            e = E_OTHERS;
+            goto fin;
+        }
+    }
+
+#if  USE_LCD
+    R_OSPL_Delay( 2*17 );  /* Synchronize to LCD */
+    LCD_SetBacklight( 100 );
+#endif
+
+
+    /* Set "self->attributes" */
+    for ( layer_num = self->layer_num_min;  layer_num <=  self->layer_num_max;  layer_num += 1 ) {
+        window_surfaces_attribute_t  *attribute = NULL;
+        /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+        e= window_surfaces_t__get_attribute( self, layer_num, &attribute );
+        IF(e) {
+            goto fin;
+        }
+
+        attribute->X = 0;
+        attribute->Y = 0;
+        attribute->Width  = R_ToSigned( GS_BUFFER_WIDTH );
+        attribute->Height = in_out_config->buffer_height;
+        attribute->OffsetX = 0;
+        attribute->OffsetY = 0;
+        attribute->OffsetByte = 0;
+    }
+
+
+    e=0;
+fin:
+    if ( e != 0 ) {
+        if ( self != NULL ) {
+            ee= R_WINDOW_SURFACES_Finalize( self, e );
+            R_UNREFERENCED_VARIABLE( ee );
+        }
+    }
+    return  e;
+}
+
+
+/**
+* @brief   vdc5_init_func
+*
+* @param   user_num channel
+* @return  None
+*/
+static void  vdc5_init_func( uint32_t const  user_num )
+{
+    vdc5_channel_t        channel;
+    struct st_cpg *const  reg_CPG = R_Get_CPG_Base();
+
+    IF_DQ( reg_CPG == NULL ) {
+        goto fin;
+    }
+
+    channel = (vdc5_channel_t)user_num;
+    if (channel == VDC5_CHANNEL_0) {
+        /* Standby control register 9 (STBCR9)
+        	b1      ------0-;  MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP91, false );
+    } else {
+        /* Standby control register 9 (STBCR9)
+        	b1      ------0-;  MSTP91 : 0 : Video display controller channel 0 & LVDS enable
+        	b0      -------0;  MSTP90 : 0 : Video display controller channel 1 enable */
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP91, false );
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP90, false );
+    }
+    GRAPHICS_SetLcdPanel(channel);
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_Finalize
+************************************************************************/
+
+static void  vdc5_quit_func( uint32_t const  user_num );
+
+errnum_t  R_WINDOW_SURFACES_Finalize( window_surfaces_t *const  self,  errnum_t e )
+{
+    vdc5_error_t  error_vdc;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_V_SYNC_Finalize( (int_fast32_t) self->screen_channel, e );
+
+    if ( ! self->is_initialized ) {
+        error_vdc = R_VDC5_Terminate( self->screen_channel, &vdc5_quit_func,
+                                      (uint32_t) self->screen_channel );
+        IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+            e = E_OTHERS;
+        }
+    } else {
+        int_fast32_t  i;
+
+        for ( i = -self->background_frame_count;  i <= self->layer_num_max;  i += 1 ) {
+            frame_buffer_t  *frame;
+            errnum_t         ee;
+
+            ee= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, i, &frame );
+            e= R_OSPL_MergeErrNum( e, ee );
+            frame->buffer_address[0] = NULL;
+        }
+
+        for ( i = self->layer_num_min;  i <=  self->layer_num_max;  i += 1 ) {
+            window_surfaces_vdc5_layer_t  *layer = NULL;
+            /* NULL is for avoiding warning C417W of mbed cloud compiler */
+            errnum_t  ee = window_surfaces_t__get_layer( self, i, &layer );
+
+            IF_DQ ( layer == NULL ) {
+                e=E_OTHERS;    /* Same check as "ee" */
+                goto fin;
+            }
+
+            if ( (ee == 0) && (layer->is_data_control) ) {
+                error_vdc = R_VDC5_StopProcess( self->screen_channel,
+                                                layer->data_control_ID );
+                IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+                    e = E_OTHERS;
+                }
+                error_vdc = R_VDC5_ReleaseDataControl( self->screen_channel,
+                                                       layer->data_control_ID );
+                layer->is_data_control = false;
+                IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+                    e = E_OTHERS;
+                }
+            }
+        }
+
+#define  R_WINDOW_SURFACES_TERMINATE_VDC5  1  /* 0 or 1 */
+#if      R_WINDOW_SURFACES_TERMINATE_VDC5
+        self->is_initialized = false;
+
+        error_vdc = R_VDC5_Terminate( self->screen_channel, &vdc5_quit_func,
+                                      (uint32_t) self->screen_channel );
+        IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+            e = E_OTHERS;
+        }
+#endif
+    }
+
+    gs_window_surfaces_t_is_init = self->is_initialized;
+
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   vdc5_quit_func
+*
+* @param   user_num channel
+* @return  None
+*/
+static void  vdc5_quit_func( uint32_t const  user_num )
+{
+    vdc5_channel_t const  channel = (vdc5_channel_t) user_num;
+    struct st_cpg *const  reg_CPG = R_Get_CPG_Base();
+
+    IF_DQ( reg_CPG == NULL ) {
+        goto fin;
+    }
+
+    if (channel == VDC5_CHANNEL_0) {
+        /* If LVDS should remain enabled, the following code should be removed. */
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP91, true );
+    } else {
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP90, true );
+    }
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_GetLayerFrameBuffer
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_GetLayerFrameBuffer( const window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  frame_buffer_t **const  out_frame_buffer )
+{
+    errnum_t       e;
+    uint_fast32_t  index;
+
+    IF_DQ( out_frame_buffer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    index = layer_num + self->background_frame_count;
+    IF ( index >= R_COUNT_OF( self->frame_buffers ) ) {
+        e = E_OTHERS;
+        goto fin;
+    }
+
+    *out_frame_buffer = (frame_buffer_t *) &self->frame_buffers[ index ];
+    /* Cast is for const */
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_SwapBuffers
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_SwapBuffers( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  graphics_t *const  context )
+{
+    errnum_t  e;
+#if GS_MEASURE_GPU_LOAD
+    enum {                interval = 60 };
+    uint32_t              idle_start_time;
+    uint32_t              idle_end_time;
+    static  uint32_t      skip_count;
+    static  uint32_t      previous_idle_end_time;
+    r_ospl_ftimer_spec_t  ts;
+#endif
+
+
+    e= R_GRAPHICS_Finish( context );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+#if GS_MEASURE_GPU_LOAD
+    e= R_OSPL_FTIMER_InitializeIfNot( &ts );
+    IF(e) {
+        goto fin;
+    }
+    idle_start_time = R_OSPL_FTIMER_Get();
+#endif
+
+
+    e= R_WINDOW_SURFACES_SwapBuffers_Sub( self, layer_num );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+    e= R_V_SYNC_Wait( self->screen_channel, 1, true );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+#if GS_MEASURE_GPU_LOAD
+    idle_end_time = R_OSPL_FTIMER_Get();
+    if ( previous_idle_end_time != 0 ) {  /* Skip at first */
+        skip_count += 1;
+        if ( skip_count >= interval ) {
+            printf( "GPU %d%% in %dmsec\n",
+                    ( idle_start_time - previous_idle_end_time ) * 100 /
+                    ( idle_end_time   - previous_idle_end_time ),
+                    R_OSPL_FTIMER_CountToTime( &ts,
+                                               idle_end_time - previous_idle_end_time ) );
+            skip_count = 0;
+
+            /* __heapstats( (__heapprt) fprintf, stdout ); */
+
+            /* R_DEBUG_BREAK(); */ /* This is for measuring CPU load */
+        }
+    }
+    previous_idle_end_time = idle_end_time;
+#endif
+
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_SwapBuffersStart
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_SwapBuffersStart( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  r_ospl_async_t *async )
+{
+    errnum_t  e;
+
+
+    e= R_WINDOW_SURFACES_SwapBuffers_Sub( self, layer_num );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+    e= R_V_SYNC_WaitStart( self->screen_channel, 1, true, async );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Sub routine of <R_WINDOW_SURFACES_SwapBuffers>
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @return  Error code, 0=No error
+*/
+static errnum_t  R_WINDOW_SURFACES_SwapBuffers_Sub( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num )
+{
+    errnum_t         e;
+    vdc5_error_t     error_vdc;
+    frame_buffer_t  *frame;
+    window_surfaces_vdc5_layer_t  *layer = NULL;
+    /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= window_surfaces_t__get_layer( self, layer_num, &layer );
+    IF(e!=0) {
+        goto fin;
+    }
+    IF_DQ( layer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    /* Swap buffer index */
+    e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+    IF(e) {
+        goto fin;
+    }
+    frame->show_buffer_index = frame->draw_buffer_index;
+    frame->draw_buffer_index += 1;
+    if ( frame->draw_buffer_index >= (int_t) frame->buffer_count ) {
+        frame->draw_buffer_index = 0;
+    }
+
+
+    /* Show the frame buffer */
+    {
+        vdc5_read_chg_t  config;
+        uintptr_t        physical_address;
+
+        window_surfaces_attribute_t   *attribute = NULL;
+        /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+        e= R_OSPL_ToPhysicalAddress( frame->buffer_address[ frame->show_buffer_index ],
+                                     &physical_address );
+        IF(e!=0) {
+            goto fin;
+        }
+
+        e= window_surfaces_t__get_attribute( self, layer_num, &attribute );
+        IF(e) {
+            goto fin;
+        }
+
+        if ( attribute->OffsetByte != GS_OFFSET_BYTE_NOT_SHOW ) {
+            physical_address += attribute->OffsetByte;
+
+            config.gr_base        = (void *) physical_address;
+            config.width_read_fb  = NULL;
+            config.gr_grc         = NULL;
+            config.gr_disp_sel    = NULL;
+            error_vdc = R_VDC5_ChangeReadProcess( self->screen_channel, layer->data_control_ID, &config );
+            IF ( error_vdc != VDC5_OK ) {
+                e=E_OTHERS;
+                goto  fin;
+            }
+        }
+    }
+
+
+    /* Show the layer */
+    {
+        vdc5_gr_disp_sel_t  new_value;
+
+        if ( layer_num == 1 ) {
+            new_value = VDC5_DISPSEL_BLEND;
+        } else if ( layer_num == 0 ) {
+            frame_buffer_t  *frame;
+
+            e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+            IF(e) {
+                goto fin;
+            }
+
+            if ( frame->pixel_format == PIXEL_FORMAT_YUV422 ) {
+                new_value = VDC5_DISPSEL_CURRENT;
+            } else {
+                new_value = VDC5_DISPSEL_BLEND;
+            }
+        } else {
+            ASSERT_D( layer_num == -1,  e=E_OTHERS; goto fin );
+
+            if ( self->background_format == BACKGROUND_FORMAT_SOLID_COLOR ) {
+                new_value = VDC5_DISPSEL_CURRENT;
+            } else {
+                new_value = VDC5_DISPSEL_LOWER;  /* "*_LOWER" is "*_CURRENT" for resize */
+            }
+        }
+
+        if ( self->vdc5_disp_sel_array[ layer->graphics_layer_ID ] != new_value ) {
+            vdc5_start_t  start;
+
+            self->vdc5_disp_sel_array[ layer->graphics_layer_ID ] = new_value;
+
+            start.gr_disp_sel = self->vdc5_disp_sel_array;
+            error_vdc = R_VDC5_StartProcess( self->screen_channel, VDC5_LAYER_ID_ALL, &start );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_WaitForVSync
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_WaitForVSync( window_surfaces_t *const  self,
+        int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum )
+{
+    return  R_V_SYNC_Wait( self->screen_channel, swap_interval, is_1_v_sync_at_minimum );
+}
+
+
+/**
+* @brief   R_WINDOW_SURFACES_AllocOffscreenStack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_WINDOW_SURFACES_AllocOffscreenStack( window_surfaces_t *const  self,
+        frame_buffer_t *const  in_out_frame_buffer )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= alloc_VRAM_stack_sub( &self->stack_pointer_of_VRAM,  self->over_of_VRAM,
+                             in_out_frame_buffer );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_WINDOW_SURFACES_FreeOffscreenStack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_WINDOW_SURFACES_FreeOffscreenStack( window_surfaces_t *const  self,
+        const frame_buffer_t *const  frame_buffer )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= free_VRAM_stack_sub( &self->stack_pointer_of_VRAM, frame_buffer,
+                            self->start_of_VRAM );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_DoMessageLoop
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_DoMessageLoop( window_surfaces_t *self )
+{
+    R_UNREFERENCED_VARIABLE( self );
+
+    R_OSPL_Delay( 2000 );
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_AccessLayerAttributes
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_AccessLayerAttributes( window_surfaces_t *self,
+        layer_attributes_t *in_out_Attributes )
+{
+    errnum_t         e;
+    vdc5_error_t     error_vdc;
+    window_surfaces_vdc5_layer_t  *layer = NULL;
+
+    if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_ID ) ) {
+        e= window_surfaces_t__get_layer( self, in_out_Attributes->id, &layer );
+        IF(e) {
+            goto fin;
+        }
+    }
+
+    ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Attributes->access, ~ACCESS_ALL_MASK ),  e=E_OTHERS; goto fin );
+
+
+    if ( in_out_Attributes->flags & F_LAYER_LAYER_COLOR ) {
+        vdc5_output_t  output;
+        vdc5_read_t    read;
+        r8g8b8a8_t     previous_layer_color = { {0,0,0,0} };
+        /* Avoid Warning: C4017W: previous_layer_color may be used before being set */
+        enum { necessary_flags = F_LAYER_ID };
+
+
+        ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, necessary_flags ),
+                  e=E_OTHERS; goto fin );
+        ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Attributes->access, ~(ACCESS_READ | ACCESS_WRITE) ),
+                  e=E_OTHERS; goto fin );
+
+
+        if ( IS_BIT_SET( in_out_Attributes->access, ACCESS_READ ) ) {
+            previous_layer_color = layer->layer_color;
+        }
+
+
+        if ( IS_BIT_SET( in_out_Attributes->access, ACCESS_WRITE ) ) {
+
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_LAYER_COLOR ) ) {
+
+                /* Set "output.bg_color" to "R_VDC5_DisplayOutput" */
+                output.tcon_half        = (uint16_t)GS_LCD_CHn_TCON_HALF;  /* TCON reference timing, 1/2fH timing */
+                output.tcon_offset      = (uint16_t)GS_LCD_CHn_TCON_OFFSET;/* TCON reference timing, offset Hsync signal timing */
+                GRAPHICS_SetLcdTconSettings( self->screen_channel, output.outctrl );
+                output.outcnt_lcd_edge  = GS_LCD_CHn_OUT_EDGE;          /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+                output.out_endian_on    = VDC5_OFF;                     /* Bit endian change ON/OFF control */
+                output.out_swap_on      = VDC5_OFF;                     /* B/R signal swap ON/OFF control */
+                output.out_format       = GS_LCD_CHn_OUT_FORMAT;        /* LCD output format select */
+                output.out_frq_sel      = VDC5_LCD_PARALLEL_CLKFRQ_1;   /* Clock frequency control */
+                output.out_dir_sel      = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
+                output.out_phase        = VDC5_LCD_SERIAL_CLKPHASE_0;   /* Clock phase adjustment */
+                output.bg_color         =
+                    ( in_out_Attributes->layer_color.u.Red << 16 ) |
+                    ( in_out_Attributes->layer_color.u.Green << 8 ) |
+                    ( in_out_Attributes->layer_color.u.Blue << 0 );  /* 24-bit RGB color format */
+
+                error_vdc = R_VDC5_DisplayOutput( self->screen_channel, &output );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+
+
+                /* Update ReadDataControl */
+
+                /* Release */
+                if ( layer->is_data_control ) {
+                    error_vdc = R_VDC5_StopProcess( self->screen_channel, layer->data_control_ID );
+                    IF ( error_vdc != VDC5_OK ) {
+                        R_NOOP();
+                    }
+                    error_vdc = R_VDC5_ReleaseDataControl( self->screen_channel, layer->data_control_ID );
+                    IF ( error_vdc != VDC5_OK ) {
+                        e=E_OTHERS;
+                        goto fin;
+                    }
+                    layer->is_data_control = false;
+                }
+
+                /* Read data parameter : These values are dummy */
+                read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+                read.gr_flm_sel     = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+                read.gr_imr_flm_inv = VDC5_OFF;                 /* Sets the frame buffer number for distortion correction */
+                read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+                read.gr_base        = (void *) &read;           /* Dummy, Frame buffer base address */
+                read.gr_ln_off      = 3200;                     /* Dummy, Frame buffer line offset address */
+                read.width_read_fb  = NULL;                     /* width of the image read from frame buffer */
+                read.adj_sel        = VDC5_OFF;                 /* Measures to decrease the influence
+				                                                   by folding pixels/lines (ON/OFF) */
+                read.gr_format      = VDC5_GR_FORMAT_RGB888;    /* Graphics format of the frame buffer read signal */
+                read.gr_ycc_swap    = VDC5_GR_YCCSWAP_Y1CRY0CB; /* Controls swapping of data read from buffer
+				                                                   in the YCbCr422 format */
+                read.gr_rdswa       = VDC5_WR_RD_WRSWA_32BIT;   /* for 32 bit format */
+
+                /* Set bakcground color area */
+                read.gr_grc.hs      = GS_LCD_CHn_DISP_HS;
+                read.gr_grc.hw      = (uint16_t) GS_LCD_CHn_DISP_HW;
+                read.gr_grc.vs      = GS_LCD_CHn_DISP_VS;
+                if ( GS_BUFFER_HEIGHT < GS_LCD_CHn_DISP_VW ) {
+                    read.gr_grc.vw      = (uint16_t) GS_BUFFER_HEIGHT;
+                } else {
+                    read.gr_grc.vw      = GS_LCD_CHn_DISP_VW;
+                }
+
+                /* Start to read again */
+                error_vdc = R_VDC5_ReadDataControl( self->screen_channel, layer->data_control_ID, &read );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+                layer->is_data_control = true;
+            }
+
+
+            /* Set graphics display mode */
+            {
+                vdc5_start_t  start;
+
+                start.gr_disp_sel = self->vdc5_disp_sel_array;
+                error_vdc = R_VDC5_StartProcess( self->screen_channel, VDC5_LAYER_ID_ALL, &start );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+            }
+        }
+
+        if ( IS_BIT_SET( in_out_Attributes->access, ACCESS_READ ) ) {
+            in_out_Attributes->layer_color = previous_layer_color;
+        }
+    }
+
+
+    /* Set window position */
+    {
+        enum { flags_of_window_position =
+                   F_LAYER_X | F_LAYER_Y | F_LAYER_WIDTH | F_LAYER_HEIGHT |
+                   F_LAYER_OFFSET_X | F_LAYER_OFFSET_Y
+             };
+
+        if ( IS_ANY_BITS_SET( in_out_Attributes->flags, flags_of_window_position )  &&
+                IS_BIT_SET( in_out_Attributes->access, ACCESS_WRITE ) ) {
+            vdc5_read_chg_t          change;
+            vdc5_width_read_fb_t     change_source_rectangle;
+            vdc5_period_rect_t       change_destination_rectangle;
+            gs_frame_width_height_t  source_frame;
+            gs_frame_width_height_t  destination_frame;
+            gs_rectangle_t           source_rectangle;
+            gs_rectangle_t           destination_rectangle;
+            frame_buffer_t          *frame;
+            bool_t                   is_interlace;
+            bool_t                   is_solid_color;
+            bool_t                   is_show = true;
+            window_surfaces_attribute_t  *attribute = NULL;
+            /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+
+            ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, F_LAYER_ID ), e=E_OTHERS; goto fin );
+
+            e= window_surfaces_t__get_attribute( self, in_out_Attributes->id, &attribute );
+            IF(e) {
+                goto fin;
+            }
+
+            is_interlace = ( self->background_format == BACKGROUND_FORMAT_VIDEO_INTERLACE  &&
+                             in_out_Attributes->id == -1 );
+
+            is_solid_color = ( self->background_format == BACKGROUND_FORMAT_SOLID_COLOR  &&
+                               in_out_Attributes->id == -1 );
+
+            change.gr_base = NULL;
+            change.width_read_fb = NULL;
+            change.gr_grc = NULL;
+            change.gr_disp_sel = NULL;
+
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_X ) ) {
+                attribute->X = in_out_Attributes->x;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_Y ) ) {
+                attribute->Y = in_out_Attributes->y;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_WIDTH ) ) {
+                attribute->Width = in_out_Attributes->width;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_HEIGHT ) ) {
+                attribute->Height = in_out_Attributes->height;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_X ) ) {
+                attribute->OffsetX = in_out_Attributes->offset_x;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_Y ) ) {
+                attribute->OffsetY = in_out_Attributes->offset_y;
+                change.gr_grc = &change_destination_rectangle;
+            }
+
+
+            /* Call "GS_ToInFrame" */
+            if ( is_solid_color ) {
+                e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, 0, &frame );
+                IF(e) {
+                    goto fin;
+                }
+            } else {
+                e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, in_out_Attributes->id, &frame );
+                IF(e) {
+                    goto fin;
+                }
+            }
+            source_frame.Width  = frame->width;
+            source_frame.Height = frame->height;
+            destination_frame.Width  = frame->width;
+            destination_frame.Height = frame->height;
+            source_rectangle.Left   = attribute->OffsetX;
+            source_rectangle.Top    = attribute->OffsetY;
+            source_rectangle.Right  = attribute->OffsetX + attribute->Width;
+            source_rectangle.Bottom = attribute->OffsetY + attribute->Height;
+            destination_rectangle.Left   = attribute->X;
+            destination_rectangle.Top    = attribute->Y;
+            destination_rectangle.Right  = attribute->X + attribute->Width;
+            destination_rectangle.Bottom = attribute->Y + attribute->Height;
+
+            e= GS_ToInFrame( &source_frame, &destination_frame,
+                             &source_rectangle, &destination_rectangle );
+            IF(e) {
+                goto fin;
+            }
+            if ( source_rectangle.Left > source_rectangle.Right ) {
+                is_show = false;
+            }
+
+
+            /* Call "R_VDC5_ChangeReadProcess" */
+            if ( is_show ) {
+                byte_t       *source_address;
+                int_fast32_t  offset_byte;
+
+                ASSERT_R( ! is_solid_color,  e=E_OTHERS; goto fin );
+
+                if ( is_interlace ) {
+                    source_address = frame->buffer_address[0];
+                    offset_byte = ( source_rectangle.Top / 2 ) * frame->stride;
+                } else {
+                    source_address = frame->buffer_address[ frame->show_buffer_index ];
+                    offset_byte = source_rectangle.Top * frame->stride;
+                }
+                offset_byte += source_rectangle.Left * frame->byte_per_pixel;
+                ASSERT_R( R_BYTE_PER_PIXEL_IsInteger( frame->byte_per_pixel ),
+                          e=E_OTHERS; goto fin );
+                attribute->OffsetByte = offset_byte;
+
+                change.gr_base = source_address + attribute->OffsetByte;
+            }
+            if ( change.gr_grc != NULL ) {
+                change_destination_rectangle.hs = destination_rectangle.Left + GS_LCD_CHn_DISP_HS;
+                change_destination_rectangle.vs = destination_rectangle.Top  + GS_LCD_CHn_DISP_VS;
+                change_destination_rectangle.hw = destination_rectangle.Right - destination_rectangle.Left + 1;
+                change_destination_rectangle.vw = destination_rectangle.Bottom - destination_rectangle.Top + 1;
+
+                change.width_read_fb = &change_source_rectangle;
+                change_source_rectangle.in_hw = change_destination_rectangle.hw;
+                change_source_rectangle.in_vw = change_destination_rectangle.vw;
+
+                if ( is_interlace ) {
+                    change_source_rectangle.in_vw /= 2;
+                }
+            }
+
+            if ( change_source_rectangle.in_hw < 3  ||  change_source_rectangle.in_vw == 0 ) {
+                is_show = false;
+            }
+
+            if ( ! is_show ) {
+                change_destination_rectangle.hs = GS_LCD_CHn_DISP_HS - 2;  /* out of visible */
+                change_destination_rectangle.vs = GS_LCD_CHn_DISP_VS;
+                change_destination_rectangle.hw = 3;
+                change_destination_rectangle.vw = 1;
+                change_source_rectangle.in_hw = 3;
+                change_source_rectangle.in_vw = 1;
+                attribute->OffsetByte = GS_OFFSET_BYTE_NOT_SHOW;
+            }
+
+            error_vdc = R_VDC5_ChangeReadProcess(
+                            self->screen_channel, layer->data_control_ID, &change );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+        if ( IS_ANY_BITS_SET( in_out_Attributes->flags, flags_of_window_position )  &&
+                IS_BIT_SET( in_out_Attributes->access, ACCESS_READ ) ) {
+            window_surfaces_attribute_t  *attribute = NULL;
+            /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+            ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, F_LAYER_ID ), e=E_OTHERS; goto fin );
+
+            e= window_surfaces_t__get_attribute( self, in_out_Attributes->id, &attribute );
+            IF(e) {
+                goto fin;
+            }
+
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_X ) ) {
+                in_out_Attributes->x = attribute->X;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_Y ) ) {
+                in_out_Attributes->y = attribute->Y;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_WIDTH ) ) {
+                in_out_Attributes->width = attribute->Width;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_HEIGHT ) ) {
+                in_out_Attributes->height = attribute->Height;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_X ) ) {
+                in_out_Attributes->offset_x = attribute->OffsetX;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_Y ) ) {
+                in_out_Attributes->offset_y = attribute->OffsetY;
+            }
+        }
+    }
+
+
+    /* Call "R_VDC5_CLUT" */
+    {
+        enum { flags_of_CLUT = F_LAYER_CLUT | F_LAYER_CLUT_COUNT };
+
+        if ( IS_ANY_BITS_SET( in_out_Attributes->flags, flags_of_CLUT ) ) {
+            vdc5_clut_t  clut_data;
+            enum { necessary_flags = flags_of_CLUT | F_LAYER_ID };
+
+            ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, necessary_flags ),
+                      e=E_OTHERS; goto fin );
+            ASSERT_R( IS_ANY_BITS_NOT_SET(
+                          in_out_Attributes->access,  ~ (bit_flags_fast32_t) ACCESS_WRITE ),
+                      e=E_OTHERS; goto fin );
+
+            clut_data.color_num = in_out_Attributes->CLUT_count;
+            clut_data.clut = (uint32_t *)( in_out_Attributes->CLUT );
+            error_vdc = R_VDC5_CLUT( self->screen_channel, layer->data_control_ID, &clut_data );
+            IF( error_vdc != VDC5_OK ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+    IF( IS_ANY_BITS_SET( in_out_Attributes->flags,
+                         ~( F_LAYER_ID | F_LAYER_LAYER_COLOR | F_LAYER_CLUT_COUNT | F_LAYER_CLUT |
+                            F_LAYER_X | F_LAYER_Y | F_LAYER_WIDTH | F_LAYER_HEIGHT |
+                            F_LAYER_OFFSET_X | F_LAYER_OFFSET_Y ) ) ) {
+        e=E_LIMITATION;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/* Section: Global */
+/**
+* @brief   Put "SourceRect" and "DestinationRect" into the frame.
+*
+* @param   SourceFrameBuffer gs_frame_width_height_t
+* @param   DestinationFrameBuffer gs_frame_width_height_t
+* @param   SourceRect gs_rectangle_t
+* @param   DestinationRect gs_rectangle_t
+* @return  Error Code. 0=No Error.
+*
+* @par Description
+*    - If out of frame then "SourceRect - >Left > SourceRect->Right".
+*/
+errnum_t  GS_ToInFrame(
+    gs_frame_width_height_t *SourceFrameBuffer,
+    gs_frame_width_height_t *DestinationFrameBuffer,
+    gs_rectangle_t *SourceRect,
+    gs_rectangle_t *DestinationRect )
+{
+    errnum_t  e;
+    int  src_top,  src_bottom,  dst_top,  dst_bottom;  /* top down coord */
+    int  diff;
+
+
+    /* fast culling by out of frame buffer horizontal */
+    if (      SourceRect->Left >= SourceFrameBuffer->Width ||
+              DestinationRect->Left >= DestinationFrameBuffer->Width ||
+              SourceRect->Right < 0 ||
+              DestinationRect->Right < 0 ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+
+    /* set "src_top", "src_bottom", "dst_top", "dst_bottom" */
+    src_top    = SourceRect->Top;
+    src_bottom = SourceRect->Bottom;
+    dst_top    = DestinationRect->Top;
+    dst_bottom = DestinationRect->Bottom;
+
+
+    /* fast culling by out of frame buffer vertical */
+    if ( src_top >= SourceFrameBuffer->Height ||
+            dst_top >= DestinationFrameBuffer->Height ||
+            src_bottom < 0 ||
+            dst_bottom < 0 ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+
+    /* set top >= 0 */
+    if ( src_top < 0 ) {
+        dst_top += - src_top;
+        src_top = 0;
+    }
+
+    if ( dst_top < 0 ) {
+        src_top += - dst_top;
+        dst_top = 0;
+    }
+
+
+    /* set bottom < frame height */
+    if ( src_bottom >= SourceFrameBuffer->Height ) {
+        diff = src_bottom - SourceFrameBuffer->Height + 1;
+        src_bottom -= diff;
+        dst_bottom -= diff;
+    }
+
+    if ( dst_bottom >= DestinationFrameBuffer->Height ) {
+        diff = dst_bottom - DestinationFrameBuffer->Height + 1;
+        src_bottom -= diff;
+        dst_bottom -= diff;
+    }
+
+
+    /* culling by out of frame buffer vertical for modified top and bottom */
+    if ( src_top < 0 ||
+            dst_top < 0 ||
+            src_bottom >= SourceFrameBuffer->Height ||
+            dst_bottom >= DestinationFrameBuffer->Height ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+
+    /* return from "src_top", "src_bottom", "dst_top", "dst_bottom" */
+    SourceRect->Top    = src_top;
+    SourceRect->Bottom = src_bottom;
+    DestinationRect->Top    = dst_top;
+    DestinationRect->Bottom = dst_bottom;
+
+
+    /* set left >= 0 */
+    if ( SourceRect->Left < 0 ) {
+        DestinationRect->Left += - SourceRect->Left;
+        SourceRect->Left = 0;
+    }
+
+    if ( DestinationRect->Left < 0 ) {
+        SourceRect->Left += - DestinationRect->Left;
+        DestinationRect->Left = 0;
+    }
+
+
+    /* set right < frame width */
+    if ( SourceRect->Right >= SourceFrameBuffer->Width ) {
+        diff = SourceRect->Right - SourceFrameBuffer->Width + 1;
+        SourceRect->Right      -= diff;
+        DestinationRect->Right -= diff;
+    }
+
+    if ( DestinationRect->Right >= DestinationFrameBuffer->Width ) {
+        diff = DestinationRect->Right - DestinationFrameBuffer->Width + 1;
+        SourceRect->Right      -= diff;
+        DestinationRect->Right -= diff;
+    }
+
+
+    /* culling by out of frame buffer horizontal for modified top and bottom */
+    if (      SourceRect->Left >= SourceFrameBuffer->Width ||
+              DestinationRect->Left >= DestinationFrameBuffer->Width ||
+              SourceRect->Right < 0 ||
+              DestinationRect->Right < 0 ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Class: vram_ex_stack_t
+************************************************************************/
+
+/***********************************************************************
+* Implement: R_VRAM_EX_STACK_Initialize
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Initialize( vram_ex_stack_t *self, void *NullConfig )
+{
+    errnum_t  e;
+    uint8_t  *address;
+    size_t    size;
+
+    R_UNREFERENCED_VARIABLE( NullConfig );
+
+    e= R_EXRAM_GetBigMemory( &address, &size );
+    IF(e) {
+        goto fin;
+    }
+
+    self->Start = address;
+    self->Over  = address + size;
+    self->StackPointer = self->Start;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_VRAM_EX_STACK_Alloc
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Alloc( vram_ex_stack_t *self, frame_buffer_t *in_out_FrameBuffer )
+{
+    return  alloc_VRAM_stack_sub( &self->StackPointer, self->Over, in_out_FrameBuffer );
+}
+
+
+/***********************************************************************
+* Implement: R_VRAM_EX_STACK_Free
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Free( vram_ex_stack_t *self, frame_buffer_t *frame_buffer )
+{
+    return  free_VRAM_stack_sub( &self->StackPointer, frame_buffer, self->Start );
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/RGA/src/window_surfaces_cpp.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,299 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_cpp.cpp
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.20 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: Window Surfaces for mbed style C++ API
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "window_surfaces.hpp"
+#include  "window_surfaces.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  GS_DEFAULT_INT_VALUE  0x7FFFFFFF
+#define  GS_DEFAULT_HEIGHT  -1
+#define  GS_DEFAULT_CLEAR_COLOR  0x00000100
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* ClassImplement: WindowSurfacesClass
+************************************************************************/
+
+/***********************************************************************
+* Implement: WindowSurfacesClass
+************************************************************************/
+WindowSurfacesClass::WindowSurfacesClass()
+{
+    this->_self = NULL;
+}
+
+
+/***********************************************************************
+* Implement: ~WindowSurfacesClass
+************************************************************************/
+WindowSurfacesClass::~WindowSurfacesClass()
+{
+    this->destroy();
+}
+
+
+/***********************************************************************
+* Implement: initialize
+************************************************************************/
+errnum_t  WindowSurfacesClass::initialize( WindowSurfacesConfigClass &in_out_config )
+{
+    this->_self = new  window_surfaces_t;
+    ASSERT_R( this->_self != NULL,  return  E_FEW_MEMORY );
+
+    in_out_config.flags =
+        F_WINDOW_SURFACES_PIXEL_FORMAT |
+        F_WINDOW_SURFACES_LAYER_COUNT |
+        F_WINDOW_SURFACES_BACKGROUND_COLOR |
+        F_WINDOW_SURFACES_BUFFER_HEIGHT;
+
+    if ( in_out_config.buffer_height == GS_DEFAULT_HEIGHT ) {
+        in_out_config.flags &= ~F_WINDOW_SURFACES_BUFFER_HEIGHT;
+    }
+    if ( in_out_config.background_color.Value == GS_DEFAULT_CLEAR_COLOR ) {
+        in_out_config.flags &= ~F_WINDOW_SURFACES_BACKGROUND_COLOR;
+    }
+
+    R_WINDOW_SURFACES_InitConst( this->_self );
+
+    return  R_WINDOW_SURFACES_Initialize( this->_self,
+                                          (window_surfaces_config_t *) &in_out_config );
+}
+
+
+/***********************************************************************
+* Implement: destroy
+************************************************************************/
+void  WindowSurfacesClass::destroy()
+{
+    if ( this->_self != NULL ) {
+        errnum_t  e = R_WINDOW_SURFACES_Finalize( this->_self,  0 );
+        ASSERT_R( e == 0,  R_NOOP() );
+    }
+}
+
+
+/***********************************************************************
+* Implement: get_layer_frame_buffer
+************************************************************************/
+errnum_t  WindowSurfacesClass::get_layer_frame_buffer( int_fast32_t const  layer_num,  frame_buffer_t **const  out_frame_buffer )
+{
+    return  R_WINDOW_SURFACES_GetLayerFrameBuffer( this->_self,  layer_num,  out_frame_buffer );
+}
+
+
+/***********************************************************************
+* Implement: swap_buffers
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  WindowSurfacesClass::swap_buffers( int_fast32_t const  layer_num,  Canvas2D_ContextClass  &context )
+{
+    return  R_WINDOW_SURFACES_SwapBuffers( this->_self,  layer_num,  context.c_LanguageContext );
+}
+#else
+errnum_t  WindowSurfacesClass::swap_buffers( int_fast32_t const  layer_num,  const void *const  null_context )
+{
+    return  R_WINDOW_SURFACES_SwapBuffers( this->_self,  layer_num,  null_context );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: swap_buffers_start
+************************************************************************/
+errnum_t  WindowSurfacesClass::swap_buffers_start( int_fast32_t const  layer_num,  r_ospl_async_t *async )
+{
+    return  R_WINDOW_SURFACES_SwapBuffersStart( this->_self,  layer_num,  async );
+}
+
+
+/***********************************************************************
+* Implement: wait_for_v_sync
+************************************************************************/
+errnum_t  WindowSurfacesClass::wait_for_v_sync( int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum )
+{
+    return  R_WINDOW_SURFACES_WaitForVSync( this->_self,  swap_interval,  is_1_v_sync_at_minimum );
+}
+
+
+/***********************************************************************
+* Implement: alloc_offscreen_stack
+************************************************************************/
+errnum_t  WindowSurfacesClass::alloc_offscreen_stack( frame_buffer_t *const  in_out_frame_buffer )
+{
+    return  R_WINDOW_SURFACES_AllocOffscreenStack( this->_self,  in_out_frame_buffer );
+}
+
+
+/***********************************************************************
+* Implement: free_offscreen_stack
+************************************************************************/
+errnum_t  WindowSurfacesClass::free_offscreen_stack( const frame_buffer_t *const  frame_buffer )
+{
+    return  R_WINDOW_SURFACES_FreeOffscreenStack( this->_self,  frame_buffer );
+}
+
+
+/***********************************************************************
+* Implement: do_message_loop
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  WindowSurfacesClass::do_message_loop()
+{
+    return  R_WINDOW_SURFACES_DoMessageLoop( this->_self );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: access_layer_attributes
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  WindowSurfacesClass::access_layer_attributes( LayerAttributes &in_out_Attributes )
+{
+    in_out_Attributes.flags =
+        F_LAYER_ID |
+        F_LAYER_PRIORITY |
+        F_LAYER_X |
+        F_LAYER_Y |
+        F_LAYER_WIDTH |
+        F_LAYER_HEIGHT |
+        F_LAYER_OFFSET_X |
+        F_LAYER_OFFSET_Y |
+        F_LAYER_CLUT |
+        F_LAYER_CLUT_COUNT;
+
+    if ( in_out_Attributes.id == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_ID;
+    }
+    if ( in_out_Attributes.priority == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_PRIORITY;
+    }
+    if ( in_out_Attributes.x == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_X;
+    }
+    if ( in_out_Attributes.y == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_Y;
+    }
+    if ( in_out_Attributes.width == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_WIDTH;
+    }
+    if ( in_out_Attributes.height == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_HEIGHT;
+    }
+    if ( in_out_Attributes.offset_x == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_OFFSET_X;
+    }
+    if ( in_out_Attributes.offset_y == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_OFFSET_Y;
+    }
+    if ( in_out_Attributes.CLUT == NULL ) {
+        in_out_Attributes.flags &= ~F_LAYER_CLUT;
+    }
+    if ( in_out_Attributes.CLUT_count == 0 ) {
+        in_out_Attributes.flags &= ~F_LAYER_CLUT_COUNT;
+    }
+
+    return  R_WINDOW_SURFACES_AccessLayerAttributes( this->_self,
+            (layer_attributes_t *) &in_out_Attributes );
+}
+#endif
+
+
+/***********************************************************************
+* ClassImplement: WindowSurfacesConfigClass
+************************************************************************/
+
+/***********************************************************************
+* Implement: WindowSurfacesConfigClass
+************************************************************************/
+WindowSurfacesConfigClass::WindowSurfacesConfigClass()
+{
+    this->flags = 0;
+    this->pixel_format = PIXEL_FORMAT_ARGB8888;
+    this->layer_count = 1;
+    this->buffer_height = GS_DEFAULT_HEIGHT;
+    this->background_color.Value = GS_DEFAULT_CLEAR_COLOR;
+}
+
+
+/***********************************************************************
+* ClassImplement: LayerAttributes
+************************************************************************/
+
+/***********************************************************************
+* Implement: LayerAttributes
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+LayerAttributes::LayerAttributes()
+{
+    this->access = ACCESS_READ;
+    this->flags = 0;
+    this->id       = GS_DEFAULT_INT_VALUE;
+    this->priority = GS_DEFAULT_INT_VALUE;
+    this->is_show = false;
+    this->is_color_key = false;
+    this->color_key.Value = GS_DEFAULT_CLEAR_COLOR;
+    this->layer_color.Value = 0;
+    this->x        = GS_DEFAULT_INT_VALUE;
+    this->y        = GS_DEFAULT_INT_VALUE;
+    this->width    = GS_DEFAULT_INT_VALUE;
+    this->height   = GS_DEFAULT_INT_VALUE;
+    this->offset_x = GS_DEFAULT_INT_VALUE;
+    this->offset_y = GS_DEFAULT_INT_VALUE;
+    this->CLUT     = NULL;
+    this->CLUT_count = 0;
+}
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/inc/clib_drivers.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,81 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_H
+#define  CLIB_DRIVERS_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "clib_drivers_typedef.h"
+
+/* for Inline Functions */
+#include  "r_multi_compiler.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+errnum_t  R_int32_t_to_int8_t( int32_t input, int8_t *output );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+/* Inline Functions */
+#include  "clib_drivers_inline.h"
+
+#endif  /* CLIB_DRIVERS_H */
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/inc/clib_drivers_config.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,127 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers_config.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_CONFIG_H
+#define  CLIB_DRIVERS_CONFIG_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  IS_SUPPORT_SAME_TYPEDEF
+* @brief  Whether compiler suppots duplicated same typedef.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_SUPPORT_SAME_TYPEDEF  1
+
+
+/**
+* @def  LIB_STATIC
+* @brief  Public library is complied by set "LIB_STATIC" static.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifndef LIB_STATIC
+#define LIB_STATIC
+#endif
+
+
+/**
+* @def  static_release
+* @brief  Hide if release version.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifndef R_OSPL_NDEBUG
+#define  static_release  static
+#else
+#define  static_release
+#endif
+
+
+/***********************************************************************
+* Macros: BYTE_ENDIAN
+*    BYTE_ENDIAN
+*
+*    : BYTE_LITTLE_ENDIAN - 1
+*    : BYTE_BIG_ENDIAN    - 2
+************************************************************************/
+#define  BYTE_ENDIAN           BYTE_LITTLE_ENDIAN
+#define  BYTE_LITTLE_ENDIAN    1
+#define  BYTE_BIG_ENDIAN       2
+
+
+/***********************************************************************
+* Macros: BIT_FIELD_ENDIAN
+*    BIT_FIELD_ENDIAN
+*
+*    : BIT_FIELD_LITTLE_ENDIAN - 1
+*    : BIT_FIELD_BIG_ENDIAN    - 2
+************************************************************************/
+#define  BIT_FIELD_ENDIAN           BIT_FIELD_LITTLE_ENDIAN
+#define  BIT_FIELD_LITTLE_ENDIAN    1
+#define  BIT_FIELD_BIG_ENDIAN       2
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_DRIVERS_CONFIG_H */
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/inc/clib_drivers_inline.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,446 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers_inline.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_INLINE_H
+#define  CLIB_DRIVERS_INLINE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+INLINE errnum_t  R_int_t_to_int8_t( int_t input, int8_t *output )
+{
+    return  R_int32_t_to_int8_t( input, output );
+}
+
+
+/**
+* @brief   Fast mod operation
+*
+* @param   value Left operand
+* @return  value % N
+*
+* @par Description
+* - This is shared description of
+*   R_Mod_2s, R_Mod_4s, R_Mod_8s, R_Mod_16s, R_Mod_32s, R_Mod_64s,
+*   R_Mod_2u, R_Mod_4u, R_Mod_8u, R_Mod_16u, R_Mod_32u, R_Mod_64u.
+* - Porting layer of fast % operator.
+* - MISRA & IPA SEC confirmed version.
+* - Minus value is expected 2's complement.
+* - Not same C99 % operator.
+*   - Sample: R_Mod_4s( - 7 ) == +1.  Sample: -7 % 4 == -3
+*/
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_2s( int_fast32_t const  value )
+{
+    enum { mask = 1 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_4s( int_fast32_t const  value )
+{
+    enum { mask = 3 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_8s( int_fast32_t const  value )
+{
+    enum { mask = 7 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_16s( int_fast32_t const  value )
+{
+    enum { mask = 15 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_32s( int_fast32_t const  value )
+{
+    enum { mask = 31 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_64s( int_fast32_t const  value )
+{
+    enum { mask = 63 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_2u( uint_fast32_t const  value )
+{
+    return  ((value) & 1u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_4u( uint_fast32_t const  value )
+{
+    return  ((value) & 3u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_8u( uint_fast32_t const  value )
+{
+    return  ((value) & 7u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_16u( uint_fast32_t const  value )
+{
+    return  ((value) & 15u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_32u( uint_fast32_t const  value )
+{
+    return  ((value) & 31u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_64u( uint_fast32_t const  value )
+{
+    return  ((value) & 63u);
+}
+
+
+/**
+* @brief   Fast ceil operation
+*
+* @param   value Left operand
+* @return  Ceil( value / N )
+*
+* @par Description
+* - This is shared description of
+*   R_Ceil_2s, R_Ceil_4s, R_Ceil_8s, R_Ceil_16s, R_Ceil_32s, R_Ceil_64s,
+*   R_Ceil_2u, R_Ceil_4u, R_Ceil_8u, R_Ceil_16u, R_Ceil_32u, R_Ceil_64u.
+* - Porting layer of fast ceil operation.
+* - Function version is confirmed with MISRA & IPA SEC.
+*/
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_2s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 1;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_4s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 3;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_8s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 7;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_16s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 15;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_32s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 31;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_64s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 63;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_2u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 1;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_4u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 3;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_8u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 7;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_16u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 15;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_32u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 31;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_64u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 63;
+    return  (((value)+mask)&~mask);
+}
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_DRIVERS_INLINE_H */
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/inc/clib_drivers_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,206 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_TYPEDEF_H
+#define  CLIB_DRIVERS_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  bool32_t
+* @brief  Boolean type in 32 bit variable. This is not C99.
+*/
+typedef  unsigned int    bool32_t;
+
+
+/**
+* @typedef  bool16_t
+* @brief  Boolean type in 16 bit variable. This is not C99.
+*/
+typedef  unsigned short  bool16_t;
+
+
+/**
+* @typedef  bool8_t
+* @brief  Boolean type in 8 bit variable. This is not C99.
+*/
+typedef  unsigned char   bool8_t;
+
+
+/**
+* @typedef  IntBoxType
+* @brief  IntBoxType
+*/
+typedef struct st_IntBoxType  IntBoxType;
+struct st_IntBoxType {
+    int  MinX;
+    int  MinY;
+    int  Width;
+    int  Height;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  DUMMY_INITIAL_VALUE
+* @brief  Avoids not right warning of not initialized.
+*
+* @par Description
+* - 0xDEDEDEDE means "not initialized".
+* - Disable VC++ warning C4701 : local variable may be used without having
+*   been initialized
+* - See @ref DUMMY_INITIAL_VALUE_8BIT, @ref DUMMY_INITIAL_VALUE_16BIT
+*/
+#ifndef  R_OSPL_NDEBUG
+#define  DUMMY_INITIAL_VALUE  0xDEDEDEDE
+#else
+enum { DUMMY_INITIAL_VALUE = 0 };
+#endif
+
+
+/**
+* @def  DUMMY_INITIAL_VALUE_8BIT
+* @brief  <DUMMY_INITIAL_VALUE> for 8 bit integer.
+*/
+#ifndef  R_OSPL_NDEBUG
+enum { DUMMY_INITIAL_VALUE_8BIT  = 0xDE };
+#else
+enum { DUMMY_INITIAL_VALUE_8BIT  = 0 };
+#endif
+
+
+/**
+* @def  DUMMY_INITIAL_VALUE_16BIT
+* @brief  <DUMMY_INITIAL_VALUE> for 16 bit integer.
+*/
+#ifndef  R_OSPL_NDEBUG
+enum { DUMMY_INITIAL_VALUE_16BIT = 0xDEDE };
+#else
+enum { DUMMY_INITIAL_VALUE_16BIT = 0 };
+#endif
+
+
+/**
+* @def  U8_255
+* @brief  Magic number of generally well known used.
+*    unsigned 8bit max value = UINT8_MAX
+*/
+#define  U8_255   255
+
+
+/**
+* @def  R_CEIL_2U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_2U( value )   (((value)+1)&~1)
+
+
+/**
+* @def  R_CEIL_4U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_4U( value )   (((value)+3)&~3)
+
+
+/**
+* @def  R_CEIL_8U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_8U( value )   (((value)+7)&~7)
+
+
+/**
+* @def  R_CEIL_16U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_16U( value )  (((value)+15)&~15)
+
+
+/**
+* @def  R_CEIL_32U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_32U( value )  (((value)+31)&~31)
+
+
+/**
+* @def  R_CEIL_64U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_64U( value )  (((value)+63)&~63)
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_DRIVERS_TYPEDEF_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/inc/clib_registers.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,321 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_registers.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_REGISTERS_H
+#define  CLIB_REGISTERS_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/******************************************************************************
+Inline Functions
+******************************************************************************/
+
+
+/**
+* @brief   CPG unit of RZ/A1H.
+*
+* @par Parameters
+*    None
+* @return  Pointer to CPG structure.
+*/
+INLINE struct st_cpg  *R_Get_CPG_Base(void) {
+    /* ->QAC 0306 */
+#if IODEFINE_H_VERSION >= 100
+    return  &CPG;
+#else
+    return  (struct st_cpg *) &CPG;
+#endif
+    /* <-QAC 0306 */
+}
+
+
+/***********************************************************************
+* Group: Register_Access
+************************************************************************/
+
+/**
+* @brief   Set a value to register bit field.
+*
+* @param   in_out_Register Address of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Writing value
+* @return  None.
+*
+* @par Description
+*    Bit width is got from "RegisterName".
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_SET_REGISTER_BIT_FIELD( \
+		in_out_Register, RegisterName, BitName, Value ) \
+	R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		in_out_Register, RegisterName, BitName, Value, \
+		DRV__BIT_WIDTH__##RegisterName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Set a value to register bit field with width parameter.
+*
+* @param   in_out_Register Address of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Writing value
+* @param   BitWidth BitWidth
+* @return  None.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		in_out_Register, RegisterName, BitName, Value, BitWidth ) \
+	R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
+		in_out_Register, RegisterName##__##BitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
+		in_out_Register, RegisterBitName, Value, BitWidth ) \
+	R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
+		in_out_Register, RegisterBitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
+		in_out_Register, RegisterBitName, Value, BitWidth ) \
+	R_OSPL_SET_TO_##BitWidth##_BIT_REGISTER( \
+		(volatile uint##BitWidth##_t*)(in_out_Register), \
+		DRV__MASK##BitWidth##__##RegisterBitName, \
+		DRV__SHIFT__##RegisterBitName, \
+		(uint##BitWidth##_t)(Value) )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Get a value from register bit field.
+*
+* @param   RegisterValue Value of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @return  Value of shifted bit field.
+*
+* @par Description
+*    Bit width is got from "RegisterName".
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_GET_REGISTER_BIT_FIELD( \
+		RegisterValue, RegisterName, BitName ) \
+	R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterValue, RegisterName, BitName, \
+		DRV__BIT_WIDTH__##RegisterName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Get a value from register bit field with width parameter.
+*
+* @param   RegisterValue Value of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   BitWidth BitWidth
+* @return  Value of shifted bit field.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterValue, RegisterName, BitName, BitWidth ) \
+	R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
+		RegisterValue, RegisterName##__##BitName, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
+		RegisterValue, RegisterBitName, BitWidth ) \
+	R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
+		RegisterValue, RegisterBitName, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
+		RegisterValue, RegisterBitName, BitWidth ) \
+	R_OSPL_GET_FROM_##BitWidth##_BIT_REGISTER( \
+		(volatile const uint##BitWidth##_t*) &(RegisterValue), \
+		DRV__MASK##BitWidth##__##RegisterBitName, \
+		DRV__SHIFT__##RegisterBitName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Returns whether specified value is overflowed from the bit field.
+*
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Checking value
+* @return  Whether specified value is overflowed.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD( \
+		RegisterName, BitName, Value ) \
+	R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterName, BitName, Value, DRV__BIT_WIDTH__##RegisterName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Returns whether specified value is overflowed from the bit field.
+*
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Checking value
+* @param   BitWidth BitWidth
+* @return  Whether specified value is overflowed.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterName, BitName, Value, BitWidth ) \
+	R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
+		RegisterName##__##BitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
+		RegisterBitName, Value, BitWidth ) \
+	R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
+		RegisterBitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
+		RegisterBitName, Value, BitWidth ) \
+	R_DRV_IsOverflowBitField##BitWidth##_Sub( \
+		DRV__MASK##BitWidth##__##RegisterBitName, \
+		DRV__SHIFT__##RegisterBitName, \
+		Value )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/* Sub function */
+/* : R_DRV_IsOverflowBitField32_Sub */
+/* : R_DRV_IsOverflowBitField16_Sub */
+/* : R_DRV_IsOverflowBitField8_Sub */
+INLINE bool_t  R_DRV_IsOverflowBitField32_Sub( uint32_t const  Mask,
+        int_fast32_t const  Shift,  uint32_t const  Value )
+{
+    return  ( ( (uint32_t)(Value) &
+                ~( (uint32_t)(Mask) >> (Shift) ) )
+              != 0u );
+}
+
+INLINE bool_t  R_DRV_IsOverflowBitField16_Sub( uint16_t const  Mask,
+        int_fast32_t const  Shift,  uint16_t const  Value )
+{
+    return  ( ( (uint_fast16_t)(Value) &
+                ~( (uint_fast16_t)(Mask) >> (Shift) ) )
+              != 0u );
+}
+
+INLINE bool_t  R_DRV_IsOverflowBitField8_Sub( uint8_t const  Mask,
+        int_fast32_t const  Shift, uint8_t const  Value )
+{
+    return  ( ( (uint_fast8_t)(Value) &
+                ~( (uint_fast8_t)(Mask) >> (Shift) ) )
+              != 0u );
+}
+
+
+/**
+* @def  CPG
+* @brief  CPG
+*/
+/* 0xFCFE0438 */
+
+#define  DRV__BIT_WIDTH__STBCR9  8
+
+enum { /*uint8_t */       DRV__MASK8__STBCR9__MSTP91 = 0x02 };  /* VDC5-0, LVDS */
+enum { /*uint8_t */       DRV__MASK8__STBCR9__MSTP90 = 0x01 };  /* VDC5-1 */
+
+enum { /* int_fast32_t */  DRV__SHIFT__STBCR9__MSTP91 =  1 };
+enum { /* int_fast32_t */  DRV__SHIFT__STBCR9__MSTP90 =  0 };
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_REGISTERS_H */
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/inc/clib_samples.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,77 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: clib_samples.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 40 $
+* $Date:: 2014-03-20 18:46:41 +0900#$
+* Description: Sample API
+*******************************************************************************/
+
+
+#ifndef  CLIB_SAMLES_H
+#define  CLIB_SAMLES_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+    /******************************************************************************
+    Typedef definitions
+    ******************************************************************************/
+    /* In "clib_samples_typedef.h" */
+
+    /******************************************************************************
+    Macro definitions
+    ******************************************************************************/
+    /* In "clib_samples_typedef.h" */
+
+    /******************************************************************************
+    Variable Externs
+    ******************************************************************************/
+    /* In "clib_samples_typedef.h" */
+
+    /******************************************************************************
+    Functions Prototypes
+    ******************************************************************************/
+
+    errnum_t  R_Sample_GetBigMemory( uint8_t **const  out_Address,  size_t *const  out_Size );
+
+#if IS_VDC_SAMPLE_VRAM_USED
+    errnum_t  R_Sample_GetBigMemory_FromVDC_Sample( void * /*<type**>*/ out_Address, size_t *out_Size );
+#endif
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/inc/clib_samples_private.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,56 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: window_surfaces.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* Description  : Sample API
+*******************************************************************************/
+
+#ifndef  CLIB_SAMPLES_PRIVATE_H
+#define  CLIB_SAMPLES_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+void  R_MEMORY_SECTION_GetMemory_ClibSamplesC( uint8_t **out_Address,  size_t *out_Size );
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/src/clib_drivers.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,169 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code.
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "clib_drivers.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_int32_t_to_int8_t( int32_t const  input, int8_t *const  output )
+{
+    errnum_t  e;
+
+    IF ( (input < INT8_MIN)  ||  (input > INT8_MAX) )  {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( output == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    *output = (int8_t) input;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_int32_t_to_int16_t( int32_t input, int16_t *output )
+{
+    IF ( input < -32768  ||  input > 32767 ) {
+        return  E_OTHERS;
+    }
+
+    *output = (int16_t) input;
+    return  0;
+}
+
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_int32_t_to_uint8_t( int32_t input, uint8_t *output )
+{
+    IF ( input < 0  ||  input > 255 ) {
+        return  E_OTHERS;
+    }
+
+    *output = (uint8_t) input;
+    return  0;
+}
+
+
+/**
+* @brief   Returns whether specified value has 1 bit only 1.
+*
+* @param   Value Input value
+* @return  Returns whether specified value has 1 bit only 1.
+*/
+bool_t  Is1bitOnlyInt( uint32_t Value )
+{
+    if ( (Value & 0x0000FFFF) == 0 ) {
+        Value >>= 16;
+    }
+    if ( (Value & 0x000000FF) == 0 ) {
+        Value >>=  8;
+    }
+    if ( (Value & 0x0000000F) == 0 ) {
+        Value >>=  4;
+    }
+    if ( (Value & 0x00000003) == 0 ) {
+        Value >>=  2;
+    }
+    if ( (Value & 0x00000001) == 0 ) {
+        Value >>=  1;
+    }
+    return  ( Value == 1 );
+}
+
+
+/**
+* @brief   Get whether 2 "IntBoxType"s are same area.
+*
+* @param   in_BoxA A box
+* @param   in_BoxB Other box
+* @param   out_IsSame Whether 2 "IntBoxType"s are same area.
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  IntBoxType_isSame( const IntBoxType *in_BoxA, const IntBoxType *in_BoxB, bool_t *out_IsSame )
+{
+    *out_IsSame = (
+                      in_BoxA->MinX   == in_BoxB->MinX  &&
+                      in_BoxA->MinY   == in_BoxB->MinY  &&
+                      in_BoxA->Width  == in_BoxB->Width  &&
+                      in_BoxA->Height == in_BoxB->Height );
+
+    return  0;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/TARGET_RZA1H/common/src/clib_samples.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: clib_samples.c $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 52 $
+* $Date:: 2014-03-20 18:41:05 +0900#$
+* Description: Sample functions
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+#include  "clib_samples.h"
+#if ! IS_VDC_SAMPLE_VRAM_USED
+#include  "clib_samples_private.h"
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: [R_Sample_GetBigMemory]
+* Description  :
+* Arguments    :
+* Return Value : Error code, 0=No error
+******************************************************************************/
+errnum_t  R_Sample_GetBigMemory( uint8_t **const  out_Address,  size_t *const  out_Size )
+{
+#if IS_VDC_SAMPLE_VRAM_USED
+    errnum_t          e;
+    static uint8_t   *address;
+    static size_t     memory_size;
+
+    IF_DQ( out_Address == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Size    == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    if ( address == NULL ) {
+        e= R_Sample_GetBigMemory_FromVDC_Sample( &address, &memory_size );
+        IF(e!=0) {
+            goto fin;
+        }
+    }
+    *out_Address = address;
+    *out_Size    = memory_size;
+
+    e=0;
+fin:
+    return  e;
+#else
+    R_MEMORY_SECTION_GetMemory_ClibSamplesC( out_Address, out_Size );
+    return  0;
+#endif
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/config/Project_Config.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,75 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: Project_Config.h $
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+* Description  : This file is for drivers and applications
+******************************************************************************/
+
+#ifndef PROJECT_CONFIG_H
+#define PROJECT_CONFIG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/* This file must be included at first of source file */
+/* Include configuration header files of drivers and applications */
+/* The #include parameter must be not depended on include path for other projects */
+#include  "Project_Config_Sub.h"
+#include  "../ospl/inc/r_ospl_config.h"
+#if defined(TARGET_RZA1H) /* mbed */
+#include  "../common/inc/clib_drivers_config.h"
+#include  "../RGA/inc/RGA_Config.h"
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/config/Project_Config_Sub.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,124 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: Project_Config.h $
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+* Description  : This file is for drivers and applications
+******************************************************************************/
+
+#ifndef PROJECT_CONFIG_SUB_H
+#define PROJECT_CONFIG_SUB_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  IS_RZ_A1_BSP_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_RZ_A1_BSP_USED  1
+
+
+/**
+* @def  IS_CMSIS_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_CMSIS_USED  1
+
+
+/**
+* @def  IS_RTX_USED
+* @brief  0 or 1. Not CMSIS API.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_RTX_USED  1
+
+
+/**
+* @def  IS_MBED_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_MBED_USED  1
+
+
+/**
+* @def  IS_VDC_SAMPLE_VRAM_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_VDC_SAMPLE_VRAM_USED  0
+
+
+/**
+* @def  R_ARM
+* @brief  ARM core = 1, otherwise = not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_ARM  1
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* PROJECT_CONFIG_SUB_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/inc/JPEG_Converter.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,215 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          JPEG_Converter.h
+* @brief         JCU API
+******************************************************************************/
+
+#ifndef JPEG_CONVERTER_H
+#define JPEG_CONVERTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/** A class to communicate a JCU
+ *
+ */
+class JPEG_Converter {
+
+public:
+    /*! @enum jpeg_conv_error_t
+        @brief Error codes
+     */
+    typedef enum {
+        JPEG_CONV_OK              =  0, /*!< Normal termination      */
+        JPEG_CONV_JCU_ERR         = -1, /*!< JCU driver error        */
+        JPEG_CONV_FORMA_ERR       = -2, /*!< Not support format      */
+        JPEG_CONV_PARAM_ERR       = -3, /*!< Parameter error         */
+        JPEG_CONV_BUSY            = -4, /*!< JCU Busy                */
+        JPEG_CONV_PARAM_RANGE_ERR = -7, /*!< Parameter range error   */
+    } jpeg_conv_error_t;
+
+    /*! @enum wr_rd_swa_t
+        @brief Write/Read image pixcel frame buffer swap setting
+     */
+    typedef enum {
+        WR_RD_WRSWA_NON        = 0,     /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+        WR_RD_WRSWA_8BIT       = 1,     /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+        WR_RD_WRSWA_16BIT      = 2,     /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+        WR_RD_WRSWA_16_8BIT    = 3,     /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+        WR_RD_WRSWA_32BIT      = 4,     /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+        WR_RD_WRSWA_32_8BIT    = 5,     /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+        WR_RD_WRSWA_32_16BIT   = 6,     /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+        WR_RD_WRSWA_32_16_8BIT = 7,     /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    } wr_rd_swa_t;
+
+    /*! @enum wr_rd_format_t
+        @brief Write/Read image pixcel format selects
+    */
+    typedef enum {
+        WR_RD_YCbCr422 = 0x00,          /*!< YCbCr422 (2byte / px)  */
+        WR_RD_ARGB8888 = 0x01,          /*!< ARGB8888 (4byte / px)  */
+        WR_RD_RGB565   = 0x02,          /*!< RGB565   (2byte / px)  */
+    } wr_rd_format_t;
+
+    /*! @enum sub_sampling_t
+        @brief Thinning output image selects
+    */
+    typedef enum {
+        SUB_SAMPLING_1_1 = 0x00,        /*!< Thinning output image to 1/1 */
+        SUB_SAMPLING_1_2 = 0x01,        /*!< Thinning output image to 1/2 */
+        SUB_SAMPLING_1_4 = 0x02,        /*!< Thinning output image to 1/4 */
+        SUB_SAMPLING_1_8 = 0x03         /*!< Thinning output image to 1/8 */
+    } sub_sampling_t;
+
+    /*! @enum cbcr_offset_t
+        @brief Cb/Cr range selects for decode
+    */
+    typedef enum {
+        CBCR_OFFSET_0   = 0x00,         /*!< Cb/Cr range -128 to 127 (all format used) */
+        CBCR_OFFSET_128 = 0x01,         /*!< Cb/Cr range    0 to 255 (Default and YCbCr format only used)      */
+    } cbcr_offset_t;
+
+    /*! @struct bitmap_buff_info_t
+        @brief Bitmap data setting struct
+     */
+    typedef struct {
+        int32_t         width;              /*!< width           width of bitmap data   */
+        int32_t         height;             /*!< height          height of bitmap data  */
+        wr_rd_format_t  format;             /*!< format          format of bitmap data  */
+        void*           buffer_address;     /*!< buffer_address  address of bitmap data */
+    } bitmap_buff_info_t;
+
+    /** Constructor method of JPEG converter(encode/decode)
+     */
+    JPEG_Converter();
+
+    /** Destructor method of JPEG converter(encode/decode)
+     */
+    virtual ~JPEG_Converter();
+
+    /*! @struct DecodeOptions_t
+        @brief Decode option setting
+     */
+    struct decode_options_t {
+        sub_sampling_t  vertical_sub_sampling;                      /*!< Vertical sampling setting */
+        sub_sampling_t  horizontal_sub_sampling;                    /*!< Horizontal sampling setting */
+        cbcr_offset_t   output_cb_cr_offset;                        /*!< Output data Cb/Cr range setting */
+        wr_rd_swa_t     output_swapsetting;                         /*!< Output data swap setteing */
+        int32_t         alpha;                                      /*!< alpha setting for ARGB8888 */
+        bool            check_jpeg_format;                          /*!< Flag check JPEG data format : Setting NULL does not check JPEG format when decoding */
+        void (* p_DecodeCallBackFunc)(jpeg_conv_error_t err_code);  /*!< Callback function address */
+
+        decode_options_t() {
+            vertical_sub_sampling   = SUB_SAMPLING_1_1;
+            horizontal_sub_sampling = SUB_SAMPLING_1_1;
+            output_cb_cr_offset     = CBCR_OFFSET_128;
+            output_swapsetting      = WR_RD_WRSWA_8BIT;
+            alpha                   = 0;
+            check_jpeg_format       = false;
+            p_DecodeCallBackFunc    = NULL;
+        }
+    };
+
+    /*! @struct encode_options_t
+        @brief Encode option setting
+     */
+    struct encode_options_t {
+        int32_t         DRI_value;              /*!< DRI setting */
+        int32_t         width;                  /*!< Encode width */
+        int32_t         height;                 /*!< Encode height */
+        cbcr_offset_t   input_cb_cr_offset;     /*!< Input data Cb/Cr range setting */
+        wr_rd_swa_t     input_swapsetting;      /*!< Input data swap setteing */
+        size_t          encode_buff_size;       /*!< Encode buffer size : Setting 0 does not the buffer size confirmation of when encoding  */
+        void*           quantization_table_Y;   /*!< Quantization table address(Y) */
+        void*           quantization_table_C;   /*!< Quantization table address(C) */
+        void*           huffman_table_Y_DC;     /*!< Huffman Table address(Y DC) */
+        void*           huffman_table_C_DC;     /*!< Huffman Table address(C DC) */
+        void*           huffman_table_Y_AC;     /*!< Huffman Table address(Y AC) */
+        void*           huffman_table_C_AC;     /*!< Huffman Table address(C AC) */
+        void (* p_EncodeCallBackFunc)(jpeg_conv_error_t err_code);  /*!< Callback function address */
+
+        encode_options_t() {
+            DRI_value           = 0;
+            width               = 0;
+            height              = 0;
+            input_cb_cr_offset  = CBCR_OFFSET_128;
+            input_swapsetting   = WR_RD_WRSWA_8BIT;
+            encode_buff_size    = 0;
+            quantization_table_Y = NULL;
+            quantization_table_C = NULL;
+            huffman_table_Y_DC = NULL;
+            huffman_table_C_DC = NULL;
+            huffman_table_Y_AC = NULL;
+            huffman_table_C_AC = NULL;
+            p_EncodeCallBackFunc = NULL;
+        }
+    };
+
+    /** Decode JPEG to rinear data
+     *
+     * @param[in]     void*                 pJpegBuff       : Input JPEG data address
+     * @param[in/out] bitmap_buff_info_t*   psOutputBuff    : Output bitmap data address
+     * @param[in]     decode_options_t*     pOptions        : Decode option(Optional)
+     * @return JPEG_CONV_OK              = success
+     *         JPEG_CONV_JCU_ERR         = failure (JCU error)
+     *         JPEG_CONV_FORMA_ERR       = failure (data format error)
+     *         JPEG_CONV_PARAM_ERR       = failure (input parameter error)
+     *         JPEG_CONV_PARAM_RANGE_ERR = failure (input parameter range error)
+     */
+    JPEG_Converter::jpeg_conv_error_t decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff );
+    JPEG_Converter::jpeg_conv_error_t decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff, decode_options_t* pOptions );
+
+    /** Encode rinear data to JPEG
+     *
+     * @param[in]   bitmap_buff_info_t*     psInputBuff     : Input bitmap data address
+     * @param[out]  void*                   pJpegBuff       : Output JPEG data address
+     * @param[out]  size_t*                 pEncodeSize     : Encode size address
+     * @param[in]   encode_options_t*       pOptions[IN]    : Encode option(Optional)
+     * @return JPEG_CONV_OK              = success
+     *         JPEG_CONV_JCU_ERR         = failure (JCU error)
+     *         JPEG_CONV_FORMA_ERR       = failure (data format error)
+     *         JPEG_CONV_PARAM_ERR       = failure (input parameter error)
+     *         JPEG_CONV_PARAM_RANGE_ERR = failure (input parameter range error)
+     */
+    JPEG_Converter::jpeg_conv_error_t encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize );
+    JPEG_Converter::jpeg_conv_error_t encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize, encode_options_t* pOptions );
+
+    /** Set encode quality
+     *
+     * @param[in]   uint8_t                  qual           : Encode quality (1 <= qual <= 100)
+     * @return JPEG_CONV_OK              = success
+     *         JPEG_CONV_PARAM_RANGE_ERR = failure (input parameter range error)
+     */
+    JPEG_Converter::jpeg_conv_error_t SetQuality(const uint8_t qual);
+
+private:
+
+};
+
+#endif  /* JPEG_CONVERTER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/inc/converter_wrapper.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,101 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         converter_wrapper.h
+* @version      1.00
+* $Rev: 1 $
+* $Date:: 2015-08-06 16:33:52 +0900#$
+* @brief        Graphics driver wrapper function definitions in C
+******************************************************************************/
+
+#ifndef CONVERTER_WRAPPER_H
+#define CONVERTER_WRAPPER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_typedef.h"
+#include "cmsis_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @enum mbed_jcu_err_t
+    @brief Error codes
+ */
+typedef	enum {
+        MBED_JCU_E_OK              =  0,	/*!< Normal termination      */
+        MBED_JCU_E_JCU_ERR         = -1,	/*!< JCU driver error        */
+        MBED_JCU_E_FORMA_ERR       = -2,	/*!< Not support format      */
+        MBED_JCU_E_PARAM_ERR       = -3,	/*!< Parameter error         */
+        MBED_JCU_E_PARAM_RANGE_ERR = -7,	/*!< Parameter range error   */
+ } mbed_jcu_err_t;
+
+
+/** Callback function format
+ */
+typedef void (mbed_CallbackFunc_t)(mbed_jcu_err_t err_code);
+
+
+/**************************************************************************//**
+ * @brief       Set callback function address for decode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   p_async          ospl async data address
+ * @param[in]   width            Decode data width
+ * @param[in]   height           Decode data height
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_set_decode_callback(mbed_CallbackFunc_t* pSetCallbackAdr, size_t width, size_t height);
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_LocalDecodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller);
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   p_async          ospl async data address
+ * @param[in]   pSize            Encode size input address
+ * @param[in]   count_max        Encode count max num
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_set_encode_callback(mbed_CallbackFunc_t* pSetCallbackAdr, size_t* pSize, int32_t count_max);
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_LocalEncodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller);
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif	/* CONVERTER_WRAPPER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/inc/r_jcu_api.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,577 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_jcu_api.h
+* @brief   JCU (JPEG hardware) driver API. Main Header.
+*
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef JCU_API_H_
+#define JCU_API_H_
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stddef.h>
+#include    "r_jcu_user.h"
+#include    "r_ospl.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   jcu_status_information_t
+* @brief  Status
+*
+*    - JCU_STATUS_UNDEF - 0x00, Undefined
+*    - JCU_STATUS_INIT - 0x01, Initialized
+*    - JCU_STATUS_SELECTED - 0x02, Codec is selected
+*    - JCU_STATUS_READY - 0x08, Ready
+*    - JCU_STATUS_RUN - 0x10, Run
+*    - JCU_STATUS_INTERRUPTING - 0x40, Interrupting
+*    - JCU_STATUS_INTERRUPTED - 0x80, Interrupted
+*/
+typedef enum {
+    JCU_STATUS_UNDEF        = 0x00,
+    JCU_STATUS_INIT         = 0x01,
+    JCU_STATUS_SELECTED     = 0x02,
+    JCU_STATUS_READY        = 0x08,
+    JCU_STATUS_RUN          = 0x10,
+    JCU_STATUS_INTERRUPTING = 0x40,
+    JCU_STATUS_INTERRUPTED  = 0x80
+} jcu_status_information_t;
+
+
+/**
+* @struct  jcu_async_status_t
+* @brief  Status of asynchronize
+*/
+typedef struct st_jcu_async_status_t  jcu_async_status_t;
+struct st_jcu_async_status_t {
+    jcu_status_information_t  Status;
+    bit_flags_fast32_t        SubStatusFlags;
+    bool_t                    IsPaused;
+    bool_t                    IsEnabledInterrupt;
+    r_ospl_flag32_t           InterruptEnables;
+    r_ospl_flag32_t           InterruptFlags;
+    r_ospl_flag32_t           CancelFlags;  /*<r_ospl_cancel_flag_t>*/
+};
+
+
+/* Section: Global */
+/**
+* @enum   SubStatusFlags
+* @brief  Sub Status
+*
+*    - JCU_SUB_INFOMATION_READY - 0x00000008
+*    - JCU_SUB_DECODE_OUTPUT_PAUSE - 0x00000100
+*    - JCU_SUB_DECODE_INPUT_PAUSE - 0x00000200
+*    - JCU_SUB_ENCODE_OUTPUT_PAUSE - 0x00001000
+*    - JCU_SUB_ENCODE_INPUT_PAUSE - 0x00002000
+*/
+#define JCU_SUB_INFOMATION_READY    0x00000008
+#define JCU_SUB_DECODE_OUTPUT_PAUSE 0x00000100
+#define JCU_SUB_DECODE_INPUT_PAUSE  0x00000200
+#define JCU_SUB_ENCODE_OUTPUT_PAUSE 0x00001000
+#define JCU_SUB_ENCODE_INPUT_PAUSE  0x00002000
+
+
+/**
+* @def  jcu_interrupt_line_t
+* @brief  Interrupt Lines
+*
+*    - JCU_INTERRUPT_LINE_JEDI - 1
+*    - JCU_INTERRUPT_LINE_JDTI - 2
+*    - JCU_INTERRUPT_LINE_ALL - 1 | 2
+*/
+typedef uint_fast32_t  jcu_interrupt_line_t;
+#define  JCU_INTERRUPT_LINE_JEDI  0x00000001u
+#define  JCU_INTERRUPT_LINE_JDTI  0x00000002u
+#define  JCU_INTERRUPT_LINE_ALL \
+    ( JCU_INTERRUPT_LINE_JEDI | JCU_INTERRUPT_LINE_JDTI )
+
+
+/**
+* @typedef  jcu_interrupt_lines_t
+* @brief  Bit flags of <jcu_interrupt_line_t>
+*/
+typedef bit_flags_fast32_t /*<jcu_interrupt_line_t>*/  jcu_interrupt_lines_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/**
+* @def  JCU_VERSION
+* @brief  VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_VERSION  100
+
+
+/**
+* @def  JCU_VERSION_STRING
+* @brief  String of <JCU_VERSION>
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_VERSION_STRING  "1.00"
+
+
+/**
+* @def  JCU_INT_TYPE_NUM
+* @brief  The number of the interrupt source
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_INT_TYPE_NUM  0x0009
+
+
+/**
+* @def  JCU_COLOR_ELEMENT_NUM
+* @brief  Y,Cb and Cr
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_COLOR_ELEMENT_NUM   3
+
+
+/******************************************************************************
+Struct & Enum definitions
+******************************************************************************/
+
+/**
+* @enum   jcu_errorcode_t
+* @brief  Error code of JCU driver
+*
+*    - JCU_ERROR_OK - 0
+*    - JCU_ERROR_PARAM - 0x4501
+*    - JCU_ERROR_STATUS - 0x4502
+*    - JCU_ERROR_CODEC_TYPE - 0x4503
+*    - JCU_ERROR_LIMITATION - 0x4504
+*/
+enum { E_CATEGORY_JCU_ERR = 0x4500 };  /* Offset of JCU error code */
+typedef errnum_t  jcu_errorcode_t;
+enum {
+    JCU_ERROR_OK            = 0x0000,
+    JCU_ERROR_PARAM         = 0x4501,
+    JCU_ERROR_STATUS        = 0x4502,
+    JCU_ERROR_CODEC_TYPE    = 0x4503,
+    JCU_ERROR_LIMITATION    = 0x4504
+};
+
+
+/**
+* @enum   jcu_detail_error_t
+* @brief  Kind of detailed error for decoding
+*
+*    - JCU_JCDERR_OK - 0x0000
+*    - JCU_JCDERR_SOI_NOT_FOUND - 0x4521
+*    - JCU_JCDERR_INVALID_SOF - 0x4522
+*    - JCU_JCDERR_UNPROVIDED_SOF - 0x4523
+*    - JCU_JCDERR_SOF_ACCURACY - 0x4524
+*    - JCU_JCDERR_DQT_ACCURACY - 0x4525
+*    - JCU_JCDERR_COMPONENT_1 - 0x4526
+*    - JCU_JCDERR_COMPONENT_2 - 0x4527
+*    - JCU_JCDERR_NO_SOF0_DQT_DHT - 0x4528
+*    - JCU_JCDERR_SOS_NOT_FOUND - 0x4529
+*    - JCU_JCDERR_EOI_NOT_FOUND - 0x452A
+*    - JCU_JCDERR_RESTART_INTERVAL - 0x452B
+*    - JCU_JCDERR_IMAGE_SIZE - 0x452C
+*    - JCU_JCDERR_LAST_MCU_DATA - 0x452D
+*    - JCU_JCDERR_BLOCK_DATA - 0x452E
+*/
+enum { E_CATEGORY_JCU_JCDERR = 0x4520 };  /* Offset of JCU detail error code */
+typedef errnum_t  jcu_detail_error_t;
+enum {
+    JCU_JCDERR_OK                = 0x0000,
+    JCU_JCDERR_SOI_NOT_FOUND     = 0x4521,
+    JCU_JCDERR_INVALID_SOF       = 0x4522,
+    JCU_JCDERR_UNPROVIDED_SOF    = 0x4523,
+    JCU_JCDERR_SOF_ACCURACY      = 0x4524,
+    JCU_JCDERR_DQT_ACCURACY      = 0x4525,
+    JCU_JCDERR_COMPONENT_1       = 0x4526,
+    JCU_JCDERR_COMPONENT_2       = 0x4527,
+    JCU_JCDERR_NO_SOF0_DQT_DHT   = 0x4528,
+    JCU_JCDERR_SOS_NOT_FOUND     = 0x4529,
+    JCU_JCDERR_EOI_NOT_FOUND     = 0x452A,
+    JCU_JCDERR_RESTART_INTERVAL  = 0x452B,
+    JCU_JCDERR_IMAGE_SIZE        = 0x452C,
+    JCU_JCDERR_LAST_MCU_DATA     = 0x452D,
+    JCU_JCDERR_BLOCK_DATA        = 0x452E
+};
+
+
+/**
+* @enum   jcu_codec_t
+* @brief  The type of codec
+*
+*    - JCU_ENCODE - 0
+*    - JCU_DECODE - 1
+*/
+typedef enum {
+    JCU_ENCODE  = 0,
+    JCU_DECODE  = 1
+} jcu_codec_t;
+
+
+/**
+* @struct  jcu_count_mode_param_t
+* @brief  Buffer settings for separating decode or encode
+*/
+typedef struct {
+    struct {
+        /** true: It uses the count mode process. */
+        bool_t      isEnable;
+
+        /** Address is changed when processing is stopped. */
+        bool_t      isInitAddress;
+
+        /** This is enable when isInitAddrss is true. */
+        uint32_t   *restartAddress;
+
+        /** Encode:8line Decode:8byte. */
+        uint32_t    dataCount;
+
+    } inputBuffer;
+
+    struct {
+        /** true: It uses the count mode process. */
+        bool_t      isEnable;
+
+        /** Address is changed when processing is stopped. */
+        bool_t      isInitAddress;      /*    */
+
+        /** This is enable when isInitAddress is true. */
+        uint32_t    *restartAddress;    /*     */
+
+        /** Encode:8byte Decode:8line. */
+        uint32_t    dataCount;
+
+    } outputBuffer;
+} jcu_count_mode_param_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_continue_type_t
+* @brief  Type of continue buffer
+*
+*    - JCU_INPUT_BUFFER - 0
+*    - JCU_OUTPUT_BUFFER - 1
+*    - JCU_IMAGE_INFO - 2
+*/
+typedef enum {
+    JCU_INPUT_BUFFER,
+    JCU_OUTPUT_BUFFER,
+    JCU_IMAGE_INFO
+} jcu_continue_type_t;
+
+
+/**
+* @def  jcu_int_detail_error_t
+* @brief  Bit flags of detail error
+*
+*    - JCU_INT_ERROR_RESTART_INTERVAL_DATA - INT7_MASK
+*    - JCU_INT_ERROR_SEGMENT_TOTAL_DATA - INT6_MASK
+*    - JCU_INT_ERROR_MCU_BLOCK_DATA - INT5_MASK
+*    - JCU_INT_ERROR_ALL - e.g. for mask
+*/
+typedef uint_fast32_t  jcu_int_detail_error_t;
+#define JCU_INT_ERROR_RESTART_INTERVAL_DATA  (0x80u)
+#define JCU_INT_ERROR_SEGMENT_TOTAL_DATA     (0x40u)
+#define JCU_INT_ERROR_MCU_BLOCK_DATA         (0x20u)
+#define JCU_INT_ERROR_ALL \
+	( JCU_INT_ERROR_RESTART_INTERVAL_DATA | JCU_INT_ERROR_SEGMENT_TOTAL_DATA | \
+	JCU_INT_ERROR_MCU_BLOCK_DATA )
+
+
+/**
+* @typedef  jcu_int_detail_errors_t
+* @brief  Bit flags of detail error
+*/
+typedef bit_flags_fast32_t /*<jcu_int_detail_error_t>*/  jcu_int_detail_errors_t;
+
+
+/**
+* @enum   jcu_swap_t
+* @brief  SampleEnum
+*
+*    - SymbolA - 0, NULL
+*    - SymbolB - 1
+*/
+typedef int_t jcu_swap_t;
+#define JCU_SWAP_NONE                           (0x00)
+#define JCU_SWAP_BYTE                           (0x01)
+#define JCU_SWAP_WORD                           (0x02)
+#define JCU_SWAP_WORD_AND_BYTE                  (0x03)
+#define JCU_SWAP_LONG_WORD                      (0x04)
+#define JCU_SWAP_LONG_WORD_AND_BYTE             (0x05)
+#define JCU_SWAP_LONG_WORD_AND_WORD             (0x06)
+#define JCU_SWAP_LONG_WORD_AND_WORD_AND_BYTE    (0x07)
+
+
+/**
+* @struct  jcu_buffer_t
+* @brief  Buffer settings
+*/
+typedef struct {
+    jcu_swap_t    swapSetting;
+    uint32_t     *address;
+} jcu_buffer_t;
+
+
+/**
+* @struct  jcu_buffer_param_t
+* @brief  Buffer parameter for input and output
+*/
+typedef struct {
+    jcu_buffer_t  source;
+    jcu_buffer_t  destination;
+    int16_t       lineOffset;
+} jcu_buffer_param_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_sub_sampling_t
+* @brief  Sub sampling settings for decoding
+*
+*    - JCU_SUB_SAMPLING_1_1 - 0x00 = 1/1
+*    - JCU_SUB_SAMPLING_1_2 - 0x01 = 1/2
+*    - JCU_SUB_SAMPLING_1_4 - 0x02 = 1/4
+*    - JCU_SUB_SAMPLING_1_8 - 0x03 = 1/8
+*/
+typedef enum {
+    JCU_SUB_SAMPLING_1_1 = 0x00,
+    JCU_SUB_SAMPLING_1_2 = 0x01,
+    JCU_SUB_SAMPLING_1_4 = 0x02,
+    JCU_SUB_SAMPLING_1_8 = 0x03
+} jcu_sub_sampling_t;
+
+
+/**
+* @enum   jcu_decode_format_t
+* @brief  Kind of pixel format can process the decoding
+*
+*    - JCU_OUTPUT_YCbCr422 - 0x00
+*    - JCU_OUTPUT_ARGB8888 - 0x01
+*    - JCU_OUTPUT_RGB565 - 0x02
+*/
+typedef enum {
+    JCU_OUTPUT_YCbCr422 = 0x00,
+    JCU_OUTPUT_ARGB8888 = 0x01,
+    JCU_OUTPUT_RGB565   = 0x02
+} jcu_decode_format_t;
+
+
+/**
+* @enum   jcu_cbcr_offset_t
+* @brief  Cb/Cr offset
+*
+*    - JCU_CBCR_OFFSET_0 - 0 = No offset
+*    - JCU_CBCR_OFFSET_128 - 1 = +128 offset
+*/
+typedef enum {
+    JCU_CBCR_OFFSET_0 = 0,
+    JCU_CBCR_OFFSET_128 = 1
+} jcu_cbcr_offset_t;
+
+
+/**
+* @enum   jcu_jpeg_format_t
+* @brief  Kind of pixel format for the jpeg file format when decoding
+*
+*    - JCU_JPEG_YCbCr444 - 0
+*    - JCU_JPEG_YCbCr422 - 1
+*    - JCU_JPEG_YCbCr420 - 2
+*    - JCU_JPEG_YCbCr411 - 6
+*/
+typedef enum {
+    JCU_JPEG_YCbCr444   = 0x00,
+    JCU_JPEG_YCbCr422   = 0x01,
+    JCU_JPEG_YCbCr420   = 0x02,
+    JCU_JPEG_YCbCr411   = 0x06
+} jcu_jpeg_format_t;
+
+
+/**
+* @struct  jcu_image_info_t
+* @brief  Image information data store variable
+*/
+typedef struct {
+    uint32_t            width;
+    uint32_t            height;
+    jcu_jpeg_format_t   encodedFormat;
+} jcu_image_info_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_table_no_t
+* @brief  The index of the table
+*
+*    - JCU_TABLE_NO_0 - 0
+*    - JCU_TABLE_NO_1 - 1
+*    - JCU_TABLE_NO_2 - 2
+*    - JCU_TABLE_NO_3 - 3
+*/
+typedef enum {
+    JCU_TABLE_NO_0 = 0,
+    JCU_TABLE_NO_1 = 1,
+    JCU_TABLE_NO_2 = 2,
+    JCU_TABLE_NO_3 = 3
+} jcu_table_no_t;
+
+
+/**
+* @enum   jcu_huff_t
+* @brief  Kind of Huffman table
+*
+*    - JCU_HUFFMAN_AC - 0
+*    - JCU_HUFFMAN_DC - 1
+*/
+typedef enum {
+    JCU_HUFFMAN_AC,
+    JCU_HUFFMAN_DC
+} jcu_huff_t;
+
+
+/**
+* @enum   jcu_color_element_t
+* @brief  Kind of color data for using the encoder parameter
+*
+*    - JCU_ELEMENT_Y - 0
+*    - JCU_ELEMENT_Cb - 1
+*    - JCU_ELEMENT_Cr - 2
+*/
+typedef enum {
+    JCU_ELEMENT_Y,
+    JCU_ELEMENT_Cb,
+    JCU_ELEMENT_Cr
+} jcu_color_element_t;
+
+
+/**
+* @struct  jcu_decode_param_t
+* @brief  Setting parameter for the Decoding
+*/
+typedef struct {
+    jcu_sub_sampling_t  verticalSubSampling;
+    jcu_sub_sampling_t  horizontalSubSampling;
+    jcu_decode_format_t decodeFormat;
+    jcu_cbcr_offset_t   outputCbCrOffset;
+    uint8_t             alpha;
+} jcu_decode_param_t;
+
+
+/**
+* @struct  jcu_encode_param_t
+* @brief  Setting parameter for the Encoding
+*/
+typedef struct {
+    jcu_jpeg_format_t   encodeFormat;
+    int32_t             QuantizationTable[JCU_COLOR_ELEMENT_NUM];
+    int32_t             HuffmanTable[JCU_COLOR_ELEMENT_NUM];
+    uint32_t            DRI_value;
+    uint32_t            width;
+    uint32_t            height;
+    jcu_cbcr_offset_t   inputCbCrOffset;
+} jcu_encode_param_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_codec_status_t
+* @brief  Codec type
+*
+*    - JCU_CODEC_NOT_SELECTED - -1
+*    - JCU_STATUS_ENCODE - 0
+*    - JCU_STATUS_DECODE - 1
+*/
+typedef enum {
+    JCU_CODEC_NOT_SELECTED  = -1,
+    JCU_STATUS_ENCODE       = 0,
+    JCU_STATUS_DECODE       = 1
+} jcu_codec_status_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+jcu_errorcode_t R_JCU_Initialize( void *const  NullConfig );
+jcu_errorcode_t R_JCU_Terminate(void);
+jcu_errorcode_t R_JCU_TerminateAsync( r_ospl_async_t *const  async );
+jcu_errorcode_t R_JCU_SelectCodec(const jcu_codec_t codec);
+jcu_errorcode_t R_JCU_Start(void);
+jcu_errorcode_t R_JCU_StartAsync( r_ospl_async_t *const  async );
+jcu_errorcode_t R_JCU_SetCountMode(const jcu_count_mode_param_t *const buffer);
+jcu_errorcode_t R_JCU_Continue(const jcu_continue_type_t type);
+jcu_errorcode_t R_JCU_ContinueAsync(const jcu_continue_type_t type, r_ospl_async_t *const  async);
+void            R_JCU_GetAsyncStatus(const jcu_async_status_t **const  out_Status);
+jcu_errorcode_t R_JCU_SetDecodeParam(const jcu_decode_param_t *const decode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t R_JCU_SetPauseForImageInfo(const bool_t is_pause);
+jcu_errorcode_t R_JCU_GetImageInfo(jcu_image_info_t *const buffer);
+jcu_errorcode_t R_JCU_SetErrorFilter(jcu_int_detail_errors_t filter);
+jcu_errorcode_t R_JCU_SetQuantizationTable(const jcu_table_no_t tableNo, const uint8_t *const table);
+jcu_errorcode_t R_JCU_SetHuffmanTable(const jcu_table_no_t tableNo, const jcu_huff_t type, const uint8_t *const table);
+jcu_errorcode_t R_JCU_SetEncodeParam(const jcu_encode_param_t *const encode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t R_JCU_GetEncodedSize(size_t *const out_Size);
+jcu_errorcode_t R_JCU_Set2ndCacheAttribute( r_ospl_axi_cache_attribute_t const  read_cache_attribute,
+        r_ospl_axi_cache_attribute_t const  write_cache_attribute );
+
+#ifndef R_OSPL_NDEBUG
+void            R_JCU_PrintRegisters(void);
+#endif
+
+/* For interrupt callback */
+errnum_t        R_JCU_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource );
+errnum_t        R_JCU_OnInterrupted(void);
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* #define JCU_API_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/inc/r_jcu_local.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,480 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: jcu_local.h $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description  : JCU driver local parameter
+******************************************************************************/
+
+#ifndef JCU_LOCAL_H
+#define JCU_LOCAL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_jcu_api.h"
+#include    "r_jcu_user.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+typedef struct st_jcu_i_lock_t   jcu_i_lock_t;  /*[jcu_i_lock_t]*/
+
+/*! [jcu_internal_information_t] Internal Information for this driver */
+typedef struct {
+    jcu_codec_status_t             Codec;
+    bool_t                         IsCountMode;
+    jcu_int_detail_errors_t        ErrorFilter;  /* 1=Enable */
+
+    jcu_async_status_t             AsyncStatus;
+    r_ospl_caller_t                InterruptCallbackCaller;
+    jcu_i_lock_t                  *I_Lock;
+    const r_ospl_i_lock_vtable_t  *I_LockVTable;
+    bool_t                         Is_I_LockMaster;
+    r_ospl_async_t                *AsyncForFinalize;
+} jcu_internal_information_t;
+
+/*[jcu_i_lock_t]*/
+struct st_jcu_i_lock_t {
+    bool_t        IsLock;
+    bool_t        IsRequestedFinalize;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+jcu_internal_information_t  *R_JCU_GetInternalInformation(void);
+jcu_i_lock_t    *R_JCU_GetILockObject(void);
+void             R_JCU_I_LOCK_Finalize(void);
+jcu_errorcode_t  R_JCU_TerminateStep2(void);
+
+#ifdef      JCU_PARAMETER_CHECK
+jcu_errorcode_t JCU_ParaCheckStart(void);
+jcu_errorcode_t JCU_ParaCheckSetCountMode(const jcu_count_mode_param_t  *const buffer);
+jcu_errorcode_t JCU_ParaCheckSelectCodec(const jcu_codec_t codec);
+jcu_errorcode_t JCU_ParaCheckSetCallbackFunc(const uintptr_t type);
+jcu_errorcode_t JCU_ParaCheckSetDecodeParam(const jcu_decode_param_t *const decode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t JCU_ParaCheckGetImageInfo(const jcu_image_info_t *const buffer);
+jcu_errorcode_t JCU_ParaCheckGetErrorInfo(const jcu_detail_error_t *const errorCode);
+jcu_errorcode_t JCU_ParaCheckSetQuantizationTbl(const jcu_table_no_t tableNo);
+jcu_errorcode_t JCU_ParaCheckSetHuffmanTable(const jcu_table_no_t tableNo, const jcu_huff_t type);
+jcu_errorcode_t JCU_ParaCheckEncodeParam(const jcu_encode_param_t *const encode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t JCU_CheckInterruptSource(const uint32_t interruptKind);
+#endif /* JCU_PARAMETER_CHECK */
+
+jcu_errorcode_t JCU_SetRegisterForInitialize(void);
+void JCU_SetRegisterForCodec(const jcu_codec_t codec);
+void JCU_SetRegisterForStart(const jcu_int_detail_error_t error_filter);
+void JCU_SetRegisterForReset(void);
+void JCU_SetRegisterForSetCountMode(const jcu_count_mode_param_t *const buffer);
+void JCU_SetRegisterForContinue(const jcu_continue_type_t type);
+void JCU_SetRegisterForSetDecodePrm(const jcu_decode_param_t *const decode, const jcu_buffer_param_t *const buffer);
+void JCU_SetRegisterForSetQtTable(const jcu_table_no_t tableNo, const uint8_t *const  table);
+void JCU_SetRegisterForSetHuffTbl(const jcu_table_no_t tableNo, const jcu_huff_t type, const uint8_t *const table);
+void JCU_SetRegisterForSetEncodePrm(const jcu_encode_param_t *const encode, const jcu_buffer_param_t *const buffer);
+void JCU_SetRegisterForSetPause(const bool_t is_pause, const jcu_int_detail_errors_t filter);
+void JCU_GetRegisterForGetImageInfo(jcu_image_info_t *const buffer);
+void JCU_GetEncodedSize(size_t *const out_Size);
+void JCU_ClearInterruptFlag(void);
+
+
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. */
+/*    But driver code is no problem. */
+/*    This expects 32bit CPU. */
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". */
+/*    But this is not depend on compiler spcifications. */
+/* ->MISRA 19.12 ->MISRA 19.13 ->SEC M5.1.2 (1) */
+#define R_SET_REG_BIT_FIELD( Register, BitName, Value ) \
+        ( (Register) = (BitName##_TYPE)( ( (uint32_t)(Register) & (uint32_t)(~(BitName##_MASK) ) ) |\
+        ( (uint32_t)( (uint32_t)(Value) << (BitName##_SHIFT) ) & (uint32_t)(BitName##_MASK) ) ) )
+#define R_GET_REG_BIT_FIELD( Register, BitName ) \
+        ( (BitName##_TYPE)( ( ((uint32_t)(Register)) & (uint32_t)(BitName##_MASK) ) >> (BitName##_SHIFT) ) )
+/* <-SEC M1.2.3(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+/* <-MISRA 19.12 <-MISRA 19.13 <-SEC M5.1.2 (1) */
+
+/* Value of register */
+/* 1bit(Flag) */
+#define REG_F_CLR (0u)
+#define REG_F_SET (1u)
+
+/* Bit field name (Register name) */
+
+/* SRST(CPG.SWRSTCR2) */
+#define SRST_MASK       (0x00000002u)
+#define SRST_SHIFT      (1u)
+#define SRST_TYPE       uint8_t
+
+
+/*DSP(JCU.JCMOD) */
+#define DSP_MASK        (0x00000008u)
+#define DSP_SHIFT       (3u)
+#define DSP_TYPE        uint8_t
+
+/*REDU(JCU.JCMOD) */
+#define REDU_MASK       (0x00000007u)
+#define REDU_SHIFT      (0u)
+#define REDU_TYPE       uint8_t
+
+
+/*BRST(JCU.JCCMD) */
+#define BRST_MASK       (0x00000080u)
+#define BRST_SHIFT      (7u)
+#define BRST_TYPE       uint8_t
+
+/*JEND(JCU.JCCMD) */
+#define JEND_MASK       (0x00000004u)
+#define JEND_SHIFT      (2u)
+#define JEND_TYPE       uint8_t
+
+/*JRST(JCU.JCCMD) */
+#define JRST_MASK       (0x00000002u)
+#define JRST_SHIFT      (1u)
+#define JRST_TYPE       uint8_t
+
+/*JSRT(JCU.JCCMD) */
+#define JSRT_MASK       (0x00000001u)
+#define JSRT_SHIFT      (0u)
+#define JSRT_TYPE       uint8_t
+
+
+/*QT3(JCU.JCQTN) */
+#define QT3_MASK        (0x00000030u)
+#define QT3_SHIFT       (4u)
+#define QT3_TYPE        uint8_t
+
+/*QT2(JCU.JCQTN) */
+#define QT2_MASK        (0x0000000Cu)
+#define QT2_SHIFT       (2u)
+#define QT2_TYPE        uint8_t
+
+/*QT1(JCU.JCQTN) */
+#define QT1_MASK        (0x00000003u)
+#define QT1_SHIFT       (0u)
+#define QT1_TYPE        uint8_t
+
+
+/*HTA3(JCU.JCHTN) */
+#define HTA3_MASK       (0x00000020u)
+#define HTA3_SHIFT      (5u)
+#define HTA3_TYPE       uint8_t
+
+/*HTD3(JCU.JCHTN) */
+#define HTD3_MASK       (0x00000010u)
+#define HTD3_SHIFT      (4u)
+#define HTD3_TYPE       uint8_t
+
+/*HTA2(JCU.JCHTN) */
+#define HTA2_MASK       (0x00000008u)
+#define HTA2_SHIFT      (3u)
+#define HTA2_TYPE       uint8_t
+
+/*HTD2(JCU.JCHTN) */
+#define HTD2_MASK       (0x00000004u)
+#define HTD2_SHIFT      (2u)
+#define HTD2_TYPE       uint8_t
+
+/*HTA1(JCU.JCHTN) */
+#define HTA1_MASK       (0x00000002u)
+#define HTA1_SHIFT      (1u)
+#define HTA1_TYPE       uint8_t
+
+/*HTD1(JCU.JCHTN) */
+#define HTD1_MASK       (0x00000001u)
+#define HTD1_SHIFT      (0u)
+#define HTD1_TYPE       uint8_t
+
+
+/*INT7(JCU.JINTE0) Error of restart interval data. JINTE0.INT7 -> JINTS0.INS5 */
+#define INT7_MASK       (0x00000080u)
+#define INT7_SHIFT      (7u)
+#define INT7_TYPE       uint8_t
+
+/*INT6(JCU.JINTE0) Error of Segment total data. JINTE0.INT6 -> JINTS0.INS5 */
+#define INT6_MASK       (0x00000040u)
+#define INT6_SHIFT      (6u)
+#define INT6_TYPE       uint8_t
+
+/*INT5(JCU.JINTE0) Error of MCU block data. JINTE0.INT5 -> JINTS0.INS5 */
+#define INT5_MASK       (0x00000020u)
+#define INT5_SHIFT      (5u)
+#define INT5_TYPE       uint8_t
+
+/*INT3(JCU.JINTE0) */
+#define INT3_MASK       (0x00000008u)
+#define INT3_SHIFT      (3u)
+#define INT3_TYPE       uint8_t
+
+
+/*INS6(JCU.JINTS0) End Core Only */
+#define INS6_MASK       (0x00000040u)
+#define INS6_SHIFT      (6u)
+#define INS6_TYPE       uint8_t
+
+/*INS5(JCU.JINTS0) Decode Error */
+#define INS5_MASK       (0x00000020u)
+#define INS5_SHIFT      (5u)
+#define INS5_TYPE       uint8_t
+
+/*INS3(JCU.JINTS0) Get Image Information */
+#define INS3_MASK       (0x00000008u)
+#define INS3_SHIFT      (3u)
+#define INS3_TYPE       uint8_t
+
+
+/*ERR(JCU.JCDERR) */
+#define ERR_MASK        (0x0000000Fu)
+#define ERR_SHIFT       (0u)
+#define ERR_TYPE        uint8_t
+
+
+/*JOUTRINI(JCU.JIFECNT) */
+#define JOUTRINI_MASK   (0x00004000u)
+#define JOUTRINI_SHIFT  (14u)
+#define JOUTRINI_TYPE   uint32_t
+
+/*JOUTRCMD(JCU.JIFECNT) */
+#define JOUTRCMD_MASK   (0x00002000u)
+#define JOUTRCMD_SHIFT  (13u)
+#define JOUTRCMD_TYPE   uint32_t
+
+/*JOUTC(JCU.JIFECNT) */
+#define JOUTC_MASK      (0x00001000u)
+#define JOUTC_SHIFT     (12u)
+#define JOUTC_TYPE      uint32_t
+
+/*JOUTSWAP(JCU.JIFECNT) */
+#define JOUTSWAP_MASK   (0x00000700u)
+#define JOUTSWAP_SHIFT  (8u)
+#define JOUTSWAP_TYPE   uint32_t
+
+/*DINRINI(JCU.JIFECNT) */
+#define DINRINI_MASK    (0x00000040u)
+#define DINRINI_SHIFT   (6u)
+#define DINRINI_TYPE    uint32_t
+
+/*DINRCMD(JCU.JIFECNT) */
+#define DINRCMD_MASK    (0x00000020u)
+#define DINRCMD_SHIFT   (5u)
+#define DINRCMD_TYPE    uint32_t
+
+/*DINLC(JCU.JIFECNT) */
+#define DINLC_MASK      (0x00000010u)
+#define DINLC_SHIFT     (4u)
+#define DINLC_TYPE      uint32_t
+
+/*DINSWAP(JCU.JIFECNT) */
+#define DINSWAP_MASK    (0x00000007u)
+#define DINSWAP_SHIFT   (0u)
+#define DINSWAP_TYPE    uint32_t
+
+
+/*ESMW(JCU.JIFESOFST) */
+#define ESMW_MASK       (0x00007FFFu)
+#define ESMW_SHIFT      (0u)
+#define ESMW_TYPE       uint32_t
+
+
+/*LINES(JCU.JIFESLC, JCU.JIFDDLC) */
+#define LINES_MASK      (0x0000FFFFu)
+#define LINES_SHIFT     (0u)
+#define LINES_TYPE      uint32_t
+#define LINES_CLEAR     (0u)
+
+
+/*JDATAS(JCU.JIFESLC, JCU.JIFDSDC, JCU.JIFEDDC) */
+#define JDATAS_MASK     (0x0000FFFFu)
+#define JDATAS_SHIFT    (0u)
+#define JDATAS_TYPE     uint32_t
+#define JDATAS_CLEAR    (0u)
+
+
+/*VINTER(JCU.JIFDCNT) */
+#define VINTER_MASK     (0x3C000000u)
+#define VINTER_SHIFT    (28u)
+#define VINTER_TYPE     uint32_t
+
+/*HINTER(JCU.JIFDCNT) */
+#define HINTER_MASK     (0x0C000000u)
+#define HINTER_SHIFT    (26u)
+#define HINTER_TYPE     uint32_t
+
+/*OPF(JCU.JIFDCNT) */
+#define OPF_MASK        (0x03000000u)
+#define OPF_SHIFT       (24u)
+#define OPF_TYPE        uint32_t
+
+/*JINRINI(JCU.JIFDCNT) */
+#define JINRINI_MASK    (0x00004000u)
+#define JINRINI_SHIFT   (14u)
+#define JINRINI_TYPE    uint32_t
+
+/*JINRCMD(JCU.JIFDCNT) */
+#define JINRCMD_MASK    (0x00002000u)
+#define JINRCMD_SHIFT   (13u)
+#define JINRCMD_TYPE    uint32_t
+
+/*JINC(JCU.JIFDCNT) */
+#define JINC_MASK       (0x00001000u)
+#define JINC_SHIFT      (12u)
+#define JINC_TYPE       uint32_t
+
+/*JINSWAP(JCU.JIFDCNT) */
+#define JINSWAP_MASK    (0x00000700u)
+#define JINSWAP_SHIFT   (8u)
+#define JINSWAP_TYPE    uint32_t
+
+/*DOUTRINI(JCU.JIFDCNT) */
+#define DOUTRINI_MASK   (0x00000040u)
+#define DOUTRINI_SHIFT  (6u)
+#define DOUTRINI_TYPE   uint32_t
+
+/*DOUTRCMD(JCU.JIFDCNT) */
+#define DOUTRCMD_MASK   (0x00000020u)
+#define DOUTRCMD_SHIFT  (5u)
+#define DOUTRCMD_TYPE   uint32_t
+
+/*DOUTLC(JCU.JIFDCNT) */
+#define DOUTLC_MASK     (0x00000010u)
+#define DOUTLC_SHIFT    (4u)
+#define DOUTLC_TYPE     uint32_t
+
+/*DOUTSWAP(JCU.JIFDCNT) */
+#define DOUTSWAP_MASK   (0x00000007u)
+#define DOUTSWAP_SHIFT  (0u)
+#define DOUTSWAP_TYPE   uint32_t
+
+
+/*DDMW(JCU.JIFDDOFST) */
+#define DDMW_MASK       (0x00007FFFu)
+#define DDMW_SHIFT      (0u)
+#define DDMW_TYPE       uint32_t
+
+
+/*ALPHA(JCU.JIFDADT) */
+#define ALPHA_MASK      (0x000000FFu)
+#define ALPHA_SHIFT     (0u)
+#define ALPHA_TYPE      uint32_t
+
+
+/*CBTEN(JCU.JINTE1) */
+#define CBTEN_MASK      (0x00000040u)
+#define CBTEN_SHIFT     (6u)
+#define CBTEN_TYPE      uint32_t
+
+/*DINLEN(JCU.JINTE1) */
+#define DINLEN_MASK     (0x00000020u)
+#define DINLEN_SHIFT    (5u)
+#define DINLEN_TYPE     uint32_t
+
+/*JOUTEN(JCU.JINTE1) */
+#define JOUTEN_MASK     (0x00000010u)
+#define JOUTEN_SHIFT    (4u)
+#define JOUTEN_TYPE     uint32_t
+
+/*DBTEN(JCU.JINTE1) */
+#define DBTEN_MASK      (0x00000004u)
+#define DBTEN_SHIFT     (2u)
+#define DBTEN_TYPE      uint32_t
+
+/*JINEN(JCU.JINTE1) */
+#define JINEN_MASK      (0x00000002u)
+#define JINEN_SHIFT     (1u)
+#define JINEN_TYPE      uint32_t
+
+/*DOUTLEN(JCU.JINTE1) */
+#define DOUTLEN_MASK    (0x00000001u)
+#define DOUTLEN_SHIFT   (0u)
+#define DOUTLEN_TYPE    uint32_t
+
+
+/*CBTF(JCU.JINTS1) JINTE1.CBTEN -> JINTS1.CBTF */
+#define CBTF_MASK       (0x00000040u)
+#define CBTF_SHIFT      (6u)
+#define CBTF_TYPE       uint32_t
+
+/*DINLF(JCU.JINTS1) Input Data for Encoding */
+#define DINLF_MASK      (0x00000020u)
+#define DINLF_SHIFT     (5u)
+#define DINLF_TYPE      uint32_t
+
+/*JOUTF(JCU.JINTS1) Output Data for Encoding */
+#define JOUTF_MASK      (0x00000010u)
+#define JOUTF_SHIFT     (4u)
+#define JOUTF_TYPE      uint32_t
+
+/*DBTF(JCU.JINTS1) JINTE1.DBTEN -> JINTS1.DBTF */
+#define DBTF_MASK       (0x00000004u)
+#define DBTF_SHIFT      (2u)
+#define DBTF_TYPE       uint32_t
+
+/*JINF(JCU.JINTS1) Input Data for Decoding */
+#define JINF_MASK       (0x00000002u)
+#define JINF_SHIFT      (1u)
+#define JINF_TYPE       uint32_t
+
+/*DOUTLF(JCU.JINTS1) Output Data for Decoding */
+#define DOUTLF_MASK     (0x00000001u)
+#define DOUTLF_SHIFT    (0u)
+#define DOUTLF_TYPE     uint32_t
+
+
+/*DINYCHG(JCU.JIFESVSZ) */
+#define DINYCHG_MASK     (0x00008000u)
+#define DINYCHG_SHIFT    (15u)
+#define DINYCHG_TYPE     uint32_t
+
+/*DOUTYCHG(JCU.JIFESHSZ) */
+#define DOUTYCHG_MASK     (0x00008000u)
+#define DOUTYCHG_SHIFT    (15u)
+#define DOUTYCHG_TYPE     uint32_t
+
+/* Others */
+#define JCU_JINTS1_ALL  ( CBTF_MASK | DINLF_MASK | JOUTF_MASK | DBTF_MASK | JINF_MASK | DOUTLF_MASK )
+#define SHIFT_16BITS    (16u)                               /* 16bit-SHIFT */
+#define SHIFT_8BITS     (8u)                                /* 8bit-SHIFT */
+#define JCU_SHIFT_JINTS1 (8)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* JCU_LOCAL_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/inc/r_jcu_pl.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,77 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: jcu_pl.h $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description  : Sample Data
+******************************************************************************/
+
+#ifndef JCU_PL_H
+#define JCU_PL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_jcu_api.h"
+#include  "r_ospl.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void      R_JCU_SetDefaultAsync( r_ospl_async_t *const  Async,  r_ospl_async_type_t AsyncType );
+errnum_t  R_JCU_OnInitialize(void);
+errnum_t  R_JCU_OnFinalize( errnum_t e );
+errnum_t  R_JCU_SetInterruptCallbackCaller( const r_ospl_caller_t *const  Caller );
+void      R_JCU_OnEnableInterrupt( jcu_interrupt_lines_t const  Enables );
+void      R_JCU_OnDisableInterrupt( jcu_interrupt_lines_t const  Disables1 );
+errnum_t  R_JCU_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                    const r_ospl_caller_t *const  Caller );
+
+/* For integrating driver */
+bool_t    R_JCU_I_LOCK_Replace( void *const  I_Lock,  const r_ospl_i_lock_vtable_t *const  I_LockVTable );
+bool_t    R_JCU_DisableInterrupt(void);
+void      R_JCU_EnableInterrupt(void);
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _JCU_PL_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/inc/r_jcu_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,66 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: jcu_user.h $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 32 $
+* $Date:: 2014-02-21 20:21:46 +0900#$
+* Description  : JCU driver User Configuration
+******************************************************************************/
+
+
+/* This file is included from "r_jcu_api.h" */
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+#ifndef JCU_USER_H
+#define JCU_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Parameter check */
+#define     JCU_PARAMETER_CHECK
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* JCU_USER_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/jcu_driver/JPEG_Coverter.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,675 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         jpeg_coverter.cpp
+* @version      1.00
+* $Rev: 1 $
+* $Date:: 2015-08-06 16:33:52 +0900#$
+* @brief        Decodes JPEG data and encodes to JPEG data
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  <string.h>
+#include  <stdio.h>
+#include  "rtos.h"
+#include  "r_typedefs.h"
+#include  "r_jcu_api.h"
+#include  "JPEG_Converter.h"
+#include  "converter_wrapper.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  QUANTIZATION_TABLE_SIZE    (64u)
+#define  HUFFMAN_TABLE_DC_SIZE      (28u)
+#define  HUFFMAN_TABLE_AC_SIZE      (178u)
+#define  JPEG_HEADER_LETTER_1       (0xFFu)
+#define  JPEG_HEADER_LETTER_2       (0xD8u)
+#define  ALPHA_VAL_MAX              (0xFF)
+#define  LOC_KIND_COLOR_FORMAT      (3u)
+#define  QUANTIZATION_TABLE_NUM     (2)
+
+#define  ENC_SIZE_MAX               (1024 * 30)
+#define  MASK_8BYTE                 (0xFFFFFFF8)
+
+    /*[HuffmanTable_Y_DC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_Y_DC[HUFFMAN_TABLE_DC_SIZE] = {
+        0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B
+    };
+
+    /*[HuffmanTable_C_DC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_C_DC[HUFFMAN_TABLE_DC_SIZE] = {
+        0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B
+    };
+
+    /*[HuffmanTable_Y_AC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_Y_AC[HUFFMAN_TABLE_AC_SIZE] = {
+        0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D,
+        0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
+        0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0,
+        0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28,
+        0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+        0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+        0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+        0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7,
+        0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5,
+        0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2,
+        0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8,
+        0xF9, 0xFA
+    };
+
+    /*[HuffmanTable_C_AC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_C_AC[HUFFMAN_TABLE_AC_SIZE] = {
+        0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77,
+        0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
+        0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0,
+        0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26,
+        0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
+        0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+        0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+        0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5,
+        0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3,
+        0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA,
+        0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8,
+        0xF9, 0xFA
+    };
+
+typedef void (JPEG_CallbackFunc_t)(JPEG_Converter::jpeg_conv_error_t err_code);
+
+static uint32_t             driver_ac_count = 0;
+static bool                 jcu_error_flag;
+static JPEG_CallbackFunc_t* pJPEG_ConverterCallback;
+Semaphore                   jpeg_converter_semaphore(1);
+#if defined(__ICCARM__)
+#pragma data_alignment=32
+static uint8_t QuantizationTable_Y[QUANTIZATION_TABLE_SIZE]@ ".mirrorram";
+#pragma data_alignment=32
+static uint8_t QuantizationTable_C[QUANTIZATION_TABLE_SIZE]@ ".mirrorram";
+#else
+static uint8_t QuantizationTable_Y[QUANTIZATION_TABLE_SIZE]__attribute((section("NC_BSS"),aligned(32)));
+static uint8_t QuantizationTable_C[QUANTIZATION_TABLE_SIZE]__attribute((section("NC_BSS"),aligned(32)));
+#endif
+
+/**************************************************************************//**
+ * @brief       Set encode quality
+ * @param[in]   uint8_t                 qual            : Encode quality (1 <= qual <= 100)
+ * @retval      error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::SetQuality(const uint8_t qual) {
+    uint8_t*            pqs[QUANTIZATION_TABLE_NUM];
+    const uint8_t*      pqb[QUANTIZATION_TABLE_NUM];
+    uint8_t*            ptqs;
+    const uint8_t*      ptqb;
+    int_t temp;
+    uint32_t i;
+    uint32_t j;
+
+    /* ITU-T Recommendation T.81 "K.1 Quantization tables for luminance and chrominance components" */
+    /* Table K.1 - Luminance quantization table */
+    const uint8_t quantization_table_y_50[QUANTIZATION_TABLE_SIZE] = {
+        16,  11,  10,  16,  24,  40,  51,  61,
+        12,  12,  14,  19,  26,  58,  60,  55,
+        14,  13,  16,  24,  40,  57,  69,  56,
+        14,  17,  22,  29,  51,  87,  80,  62,
+        18,  22,  37,  56,  68, 109, 103,  77,
+        24,  35,  55,  64,  81, 104, 113,  92,
+        49,  64,  78,  87, 103, 121, 120, 101,
+        72,  92,  95,  98, 112, 100, 103,  99
+    };
+
+    /* Table K.2 - Chrominance quantization table */
+    const uint8_t quantization_table_c_50[QUANTIZATION_TABLE_SIZE] = {
+        17,  18,  24,  47,  99,  99,  99,  99,
+        18,  21,  26,  66,  99,  99,  99,  99,
+        24,  26,  56,  99,  99,  99,  99,  99,
+        47,  66,  99,  99,  99,  99,  99,  99,
+        99,  99,  99,  99,  99,  99,  99,  99,
+        99,  99,  99,  99,  99,  99,  99,  99,
+        99,  99,  99,  99,  99,  99,  99,  99,
+        99,  99,  99,  99,  99,  99,  99,  99
+    };
+
+    if (((int_t)qual < 1) || ((int_t)qual > 100)) {
+        return JPEG_CONV_PARAM_RANGE_ERR;
+    }
+
+    pqs[0] = QuantizationTable_Y;
+    pqb[0] = quantization_table_y_50;
+    pqs[1] = QuantizationTable_C;
+    pqb[1] = quantization_table_c_50;
+
+    for (j = 0; j < QUANTIZATION_TABLE_NUM; j++) {
+        ptqs = pqs[j];
+        ptqb = pqb[j];
+        if ((int_t)qual < 50) {
+            for (i = 0; i < QUANTIZATION_TABLE_SIZE; i++) {
+                temp = (((int_t)ptqb[i] * 100) + (int_t)qual) / (2 * (int_t)qual);
+                if (temp == 0) {
+                    temp = 1;
+                }
+                if (temp > 255) {
+                    temp = 255;
+                }
+                ptqs[i] = (uint8_t)temp;
+            }
+        } else {
+            for (i = 0; i < QUANTIZATION_TABLE_SIZE; i++) {
+                temp = (((200 - (2 * (int_t)qual)) * (int_t)ptqb[i]) + 50) / 100;
+                if (temp == 0) {
+                    temp = 1;
+                }
+                if (temp > 255) {
+                    temp = 255;
+                }
+                ptqs[i] = (uint8_t)temp;
+            }
+        }
+    }
+
+    return JPEG_CONV_OK;
+}
+
+
+/**************************************************************************//**
+ * @brief       Callback function from JCU async mode
+ * @param[in]   mbed_jcu_err_t          err_code       : JCU result
+ * @retval      None
+******************************************************************************/
+void JPEG_CallbackFunction(mbed_jcu_err_t err_code) {
+    if (pJPEG_ConverterCallback != NULL) {
+        pJPEG_ConverterCallback((JPEG_Converter::jpeg_conv_error_t)err_code);
+    }
+    if (err_code != MBED_JCU_E_OK) {
+        jcu_error_flag = true;
+    }
+    jpeg_converter_semaphore.release(); // RELEASE
+} /* End of callback function method () */
+
+/**************************************************************************//**
+ * @brief       Constructor of the JPEG_Converter class
+ * @param[in]   None
+ * @retval      None
+******************************************************************************/
+JPEG_Converter::JPEG_Converter(void) {
+    jcu_errorcode_t           jcu_error;
+    
+    if (driver_ac_count == 0) {
+        SetQuality(75);
+        jcu_error = R_JCU_Initialize(NULL);
+        if (jcu_error == JCU_ERROR_OK) {
+            driver_ac_count++;
+            jcu_error_flag = false;
+        }
+    } else {
+        driver_ac_count++;
+    }
+} /* End of constructor method () */
+
+/**************************************************************************//**
+ * @brief       Destructor of the JPEG_Converter class
+ * @param[in]   None
+ * @retval      None
+******************************************************************************/
+JPEG_Converter::~JPEG_Converter(void) {
+    if (driver_ac_count > 0) {
+        driver_ac_count--;
+        if (driver_ac_count == 0) {
+            (void)R_JCU_Terminate();
+        }
+    }
+} /* End of destructor method () */
+
+/**************************************************************************//**
+ * @brief         JPEG data decode to bitmap
+ * @param[in]     void*                 pJpegBuff       : Input JPEG data address
+ * @param[in/out] bitmap_buff_info_t*   psOutputBuff    : Output bitmap data address
+ * @retval        error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff) {
+    decode_options_t Options;
+    
+    return (decode(pJpegBuff, psOutputBuff, &Options));
+} /* End of method decode() */
+
+/**************************************************************************//**
+ * @brief       JPEG data decode to bitmap
+ * @param[in]     void*                 pJpegBuff       : Input JPEG data address
+ * @param[in/out] bitmap_buff_info_t*   psOutputBuff    : Output bitmap data address
+ * @param[in]     decode_options_t*     pOptions        : Decode option(Optional)
+ * @retval      error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff, decode_options_t* pOptions) {
+    jpeg_conv_error_t           e;
+    jcu_errorcode_t             jcu_error;
+    jcu_decode_param_t          decode;
+    jcu_buffer_param_t          buffer;
+    uint8_t*            pBuff = (uint8_t *)pJpegBuff;
+    const jcu_async_status_t*   status;
+    jcu_image_info_t            image_info;
+    bool                        mutex_release = false;
+    
+    // Check JCU initialized
+    if (driver_ac_count > 0) {
+        size_t calc_height;
+        size_t calc_width;
+        
+        calc_height = psOutputBuff->height * (2 ^ pOptions->vertical_sub_sampling);
+        calc_width  = psOutputBuff->width * (2 ^ pOptions->horizontal_sub_sampling);
+        
+        // Check input address
+        if ((pJpegBuff == NULL) || (psOutputBuff == NULL) || (pOptions == NULL)) {
+            e = JPEG_CONV_PARAM_ERR;  // Input address error
+            goto  fin;
+        }
+        // Check JPEG header
+        if (((uint32_t)(pBuff[0]) != JPEG_HEADER_LETTER_1) ||
+            ((uint32_t)(pBuff[1]) != JPEG_HEADER_LETTER_2)) {
+            e = JPEG_CONV_FORMA_ERR;  // JPEG data is not in ROM
+            goto  fin;
+        }
+        // JCU Error reset
+        if (jcu_error_flag == true) {
+            (void)R_JCU_Terminate();
+            (void)R_JCU_Initialize(NULL);
+            jcu_error_flag = false;
+        }
+        // Get mutex
+        if (pOptions->p_DecodeCallBackFunc == NULL) {
+            jpeg_converter_semaphore.wait(0xFFFFFFFFuL); // WAIT
+        } else {
+            if (!jpeg_converter_semaphore.wait(0)) {
+                e = JPEG_CONV_BUSY;  // Busy
+                goto  fin;
+            }
+        }
+        // Select decode
+        jcu_error = R_JCU_SelectCodec( JCU_DECODE );
+        if (jcu_error != JCU_ERROR_OK) {
+            e = JPEG_CONV_JCU_ERR;
+            mutex_release = true;
+            goto fin;
+        }
+        
+        buffer.source.swapSetting       = JCU_SWAP_LONG_WORD_AND_WORD_AND_BYTE;
+        buffer.source.address           = (uint32_t *)pBuff;
+        buffer.lineOffset               = (int16_t)psOutputBuff->width;
+        buffer.destination.address      = (uint32_t *)psOutputBuff->buffer_address;
+        decode.decodeFormat             = (jcu_decode_format_t)psOutputBuff->format;
+        buffer.destination.swapSetting  = (jcu_swap_t)pOptions->output_swapsetting;
+        decode.outputCbCrOffset         = (jcu_cbcr_offset_t)pOptions->output_cb_cr_offset;
+        decode.alpha                    = pOptions->alpha;
+        decode.horizontalSubSampling    = (jcu_sub_sampling_t)pOptions->horizontal_sub_sampling;
+        decode.verticalSubSampling      = (jcu_sub_sampling_t)pOptions->vertical_sub_sampling;
+
+        jcu_error = R_JCU_SetDecodeParam(&decode, &buffer);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = JPEG_CONV_FORMA_ERR;
+            mutex_release = true;
+            jcu_error_flag = false;
+            goto fin;
+        }
+
+        if (pOptions->check_jpeg_format != false) {
+            jcu_error = R_JCU_SetPauseForImageInfo(true);
+            if (jcu_error != JCU_ERROR_OK) {
+                e = JPEG_CONV_JCU_ERR;
+                mutex_release = true;
+                jcu_error_flag = false;
+                goto fin;
+            }
+        }
+        if (pOptions->p_DecodeCallBackFunc == NULL) {
+            jcu_error = R_JCU_Start();
+            mutex_release = true;
+            if (jcu_error != JCU_ERROR_OK) {
+                e = JPEG_CONV_JCU_ERR;
+                jcu_error_flag = false;
+                goto fin;
+            }
+            if (pOptions->check_jpeg_format != false) {
+                R_JCU_GetAsyncStatus( &status );
+                if (status -> IsPaused == false) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                if ((status->SubStatusFlags & JCU_SUB_INFOMATION_READY) == 0) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                jcu_error = R_JCU_GetImageInfo( &image_info );
+                if (jcu_error != JCU_ERROR_OK) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                if ((image_info.width == 0u) || (image_info.height == 0u) || 
+                    (image_info.width > calc_width) || 
+                    (image_info.height > calc_height)) {
+                    e = JPEG_CONV_FORMA_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                if ((image_info.encodedFormat != JCU_JPEG_YCbCr444) &&
+                    (image_info.encodedFormat != JCU_JPEG_YCbCr422) &&
+                    (image_info.encodedFormat != JCU_JPEG_YCbCr420) &&
+                    (image_info.encodedFormat != JCU_JPEG_YCbCr411)) {
+                    e = JPEG_CONV_FORMA_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                jcu_error = R_JCU_Continue(JCU_IMAGE_INFO);
+                if (jcu_error != JCU_ERROR_OK) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+            }
+        } else {
+            pJPEG_ConverterCallback = pOptions->p_DecodeCallBackFunc;
+            jcu_error = R_wrpper_set_decode_callback((mbed_CallbackFunc_t*)JPEG_CallbackFunction, (size_t)calc_width, calc_height);
+            if (jcu_error != JCU_ERROR_OK) {
+                e = JPEG_CONV_JCU_ERR;
+                mutex_release = true;
+                goto fin;
+            }
+        }
+        e = JPEG_CONV_OK;
+    }
+    else
+    {
+        e = JPEG_CONV_JCU_ERR;
+    }
+fin:
+    if (mutex_release == true) {
+        jpeg_converter_semaphore.release(); // RELEASE
+    }
+
+    return  e;
+} /* End of method decode() */
+
+
+/**************************************************************************//**
+ * @brief       Bitmap data encode to JPEG
+ * @param[in]   bitmap_buff_info_t*     psInputBuff     : Input bitmap data address
+ * @param[out]  void*                   pJpegBuff       : Output JPEG data address
+ * @param[out]  size_t*                 pEncodeSize     : Encode size address
+ * @retval      error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize ) {
+    encode_options_t Options;
+    
+    return (encode(psInputBuff, pJpegBuff, pEncodeSize, &Options));
+} /* End of method encode() */
+
+
+/**************************************************************************//**
+ * @brief       Bitmap data encode to JPEG
+ * @param[in]   bitmap_buff_info_t*     psInputBuff     : Input bitmap data address
+ * @param[out]  void*                   pJpegBuff       : Output JPEG data address
+ * @param[out]  size_t*                 pEncodeSize     : Encode size address
+ * @param[in]   encode_options_t*       pOptions        : Encode option(Optional)
+ * @retval      error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize, encode_options_t* pOptions ) {
+
+    jpeg_conv_error_t   e;
+    jcu_errorcode_t     jcu_error;
+    jcu_buffer_param_t  buffer;
+    uint8_t*            TableAddress;
+    jcu_encode_param_t  encode;
+    jcu_count_mode_param_t      count_para;
+    int32_t     encode_count;
+    int32_t    size_max_count = 1;
+    size_t      BufferSize = pOptions->encode_buff_size;
+    const jcu_async_status_t*  status;
+    bool                        mutex_release = false;
+
+    // Check JCU initialized
+    if (driver_ac_count > 0) {
+        // Check input address
+        if ((pJpegBuff == NULL) || (psInputBuff == NULL) || (pEncodeSize == NULL)) {
+            e = JPEG_CONV_PARAM_ERR;  // Input address error
+            goto  fin;
+        }
+        // JCU Error reset
+        if (jcu_error_flag == true) {
+            (void)R_JCU_Terminate();
+            (void)R_JCU_Initialize(NULL);
+            jcu_error_flag = false;
+        }
+        // Get mutex
+        if ( pOptions->p_EncodeCallBackFunc == NULL ) {
+            jpeg_converter_semaphore.wait(0xFFFFFFFFuL); // WAIT
+        } else {
+            if (!jpeg_converter_semaphore.wait(0)) {
+                e = JPEG_CONV_BUSY;  // Busy
+                goto  fin;
+            }
+        }
+        // Select encode
+        jcu_error = R_JCU_SelectCodec(JCU_ENCODE);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = JPEG_CONV_JCU_ERR;
+            mutex_release = true;
+            goto fin;
+        }
+        /* Set tables */
+        if ( pOptions->quantization_table_Y != NULL ) {
+            TableAddress = (uint8_t*)pOptions->quantization_table_Y;
+        } else {
+            TableAddress = (uint8_t*)QuantizationTable_Y;
+        }
+        jcu_error = R_JCU_SetQuantizationTable( JCU_TABLE_NO_0, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->quantization_table_C != NULL ) {
+            TableAddress = (uint8_t*)pOptions->quantization_table_C;
+        } else {
+            TableAddress = (uint8_t*)QuantizationTable_C;
+        }
+        jcu_error = R_JCU_SetQuantizationTable( JCU_TABLE_NO_1, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_Y_DC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_Y_DC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_Y_DC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_0, JCU_HUFFMAN_DC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_C_DC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_C_DC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_C_DC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_1, JCU_HUFFMAN_DC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_Y_AC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_Y_AC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_Y_AC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_0, JCU_HUFFMAN_AC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_C_AC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_C_AC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_C_AC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_1, JCU_HUFFMAN_AC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+
+        // JPEG encode
+        buffer.source.swapSetting       = (jcu_swap_t)pOptions->input_swapsetting;
+        buffer.source.address           = (uint32_t *)psInputBuff->buffer_address;
+        buffer.destination.swapSetting  = JCU_SWAP_LONG_WORD_AND_WORD_AND_BYTE;
+        buffer.destination.address      = (uint32_t *)pJpegBuff;
+        buffer.lineOffset               = psInputBuff->width;
+        encode.encodeFormat = (jcu_jpeg_format_t)JCU_JPEG_YCbCr422;
+        encode.QuantizationTable[ JCU_ELEMENT_Y  ] = JCU_TABLE_NO_0;
+        encode.QuantizationTable[ JCU_ELEMENT_Cb ] = JCU_TABLE_NO_1;
+        encode.QuantizationTable[ JCU_ELEMENT_Cr ] = JCU_TABLE_NO_1;
+        encode.HuffmanTable[ JCU_ELEMENT_Y  ] = JCU_TABLE_NO_0;
+        encode.HuffmanTable[ JCU_ELEMENT_Cb ] = JCU_TABLE_NO_1;
+        encode.HuffmanTable[ JCU_ELEMENT_Cr ] = JCU_TABLE_NO_1;
+        encode.DRI_value = pOptions->DRI_value;
+        if ( pOptions->width != 0 ) {
+            encode.width  = pOptions->width;
+        } else {
+            encode.width  = psInputBuff->width;
+        }
+        if ( pOptions->height != 0 ) {
+            encode.height = pOptions->height;
+        } else {
+            encode.height = psInputBuff->height;
+        }
+        encode.inputCbCrOffset = (jcu_cbcr_offset_t)pOptions->input_cb_cr_offset;
+        jcu_error = R_JCU_SetEncodeParam( &encode, &buffer );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if (pOptions->encode_buff_size > 0) {
+
+            while(BufferSize > ENC_SIZE_MAX) {
+                size_max_count *= 2;
+                BufferSize /= 2;
+            }
+            BufferSize = BufferSize & MASK_8BYTE;
+            
+            count_para.inputBuffer.isEnable       = false;
+            count_para.inputBuffer.isInitAddress  = false;
+            count_para.inputBuffer.restartAddress = NULL;
+            count_para.inputBuffer.dataCount      = 0;
+            count_para.outputBuffer.isEnable       = true;
+            count_para.outputBuffer.isInitAddress  = false;
+            count_para.outputBuffer.restartAddress = NULL;
+            count_para.outputBuffer.dataCount      = BufferSize;
+            
+            R_JCU_SetCountMode(&count_para);
+        } else {
+            size_max_count = 0;
+        }
+        // Check async
+        if ( pOptions->p_EncodeCallBackFunc == NULL ) {
+            jcu_error = R_JCU_Start();
+            mutex_release = true;
+            if ( jcu_error != JCU_ERROR_OK ) {
+                e = JPEG_CONV_JCU_ERR;
+                jcu_error_flag = true;
+                goto fin;
+            }
+            if (pOptions->encode_buff_size > 0) {
+                // Check Pause flag
+                R_JCU_GetAsyncStatus( &status );
+                for ( encode_count = 1; (encode_count < size_max_count) && (status->IsPaused != false); encode_count++) {
+                    if ((status->SubStatusFlags & JCU_SUB_ENCODE_OUTPUT_PAUSE) == 0) {
+                        e = JPEG_CONV_JCU_ERR;
+                        jcu_error_flag = true;
+                        goto fin;
+                    }
+                    jcu_error = R_JCU_Continue( JCU_OUTPUT_BUFFER );
+                    if (jcu_error != JCU_ERROR_OK) {
+                        e = JPEG_CONV_JCU_ERR;
+                        jcu_error_flag = true;
+                        goto fin;
+                    }
+                    R_JCU_GetAsyncStatus( &status );
+                }
+                if (status->IsPaused != false) {
+                    e = JPEG_CONV_PARAM_RANGE_ERR;
+                    jcu_error_flag = true;
+                    goto fin;
+                }
+            }
+            (void)R_JCU_GetEncodedSize(pEncodeSize);
+        } else {
+            pJPEG_ConverterCallback = pOptions->p_EncodeCallBackFunc;
+            jcu_error = R_wrpper_set_encode_callback((mbed_CallbackFunc_t*)JPEG_CallbackFunction, pEncodeSize, size_max_count);
+            if ( jcu_error != JCU_ERROR_OK ) {
+                e = JPEG_CONV_JCU_ERR;
+                goto fin;
+            }
+        }
+        e = JPEG_CONV_OK;
+    } else {
+        e = JPEG_CONV_PARAM_RANGE_ERR;
+    }
+fin:
+    if (mutex_release == true) {
+        jpeg_converter_semaphore.release(); // RELEASE
+    }
+
+    return  e;
+} /* End of method encode() */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/jcu_driver/TARGET_RZ_A1XX/jcu_reg.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,804 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_reg.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver setting register
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <r_typedefs.h>
+#include    <iodefine.h>
+#include    <r_jcu_api.h>
+#include    <r_jcu_local.h>
+#include    <r_jcu_user.h>
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define NUMBER_OF_QUANTIZATION_TABLE_DATA   (64)
+#define NUMBER_OF_HUFFMAN_TABLE_DATA_DC     (28)
+#define NUMBER_OF_HUFFMAN_TABLE_DATA_AC     (178)
+
+#define CBCR_OFFSET_NUM     (2u)
+
+#define SWAP_NORMAL         (0u)
+#define SWAP_16BIT_OUTPUT   (1u)
+#define SWAP_32BIT_OUTPUT   (2u)
+
+#define KIND_COLOR_FORMAT   (3u)
+#define KIND_LINEOFFSET     (2u)
+#define KIND_TABLE          (4u)
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_UPPER_BYTE( uint32_t const  value );
+STATIC_INLINE uint8_t  GET_LOWER_BYTE( uint32_t const  value );
+static void JCU_GetRegisterForGetErrorInfo(jcu_detail_error_t *const errorCode);
+
+
+/**************************************************************************//**
+* Function Name: [GET_UPPER_BYTE]
+* @brief         GET_UPPER_BYTE
+* @retval        Byte
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_UPPER_BYTE( uint32_t const  value )
+{
+    enum { num_8 = 8 }; /* SEC M1.10.1, QAC-3132 */
+    return  (uint8_t)( value >> num_8 );
+}
+
+/**************************************************************************//**
+* Function Name: [GET_LOWER_BYTE]
+* @brief         GET_LOWER_BYTE
+* @retval        Byte
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_LOWER_BYTE( uint32_t const  value )
+{
+    return  (uint8_t)( value );
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForInitialize]
+* @brief         SetRegisterForInitialize
+* @retval        jcu_errorcode_t
+******************************************************************************/
+jcu_errorcode_t JCU_SetRegisterForInitialize(
+    void)
+{
+    return JCU_ERROR_OK;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForCodec]
+* @brief         SetRegisterForCodec
+* @param[out]    codec
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForCodec(
+    const jcu_codec_t codec)
+{
+    volatile uint8_t DummyRead;
+
+    /* Reset this IP */
+    R_SET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST, REG_F_SET );
+    DummyRead = R_GET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST );
+    R_UNREFERENCED_VARIABLE( DummyRead );
+
+    R_SET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST, REG_F_CLR );
+    DummyRead = R_GET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST );
+    R_UNREFERENCED_VARIABLE( DummyRead );
+
+    R_SET_REG_BIT_FIELD( JCU.JCCMD, BRST, REG_F_SET);
+
+    /* Enable interrupts in registers (Interrupt lines in INTC are still disabled) */
+    /* This registers are set to 0 by reset this IP */
+    /* ->QAC 0306 */
+
+    JCU.JINTE1 = JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+
+    /* Clear the all of count mode settings */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINLC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFESLC = LINES_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFEDDC = JDATAS_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFDSDC = JDATAS_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTLC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFDDLC = LINES_CLEAR;
+    /* <-QAC 0306 */
+
+    /* Set the which process is select */
+    R_SET_REG_BIT_FIELD( JCU.JCMOD, DSP, codec );
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_ClearInterruptFlag]
+* @brief         ClearInterruptFlag
+* @retval        None
+******************************************************************************/
+void JCU_ClearInterruptFlag(
+    void)
+{
+    /* Interrupt request clear */
+    R_SET_REG_BIT_FIELD( JCU.JCCMD, JEND, REG_F_SET);
+
+    /* Clear the JEDI interrupt source flag */
+    /* ->QAC 0306 */
+    JCU.JINTS0 = (uint8_t) 0u;  /* Write 0 only */
+    /* <-QAC 0306 */
+
+    /* Clear the JDTI interrupt source flag */
+    /* ->QAC 0306 */
+    JCU.JINTS1 &= ~JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForStart]
+* @brief         SetRegisterForStart
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForStart(
+    const jcu_int_detail_error_t error_filter)
+{
+    uint32_t reg_jinte0;
+    reg_jinte0 = (uint32_t)JCU.JINTE0 & (uint32_t)(~JCU_INT_ERROR_ALL);
+    JCU.JINTE0 = (uint8_t)( reg_jinte0 | (uint32_t)error_filter );
+    R_SET_REG_BIT_FIELD( JCU.JCCMD, JSRT, REG_F_SET );
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetCountMode]
+* @brief         SetRegisterForSetCountMode
+* @param[in]     buffer
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetCountMode(
+    const jcu_count_mode_param_t    *const buffer)
+{
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF (buffer == NULL) {
+        goto fin;
+    } /* end if */
+
+    IF_DQ ( self == NULL ) {
+        goto fin;
+    } /* end if */
+
+    switch(self->Codec) {
+        case JCU_STATUS_ENCODE:
+            /* ->QAC 0306 */
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINRINI, buffer->inputBuffer.isInitAddress );
+            if ((buffer->inputBuffer.isEnable != false) && (buffer->inputBuffer.isInitAddress != false)) {
+                JCU.JIFESA = (uint32_t)(buffer->inputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFESLC = ( LINES_MASK & (buffer->inputBuffer.dataCount) );
+
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTRINI ,buffer->outputBuffer.isInitAddress );
+            if ((buffer->outputBuffer.isEnable != false) && (buffer->outputBuffer.isInitAddress != false)) {
+                JCU.JIFEDA = (uint32_t)(buffer->outputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFEDDC = ( JDATAS_MASK & ( buffer->outputBuffer.dataCount ) );
+            /* <-QAC 0306 */
+
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINLC ,buffer->inputBuffer.isEnable );
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTC ,buffer->outputBuffer.isEnable );
+            break;
+
+        case JCU_STATUS_DECODE:
+            /* ->QAC 0306 */
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINRINI ,buffer->inputBuffer.isInitAddress );
+            if ((buffer->inputBuffer.isEnable != false) && (buffer->inputBuffer.isInitAddress != false)) {
+                JCU.JIFDSA = (uint32_t)(buffer->inputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFDSDC = ( JDATAS_MASK & (buffer->inputBuffer.dataCount ) );
+
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTRINI, buffer->outputBuffer.isInitAddress );
+            if ((buffer->outputBuffer.isEnable != false) && (buffer->outputBuffer.isInitAddress != false)) {
+                JCU.JIFDDA = (uint32_t)(buffer->outputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFDDLC = ( LINES_MASK & ( buffer->outputBuffer.dataCount ) );
+            /* <-QAC 0306 */
+
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINC, buffer->inputBuffer.isEnable );
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTLC, buffer->outputBuffer.isEnable );
+            break;
+
+        case JCU_CODEC_NOT_SELECTED:
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForContinue]
+* @brief         SetRegisterForContinue
+* @param[in]     type
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForContinue(
+    const jcu_continue_type_t  type)
+{
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF_DQ ( self == NULL ) {
+        goto fin;
+    } /* end if */
+
+    /* Restart register setting */
+    switch (type) {
+        case JCU_INPUT_BUFFER:
+            if (self->Codec == JCU_STATUS_DECODE) {
+                R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINRCMD, REG_F_SET );
+            } else {
+                R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINRCMD, REG_F_SET );
+            } /* end if */
+            break;
+
+        case JCU_OUTPUT_BUFFER:
+            if (self->Codec == JCU_STATUS_DECODE) {
+                R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTRCMD, REG_F_SET );
+            } else {
+                R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTRCMD, REG_F_SET );
+            } /* end if */
+            break;
+
+        case JCU_IMAGE_INFO:
+            R_SET_REG_BIT_FIELD( JCU.JCCMD, JRST, REG_F_SET );
+            break;
+
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetDecodePrm]
+* @brief         SetRegisterForSetDecod
+* @param[in]     decode
+* @param[in]     buffer
+* @param[in]     interruptKind
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetDecodePrm(
+    const jcu_decode_param_t   *const decode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    const uint32_t byteSize[KIND_COLOR_FORMAT] =
+        /* ->SEC M1.10.1 Table data. */
+    {
+        2u, /* JCU_OUTPUT_YCbCr422 */
+        4u, /* JCU_OUTPUT_ARGB8888 */
+        2u  /* JCU_OUTPUT_RGB565   */
+    };
+    /* <-SEC M1.10.1 */
+
+    if ((decode == NULL) || (buffer == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Settings for the cull */
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, VINTER, decode->verticalSubSampling );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, HINTER, decode->horizontalSubSampling );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, OPF, decode->decodeFormat );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINSWAP, buffer->source.swapSetting );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTSWAP, buffer->destination.swapSetting );
+
+    /* Settings for input jpeg file information */
+    /* ->QAC 0306 */
+    JCU.JIFDSA = (uint32_t)(buffer->source.address);
+    /* <-QAC 0306 */
+    /* Settings for output image data information */
+    /* ->QAC 0306 */
+    JCU.JIFDDA = (uint32_t)(buffer->destination.address);
+    /* <-QAC 0306 */
+    R_SET_REG_BIT_FIELD( JCU.JIFDDOFST, DDMW, ((uint32_t)buffer->lineOffset * (uint32_t)(byteSize[decode->decodeFormat])) );
+    R_SET_REG_BIT_FIELD( JCU.JIFDADT, ALPHA, (uint32_t)(decode->alpha) );
+
+
+    /* Setting for Cb/Cr offset */
+    R_SET_REG_BIT_FIELD( JCU.JIFESHSZ, DOUTYCHG, decode->outputCbCrOffset );
+fin:
+    return;
+
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetQtTable]
+* @brief         SetRegisterForSetQtTable
+* @param[in]     tableNo
+* @param[in]     table
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetQtTable(
+    const jcu_table_no_t   tableNo,
+    const uint8_t *const   table)
+{
+    volatile uint8_t  *tableAtRegister;
+    int_fast32_t       counter;
+
+    /* Select the destination of the Quantization table */
+    switch (tableNo) {
+            /* ->QAC 0306 */
+        case JCU_TABLE_NO_0:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL0;
+            break;
+        case JCU_TABLE_NO_1:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL1;
+            break;
+        case JCU_TABLE_NO_2:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL2;
+            break;
+        case JCU_TABLE_NO_3:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL3;
+            break;
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            /* NOT REACHED */
+            return;
+            /* <-QAC 0306 */
+    } /* end switch */
+
+    IF ((tableAtRegister == NULL) || (table == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Update the quantization table data */
+    for (counter = 0; counter < NUMBER_OF_QUANTIZATION_TABLE_DATA; counter++) {
+        tableAtRegister[ counter ] = table[ counter ];
+    } /* end for */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetHuffTbl]
+* @brief         SetRegisterForSetHuffTbl
+* @param[in]     tableNo
+* @param[in]     type
+* @param[in]     table
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetHuffTbl(
+    const jcu_table_no_t   tableNo,
+    const jcu_huff_t       type,
+    const uint8_t         *table)
+{
+    volatile uint8_t  *tableAtRegister;
+    int_fast32_t       copyCount;
+    int_fast32_t       counter;
+
+    /* Select the destination Huffman table and the size of copy data */
+    if (tableNo == JCU_TABLE_NO_0) {
+        /* ->QAC 0306 */
+        if (type == JCU_HUFFMAN_DC) {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBD0;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_DC;
+        } else {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBA0;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_AC;
+        } /* end if */
+        /* <-QAC 0306 */
+    } else {
+        /* ->QAC 0306 */
+        if (type == JCU_HUFFMAN_DC) {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBD1;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_DC;
+        } else {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBA1;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_AC;
+        } /* end if */
+        /* <-QAC 0306 */
+    }  /* end if */
+
+    IF(table == NULL) {
+        goto fin;
+    } /* end if */
+
+    /* Update the Huffman table */
+    for (counter = 0; counter < copyCount; counter++) {
+        tableAtRegister[ counter ] = table[ counter ];
+    } /* end for */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetEncodePrm]
+* @brief         SetRegisterForSetEncode
+* @param[in]     encode
+* @param[in]     buffer
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetEncodePrm(
+    const jcu_encode_param_t   *const encode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    jcu_jpeg_format_t encodeFormatTemp;
+    const uint32_t byteSize[KIND_LINEOFFSET] =
+        /* ->SEC M1.10.1 Table data. */
+    {
+        0u, /* Reserved          */
+        2u  /* JCU_JPEG_YCbCr422 */
+    };
+    /* <-SEC M1.10.1 */
+
+    IF ((encode == NULL) || (buffer == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Settings for the input image format */
+    R_SET_REG_BIT_FIELD( JCU.JCMOD, REDU, encode->encodeFormat );
+
+    /* Settings for the quantization table */
+    R_SET_REG_BIT_FIELD( JCU.JCQTN, QT1, encode->QuantizationTable[JCU_ELEMENT_Y]  );
+    R_SET_REG_BIT_FIELD( JCU.JCQTN, QT2, encode->QuantizationTable[JCU_ELEMENT_Cb]  );
+    R_SET_REG_BIT_FIELD( JCU.JCQTN, QT3, encode->QuantizationTable[JCU_ELEMENT_Cr]  );
+
+    /* Settings for the Huffman table */
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTA1, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Y])  );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTD1, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Y])  );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTA2, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cb]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTD2, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cb]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTA3, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cr]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTD3, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cr]) );
+
+    /* ->QAC 0306 */
+    JCU.JCDRIU = GET_UPPER_BYTE(encode->DRI_value);
+    JCU.JCDRID = GET_LOWER_BYTE(encode->DRI_value);
+    /* Settings for the image size */
+    /* width setting */
+    JCU.JCHSZU = GET_UPPER_BYTE(encode->width);
+    JCU.JCHSZD = GET_LOWER_BYTE(encode->width);
+    /* height setting */
+    JCU.JCVSZU = GET_UPPER_BYTE(encode->height);
+    JCU.JCVSZD = GET_LOWER_BYTE(encode->height);
+    /* <-QAC 0306 */
+
+
+    /* Settings for input jpeg file information */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINSWAP, buffer->source.swapSetting );
+
+    /* ->QAC 0306 */
+    JCU.JIFESA              = (uint32_t)(buffer->source.address);
+    /* <-QAC 0306 */
+
+    /* Settings for output image data information */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTSWAP, buffer->destination.swapSetting );
+
+    /* ->QAC 0306 */
+    JCU.JIFEDA = (uint32_t)(buffer->destination.address);
+    /* <-QAC 0306 */
+
+    encodeFormatTemp = encode->encodeFormat;
+    if((encodeFormatTemp != JCU_JPEG_YCbCr444) && (encodeFormatTemp != JCU_JPEG_YCbCr422)) {
+        encodeFormatTemp = JCU_JPEG_YCbCr444;
+    } /* end if */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFESOFST, ESMW, ((uint32_t)buffer->lineOffset * (uint32_t)(byteSize[encodeFormatTemp])) );
+
+    /* Setting for Cb/Cr offset */
+    R_SET_REG_BIT_FIELD( JCU.JIFESVSZ, DINYCHG, encode->inputCbCrOffset );
+fin:
+    return;
+
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetPause]
+* @brief
+* @param[out]    is_stop
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetPause( const bool_t is_pause, const jcu_int_detail_errors_t filter )
+{
+    /* ->QAC 0306 */
+    if ( IS( is_pause ) ) {
+        JCU.JINTE0 = filter | INT3_MASK;
+    } else {
+        JCU.JINTE0 = filter;
+    }
+    /* <-QAC 0306 */
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetRegisterForGetImageInfo]
+* @brief         Get "jcu_image_info_t" type value
+* @param[out]    buffer  :jcu_image_info_t
+* @retval        None
+******************************************************************************/
+void JCU_GetRegisterForGetImageInfo(
+    jcu_image_info_t *const buffer)
+{
+    if (buffer == NULL) {
+        goto fin;
+    } /* end if */
+
+    /* Set the register value to the variables */
+    /* ->QAC 0306 */
+    buffer->width           = ((uint32_t)JCU.JCHSZU << SHIFT_8BITS);
+    buffer->width           |= (uint32_t)JCU.JCHSZD;
+    buffer->height          = ((uint32_t)JCU.JCVSZU << SHIFT_8BITS);
+    buffer->height          |= (uint32_t)JCU.JCVSZD;
+    buffer->encodedFormat   = (jcu_jpeg_format_t)R_GET_REG_BIT_FIELD( JCU.JCMOD, REDU );
+    /* <-QAC 0306 */
+
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetRegisterForGetErrorInfo]
+* @brief         Get "jcu_detail_error_t" type value
+* @param[out]    errorCode
+* @retval        None
+******************************************************************************/
+static void JCU_GetRegisterForGetErrorInfo(
+    jcu_detail_error_t *const errorCode)
+{
+    if (errorCode != NULL) {
+        /* ->QAC 0306 */
+        uint8_t const  code = R_GET_REG_BIT_FIELD( JCU.JCDERR, ERR );
+        /* <-QAC 0306 */
+
+        if ( (uint_fast8_t) code == 0u ) {
+            *errorCode = JCU_JCDERR_OK;
+        } else {
+            *errorCode = (jcu_detail_error_t)( (int_t) code + E_CATEGORY_JCU_JCDERR );
+        }
+    } /* end if */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetEncodedSize]
+* @brief         GetEncodedSize
+* @param[out]    out_Size
+* @retval        None
+******************************************************************************/
+void JCU_GetEncodedSize(
+    size_t *const out_Size)
+{
+    if (out_Size != NULL) {
+        /* ->QAC 0306 */
+        *out_Size = (((uint32_t)JCU.JCDTCU) << SHIFT_16BITS);
+        *out_Size |= (((uint32_t)JCU.JCDTCM) << SHIFT_8BITS);
+        *out_Size |= ((uint32_t)JCU.JCDTCD);
+        /* <-QAC 0306 */
+    } /* end if */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInterrupting]
+* @brief         Operations on interrupting
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource )
+{
+    errnum_t  e;
+    uint32_t  flags0;
+    uint32_t  flags1;
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    R_UNREFERENCED_VARIABLE( InterruptSource );
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    ASSERT_R( self->AsyncStatus.Status == JCU_STATUS_INTERRUPTING,  e=E_STATE; goto fin );
+
+    /* Get interrupt status */
+    /* ->QAC 0306 */
+    flags0 = JCU.JINTS0;
+    flags1 = JCU.JINTS1;
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptFlags, flags0 );
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptFlags, flags1 << JCU_SHIFT_JINTS1 );
+
+    /* Clear interrupt status "JINTS0" */
+    if ( flags0 != 0u ) {
+        R_SET_REG_BIT_FIELD( JCU.JCCMD, JEND, 1u );
+        JCU.JINTS0 = (uint8_t) 0u;  /* Write 0 only */
+    }
+
+    /* Clear interrupt status "JINTS1" */
+    JCU.JINTS1 = ~flags1 & JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+
+    /* Set state */
+    self->AsyncStatus.Status = JCU_STATUS_INTERRUPTED;
+
+    e=0;
+fin:
+    return  e;
+}
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInterrupted]
+* @brief         Bottom half operations on interrupting
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterrupted(void)
+{
+    bit_flags32_t const  sub_status_bits =
+        ( INS3_MASK ) |
+        ( JINF_MASK   << JCU_SHIFT_JINTS1 ) |
+        ( DOUTLF_MASK << JCU_SHIFT_JINTS1 ) |
+        ( DINLF_MASK  << JCU_SHIFT_JINTS1 ) |
+        ( JOUTF_MASK  << JCU_SHIFT_JINTS1 );
+
+    errnum_t         e;
+    uint32_t         cancel_flag;
+    uint32_t         interrupt_flags;
+    bool_t           was_enabled = false;
+    bool_t           is_end;
+    bool_t           or;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t  *notify_async_1 = NULL;
+    r_ospl_async_t  *notify_async_2 = NULL;
+    jcu_i_lock_t *const                i_lock = R_JCU_GetILockObject();
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+    ASSERT_R( self->AsyncStatus.Status != JCU_STATUS_UNDEF,  e=E_STATE; goto fin );
+
+    interrupt_flags = R_OSPL_FLAG32_GetAndClear( &self->AsyncStatus.InterruptFlags );
+
+
+    if ( IS_ANY_BITS_SET( interrupt_flags, sub_status_bits ) ) {
+        if ( IS_BIT_NOT_SET( interrupt_flags, INS6_MASK ) ) {
+            self->AsyncStatus.IsPaused = true;
+            self->AsyncStatus.SubStatusFlags = interrupt_flags & sub_status_bits;
+        }
+    }
+
+
+    if ( IS_ANY_BITS_SET( interrupt_flags, INS6_MASK ) ) {
+        is_end = true;
+    } else {
+        is_end = false;
+    }
+
+
+    or = ( (is_end) || (self->AsyncStatus.IsPaused) );
+    if (!or) {
+        or = IS_BIT_SET( interrupt_flags, INS5_MASK );
+    }
+    if (IS( or )) {
+        /* Set "AsyncStatus" */
+        R_OSPL_FLAG32_Clear( &self->AsyncStatus.InterruptEnables, JCU_INTERRUPT_LINE_ALL );
+        self->AsyncStatus.Status = JCU_STATUS_READY;
+        notify_async_1 = self->InterruptCallbackCaller.Async;
+    } else {
+        self->AsyncStatus.Status = JCU_STATUS_RUN;
+    }
+
+
+    IF ( IS_BIT_SET( interrupt_flags, INS5_MASK ) ) {
+        jcu_detail_error_t  ed;
+
+        JCU_GetRegisterForGetErrorInfo( &ed );
+        e = ed;
+        goto fin;
+    }
+
+
+    if ( notify_async_1 != NULL ) {
+        cancel_flag = R_OSPL_FLAG32_Get( &self->AsyncStatus.CancelFlags );
+        if ( IS_BIT_SET( cancel_flag, R_OSPL_FINALIZE_REQUEST ) ) {
+            notify_async_2 = self->AsyncForFinalize;
+            ej= R_JCU_TerminateStep2();
+            IF ( ej != JCU_ERROR_OK ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+    e=0;
+fin:
+    if ( IS( was_enabled ) ) {
+        /* ->QAC 3353 : "self" is always assigned, if "was_enabled" is true */
+        IF_DQ( self == NULL ) {}  /* QAC 3353 raises SEC R3.2.2 */
+        else {
+            self->I_LockVTable->Unlock( self->I_Lock );
+
+            if ( IS( self->Is_I_LockMaster ) ) {
+                IF_DQ( i_lock == NULL ) {}
+                else {
+                    if ( IS( i_lock->IsRequestedFinalize ) ) {
+                        R_JCU_I_LOCK_Finalize();
+                    }
+                }
+            }
+        }
+        /* <-QAC 3353 */
+    }
+
+    if ( notify_async_1 != NULL ) {
+        R_OSPL_EVENT_Set( notify_async_1->A_Thread, notify_async_1->A_EventValue );
+    }
+    if ( notify_async_2 != NULL ) {
+        R_OSPL_EVENT_Set( notify_async_2->A_Thread, notify_async_2->A_EventValue );
+    }
+
+    return  e;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/jcu_driver/TARGET_RZ_A2XX/jcu_reg.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,802 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_reg.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver setting register
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <r_typedefs.h>
+#include    <iodefine.h>
+#include    <r_jcu_api.h>
+#include    <r_jcu_local.h>
+#include    <r_jcu_user.h>
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define NUMBER_OF_QUANTIZATION_TABLE_DATA   (64)
+#define NUMBER_OF_HUFFMAN_TABLE_DATA_DC     (28)
+#define NUMBER_OF_HUFFMAN_TABLE_DATA_AC     (178)
+
+#define CBCR_OFFSET_NUM     (2u)
+
+#define SWAP_NORMAL         (0u)
+#define SWAP_16BIT_OUTPUT   (1u)
+#define SWAP_32BIT_OUTPUT   (2u)
+
+#define KIND_COLOR_FORMAT   (3u)
+#define KIND_LINEOFFSET     (2u)
+#define KIND_TABLE          (4u)
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_UPPER_BYTE( uint32_t const  value );
+STATIC_INLINE uint8_t  GET_LOWER_BYTE( uint32_t const  value );
+static void JCU_GetRegisterForGetErrorInfo(jcu_detail_error_t *const errorCode);
+
+
+/**************************************************************************//**
+* Function Name: [GET_UPPER_BYTE]
+* @brief         GET_UPPER_BYTE
+* @retval        Byte
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_UPPER_BYTE( uint32_t const  value )
+{
+    enum { num_8 = 8 }; /* SEC M1.10.1, QAC-3132 */
+    return  (uint8_t)( value >> num_8 );
+}
+
+/**************************************************************************//**
+* Function Name: [GET_LOWER_BYTE]
+* @brief         GET_LOWER_BYTE
+* @retval        Byte
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_LOWER_BYTE( uint32_t const  value )
+{
+    return  (uint8_t)( value );
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForInitialize]
+* @brief         SetRegisterForInitialize
+* @retval        jcu_errorcode_t
+******************************************************************************/
+jcu_errorcode_t JCU_SetRegisterForInitialize(
+    void)
+{
+    return JCU_ERROR_OK;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForCodec]
+* @brief         SetRegisterForCodec
+* @param[out]    codec
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForCodec(
+    const jcu_codec_t codec)
+{
+    volatile uint8_t DummyRead;
+
+    /* Reset this IP */
+    CPG.SWRSTCR1.BIT.SRST11 = 1;
+    DummyRead = CPG.SWRSTCR1.BYTE;
+    CPG.SWRSTCR1.BIT.SRST11 = 0;
+    DummyRead = CPG.SWRSTCR1.BYTE;
+    (void)DummyRead;
+
+    R_SET_REG_BIT_FIELD( JCU.JCCMD.BYTE, BRST, REG_F_SET);
+
+    /* Enable interrupts in registers (Interrupt lines in INTC are still disabled) */
+    /* This registers are set to 0 by reset this IP */
+    /* ->QAC 0306 */
+
+    JCU.JINTE1.LONG = JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+
+    /* Clear the all of count mode settings */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, DINLC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, DINRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFESLC.LONG = LINES_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, JOUTC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, JOUTRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFEDDC.LONG = JDATAS_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, JINC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, JINRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFDSDC.LONG = JDATAS_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, DOUTLC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, DOUTRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFDDLC.LONG = LINES_CLEAR;
+    /* <-QAC 0306 */
+
+    /* Set the which process is select */
+    R_SET_REG_BIT_FIELD( JCU.JCMOD.BYTE, DSP, codec );
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_ClearInterruptFlag]
+* @brief         ClearInterruptFlag
+* @retval        None
+******************************************************************************/
+void JCU_ClearInterruptFlag(
+    void)
+{
+    /* Interrupt request clear */
+    R_SET_REG_BIT_FIELD( JCU.JCCMD.BYTE, JEND, REG_F_SET);
+
+    /* Clear the JEDI interrupt source flag */
+    /* ->QAC 0306 */
+    JCU.JINTS0.BYTE = (uint8_t) 0u;  /* Write 0 only */
+    /* <-QAC 0306 */
+
+    /* Clear the JDTI interrupt source flag */
+    /* ->QAC 0306 */
+    JCU.JINTS1.LONG &= ~JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForStart]
+* @brief         SetRegisterForStart
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForStart(
+    const jcu_int_detail_error_t error_filter)
+{
+    uint32_t reg_jinte0;
+    reg_jinte0 = (uint32_t)JCU.JINTE0.BYTE & (uint32_t)(~JCU_INT_ERROR_ALL);
+    JCU.JINTE0.BYTE = (uint8_t)( reg_jinte0 | (uint32_t)error_filter );
+    R_SET_REG_BIT_FIELD( JCU.JCCMD.BYTE, JSRT, REG_F_SET );
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetCountMode]
+* @brief         SetRegisterForSetCountMode
+* @param[in]     buffer
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetCountMode(
+    const jcu_count_mode_param_t    *const buffer)
+{
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF (buffer == NULL) {
+        goto fin;
+    } /* end if */
+
+    IF_DQ ( self == NULL ) {
+        goto fin;
+    } /* end if */
+
+    switch(self->Codec) {
+        case JCU_STATUS_ENCODE:
+            /* ->QAC 0306 */
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, DINRINI, buffer->inputBuffer.isInitAddress );
+            if ((buffer->inputBuffer.isEnable != false) && (buffer->inputBuffer.isInitAddress != false)) {
+                JCU.JIFESA.LONG = (uint32_t)(buffer->inputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFESLC.LONG = ( LINES_MASK & (buffer->inputBuffer.dataCount) );
+
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, JOUTRINI ,buffer->outputBuffer.isInitAddress );
+            if ((buffer->outputBuffer.isEnable != false) && (buffer->outputBuffer.isInitAddress != false)) {
+                JCU.JIFEDA.LONG = (uint32_t)(buffer->outputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFEDDC.LONG = ( JDATAS_MASK & ( buffer->outputBuffer.dataCount ) );
+            /* <-QAC 0306 */
+
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, DINLC ,buffer->inputBuffer.isEnable );
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, JOUTC ,buffer->outputBuffer.isEnable );
+            break;
+
+        case JCU_STATUS_DECODE:
+            /* ->QAC 0306 */
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, JINRINI ,buffer->inputBuffer.isInitAddress );
+            if ((buffer->inputBuffer.isEnable != false) && (buffer->inputBuffer.isInitAddress != false)) {
+                JCU.JIFDSA.LONG = (uint32_t)(buffer->inputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFDSDC.LONG = ( JDATAS_MASK & (buffer->inputBuffer.dataCount ) );
+
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, DOUTRINI, buffer->outputBuffer.isInitAddress );
+            if ((buffer->outputBuffer.isEnable != false) && (buffer->outputBuffer.isInitAddress != false)) {
+                JCU.JIFDDA.LONG = (uint32_t)(buffer->outputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFDDLC.LONG = ( LINES_MASK & ( buffer->outputBuffer.dataCount ) );
+            /* <-QAC 0306 */
+
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, JINC, buffer->inputBuffer.isEnable );
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, DOUTLC, buffer->outputBuffer.isEnable );
+            break;
+
+        case JCU_CODEC_NOT_SELECTED:
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForContinue]
+* @brief         SetRegisterForContinue
+* @param[in]     type
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForContinue(
+    const jcu_continue_type_t  type)
+{
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF_DQ ( self == NULL ) {
+        goto fin;
+    } /* end if */
+
+    /* Restart register setting */
+    switch (type) {
+        case JCU_INPUT_BUFFER:
+            if (self->Codec == JCU_STATUS_DECODE) {
+                R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, JINRCMD, REG_F_SET );
+            } else {
+                R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, DINRCMD, REG_F_SET );
+            } /* end if */
+            break;
+
+        case JCU_OUTPUT_BUFFER:
+            if (self->Codec == JCU_STATUS_DECODE) {
+                R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, DOUTRCMD, REG_F_SET );
+            } else {
+                R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, JOUTRCMD, REG_F_SET );
+            } /* end if */
+            break;
+
+        case JCU_IMAGE_INFO:
+            R_SET_REG_BIT_FIELD( JCU.JCCMD.BYTE, JRST, REG_F_SET );
+            break;
+
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetDecodePrm]
+* @brief         SetRegisterForSetDecod
+* @param[in]     decode
+* @param[in]     buffer
+* @param[in]     interruptKind
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetDecodePrm(
+    const jcu_decode_param_t   *const decode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    const uint32_t byteSize[KIND_COLOR_FORMAT] =
+        /* ->SEC M1.10.1 Table data. */
+    {
+        2u, /* JCU_OUTPUT_YCbCr422 */
+        4u, /* JCU_OUTPUT_ARGB8888 */
+        2u  /* JCU_OUTPUT_RGB565   */
+    };
+    /* <-SEC M1.10.1 */
+
+    if ((decode == NULL) || (buffer == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Settings for the cull */
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, VINTER, decode->verticalSubSampling );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, HINTER, decode->horizontalSubSampling );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, OPF, decode->decodeFormat );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, JINSWAP, buffer->source.swapSetting );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT.LONG, DOUTSWAP, buffer->destination.swapSetting );
+
+    /* Settings for input jpeg file information */
+    /* ->QAC 0306 */
+    JCU.JIFDSA.LONG = (uint32_t)(buffer->source.address);
+    /* <-QAC 0306 */
+    /* Settings for output image data information */
+    /* ->QAC 0306 */
+    JCU.JIFDDA.LONG = (uint32_t)(buffer->destination.address);
+    /* <-QAC 0306 */
+    R_SET_REG_BIT_FIELD( JCU.JIFDDOFST.LONG, DDMW, ((uint32_t)buffer->lineOffset * (uint32_t)(byteSize[decode->decodeFormat])) );
+    R_SET_REG_BIT_FIELD( JCU.JIFDADT.LONG, ALPHA, (uint32_t)(decode->alpha) );
+
+
+    /* Setting for Cb/Cr offset */
+    R_SET_REG_BIT_FIELD( JCU.JIFESHSZ.LONG, DOUTYCHG, decode->outputCbCrOffset );
+fin:
+    return;
+
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetQtTable]
+* @brief         SetRegisterForSetQtTable
+* @param[in]     tableNo
+* @param[in]     table
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetQtTable(
+    const jcu_table_no_t   tableNo,
+    const uint8_t *const   table)
+{
+    volatile uint8_t  *tableAtRegister;
+    int_fast32_t       counter;
+
+    /* Select the destination of the Quantization table */
+    switch (tableNo) {
+            /* ->QAC 0306 */
+        case JCU_TABLE_NO_0:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL0;
+            break;
+        case JCU_TABLE_NO_1:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL1;
+            break;
+        case JCU_TABLE_NO_2:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL2;
+            break;
+        case JCU_TABLE_NO_3:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL3;
+            break;
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            /* NOT REACHED */
+            return;
+            /* <-QAC 0306 */
+    } /* end switch */
+
+    IF ((tableAtRegister == NULL) || (table == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Update the quantization table data */
+    for (counter = 0; counter < NUMBER_OF_QUANTIZATION_TABLE_DATA; counter++) {
+        tableAtRegister[ counter ] = table[ counter ];
+    } /* end for */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetHuffTbl]
+* @brief         SetRegisterForSetHuffTbl
+* @param[in]     tableNo
+* @param[in]     type
+* @param[in]     table
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetHuffTbl(
+    const jcu_table_no_t   tableNo,
+    const jcu_huff_t       type,
+    const uint8_t         *table)
+{
+    volatile uint8_t  *tableAtRegister;
+    int_fast32_t       copyCount;
+    int_fast32_t       counter;
+
+    /* Select the destination Huffman table and the size of copy data */
+    if (tableNo == JCU_TABLE_NO_0) {
+        /* ->QAC 0306 */
+        if (type == JCU_HUFFMAN_DC) {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBD0;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_DC;
+        } else {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBA0;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_AC;
+        } /* end if */
+        /* <-QAC 0306 */
+    } else {
+        /* ->QAC 0306 */
+        if (type == JCU_HUFFMAN_DC) {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBD1;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_DC;
+        } else {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBA1;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_AC;
+        } /* end if */
+        /* <-QAC 0306 */
+    }  /* end if */
+
+    IF(table == NULL) {
+        goto fin;
+    } /* end if */
+
+    /* Update the Huffman table */
+    for (counter = 0; counter < copyCount; counter++) {
+        tableAtRegister[ counter ] = table[ counter ];
+    } /* end for */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetEncodePrm]
+* @brief         SetRegisterForSetEncode
+* @param[in]     encode
+* @param[in]     buffer
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetEncodePrm(
+    const jcu_encode_param_t   *const encode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    jcu_jpeg_format_t encodeFormatTemp;
+    const uint32_t byteSize[KIND_LINEOFFSET] =
+        /* ->SEC M1.10.1 Table data. */
+    {
+        0u, /* Reserved          */
+        2u  /* JCU_JPEG_YCbCr422 */
+    };
+    /* <-SEC M1.10.1 */
+
+    IF ((encode == NULL) || (buffer == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Settings for the input image format */
+    R_SET_REG_BIT_FIELD( JCU.JCMOD.BYTE, REDU, encode->encodeFormat );
+
+    /* Settings for the quantization table */
+    R_SET_REG_BIT_FIELD( JCU.JCQTN.BYTE, QT1, encode->QuantizationTable[JCU_ELEMENT_Y]  );
+    R_SET_REG_BIT_FIELD( JCU.JCQTN.BYTE, QT2, encode->QuantizationTable[JCU_ELEMENT_Cb]  );
+    R_SET_REG_BIT_FIELD( JCU.JCQTN.BYTE, QT3, encode->QuantizationTable[JCU_ELEMENT_Cr]  );
+
+    /* Settings for the Huffman table */
+    R_SET_REG_BIT_FIELD( JCU.JCHTN.BYTE, HTA1, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Y])  );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN.BYTE, HTD1, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Y])  );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN.BYTE, HTA2, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cb]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN.BYTE, HTD2, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cb]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN.BYTE, HTA3, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cr]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN.BYTE, HTD3, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cr]) );
+
+    /* ->QAC 0306 */
+    JCU.JCDRIU.BYTE = GET_UPPER_BYTE(encode->DRI_value);
+    JCU.JCDRID.BYTE = GET_LOWER_BYTE(encode->DRI_value);
+    /* Settings for the image size */
+    /* width setting */
+    JCU.JCHSZU.BYTE = GET_UPPER_BYTE(encode->width);
+    JCU.JCHSZD.BYTE = GET_LOWER_BYTE(encode->width);
+    /* height setting */
+    JCU.JCVSZU.BYTE = GET_UPPER_BYTE(encode->height);
+    JCU.JCVSZD.BYTE = GET_LOWER_BYTE(encode->height);
+    /* <-QAC 0306 */
+
+
+    /* Settings for input jpeg file information */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, DINSWAP, buffer->source.swapSetting );
+
+    /* ->QAC 0306 */
+    JCU.JIFESA.LONG              = (uint32_t)(buffer->source.address);
+    /* <-QAC 0306 */
+
+    /* Settings for output image data information */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT.LONG, JOUTSWAP, buffer->destination.swapSetting );
+
+    /* ->QAC 0306 */
+    JCU.JIFEDA.LONG = (uint32_t)(buffer->destination.address);
+    /* <-QAC 0306 */
+
+    encodeFormatTemp = encode->encodeFormat;
+    if((encodeFormatTemp != JCU_JPEG_YCbCr444) && (encodeFormatTemp != JCU_JPEG_YCbCr422)) {
+        encodeFormatTemp = JCU_JPEG_YCbCr444;
+    } /* end if */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFESOFST.LONG, ESMW, ((uint32_t)buffer->lineOffset * (uint32_t)(byteSize[encodeFormatTemp])) );
+
+    /* Setting for Cb/Cr offset */
+    R_SET_REG_BIT_FIELD( JCU.JIFESVSZ.LONG, DINYCHG, encode->inputCbCrOffset );
+fin:
+    return;
+
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetPause]
+* @brief
+* @param[out]    is_stop
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetPause( const bool_t is_pause, const jcu_int_detail_errors_t filter )
+{
+    /* ->QAC 0306 */
+    if ( IS( is_pause ) ) {
+        JCU.JINTE0.BYTE = filter | INT3_MASK;
+    } else {
+        JCU.JINTE0.BYTE = filter;
+    }
+    /* <-QAC 0306 */
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetRegisterForGetImageInfo]
+* @brief         Get "jcu_image_info_t" type value
+* @param[out]    buffer  :jcu_image_info_t
+* @retval        None
+******************************************************************************/
+void JCU_GetRegisterForGetImageInfo(
+    jcu_image_info_t *const buffer)
+{
+    if (buffer == NULL) {
+        goto fin;
+    } /* end if */
+
+    /* Set the register value to the variables */
+    /* ->QAC 0306 */
+    buffer->width           = ((uint32_t)JCU.JCHSZU.BYTE << SHIFT_8BITS);
+    buffer->width           |= (uint32_t)JCU.JCHSZD.BYTE;
+    buffer->height          = ((uint32_t)JCU.JCVSZU.BYTE << SHIFT_8BITS);
+    buffer->height          |= (uint32_t)JCU.JCVSZD.BYTE;
+    buffer->encodedFormat   = (jcu_jpeg_format_t)R_GET_REG_BIT_FIELD( JCU.JCMOD.BYTE, REDU );
+    /* <-QAC 0306 */
+
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetRegisterForGetErrorInfo]
+* @brief         Get "jcu_detail_error_t" type value
+* @param[out]    errorCode
+* @retval        None
+******************************************************************************/
+static void JCU_GetRegisterForGetErrorInfo(
+    jcu_detail_error_t *const errorCode)
+{
+    if (errorCode != NULL) {
+        /* ->QAC 0306 */
+        uint8_t const  code = R_GET_REG_BIT_FIELD( JCU.JCDERR.BYTE, ERR );
+        /* <-QAC 0306 */
+
+        if ( (uint_fast8_t) code == 0u ) {
+            *errorCode = JCU_JCDERR_OK;
+        } else {
+            *errorCode = (jcu_detail_error_t)( (int_t) code + E_CATEGORY_JCU_JCDERR );
+        }
+    } /* end if */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetEncodedSize]
+* @brief         GetEncodedSize
+* @param[out]    out_Size
+* @retval        None
+******************************************************************************/
+void JCU_GetEncodedSize(
+    size_t *const out_Size)
+{
+    if (out_Size != NULL) {
+        /* ->QAC 0306 */
+        *out_Size = (((uint32_t)JCU.JCDTCU.BYTE) << SHIFT_16BITS);
+        *out_Size |= (((uint32_t)JCU.JCDTCM.BYTE) << SHIFT_8BITS);
+        *out_Size |= ((uint32_t)JCU.JCDTCD.BYTE);
+        /* <-QAC 0306 */
+    } /* end if */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInterrupting]
+* @brief         Operations on interrupting
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource )
+{
+    errnum_t  e;
+    uint32_t  flags0;
+    uint32_t  flags1;
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    R_UNREFERENCED_VARIABLE( InterruptSource );
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    ASSERT_R( self->AsyncStatus.Status == JCU_STATUS_INTERRUPTING,  e=E_STATE; goto fin );
+
+    /* Get interrupt status */
+    /* ->QAC 0306 */
+    flags0 = JCU.JINTS0.BYTE;
+    flags1 = JCU.JINTS1.LONG;
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptFlags, flags0 );
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptFlags, flags1 << JCU_SHIFT_JINTS1 );
+
+    /* Clear interrupt status "JINTS0" */
+    if ( flags0 != 0u ) {
+        R_SET_REG_BIT_FIELD( JCU.JCCMD.BYTE, JEND, 1u );
+        JCU.JINTS0.BYTE = (uint8_t) 0u;  /* Write 0 only */
+    }
+
+    /* Clear interrupt status "JINTS1" */
+    JCU.JINTS1.LONG = ~flags1 & JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+
+    /* Set state */
+    self->AsyncStatus.Status = JCU_STATUS_INTERRUPTED;
+
+    e=0;
+fin:
+    return  e;
+}
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInterrupted]
+* @brief         Bottom half operations on interrupting
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterrupted(void)
+{
+    bit_flags32_t const  sub_status_bits =
+        ( INS3_MASK ) |
+        ( JINF_MASK   << JCU_SHIFT_JINTS1 ) |
+        ( DOUTLF_MASK << JCU_SHIFT_JINTS1 ) |
+        ( DINLF_MASK  << JCU_SHIFT_JINTS1 ) |
+        ( JOUTF_MASK  << JCU_SHIFT_JINTS1 );
+
+    errnum_t         e;
+    uint32_t         cancel_flag;
+    uint32_t         interrupt_flags;
+    bool_t           was_enabled = false;
+    bool_t           is_end;
+    bool_t           or;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t  *notify_async_1 = NULL;
+    r_ospl_async_t  *notify_async_2 = NULL;
+    jcu_i_lock_t *const                i_lock = R_JCU_GetILockObject();
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+    ASSERT_R( self->AsyncStatus.Status != JCU_STATUS_UNDEF,  e=E_STATE; goto fin );
+
+    interrupt_flags = R_OSPL_FLAG32_GetAndClear( &self->AsyncStatus.InterruptFlags );
+
+
+    if ( IS_ANY_BITS_SET( interrupt_flags, sub_status_bits ) ) {
+        if ( IS_BIT_NOT_SET( interrupt_flags, INS6_MASK ) ) {
+            self->AsyncStatus.IsPaused = true;
+            self->AsyncStatus.SubStatusFlags = interrupt_flags & sub_status_bits;
+        }
+    }
+
+
+    if ( IS_ANY_BITS_SET( interrupt_flags, INS6_MASK ) ) {
+        is_end = true;
+    } else {
+        is_end = false;
+    }
+
+
+    or = ( (is_end) || (self->AsyncStatus.IsPaused) );
+    if (!or) {
+        or = IS_BIT_SET( interrupt_flags, INS5_MASK );
+    }
+    if (IS( or )) {
+        /* Set "AsyncStatus" */
+        R_OSPL_FLAG32_Clear( &self->AsyncStatus.InterruptEnables, JCU_INTERRUPT_LINE_ALL );
+        self->AsyncStatus.Status = JCU_STATUS_READY;
+        notify_async_1 = self->InterruptCallbackCaller.Async;
+    } else {
+        self->AsyncStatus.Status = JCU_STATUS_RUN;
+    }
+
+
+    IF ( IS_BIT_SET( interrupt_flags, INS5_MASK ) ) {
+        jcu_detail_error_t  ed;
+
+        JCU_GetRegisterForGetErrorInfo( &ed );
+        e = ed;
+        goto fin;
+    }
+
+
+    if ( notify_async_1 != NULL ) {
+        cancel_flag = R_OSPL_FLAG32_Get( &self->AsyncStatus.CancelFlags );
+        if ( IS_BIT_SET( cancel_flag, R_OSPL_FINALIZE_REQUEST ) ) {
+            notify_async_2 = self->AsyncForFinalize;
+            ej= R_JCU_TerminateStep2();
+            IF ( ej != JCU_ERROR_OK ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+    e=0;
+fin:
+    if ( IS( was_enabled ) ) {
+        /* ->QAC 3353 : "self" is always assigned, if "was_enabled" is true */
+        IF_DQ( self == NULL ) {}  /* QAC 3353 raises SEC R3.2.2 */
+        else {
+            self->I_LockVTable->Unlock( self->I_Lock );
+
+            if ( IS( self->Is_I_LockMaster ) ) {
+                IF_DQ( i_lock == NULL ) {}
+                else {
+                    if ( IS( i_lock->IsRequestedFinalize ) ) {
+                        R_JCU_I_LOCK_Finalize();
+                    }
+                }
+            }
+        }
+        /* <-QAC 3353 */
+    }
+
+    if ( notify_async_1 != NULL ) {
+        R_OSPL_EVENT_Set( notify_async_1->A_Thread, notify_async_1->A_EventValue );
+    }
+    if ( notify_async_2 != NULL ) {
+        R_OSPL_EVENT_Set( notify_async_2->A_Thread, notify_async_2->A_EventValue );
+    }
+
+    return  e;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/jcu_driver/converter_wrapper.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,197 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         converter_wrapper.c
+* @version      1.00
+* $Rev: 1 $
+* $Date:: 2015-08-06 16:33:52 +0900#$
+* @brief        Graphics driver wrapper function definitions in C
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "converter_wrapper.h"
+#include  "r_ospl.h"
+#include  "r_jcu_api.h"
+#include  "r_jcu_pl.h"
+
+static mbed_CallbackFunc_t*     SetCallback;
+static size_t*                  pEncodeSize;
+static int32_t                  EncodeCount;
+static int32_t                  EncodeCountMax;
+static size_t                   DecodeWidth;
+static size_t                   DecodeHeight;
+static r_ospl_async_t           Async;
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Set callback function address for decode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   width            Decode data width
+ * @param[in]   height           Decode data height
+ * @retval      error code
+******************************************************************************/
+errnum_t    R_wrpper_set_decode_callback(mbed_CallbackFunc_t* pSetCallbackAdr, size_t width, size_t height)
+{
+    errnum_t    e;
+
+    Async.Flags             = R_F_OSPL_InterruptCallback;
+    Async.A_Thread          = R_OSPL_THREAD_GetCurrentId();
+    Async.InterruptCallback = &R_wrpper_LocalDecodeCallback;
+    SetCallback             = pSetCallbackAdr;
+    DecodeWidth             = width;
+    DecodeHeight            = height;
+
+    e = R_JCU_StartAsync(&Async);
+
+    return e;
+}
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_LocalDecodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller)
+{
+    errnum_t                  e = 0;
+    const jcu_async_status_t* status;
+    jcu_image_info_t          image_info;
+    jcu_errorcode_t           jcu_error;
+
+    e = R_JCU_OnInterruptDefault(InterruptSource, Caller);
+    if (e != 0) {
+        SetCallback(MBED_JCU_E_JCU_ERR);
+        goto fin;
+    }
+    R_JCU_GetAsyncStatus( &status );
+    if (status -> IsPaused == true) {
+        if ((status->SubStatusFlags & JCU_SUB_INFOMATION_READY) == 0) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_FORMA_ERR);
+            goto fin;
+        }
+        R_JCU_GetImageInfo( &image_info );
+        if ((image_info.width == 0u) || (image_info.height == 0u) || 
+            (image_info.width > DecodeWidth) || 
+            (image_info.height > DecodeHeight)) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_FORMA_ERR);
+            goto fin;
+        }
+        if ((image_info.encodedFormat != JCU_JPEG_YCbCr444) &&
+            (image_info.encodedFormat != JCU_JPEG_YCbCr422) &&
+            (image_info.encodedFormat != JCU_JPEG_YCbCr420) &&
+            (image_info.encodedFormat != JCU_JPEG_YCbCr411)) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_FORMA_ERR);
+            goto fin;
+        }
+        jcu_error = R_JCU_ContinueAsync(JCU_IMAGE_INFO, &Async);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_JCU_ERR);
+            goto fin;
+        }
+    } else {
+        SetCallback(MBED_JCU_E_OK);
+    }
+
+fin:
+    return  e;
+
+}
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   pSize            Encode size input address
+ * @param[in]   count_max        Encode count max num
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_set_encode_callback( mbed_CallbackFunc_t* pSetCallbackAdr, size_t* pSize, int32_t count_max)
+{
+    errnum_t e;
+
+    Async.Flags             = R_F_OSPL_InterruptCallback;
+    Async.A_Thread          = R_OSPL_THREAD_GetCurrentId();
+    Async.InterruptCallback = &R_wrpper_LocalEncodeCallback;
+    SetCallback             = pSetCallbackAdr;
+    pEncodeSize             = pSize;
+    *pEncodeSize            = 0;
+    EncodeCount             = 1;
+    EncodeCountMax          = count_max;
+
+    e = R_JCU_StartAsync(&Async);
+
+    return e;
+}
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t    R_wrpper_LocalEncodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller)
+{
+    errnum_t                  e = 0;
+    const jcu_async_status_t* status;
+    jcu_errorcode_t           jcu_error;
+
+    e = R_JCU_OnInterruptDefault(InterruptSource, Caller);
+    if (e != 0) {
+        SetCallback(MBED_JCU_E_JCU_ERR);
+        goto fin;
+    }
+    R_JCU_GetAsyncStatus(&status);
+    if (status -> IsPaused == true) {
+        if ((status->SubStatusFlags & JCU_SUB_ENCODE_OUTPUT_PAUSE) == 0) {
+            e = E_OTHERS;
+            goto fin;
+        }
+        if (EncodeCount >= EncodeCountMax) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_JCU_ERR);
+            goto fin;
+        }
+        EncodeCount++;
+        jcu_error = R_JCU_ContinueAsync(JCU_OUTPUT_BUFFER, &Async);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_JCU_ERR);
+            goto fin;
+        }
+    } else {
+        (void)R_JCU_GetEncodedSize(pEncodeSize);
+        SetCallback(MBED_JCU_E_OK);
+    }
+
+fin:
+    return  e;
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/jcu_driver/jcu_api.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1336 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_api.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver API
+******************************************************************************/
+/**
+* @file  jcu_api.c
+* @brief   JCU (JPEG hardware) driver API. Main Code.
+*
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+#include    "r_ospl.h"
+#include    "r_jcu_api.h"
+#include    "r_jcu_local.h"
+#include    "r_jcu_pl.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* Section: Internal Global */
+
+/** gs_jcu_internal_information */
+static jcu_internal_information_t  gs_jcu_internal_information;
+
+
+/** gs_jcu_i_lock */
+static jcu_i_lock_t  gs_jcu_i_lock;
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/***********************************************************************
+* Class: jcu_i_lock_t
+************************************************************************/
+static void    R_JCU_I_LOCK_Reset( jcu_i_lock_t *const  self );
+static bool_t  R_JCU_I_LOCK_Lock( void *const  self_ );
+static void    R_JCU_I_LOCK_Unlock( void *const  self_ );
+static void    R_JCU_I_LOCK_RequestFinalize( void *const  self_ );
+static int_fast32_t  R_JCU_I_LOCK_GetRootChannelNum( const void *const  self_ );
+
+
+/* Section: Global */
+/**
+* @brief   Initialize the driver
+*
+* @param   NullConfig (in) NULL
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Initialize( void *const  NullConfig )
+/* <-SEC M1.1.1 */
+{
+    errnum_t          e;
+    jcu_errorcode_t   returnValue;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    static const r_ospl_i_lock_vtable_t  gs_I_LockVTable = {
+        &( R_JCU_I_LOCK_Lock ),  /* MISRA 16.9 */
+        &( R_JCU_I_LOCK_Unlock ),
+        &( R_JCU_I_LOCK_RequestFinalize ),
+        &( R_JCU_I_LOCK_GetRootChannelNum )
+    };
+
+    R_UNREFERENCED_VARIABLE( NullConfig );
+    R_IT_WILL_BE_NOT_CONST( NullConfig );
+
+    if ( self->I_Lock == NULL ) {
+        jcu_i_lock_t *const  i_lock = &gs_jcu_i_lock;
+
+        self->Is_I_LockMaster = R_JCU_I_LOCK_Replace(
+                                    i_lock,  &gs_I_LockVTable );
+    }
+
+    if ( IS( self->Is_I_LockMaster ) ) {
+        R_JCU_I_LOCK_Reset( self->I_Lock );
+    }
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.InterruptFlags );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.InterruptEnables );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.CancelFlags );
+    self->AsyncStatus.IsEnabledInterrupt = false;
+
+    /* Error check */
+    if (self->AsyncStatus.Status != JCU_STATUS_UNDEF) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    /* Run the User-defined function if user set the function */
+    e= R_JCU_OnInitialize();
+    IF ( e != 0 ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    /* Initialize the variable */
+    self->AsyncStatus.IsPaused = false;
+    self->AsyncStatus.SubStatusFlags = 0;
+    self->IsCountMode = false;
+    self->ErrorFilter = JCU_INT_ERROR_ALL;
+    self->AsyncForFinalize = NULL;
+
+    /* Set the register */
+    returnValue = JCU_SetRegisterForInitialize();
+
+    if (returnValue == JCU_ERROR_OK) {
+        /* Set the updated status */
+        self->AsyncStatus.Status = JCU_STATUS_INIT;
+
+        /* Initialize the status for the encode */
+        self->Codec = JCU_CODEC_NOT_SELECTED;
+    } /* end if */
+
+fin:
+    return returnValue;
+}
+
+
+/**
+* @brief   Terminate the driver function
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Terminate(void)
+/* <-SEC M1.1.1 */
+{
+    errnum_t         e;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t   async;
+    bit_flags32_t    got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    ej= R_JCU_TerminateAsync( &async );
+    IF( ej != JCU_ERROR_OK ) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+fin:
+    return  ej;
+}
+
+
+/**
+* @brief   Terminate the driver function
+*
+* @param   async <r_ospl_async_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_TerminateAsync( r_ospl_async_t *const  async )
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue = JCU_ERROR_OK;
+    bool_t            was_enabled = false;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    IF_DQ( async == NULL ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    R_JCU_SetDefaultAsync( async, R_OSPL_ASYNC_TYPE_FINALIZE );
+    async->ReturnValue = 0;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+    /* Check the status */
+    if ( self->AsyncStatus.Status == JCU_STATUS_UNDEF ) {
+        returnValue = JCU_ERROR_OK;
+        goto fin;
+    } /* end if */
+
+    if ( self->AsyncStatus.Status == JCU_STATUS_RUN ) {
+        self->AsyncForFinalize = async;
+
+        R_OSPL_FLAG32_Set( &self->AsyncStatus.CancelFlags, R_OSPL_FINALIZE_REQUEST );
+
+        /* "R_JCU_OnInterrupted" will be called */
+    } else {
+        returnValue = R_JCU_TerminateStep2();
+        R_OSPL_EVENT_Set( async->A_Thread, async->A_EventValue );
+    } /* end if */
+
+fin:
+    /* Finalize I-Lock */
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+
+        if ( IS( self->Is_I_LockMaster ) ) {
+            if ( IS( gs_jcu_i_lock.IsRequestedFinalize ) ) {
+                R_JCU_I_LOCK_Finalize();
+            }
+        }
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Terminate the driver function
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t  R_JCU_TerminateStep2(void)
+{
+    errnum_t         ee;
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    R_AVOID_UNSAFE_ALWAYS_WARNING( returnValue );
+
+
+    /* Set the updated status */
+    R_OSPL_FLAG32_Clear( &self->AsyncStatus.CancelFlags, R_OSPL_FLAG32_ALL_BITS );
+    self->AsyncStatus.Status = JCU_STATUS_UNDEF;
+    self->I_LockVTable->RequestFinalize( self->I_Lock );
+
+
+    /* Run the additional function selected by parameter */
+    ee= R_JCU_OnFinalize( returnValue );
+    IF ( (ee != 0) && (returnValue == JCU_ERROR_OK) ) {
+        returnValue = JCU_ERROR_PARAM;
+    }
+
+    return  returnValue;
+}
+
+
+/**
+* @brief   Select Codec Type
+*
+* @param   codec <jcu_codec_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SelectCodec(
+    const jcu_codec_t codec)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled;  /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF ((self->AsyncStatus.Status == JCU_STATUS_UNDEF)
+        || (self->AsyncStatus.Status == JCU_STATUS_RUN)) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSelectCodec(codec);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    }
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Clear the count mode flag */
+    self->IsCountMode = false;
+
+    /* Register set */
+    JCU_SetRegisterForCodec(codec);
+
+    /* Set the updated status */
+    self->AsyncStatus.Status = JCU_STATUS_SELECTED;
+
+    /* Set codec type to internal information variable */
+    switch (codec) {
+        case JCU_ENCODE:
+            self->Codec = JCU_STATUS_ENCODE;
+            break;
+        case JCU_DECODE:
+            self->Codec = JCU_STATUS_DECODE;
+            break;
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Start decoding or encoding. Synchronized.
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Start(
+    void)
+/* <-SEC M1.1.1 */
+{
+    errnum_t         e;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t   async;
+    bit_flags32_t    got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    ej= R_JCU_StartAsync( &async );
+    IF( ej != JCU_ERROR_OK ) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        ej=e;
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        ej=e;
+        goto fin;
+    }
+
+fin:
+    return  ej;
+}
+
+
+/**
+* @brief   Start decoding or encoding. Asynchronized.
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_StartAsync(
+    r_ospl_async_t *const  async)
+/* <-SEC M1.1.1 */
+{
+    errnum_t          e;
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (self->AsyncStatus.Status != JCU_STATUS_READY) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckStart();
+    IF(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+
+    IF ( async == NULL ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    R_JCU_SetDefaultAsync( async, R_OSPL_ASYNC_TYPE_NORMAL );
+    async->ReturnValue = 0;
+
+    /* Attach "Async" to interrupt */
+    /* ->MISRA 11.4 : Not too big "enum" is same bit count as "int" */ /* ->SEC R2.7.1 */
+    R_OSPL_CALLER_Initialize( &self->InterruptCallbackCaller,
+                              async, (int_fast32_t *)&self->AsyncStatus.Status, JCU_STATUS_INTERRUPTING,
+                              self->I_Lock, self->I_LockVTable );
+    /* <-MISRA 11.4 */ /* <-SEC R2.7.1 */
+    e= R_JCU_SetInterruptCallbackCaller( &self->InterruptCallbackCaller );
+    IF ( e != 0 ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptEnables, JCU_INTERRUPT_LINE_ALL );
+
+    /* Clear event flags */
+    R_OSPL_EVENT_Clear( async->A_Thread, async->A_EventValue );
+    R_OSPL_EVENT_Clear( async->I_Thread, async->I_EventValue );
+
+    /* Set the updated status when register update is finished */
+    /* Change the status */
+    self->AsyncStatus.Status = JCU_STATUS_RUN;
+
+    /* Register set */
+    JCU_SetRegisterForStart( self->ErrorFilter );
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Set the count mode (separate operating) parameter
+*
+* @param   buffer <jcu_count_mode_param_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetCountMode(
+    const jcu_count_mode_param_t  *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_SELECTED)
+          || (self->AsyncStatus.Status == JCU_STATUS_READY))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF(buffer == NULL) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetCountMode(buffer);
+    IF(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Set the count mode flag */
+    if ((buffer->inputBuffer.isEnable != false) || (buffer->outputBuffer.isEnable != false)) {
+        self->IsCountMode = true;
+    } else {
+        self->IsCountMode = false;
+    } /* end if */
+
+    /* Register set */
+    JCU_SetRegisterForSetCountMode(buffer);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Restart the processing caused by count mode. Synchronized.
+*
+* @param   type The target to continue
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Continue(
+    const jcu_continue_type_t  type)
+/* <-SEC M1.1.1 */
+{
+    errnum_t         e;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t   async;
+    bit_flags32_t    got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    ej= R_JCU_ContinueAsync( type, &async );
+    IF( ej != JCU_ERROR_OK ) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+fin:
+    return  ej;
+}
+
+
+/**
+* @brief   Restart the processing caused by count mode. Asynchronized.
+*
+* @param   type The target to continue
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_ContinueAsync(
+    const jcu_continue_type_t  type,
+    r_ospl_async_t *const  async)
+/* <-SEC M1.1.1 */
+{
+    errnum_t          e;
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    bit_flags32_t     mask;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (self->AsyncStatus.Status != JCU_STATUS_READY) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->AsyncStatus.IsPaused == false) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    IF ( async == NULL ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Clear the sub status flag */
+    switch ( type ) {
+        case JCU_INPUT_BUFFER:
+            mask = ( ( JINF_MASK | DINLF_MASK ) << JCU_SHIFT_JINTS1 );
+            break;
+        case JCU_OUTPUT_BUFFER:
+            mask = ( ( DOUTLF_MASK | JOUTF_MASK ) << JCU_SHIFT_JINTS1 );
+            break;
+        default:
+            ASSERT_R( type == JCU_IMAGE_INFO, returnValue=E_OTHERS; goto fin );
+            mask = INS3_MASK;
+            break;
+    }
+    ASSERT_R( IS_ANY_BITS_SET( self->AsyncStatus.SubStatusFlags, mask ), returnValue=E_OTHERS; goto fin );
+    self->AsyncStatus.SubStatusFlags &= ~mask;
+
+
+    R_JCU_SetDefaultAsync( async, R_OSPL_ASYNC_TYPE_NORMAL );
+    async->ReturnValue = 0;
+
+    /* Clear event flags */
+    R_OSPL_EVENT_Clear( async->A_Thread, async->A_EventValue );
+    R_OSPL_EVENT_Clear( async->I_Thread, async->I_EventValue );
+
+    /* JCU will restart */
+    if( self->AsyncStatus.SubStatusFlags == 0 ) {
+        /* Attach "Async" to interrupt */
+        /* ->MISRA 11.4 : Not too big "enum" is same bit count as "int" */ /* ->SEC R2.7.1 */
+        R_OSPL_CALLER_Initialize( &self->InterruptCallbackCaller,
+                                  async, (int_fast32_t *)&self->AsyncStatus.Status, JCU_STATUS_INTERRUPTING,
+                                  self->I_Lock, self->I_LockVTable );
+        /* <-MISRA 11.4 */ /* <-SEC R2.7.1 */
+        e= R_JCU_SetInterruptCallbackCaller( &self->InterruptCallbackCaller );
+        IF ( e != 0 ) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        }
+        R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptEnables, JCU_INTERRUPT_LINE_ALL );
+
+        /* Change the status */
+        self->AsyncStatus.Status = JCU_STATUS_RUN;
+        self->AsyncStatus.IsPaused = false;
+
+        /* Register set */
+        JCU_SetRegisterForContinue( type );
+    }
+
+    /* JCU will not restart */
+    else {
+        /* Register set */
+        JCU_SetRegisterForContinue( type );
+
+        /* Change the status */
+        self->AsyncStatus.Status = JCU_STATUS_READY;
+
+        /* Set event flags */
+        R_OSPL_EVENT_Set( async->A_Thread, async->A_EventValue );
+        R_OSPL_EVENT_Set( async->I_Thread, async->I_EventValue );
+    }
+
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   R_JCU_GetAsyncStatus.
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void  R_JCU_GetAsyncStatus( const jcu_async_status_t **const  out_Status )
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    IF_DQ( out_Status == NULL ) {
+        goto fin;
+    }
+
+    *out_Status = &self->AsyncStatus;
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Set parameter for decode.
+*
+* @param   decode Select the encode parameter for decoding. <jcu_decode_param_t>
+* @param   buffer Buffer settings for decode. <jcu_buffer_param_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetDecodeParam(
+    const jcu_decode_param_t   *const decode,
+    const jcu_buffer_param_t   *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF(self->Codec != JCU_STATUS_DECODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF((decode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetDecodeParam(decode, buffer);
+    IF(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetDecodePrm(decode, buffer);
+
+    /* Set the updated status */
+    self->AsyncStatus.Status = JCU_STATUS_READY;
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Whether stop or not stop for R_JCU_GetImageInfo()
+*
+* @param   is_pause Whether stop or not stop
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t R_JCU_SetPauseForImageInfo( const bool_t is_pause )
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF(self->Codec != JCU_STATUS_DECODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetPause( is_pause, self->ErrorFilter );
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   GetImageInfo
+*
+* @param   buffer Image information. <jcu_image_info_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_GetImageInfo(
+    jcu_image_info_t   *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (self->AsyncStatus.Status != JCU_STATUS_READY) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_DECODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (buffer == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckGetImageInfo(buffer);
+    if(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_GetRegisterForGetImageInfo(buffer);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   SetErrorFilter
+*
+* @param   filter enable bit of error. <jcu_int_detail_errors_t>
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t R_JCU_SetErrorFilter(jcu_int_detail_errors_t filter)
+{
+    jcu_errorcode_t   returnValue;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_INIT)
+          || (self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    IF ( IS_ANY_BITS_SET( filter, ~JCU_INT_ERROR_ALL ) ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    self->ErrorFilter = filter;
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    return returnValue;
+}
+
+
+/**
+* @brief   SetQuantizationTable
+*
+* @param   tableNo The table number to set the value. <jcu_table_no_t>
+* @param   table The body of the table to set.
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetQuantizationTable(
+    const jcu_table_no_t   tableNo,
+    const uint8_t         *const table)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_ENCODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (table == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetQuantizationTbl(tableNo);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetQtTable(tableNo, table);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Set the Huffman table
+*
+* @param   tableNo The table number to set the value. <jcu_table_no_t>
+* @param   type The type of Huffman table type (AC or DC). <jcu_huff_t>
+* @param   table The body of the table to set
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetHuffmanTable(
+    const jcu_table_no_t   tableNo,
+    const jcu_huff_t       type,
+    const uint8_t         *const table)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_ENCODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (table == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetHuffmanTable(tableNo, type);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetHuffTbl(tableNo, type, table);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Set the parameter fo encoding
+*
+* @param   encode Select the encode parameter for encoding. <jcu_encode_param_t>
+* @param   buffer Select the buffer settings for encoding. <jcu_buffer_param_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetEncodeParam(
+    const jcu_encode_param_t   *const encode,
+    const jcu_buffer_param_t   *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_ENCODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF ((encode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckEncodeParam(encode, buffer);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetEncodePrm(encode, buffer);
+
+    /* Set the updated status */
+    self->AsyncStatus.Status = JCU_STATUS_READY;
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   GetEncodedSize
+*
+* @param   out_Size EncodedSize
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_GetEncodedSize(
+    size_t *const out_Size)
+/* <-SEC M1.1.1 */
+{
+    JCU_GetEncodedSize(out_Size);
+    return  JCU_ERROR_OK;
+}
+
+
+/**
+* @brief   Set AXI bus A*CACHE bits for 2nd cache to JCU.
+*
+* @param   read_cache_attribute <r_ospl_axi_cache_attribute_t>
+* @param   write_cache_attribute <r_ospl_axi_cache_attribute_t>
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t  R_JCU_Set2ndCacheAttribute(
+    r_ospl_axi_cache_attribute_t const  read_cache_attribute,
+    r_ospl_axi_cache_attribute_t const  write_cache_attribute )
+{
+    static const uint32_t  mask_JCU = 0xFFFF0000u;
+    jcu_errorcode_t    returnValue;
+    uint32_t           new_value;
+    volatile uint32_t  value;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+
+    new_value = ( read_cache_attribute << 24 ) | ( write_cache_attribute << 16 );
+
+    R_OSPL_DisableAllInterrupt();
+
+#if defined(TARGET_RZ_A1XX)
+    value = INB.AXIBUSCTL0;
+    value = new_value | ( value & ~mask_JCU );  /* Mutual Exclusion from Ether */
+    INB.AXIBUSCTL0 = value;
+#elif defined(TARGET_RZ_A2XX)
+    value = PRR.AXIBUSCTL0.LONG;
+    value = new_value | ( value & ~mask_JCU );  /* Mutual Exclusion from Ether */
+    PRR.AXIBUSCTL0.LONG = value;
+#endif
+
+    returnValue = JCU_ERROR_OK;
+    R_OSPL_EnableAllInterrupt();
+fin:
+
+    return  returnValue;
+}
+
+
+/**
+* @brief   EnableInterrupt
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void  R_JCU_EnableInterrupt(void)
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    self->AsyncStatus.IsEnabledInterrupt = true;
+    R_JCU_OnEnableInterrupt( self->AsyncStatus.InterruptEnables.Flags );
+}
+
+
+/**
+* @brief   DisableInterrupt
+*
+* @par Parameters
+*    None
+* @return  Was interrupt enabled
+*/
+bool_t  R_JCU_DisableInterrupt(void)
+{
+    bool_t    was_interrupted;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_interrupted = self->AsyncStatus.IsEnabledInterrupt;
+
+    R_JCU_OnDisableInterrupt( self->AsyncStatus.InterruptEnables.Flags );
+    self->AsyncStatus.IsEnabledInterrupt = false;
+
+    return  was_interrupted;
+}
+
+
+/**
+* @brief   R_JCU_GetInternalInformation
+*
+* @par Parameters
+*    None
+* @return  <jcu_internal_information_t> type.
+*/
+jcu_internal_information_t  *R_JCU_GetInternalInformation(void)
+{
+    return  &gs_jcu_internal_information;
+}
+
+
+/**
+* @brief   R_JCU_GetILockObject
+*
+* @par Parameters
+*    None
+* @return  <jcu_i_lock_t> type.
+*/
+jcu_i_lock_t  *R_JCU_GetILockObject(void)
+{
+    return  &gs_jcu_i_lock;
+}
+
+
+/**
+* @brief   Replace associated I-Lock object
+*
+* @param   I_Lock I-Lock object
+* @param   I_LockVTable V-Table
+* @return  Whether success to replace
+*/
+bool_t  R_JCU_I_LOCK_Replace( void *const  I_Lock,  const r_ospl_i_lock_vtable_t *const  I_LockVTable )
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+    bool_t  ret = false;
+
+    ASSERT_R( self->AsyncStatus.Status == JCU_STATUS_UNDEF,  ret = false; goto fin );
+
+    if ( I_Lock != NULL ) {
+        if ( self->I_Lock == NULL ) {
+            self->I_Lock = I_Lock;
+            self->I_LockVTable = I_LockVTable;
+            ret = true;
+        }
+    } else {
+        self->I_Lock = NULL;
+    }
+
+fin:
+    return  ret;
+}
+
+
+/**
+* @brief   Finalize the I-Lock object
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void  R_JCU_I_LOCK_Finalize(void)
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+    bool_t  b;
+
+    ASSERT_D( self->Is_I_LockMaster, R_NOOP() );
+
+    R_JCU_I_LOCK_Reset( self->I_Lock );
+    b= R_JCU_I_LOCK_Replace( NULL, NULL );
+    R_UNREFERENCED_VARIABLE( b );  /* QAC 3200 : This is not error information */
+    self->Is_I_LockMaster = false;
+}
+
+
+/**
+* @brief   Reset the I-Lock object
+*
+* @param   self I-Lock object
+* @return  None
+*/
+static void   R_JCU_I_LOCK_Reset( jcu_i_lock_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->IsLock = false;
+    R_JCU_OnDisableInterrupt( JCU_INTERRUPT_LINE_ALL );
+    JCU_ClearInterruptFlag();
+    self->IsRequestedFinalize = false;
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Lock the I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  Was interrupt enabled
+*/
+static bool_t  R_JCU_I_LOCK_Lock( void *const  self_ )
+{
+    bool_t  is_locked;
+    bool_t  b;
+    jcu_i_lock_t *const  self = (jcu_i_lock_t *) self_;
+
+    IF_DQ( self == NULL ) {
+        is_locked = true;
+        goto fin;
+    }
+
+    R_OSPL_DisableAllInterrupt();
+
+    is_locked = self->IsLock;
+    if ( ! is_locked ) {
+        b= R_JCU_DisableInterrupt();
+        R_UNREFERENCED_VARIABLE( b );  /* QAC 3200 : This is not error information */
+        self->IsLock = true;
+    }
+
+    R_OSPL_EnableAllInterrupt();
+
+fin:
+    return  ! is_locked;
+}
+
+
+/**
+* @brief   Unlock the I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  None
+*/
+static void  R_JCU_I_LOCK_Unlock( void *const  self_ )
+{
+    jcu_i_lock_t *const  self = (jcu_i_lock_t *) self_;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    R_OSPL_DisableAllInterrupt();
+
+    R_JCU_EnableInterrupt();
+    self->IsLock = false;
+
+    R_OSPL_EnableAllInterrupt();
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Request to finalize the I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  None
+*/
+static void   R_JCU_I_LOCK_RequestFinalize( void *const  self_ )
+{
+    jcu_i_lock_t *const  self = (jcu_i_lock_t *) self_;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->IsRequestedFinalize = true;
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Get root channel number of I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  A channel number
+*/
+static int_fast32_t  R_JCU_I_LOCK_GetRootChannelNum( const void *const  self_ )
+{
+    R_UNREFERENCED_VARIABLE( self_ );
+
+    return  0;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/jcu_driver/jcu_para.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,360 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_para.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+* Description : JCU driver checking parameter
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+#include    "r_typedefs.h"
+#include    "r_ospl.h"
+#include    "r_jcu_api.h"
+#include    "r_jcu_local.h"
+#include    "r_jcu_user.h"
+#include    "iodefine.h"
+
+#ifdef      JCU_PARAMETER_CHECK
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define MASK_LOW_3BIT   (0x7u)
+#define MOD_8           (0x8u)
+#define MOD_16          (0x10u)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSelectCodec]
+ * @brief       SelectCodec api's parameter checking
+ * @param       [in] codec  codec type
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSelectCodec(
+    const jcu_codec_t   codec)
+{
+    jcu_errorcode_t  returnValue;
+
+    IF_DS ((codec != JCU_ENCODE)
+           && (codec != JCU_DECODE)) {
+        returnValue = JCU_ERROR_PARAM;
+    }
+    else {
+        returnValue = JCU_ERROR_OK;
+    } /* end if */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckStart]
+ * @brief       Start api's parameter checking
+ * @param       [in] codec  codec type
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckStart(
+    void)
+{
+    jcu_errorcode_t   returnValue;
+
+    /* If jcu already start, it cannot update this bit (this is limitation of hardware) */
+#if defined(TARGET_RZ_A1XX)
+    IF ( (uint32_t)R_GET_REG_BIT_FIELD( JCU.JCCMD, JSRT ) == REG_F_SET ) {
+#elif defined(TARGET_RZ_A2XX)
+    IF ( (uint32_t)R_GET_REG_BIT_FIELD( JCU.JCCMD.BYTE, JSRT ) == REG_F_SET ) {
+#endif
+        returnValue = JCU_ERROR_STATUS;
+    }
+    else {
+        returnValue = JCU_ERROR_OK;
+    } /* end if */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetCountMode]
+ * @brief       parameter check for the SetCountMode
+ * @param       [in] buffer the parameter for the Count Mode
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetCountMode(
+    const jcu_count_mode_param_t  *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF (buffer == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    IF ((buffer->inputBuffer.isEnable != false) && (buffer->outputBuffer.isEnable != false)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    if (buffer->inputBuffer.isEnable != false) {
+        /* When initAddress is true, restartAddress has to set the address */
+        if (buffer->inputBuffer.isInitAddress != false) {
+            IF (buffer->inputBuffer.restartAddress == NULL) {
+                returnValue = JCU_ERROR_PARAM;
+                goto fin;
+            } /* end if */
+        } /* end if */
+
+        /* Datasize(JDATAS/LINES bit) have to 8byte alignment */
+        IF ((buffer->inputBuffer.dataCount & MASK_LOW_3BIT) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+        /* Datasize have to bigger than 0 */
+        IF (buffer->inputBuffer.dataCount == 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+    } /* end if */
+
+    if (buffer->outputBuffer.isEnable != false) {
+        /* When initAddress is true, restartAddress has to set the address */
+        if (buffer->outputBuffer.isInitAddress != false) {
+            IF (buffer->outputBuffer.restartAddress == NULL) {
+                returnValue = JCU_ERROR_PARAM;
+                goto fin;
+            } /* end if */
+        } /* end if */
+
+        /* Datasize(JDATAS/LINES bit) have to 8byte alignment */
+        IF ((buffer->outputBuffer.dataCount & MASK_LOW_3BIT) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+        /* Datasize have to bigger than 0 */
+        IF (buffer->outputBuffer.dataCount == 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+    } /* end if */
+fin:
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetDecodeParam]
+ * @brief       SetDecodeParam api's parameter checking
+ * @param       [in] buffer         input and output buffer settings
+ * @param       [in] interruptKind  tye type of interrupt that use in this system
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetDecodeParam(
+    const jcu_decode_param_t   *const decode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF ((decode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    /* NULL check for the address data */
+    IF ((buffer->source.address == NULL)
+        || (buffer->destination.address == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }  /* end if */
+
+    /* Check for the address alignment */
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    IF ((((uint32_t) (buffer->source.address) % MOD_8) != 0u) ||
+        (((uint32_t) (buffer->destination.address) % MOD_8) != 0u))
+    /* <-MISRA 11.3 */ { /* <-SEC R2.7.1 */
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }  /* end if */
+
+    /*Check for Cb/Cr offset */
+    if(decode->decodeFormat == JCU_OUTPUT_YCbCr422) {
+        IF (((decode->outputCbCrOffset) != JCU_CBCR_OFFSET_0) && ((decode->outputCbCrOffset) != JCU_CBCR_OFFSET_128)) {
+            returnValue = JCU_ERROR_PARAM;
+        }  /* end if */
+    } else {
+        IF ((decode->outputCbCrOffset) != JCU_CBCR_OFFSET_0) {
+            returnValue = JCU_ERROR_PARAM;
+        }  /* end if */
+    } /* end if */
+fin:
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckGetImageInfo]
+ * @brief       GetImageInfo api's parameter checking
+ * @param       [in] buffer         buffer address that set the image information
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckGetImageInfo(
+    const jcu_image_info_t   *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF (buffer == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+    } /* end if */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetQuantizationTbl]
+ * @brief       SetQuantizationTable api's parameter checking
+ * @param       [in] tableNo        the table number that set the parameter
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetQuantizationTbl(
+    const jcu_table_no_t   tableNo)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    /* ->MISRA 13.7 : For fail safe. */
+    IF_DS (tableNo > JCU_TABLE_NO_3)
+    /* <-MISRA 13.7 */
+    /* ->MISRA 14.1 ->QAC 3201 : For fail safe. */
+    {
+        returnValue = JCU_ERROR_PARAM;
+    } /* end if */
+    /* <-MISRA 14.1 <-QAC 3201 */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetHuffmanTable]
+ * @brief       SetHuffmanTable api's parameter checking
+ * @param       [in] tableNo        the table number that set the parameter
+ * @param       [in] type        the type which table is set(AC or DC)
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetHuffmanTable(
+    const jcu_table_no_t   tableNo,
+    const jcu_huff_t       type)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    /* ->MISRA 13.7 : For fail safe. */
+    IF (tableNo > JCU_TABLE_NO_1)
+    /* <-MISRA 13.7 */
+    {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    /* ->MISRA 13.7 : For fail safe. */
+    IF_DS ((type != JCU_HUFFMAN_AC)
+           && (type != JCU_HUFFMAN_DC))
+    /* <-MISRA 13.7 */
+    /* ->MISRA 14.1 ->QAC 3201 : For fail safe. */
+    {
+        returnValue = JCU_ERROR_PARAM;
+    } /* end if */
+    /* <-MISRA 14.1 <-QAC 3201 */
+fin:
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckEncodeParam]
+ * @brief        api's parameter checking
+ * @param       [in]
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckEncodeParam(
+    const jcu_encode_param_t   *const encode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF ((encode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    /* NULL check for the address data */
+    IF ((buffer->source.address == NULL)
+        || (buffer->destination.address == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }  /* end if */
+
+
+    if (encode->encodeFormat == JCU_JPEG_YCbCr422) {
+        /* Check the width of the image data */
+        IF ((encode->width % MOD_16) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+        /* Check the height of the image data */
+        IF ((encode->height % MOD_8) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+    } else {
+        returnValue = JCU_ERROR_PARAM;
+        ASSERT_D( false, R_NOOP() );
+        goto fin;
+    } /* end if */
+
+    /*Check for Cb/Cr offset */
+    IF (((encode->inputCbCrOffset) != JCU_CBCR_OFFSET_0) && ((encode->inputCbCrOffset) != JCU_CBCR_OFFSET_128)) {
+        returnValue = JCU_ERROR_PARAM;
+    }  /* end if */
+
+fin:
+    return (returnValue);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/porting/jcu_pl.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,341 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_pl.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver porting layer
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "iodefine.h"
+#include  "r_jcu_api.h"
+#include  "r_jcu_pl.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct st_jcu_pl_t  jcu_pl_t;
+
+/*[jcu_pl_t]*/
+struct st_jcu_pl_t {
+    const r_ospl_caller_t     *InterruptCallbackCaller;
+    const jcu_async_status_t  *Status;
+};
+
+/*[gs_jcu_pl]*/
+static jcu_pl_t  gs_jcu_pl
+;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+enum { JCU_INT_PRI = 2 };
+#define  CPG_JCU_CLOCK_POWER_OFF  0x00000002u
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void  JCU_IRQ_JEDI_Handler(void);
+static void  JCU_IRQ_JDTI_Handler(void);
+
+/*[gs_jedi_interrupt_context] JEDI interrupt context */
+/*[gs_jdti_interrupt_context] JDTI interrupt context */
+static const r_ospl_interrupt_t  gs_jedi_interrupt_context = { BSP_INT_SRC_JEDI, 0 };
+static const r_ospl_interrupt_t  gs_jdti_interrupt_context = { BSP_INT_SRC_JDTI, 0 };
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_SetDefaultAsync]
+* @retval        None
+******************************************************************************/
+void  R_JCU_SetDefaultAsync( r_ospl_async_t *const  Async,  r_ospl_async_type_t AsyncType )
+{
+    IF_DQ( Async == NULL ) {
+        goto fin;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_Thread ) ) {
+        Async->A_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_EventValue ) ) {
+        if ( AsyncType == R_OSPL_ASYNC_TYPE_NORMAL ) {
+            Async->A_EventValue = R_OSPL_A_FLAG;
+        } else {
+            Async->A_EventValue = R_OSPL_FINAL_A_FLAG;
+        }
+    } else {
+        ASSERT_D( IS_BIT_SET( Async->Flags, R_F_OSPL_A_Thread ), R_NOOP() );
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_Thread ) ) {
+        Async->I_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_EventValue ) ) {
+        Async->I_EventValue = R_OSPL_I_FLAG;
+    } else {
+        ASSERT_D( IS_BIT_SET( Async->Flags, R_F_OSPL_I_Thread ), R_NOOP() );
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_InterruptCallback ) ) {
+        Async->InterruptCallback = &( R_JCU_OnInterruptDefault );    /* MISRA 16.9 */
+    }
+
+    Async->Flags = R_F_OSPL_A_Thread | R_F_OSPL_A_EventValue |
+                   R_F_OSPL_I_Thread | R_F_OSPL_I_EventValue |
+                   R_F_OSPL_InterruptCallback | R_F_OSPL_Delegate;
+fin:
+    return;
+}
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInitialize]
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInitialize(void)
+{
+    errnum_t         e;
+    bsp_int_err_t    eb;
+    bsp_int_src_t const  num_of_JEDI_IRQ = gs_jedi_interrupt_context.IRQ_Num;
+    bsp_int_src_t const  num_of_JDTI_IRQ = gs_jdti_interrupt_context.IRQ_Num;
+    jcu_pl_t *const  self = &gs_jcu_pl;
+
+    self->InterruptCallbackCaller = NULL;
+    self->Status = NULL;
+
+
+    /* Register "JEDI" */
+    eb= R_BSP_InterruptWrite( num_of_JEDI_IRQ, &( JCU_IRQ_JEDI_Handler ) );  /* MISRA 16.9 */
+    IF ( eb != 0 ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_OSPL_SetInterruptPriority( num_of_JEDI_IRQ, JCU_INT_PRI );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+
+    /* Register "JDTI" */
+    eb= R_BSP_InterruptWrite( num_of_JDTI_IRQ, &( JCU_IRQ_JDTI_Handler ) );  /* MISRA 16.9 */
+    IF ( eb != 0 ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_OSPL_SetInterruptPriority( num_of_JDTI_IRQ, JCU_INT_PRI );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+
+    /* start to suuply the clock for JCU */
+    { /* ->QAC 0306 */
+#if defined(TARGET_RZ_A1XX)
+        uint32_t cpg_reg;
+        cpg_reg = (uint32_t)(CPG.STBCR6) & ~CPG_JCU_CLOCK_POWER_OFF;
+        CPG.STBCR6 =(uint8_t)cpg_reg;
+#elif defined(TARGET_RZ_A2XX)
+        CPG.STBCR5.BIT.MSTP51 = 0;
+#endif
+    } /* <-QAC 0306 */
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnFinalize]
+* @retval        Error code, 0=No error and e=0
+******************************************************************************/
+/* ->QAC 3227 : "e" is usually changed in finalize function. */
+errnum_t  R_JCU_OnFinalize( errnum_t e )
+/* <-QAC 3227 */
+{
+    /* stop to suuply the clock for JCU */
+    { /* ->QAC 0306 */
+#if defined(TARGET_RZ_A1XX)
+        uint32_t cpg_reg;
+        cpg_reg = (uint32_t)(CPG.STBCR6) | CPG_JCU_CLOCK_POWER_OFF;
+        CPG.STBCR6 = (uint8_t)cpg_reg;
+#elif defined(TARGET_RZ_A2XX)
+        CPG.STBCR5.BIT.MSTP51 = 1;
+#endif
+    } /* <-QAC 0306 */
+
+    return  e;
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_SetInterruptCallbackCaller]
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_SetInterruptCallbackCaller( const r_ospl_caller_t *const  Caller )
+{
+    jcu_pl_t *const  self = &gs_jcu_pl;
+
+    self->InterruptCallbackCaller = Caller;
+
+    return  0;
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_OnEnableInterrupt]
+* @retval        None
+******************************************************************************/
+void  R_JCU_OnEnableInterrupt( jcu_interrupt_lines_t const  Enables )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Enables, JCU_INTERRUPT_LINE_JEDI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jedi_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+
+    if ( IS_BIT_SET( Enables, JCU_INTERRUPT_LINE_JDTI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jdti_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_OnDisableInterrupt]
+* @retval        None
+******************************************************************************/
+void  R_JCU_OnDisableInterrupt( jcu_interrupt_lines_t const  Disables1 )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Disables1, JCU_INTERRUPT_LINE_JEDI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jedi_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+
+    if ( IS_BIT_SET( Disables1, JCU_INTERRUPT_LINE_JDTI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jdti_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_OnInterruptDefault]
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                    const r_ospl_caller_t *const  Caller )
+{
+    errnum_t  e;
+    errnum_t  ee;
+    r_ospl_async_t  *async;
+
+    e = 0;
+    R_AVOID_UNSAFE_ALWAYS_WARNING( e );
+
+    IF_DQ( Caller == NULL ) {
+        goto fin;
+    }
+
+    ee= R_JCU_OnInterrupting( InterruptSource );
+    IF ( (ee != 0) && (e == 0) ) {
+        e = ee;
+    }
+
+    async = Caller->Async;
+
+    if ( async->I_Thread == NULL ) {
+        ee= R_JCU_OnInterrupted();
+        IF ( (ee != 0) && (e == 0) ) {
+            e = ee;
+        }
+    } else {
+        R_OSPL_EVENT_Set( async->I_Thread, async->I_EventValue );
+    }
+
+fin:
+    return  e;
+}
+
+
+/**************************************************************************//**
+* Function Name: [JCU_IRQ_JEDI_Handler]
+* @brief         JEDI (JCU Encode Decode Interrupt) interrupt handler
+* @retval        None
+******************************************************************************/
+static void  JCU_IRQ_JEDI_Handler(void)
+{
+    jcu_pl_t *const                  self = &gs_jcu_pl;
+    const r_ospl_interrupt_t *const  i_context = &gs_jedi_interrupt_context;
+
+    R_OSPL_CallInterruptCallback( self->InterruptCallbackCaller, i_context );
+}
+
+
+/**************************************************************************//**
+* Function Name: [JCU_IRQ_JDTI_Handler]
+* @brief         JDTI (JCU Data Transfer Interrupt) interrupt handler
+* @retval        None
+******************************************************************************/
+static void  JCU_IRQ_JDTI_Handler(void)
+{
+    jcu_pl_t *const                  self = &gs_jcu_pl;
+    const r_ospl_interrupt_t *const  i_context = &gs_jdti_interrupt_context;
+
+    R_OSPL_CallInterruptCallback( self->InterruptCallbackCaller, i_context );
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/jcu/userdef/jcu_user.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,118 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_user.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver porting layer
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "iodefine.h"
+#include  "r_jcu_api.h"
+#ifndef R_OSPL_NDEBUG
+#include  <stdio.h>
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_PrintRegisters]
+* @brief
+* @retval        None
+******************************************************************************/
+#ifndef R_OSPL_NDEBUG
+void  R_JCU_PrintRegisters()
+{
+    printf( "\n" );
+    printf( "JCU Registers\n" );
+    printf( "JCMOD  = 0x%02X\n", JCU.JCMOD  );
+    printf( "JCCMD  = 0x%02X\n", JCU.JCCMD  );
+    printf( "JCQTN  = 0x%02X\n", JCU.JCQTN  );
+    printf( "JCHTN  = 0x%02X\n", JCU.JCHTN  );
+    printf( "JCDRIU = 0x%02X\n", JCU.JCDRIU );
+    printf( "JCDRID = 0x%02X\n", JCU.JCDRID );
+    printf( "JCVSZU = 0x%02X\n", JCU.JCVSZU );
+    printf( "JCVSZD = 0x%02X\n", JCU.JCVSZD );
+    printf( "JCHSZU = 0x%02X\n", JCU.JCHSZU );
+    printf( "JCHSZD = 0x%02X\n", JCU.JCHSZD );
+    printf( "JCDTCU = 0x%02X\n", JCU.JCDTCU );
+    printf( "JCDTCM = 0x%02X\n", JCU.JCDTCM );
+    printf( "JCDTCD = 0x%02X\n", JCU.JCDTCD );
+    printf( "JINTE0 = 0x%02X\n", JCU.JINTE0 );
+    printf( "JINTS0 = 0x%02X\n", JCU.JINTS0 );
+    printf( "JCDERR = 0x%02X\n", JCU.JCDERR );
+    printf( "JCRST  = 0x%02X\n", JCU.JCRST  );
+    printf( "JIFECNT   = 0x%08X\n", (uint_fast32_t) JCU.JIFECNT   );
+    /* Cast is for avoiding "format" warning of GCC_ARM */
+    printf( "JIFESA    = 0x%08X\n", (uint_fast32_t) JCU.JIFESA    );
+    printf( "JIFESOFST = 0x%08X\n", (uint_fast32_t) JCU.JIFESOFST );
+    printf( "JIFEDA    = 0x%08X\n", (uint_fast32_t) JCU.JIFEDA    );
+    printf( "JIFESLC   = 0x%08X\n", (uint_fast32_t) JCU.JIFESLC   );
+    printf( "JIFEDDC   = 0x%08X\n", (uint_fast32_t) JCU.JIFEDDC   );
+    printf( "JIFDCNT   = 0x%08X\n", (uint_fast32_t) JCU.JIFDCNT   );
+    printf( "JIFDSA    = 0x%08X\n", (uint_fast32_t) JCU.JIFDSA    );
+    printf( "JIFDDOFST = 0x%08X\n", (uint_fast32_t) JCU.JIFDDOFST );
+    printf( "JIFDDA    = 0x%08X\n", (uint_fast32_t) JCU.JIFDDA    );
+    printf( "JIFDSDC   = 0x%08X\n", (uint_fast32_t) JCU.JIFDSDC   );
+    printf( "JIFDDLC   = 0x%08X\n", (uint_fast32_t) JCU.JIFDDLC   );
+    printf( "JIFDADT   = 0x%08X\n", (uint_fast32_t) JCU.JIFDADT   );
+    printf( "JINTE1    = 0x%08X\n", (uint_fast32_t) JCU.JINTE1    );
+    printf( "JINTS1    = 0x%08X\n", (uint_fast32_t) JCU.JINTS1    );
+    printf( "JIFESVSZ  = 0x%08X\n", (uint_fast32_t) JCU.JIFESVSZ  );
+    printf( "JIFESHSZ  = 0x%08X\n", (uint_fast32_t) JCU.JIFESHSZ  );
+    printf( "JCQTBL0[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL0 );
+    printf( "JCQTBL1[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL1 );
+    printf( "JCQTBL2[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL2 );
+    printf( "JCQTBL3[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL3 );
+    printf( "JCHTBD0[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBD0 );
+    printf( "JCHTBA0[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBA0 );
+    printf( "JCHTBD1[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBD1 );
+    printf( "JCHTBA1[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBA1 );
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/cpu.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,92 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  cpu.h
+* @brief   CPU related FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef CPU_H
+#define CPU_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "cpu_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "cpu_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "cpu_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Globally enables interrupts.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+void  R_BSP_InterruptsEnable(void);
+
+
+/**
+* @brief   Globally disables interrupts.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+void  R_BSP_InterruptsDisable(void);
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* CPU_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/locking.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,115 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking.h
+* @brief   Lock related FIT BSP. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef LOCKING_H
+#define LOCKING_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#if BSP_CFG_USER_LOCKING_ENABLED
+#include "locking_user.h"
+#endif
+#include "r_typedefs.h"
+#include "locking_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "locking_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "locking_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "locking_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   Attempts to reserve a hardware peripheral lock.
+*
+* @param   HardwareIndex Index of lock to acquire from the hardware lock array.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_HardwareLock( mcu_lock_t const  HardwareIndex );
+
+
+/**
+* @brief   Releases a hardware peripheral lock.
+*
+* @param   HardwareIndex Index of lock to release from the hardware lock array.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_HardwareUnlock( mcu_lock_t const  HardwareIndex );
+
+
+/**
+* @brief   Attempts to reserve a lock.
+*
+* @param   LockObject Pointer to lock structure with lock to try and acquire.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_SoftwareLock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject );
+
+
+/**
+* @brief   Releases a lock.
+*
+* @param   LockObject Pointer to lock structure with lock to release.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_SoftwareUnlock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject );
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* LOCKING_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/locking_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,194 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking_typedef.h
+* @brief   Lock related FIT BSP. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-05-15 16:39:09 +0900#$
+*/
+
+#ifndef LOCKING_TYPEDEF_H
+#define LOCKING_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_c_lock_t
+* @brief  C-lock
+*/
+typedef struct st_r_ospl_c_lock_t  r_ospl_c_lock_t;
+struct st_r_ospl_c_lock_t {
+
+    /** IsLocked */
+    volatile bool_t  IsLocked;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  BSP_CFG_USER_LOCKING_TYPE
+* @brief  C-lock (FIT BSP portable)
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if ! BSP_CFG_USER_LOCKING_ENABLED
+#define  BSP_CFG_USER_LOCKING_TYPE  r_ospl_c_lock_t
+#endif
+
+
+/**
+* @enum   mcu_lock_t
+* @brief  Hardware channel number for locking
+*
+*    : BSP_LOCK_ADC
+*    @par :
+*/
+typedef enum {
+    BSP_LOCK_ADC,
+    BSP_LOCK_BSC,
+    BSP_LOCK_CEU,
+    BSP_LOCK_CPG,
+    BSP_LOCK_DISC0,
+    BSP_LOCK_DISC1,
+    BSP_LOCK_DMAC0,
+    BSP_LOCK_DMAC1,
+    BSP_LOCK_DMAC2,
+    BSP_LOCK_DMAC3,
+    BSP_LOCK_DMAC4,
+    BSP_LOCK_DMAC5,
+    BSP_LOCK_DMAC6,
+    BSP_LOCK_DMAC7,
+    BSP_LOCK_DMAC8,
+    BSP_LOCK_DMAC9,
+    BSP_LOCK_DMAC10,
+    BSP_LOCK_DMAC11,
+    BSP_LOCK_DMAC12,
+    BSP_LOCK_DMAC13,
+    BSP_LOCK_DMAC14,
+    BSP_LOCK_DMAC15,
+    BSP_LOCK_DVDEC0,
+    BSP_LOCK_DVDEC1,
+    BSP_LOCK_ETHER,
+    BSP_LOCK_FLCTL,
+    BSP_LOCK_GPIO,
+    BSP_LOCK_IEB,
+    BSP_LOCK_INB,
+    BSP_LOCK_INTC,
+    BSP_LOCK_IRDA,
+    BSP_LOCK_JCU,
+    BSP_LOCK_I2C,
+    BSP_LOCK_LIN0,
+    BSP_LOCK_LIN1,
+    BSP_LOCK_LVDS,
+    BSP_LOCK_MLB,
+    BSP_LOCK_MMC,
+    BSP_LOCK_MTU2,
+    BSP_LOCK_OSTM0,
+    BSP_LOCK_OSTM1,
+    BSP_LOCK_PFV0,
+    BSP_LOCK_PFV1,
+    BSP_LOCK_PWM,
+    BSP_LOCK_RIIC0,
+    BSP_LOCK_RIIC1,
+    BSP_LOCK_RIIC2,
+    BSP_LOCK_RIIC3,
+    BSP_LOCK_ROMDEC,
+    BSP_LOCK_RSCAN0,
+    BSP_LOCK_RSPI0,
+    BSP_LOCK_RSPI1,
+    BSP_LOCK_RSPI2,
+    BSP_LOCK_RSPI3,
+    BSP_LOCK_RSPI4,
+    BSP_LOCK_RTC,
+    BSP_LOCK_SCIF0,
+    BSP_LOCK_SCIF1,
+    BSP_LOCK_SCIF2,
+    BSP_LOCK_SCIF3,
+    BSP_LOCK_SCIF4,
+    BSP_LOCK_SCIF5,
+    BSP_LOCK_SCIF6,
+    BSP_LOCK_SCIF7,
+    BSP_LOCK_SCIM0,
+    BSP_LOCK_SCIM1,
+    BSP_LOCK_SCUX,
+    BSP_LOCK_SDG0,
+    BSP_LOCK_SDG1,
+    BSP_LOCK_SDG2,
+    BSP_LOCK_SDG3,
+    BSP_LOCK_SPDIF,
+    BSP_LOCK_SPIBSC0,
+    BSP_LOCK_SPIBSC1,
+    BSP_LOCK_SSIF0,
+    BSP_LOCK_SSIF1,
+    BSP_LOCK_SSIF2,
+    BSP_LOCK_SSIF3,
+    BSP_LOCK_SSIF4,
+    BSP_LOCK_SSIF5,
+    BSP_LOCK_USB200,
+    BSP_LOCK_USB201,
+    BSP_LOCK_VDC50,
+    BSP_LOCK_VDC51,
+    BSP_LOCK_WDT,
+    BSP_NUM_LOCKS /* This entry is not a valid lock. It is used for sizing
+		g_bsp_Locks[] array below. Do not touch! */
+} mcu_lock_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "mcu_interrupts.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* LOCKING_TYPEDEF_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/locking_user.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,211 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking_user.h
+* @brief   Lock related FIT BSP. User defined.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef LOCKING_USER_H
+#define LOCKING_USER_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "locking_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_user_lock_t
+* @brief  Example of user defined lock type
+*/
+typedef struct st_r_ospl_user_lock_t  r_ospl_user_lock_t;
+struct st_r_ospl_user_lock_t {
+    int  UserLockMember;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  BSP_CFG_USER_LOCKING_TYPE
+* @brief  C-lock (FIT BSP portable)
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_TYPE  r_ospl_user_lock_t
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION
+* @brief  Start C-lock for software module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION    R_OSPL_USER_LOCK_SoftwareLock
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION
+* @brief  End C-lock for software module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION  R_OSPL_USER_LOCK_SoftwareUnlock
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION
+* @brief  Start C-lock for hardware module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION    R_OSPL_USER_LOCK_HardwareLock
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION
+* @brief  End C-lock for hardware module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION  R_OSPL_USER_LOCK_HardwareUnlock
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_SoftwareLock( r_ospl_user_lock_t *LockObject );
+#endif
+
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_SoftwareUnlock( r_ospl_user_lock_t *LockObject );
+#endif
+
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_HardwareLock( mcu_lock_t  HardwareIndex );
+#endif
+
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_HardwareUnlock( mcu_lock_t  HardwareIndex );
+#endif
+
+
+/**
+* @brief   For Test
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+r_ospl_user_lock_t  *R_OSPL_GetHardwareLockObjectForTest( mcu_lock_t  HardwareIndex );
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* LOCKING_USER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/mcu_interrupts.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,106 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  mcu_interrupts.h
+* @brief   Interrupt related FIT BSP. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef MCU_INTERRUPTS_H
+#define MCU_INTERRUPTS_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#include "mcu_interrupts_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Registers a interrupt handler
+*
+* @param   IRQ_Num Interrupt request number
+* @param   Callback The function as interrupt handler
+* @return  Error code.  If there is no error, the return value is BSP_INT_SUCCESS.
+*/
+bsp_int_err_t  R_BSP_InterruptWrite( bsp_int_src_t const  IRQ_Num,  bsp_int_cb_t const  Callback );
+
+
+/**
+* @brief   Returns registered interrupt handler
+*
+* @param   IRQ_Num Interrupt request number
+* @param   out_Callback Output: the function as interrupt handler
+* @return  Error code.  If there is no error, the return value is BSP_INT_SUCCESS.
+*/
+bsp_int_err_t  R_BSP_InterruptRead( bsp_int_src_t const  IRQ_Num,  bsp_int_cb_t *const  out_Callback );
+
+
+/**
+* @brief   Controls related to the interrupt
+*
+* @param   IRQ_Num Interrupt request number
+* @param   Command Control command. See <bsp_int_cmd_t>
+* @param   NotUsed Depend on "Command" argument
+* @return  Error code.  If there is no error, the return value is BSP_INT_SUCCESS.
+*/
+bsp_int_err_t  R_BSP_InterruptControl( bsp_int_src_t const  IRQ_Num,  bsp_int_cmd_t const  Command,
+                                       void *const  NotUsed );
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* MCU_INTERRUPTS_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/mcu_interrupts_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,666 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  mcu_interrupts_typedef.h
+* @brief   Interrupt related FIT BSP. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef MCU_INTERRUPTS_TYPEDEF_H
+#define MCU_INTERRUPTS_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_multi_compiler_typedef.h"
+#if  IS_MBED_USED
+#include  "cmsis.h"
+#else
+#include  "Renesas_RZ_A1.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   bsp_int_err_t
+* @brief  Error code defined by FIT BSP.
+*
+*    - BSP_INT_SUCCESS - 0
+*    - BSP_INT_ERR_NO_REGISTERED_CALLBACK - 0x2101
+*    - BSP_INT_ERR_INVALID_ARG - 1
+*    - BSP_INT_ERR_UNSUPPORTED - 15
+*/
+typedef enum {
+    BSP_INT_SUCCESS = 0,
+    BSP_INT_ERR_NO_REGISTERED_CALLBACK = 0x2101,
+    BSP_INT_ERR_INVALID_ARG = 1,
+    BSP_INT_ERR_UNSUPPORTED = 15
+}
+                          bsp_int_err_t;
+
+
+/**
+* @brief   Interrupt Handler
+*
+* @param   int_sense uint32_t
+* @return  None
+*/
+typedef void  (* bsp_int_cb_t )(void);
+
+
+/**
+* @enum   bsp_int_cmd_t
+* @brief  Control command related to the interrupt.
+*
+*    - BSP_INT_CMD_INTERRUPT_ENABLE - 0
+*    - BSP_INT_CMD_INTERRUPT_DISABLE - 1
+*/
+typedef enum {
+    BSP_INT_CMD_INTERRUPT_ENABLE,
+    BSP_INT_CMD_INTERRUPT_DISABLE
+} bsp_int_cmd_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  FIT_NO_PTR
+* @brief  None as pointer type
+*/
+#define  FIT_NO_PTR  ( (void*) 0 )
+
+
+/**
+* @def  FIT_NO_FUNC
+* @brief  None as function pointer type
+*/
+#define  FIT_NO_FUNC ( (void*) 0 )
+
+
+/**
+* @enum   bsp_int_src_t
+* @brief  Interrupt number.
+*/
+typedef IRQn_Type  bsp_int_src_t;
+#if defined(TARGET_RZ_A1XX)
+
+#define BSP_INT_SRC_SW0             ((IRQn_Type)(0))     /* GIC software interrupt             */
+#define BSP_INT_SRC_SW1             ((IRQn_Type)(1))     /*                                    */
+#define BSP_INT_SRC_SW2             ((IRQn_Type)(2))     /*                                    */
+#define BSP_INT_SRC_SW3             ((IRQn_Type)(3))     /*                                    */
+#define BSP_INT_SRC_SW4             ((IRQn_Type)(4))     /*                                    */
+#define BSP_INT_SRC_SW5             ((IRQn_Type)(5))     /*                                    */
+#define BSP_INT_SRC_SW6             ((IRQn_Type)(6))     /*                                    */
+#define BSP_INT_SRC_SW7             ((IRQn_Type)(7))     /*                                    */
+#define BSP_INT_SRC_SW8             ((IRQn_Type)(8))     /*                                    */
+#define BSP_INT_SRC_SW9             ((IRQn_Type)(9))     /*                                    */
+#define BSP_INT_SRC_SW10            ((IRQn_Type)(10))    /*                                    */
+#define BSP_INT_SRC_SW11            ((IRQn_Type)(11))    /*                                    */
+#define BSP_INT_SRC_SW12            ((IRQn_Type)(12))    /*                                    */
+#define BSP_INT_SRC_SW13            ((IRQn_Type)(13))    /*                                    */
+#define BSP_INT_SRC_SW14            ((IRQn_Type)(14))    /*                                    */
+#define BSP_INT_SRC_SW15            ((IRQn_Type)(15))    /*                                    */
+#define BSP_INT_SRC_PMUIRQ0         ((IRQn_Type)(16))    /* CPU                                */
+#define BSP_INT_SRC_COMMRX0         ((IRQn_Type)(17))    /*                                    */
+#define BSP_INT_SRC_COMMTX0         ((IRQn_Type)(18))    /*                                    */
+#define BSP_INT_SRC_CTIIRQ0         ((IRQn_Type)(19))    /*                                    */
+#define BSP_INT_SRC_IRQ0            ((IRQn_Type)(32))    /* IRQ                                */
+#define BSP_INT_SRC_IRQ1            ((IRQn_Type)(33))    /*                                    */
+#define BSP_INT_SRC_IRQ2            ((IRQn_Type)(34))    /*                                    */
+#define BSP_INT_SRC_IRQ3            ((IRQn_Type)(35))    /*                                    */
+#define BSP_INT_SRC_IRQ4            ((IRQn_Type)(36))    /*                                    */
+#define BSP_INT_SRC_IRQ5            ((IRQn_Type)(37))    /*                                    */
+#define BSP_INT_SRC_IRQ6            ((IRQn_Type)(38))    /*                                    */
+#define BSP_INT_SRC_IRQ7            ((IRQn_Type)(39))    /*                                    */
+#define BSP_INT_SRC_PL310ERR        ((IRQn_Type)(40))    /* Level 2 cache                      */
+#define BSP_INT_SRC_DMAINT0         ((IRQn_Type)(41))    /* Direct memory access controller    */
+#define BSP_INT_SRC_DMAINT1         ((IRQn_Type)(42))    /*                                    */
+#define BSP_INT_SRC_DMAINT2         ((IRQn_Type)(43))    /*                                    */
+#define BSP_INT_SRC_DMAINT3         ((IRQn_Type)(44))    /*                                    */
+#define BSP_INT_SRC_DMAINT4         ((IRQn_Type)(45))    /*                                    */
+#define BSP_INT_SRC_DMAINT5         ((IRQn_Type)(46))    /*                                    */
+#define BSP_INT_SRC_DMAINT6         ((IRQn_Type)(47))    /*                                    */
+#define BSP_INT_SRC_DMAINT7         ((IRQn_Type)(48))    /*                                    */
+#define BSP_INT_SRC_DMAINT8         ((IRQn_Type)(49))    /*                                    */
+#define BSP_INT_SRC_DMAINT9         ((IRQn_Type)(50))    /*                                    */
+#define BSP_INT_SRC_DMAINT10        ((IRQn_Type)(51))    /*                                    */
+#define BSP_INT_SRC_DMAINT11        ((IRQn_Type)(52))    /*                                    */
+#define BSP_INT_SRC_DMAINT12        ((IRQn_Type)(53))    /*                                    */
+#define BSP_INT_SRC_DMAINT13        ((IRQn_Type)(54))    /*                                    */
+#define BSP_INT_SRC_DMAINT14        ((IRQn_Type)(55))    /*                                    */
+#define BSP_INT_SRC_DMAINT15        ((IRQn_Type)(56))    /*                                    */
+#define BSP_INT_SRC_DMAERR          ((IRQn_Type)(57))    /*                                    */
+#define BSP_INT_SRC_USBI0           ((IRQn_Type)(73))    /* USB 2.0 host/function module       */
+#define BSP_INT_SRC_USBI1           ((IRQn_Type)(74))    /*                                    */
+#define BSP_INT_SRC_S0_VI_VSYNC0    ((IRQn_Type)(75))    /* Video display controller 5         */
+#define BSP_INT_SRC_S0_LO_VSYNC0    ((IRQn_Type)(76))    /*                                    */
+#define BSP_INT_SRC_S0_VSYNCERR0    ((IRQn_Type)(77))    /*                                    */
+#define BSP_INT_SRC_GR3_VLINE0      ((IRQn_Type)(78))    /*                                    */
+#define BSP_INT_SRC_S0_VFIELD0      ((IRQn_Type)(79))    /*                                    */
+#define BSP_INT_SRC_IV1_VBUFERR0    ((IRQn_Type)(80))    /*                                    */
+#define BSP_INT_SRC_IV3_VBUFERR0    ((IRQn_Type)(81))    /*                                    */
+#define BSP_INT_SRC_IV5_VBUFERR0    ((IRQn_Type)(82))    /*                                    */
+#define BSP_INT_SRC_IV6_VBUFERR0    ((IRQn_Type)(83))    /*                                    */
+#define BSP_INT_SRC_S0_WLINE0       ((IRQn_Type)(84))    /*                                    */
+#define BSP_INT_SRC_S1_VI_VSYNC0    ((IRQn_Type)(85))    /*                                    */
+#define BSP_INT_SRC_S1_LO_VSYNC0    ((IRQn_Type)(86))    /*                                    */
+#define BSP_INT_SRC_S1_VSYNCERR0    ((IRQn_Type)(87))    /*                                    */
+#define BSP_INT_SRC_S1_VFIELD0      ((IRQn_Type)(88))    /*                                    */
+#define BSP_INT_SRC_IV2_VBUFERR0    ((IRQn_Type)(89))    /*                                    */
+#define BSP_INT_SRC_IV4_VBUFERR0    ((IRQn_Type)(90))    /*                                    */
+#define BSP_INT_SRC_S1_WLINE0       ((IRQn_Type)(91))    /*                                    */
+#define BSP_INT_SRC_OIR_VI_VSYNC0   ((IRQn_Type)(92))    /*                                    */
+#define BSP_INT_SRC_OIR_LO_VSYNC0   ((IRQn_Type)(93))    /*                                    */
+#define BSP_INT_SRC_OIR_VSYNCERR0   ((IRQn_Type)(94))    /*                                    */
+#define BSP_INT_SRC_OIR_VFIELD0     ((IRQn_Type)(95))    /*                                    */
+#define BSP_INT_SRC_IV7_VBUFERR0    ((IRQn_Type)(96))    /*                                    */
+#define BSP_INT_SRC_IV8_VBUFERR0    ((IRQn_Type)(97))    /*                                    */
+#define BSP_INT_SRC_OIR_WLINE0      ((IRQn_Type)(98))    /*                                    */
+#define BSP_INT_SRC_S0_VI_VSYNC1    ((IRQn_Type)(99))    /*                                    */
+#define BSP_INT_SRC_S0_LO_VSYNC1    ((IRQn_Type)(100))   /*                                    */
+#define BSP_INT_SRC_S0_VSYNCERR1    ((IRQn_Type)(101))   /*                                    */
+#define BSP_INT_SRC_GR3_VLINE1      ((IRQn_Type)(102))   /*                                    */
+#define BSP_INT_SRC_S0_VFIELD1      ((IRQn_Type)(103))   /*                                    */
+#define BSP_INT_SRC_IV1_VBUFERR1    ((IRQn_Type)(104))   /*                                    */
+#define BSP_INT_SRC_IV3_VBUFERR1    ((IRQn_Type)(105))   /*                                    */
+#define BSP_INT_SRC_IV5_VBUFERR1    ((IRQn_Type)(106))   /*                                    */
+#define BSP_INT_SRC_IV6_VBUFERR1    ((IRQn_Type)(107))   /*                                    */
+#define BSP_INT_SRC_S0_WLINE1       ((IRQn_Type)(108))   /*                                    */
+#define BSP_INT_SRC_S1_VI_VSYNC1    ((IRQn_Type)(109))   /*                                    */
+#define BSP_INT_SRC_S1_LO_VSYNC1    ((IRQn_Type)(110))   /*                                    */
+#define BSP_INT_SRC_S1_VSYNCERR1    ((IRQn_Type)(111))   /*                                    */
+#define BSP_INT_SRC_S1_VFIELD1      ((IRQn_Type)(112))   /*                                    */
+#define BSP_INT_SRC_IV2_VBUFERR1    ((IRQn_Type)(113))   /*                                    */
+#define BSP_INT_SRC_IV4_VBUFERR1    ((IRQn_Type)(114))   /*                                    */
+#define BSP_INT_SRC_S1_WLINE1       ((IRQn_Type)(115))   /*                                    */
+#define BSP_INT_SRC_OIR_VI_VSYNC1   ((IRQn_Type)(116))   /*                                    */
+#define BSP_INT_SRC_OIR_LO_VSYNC1   ((IRQn_Type)(117))   /*                                    */
+#define BSP_INT_SRC_OIR_VLINE1      ((IRQn_Type)(118))   /*                                    */
+#define BSP_INT_SRC_OIR_VFIELD1     ((IRQn_Type)(119))   /*                                    */
+#define BSP_INT_SRC_IV7_VBUFERR1    ((IRQn_Type)(120))   /*                                    */
+#define BSP_INT_SRC_IV8_VBUFERR1    ((IRQn_Type)(121))   /*                                    */
+#define BSP_INT_SRC_OIR_WLINE1      ((IRQn_Type)(122))   /*                                    */
+#define BSP_INT_SRC_IMRDI           ((IRQn_Type)(123))   /* Image renderer                     */
+#define BSP_INT_SRC_IMR2I0          ((IRQn_Type)(124))   /*                                    */
+#define BSP_INT_SRC_IMR2I1          ((IRQn_Type)(125))   /*                                    */
+#define BSP_INT_SRC_JEDI            ((IRQn_Type)(126))   /* JPEG Codec unit                    */
+#define BSP_INT_SRC_JDTI            ((IRQn_Type)(127))   /*                                    */
+#define BSP_INT_SRC_CMP0            ((IRQn_Type)(128))   /* Display out comparison unit        */
+#define BSP_INT_SRC_CMP1            ((IRQn_Type)(129))   /*                                    */
+#define BSP_INT_SRC_INT0            ((IRQn_Type)(130))   /* OpenVG-Compliant Renesas graphics processor */
+#define BSP_INT_SRC_INT1            ((IRQn_Type)(131))   /*                                    */
+#define BSP_INT_SRC_INT2            ((IRQn_Type)(132))   /*                                    */
+#define BSP_INT_SRC_INT3            ((IRQn_Type)(133))   /*                                    */
+#define BSP_INT_SRC_OSTM0TINT       ((IRQn_Type)(134))   /* OS timer                           */
+#define BSP_INT_SRC_OSTM1TINT       ((IRQn_Type)(135))   /*                                    */
+#define BSP_INT_SRC_CMI             ((IRQn_Type)(136))   /* Bus state controller               */
+#define BSP_INT_SRC_WTOUT           ((IRQn_Type)(137))   /*                                    */
+#define BSP_INT_SRC_ITI             ((IRQn_Type)(138))   /* Watchdog timer                     */
+#define BSP_INT_SRC_TGI0A           ((IRQn_Type)(139))   /* Multi-function timer pulse unit 2  */
+#define BSP_INT_SRC_TGI0B           ((IRQn_Type)(140))   /*                                    */
+#define BSP_INT_SRC_TGI0C           ((IRQn_Type)(141))   /*                                    */
+#define BSP_INT_SRC_TGI0D           ((IRQn_Type)(142))   /*                                    */
+#define BSP_INT_SRC_TGI0V           ((IRQn_Type)(143))   /*                                    */
+#define BSP_INT_SRC_TGI0E           ((IRQn_Type)(144))   /*                                    */
+#define BSP_INT_SRC_TGI0F           ((IRQn_Type)(145))   /*                                    */
+#define BSP_INT_SRC_TGI1A           ((IRQn_Type)(146))   /*                                    */
+#define BSP_INT_SRC_TGI1B           ((IRQn_Type)(147))   /*                                    */
+#define BSP_INT_SRC_TGI1V           ((IRQn_Type)(148))   /*                                    */
+#define BSP_INT_SRC_TGI1U           ((IRQn_Type)(149))   /*                                    */
+#define BSP_INT_SRC_TGI2A           ((IRQn_Type)(150))   /*                                    */
+#define BSP_INT_SRC_TGI2B           ((IRQn_Type)(151))   /*                                    */
+#define BSP_INT_SRC_TGI2V           ((IRQn_Type)(152))   /*                                    */
+#define BSP_INT_SRC_TGI2U           ((IRQn_Type)(153))   /*                                    */
+#define BSP_INT_SRC_TGI3A           ((IRQn_Type)(154))   /*                                    */
+#define BSP_INT_SRC_TGI3B           ((IRQn_Type)(155))   /*                                    */
+#define BSP_INT_SRC_TGI3C           ((IRQn_Type)(156))   /*                                    */
+#define BSP_INT_SRC_TGI3D           ((IRQn_Type)(157))   /*                                    */
+#define BSP_INT_SRC_TGI3V           ((IRQn_Type)(158))   /*                                    */
+#define BSP_INT_SRC_TGI4A           ((IRQn_Type)(159))   /*                                    */
+#define BSP_INT_SRC_TGI4B           ((IRQn_Type)(160))   /*                                    */
+#define BSP_INT_SRC_TGI4C           ((IRQn_Type)(161))   /*                                    */
+#define BSP_INT_SRC_TGI4D           ((IRQn_Type)(162))   /*                                    */
+#define BSP_INT_SRC_TGI4V           ((IRQn_Type)(163))   /*                                    */
+#define BSP_INT_SRC_CMI1            ((IRQn_Type)(164))   /* Motor control PWM timer            */
+#define BSP_INT_SRC_CMI2            ((IRQn_Type)(165))   /*                                    */
+#define BSP_INT_SRC_SGDEI0          ((IRQn_Type)(166))   /* Sound generator                    */
+#define BSP_INT_SRC_SGDEI1          ((IRQn_Type)(167))   /*                                    */
+#define BSP_INT_SRC_SGDEI2          ((IRQn_Type)(168))   /*                                    */
+#define BSP_INT_SRC_SGDEI3          ((IRQn_Type)(169))   /*                                    */
+#define BSP_INT_SRC_ADI             ((IRQn_Type)(170))   /* 12bit A/D converter                */
+#define BSP_INT_SRC_LMTI            ((IRQn_Type)(171))   /*                                    */
+#define BSP_INT_SRC_SSII0           ((IRQn_Type)(172))   /* Serial sound interface             */
+#define BSP_INT_SRC_SSIRXI0         ((IRQn_Type)(173))   /*                                    */
+#define BSP_INT_SRC_SSITXI0         ((IRQn_Type)(174))   /*                                    */
+#define BSP_INT_SRC_SSII1           ((IRQn_Type)(175))   /*                                    */
+#define BSP_INT_SRC_SSIRXI1         ((IRQn_Type)(176))   /*                                    */
+#define BSP_INT_SRC_SSITXI1         ((IRQn_Type)(177))   /*                                    */
+#define BSP_INT_SRC_SSII2           ((IRQn_Type)(178))   /*                                    */
+#define BSP_INT_SRC_SSIRTI2         ((IRQn_Type)(179))   /*                                    */
+#define BSP_INT_SRC_SSII3           ((IRQn_Type)(180))   /*                                    */
+#define BSP_INT_SRC_SSIRXI3         ((IRQn_Type)(181))   /*                                    */
+#define BSP_INT_SRC_SSITXI3         ((IRQn_Type)(182))   /*                                    */
+#define BSP_INT_SRC_SSII4           ((IRQn_Type)(183))   /*                                    */
+#define BSP_INT_SRC_SSIRTI4         ((IRQn_Type)(184))   /*                                    */
+#define BSP_INT_SRC_SSII5           ((IRQn_Type)(185))   /*                                    */
+#define BSP_INT_SRC_SSIRXI5         ((IRQn_Type)(186))   /*                                    */
+#define BSP_INT_SRC_SSITXI5         ((IRQn_Type)(187))   /*                                    */
+#define BSP_INT_SRC_SPDIFI          ((IRQn_Type)(188))   /* Renesas SPDIF interface            */
+#define BSP_INT_SRC_INTIICTEI0      ((IRQn_Type)(189))   /* I2C interface                      */
+#define BSP_INT_SRC_INTIICRI0       ((IRQn_Type)(190))   /*                                    */
+#define BSP_INT_SRC_INTIICTI0       ((IRQn_Type)(191))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI0      ((IRQn_Type)(192))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI0      ((IRQn_Type)(193))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI0     ((IRQn_Type)(194))   /*                                    */
+#define BSP_INT_SRC_INTIICALI0      ((IRQn_Type)(195))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI0     ((IRQn_Type)(196))   /*                                    */
+#define BSP_INT_SRC_INTIICTEI1      ((IRQn_Type)(197))   /*                                    */
+#define BSP_INT_SRC_INTIICRI1       ((IRQn_Type)(198))   /*                                    */
+#define BSP_INT_SRC_INTIICTI1       ((IRQn_Type)(199))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI1      ((IRQn_Type)(200))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI1      ((IRQn_Type)(201))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI1     ((IRQn_Type)(202))   /*                                    */
+#define BSP_INT_SRC_INTIICALI1      ((IRQn_Type)(203))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI1     ((IRQn_Type)(204))   /*                                    */
+#define BSP_INT_SRC_INTIICTEI2      ((IRQn_Type)(205))   /*                                    */
+#define BSP_INT_SRC_INTIICRI2       ((IRQn_Type)(206))   /*                                    */
+#define BSP_INT_SRC_INTIICTI2       ((IRQn_Type)(207))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI2      ((IRQn_Type)(208))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI2      ((IRQn_Type)(209))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI2     ((IRQn_Type)(210))   /*                                    */
+#define BSP_INT_SRC_INTIICALI2      ((IRQn_Type)(211))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI2     ((IRQn_Type)(212))   /*                                    */
+#define BSP_INT_SRC_INTIICTEI3      ((IRQn_Type)(213))   /*                                    */
+#define BSP_INT_SRC_INTIICRI3       ((IRQn_Type)(214))   /*                                    */
+#define BSP_INT_SRC_INTIICTI3       ((IRQn_Type)(215))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI3      ((IRQn_Type)(216))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI3      ((IRQn_Type)(217))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI3     ((IRQn_Type)(218))   /*                                    */
+#define BSP_INT_SRC_INTIICALI3      ((IRQn_Type)(219))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI3     ((IRQn_Type)(220))   /*                                    */
+#define BSP_INT_SRC_BRI0            ((IRQn_Type)(221))   /* Serial Communication Interface with FIFO */
+#define BSP_INT_SRC_ERI0            ((IRQn_Type)(222))   /*                                    */
+#define BSP_INT_SRC_RXI0            ((IRQn_Type)(223))   /*                                    */
+#define BSP_INT_SRC_TXI0            ((IRQn_Type)(224))   /*                                    */
+#define BSP_INT_SRC_BRI1            ((IRQn_Type)(225))   /*                                    */
+#define BSP_INT_SRC_ERI1            ((IRQn_Type)(226))   /*                                    */
+#define BSP_INT_SRC_RXI1            ((IRQn_Type)(227))   /*                                    */
+#define BSP_INT_SRC_TXI1            ((IRQn_Type)(228))   /*                                    */
+#define BSP_INT_SRC_BRI2            ((IRQn_Type)(229))   /*                                    */
+#define BSP_INT_SRC_ERI2            ((IRQn_Type)(230))   /*                                    */
+#define BSP_INT_SRC_RXI2            ((IRQn_Type)(231))   /*                                    */
+#define BSP_INT_SRC_TXI2            ((IRQn_Type)(232))   /*                                    */
+#define BSP_INT_SRC_BRI3            ((IRQn_Type)(233))   /*                                    */
+#define BSP_INT_SRC_ERI3            ((IRQn_Type)(234))   /*                                    */
+#define BSP_INT_SRC_RXI3            ((IRQn_Type)(235))   /*                                    */
+#define BSP_INT_SRC_TXI3            ((IRQn_Type)(236))   /*                                    */
+#define BSP_INT_SRC_BRI4            ((IRQn_Type)(237))   /*                                    */
+#define BSP_INT_SRC_ERI4            ((IRQn_Type)(238))   /*                                    */
+#define BSP_INT_SRC_RXI4            ((IRQn_Type)(239))   /*                                    */
+#define BSP_INT_SRC_TXI4            ((IRQn_Type)(240))   /*                                    */
+#define BSP_INT_SRC_BRI5            ((IRQn_Type)(241))   /*                                    */
+#define BSP_INT_SRC_ERI5            ((IRQn_Type)(242))   /*                                    */
+#define BSP_INT_SRC_RXI5            ((IRQn_Type)(243))   /*                                    */
+#define BSP_INT_SRC_TXI5            ((IRQn_Type)(244))   /*                                    */
+#define BSP_INT_SRC_BRI6            ((IRQn_Type)(245))   /*                                    */
+#define BSP_INT_SRC_ERI6            ((IRQn_Type)(246))   /*                                    */
+#define BSP_INT_SRC_RXI6            ((IRQn_Type)(247))   /*                                    */
+#define BSP_INT_SRC_TXI6            ((IRQn_Type)(248))   /*                                    */
+#define BSP_INT_SRC_BRI7            ((IRQn_Type)(249))   /*                                    */
+#define BSP_INT_SRC_ERI7            ((IRQn_Type)(250))   /*                                    */
+#define BSP_INT_SRC_RXI7            ((IRQn_Type)(251))   /*                                    */
+#define BSP_INT_SRC_TXI7            ((IRQn_Type)(252))   /*                                    */
+#define BSP_INT_SRC_INTRCANGERR     ((IRQn_Type)(253))   /* CAN interface                      */
+#define BSP_INT_SRC_INTRCANGRECC    ((IRQn_Type)(254))   /*                                    */
+#define BSP_INT_SRC_INTRCAN0REC     ((IRQn_Type)(255))   /*                                    */
+#define BSP_INT_SRC_INTRCAN0ERR     ((IRQn_Type)(256))   /*                                    */
+#define BSP_INT_SRC_INTRCAN0TRX     ((IRQn_Type)(257))   /*                                    */
+#define BSP_INT_SRC_INTRCAN1REC     ((IRQn_Type)(258))   /*                                    */
+#define BSP_INT_SRC_INTRCAN1ERR     ((IRQn_Type)(259))   /*                                    */
+#define BSP_INT_SRC_INTRCAN1TRX     ((IRQn_Type)(260))   /*                                    */
+#define BSP_INT_SRC_INTRCAN2REC     ((IRQn_Type)(261))   /*                                    */
+#define BSP_INT_SRC_INTRCAN2ERR     ((IRQn_Type)(262))   /*                                    */
+#define BSP_INT_SRC_INTRCAN2TRX     ((IRQn_Type)(263))   /*                                    */
+#define BSP_INT_SRC_INTRCAN3REC     ((IRQn_Type)(264))   /*                                    */
+#define BSP_INT_SRC_INTRCAN3ERR     ((IRQn_Type)(265))   /*                                    */
+#define BSP_INT_SRC_INTRCAN3TRX     ((IRQn_Type)(266))   /*                                    */
+#define BSP_INT_SRC_INTRCAN4REC     ((IRQn_Type)(267))   /*                                    */
+#define BSP_INT_SRC_INTRCAN4ERR     ((IRQn_Type)(268))   /*                                    */
+#define BSP_INT_SRC_INTRCAN4TRX     ((IRQn_Type)(269))   /*                                    */
+#define BSP_INT_SRC_SPEI0           ((IRQn_Type)(270))   /* Renesas serial peripheral interface */
+#define BSP_INT_SRC_SPRI0           ((IRQn_Type)(271))   /*                                    */
+#define BSP_INT_SRC_SPTI0           ((IRQn_Type)(272))   /*                                    */
+#define BSP_INT_SRC_SPEI1           ((IRQn_Type)(273))   /*                                    */
+#define BSP_INT_SRC_SPRI1           ((IRQn_Type)(274))   /*                                    */
+#define BSP_INT_SRC_SPTI1           ((IRQn_Type)(275))   /*                                    */
+#define BSP_INT_SRC_SPEI2           ((IRQn_Type)(276))   /*                                    */
+#define BSP_INT_SRC_SPRI2           ((IRQn_Type)(277))   /*                                    */
+#define BSP_INT_SRC_SPTI2           ((IRQn_Type)(278))   /*                                    */
+#define BSP_INT_SRC_SPEI3           ((IRQn_Type)(279))   /*                                    */
+#define BSP_INT_SRC_SPRI3           ((IRQn_Type)(280))   /*                                    */
+#define BSP_INT_SRC_SPTI3           ((IRQn_Type)(281))   /*                                    */
+#define BSP_INT_SRC_SPEI4           ((IRQn_Type)(282))   /*                                    */
+#define BSP_INT_SRC_SPRI4           ((IRQn_Type)(283))   /*                                    */
+#define BSP_INT_SRC_SPTI4           ((IRQn_Type)(284))   /*                                    */
+#define BSP_INT_SRC_IEBBTD          ((IRQn_Type)(285))   /* IEBusTM controller                 */
+#define BSP_INT_SRC_IEBBTERR        ((IRQn_Type)(286))   /*                                    */
+#define BSP_INT_SRC_IEBBTSTA        ((IRQn_Type)(287))   /*                                    */
+#define BSP_INT_SRC_IEBBTV          ((IRQn_Type)(288))   /*                                    */
+#define BSP_INT_SRC_ISY             ((IRQn_Type)(289))   /* CD-ROM decoder                     */
+#define BSP_INT_SRC_IERR            ((IRQn_Type)(290))   /*                                    */
+#define BSP_INT_SRC_ITARG           ((IRQn_Type)(291))   /*                                    */
+#define BSP_INT_SRC_ISEC            ((IRQn_Type)(292))   /*                                    */
+#define BSP_INT_SRC_IBUF            ((IRQn_Type)(293))   /*                                    */
+#define BSP_INT_SRC_IREADY          ((IRQn_Type)(294))   /*                                    */
+#define BSP_INT_SRC_FLSTE           ((IRQn_Type)(295))   /* NAND Flash memory controller       */
+#define BSP_INT_SRC_FLTENDI         ((IRQn_Type)(296))   /*                                    */
+#define BSP_INT_SRC_FLTREQ0I        ((IRQn_Type)(297))   /*                                    */
+#define BSP_INT_SRC_FLTREQ1I        ((IRQn_Type)(298))   /*                                    */
+#define BSP_INT_SRC_MMC0            ((IRQn_Type)(299))   /* MMC Host interface                 */
+#define BSP_INT_SRC_MMC1            ((IRQn_Type)(300))   /*                                    */
+#define BSP_INT_SRC_MMC2            ((IRQn_Type)(301))   /*                                    */
+#define BSP_INT_SRC_SDHI0_3         ((IRQn_Type)(302))   /* SD Host interface                  */
+#define BSP_INT_SRC_SDHI0_0         ((IRQn_Type)(303))   /*                                    */
+#define BSP_INT_SRC_SDHI0_1         ((IRQn_Type)(304))   /*                                    */
+#define BSP_INT_SRC_SDHI1_3         ((IRQn_Type)(305))   /*                                    */
+#define BSP_INT_SRC_SDHI1_0         ((IRQn_Type)(306))   /*                                    */
+#define BSP_INT_SRC_SDHI1_1         ((IRQn_Type)(307))   /*                                    */
+#define BSP_INT_SRC_ARM             ((IRQn_Type)(308))   /* Real time clock                    */
+#define BSP_INT_SRC_PRD             ((IRQn_Type)(309))   /*                                    */
+#define BSP_INT_SRC_CUP             ((IRQn_Type)(310))   /*                                    */
+#define BSP_INT_SRC_SCUAI0          ((IRQn_Type)(311))   /* SCUX                               */
+#define BSP_INT_SRC_SCUAI1          ((IRQn_Type)(312))   /*                                    */
+#define BSP_INT_SRC_SCUFDI0         ((IRQn_Type)(313))   /*                                    */
+#define BSP_INT_SRC_SCUFDI1         ((IRQn_Type)(314))   /*                                    */
+#define BSP_INT_SRC_SCUFDI2         ((IRQn_Type)(315))   /*                                    */
+#define BSP_INT_SRC_SCUFDI3         ((IRQn_Type)(316))   /*                                    */
+#define BSP_INT_SRC_SCUFUI0         ((IRQn_Type)(317))   /*                                    */
+#define BSP_INT_SRC_SCUFUI1         ((IRQn_Type)(318))   /*                                    */
+#define BSP_INT_SRC_SCUFUI2         ((IRQn_Type)(319))   /*                                    */
+#define BSP_INT_SRC_SCUFUI3         ((IRQn_Type)(320))   /*                                    */
+#define BSP_INT_SRC_SCUDVI0         ((IRQn_Type)(321))   /*                                    */
+#define BSP_INT_SRC_SCUDVI1         ((IRQn_Type)(322))   /*                                    */
+#define BSP_INT_SRC_SCUDVI2         ((IRQn_Type)(323))   /*                                    */
+#define BSP_INT_SRC_SCUDVI3         ((IRQn_Type)(324))   /*                                    */
+#define BSP_INT_SRC_MLB_CINT        ((IRQn_Type)(325))   /* Media local bus                    */
+#define BSP_INT_SRC_MLB_SINT        ((IRQn_Type)(326))   /*                                    */
+#define BSP_INT_SRC_DRC0            ((IRQn_Type)(327))   /* Dynamic range compalator           */
+#define BSP_INT_SRC_DRC1            ((IRQn_Type)(328))   /*                                    */
+#define BSP_INT_SRC_LINI0_INT_T     ((IRQn_Type)(331))   /* LIN/UART interface                 */
+#define BSP_INT_SRC_LINI0_INT_R     ((IRQn_Type)(332))   /*                                    */
+#define BSP_INT_SRC_LINI0_INT_S     ((IRQn_Type)(333))   /*                                    */
+#define BSP_INT_SRC_LINI0_INT_M     ((IRQn_Type)(334))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_T     ((IRQn_Type)(335))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_R     ((IRQn_Type)(336))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_S     ((IRQn_Type)(337))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_M     ((IRQn_Type)(338))   /*                                    */
+#define BSP_INT_SRC_SCI_ERI0        ((IRQn_Type)(347))   /* Serial communication interface     */
+#define BSP_INT_SRC_SCI_RXI0        ((IRQn_Type)(348))   /*                                    */
+#define BSP_INT_SRC_SCI_TXI0        ((IRQn_Type)(349))   /*                                    */
+#define BSP_INT_SRC_SCI_TEI0        ((IRQn_Type)(350))   /*                                    */
+#define BSP_INT_SRC_SCI_ERI1        ((IRQn_Type)(351))   /*                                    */
+#define BSP_INT_SRC_SCI_RXI1        ((IRQn_Type)(352))   /*                                    */
+#define BSP_INT_SRC_SCI_TXI1        ((IRQn_Type)(353))   /*                                    */
+#define BSP_INT_SRC_SCI_TEI1        ((IRQn_Type)(354))   /*                                    */
+#define BSP_INT_SRC_AVBI_DATA       ((IRQn_Type)(355))   /* EthernetAVB                        */
+#define BSP_INT_SRC_AVBI_ERROR      ((IRQn_Type)(356))   /*                                    */
+#define BSP_INT_SRC_AVBI_MANAGE     ((IRQn_Type)(357))   /*                                    */
+#define BSP_INT_SRC_AVBI_MAC        ((IRQn_Type)(358))   /*                                    */
+#define BSP_INT_SRC_ETHERI          ((IRQn_Type)(359))   /* Ethernet controller                */
+#define BSP_INT_SRC_CEUI            ((IRQn_Type)(364))   /* Capture engine unit                */
+#define BSP_INT_SRC_H2XMLB_ERRINT   ((IRQn_Type)(381))   /* Internal bus                       */
+#define BSP_INT_SRC_H2XIC1_ERRINT   ((IRQn_Type)(382))   /*                                    */
+#define BSP_INT_SRC_X2HPERI1_ERRINT ((IRQn_Type)(383))   /*                                    */
+#define BSP_INT_SRC_X2HPERI2_ERRINT ((IRQn_Type)(384))   /*                                    */
+#define BSP_INT_SRC_X2HPERI34_ERRINT ((IRQn_Type)(385))  /*                                    */
+#define BSP_INT_SRC_X2HPERI5_ERRINT ((IRQn_Type)(386))   /*                                    */
+#define BSP_INT_SRC_X2HPERI67_ERRINT ((IRQn_Type)(387))  /*                                    */
+#define BSP_INT_SRC_X2HDBGR_ERRINT  ((IRQn_Type)(388))   /*                                    */
+#define BSP_INT_SRC_X2HBSC_ERRINT   ((IRQn_Type)(389))   /*                                    */
+#define BSP_INT_SRC_X2HSPI1_ERRINT  ((IRQn_Type)(390))   /*                                    */
+#define BSP_INT_SRC_X2HSPI2_ERRINT  ((IRQn_Type)(391))   /*                                    */
+#define BSP_INT_SRC_PRRI            ((IRQn_Type)(392))   /*                                    */
+#define BSP_INT_SRC_IFEI0           ((IRQn_Type)(393))   /* Pixel format converter             */
+#define BSP_INT_SRC_OFFI0           ((IRQn_Type)(394))   /*                                    */
+#define BSP_INT_SRC_PFVEI0          ((IRQn_Type)(395))   /*                                    */
+#define BSP_INT_SRC_IFEI1           ((IRQn_Type)(396))   /*                                    */
+#define BSP_INT_SRC_OFFI1           ((IRQn_Type)(397))   /*                                    */
+#define BSP_INT_SRC_PFVEI1          ((IRQn_Type)(398))   /*                                    */
+#define BSP_INT_SRC_TINT0           ((IRQn_Type)(416))   /* Terminal interrupts                */
+#define BSP_INT_SRC_TINT1           ((IRQn_Type)(417))   /*                                    */
+#define BSP_INT_SRC_TINT2           ((IRQn_Type)(418))   /*                                    */
+#define BSP_INT_SRC_TINT3           ((IRQn_Type)(419))   /*                                    */
+#define BSP_INT_SRC_TINT4           ((IRQn_Type)(420))   /*                                    */
+#define BSP_INT_SRC_TINT5           ((IRQn_Type)(421))   /*                                    */
+#define BSP_INT_SRC_TINT6           ((IRQn_Type)(422))   /*                                    */
+#define BSP_INT_SRC_TINT7           ((IRQn_Type)(423))   /*                                    */
+#define BSP_INT_SRC_TINT8           ((IRQn_Type)(424))   /*                                    */
+#define BSP_INT_SRC_TINT9           ((IRQn_Type)(425))   /*                                    */
+#define BSP_INT_SRC_TINT10          ((IRQn_Type)(426))   /*                                    */
+#define BSP_INT_SRC_TINT11          ((IRQn_Type)(427))   /*                                    */
+#define BSP_INT_SRC_TINT12          ((IRQn_Type)(428))   /*                                    */
+#define BSP_INT_SRC_TINT13          ((IRQn_Type)(429))   /*                                    */
+#define BSP_INT_SRC_TINT14          ((IRQn_Type)(430))   /*                                    */
+#define BSP_INT_SRC_TINT15          ((IRQn_Type)(431))   /*                                    */
+#define BSP_INT_SRC_TINT16          ((IRQn_Type)(432))   /*                                    */
+#define BSP_INT_SRC_TINT17          ((IRQn_Type)(433))   /*                                    */
+#define BSP_INT_SRC_TINT18          ((IRQn_Type)(434))   /*                                    */
+#define BSP_INT_SRC_TINT19          ((IRQn_Type)(435))   /*                                    */
+#define BSP_INT_SRC_TINT20          ((IRQn_Type)(436))   /*                                    */
+#define BSP_INT_SRC_TINT21          ((IRQn_Type)(437))   /*                                    */
+#define BSP_INT_SRC_TINT22          ((IRQn_Type)(438))   /*                                    */
+#define BSP_INT_SRC_TINT23          ((IRQn_Type)(439))   /*                                    */
+#define BSP_INT_SRC_TINT24          ((IRQn_Type)(440))   /*                                    */
+#define BSP_INT_SRC_TINT25          ((IRQn_Type)(441))   /*                                    */
+#define BSP_INT_SRC_TINT26          ((IRQn_Type)(442))   /*                                    */
+#define BSP_INT_SRC_TINT27          ((IRQn_Type)(443))   /*                                    */
+#define BSP_INT_SRC_TINT28          ((IRQn_Type)(444))   /*                                    */
+#define BSP_INT_SRC_TINT29          ((IRQn_Type)(445))   /*                                    */
+#define BSP_INT_SRC_TINT30          ((IRQn_Type)(446))   /*                                    */
+#define BSP_INT_SRC_TINT31          ((IRQn_Type)(447))   /*                                    */
+#define BSP_INT_SRC_TINT32          ((IRQn_Type)(448))   /*                                    */
+#define BSP_INT_SRC_TINT33          ((IRQn_Type)(449))   /*                                    */
+#define BSP_INT_SRC_TINT34          ((IRQn_Type)(450))   /*                                    */
+#define BSP_INT_SRC_TINT35          ((IRQn_Type)(451))   /*                                    */
+#define BSP_INT_SRC_TINT36          ((IRQn_Type)(452))   /*                                    */
+#define BSP_INT_SRC_TINT37          ((IRQn_Type)(453))   /*                                    */
+#define BSP_INT_SRC_TINT38          ((IRQn_Type)(454))   /*                                    */
+#define BSP_INT_SRC_TINT39          ((IRQn_Type)(455))   /*                                    */
+#define BSP_INT_SRC_TINT40          ((IRQn_Type)(456))   /*                                    */
+#define BSP_INT_SRC_TINT41          ((IRQn_Type)(457))   /*                                    */
+#define BSP_INT_SRC_TINT42          ((IRQn_Type)(458))   /*                                    */
+#define BSP_INT_SRC_TINT43          ((IRQn_Type)(459))   /*                                    */
+#define BSP_INT_SRC_TINT44          ((IRQn_Type)(460))   /*                                    */
+#define BSP_INT_SRC_TINT45          ((IRQn_Type)(461))   /*                                    */
+#define BSP_INT_SRC_TINT46          ((IRQn_Type)(462))   /*                                    */
+#define BSP_INT_SRC_TINT47          ((IRQn_Type)(463))   /*                                    */
+#define BSP_INT_SRC_TINT48          ((IRQn_Type)(464))   /*                                    */
+#define BSP_INT_SRC_TINT49          ((IRQn_Type)(465))   /*                                    */
+#define BSP_INT_SRC_TINT50          ((IRQn_Type)(466))   /*                                    */
+#define BSP_INT_SRC_TINT51          ((IRQn_Type)(467))   /*                                    */
+#define BSP_INT_SRC_TINT52          ((IRQn_Type)(468))   /*                                    */
+#define BSP_INT_SRC_TINT53          ((IRQn_Type)(469))   /*                                    */
+#define BSP_INT_SRC_TINT54          ((IRQn_Type)(470))   /*                                    */
+#define BSP_INT_SRC_TINT55          ((IRQn_Type)(471))   /*                                    */
+#define BSP_INT_SRC_TINT56          ((IRQn_Type)(472))   /*                                    */
+#define BSP_INT_SRC_TINT57          ((IRQn_Type)(473))   /*                                    */
+#define BSP_INT_SRC_TINT58          ((IRQn_Type)(474))   /*                                    */
+#define BSP_INT_SRC_TINT59          ((IRQn_Type)(475))   /*                                    */
+#define BSP_INT_SRC_TINT60          ((IRQn_Type)(476))   /*                                    */
+#define BSP_INT_SRC_TINT61          ((IRQn_Type)(477))   /*                                    */
+#define BSP_INT_SRC_TINT62          ((IRQn_Type)(478))   /*                                    */
+#define BSP_INT_SRC_TINT63          ((IRQn_Type)(479))   /*                                    */
+#define BSP_INT_SRC_TINT64          ((IRQn_Type)(480))   /*                                    */
+#define BSP_INT_SRC_TINT65          ((IRQn_Type)(481))   /*                                    */
+#define BSP_INT_SRC_TINT66          ((IRQn_Type)(482))   /*                                    */
+#define BSP_INT_SRC_TINT67          ((IRQn_Type)(483))   /*                                    */
+#define BSP_INT_SRC_TINT68          ((IRQn_Type)(484))   /*                                    */
+#define BSP_INT_SRC_TINT69          ((IRQn_Type)(485))   /*                                    */
+#define BSP_INT_SRC_TINT70          ((IRQn_Type)(486))   /*                                    */
+#define BSP_INT_SRC_TINT71          ((IRQn_Type)(487))   /*                                    */
+#define BSP_INT_SRC_TINT72          ((IRQn_Type)(488))   /*                                    */
+#define BSP_INT_SRC_TINT73          ((IRQn_Type)(489))   /*                                    */
+#define BSP_INT_SRC_TINT74          ((IRQn_Type)(490))   /*                                    */
+#define BSP_INT_SRC_TINT75          ((IRQn_Type)(491))   /*                                    */
+#define BSP_INT_SRC_TINT76          ((IRQn_Type)(492))   /*                                    */
+#define BSP_INT_SRC_TINT77          ((IRQn_Type)(493))   /*                                    */
+#define BSP_INT_SRC_TINT78          ((IRQn_Type)(494))   /*                                    */
+#define BSP_INT_SRC_TINT79          ((IRQn_Type)(495))   /*                                    */
+#define BSP_INT_SRC_TINT80          ((IRQn_Type)(496))   /*                                    */
+#define BSP_INT_SRC_TINT81          ((IRQn_Type)(497))   /*                                    */
+#define BSP_INT_SRC_TINT82          ((IRQn_Type)(498))   /*                                    */
+#define BSP_INT_SRC_TINT83          ((IRQn_Type)(499))   /*                                    */
+#define BSP_INT_SRC_TINT84          ((IRQn_Type)(500))   /*                                    */
+#define BSP_INT_SRC_TINT85          ((IRQn_Type)(501))   /*                                    */
+#define BSP_INT_SRC_TINT86          ((IRQn_Type)(502))   /*                                    */
+#define BSP_INT_SRC_TINT87          ((IRQn_Type)(503))   /*                                    */
+#define BSP_INT_SRC_TINT88          ((IRQn_Type)(504))   /*                                    */
+#define BSP_INT_SRC_TINT89          ((IRQn_Type)(505))   /*                                    */
+#define BSP_INT_SRC_TINT90          ((IRQn_Type)(506))   /*                                    */
+#define BSP_INT_SRC_TINT91          ((IRQn_Type)(507))   /*                                    */
+#define BSP_INT_SRC_TINT92          ((IRQn_Type)(508))   /*                                    */
+#define BSP_INT_SRC_TINT93          ((IRQn_Type)(509))   /*                                    */
+#define BSP_INT_SRC_TINT94          ((IRQn_Type)(510))   /*                                    */
+#define BSP_INT_SRC_TINT95          ((IRQn_Type)(511))   /*                                    */
+#define BSP_INT_SRC_TINT96          ((IRQn_Type)(512))   /*                                    */
+#define BSP_INT_SRC_TINT97          ((IRQn_Type)(513))   /*                                    */
+#define BSP_INT_SRC_TINT98          ((IRQn_Type)(514))   /*                                    */
+#define BSP_INT_SRC_TINT99          ((IRQn_Type)(515))   /*                                    */
+#define BSP_INT_SRC_TINT100         ((IRQn_Type)(516))   /*                                    */
+#define BSP_INT_SRC_TINT101         ((IRQn_Type)(517))   /*                                    */
+#define BSP_INT_SRC_TINT102         ((IRQn_Type)(518))   /*                                    */
+#define BSP_INT_SRC_TINT103         ((IRQn_Type)(519))   /*                                    */
+#define BSP_INT_SRC_TINT104         ((IRQn_Type)(520))   /*                                    */
+#define BSP_INT_SRC_TINT105         ((IRQn_Type)(521))   /*                                    */
+#define BSP_INT_SRC_TINT106         ((IRQn_Type)(522))   /*                                    */
+#define BSP_INT_SRC_TINT107         ((IRQn_Type)(523))   /*                                    */
+#define BSP_INT_SRC_TINT108         ((IRQn_Type)(524))   /*                                    */
+#define BSP_INT_SRC_TINT109         ((IRQn_Type)(525))   /*                                    */
+#define BSP_INT_SRC_TINT110         ((IRQn_Type)(526))   /*                                    */
+#define BSP_INT_SRC_TINT111         ((IRQn_Type)(527))   /*                                    */
+#define BSP_INT_SRC_TINT112         ((IRQn_Type)(528))   /*                                    */
+#define BSP_INT_SRC_TINT113         ((IRQn_Type)(529))   /*                                    */
+#define BSP_INT_SRC_TINT114         ((IRQn_Type)(530))   /*                                    */
+#define BSP_INT_SRC_TINT115         ((IRQn_Type)(531))   /*                                    */
+#define BSP_INT_SRC_TINT116         ((IRQn_Type)(532))   /*                                    */
+#define BSP_INT_SRC_TINT117         ((IRQn_Type)(533))   /*                                    */
+#define BSP_INT_SRC_TINT118         ((IRQn_Type)(534))   /*                                    */
+#define BSP_INT_SRC_TINT119         ((IRQn_Type)(535))   /*                                    */
+#define BSP_INT_SRC_TINT120         ((IRQn_Type)(536))   /*                                    */
+#define BSP_INT_SRC_TINT121         ((IRQn_Type)(537))   /*                                    */
+#define BSP_INT_SRC_TINT122         ((IRQn_Type)(538))   /*                                    */
+#define BSP_INT_SRC_TINT123         ((IRQn_Type)(539))   /*                                    */
+#define BSP_INT_SRC_TINT124         ((IRQn_Type)(540))   /*                                    */
+#define BSP_INT_SRC_TINT125         ((IRQn_Type)(541))   /*                                    */
+#define BSP_INT_SRC_TINT126         ((IRQn_Type)(542))   /*                                    */
+#define BSP_INT_SRC_TINT127         ((IRQn_Type)(543))   /*                                    */
+#define BSP_INT_SRC_TINT128         ((IRQn_Type)(544))   /*                                    */
+#define BSP_INT_SRC_TINT129         ((IRQn_Type)(545))   /*                                    */
+#define BSP_INT_SRC_TINT130         ((IRQn_Type)(546))   /*                                    */
+#define BSP_INT_SRC_TINT131         ((IRQn_Type)(547))   /*                                    */
+#define BSP_INT_SRC_TINT132         ((IRQn_Type)(548))   /*                                    */
+#define BSP_INT_SRC_TINT133         ((IRQn_Type)(549))   /*                                    */
+#define BSP_INT_SRC_TINT134         ((IRQn_Type)(550))   /*                                    */
+#define BSP_INT_SRC_TINT135         ((IRQn_Type)(551))   /*                                    */
+#define BSP_INT_SRC_TINT136         ((IRQn_Type)(552))   /*                                    */
+#define BSP_INT_SRC_TINT137         ((IRQn_Type)(553))   /*                                    */
+#define BSP_INT_SRC_TINT138         ((IRQn_Type)(554))   /*                                    */
+#define BSP_INT_SRC_TINT139         ((IRQn_Type)(555))   /*                                    */
+#define BSP_INT_SRC_TINT140         ((IRQn_Type)(556))   /*                                    */
+#define BSP_INT_SRC_TINT141         ((IRQn_Type)(557))   /*                                    */
+#define BSP_INT_SRC_TINT142         ((IRQn_Type)(558))   /*                                    */
+#define BSP_INT_SRC_TINT143         ((IRQn_Type)(559))   /*                                    */
+#define BSP_INT_SRC_TINT144         ((IRQn_Type)(560))   /*                                    */
+#define BSP_INT_SRC_TINT145         ((IRQn_Type)(561))   /*                                    */
+#define BSP_INT_SRC_TINT146         ((IRQn_Type)(562))   /*                                    */
+#define BSP_INT_SRC_TINT147         ((IRQn_Type)(563))   /*                                    */
+#define BSP_INT_SRC_TINT148         ((IRQn_Type)(564))   /*                                    */
+#define BSP_INT_SRC_TINT149         ((IRQn_Type)(565))   /*                                    */
+#define BSP_INT_SRC_TINT150         ((IRQn_Type)(566))   /*                                    */
+#define BSP_INT_SRC_TINT151         ((IRQn_Type)(567))   /*                                    */
+#define BSP_INT_SRC_TINT152         ((IRQn_Type)(568))   /*                                    */
+#define BSP_INT_SRC_TINT153         ((IRQn_Type)(569))   /*                                    */
+#define BSP_INT_SRC_TINT154         ((IRQn_Type)(570))   /*                                    */
+#define BSP_INT_SRC_TINT155         ((IRQn_Type)(571))   /*                                    */
+#define BSP_INT_SRC_TINT156         ((IRQn_Type)(572))   /*                                    */
+#define BSP_INT_SRC_TINT157         ((IRQn_Type)(573))   /*                                    */
+#define BSP_INT_SRC_TINT158         ((IRQn_Type)(574))   /*                                    */
+#define BSP_INT_SRC_TINT159         ((IRQn_Type)(575))   /*                                    */
+#define BSP_INT_SRC_TINT160         ((IRQn_Type)(576))   /*                                    */
+#define BSP_INT_SRC_TINT161         ((IRQn_Type)(577))   /*                                    */
+#define BSP_INT_SRC_TINT162         ((IRQn_Type)(578))   /*                                    */
+#define BSP_INT_SRC_TINT163         ((IRQn_Type)(579))   /*                                    */
+#define BSP_INT_SRC_TINT164         ((IRQn_Type)(580))   /*                                    */
+#define BSP_INT_SRC_TINT165         ((IRQn_Type)(581))   /*                                    */
+#define BSP_INT_SRC_TINT166         ((IRQn_Type)(582))   /*                                    */
+#define BSP_INT_SRC_TINT167         ((IRQn_Type)(583))   /*                                    */
+#define BSP_INT_SRC_TINT168         ((IRQn_Type)(584))   /*                                    */
+#define BSP_INT_SRC_TINT169         ((IRQn_Type)(585))   /*                                    */
+#define BSP_INT_SRC_TINT170         ((IRQn_Type)(586))   /*                                    */
+
+#elif defined(TARGET_RZ_A2XX)
+
+#define BSP_INT_SRC_JEDI            ((IRQn_Type)(84))    /* JPEG Codec unit                    */
+#define BSP_INT_SRC_JDTI            ((IRQn_Type)(85))    /*                                    */
+
+#endif
+
+INLINE IRQn_Type  R_CAST_bsp_int_src_t_to_IRQn_Type( bsp_int_src_t const  Value )
+{
+    return  (IRQn_Type) Value;
+}
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "mcu_interrupts.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* MCU_INTERRUPTS_TYPEDEF_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/ospl_platform.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,77 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  ospl_platform.h
+* @brief   Header files of FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_PLATFORM_H
+#define OSPL_PLATFORM_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#include "cpu.h"
+#include "locking.h"
+#include "mcu_interrupts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_PLATFORM_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/platform_config.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  platform_config.h
+* @brief   Configuration of FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+
+/* This file is included from "Project_Config.h" */
+
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  BSP_CFG_USER_LOCKING_ENABLED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This value can be changed.
+*    See locking_user.h file.
+*/
+#define  BSP_CFG_USER_LOCKING_ENABLED   0
+
+
+/**
+* @def  BSP_CFG_RTOS_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This value cannot be changed.
+*    This value is 1 in OSPL for RTOS.
+*/
+#define  BSP_CFG_RTOS_USED  1
+
+
+/**
+* @def  BSP_CFG_PARAM_CHECKING_ENABLE
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This value can be changed.
+*/
+#define  BSP_CFG_PARAM_CHECKING_ENABLE  1
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* PLATFORM_CONFIG_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_multi_compiler.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,74 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_multi_compiler.h
+* @brief   Compiler Porting Layer. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_MULTI_COMPILER_H
+#define R_MULTI_COMPILER_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_multi_compiler_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "r_multi_compiler_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "r_multi_compiler_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "r_multi_compiler_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+} /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_MULTI_COMPILER_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_multi_compiler_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,391 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_multi_compiler_typedef.h
+* @brief   Compiler Porting Layer. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 42 $
+* $Date:: 2014-06-03 16:54:02 +0900#$
+*/
+
+#ifndef R_MULTI_COMPILER_TYPEDEF_H
+#define R_MULTI_COMPILER_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_OSPL_SECTION_INLINE_VERSION
+* @brief  R_OSPL_SECTION_INLINE_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define R_OSPL_SECTION_INLINE_VERSION  4
+
+
+/**
+* @def  R_OSPL_LIST_UP_INLINE_BODY
+* @brief  Define or not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* #define  R_OSPL_LIST_UP_INLINE_BODY */
+
+
+/**
+* @def  R_OSPL_MAKE_INLINE_BODY
+* @brief  Define or not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* #define  R_OSPL_MAKE_INLINE_BODY */
+
+
+/**
+* @def  INLINE
+* @brief  Inline function
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    "__INLINE" is reserved by compiler.
+*/
+/* ->QAC 1252 : QAC considers that && is not short-circuit evaluation */
+#if defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 199901L  &&  ! defined( __ICCARM__ ) /* For C99 */ \
+&&  ! IS_MBED_USED  ||  defined( __cplusplus )
+/* <-QAC 1252 */
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  INLINE  extern inline
+#else
+#define  INLINE  inline
+#endif
+
+/* ->QAC 1252 : QAC considers that && is not short-circuit evaluation */
+#elif defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 199901L  &&  defined( __ICCARM__ ) /* For IAR C99 */
+/* <-QAC 1252 */
+#if defined( R_OSPL_MAKE_INLINE_BODY )
+#define  INLINE
+/* "extern inline" raises a error, if with "@" operator */
+#else
+#define  INLINE  inline  /* Special inline */
+#endif
+
+#elif defined( __CC_ARM )  &&  ! defined( __GNUC__ )  /* For ARMCC not C99, not -gnu */
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#if R_OSPL_LIBRARY_MAKING
+#define  INLINE  static __inline
+#else
+#define  INLINE  extern __inline  /* Special inline */
+#endif
+#else
+#if R_OSPL_LIBRARY_MAKING
+#define  INLINE  static __inline
+#else
+#define  INLINE  extern __inline  /* Special inline */
+#endif
+#endif
+/* Function bodys are in shared "i.<FunctionName>" section */
+
+#elif defined( __GNUC__ )  /* For gcc */
+#if  IS_MBED_USED
+#define  INLINE  static __inline
+#else
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  INLINE  __inline__  /* extern inline of C99 */
+#else
+#define  INLINE  extern __inline__  /* inline of C99 */
+#endif
+#endif
+
+#elif defined( _SH )  /* For SH compiler */
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  INLINE
+#else
+#define  INLINE  static
+/* "extern" is ignored, if 'C1400 (W) Function "..." in #pragma inline is not expanded' */
+#endif
+/* No inline qualifier */
+/* #ifdef _SH */
+/* #pragma inline <function_name> */
+/* #endif */
+
+#else
+#error
+#endif
+
+
+/**
+* @def  STATIC_INLINE
+* @brief  Static inline in C source file
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    "__STATIC_INLINE" is reserved by compiler.
+*/
+
+#ifndef  __cplusplus
+
+#ifdef __CC_ARM
+#define  STATIC_INLINE  static __inline
+#endif
+
+#ifdef __ICCARM__
+#define  STATIC_INLINE  static inline
+#endif
+
+#if  defined( __GNUC__ )  &&  ! defined( __CC_ARM )
+#define  STATIC_INLINE  static inline
+#endif
+
+#else
+
+#define  STATIC_INLINE  static inline
+
+#endif  /* __cplusplus */
+
+
+/**
+* @def  R_OSPL_SECTION
+* @brief  Names section name to function or varaible
+* @par Parameters
+*    None
+* @return  None.
+*/
+/**
+* @def  R_OSPL_SECTION_FOR_ZERO_INIT
+* @brief  Names section name to zero initialized varaible
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->MISRA 19.10 : Cannot ( ) */ /* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#if defined( __CC_ARM )
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName)))  Declaration
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName), zero_init))  Declaration
+
+#elif defined( __GNUC__ )  &&  ! defined( __CC_ARM )
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName)))  Declaration
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName)))  Declaration
+
+#elif defined( __ICCARM__ )
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		Declaration @ SectionName
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		Declaration @ SectionName
+
+#elif defined( _SH )  /* For SH compiler */
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		Declaration
+/* No section qualifier */
+/* #ifdef _SH */
+/* #pragma section <section_name> */
+/* #endif */
+/*   :   */
+/* <Not extern code> */
+/*   :   */
+/* #ifdef _SH */
+/* #pragma section */
+/* #endif */
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		Declaration
+
+#else
+#error
+#endif
+/* <-MISRA 19.10 */ /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @def  R_OSPL_SECTION_FOR_INLINE
+* @brief  Names section name to inline function
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->MISRA 19.10 : Cannot ( ) */ /* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#if defined( __CC_ARM )  ||  defined( __GNUC__ )
+#if defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+			__attribute__ ((section ("INLINE_BODY")))  Declaration
+#else
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+			__attribute__ ((section (SectionName)))  Declaration
+#endif
+
+#elif defined( __ICCARM__ )
+#if defined( R_OSPL_MAKE_INLINE_BODY )
+#if defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+				Declaration @ "INLINE_BODY"
+#else
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+				Declaration @ SectionName
+#endif
+#else
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+			Declaration
+#endif
+
+#elif defined( _SH )  /* For SH compiler */
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+		Declaration
+/* No section qualifier */
+/* #ifdef _SH */
+/* #pragma section <section_name> */
+/* #endif */
+/*   :   */
+/* <Not extern code> */
+/*   :   */
+/* #ifdef _SH */
+/* #pragma section */
+/* #endif */
+
+#else
+#error
+#endif
+/* <-MISRA 19.10 */ /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @def  R_OSPL_ALIGNMENT
+* @brief  Alignments first addres of global variable
+* @param   ByteCount Value of alignment
+* @param   Declaration_with_Semicolon Declaration of the variable
+* @return  None.
+*/
+/* ->MISRA 19.10 : Cannot ( ) */ /* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#if defined( __CC_ARM )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		__align( ByteCount )  Declaration_with_Semicolon
+
+#elif defined( __GNUC__ )  &&  ! defined( __CC_ARM )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		__attribute__((aligned( ByteCount )))  Declaration_with_Semicolon
+
+#elif defined( __ICCARM__ )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		R_OSPL_ALIGNMENT_SUB( ByteCount, Declaration_with_Semicolon )
+#define  R_OSPL_ALIGNMENT_SUB( ByteCount, Declaration_with_Semicolon ) \
+		_Pragma( "diag_suppress=Pe606" ) \
+		_Pragma( "diag_suppress=Pa060" ) \
+		_Pragma( "diag_suppress=Pe609" ) \
+		R_OSPL_ALIGNMENT_##ByteCount() \
+		Declaration_with_Semicolon \
+		R_OSPL_ALIGNMENT_##0x4()
+/* align 0x4 must be written after ";" */
+
+#define  R_OSPL_ALIGNMENT_0x4()      _Pragma( "data_alignment=0x4" )
+#define  R_OSPL_ALIGNMENT_0x8()      _Pragma( "data_alignment=0x8" )
+#define  R_OSPL_ALIGNMENT_0x10()     _Pragma( "data_alignment=0x10" )
+#define  R_OSPL_ALIGNMENT_0x20()     _Pragma( "data_alignment=0x20" )
+#define  R_OSPL_ALIGNMENT_0x40()     _Pragma( "data_alignment=0x40" )
+#define  R_OSPL_ALIGNMENT_0x80()     _Pragma( "data_alignment=0x80" )
+#define  R_OSPL_ALIGNMENT_0x100()    _Pragma( "data_alignment=0x100" )
+#define  R_OSPL_ALIGNMENT_0x200()    _Pragma( "data_alignment=0x200" )
+#define  R_OSPL_ALIGNMENT_0x400()    _Pragma( "data_alignment=0x400" )
+#define  R_OSPL_ALIGNMENT_0x800()    _Pragma( "data_alignment=0x800" )
+#define  R_OSPL_ALIGNMENT_0x1000()   _Pragma( "data_alignment=0x1000" )
+#define  R_OSPL_ALIGNMENT_0x2000()   _Pragma( "data_alignment=0x2000" )
+#define  R_OSPL_ALIGNMENT_0x4000()   _Pragma( "data_alignment=0x4000" )
+#define  R_OSPL_ALIGNMENT_0x8000()   _Pragma( "data_alignment=0x8000" )
+#define  R_OSPL_ALIGNMENT_0x10000()  _Pragma( "data_alignment=0x10000" )
+#define  R_OSPL_ALIGNMENT_0x20000()  _Pragma( "data_alignment=0x20000" )
+#define  R_OSPL_ALIGNMENT_0x40000()  _Pragma( "data_alignment=0x40000" )
+#define  R_OSPL_ALIGNMENT_0x80000()  _Pragma( "data_alignment=0x80000" )
+#define  R_OSPL_ALIGNMENT_0x100000() _Pragma( "data_alignment=0x100000" )
+
+#define  R_OSPL_ALIGNMENT_4()        _Pragma( "data_alignment=4" )
+#define  R_OSPL_ALIGNMENT_8()        _Pragma( "data_alignment=8" )
+#define  R_OSPL_ALIGNMENT_16()       _Pragma( "data_alignment=16" )
+#define  R_OSPL_ALIGNMENT_32()       _Pragma( "data_alignment=32" )
+#define  R_OSPL_ALIGNMENT_64()       _Pragma( "data_alignment=64" )
+#define  R_OSPL_ALIGNMENT_128()      _Pragma( "data_alignment=128" )
+#define  R_OSPL_ALIGNMENT_256()      _Pragma( "data_alignment=256" )
+#define  R_OSPL_ALIGNMENT_512()      _Pragma( "data_alignment=512" )
+#define  R_OSPL_ALIGNMENT_1024()     _Pragma( "data_alignment=1024" )
+#define  R_OSPL_ALIGNMENT_2048()     _Pragma( "data_alignment=2048" )
+#define  R_OSPL_ALIGNMENT_4096()     _Pragma( "data_alignment=4096" )
+#define  R_OSPL_ALIGNMENT_8192()     _Pragma( "data_alignment=8192" )
+#define  R_OSPL_ALIGNMENT_16384()    _Pragma( "data_alignment=16384" )
+#define  R_OSPL_ALIGNMENT_32768()    _Pragma( "data_alignment=32768" )
+#define  R_OSPL_ALIGNMENT_65536()    _Pragma( "data_alignment=65536" )
+
+#elif defined( _SH )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		Declaration_with_Semicolon
+/* No alignment qualifier */
+/* Set aligned address by "Map section information" */
+
+#else
+#error
+#endif
+/* <-MISRA 19.10 */ /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/* Form: C Language Header */
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "r_multi_compiler.h" */
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* End of extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_MULTI_COMPILER_TYPEDEF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2036 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl.h
+* @brief   OS Porting Layer. Main Header. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_OSPL_H
+#define R_OSPL_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#include "ospl_platform.h"
+#include "r_ospl_typedef.h"
+#include "r_multi_compiler_typedef.h"
+#include "locking.h"
+#include "r_static_an_tag.h"
+#include "r_ospl_debug.h"
+#if ! R_OSPL_IS_PREEMPTION
+#include "r_ospl_os_less.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "r_ospl_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "r_ospl_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "r_ospl_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/* Section: Version and initialize */
+/**
+* @brief   Returns version number of OSPL
+*
+* @par Parameters
+*    None
+* @return  Version number of OSPL
+*
+* @par Description
+*    Return value is same as "R_OSPL_VERSION" macro.
+*/
+int32_t   R_OSPL_GetVersion(void);
+
+
+/**
+* @brief   Returns whether the environment is supported preemption
+*
+* @par Parameters
+*    None
+* @return  Whether the environment is RTOS supported preemption
+*
+* @par Description
+*    Return value is same as "R_OSPL_IS_PREEMPTION" macro.
+*/
+bool_t    R_OSPL_IsPreemption(void);
+
+
+/**
+* @brief   Initializes the internal of OSPL
+*
+* @param   NullConfig Specify NULL
+* @return  None
+*
+* @par Description
+*    Initializes internal mutual exclusion objects.
+*    However, "R_OSPL_Initialize" function does not have to be called for
+*    OSPL of "R_OSPL_IS_PREEMPTION = 0".
+*    "E_ACCESS_DENIED" error is raised, when the OSPL API that it is
+*    necessary to call "R_OSPL_Initialize" before calling the API was called.
+*/
+errnum_t  R_OSPL_Initialize( const void *const  NullConfig );
+
+
+/* Section: Standard functions */
+/**
+* @brief   No operation from C++ specification
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Compatible with __noop (MS C++). But our naming rule is not match.
+*/
+INLINE void  R_NOOP(void) {}
+
+
+/**
+* @brief   Returns element count of the array
+*
+* @param   Array An array
+* @return  Count of specified array's element
+*
+* @par Description
+*    Compatible with _countof (MS C++) and ARRAY_SIZE (Linux).
+*    But our naming rule is not match.
+*
+* @par Example
+*    @code
+*    uint32_t  array[10];
+*    R_COUNT_OF( array )  // = 10
+*    @endcode
+*
+* @par Example
+*    Array argument must not be specified the pointer using like array.
+*    @code
+*    uint32_t   array[10];
+*    func( array );
+*
+*    void  func( uint32_t array[] )  // "array" is a pointer
+*    {
+*        R_COUNT_OF( array )  // NG
+*    }
+*    @endcode
+*/
+/* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#define  R_COUNT_OF( Array )  ( sizeof( Array ) / sizeof( *(Array) ) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/* Section: Error handling and debugging (1) */
+
+
+/**
+* @def  IF
+* @brief  Breaks and transits to error state, if condition expression is not 0
+* @param   Condition Condition expression
+* @return  None
+*
+* @par Example
+*    @code
+*    e= TestFunction(); IF(e){goto fin;}
+*    @endcode
+*
+* @par Description
+*    "IF" is as same as general "if", if "R_OSPL_ERROR_BREAK" macro was
+*    defined to be 0. The following descriptions are available,
+*    if "R_OSPL_ERROR_BREAK" macro was defined to be 1.
+*
+*    "IF" macro supports to find the code raising an error.
+*
+*    If the "if statement" that is frequently seen in guard condition and
+*    after calling functions was changed to "IF" macro, the CPU breaks
+*    at raising an error. Then the status (values of variables) can be
+*    looked immediately and the code (call stack) can be looked. Thus,
+*    debug work grows in efficiency.
+*
+*    "IF" macro promotes recognizing normal code and exceptional code.
+*    Reading speed will grow up by skipping exceptional code.
+*
+*    Call "R_OSPL_SET_BREAK_ERROR_ID" function, if set to break at the code
+*    raising an error.
+*
+*    Whether the state was error state or the error raised count is stored
+*    in the thread local storage. In Release configuration, the variable
+*    of error state and the error raised count is deleted. Manage the error
+*    code using auto variable and so on at out of OSPL.
+*
+*    The error state is resolved by calling "R_OSPL_CLEAR_ERROR" function.
+*    If "R_DEBUG_BREAK_IF_ERROR" macro was called with any error state,
+*    the process breaks at the macro.
+*/
+#if R_OSPL_ERROR_BREAK
+
+/* ->MISRA 19.4 : Abnormal termination. Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#define  IF( Condition ) \
+		if ( IS( R_OSPL_OnRaisingErrorForMISRA( \
+			IS( (int_fast32_t)( Condition ) ), __FILE__, __LINE__ ) ) )
+/* (int_fast32_t) cast is for QAC warning of implicit cast unsigned to signed */
+/* != 0 is for QAC warning of MISRA 13.2 Advice */
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+#else  /* ! R_OSPL_ERROR_BREAK */
+
+/* ->MISRA 19.4 : Abnormal termination. Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#define  IF  if
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+#endif
+
+
+/**
+* @def  IF_D
+* @brief  It is same as "IF" (for Debug configuration only)
+* @param   Condition Condition expression
+* @return  None
+*
+* @par Description
+*    In Release configuration, the result of condition expression is always "false".
+*    The release configuration is the configuration defined "R_OSPL_NDEBUG".
+*/
+/* ->MISRA 19.4 : Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+/* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#ifndef R_OSPL_NDEBUG
+#define  IF_D( Condition )  IF ( Condition )
+#else
+#define  IF_D( Condition )  if ( false )
+#endif
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+
+/**
+* @def  ASSERT_R
+* @brief  Assertion (Programming By Contract)
+* @param   Condition The condition expression expected true
+* @param   goto_fin_Statement The operation doing at condition is false
+* @return  None
+*
+* @par Description
+*    It is possible to write complex sentence divided by ";" in
+*    "goto_fin_Statement" argument.
+*
+*    @par - Case of defined "R_OSPL_ERROR_BREAK" to be 0
+*    If the result of condition expression is 0(false), do "StatementsForError".
+*    If operations did nothing, write "R_NOOP()" at "StatementsForError" argument.
+*
+*    @par - Case of defined "R_OSPL_ERROR_BREAK" to be 1
+*    If the result of condition expression is 0(false), the error state
+*    will become active and the operation of "StatementForError" argument
+*    will be done.
+*/
+#ifndef  __cplusplus
+#define  ASSERT_R( Condition, goto_fin_Statement ) \
+		do{ IF(!(Condition)) { goto_fin_Statement; } } while(0)  /* do-while is CERT standard PRE10-C */
+#else
+#define  ASSERT_R( Condition, goto_fin_Statement ) \
+		{ IF(!(Condition)) { goto_fin_Statement; } }  /* no C5236(I) */
+#endif
+
+
+/**
+* @def  ASSERT_D
+* @brief  Assertion (Programming By Contract) (for Debug configuration only)
+* @param   Condition The condition expression expected true
+* @param   goto_fin_Statement The operation doing at condition is false
+* @return  None
+*
+* @par Description
+*    This does nothing in Release configuration.
+*    Release configuration is the configuration defined "R_OSPL_NDEBUG"
+*    as same as standard library.
+*/
+#ifndef R_OSPL_NDEBUG
+#define  ASSERT_D  ASSERT_R
+#else
+/* ->MISRA 19.7 : Function's argument can not get "goto_fin_Statement" */ /* ->SEC M5.1.3 */
+#define  ASSERT_D( Condition, goto_fin_Statement )  R_NOOP()
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+#endif
+
+
+/**
+* @brief   Sub routine of IF macro
+*
+* @param   Condition Condition in IF macro
+* @param   File File name
+* @param   Line Line number
+* @return  "Condition" argument
+*
+* @par Description
+*    - This part is for compliant to MISRA 2004 - 19.7.
+*/
+bool_t  R_OSPL_OnRaisingErrorForMISRA( bool_t const  Condition,  const char_t *const  File,
+                                       int_t const  Line );
+
+
+/***********************************************************************
+* Class: r_ospl_thread_id_t
+************************************************************************/
+
+/**
+* @brief   Get running thread ID (for OS less and OS-using environment)
+*
+* @par Parameters
+*    None
+* @return  The current running thread ID
+*
+* @par Description
+*    - It is possible to use this function for both OS less and OS - using environment.
+*    For OS less, returns thread ID passed to "R_OSPL_THREAD_SetCurrentId" function.
+*    "NULL" is returned, if in interrupt context.
+*/
+r_ospl_thread_id_t  R_OSPL_THREAD_GetCurrentId(void);
+
+
+/**
+* @brief   Set one or some bits to 1
+*
+* @param   ThreadId The thread ID attached the target event
+* @param   SetFlags The value of bit flags that target bit is 1
+* @return  None
+*
+* @par Description
+*    For OS less, there is the area disabled all interrupts.
+*
+*    - For OS - using environment, the thread waiting in "R_OSPL_EVENT_Wait"
+*    function might wake up soon.
+*
+*    Do nothing, when "ThreadId" = "NULL"
+*/
+void  R_OSPL_EVENT_Set( r_ospl_thread_id_t const  ThreadId, bit_flags32_t const  SetFlags );
+
+
+/**
+* @brief   Set one or some bits to 0
+*
+* @param   ThreadId The thread ID attached the target event
+* @param   ClearFlags1 The value of bit flags that clearing bit is 1
+* @return  None
+*
+* @par Description
+*    It is not necessary to call this function after called "R_OSPL_EVENT_Wait"
+*    function.
+*
+*    The way that all bit flags is cleared is setting "R_OSPL_EVENT_ALL_BITS"
+*    (=0x0000FFFF) at "ClearFlags1" argument.
+*
+*    When other thread was nofied by calling "R_OSPL_EVENT_Set", "R_OSPL_EVENT_Clear"
+*    must not be called from caller (notifier) thread.
+*
+*    For OS less, there is the area disabled all interrupts.
+*
+*    Do nothing, when "ThreadId" = "NULL"
+*/
+void  R_OSPL_EVENT_Clear( r_ospl_thread_id_t const  ThreadId, bit_flags32_t const  ClearFlags1 );
+
+
+/**
+* @brief   Get 16bit flags value
+*
+* @param   ThreadId The thread ID attached the target event
+* @return  The value of 16bit flags
+*
+* @par Description
+*    This API cannot be used in newest specification.
+*
+*    In receiving the event, call "R_OSPL_EVENT_Wait" function instead of
+*    "R_OSPL_EVENT_Get" function or call "R_OSPL_EVENT_Clear" function
+*    passed the NOT operated value of flags got by "R_OSPL_EVENT_Get" function.
+*/
+#if ( ! defined( osCMSIS )  ||  osCMSIS <= 0x10001 ) &&  R_OSPL_VERSION < 85
+bit_flags32_t  R_OSPL_EVENT_Get( r_ospl_thread_id_t const  ThreadId );
+#endif
+
+
+/**
+* @brief   Waits for setting the flags in 16bit and clear received flags
+*
+* @param   WaigingFlags The bit flags set to 1 waiting or "R_OSPL_ANY_FLAG"
+* @param   out_GotFlags NULL is permitted. Output: 16 bit flags or "R_OSPL_TIMEOUT"
+* @param   Timeout_msec Time out (millisecond) or "R_OSPL_INFINITE"
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    Waits in this function until the flags become passed flags pattern
+*    by "R_OSPL_EVENT_Set" function.
+*
+*    Check "r_ospl_async_t::ReturnValue", when the asynchronous operation
+*    was ended.
+*/
+errnum_t  R_OSPL_EVENT_Wait( bit_flags32_t const  WaigingFlags,  bit_flags32_t *const  out_GotFlags,
+                             uint32_t const  Timeout_msec );
+/* Unsigned flag (bit_flags32_t) is for QAC 4130 */
+
+
+/***********************************************************************
+* Class: r_ospl_flag32_t
+************************************************************************/
+
+/**
+* @brief   Clears all flags in 32bit to 0
+*
+* @param   self The value of 32bit flags
+* @return  None
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->flags;
+*    self->flags = 0;
+*    @endcode
+*/
+void  R_OSPL_FLAG32_InitConst( volatile r_ospl_flag32_t *const  self );
+
+
+/**
+* @brief   Set one or some bits to 1
+*
+* @param   self The value of 32bit flags
+* @param   SetFlags The value of bit flags that target bit is 1
+* @return  None
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           SetFlags;
+*    self->Flags |= SetFlags;
+*    @endcode
+*    This function is not atomic because "|=" operator is "Read Modify Write" operation.
+*/
+void  R_OSPL_FLAG32_Set( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  SetFlags );
+
+
+/**
+* @brief   Set one or some bits to 0
+*
+* @param   self The value of 32bit flags
+* @param   ClearFlags1 The value of bit flags that clearing bit is 1
+* @return  None
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           ClearFlags1;
+*
+*    self->Flags &= ~ClearFlags1;
+*    @endcode
+*
+*    Set "R_OSPL_FLAG32_ALL_BITS", if you wanted to clear all bits.
+*
+*    This function is not atomic because "&=" operator is "Read Modify Write" operation.
+*/
+void  R_OSPL_FLAG32_Clear( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  ClearFlags1 );
+
+
+/**
+* @brief   Get 32bit flags value
+*
+* @param   self The value of 32bit flags
+* @return  The value of 32bit flags
+*
+* @par Description
+*    In receiving the event, call "R_OSPL_FLAG32_GetAndClear" function
+*    instead of "R_OSPL_FLAG32_Get" function or call "R_OSPL_FLAG32_Clear"
+*    function passed the NOT operated value of flags got by "R_OSPL_FLAG32_Get"
+*    function.
+*
+*    @code
+*    Operates following operation.
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           return_flags;
+*
+*    return_flags = self->Flags;
+*
+*    return  return_flags;
+*    @endcode
+*/
+bit_flags32_t  R_OSPL_FLAG32_Get( volatile const r_ospl_flag32_t *const  self );
+
+
+/**
+* @brief   Get 32bit flags value
+*
+* @param   self The value of 32bit flags
+* @return  The value of 32bit flags
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           return_flags;
+*
+*    return_flags = self->Flags;
+*    self->Flags = 0;
+*
+*    return  return_flags;
+*    @endcode
+*
+*    This function is not atomic because the value might be set before clearing to 0.
+*/
+bit_flags32_t  R_OSPL_FLAG32_GetAndClear( volatile r_ospl_flag32_t *const  self );
+
+
+/***********************************************************************
+* Class: r_ospl_queue_t
+************************************************************************/
+
+/**
+* @brief   Initializes a queue
+*
+* @param   out_self Output: Address of initialized queue object
+* @param   QueueDefine Initial attributes of queue and work area
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    It is not possible to call this function from the library.
+*    This function is called from porting layer of the driver and send
+*    created queue to the driver.
+*
+*    OSPL does not have finalizing function (portabled with CMSIS).
+*    An object specified "QueueDefine" argument can be specified to the
+*    create function 1 times only. Some OS does not have this limitation.
+*
+*    The address of a variable as "r_ospl_queue_t*" type is set at
+*    "out_self" argument.
+*    Internal variables of the queue are stored in the variable specified
+*    with "QueueDefine" argument.
+*/
+errnum_t  R_OSPL_QUEUE_Create( r_ospl_queue_t **out_self, r_ospl_queue_def_t *QueueDefine );
+
+
+/**
+* @brief   Gets status of the queue
+*
+* @param   self A queue object
+* @param   out_Status Output: Pointer to the status structure
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    Got status are the information at calling moment.
+*    If ohter threads were run, the status will be changed.
+*    See "R_DRIVER_GetAsyncStatus" function about pointer type of
+*    "out_Status" argument
+*/
+errnum_t  R_OSPL_QUEUE_GetStatus( r_ospl_queue_t *self,  const r_ospl_queue_status_t **out_Status );
+
+
+/**
+* @brief   Allocates an element from the queue object
+*
+* @param   self A queue object
+* @param   out_Address Output: Address of allocated element
+* @param   Timeout_msec Timeout (msec) or R_OSPL_INFINITE
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    An error will be raised, if "Timeout_msec != 0" in interrupt context.
+*    It becomes "*out_Address = NULL", when it was timeout and
+*    "Timeout_msec = 0".
+*    E_TIME_OUT error is raised, when it was timeout and "Timeout_msec != 0".
+*/
+errnum_t  R_OSPL_QUEUE_Allocate( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec );
+
+
+/**
+* @brief   Sends the element to the queue
+*
+* @param   self A queue object
+* @param   Address Address of element to put
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    It is correct, even if other thread put to the queue or get from
+*    the queue from calling "R_OSPL_QUEUE_Allocate" to calling
+*    "R_OSPL_QUEUE_Put".
+*
+*    The message put to the queue by this function receives the thread
+*    calling "R_OSPL_QUEUE_Get" function.
+*/
+errnum_t  R_OSPL_QUEUE_Put( r_ospl_queue_t *self,  void *Address );
+
+
+/**
+* @brief   Receives the element from the queue
+*
+* @param   self A queue object
+* @param   out_Address Output: Address of received element
+* @param   Timeout_msec Timeout (msec) or R_OSPL_INFINITE
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    Call "R_OSPL_QUEUE_Free" function after finishing to access to
+*    the element. Don't access the memory area of the element after
+*    calling "R_OSPL_QUEUE_Free".
+*
+*    "E_NOT_THREAD" error is raised, if "Timeout_msec = 0" was specified
+*    from interrupt context. It is not possible to wait for put data to
+*    the queue in interrupt context.
+*
+*    "*out_Address" is NULL and any errors are not raised, if it becomed
+*    to timeout and "Timeout_msec = 0". "E_TIME_OUT" is raised,
+*    if "Timeout_msec != 0".
+*
+*    Specify "Timeout_msec = 0", call the following functions by the following
+*    order and use an event for preventing to block to receive other events
+*    by the thread having waited for the queue.
+*
+*    Sending Side
+*    - R_OSPL_QUEUE_Allocate
+*    - R_OSPL_QUEUE_Put
+*    - R_OSPL_EVENT_Set
+*
+*    Receiving Side
+*    - R_OSPL_EVENT_Wait
+*    - R_OSPL_QUEUE_Get
+*    - R_OSPL_QUEUE_Free
+*
+*    In OS less environment, "R_OSPL_QUEUE_Get" supports pseudo multi
+*    threading. See "R_OSPL_THREAD_GetIsWaiting" function.
+*/
+errnum_t  R_OSPL_QUEUE_Get( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec );
+
+
+/**
+* @brief   Releases the element to the queue object
+*
+* @param   self A queue object
+* @param   Address Address of received element
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    It is correct, even if other thread put to the queue or get from
+*    the queue from calling "R_OSPL_QUEUE_Get" to calling "R_OSPL_QUEUE_Free".
+*/
+errnum_t  R_OSPL_QUEUE_Free( r_ospl_queue_t *self,  void *Address );
+
+
+/**
+* @brief   Print status of the queue object
+*
+* @param   self A queue object
+* @return  Error code.  If there is no error, the return value is 0
+*/
+#ifndef  R_OSPL_NDEBUG
+errnum_t  R_OSPL_QUEUE_Print( r_ospl_queue_t *self );
+#endif
+
+
+/***********************************************************************
+* Class: r_ospl_async_t
+************************************************************************/
+
+/**
+* @brief   CopyExceptAThread
+*
+* @param   Source Source
+* @param   Destination Destination
+* @return  None
+*/
+void  R_OSPL_ASYNC_CopyExceptAThread( const r_ospl_async_t *const  Source,
+                                      r_ospl_async_t *const  Destination );
+
+
+/***********************************************************************
+* Class: r_ospl_caller_t
+************************************************************************/
+
+/**
+* @brief   Calls the interrupt callback function. It is called from OS porting layer in the driver
+*
+* @param   self The internal parameters about interrupt operations
+* @param   InterruptSource The source of the interrupt
+* @return  None
+*/
+void  R_OSPL_CallInterruptCallback( const r_ospl_caller_t *const  self,
+                                    const r_ospl_interrupt_t *const  InterruptSource );
+
+
+/**
+* @brief   Initialize <r_ospl_caller_t>.
+*
+* @param   self The internal parameters about interrupt operations
+* @param   Async <r_ospl_async_t>
+* @return  None
+*/
+void  R_OSPL_CALLER_Initialize( r_ospl_caller_t *const  self,  r_ospl_async_t *const  Async,
+                                volatile void *const  PointerToState,  int_t const  StateValueOfOnInterrupting,
+                                void *const  I_Lock, const r_ospl_i_lock_vtable_t *const  I_LockVTable );
+
+
+/**
+* @brief   GetRootChannelNum.
+*
+* @param   self The internal parameters about interrupt operations
+* @return  RootChannelNum
+*/
+INLINE int_fast32_t  R_OSPL_CALLER_GetRootChannelNum( const r_ospl_caller_t *const  self );
+
+
+/* Section: Interrupt */
+/**
+* @brief   Interrupt callback function for unregisterd interrupt.
+*
+* @param   int_sense (See INTC driver)
+* @return  None
+*/
+void  R_OSPL_OnInterruptForUnregistered( uint32_t const  int_sense );
+
+
+/**
+* @brief   Releases all disabled interrupts
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Driver user should not call this function.
+*    Call this function at the end of area of all interrupts disabled.
+*    Do not release, if all interrupts was already disabled by caller function.
+*    This function does not release disabled NMI.
+*/
+void  R_OSPL_EnableAllInterrupt(void);
+
+
+/**
+* @brief   Disables all interrupts
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Driver user should not call this function.
+*    Call this function at begin of area of all interrupts disabled.
+*    This function does not disable NMI.
+*
+* @par Example
+*    @code
+*    void  Func()
+*    {
+*        R_OSPL_DisableAllInterrupt();
+*
+*        // All interrupt disabled
+*
+*        R_OSPL_EnableAllInterrupt();
+*    }
+*    @endcode
+*/
+void    R_OSPL_DisableAllInterrupt(void);
+
+
+/**
+* @brief   Sets the priority of the interrupt line.
+*
+* @param   IRQ_Num Interrupt request number
+* @param   Priority Priority. The less the prior.
+* @return  Error code.  If there is no error, the return value is 0
+*/
+errnum_t  R_OSPL_SetInterruptPriority( bsp_int_src_t const  IRQ_Num, int_fast32_t const  Priority );
+
+
+/* Section: Locking channel */
+/**
+* @brief   Locks by channel number.
+*
+* @param   ChannelNum Locking channel number or "R_OSPL_UNLOCKED_CHANNEL"
+* @param   out_ChannelNum Output: Locked channel number, (in) NULL is permitted
+* @param   HardwareIndexMin Hardware index of channel number = 0
+* @param   HardwareIndexMax Hardware index of max channel number
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    This function is called from the internal of "R_DRIVER_Initialize"
+*    function or "R_DRIVER_LockChannel" function.
+*    This function calls "R_BSP_HardwareLock".
+*/
+errnum_t  R_OSPL_LockChannel( int_fast32_t ChannelNum, int_fast32_t *out_ChannelNum,
+                              mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax );
+
+
+/**
+* @brief   Unlocks by channel number.
+*
+* @param   ChannelNum Channel number
+* @param   e Raising error code, If there is no error, 0
+* @param   HardwareIndexMin Hardware index of channel number = 0
+* @param   HardwareIndexMax Hardware index of max channel number
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    This function is called from the internal of "R_DRIVER_Finalize"
+*    function or "R_DRIVER_UnlockChannel" function.
+*    This function calls "R_BSP_HardwareUnlock".
+*/
+errnum_t  R_OSPL_UnlockChannel( int_fast32_t ChannelNum,  errnum_t  e,
+                                mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax );
+
+
+/***********************************************************************
+* Class: r_ospl_c_lock_t
+************************************************************************/
+
+/**
+* @brief   Initializes the C-lock object
+*
+* @param   self C-lock object
+* @return  None
+*
+* @par Description
+*    If *self is global variable or static variable initialized 0,
+*    this function does not have to be called.
+*/
+void      R_OSPL_C_LOCK_InitConst( r_ospl_c_lock_t *const  self );
+
+
+/**
+* @brief   Locks the target, if lockable state.
+*
+* @param   self C-lock object
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    Even if lock owner called this function, if lock object was already
+*    locked, E_ACCESS_DENIED error is raised.
+*
+*    "R_OSPL_C_LOCK_Lock" does not do exclusive control.
+*/
+errnum_t  R_OSPL_C_LOCK_Lock( r_ospl_c_lock_t *const  self );
+
+
+/**
+* @brief   Unlocks the target.
+*
+* @param   self C-lock object
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    If this function was called with unlocked object, this function
+*    does nothing and raises "E_ACCESS_DENIED" error.
+*
+*    If self == NULL, this function does nothing and raises no error.
+*    E_NOT_THREAD error is raised, if this function was called from the
+*    interrupt context.
+*
+*    - I - lock does not do in this function.
+*
+*    "R_OSPL_C_LOCK_Unlock" does not do exclusive control.
+*/
+errnum_t  R_OSPL_C_LOCK_Unlock( r_ospl_c_lock_t *const  self );
+
+
+/***********************************************************************
+* Class: r_ospl_i_lock_vtable_t
+************************************************************************/
+
+/**
+* @brief   Do nothing. This is registered to r_ospl_i_lock_vtable_t::Lock.
+*
+* @param   self_ I-lock object
+* @return  false
+*/
+bool_t    R_OSPL_I_LOCK_LockStub( void *const  self_ );
+
+
+/**
+* @brief   Do nothing. This is registered to r_ospl_i_lock_vtable_t::Unlock.
+*
+* @param   self_ I-lock object
+* @return  None
+*/
+void      R_OSPL_I_LOCK_UnlockStub( void *const  self_ );
+
+
+/**
+* @brief   Do nothing. This is registered to r_ospl_i_lock_vtable_t::RequestFinalize.
+*
+* @param   self_ I-lock object
+* @return  None
+*/
+void      R_OSPL_I_LOCK_RequestFinalizeStub( void *const  self_ );
+
+
+/**
+* @brief   Get root channel number
+*
+* @param   self <r_ospl_caller_t> object
+* @return  Root channel number
+*/
+INLINE int_fast32_t  R_OSPL_CALLER_GetRootChannelNum( const r_ospl_caller_t *const  self )
+{
+    int_fast32_t  root_channel_num;
+
+    IF_DQ( self == NULL ) {
+        root_channel_num = 0;
+    }
+    else {
+        root_channel_num = self->I_LockVTable->GetRootChannelNum( self->I_Lock );
+    }
+
+    return  root_channel_num;
+}
+
+
+/* Section: Memory Operation */
+/**
+* @brief   Flushes cache memory
+*
+* @param   FlushType The operation of flush
+* @return  None
+*
+* @par Description
+*    Call the function of the driver after flushing input output buffer
+*    in the cache memory, If the data area accessing by the hardware is
+*    on cache and the driver did not manage the cache memory.
+*    Whether the driver manages the cache memory is depend on the driver
+*    specification.
+*/
+void  R_OSPL_MEMORY_Flush( r_ospl_flush_t const  FlushType );
+
+
+/**
+* @brief   Flushes cache memory with the range of virtual address.
+*
+* @param   FlushType The operation of flush
+* @return  None
+*
+* @par Description
+*    Align "StartAddress" argument and "Length" argument to cache line size.
+*    If not aligned, E_OTHERS error is raised.
+*    Refer to : R_OSPL_MEMORY_GetSpecification
+*
+*    If the data area written by the hardware and read from CPU was in cache
+*    rea, when the hardware started without invalidate
+*    ("R_OSPL_FLUSH_WRITEBACK_INVALIDATE" or "R_OSPL_FLUSH_INVALIDATE"),
+*    invalidate the data area and read it after finished to write by hardware.
+*    (If the driver does not manage the cache memory.)
+*/
+errnum_t  R_OSPL_MEMORY_RangeFlush( r_ospl_flush_t const  FlushType,
+                                    const void *const  StartAddress,  size_t const  Length );
+
+
+/**
+* @brief   Gets the specification about memory and cache memory.
+*
+* @param   out_MemorySpec The specification about memory and cache memory
+* @return  None
+*/
+void      R_OSPL_MEMORY_GetSpecification( r_ospl_memory_spec_t *const  out_MemorySpec );
+
+
+/**
+* @brief   Set a memory barrier.
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    In ARM, This function calls DSB assembler operation.
+*    This effects to L1 cache only.
+*/
+void      R_OSPL_MEMORY_Barrier(void);
+
+
+/**
+* @brief   Set a instruction barrier.
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    In ARM, This function calls ISB assembler operation.
+*/
+void      R_OSPL_InstructionSyncBarrier(void);
+
+
+/**
+* @brief   Changes to physical address
+*
+* @param   Address Virtual address
+* @param   out_PhysicalAddress Output: Physical address
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    This function must be modified by MMU setting.
+*/
+errnum_t  R_OSPL_ToPhysicalAddress( const volatile void *const  Address, uintptr_t *const  out_PhysicalAddress );
+
+
+/**
+* @brief   Changes to the address in the L1 cache area
+*
+* @param   Address Virtual address
+* @param   out_CachedAddress Output: Virtual address for cached area
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    This function must be modified by MMU setting.
+*    If "E_ACCESS_DENIED" error was raised, you may know the variable by
+*    looking at value of "Address" argument and map file.
+*/
+errnum_t  R_OSPL_ToCachedAddress( const volatile void *const  Address, void *const  out_CachedAddress );
+
+
+/**
+* @brief   Changes to the address in the L1 uncached area
+*
+* @param   Address Virtual address
+* @param   out_UncachedAddress Output: Virtual address for uncached area
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    This function must be modified by MMU setting.
+*    If "E_ACCESS_DENIED" error was raised, you may know the variable by
+*    looking at value of "Address" argument and map file.
+*/
+errnum_t  R_OSPL_ToUncachedAddress( const volatile void *const  Address, void *const  out_UncachedAddress );
+
+
+/**
+* @brief   Gets the level of cache for flushing the memory indicated by the address.
+*
+* @param   Address The address in flushing memory
+* @param   out_Level Output: 0=Not need to flush, 1=L1 cache only, 2=both of L1 and L2 cache
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_MEMORY_GetLevelOfFlush( const void *Address, int_fast32_t *out_Level );
+
+
+/**
+* @brief   Get 2nd cache attribute of AXI bus for peripheral (not CPU) from physical address.
+*
+* @param   PhysicalAddress The physical address in the memory area
+* @param   out_CacheAttribute Output: Cache_attribute, AWCACHE[3:0], ARCACHE[3:0]
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_AXI_Get2ndCacheAttribute( uintptr_t const  PhysicalAddress,
+        r_ospl_axi_cache_attribute_t *const  out_CacheAttribute );
+
+
+/**
+* @brief   Gets protection attribute of AXI bus from the address
+*
+* @param   PhysicalAddress The physical address in the memory area
+* @param   out_CacheAttribute Output: The protection attribute of AXI bus AWPROT[2:0], ARPROT[2:0]
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_AXI_GetProtection( uintptr_t const  physical_address,
+                                    r_ospl_axi_protection_t *const  out_protection );
+
+
+/* Section: Timer */
+/**
+* @brief   Waits for a while until passed time
+*
+* @param   DelayTime_msec Time of waiting (millisecond)
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    Maximum value is "R_OSPL_MAX_TIME_OUT" (=65533).
+*/
+errnum_t  R_OSPL_Delay( uint32_t const  DelayTime_msec );
+
+
+/**
+* @brief   Set up the free running timer
+*
+* @param   out_Specification NULL is permitted. Output: The precision of the free run timer
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    The free running timer does not stop.
+*
+*    If the counter of the free running timer was overflow, the counter returns to 0.
+*    Even in interrupt handler, the counter does count up.
+*    OSPL free running timer does not use any interrupt.
+*
+*    Using timer can be selected by "R_OSPL_FTIMER_IS" macro.
+*
+*    If the free running timer was already set up, this function does not set up it,
+*    outputs to "out_Specification" argument and does not raise any error.
+*
+*    When OSPL API function with timeout or "R_OSPL_Delay" function was called,
+*    "R_OSPL_FTIMER_InitializeIfNot" function is callbacked from these functions.
+*
+*    There is all interrupt disabled area inside.
+*/
+errnum_t  R_OSPL_FTIMER_InitializeIfNot(  r_ospl_ftimer_spec_t *const  out_Specification );
+
+
+/**
+* @brief   Gets the specification of free running timer.
+*
+* @param   out_Specification Output: The precision of the free run timer
+* @return  None
+*/
+void      R_OSPL_FTIMER_GetSpecification( r_ospl_ftimer_spec_t *const  out_Specification );
+
+
+/**
+* @brief   Get current time of free running timer.
+*
+* @par Parameters
+*    None
+* @return  The current clock count of free run timer
+*
+* @par Description
+*    Call "R_OSPL_FTIMER_InitializeIfNot" function before calling this function.
+*    Call "R_OSPL_FTIMER_IsPast" function, when it is determined whether time passed.
+*
+* @par Example
+*    @code
+*    errnum_t              e;
+*    r_ospl_ftimer_spec_t  ts;
+*    uint32_t              start;
+*    uint32_t              end;
+*
+*    e= R_OSPL_FTIMER_InitializeIfNot( &ts ); IF(e){goto fin;}
+*    start = R_OSPL_FTIMER_Get();
+*
+*    // The section of measuring
+*
+*    end = R_OSPL_FTIMER_Get();
+*    printf( "%d msec\n", R_OSPL_FTIMER_CountToTime(
+*            &ts, end - start ) );
+*    @endcode
+*/
+uint32_t  R_OSPL_FTIMER_Get(void);
+
+
+/**
+* @brief   Returns whether specified time was passed
+*
+* @param   ts Precision of the free running timer
+* @param   Now Count of current time
+* @param   TargetTime Count of target time
+* @param   out_IsPast Output: Whether the target time was past or not
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_FTIMER_IsPast( const r_ospl_ftimer_spec_t *const  ts,
+                                uint32_t const  Now,  uint32_t const  TargetTime,  bool_t *const  out_IsPast );
+
+
+/**
+* @brief   Change from mili-second unit to free running timer unit
+*
+* @param   ts Precision of the free running timer
+* @param   msec The value of mili-second unit
+* @return  The value of free running timer unit
+*
+* @par Description
+*    The fractional part is been round up. (For waiting time must be more
+*    than specified time.)
+*
+*    This function calculates like the following formula.
+*    @code
+*    ( msec * ts->msec_Denominator + ts->msec_Numerator - 1 ) / ts->msec_Numerator
+*    @endcode
+*
+*    - Attention: If "ts - >msec_Denominator" was more than "ts->msec_Numerator",
+*    take care of overflow.
+*/
+INLINE uint32_t  R_OSPL_FTIMER_TimeToCount( const r_ospl_ftimer_spec_t *const  ts,
+        uint32_t const  msec )
+{
+    uint32_t  count;
+
+    IF_DQ( ts == NULL ) {
+        count = 0;
+    }
+    else {
+        count = ( ((msec * ts->msec_Denominator) + ts->msec_Numerator) - 1u ) / ts->msec_Numerator;
+    }
+    return  count;
+}
+
+
+/**
+* @brief   Change from free running timer unit to mili-second unit
+*
+* @param   ts Precision of the free running timer
+* @param   Count The value of free running timer unit
+* @return  The value of mili-second unit
+*
+* @par Description
+*    The fractional part is been round down. (Because overflow does not
+*    occur, when "Count = r_ospl_ftimer_spec_t::MaxCount" )
+*
+*    This function calculates like the following formula.
+*    @code
+*    ( Count * ts->msec_Numerator ) / ts->msec_Denominator
+*    @endcode
+*/
+INLINE uint32_t  R_OSPL_FTIMER_CountToTime( const r_ospl_ftimer_spec_t *const  ts,
+        uint32_t const  Count )
+{
+    uint32_t  time;
+
+    IF_DQ( ts == NULL ) {
+        time = 0;
+    }
+    else {
+        time = ( Count * ts->msec_Numerator ) / ts->msec_Denominator;
+    }
+    return  time;
+}
+
+
+/***********************************************************************
+* Class: r_ospl_table_t
+************************************************************************/
+
+/**
+* @brief   Initializes an index table
+*
+* @param   self Index table object
+* @param   Area First address of the index table
+* @param   AreaByteSize Size of the index table. See <R_OSPL_TABLE_SIZE>
+* @param   Is_T_Lock Whether to call <R_OSPL_Start_T_Lock>
+* @return  None
+*/
+void  R_OSPL_TABLE_InitConst( r_ospl_table_t *const  self,
+                              void *const  Area, size_t const  AreaByteSize, bool_t const  Is_T_Lock );
+
+
+/**
+* @brief   Returns index from related key
+*
+* @param   self Index table object
+* @param   Key Key number
+* @param   out_Index Output: Related index
+* @param   TypeOfIfNot Behavior when key was not registerd. See <r_ospl_if_not_t>
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_TABLE_GetIndex( r_ospl_table_t *const  self, const void *const  Key,
+                                 int_fast32_t *const  out_Index,  r_ospl_if_not_t const  TypeOfIfNot );
+
+
+/**
+* @brief   Separates relationship of specified key and related index
+*
+* @param   self Index table object
+* @param   Key Key number
+* @return  None
+*
+* @par Description
+*    Error is not raised, even if specified key was already separated.
+*/
+void  R_OSPL_TABLE_Free( r_ospl_table_t *const  self, const void *const  Key );
+
+
+/**
+* @brief   Print status of specified index table object (for debug)
+*
+* @param   self Index table object
+* @return  None
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_OSPL_TABLE_Print( r_ospl_table_t *const  self );
+#endif
+
+
+/* Section: Bit flags */
+/**
+* @brief   Evaluate whether any passed bits are 1 or not
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bits are 1
+* @return  Whether the any passed bit are 1
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_BIT_SET( Variable, ConstValue ) \
+	( BIT_And_Sub( Variable, ConstValue ) != 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether any passed bits are 1 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the any passed bit are 1
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ANY_BITS_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) != 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether all passed bits are 1 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 1
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ALL_BITS_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) == (OrConstValue) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether the passed bit is 0 or not
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bit is 1
+* @return  Whether the passed bit is 0
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_BIT_NOT_SET( Variable, ConstValue ) \
+	( BIT_And_Sub( Variable, ConstValue ) == 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether any passed bits are 0 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the any passed bit are 0
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ANY_BITS_NOT_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) != (OrConstValue) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether all passed bits are 0 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 0
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ALL_BITS_NOT_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) == 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Sub routine of bitwise operation
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 0
+*
+* @par Description
+*    - This part is for compliant to MISRA 2004 - 19.7.
+*/
+INLINE uint_fast32_t  BIT_And_Sub( bit_flags_fast32_t const  Variable,
+                                   bit_flags_fast32_t const  ConstValue )
+{
+    return  ((Variable) & (ConstValue));
+}
+
+
+/***********************************************************************
+* About: IS_BIT_SET__Warning
+*
+* - This is for QAC-3344 warning : MISRA 13.2 Advice : Tests of a value against
+*   zero should be made explicit, unless the operand is effectively Boolean.
+* - This is for QAC-1253 warning : SEC M1.2.2 : A "U" suffix shall be applied
+*   to all constants of unsigned type.
+************************************************************************/
+
+
+/* Section: Error handling and debugging (2) */
+/**
+* @brief   Breaks here
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Does break by calling "R_DebugBreak" function.
+*    This macro is not influenced the setting of "R_OSPL_ERROR_BREAK" macro.
+*/
+#define  R_DEBUG_BREAK()  R_DebugBreak(__FILE__,__LINE__)
+
+
+/**
+* @brief   The function callbacked from OSPL for breaking
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 0
+*
+* @par Description
+*    Set a break point at this function.
+*    In Release configuration, "File = NULL, Line = 0".
+*    If "File = NULL", "Line" argument is error code.
+*    This function can be customized by application developer.
+*/
+void  R_DebugBreak( const char_t *const  File,  int_fast32_t const  Line );
+
+
+/**
+* @brief   Breaks here, if it is error state
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    Checks the error state of the current thread.
+*    Call this macro from the last of each thread.
+*    Does break by calling "R_DebugBreak" function.
+*
+*    If an error was raised, this function calls "printf" with following message.
+*    Set "error_ID" to "R_OSPL_SET_BREAK_ERROR_ID"
+*    @code
+*    <ERROR error_ID="0x1" file="../src/api.c(336)"/>
+*    @endcode
+*/
+#if R_OSPL_ERROR_BREAK
+#define  R_DEBUG_BREAK_IF_ERROR()  R_OSPL_DebugBreakIfError(__FILE__,__LINE__)
+void  R_OSPL_DebugBreakIfError( const char_t *const  File,  int_fast32_t const  Line );
+#else
+INLINE void  R_DEBUG_BREAK_IF_ERROR(void) {}
+#endif
+
+
+/**
+* @brief   Raises the error of system unrecoverable
+*
+* @param   e Error code
+* @return  None
+*
+* @par Description
+*    The error of system unrecoverable is the error of impossible to
+*    - self - recover by process or main system. Example, the heap area was
+*    broken or there are not any responses from hardware. This error can
+*    be recoverable by OS or the system controller(e.g. Software reset)
+*
+*    Example, when an error of recovery process was raised,
+*    "R_OSPL_RaiseUnrecoverable" function must be called.
+*
+*    "R_OSPL_RaiseUnrecoverable" function can be customized by the
+*    application. By default, it calls "R_DebugBreak" function and falls
+*    into the infinite loop.
+*/
+void  R_OSPL_RaiseUnrecoverable( errnum_t const  e );
+
+
+/**
+* @brief   Merge the error code raised in the finalizing operation
+*
+* @param   CurrentError Current error code
+* @param   AppendError New append error code
+* @return  Merged error code
+*
+* @par Description
+*    When the state was error state, if other new error was raised,
+*    new error code is ignored.
+*    - If "CurrentError != 0", this function returns "CurrentError" argument.
+*    - If "CurrentError == 0", this function returns "AppendError" argument.
+*
+*    This function can be modify by user.
+*
+* @par Example
+*    @code
+*    ee= Sample();
+*    e= R_OSPL_MergeErrNum( e, ee );
+*    return  e;
+*    @endcode
+*/
+INLINE errnum_t  R_OSPL_MergeErrNum( errnum_t const  CurrentError,  errnum_t const  AppendError )
+{
+    errnum_t  e;
+
+    if ( CurrentError != 0 ) {
+        e = CurrentError;
+    } else {
+        e = AppendError;
+    }
+    return  e;
+}
+
+
+/**
+* @brief   Sets an error code to TLS (Thread Local Storage).
+*
+* @param   e Raising error code
+* @return  None
+*
+* @par Description
+*    Usually error code is returned. If API function cannot return any
+*    error code, API function can have the specification of setting error
+*    code by "R_OSPL_SetErrNum".
+*
+*    There is this function, if "R_OSPL_TLS_ERROR_CODE" macro was defined
+*    to be 1.
+*    This function does nothing, if any error code was stored already in TLS.
+*    The state does not change to error state, if "R_OSPL_SetErrNum" function
+*    was called only. See "R_OSPL_GET_ERROR_ID".
+*/
+#if R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_SetErrNum( errnum_t const  e );
+#endif
+
+
+/**
+* @brief   Returns the error code from TLS (Thread Local Storage).
+*
+* @par Parameters
+*    None
+* @return  Error code
+*
+* @par Description
+*    Usually error code is returned. If API function cannot return any
+*    error code, API function may have the specification of getting error
+*    code by "R_OSPL_GetErrNum".
+*
+*    There is this function, if "R_OSPL_TLS_ERROR_CODE" macro was defined
+*    to be 1. This function returns 0 after called "R_OSPL_CLEAR_ERROR"
+*    function.
+*/
+#if R_OSPL_TLS_ERROR_CODE
+errnum_t  R_OSPL_GetErrNum(void);
+#endif
+
+
+/**
+* @brief   Clears the error state
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro and
+*    "R_OSPL_TLS_ERROR_CODE" macro were defined to be 0. The following
+*    descriptions are available, if "R_OSPL_ERROR_BREAK" macro was
+*    defined to be 1.
+*
+*    Whether the state is the error state is stored in thread local
+*    storage. "R_OSPL_GetErrNum" function returns 0 after called this
+*    function.
+*
+*    If the error state was not cleared, the following descriptions were caused.
+*    - Breaks at "R_DEBUG_BREAK_IF_ERROR" macro
+*    - "R_OSPL_SET_BREAK_ERROR_ID" function behaves not expected behavior
+*       because the count of error is not counted up.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_CLEAR_ERROR(void);
+#else
+INLINE void  R_OSPL_CLEAR_ERROR(void) {}  /* QAC 3138 */
+#endif
+
+
+/**
+* @brief   Returns the number of current error
+*
+* @par Parameters
+*    None
+* @return  The number of current error
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    This function returns 0, if any errors were not raised.
+*
+*    This function returns 1, if first error was raised.
+*
+*    After that, this function returns 2, if second error was raised after
+*    calling "R_OSPL_CLEAR_ERROR" function.
+*    This function does not return 0 after that the error was cleared by
+*    calling "R_OSPL_CLEAR_ERROR".
+*    The number of current error is running number in the whole of system
+*    (all threads).
+*
+*    Error is raised by following macros.
+*    @code
+*    IF, IF_D, ASSERT_R, ASSERT_D
+*    @endcode
+*    The process breaks at a moment of error raised, if the number of current
+*    error was set to "R_OSPL_SET_BREAK_ERROR_ID" macro.
+*/
+#if R_OSPL_ERROR_BREAK
+int_fast32_t  R_OSPL_GET_ERROR_ID(void);
+#else
+INLINE int_fast32_t  R_OSPL_GET_ERROR_ID(void)
+{
+    return -1;
+}
+#endif
+
+
+/**
+* @brief   Register to break at raising error at the moment
+*
+* @param   ID Breaking number of error
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    Set a break point at "R_DebugBreak" function, when the process breaks
+*    at the error raised code.
+*
+*    The number of "ErrorID" argument can be known by "R_DEBUG_BREAK_IF_ERROR"
+*    macro or "R_OSPL_GET_ERROR_ID" macro.
+*    - In multi - threading environment, the number of "ErrorID" argument is the
+*    number of raised errors in all threads. But when "ErrorID" argument was
+*    set to be over 2, call "R_OSPL_SET_DEBUG_WORK" function before calling
+*    "R_OSPL_SET_BREAK_ERROR_ID" function.
+*
+*    The following code breaks at first error.
+*    @code
+*    R_OSPL_SET_BREAK_ERROR_ID( 1 );
+*    @endcode
+*
+*    The following code breaks at next error after resuming from meny errors.
+*    @code
+*    R_OSPL_SET_BREAK_ERROR_ID( R_OSPL_GET_ERROR_ID() + 1 );
+*    @endcode
+*/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_BREAK_ERROR_ID( int_fast32_t ID );
+#else
+INLINE void  R_OSPL_SET_BREAK_ERROR_ID( int_fast32_t const ID )
+{
+    R_UNREFERENCED_VARIABLE( ID );
+}
+#endif
+
+
+/**
+* @brief   Set the debug work area
+*
+* @param   WorkArea Start address of work area
+* @param   WorkAreaSize Size of work area (byte). See. <R_OSPL_DEBUG_WORK_SIZE>
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    Set the debug work area, when "R_OSPL_SET_BREAK_ERROR_ID" function
+*    supports multi thread. "E_NO_DEBUG_TLS" error is raised, if the debug
+*    work area was not set, when errors was raised in 2 or more threads.
+*    It is not necessary to call this function, if error handling did by one
+*    thread only.
+*
+* @par Example
+*    @code
+*    #if R_OSPL_ERROR_BREAK
+*    #define  GS_MAX_THREAD  10
+*    static uint8_t  gs_DebugWorkArea[ R_OSPL_DEBUG_WORK_SIZE( GS_MAX_THREAD ) ];
+*    #endif
+*
+*    R_OSPL_SET_DEBUG_WORK( gs_DebugWorkArea, sizeof(gs_DebugWorkArea) );
+*    @endcode
+*/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_DEBUG_WORK( void *WorkArea, uint32_t WorkAreaSize );
+#else
+INLINE void  R_OSPL_SET_DEBUG_WORK( const void *const WorkArea, uint32_t const WorkAreaSize )
+{
+    R_UNREFERENCED_VARIABLE_2( WorkArea, WorkAreaSize );
+}
+#endif
+
+
+/**
+* @brief   Returns debbug information of current thread.
+*
+* @par Parameters
+*    None
+* @return  Debbug information of current thread.
+*/
+#if R_OSPL_ERROR_BREAK
+r_ospl_error_t  *R_OSPL_GetCurrentThreadError(void);
+#endif
+
+
+/**
+* @brief   Modifies count of objects that current thread has locked.
+*
+* @param   Plus The value of adding to the counter.
+* @return  None
+*
+* @par Description
+*    The counter is subtracted, if this argument was minus.
+*
+*    Drivers calls this function.
+*    This function is not called from OSPL.
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro is 0.
+*/
+#if R_OSPL_ERROR_BREAK
+#if R_OSPL_IS_PREEMPTION
+void         R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus );
+#else
+INLINE void  R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus ) {}
+#endif
+#else
+INLINE void          R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus ) {}
+#endif
+
+
+/**
+* @brief   Returns count of objects that current thread has locked.
+*
+* @par Parameters
+*    None
+* @return  Count of objects that current thread has locked
+*
+* @par Description
+*    This function returns 0, if "R_OSPL_ERROR_BREAK" macro is 0.
+*/
+#if R_OSPL_ERROR_BREAK
+#if R_OSPL_IS_PREEMPTION
+int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void);
+#else
+INLINE int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void)
+{
+    return 0;
+}
+#endif
+#else
+INLINE int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void)
+{
+    return 0;
+}
+#endif
+
+
+/* Section: Accessing to register bit field */
+/**
+* @brief   Reads modifies writes for bit field of 32bit register.
+*
+* @param   in_out_Register Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @param   Value Writing value before shift to the bit field
+* @return  None
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". But this is not depend on compiler spcifications. */
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. This expects 32bit CPU. But driver code is no problem. */
+
+#define  R_OSPL_SET_TO_32_BIT_REGISTER( in_out_Register, Mask, Shift, Value ) \
+	( *(volatile uint32_t*)(in_out_Register) = (uint32_t)( \
+		( ((uint32_t) *(volatile uint32_t*)(in_out_Register)) & \
+		~(Mask) ) | ( (Mask) & ( ( (uint_fast32_t)(Value) << (Shift) ) & (Mask) ) ) ) )
+/* This code is optimized well. */
+
+/* <-SEC M1.2.2(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else
+
+INLINE void  R_OSPL_SET_TO_32_BIT_REGISTER( volatile uint32_t *const  Register,
+        uint32_t const  Mask,  int_fast32_t const  Shift,  uint32_t const  Value )
+{
+    uint32_t  reg_value;
+
+    IF_DQ ( Register == NULL ) {}
+    else {
+        reg_value = *Register;
+        reg_value = ( reg_value & ~Mask ) | ( ( Value << Shift ) & Mask );
+        *Register = reg_value;
+    }
+}
+
+#endif
+
+
+/**
+* @brief   Reads modifies writes for bit field of 16bit register.
+*
+* @param   in_out_Register Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @param   Value Writing value before shift to the bit field
+* @return  None
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". But this is not depend on compiler spcifications. */
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. This expects 32bit CPU. But driver code is no problem. */
+
+#define  R_OSPL_SET_TO_16_BIT_REGISTER( in_out_Register, Mask, Shift, Value ) \
+	( *(volatile uint16_t*)(in_out_Register) = (uint16_t)( \
+		( ((uint16_t) *(volatile uint16_t*)(in_out_Register)) & \
+		~(Mask) ) | ( (Mask) & ( ( (uint_fast16_t)(Value) << (Shift) ) & (Mask) ) ) ) )
+/* This code is optimized well. */
+
+
+/* <-SEC M1.2.2(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else
+
+INLINE void  R_OSPL_SET_TO_16_BIT_REGISTER( volatile uint16_t *const  Register,
+        uint16_t const  Mask,  int_fast32_t const  Shift,  uint16_t const  Value )
+{
+    uint16_t  reg_value;
+
+    IF_DQ ( Register == NULL ) {}
+    else {
+        reg_value = *Register;
+        reg_value = (uint16_t)( ( (uint_fast32_t) reg_value & ~(uint_fast32_t) Mask ) |
+                                ( ( (uint_fast32_t) Value << Shift ) & (uint_fast32_t) Mask ) );
+        /* Cast is for SEC R2.4.2 */
+        *Register = reg_value;
+    }
+}
+
+#endif
+
+
+/**
+* @brief   Reads modifies writes for bit field of 8bit register.
+*
+* @param   in_out_Register Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @param   Value Writing value before shift to the bit field
+* @return  None
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". But this is not depend on compiler spcifications. */
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. This expects 32bit CPU. But driver code is no problem. */
+
+
+#define  R_OSPL_SET_TO_8_BIT_REGISTER( in_out_Register, Mask, Shift, Value ) \
+	( *(volatile uint8_t*)(in_out_Register) = (uint8_t)( \
+		( ((uint8_t) *(volatile uint8_t*)(in_out_Register)) & \
+		~(Mask) ) | ( (Mask) & ( ( (uint_fast8_t)(Value) << (Shift) ) & (Mask) ) ) ) )
+/* This code is optimized well. */
+
+/* <-SEC M1.2.2(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else
+
+INLINE void  R_OSPL_SET_TO_8_BIT_REGISTER( volatile uint8_t *const  Register,
+        uint8_t const  Mask,  int_fast32_t const  Shift,  uint8_t const  Value )
+{
+    uint8_t  reg_value;
+
+    IF_DQ ( Register == NULL ) {}
+    else {
+        reg_value = *Register;
+        reg_value = (uint8_t)( ( (uint_fast32_t) reg_value & ~(uint_fast32_t) Mask ) |
+                               ( ( (uint_fast32_t) Value << Shift ) & (uint_fast32_t) Mask ) );
+        /* Cast is for SEC R2.4.2 */
+        *Register = reg_value;
+    }
+}
+
+#endif
+
+
+/**
+* @brief   Reads for bit field of 32bit register.
+*
+* @param   RegisterValueAddress Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @return  Read value after shift
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at &(get address), cast and *(memory load). But this is not double volatile access. */
+/*    RegisterValueAddress is for avoid QAC-0310,QAC-3345 by cast code at caller. */
+
+#define  R_OSPL_GET_FROM_32_BIT_REGISTER( RegisterValueAddress, Mask, Shift ) \
+	( (uint32_t)( ( (uint32_t)*(volatile const uint32_t*) (RegisterValueAddress) \
+		&  (uint_fast32_t)(Mask) ) >> (Shift) ) )
+/* This code is optimized well. */
+
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else  /* __QAC_ARM_H__ */  /* This code must be tested defined "__QAC_ARM_H__" */
+
+
+/* This inline functions is not expanded on __CC_ARM 5.15 */
+INLINE uint32_t  R_OSPL_GET_FROM_32_BIT_REGISTER( volatile const uint32_t *const  RegisterAddress,
+        uint32_t const  Mask,  int_fast32_t const  Shift )
+{
+    uint32_t  reg_value;
+
+    IF_DQ ( RegisterAddress == NULL ) {
+        enum { num = 0x0EDEDEDE };  /* SEC M1.10.1 */
+        reg_value = num;
+    }
+    else {
+        reg_value = *RegisterAddress;
+        reg_value = ( reg_value & Mask ) >> Shift;
+    }
+    return  reg_value;
+}
+
+#endif
+
+
+/**
+* @brief   Reads for bit field of 16bit register.
+*
+* @param   RegisterValueAddress Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @return  Read value after shift
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at &(get address), cast and *(memory load). But this is not double volatile access. */
+/*    RegisterValueAddress is for avoid QAC-0310,QAC-3345 by cast code at caller. */
+
+#define  R_OSPL_GET_FROM_16_BIT_REGISTER( RegisterValueAddress, Mask, Shift ) \
+	( (uint16_t)( ( (uint_fast32_t)*(volatile const uint16_t*) (RegisterValueAddress) \
+		&  (uint_fast16_t)(Mask) ) >> (Shift) ) )
+/* This code is optimized well. */
+
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else  /* __QAC_ARM_H__ */  /* This code must be tested defined "__QAC_ARM_H__" */
+
+/* This inline functions is not expanded on __CC_ARM 5.15 */
+INLINE uint16_t  R_OSPL_GET_FROM_16_BIT_REGISTER( volatile const uint16_t *const  RegisterAddress,
+        uint16_t const  Mask,  int_fast32_t const  Shift )
+{
+    uint16_t  reg_value;
+
+    IF_DQ ( RegisterAddress == NULL ) {
+        enum { num = 0xDEDE };  /* SEC M1.10.1 */
+        reg_value = num;
+    }
+    else {
+        reg_value = *RegisterAddress;
+        reg_value = (uint16_t)( ( (uint_fast32_t) reg_value & (uint_fast32_t) Mask ) >> Shift );
+        /* Cast is for SEC R2.4.2 */
+    }
+    return  reg_value;
+}
+
+#endif
+
+
+/**
+* @brief   Reads for bit field of 8bit register.
+*
+* @param   RegisterValueAddress Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @return  Read value after shift
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at &(get address), cast and *(memory load). But this is not double volatile access. */
+/*    RegisterValueAddress is for avoid QAC-0310,QAC-3345 by cast code at caller. */
+
+#define  R_OSPL_GET_FROM_8_BIT_REGISTER( RegisterValueAddress, Mask, Shift ) \
+	( (uint8_t)( ( (uint_fast32_t)*(volatile const uint8_t*) (RegisterValueAddress) \
+		&  (uint_fast8_t)(Mask) ) >> (Shift) ) )
+/* This code is optimized well. */
+
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else  /* __QAC_ARM_H__ */  /* This code must be tested defined "__QAC_ARM_H__" */
+
+/* This inline functions is not expanded on __CC_ARM 5.15 */
+INLINE uint8_t  R_OSPL_GET_FROM_8_BIT_REGISTER( volatile const uint8_t *const  RegisterAddress,
+        uint8_t const  Mask,  int_fast32_t const  Shift )
+{
+    uint8_t  reg_value;
+
+    IF_DQ ( RegisterAddress == NULL ) {
+        enum { num = 0xDE };  /* SEC M1.10.1 */
+        reg_value = num;
+    }
+    else {
+        reg_value = *RegisterAddress;
+        reg_value = (uint8_t)( ( (uint_fast32_t) reg_value & (uint_fast32_t) Mask ) >> Shift );
+        /* Cast is for SEC R2.4.2 */
+    }
+    return  reg_value;
+}
+
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_RTX_private.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,86 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_RTX_private.h
+* @brief   OS Porting Layer API for RTX
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_RTX_PRIVATE_H
+#define OSPL_RTX_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Starts T-Lock. It is mutual exclusion of threads.
+*
+* @par Parameters
+*    None
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_OSPL_Start_T_Lock(void);
+
+
+/**
+* @brief   Ends T-Lock. It is mutual exclusion of threads.
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void      R_OSPL_End_T_Lock(void);
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_RTX_PRIVATE_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_config.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,243 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_config.h
+* @brief   Configuration of OSPL.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+
+/* This file is included from "Project_Config.h" */
+
+
+#ifndef R_OSPL_CONFIG_H
+#define R_OSPL_CONFIG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "platform_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_OSPL_VERSION
+* @brief  Version number of OSPL
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can not be changed.
+*    101 = version 1.01.
+*    Hundreds place is version number of OSPL specification.
+*    Tens place and one's place are minor version number in specified OS and board.
+*/
+#define  R_OSPL_VERSION  90
+
+
+/**
+* @def  R_OSPL_VERSION_STRING
+* @brief  String of version number of OSPL.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can not be changed.
+*/
+#define  R_OSPL_VERSION_STRING  "0.90"
+
+
+/**
+* @def  R_OSPL_IS_PREEMPTION
+* @brief  Whether preemptive RTOS or not.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can not be changed.
+*    The value is 1 or 0.
+*    This value is 0, if the environment was OS less.
+*    It is necessary to configure to pseudo multithreading, if this value was 0.
+*/
+#define  R_OSPL_IS_PREEMPTION   BSP_CFG_RTOS_USED
+
+
+/**
+* @def  R_OSPL_NDEBUG
+* @brief  Debug configuration or Release configuration.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    Define (=Release) or not define (=Debug).
+*    This is same as "NDEBUG" of standard library.
+*    The system can run with the debug configuration OSPL and the release
+*    configuration application.
+*    If the library (compiled binary) called the debug configuration OSPL,
+*    compile the OSPL source with debug configuration.
+*/
+#ifndef  R_OSPL_NDEBUG
+#define  R_OSPL_NDEBUG
+#endif
+
+
+/**
+* @def  R_OSPL_ERROR_BREAK
+* @brief  Whether it is supported to break, when error was raised.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#ifndef  R_OSPL_ERROR_BREAK
+#ifdef  R_OSPL_NDEBUG
+#define  R_OSPL_ERROR_BREAK  0
+#else
+#define  R_OSPL_ERROR_BREAK  1
+#endif
+#endif
+
+
+/**
+* @def  R_OSPL_TLS_ERROR_CODE
+* @brief  Whether it is supported that error code is stored in thread local storage
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*    This value must be 1 by some application or some library with OSPL.
+*/
+#ifndef  R_OSPL_TLS_ERROR_CODE
+#define  R_OSPL_TLS_ERROR_CODE  1
+#endif
+
+
+/**
+* @def  R_OSPL_LIBRARY_MAKING
+* @brief  Whether current project makes library.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#ifndef  R_OSPL_LIBRARY_MAKING
+#define  R_OSPL_LIBRARY_MAKING  0
+#endif
+
+
+/**
+* @def  R_BOOL_IS_SIGNED
+* @brief  Whether compiler defines that bool_t type is signed.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#define  R_BOOL_IS_SIGNED  1
+
+
+/**
+* @def  R_OSPL_BIT_FIELD_ACCESS_MACRO
+* @brief  Whether bit field access function is provided as macro or function.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 (=macro) or 0 (=function).
+*/
+#define  R_OSPL_BIT_FIELD_ACCESS_MACRO  1
+
+
+/***********************************************************************
+* Macros: R_OSPL_FTIMER_IS
+*    Which channel of timer to use.
+*
+*    : R_OSPL_FTIMER_IS_OSTM0    - OSTM0
+*    : R_OSPL_FTIMER_IS_OSTM1    - OSTM1
+*    : R_OSPL_FTIMER_IS_MTU2_1_2 - MTU2 ch1 and ch2
+*
+* Description:
+*    The value can be changed.
+************************************************************************/
+#define  R_OSPL_FTIMER_IS        R_OSPL_FTIMER_IS_MTU2_1_2
+#define  R_OSPL_FTIMER_IS_OSTM0     0
+#define  R_OSPL_FTIMER_IS_OSTM1     1
+#define  R_OSPL_FTIMER_IS_MTU2_1_2  2
+
+#if R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+#error  OSTM0 is used by RTX
+#endif
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_debug.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,250 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_debug.h
+* @brief   Debug tools provided by OSPL.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_DEBUG_H
+#define OSPL_DEBUG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_OSPL_DEBUG_TOOL
+* @brief  Whether debug tools function is defined
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#ifndef  R_OSPL_DEBUG_TOOL
+#ifndef R_OSPL_NDEBUG
+#define  R_OSPL_DEBUG_TOOL  1
+#else
+#define  R_OSPL_DEBUG_TOOL  0
+#endif
+#endif
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/* Group: Watch */
+
+/**
+* @brief   Registers watching integer variable or pointer variable
+*
+* @param   IndexNum Watch Number, 0 or more
+* @param   Address Address of watching integer variable or pointer variable
+* @param   BreakValue Breaking value of variable when "R_D_Watch" was called
+* @param   IsPrintf Whether "printf" is called, when "R_D_Watch" was called
+* @return  None
+*
+* @par Description
+*    @ref R_D_Add and @ref R_D_Watch are APIs related to watch function.
+*    This debug tool is available, if @ref R_OSPL_DEBUG_TOOL was set to 1.
+*
+*    There is not this function, if @ref R_OSPL_DEBUG_TOOL macro was defined
+*    to be 0. This function is available, if @ref R_OSPL_DEBUG_TOOL macro was
+*    defined to be 1.
+*
+* @par Example
+*    @code
+*    R_D_Add( 0, &var, 0xB0, true );  // 0xB0 may be not hit
+*    @endcode
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Add( int_fast32_t IndexNum, volatile const void *Address, uint32_t BreakValue, bool_t IsPrintf );
+#endif
+
+
+/**
+* @brief   Show and Check watching variable's value
+*
+* @param   IndexNum Watch Number, 0 or more
+* @return  None
+*
+* @par Description
+*    @ref R_D_Add and @ref R_D_Watch are APIs related to watch function.
+*    This debug tool is available, if "R_OSPL_DEBUG_TOOL" was set to 1.
+*    This function calls "printf" with the value of variable registered
+*    by "R_D_Add" and breaks when watching variable becomes registered value.
+*    This function can be called from out of scope of registered variable.
+*    Then this function can be written at many places without care of the scope.
+*
+*    There is not this function, if @ref R_OSPL_DEBUG_TOOL macro was defined
+*    to be 0. This function is available, if @ref R_OSPL_DEBUG_TOOL macro was
+*    defined to be 1.
+*
+*    If internal data of the debug tool was broken, the global variable in
+*    "r_ospl_debug.o" file should be move to safe address (memory map).
+*
+* @par Example
+*    @code
+*    printf( 41 );  // Show the value indicated this place
+*    R_D_Watch( 0 );
+*    @endcode
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Watch( int_fast32_t IndexNum );
+#endif
+
+
+/* Group: Int Log */
+
+/**
+* @brief   Records to the log fast
+*
+* @param   Value Recording value
+* @return  None
+*
+* @par Description
+*    @ref R_D_AddToIntLog, @ref g_IntLog and @ref g_IntLogLength are APIs related
+*    to Int Log function.
+*    This debug tool is available, if @ref R_OSPL_DEBUG_TOOL was set to 1.
+*    This function overwrites from the first of the log, if max element
+*    value of "g_IntLog" was over.
+*    It is recommended to record not only the showing value of variable,
+*    but also the value of the identifier of the place and the value of
+*    current time.
+*
+*    There is not this function, if @ref R_OSPL_DEBUG_TOOL macro was defined
+*    to be 0. This function is available, if @ref R_OSPL_DEBUG_TOOL macro was
+*    defined to be 1.
+*
+*    If internal data of the debug tool was broken, the global variable in
+*    "r_ospl_debug.o" file should be move to safe address (memory map).
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_AddToIntLog( int_fast32_t Value );
+#endif
+
+
+/**
+* @def  g_IntLogCount
+* @brief  Max count of int log
+*/
+#if R_OSPL_DEBUG_TOOL
+enum { g_IntLogCount = 100 };
+#endif
+
+
+/** Memory area of int log */
+#if R_OSPL_DEBUG_TOOL
+extern volatile int_fast32_t   g_IntLog[ g_IntLogCount ];
+#endif
+
+
+/** Length of recorded in <g_IntLog> */
+#if R_OSPL_DEBUG_TOOL
+extern volatile int_fast32_t   g_IntLogLength;
+#endif
+
+
+/* Group: Debug Variable */
+
+/**
+* @def  g_DebugVarCount
+* @brief  Count of debug variable.
+*/
+#if R_OSPL_DEBUG_TOOL
+enum { g_DebugVarCount = 10 };
+#endif
+
+
+/** Debug variables. */
+#if R_OSPL_DEBUG_TOOL
+extern volatile uint_fast32_t  g_DebugVar[ g_DebugVarCount ];
+#endif
+
+
+/* Group: Through Counter */
+
+/**
+* @brief   Count the through count
+*
+* @param   in_out_Counter Input/Output: The through counter
+* @param   TargetCount The value comparing with the through counter
+* @param   Label The label for "printf", NULL=printf : no output
+* @return  None
+*
+* @par Description
+*    This debug tool is available, if @ref R_OSPL_DEBUG_TOOL was set to 1.
+*    If this function was called with "TargetCount = 0", the count of
+*    through is output by "printf" for each calling. If "TargetCount"
+*    argument was set to the through count and restart the program,
+*    when the counter was counted up to "TargetCount", this function
+*    returns "true". If there were many "printf" output, set "Label = NULL".
+*    At first calling, the address of the counter is output by "printf".
+*    The counter can be look by the debugger.
+*
+* @par Example
+*    @code
+*    { static int tc;  if ( R_D_Counter( &tc, 0, "A" ) ) {
+*    R_DEBUG_BREAK(); }}
+*    @endcode
+*/
+#if R_OSPL_DEBUG_TOOL
+bool_t  R_D_Counter( int_fast32_t *in_out_Counter, int_fast32_t TargetCount, char_t *Label );
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* _OSPL_DEBUG_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_os_less.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,197 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_os_less.h
+* @brief   OS Porting Layer API for OS less Compatibility
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_OS_LESS_H
+#define OSPL_OS_LESS_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_os_less_typedef.h"
+#include "./r_ospl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "ospl_os_less_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "ospl_os_less_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "ospl_os_less_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Set waiting behavior of current thread.
+*
+* @param   OnWait Behavior on waiting
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    Initial value is @ref R_OSPL_WAIT_POLLING.
+*    If this function was called from the interrupt context, E_STATE error is raised.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    Arguments are ignored.
+*    This function returns 0.
+*
+*    Refer to: @ref R_OSPL_THREAD_GetIsWaiting
+*/
+INLINE errnum_t  R_OSPL_THREAD_SetOnWait( r_ospl_wait_t const  OnWait )
+{
+    return  0;
+}
+
+
+/**
+* @brief   Get waiting behavior of current thread.
+*
+* @par Parameters
+*    None
+* @return  Behavior on waiting
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    Initial value is @ref R_OSPL_WAIT_POLLING.
+*    If this function was called from the interrupt context,
+*    this function returns @ref R_OSPL_WAIT_POLLING.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    This function returns R_OSPL_WAIT_POLLING.
+*    But it does not polling on waiting
+*
+*    Refer to: @ref R_OSPL_THREAD_SetOnWait
+*/
+INLINE r_ospl_wait_t  R_OSPL_THREAD_GetOnWait(void)
+{
+    return  R_OSPL_WAIT_POLLING;
+}
+
+
+/**
+* @brief   Get whether the current thread is waiting or not.
+*
+* @par Parameters
+*    None
+* @return  Whether the current thread is waiting or not
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    If @ref R_OSPL_WAIT_PM_THREAD was set by @ref R_OSPL_THREAD_SetOnWait function,
+*    some waiting functions return soon even if the state is waiting and
+*    @ref R_OSPL_THREAD_GetIsWaiting function returns true.
+*
+*    If time out was set to 0, @ref R_OSPL_THREAD_GetIsWaiting function returns
+*    true at time out, even if any value was passed to @ref R_OSPL_THREAD_SetOnWait
+*    function,
+*
+*    If this function was called from the interrupt context, this function
+*    returns false and @ref ASSERT_D in this function notifies in debug configuration.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    This function returns false.
+*
+* @par Example
+*    @code
+*    e= R_OSPL_Delay( 100 ); IF(e){goto fin;}
+*    if ( R_OSPL_THREAD_GetIsWaiting() ) { e=0; goto fin; }
+*    @endcode
+*/
+INLINE bool_t  R_OSPL_THREAD_GetIsWaiting(void)
+{
+    return  false;
+}
+
+
+/**
+* @brief   Exit waiting state, if current thread was waiting state.
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    The thread returned true from @ref R_OSPL_THREAD_GetIsWaiting function
+*    after a waiting function must call the waiting function again.
+*    After exiting waiting state, other operation and other waiting can
+*    be done. If time out was set to 0, exiting does not have to do.
+*
+*    If it was detected in OSPL API that necessary exiting was not done,
+*    E_STATE error is raised. However sometimes the state can not be detected.
+*    In this case, time out will be not correct.
+*
+*    This function does not do anything called from the interrupt context.
+*    "ASSERT_D" in this function notifies in debug configuration.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    This function does not do anything.
+*/
+INLINE void  R_OSPL_THREAD_ExitWaiting(void)
+{
+}
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_OS_LESS_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_os_less_private.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,133 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_os_less_private.h
+* @brief   OS Porting Layer private functions for OS less
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_OS_LESS_PRIVATE_H
+#define OSPL_OS_LESS_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_os_less_typedef.h"
+#include "./r_ospl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/**
+* @struct  r_ospl_master_t
+* @brief  Variables for OSPL
+*/
+typedef struct st_r_ospl_master_t  r_ospl_master_t;
+struct st_r_ospl_master_t {
+#if ! R_OSPL_IS_PREEMPTION
+    /** CurrentThread */
+    r_ospl_thread_def_t    *CurrentThread;
+
+    /** IdleCallback */
+    r_ospl_idle_callback_t  IdleCallback;
+#endif
+    /** IsFreeRunTimerSpec */
+    bool_t  IsFreeRunTimerSpec;
+
+    /** FreeRunTimerSpec */
+    r_ospl_ftimer_spec_t  FreeRunTimerSpec;
+
+    /** MaxOneTimeoutTime */
+    uint32_t  MaxOneTimeoutTime;
+};
+
+
+/* Section: Global */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Returns <r_ospl_master_t> type variable.
+*
+* @par Parameters
+*    None
+* @return  <r_ospl_master_t> type variable.
+*/
+r_ospl_master_t  *R_OSPL_GetPrivateContext(void);
+
+
+/**
+* @brief   Sub routine of <R_OSPL_MEMORY_Flush>
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void    R_OSPL_MEMORY_Flush_Sub(void);
+
+
+/**
+* @brief   GetCacheLineSize
+*
+* @par Parameters
+*    None
+* @return  CacheLineSize
+*/
+size_t  R_OSPL_MEMORY_GetCacheLineSize(void);
+
+
+/**
+* @brief   Sub routine of <R_OSPL_MEMORY_RangeFlush>
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void    R_OSPL_MEMORY_RangeFlush_Sub( uintptr_t Start,  uintptr_t Over,  size_t CacheLineSize );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_OS_LESS_PRIVATE_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_os_less_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,83 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_os_less_typedef.h
+* @brief   OS Porting Layer API for OS less Compatibility. Data types.
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_OS_LESS_TYPEDEF_H
+#define OSPL_OS_LESS_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   r_ospl_wait_t
+* @brief  Waitnig mode of pseudo multi thread
+*
+*    - R_OSPL_WAIT_POLLING - 0
+*    - R_OSPL_WAIT_PM_THREAD - 1
+*/
+typedef enum {
+    R_OSPL_WAIT_POLLING   = 0,
+    R_OSPL_WAIT_PM_THREAD = 1
+}
+                        r_ospl_wait_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "r_ospl_os_less.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_OS_LESS_TYPEDEF_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_private.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_private.h
+* @brief   OS Porting Layer private API for OS less
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_OSPL_PRIVATE_H
+#define R_OSPL_PRIVATE_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_table_block_t
+* @brief  Block of <r_ospl_table_t>
+*/
+typedef struct st_r_ospl_table_block_t  r_ospl_table_block_t;
+struct st_r_ospl_table_block_t {
+
+    /** this[ SortedKeyIndex ].Key ... */
+    const void  *Key;
+
+    /** Index */
+    int16_t  Index;
+
+    /** this[ Index ].NextFreeIndex  : Index is not same as SortedKeyIndex */
+    int16_t  NextFreeIndex;
+};
+enum {
+    R_OSPL_TABLE_BLOCK_USED    = -1,
+    R_OSPL_TABLE_BLOCK_NO_NEXT = -2
+};
+
+
+/**
+* @struct  r_ospl_table_searched_t
+* @brief  Result of searching
+*/
+typedef struct st_r_ospl_table_searched_t  r_ospl_table_searched_t;
+struct st_r_ospl_table_searched_t {
+
+    /** SortedKeyIndex */
+    int_fast32_t  SortedKeyIndex;
+
+    /** IsFound */
+    bool_t  IsFound;
+};
+
+
+/* Section: Global */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+#if ! IS_MBED_USED
+#if  defined( __CC_ARM )
+
+/* ->QAC 0289 */ /* ->QAC 1002 */ /* ->MISRA 5.1 */
+extern uint32_t  Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base;
+extern uint32_t  Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base;
+extern uint32_t  Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$ZI$$Limit;
+extern uint32_t  Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit;
+/* <-QAC 0289 */ /* <-QAC 1002 */ /* <-MISRA 5.1 */
+
+#endif
+#else  /* IS_MBED_USED */
+extern uint32_t  Image$$RW_DATA_NC$$Base;
+#endif
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   LockUnlockedChannel
+*
+* @param   out_ChannelNum ChannelNum
+* @param   HardwareIndexMin HardwareIndexMin
+* @param   HardwareIndexMax HardwareIndexMax
+* @return  Error Code. 0=No Error.
+*/
+#if ! BSP_CFG_USER_LOCKING_ENABLED
+errnum_t  R_OSPL_LockUnlockedChannel( int_fast32_t *out_ChannelNum,
+                                      mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax );
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_PRIVATE_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_ospl_typedef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,917 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_typedef.h
+* @brief   OS Porting Layer. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_OSPL_TYPEDEF_H
+#define R_OSPL_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef  __GNUC__
+#include  <stdint.h>
+#include  <stdbool.h>
+#endif
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "mcu_interrupts_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+typedef struct st_r_ospl_async_t          r_ospl_async_t;
+typedef struct st_r_ospl_async_status_t   r_ospl_async_status_t;
+typedef struct st_r_ospl_flag32_t         r_ospl_flag32_t;
+typedef struct st_r_ospl_interrupt_t      r_ospl_interrupt_t;
+typedef struct st_r_ospl_irq_mask_t       r_ospl_irq_mask_t;
+typedef struct st_r_ospl_memory_spec_t    r_ospl_memory_spec_t;
+typedef struct st_r_ospl_ftimer_spec_t    r_ospl_ftimer_spec_t;
+typedef struct st_r_ospl_table_t          r_ospl_table_t;
+typedef struct st_r_ospl_i_lock_vtable_t  r_ospl_i_lock_vtable_t;
+typedef struct st_r_ospl_caller_t         r_ospl_caller_t;
+
+
+/**
+* @typedef  errnum_t
+* @brief  Error number
+*/
+typedef int_fast32_t   errnum_t;
+
+
+/**
+* @typedef  bit_flags_fast32_t
+* @brief  Bit flags as "uint_fast32_t"
+*/
+typedef uint_fast32_t  bit_flags_fast32_t;
+
+
+/**
+* @typedef  bit_flags32_t
+* @brief  Bit flags as "uint32_t"
+*/
+typedef uint32_t       bit_flags32_t;
+
+
+/**
+* @typedef  bit_flags16_t
+* @brief  Bit flags as "uint16_t"
+*/
+typedef uint16_t       bit_flags16_t;
+
+
+/**
+* @typedef  bit_flags8_t
+* @brief  Bit flags as "uint8_t"
+*/
+typedef uint8_t       bit_flags8_t;
+
+
+/**
+* @typedef  byte_t
+* @brief  Byte type
+*/
+typedef uint8_t        byte_t;
+
+
+/**
+* @typedef  ssize_t
+* @brief  Signed size type. This is a POSIX specification.
+*/
+#if ! defined( __GNUC__ )  ||  defined( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+typedef int  ssize_t;
+#endif
+
+
+/***********************************************************************
+* Section: Global
+************************************************************************/
+/* Start of a part of CMSIS : Copy from cmsys_os.h */
+/* This is for not calling CMSIS function */
+
+
+/**
+* @typedef  osMailQId
+* @brief  osMailQId
+*/
+#ifdef IS_CMSIS_USED
+typedef void *osMailQId;
+#endif
+
+
+/**
+* @struct  r_ospl_rtx_osMailQDef_t
+* @brief  RTX:osMailQDef_t
+*/
+#ifdef IS_CMSIS_USED
+typedef struct r_ospl_rtx_os_mailQ_def  {
+    uint32_t                queue_sz;    ///< number of elements in the queue
+    uint32_t                 item_sz;    ///< size of an item
+    void                       *pool;    ///< memory array for mail
+} r_ospl_rtx_osMailQDef_t;
+#endif
+
+
+/* Section: Global */
+/**
+* @def  r_ospl_rtx_osMailQDef
+* @brief  RTX:osMailQDef
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifdef IS_CMSIS_USED
+#if defined (osObjectsExternal)  // object is external
+#define r_ospl_rtx_osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define r_ospl_rtx_osMailQDef(name, queue_sz, type) \
+uint32_t os_mailQ_q_##name[4+(queue_sz)] = { 0 }; \
+uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \
+void *   os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \
+const r_ospl_rtx_osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof(type), (os_mailQ_p_##name) }
+#endif
+#endif
+
+
+/**
+* @def  osMailQ
+* @brief  osMailQ
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifdef IS_CMSIS_USED
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+#endif
+
+
+/***********************************************************************
+*  Section: Global
+************************************************************************/
+/* End of a part of CMSIS */
+
+
+/**
+* @struct  r_ospl_thread_id_t
+* @brief  Pointer to a thread
+*/
+#ifdef IS_CMSIS_USED
+typedef void * /*<r_ospl_thread_def_t*>*/  r_ospl_thread_id_t;
+#define  R_OSPL_THREAD_INTERRUPT  ((void*) 0 )
+#endif
+
+
+/* Section: Global */
+/**
+* @brief   The function type of interrupt callback
+*
+* @param   InterruptSource Source of interrupt
+* @param   Caller Driver's internal parameters about interrupt operations
+* @return  Error code.  If there is no error, the return value is 0. The value set to "r_ospl_async_t::ReturnValue"
+*
+* @par Description
+*    This is type of the interrupt callback function running in the
+*    interrupt context and called from the interrupt handler.
+*
+*    It is possible to replace to application defined interrupt callback function
+*    by setting to "r_ospl_async_t::InterruptCallback". But it is usually not
+*    necessary to replace.
+*
+*    As interrupt callback function, the default interrupt callback function
+*    provided from the driver is used. It is unusual to use application defined
+*    interrupt callback function.
+*    Write the response code of the interrupt (event driven code) next to the
+*    code calling @ref R_OSPL_EVENT_Wait function
+*
+*    Whether the asynchronous operation was ended is possible to know whether
+*    the variable of "r_ospl_async_state_t" type referred from
+*    @ref R_DRIVER_GetAsyncStatus function is set to @ref R_OSPL_RUNNABLE value.
+*
+*    It is not necessary to write the code of interrupt return (IRET) in
+*    the interrupt callback function. The interrupt handlers calling interrupt
+*    callback function calls IRET, if necessary.
+*
+*    It is not possible to divide interrupt callback functions by the kind of
+*    interrupt. Alternatively, it is possible to write operations in interrupt
+*    handlers calling interrupt callback function in porting layer under the driver.
+*    There are interrupt handlers by each interrupt numbers.
+*
+*    It is possible to signal any event from application defined interrupt
+*    @par callback function. But it is necessary to do following operations
+*/
+typedef errnum_t  (* r_ospl_callback_t )( const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller );
+
+
+/**
+* @enum   r_ospl_async_state_t
+* @brief  Asynchronous State
+*
+*    - R_OSPL_UNINITIALIZED - 0
+*    - R_OSPL_RUNNABLE - 1, Runnable or Waitable
+*    - R_OSPL_RUNNING - 2, Running  or Waiting
+*    - R_OSPL_INTERRUPTING - 3
+*    - R_OSPL_INTERRUPTED - 4
+*/
+typedef enum {
+    R_OSPL_UNINITIALIZED = 0,
+    R_OSPL_RUNNABLE,
+    R_OSPL_RUNNING,
+    R_OSPL_INTERRUPTING,
+    R_OSPL_INTERRUPTED
+} r_ospl_async_state_t;
+
+
+/**
+* @enum   r_ospl_async_type_t
+* @brief  Asynchronous State
+*
+*    - R_OSPL_ASYNC_TYPE_NORMAL - 1
+*    - R_OSPL_ASYNC_TYPE_FINALIZE - 2, Asynchronous finalizing
+*/
+typedef enum {
+    R_OSPL_ASYNC_TYPE_NORMAL   = 1,
+    R_OSPL_ASYNC_TYPE_FINALIZE = 2
+} r_ospl_async_type_t;
+
+
+/**
+* @struct  r_ospl_block_t
+* @brief  Block in queue
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+typedef struct st_r_ospl_block_t  r_ospl_block_t;
+struct st_r_ospl_block_t {
+    r_ospl_block_t  *Next;
+};
+
+
+/**
+* @struct  r_ospl_queue_status_t
+* @brief  r_ospl_queue_status_t
+*/
+typedef struct st_r_ospl_queue_status_t {
+
+    /** UsedCount */
+    int_fast32_t  UsedCount;
+
+    /** MaxCount */
+    int_fast32_t  MaxCount;
+} r_ospl_queue_status_t;
+
+
+/**
+* @struct  r_ospl_queue_def_t
+* @brief  r_ospl_queue_def_t
+* @par Description
+*    Member variables should not be accessed.
+*/
+typedef struct st_r_ospl_queue_def_t {
+    osMailQId                       MailQId;
+    r_ospl_queue_status_t           PublicStatus;
+    const r_ospl_rtx_osMailQDef_t  *MailQDef;
+} r_ospl_queue_def_t;
+
+
+/**
+* @struct  r_ospl_queue_t
+* @brief  r_ospl_queue_t
+* @par Description
+*    Member variables should not be accessed.
+*/
+typedef r_ospl_queue_def_t  r_ospl_queue_t;
+
+
+/* Section: Global */
+/**
+* @def  R_OSPL_QUEUE_DEF
+* @brief  Defines attributes of queue and work area.
+* @param   Name Thread name. Do not bracket by ""
+* @param   MaxCount Max count of elements in the queue
+* @param   Type Output
+* @return  None.
+*
+* @par Description
+*    It is not possible to use this macro in the library.
+*    If implement of OSPL was changed, the library must be recompiled.
+*/
+#define  R_OSPL_QUEUE_DEF( Name, MaxCount, Type ) \
+	r_ospl_rtx_osMailQDef( Name, MaxCount, Type ); \
+	r_ospl_queue_def_t  Name##_OSPL_DEF = { NULL, 0, (MaxCount), osMailQ( Name ) }
+
+
+/**
+* @def  R_OSPL_QUEUE
+* @brief  Returns initial attributes of queue and work area.
+* @param   Name Queue's name. Do not bracket by ""
+* @return  None.
+*
+* @par Description
+*    It is not possible to use this macro in the library.
+*    If implement of OSPL was changed, the library must be recompiled.
+*/
+#define  R_OSPL_QUEUE( Name )  (&Name##_OSPL_DEF)
+
+
+/**
+* @typedef  r_ospl_flush_t
+* @brief  r_ospl_flush_t
+*/
+typedef bit_flags_fast32_t  r_ospl_flush_t;
+#define  /*<uint_fast32_t>*/  R_OSPL_FLUSH_INVALIDATE                0u
+#define  /*<uint_fast32_t>*/  R_OSPL_FLUSH_WRITEBACK_INVALIDATE      2u
+#define  /*<uint_fast32_t>*/  R_OSPL_FLUSH_WRITEBACK_INVALIDATE_2ND  8u
+
+
+/**
+* @struct  r_ospl_flag32_t
+* @brief  This is the type of flags having 32bit
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+struct st_r_ospl_flag32_t {
+    volatile uint32_t  Flags;
+};
+
+
+/**
+* @struct  r_ospl_interrupt_t
+* @brief  Structure related to interrupt source. e.g. interrupt number
+*/
+struct st_r_ospl_interrupt_t {
+
+    /** <bsp_int_src_t> */
+    bsp_int_src_t  IRQ_Num;
+
+    /** ChannelNum */
+    int_fast32_t   ChannelNum;
+
+    /** Type */
+    int_fast32_t   Type;
+
+    /** Delegate */
+    void  *Delegate;
+};
+
+
+/**
+* @struct  r_ospl_async_status_t
+* @brief  Structure of driver's status and interrupt status defined by OSPL
+*/
+struct st_r_ospl_async_status_t {
+
+    /** <r_ospl_async_state_t> */
+    volatile r_ospl_async_state_t  State;
+
+    /** IsEnabledInterrupt */
+    volatile bool_t  IsEnabledInterrupt;
+
+    /** InterruptEnables */
+    volatile r_ospl_flag32_t  InterruptEnables;
+
+    /** InterruptFlags */
+    volatile r_ospl_flag32_t  InterruptFlags;
+
+    /** r_ospl_flag32_t < <r_ospl_cancel_flag_t> > */
+    volatile r_ospl_flag32_t  CancelFlags;  /*<r_ospl_cancel_flag_t>*/
+#if  R_OSPL_IS_PREEMPTION
+    union {
+
+        /** LockOwner */
+        volatile r_ospl_thread_id_t  Thread;
+
+        /** LockOwner */
+        volatile void  *Context;
+    } LockOwner;
+#endif
+};
+
+
+/**
+* @struct  r_ospl_async_t
+* @brief  Setting of notifications
+*/
+struct st_r_ospl_async_t {
+
+    /** Flags */
+    bit_flags_fast32_t  Flags;
+
+    /** Delegate */
+    void  *Delegate;
+
+    /** A_Thread */
+    r_ospl_thread_id_t  A_Thread;
+
+    /** A_EventValue */
+    uint32_t  A_EventValue;  /* QAC 4130 */
+
+    /** I_Thread */
+    r_ospl_thread_id_t  I_Thread;
+
+    /** I_EventValue */
+    uint32_t  I_EventValue;  /* QAC 4130 */
+
+    /** InterruptCallback */
+    r_ospl_callback_t  InterruptCallback;
+
+    /** ReturnValue */
+    errnum_t  ReturnValue;
+};
+
+enum {
+    R_F_OSPL_A_Thread          = 0x0001,
+    R_F_OSPL_A_EventValue      = 0x0002,
+    R_F_OSPL_I_Thread          = 0x0004,
+    R_F_OSPL_I_EventValue      = 0x0008,
+    R_F_OSPL_InterruptCallback = 0x0010,
+    R_F_OSPL_Delegate          = 0x0080
+};
+
+
+/* Section: Global */
+/***********************************************************************
+* Macros: r_ospl_internal_sentinel
+*
+*    : R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK  - 0x7FFFFF40
+*    : R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE - 0x4A5C0000
+************************************************************************/
+#ifndef R_OSPL_NDEBUG
+enum {
+    R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK  = 0x7FFFFF40,
+    R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE = 0x4A5C0000
+};
+#endif
+
+
+/**
+* @struct  r_ospl_caller_t
+* @brief  Context of interrupt callback function caller
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+struct st_r_ospl_caller_t {
+    r_ospl_async_t                *Async;
+    volatile int_fast32_t         *PointerToState;
+    int_fast32_t                   StateValueOfOnInterrupting;
+    void                          *I_Lock;
+    const r_ospl_i_lock_vtable_t  *I_LockVTable;
+};
+
+
+/***********************************************************************
+* Class: r_ospl_i_lock_vtable_t
+*    I-Lock V-Table
+************************************************************************/
+typedef bool_t (* r_ospl_i_lock_lock_func_t )( void *const  self_ );
+typedef void   (* r_ospl_i_lock_unlock_func_t )( void *const  self_ );
+typedef void   (* r_ospl_i_lock_get_rf_func_t )( void *const  self_ );    /* rf = RequestFinalize */
+typedef bool_t (* r_ospl_i_lock_get_rcn_func_t )( const void *const  self_ );   /* rcn = RootChannelNum */
+
+struct st_r_ospl_i_lock_vtable_t {
+
+    /**
+    * @brief   Lock
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    bool_t  (* Lock )( void *const  self_ );
+
+    /**
+    * @brief   Unlock
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    void    (* Unlock )( void *const  self_ );
+
+    /**
+    * @brief   RequestFinalize
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    void    (* RequestFinalize )( void *const  self_ );
+
+    /**
+    * @brief   GetRootChannelNum
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    int_fast32_t  (* GetRootChannelNum )( const void *const  self_ );
+};
+
+
+/**
+* @struct  r_ospl_memory_spec_t
+* @brief  Memory specification
+*/
+struct st_r_ospl_memory_spec_t {
+
+    /** (byte) */
+    uint_fast32_t  CacheLineSize;
+};
+
+
+/**
+* @struct  r_ospl_ftimer_spec_t
+* @brief  Free run timer specification
+*/
+struct st_r_ospl_ftimer_spec_t {
+
+    /** msec_Numerator */
+    uint32_t  msec_Numerator;
+
+    /** msec_Denominator */
+    uint32_t  msec_Denominator;
+
+    /** MaxCount */
+    uint32_t  MaxCount;
+
+    /** ExtensionOfCount */
+    uint32_t  ExtensionOfCount;
+};
+
+
+/**
+* @struct  r_ospl_table_t
+* @brief  Index table
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+struct st_r_ospl_table_t {
+    void         *Area;
+    int_fast32_t  Count;
+    int_fast32_t  MaxCount;
+    const void   *KeyCache;
+    int_fast32_t  IndexCache;  /* Not SortedKeyIndex */
+    int16_t       FirstFreeIndex;
+#if R_OSPL_IS_PREEMPTION
+    bool_t        Is_T_Lock;
+#endif
+};
+
+
+/* Section: Global */
+/**
+* @enum   r_ospl_if_not_t
+* @brief  Operation if not exists
+*
+*    - R_OSPL_ERROR_IF_NOT - 0
+*    - R_OSPL_ALLOCATE_IF_NOT - 1
+*    - R_OSPL_DO_NOTHING_IF_NOT - 2
+*/
+typedef enum {
+    R_OSPL_ERROR_IF_NOT      = 0,
+    R_OSPL_ALLOCATE_IF_NOT   = 1,
+    R_OSPL_DO_NOTHING_IF_NOT = 2
+} r_ospl_if_not_t;
+
+
+/**
+* @struct  r_ospl_error_t
+* @brief  Error status of a thread
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+typedef  struct st_r_ospl_error_t  r_ospl_error_t;
+struct st_r_ospl_error_t {
+#if R_OSPL_ERROR_BREAK
+    bool_t         IsError;
+    int_fast32_t   ErrorID;
+    const char_t  *FilePath;
+    int_fast32_t   LineNum;
+#if R_OSPL_IS_PREEMPTION
+    int_fast32_t   ThreadLockedCount;
+#endif
+#endif
+#if R_OSPL_TLS_ERROR_CODE
+    errnum_t       ErrNum;
+#endif
+};
+#endif
+
+
+/**
+* @struct  r_ospl_global_error_t
+* @brief  Error status of global
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+typedef  struct st_r_ospl_global_error_t  r_ospl_global_error_t;
+struct st_r_ospl_global_error_t {
+    r_ospl_table_t   ThreadIndexTable;
+    r_ospl_error_t  *ErrorArray;
+
+#if R_OSPL_ERROR_BREAK
+    int_fast32_t     RaisedGlobalErrorID;
+    int_fast32_t     BreakGlobalErrorID;
+#endif
+};
+#endif
+
+
+/* Section: Global */
+/**
+* @enum   r_ospl_axi_cache_attribute_t
+* @brief  Cache attribute on AXI bus.
+*
+*    - R_OSPL_AXI_CACHE_ZERO - Not AXI
+*    - R_OSPL_AXI_STRONGLY - Strongly order access
+*    - R_OSPL_AXI_DEVICE - DEVICE
+*    - R_OSPL_AXI_UNCACHED - Normal access (Out of order) uncached
+*    - R_OSPL_AXI_WRITE_BACK_W - Write back, allocate on write
+*    - R_OSPL_AXI_WRITE_BACK - Write back, allocate on both read and write
+*/
+typedef enum {
+    R_OSPL_AXI_CACHE_ZERO     =  0,
+    R_OSPL_AXI_STRONGLY       =  0,
+    R_OSPL_AXI_DEVICE         =  1,
+    R_OSPL_AXI_UNCACHED       =  3,
+    R_OSPL_AXI_WRITE_BACK_W   = 11,
+    R_OSPL_AXI_WRITE_BACK     = 15
+} r_ospl_axi_cache_attribute_t;
+
+
+/**
+* @enum   r_ospl_axi_protection_t
+* @brief  Protection on AXI bus.
+*
+*    - R_OSPL_AXI_PROTECTION_ZERO - Not AXI
+*    - R_OSPL_AXI_SECURE - TrustZone secure acccess
+*    - R_OSPL_AXI_NON_SECURE - TrustZone non-secure acccess
+*/
+typedef enum {
+    R_OSPL_AXI_PROTECTION_ZERO = 0,
+    R_OSPL_AXI_SECURE          = 0,
+    R_OSPL_AXI_NON_SECURE      = 2
+} r_ospl_axi_protection_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @enum   Event_Bit_Name
+* @brief  Event_Bit_Name
+*    - R_OSPL_ANY_FLAG - 0x0000
+*    - R_OSPL_A_FLAG - 0x0001
+*    - R_OSPL_I_FLAG - 0x0002
+*    - R_OSPL_FINAL_A_FLAG - 0x0004
+*/
+enum {
+    R_OSPL_ANY_FLAG         = 0x00000000,
+    R_OSPL_A_FLAG           = 0x00000001,
+    R_OSPL_I_FLAG           = 0x00000002,
+    R_OSPL_FINAL_A_FLAG     = 0x00000004
+};
+
+
+/**
+* @typedef  r_ospl_cancel_flag_t
+* @brief  Bit flags of <r_ospl_cancel_bit_t>
+*/
+typedef int_t  r_ospl_cancel_flag_t;
+
+
+/**
+* @enum   r_ospl_cancel_bit_t
+* @brief  r_ospl_cancel_bit_t
+*    - R_OSPL_CANNEL_REQUEST - 0x0001
+*    - R_OSPL_CANNELING - 0x0002
+*    - R_OSPL_CANNELED - 0x0004
+*    - R_OSPL_FINALIZE_REQUEST - 0x0010
+*    - R_OSPL_FINALIZING - 0x0020
+*    - R_OSPL_FINALIZED - 0x0040
+*/
+enum {
+    R_OSPL_CANNEL_REQUEST   = 0x00000001,
+    R_OSPL_CANNELING        = 0x00000002,
+    R_OSPL_CANNELED         = 0x00000004,
+    R_OSPL_FINALIZE_REQUEST = 0x00000010,
+    R_OSPL_FINALIZING       = 0x00000020,
+    R_OSPL_FINALIZED        = 0x00000040
+};
+
+
+/***********************************************************************
+* Macros: OSPL_Others
+*
+*    : R_OSPL_INFINITE         - One of time out value
+*    : R_OSPL_FLAG32_ALL_BITS  - R_OSPL_FLAG32_ALL_BITS
+*    : R_OSPL_EVENT_ALL_BITS   - R_OSPL_EVENT_ALL_BITS
+*    : R_OSPL_TIMEOUT          - Raised time out
+*    : R_OSPL_MAX_TIME_OUT     - Max value of time out
+*    : R_OSPL_NO_INDEX         - R_OSPL_NO_INDEX
+*    : R_OSPL_UNLOCKED_CHANNEL - R_OSPL_UNLOCKED_CHANNEL
+************************************************************************/
+#define R_OSPL_INFINITE           0xFFFFFFFFu   /* uint32_t */
+#define R_OSPL_FLAG32_ALL_BITS    0xFFFFFFFFu   /* uint32_t */
+enum {  R_OSPL_EVENT_ALL_BITS   = 0x0000FFFF };
+enum {  R_OSPL_TIMEOUT          = 0x40000000 };
+enum {  R_OSPL_MAX_TIME_OUT     = 65533 };
+enum {  R_OSPL_NO_INDEX         = -1         };
+enum {  R_OSPL_UNLOCKED_CHANNEL = 0x00000FEE };
+
+
+/**
+* @def  R_OSPL_TABLE_SIZE
+* @brief  Calculates the size of <r_ospl_table_t> type index table
+* @param   MaxCount Max index count
+* @return  Table size
+*/
+/* ->MISRA 19.7 : Array count must const */ /* ->SEC M5.1.3 */
+#define  R_OSPL_TABLE_1_SIZE  8  /* sizeof(r_ospl_table_block_t) */
+#define  R_OSPL_TABLE_SIZE( MaxCount ) \
+	( (MaxCount) * R_OSPL_TABLE_1_SIZE )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @def  R_OSPL_DEBUG_WORK_SIZE
+* @brief  Calculates the size of debug work area
+* @param   ThreadMaxCount Max thread count using error breaking system of OSPL
+* @return  Size of debug work area
+*/
+/* ->MISRA 19.7 : Array count must const */ /* ->SEC M5.1.3 */
+#define  R_OSPL_DEBUG_WORK_1_SIZE  32  /* sizeof(r_ospl_table_block_t) + sizeof(r_ospl_error_t) */
+#define  R_OSPL_DEBUG_WORK_SIZE( ThreadMaxCount ) \
+	( (ThreadMaxCount) * R_OSPL_DEBUG_WORK_1_SIZE )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @enum   errnum_t
+* @brief  Error code defined by OSPL
+*
+*    - E_OTHERS - 0x01
+*    - E_FEW_ARRAY - 0x02
+*    - E_FEW_MEMORY - 0x03
+*    - E_FIFO_OVER - 0x04
+*    - E_NOT_FOUND_SYMBOL - 0x05
+*    - E_NO_NEXT - 0x06
+*    - E_ACCESS_DENIED - 0x07
+*    - E_NOT_IMPLEMENT_YET - 0x09
+*    - E_ERRNO - 0x0E
+*    - E_LIMITATION - 0x0F
+*    - E_STATE - 0x10
+*    - E_NOT_THREAD - 0x11
+*    - E_PATH_NOT_FOUND - 0x12
+*    - E_BAD_COMMAND_ID - 0x16
+*    - E_TIME_OUT - 0x17
+*    - E_NO_DEBUG_TLS - 0x1D
+*    - E_EXIT_TEST - 0x1E
+*/
+#define  E_CATEGORY_MASK   0xFFFFFFE0u  /* E_CATEGORY_* */
+enum {   E_OFFSET_MASK   = 0x0000001F };
+
+#ifndef  E_CATEGORY_COMMON  /* Overwritable */
+#define  E_CATEGORY_COMMON  E_CATEGORY_COMMON
+enum { E_CATEGORY_COMMON = 0x00000000 };  /* 0x01, 0x02 .. 0x1F : Reseved */
+#endif
+
+enum { E_OTHERS             = E_CATEGORY_COMMON | 0x01 }; /*  1 */
+enum { E_FEW_ARRAY          = E_CATEGORY_COMMON | 0x02 }; /*  2 */
+enum { E_FEW_MEMORY         = E_CATEGORY_COMMON | 0x03 }; /*  3 */
+enum { E_FIFO_OVER          = E_CATEGORY_COMMON | 0x04 }; /*  4 */
+enum { E_NOT_FOUND_SYMBOL   = E_CATEGORY_COMMON | 0x05 }; /*  5 */
+enum { E_NO_NEXT            = E_CATEGORY_COMMON | 0x06 }; /*  6 */
+enum { E_ACCESS_DENIED      = E_CATEGORY_COMMON | 0x07 }; /*  7 */
+enum { E_NOT_IMPLEMENT_YET  = E_CATEGORY_COMMON | 0x09 }; /*  9 */
+enum { E_ERRNO              = E_CATEGORY_COMMON | 0x0E }; /* 14 */
+enum { E_LIMITATION         = E_CATEGORY_COMMON | 0x0F }; /* 15 */
+enum { E_STATE              = E_CATEGORY_COMMON | 0x10 }; /* 16 */
+enum { E_NOT_THREAD         = E_CATEGORY_COMMON | 0x11 }; /* 17 */
+enum { E_PATH_NOT_FOUND     = E_CATEGORY_COMMON | 0x12 }; /* 18 */
+enum { E_BAD_COMMAND_ID     = E_CATEGORY_COMMON | 0x16 }; /* 22 */
+enum { E_TIME_OUT           = E_CATEGORY_COMMON | 0x17 }; /* 23 */
+enum { E_NO_DEBUG_TLS       = E_CATEGORY_COMMON | 0x1D }; /* 29 */
+enum { E_EXIT_TEST          = E_CATEGORY_COMMON | 0x1E }; /* 30 */
+
+
+/**
+* @def  R_JOIN_SYMBOL_FOR_ASSERT
+* @brief  Sub routine of <R_STATIC_ASSERT>
+* @par Parameters
+*    None
+* @return  None.
+*
+* - This macro extends "x", "y"
+* - This code is referenced by CERT secure coding standard PRE05-C
+*/
+/* ->MISRA 19.7 : Extend macro arguments */ /* ->SEC M5.1.3 */
+#define R_JOIN_SYMBOL_FOR_ASSERT(x, y)  R_JOIN_SYMBOL_FOR_ASSERT_SUB(x, y)
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->MISRA 19.13 : This is used only assertion in compiling */ /* ->SEC M5.1.2 (1) */
+#define R_JOIN_SYMBOL_FOR_ASSERT_SUB(x, y) x##y
+/* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @def  R_STATIC_ASSERT
+* @brief  "static_assert" for in function
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    Compatible with static_assert (C++0x). But our naming rule is not match.
+*    - This code is referenced by CERT secure coding standard DCL03 - C.
+*    This macro raised QAC warning 3205. This is no problem.
+*/
+/* ->SEC M1.1.1 */
+#define  R_STATIC_ASSERT( ConstantExpression, StringLiteral ) \
+	do { typedef char_t R_JOIN_SYMBOL_FOR_ASSERT( assertion_failed_t_, __LINE__ ) \
+		[(ConstantExpression) ? 1 : -1]; } while(0)
+/* If "ConstantExpression" is false, illegal array size error will be raised. */
+/* <-SEC M1.1.1 */
+
+
+/**
+* @def  R_STATIC_ASSERT_GLOBAL
+* @brief  "static_assert" for in global scope
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->SEC M1.1.1 */
+/* ->MISRA 19.4 : There is not if statement in global */ /* ->SEC M1.8.2 */
+/* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#define  R_STATIC_ASSERT_GLOBAL( ConstantExpression, StringLiteral ) \
+	     typedef char_t R_JOIN_SYMBOL_FOR_ASSERT( assertion_failed_t_, __LINE__ ) \
+		[(ConstantExpression) ? 1 : -1]
+/* If "ConstantExpression" is false, illegal array size error will be raised. */
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+/* <-SEC M1.1.1 */
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "r_ospl.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/inc/r_static_an_tag.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,376 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_static_an_tag.h
+* @brief   Reviewed tag for warnings of static code analysis.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_STATIC_AN_TAG_H
+#define R_STATIC_AN_TAG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "r_multi_compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/***********************************************************************
+* Macros: IS
+*    Changes the code accepted with MISRA 13.2 to readable
+*
+* Arguments:
+*    bool_value - The expression that evaluated result becomes boolean type
+*
+* Return Value:
+*    Evaluate result of "bool_value != 0".
+*
+* Description:
+*   Avoid "not 0" as double negation.
+*   "IS" macro corresponds to cast to boolean type specified in the language.
+*
+*   This is for QAC warning : MISRA 13.2 Advice : Tests of a value against
+*   zero should be made explicit, unless the operand is effectively Boolean.
+*
+*   Write this macro after being warned by static code analyzer.
+*
+* Example:
+*    > if ( IS( bool_value ) ) {...}
+*    > if ( IS( bool_value ) && IS( bool_value2 ) && ! bool_value3 ) {...}
+*    > if ( IS( unsigned_bitfield ) ) {...}
+*    > bool_t is_flag = (bool_t) unsigned_bitfield;  ("IS" is not used)
+************************************************************************/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#if ! R_BOOL_IS_SIGNED
+#define  IS( bool_value )  ( (bool_t)( bool_value ) != 0u )
+#else
+#define  IS( bool_value )  ( (bool_t)( bool_value ) != 0 )
+#endif
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+#if 0
+/* Comment out because if checking type function(this) was called, raises SEC R3.6.2(QAC 3441) */
+#define  IS( bool_value )  ( IS_Sub( bool_value ) != 0 )
+INLINE bool_t  IS_Sub( bool_t const  value )   /* Check type only */
+{
+    return  value;
+}
+#endif
+
+
+/***********************************************************************
+* Macros: IF_DQ
+*    Error check on DEBUG and QAC version for faster
+************************************************************************/
+/* ->MISRA 19.4 : Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#if defined(__QAC_ARM_H__)
+#define  IF_DQ  if
+#else
+#define  IF_DQ  IF_D
+#endif
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+
+/***********************************************************************
+* Macros: IF_DS
+*    Error check on DEBUG and QAC version for always false
+*
+* Description:
+*    QAC assist tool founds IF_DS keyword.
+*    Sentence using this expects IPA SEC O4.1, O1.1.
+************************************************************************/
+#define  IF_DS  IF_DQ
+
+
+/***********************************************************************
+* Macros: IF_S
+*    Error check on QAC version for always false
+*
+* Description:
+*    QAC assist tool founds IF_S keyword.
+*    Compiler always does not check it.
+************************************************************************/
+/* ->MISRA 19.4 : Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#if defined(__QAC_ARM_H__)
+#define  IF_S               if
+#else
+#define  IF_S( Condition )  if ( false )
+#endif
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+
+/**
+* @def  R_CUT_IF_ALWAYS
+* @brief  Whether a expression always true/false was cut or not.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value is 0 or 1.
+*    This macro is for @ref R_CUT_IF_ALWAYS_TRUE and @ref R_CUT_IF_ALWAYS_FALSE.
+*/
+#ifndef  R_CUT_IF_ALWAYS
+#if defined(__QAC_ARM_H__)
+#define  R_CUT_IF_ALWAYS  0
+#else
+#define  R_CUT_IF_ALWAYS  1
+#endif
+#endif
+
+
+/**
+* @def  R_CUT_IF_ALWAYS_TRUE
+* @brief  Assertion that the expression is always true
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_CUT_IF_ALWAYS
+#define  R_CUT_IF_ALWAYS_TRUE( expression_and )
+#else
+/* ->MISRA 19.10 : Can not in ( ). e.g. expression_and = " a >= 0  &&" */
+#define  R_CUT_IF_ALWAYS_TRUE( expression_and )  expression_and
+/* <-MISRA 19.10 */
+#endif
+
+
+/**
+* @def  R_CUT_IF_ALWAYS_FALSE
+* @brief  Assertion that the expression is always false
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_CUT_IF_ALWAYS
+#define  R_CUT_IF_ALWAYS_FALSE( expression_or )
+#else
+/* ->MISRA 19.10 : Can not in ( ). e.g. expression_and = " a >= 0  &&" */
+#define  R_CUT_IF_ALWAYS_FALSE( expression_or )  expression_or
+/* <-MISRA 19.10 */
+#endif
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE( a1 )  R_UNREFERENCED_VARIABLE_Sub( &(a1) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_Sub( volatile const void *a1 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE_2
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE_2( a1,a2 )  R_UNREFERENCED_VARIABLE_2_Sub( &(a1), &(a2) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_2_Sub( volatile const void *a1, volatile const void *a2 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE_3
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE_3( a1,a2,a3 )  R_UNREFERENCED_VARIABLE_3_Sub( &(a1), &(a2), &(a3) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_3_Sub( volatile const void *a1, volatile const void *a2,
+        volatile const void *a3 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE_4
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE_4( a1,a2,a3,a4 )  R_UNREFERENCED_VARIABLE_4_Sub( &(a1), &(a2), &(a3), &(a4) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_4_Sub( volatile const void *a1, volatile const void *a2,
+        volatile const void *a3, volatile const void *a4 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_IT_WILL_BE_NOT_CONST
+* @brief  variable WILL_BE_NOT_CONST
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids MISRA 16.7 advisory and SEC M1.11.1 for not modified API argument
+*    will be not const future.
+*/
+/* ->MISRA 16.7 */ /* ->SEC M1.11.1 : Tell to QAC/compiler that "*Pointer" was changed */
+INLINE void  R_IT_WILL_BE_NOT_CONST( void *Pointer );  /* MISRA 8.1 Advice */
+INLINE void  R_IT_WILL_BE_NOT_CONST( void *Pointer )
+{
+    R_UNREFERENCED_VARIABLE( Pointer );
+}
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+
+
+/**
+* @def  R_AVOID_UNSAFE_ALWAYS_WARNING
+* @brief  Specifies the code cannot be cut.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoid MISRA 13.7 require always true/false condition.
+*    This tells to QAC/compiler that "Variable" was changed.
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_AVOID_UNSAFE_ALWAYS_WARNING( Variable ) \
+	R_AVOID_UNSAFE_ALWAYS_WARNING_SUB( &(Variable) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->MISRA 16.7 : Tell to QAC/compiler that "Variable" was changed */ /* ->SEC M1.11.1 */
+INLINE void  R_AVOID_UNSAFE_ALWAYS_WARNING_SUB( void *Pointer );  /* MISRA 8.1 Advice */
+INLINE void  R_AVOID_UNSAFE_ALWAYS_WARNING_SUB( void *Pointer )
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+{
+    R_UNREFERENCED_VARIABLE( Pointer );
+}
+
+
+/**
+* @def  TO_UNSIGNED
+* @brief  Cast to unsigned type constant value
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->MISRA 19.7 : It is not able to replace to function because this expands macro's parameter */
+/* ->SEC M5.1.3 */
+#define  TO_UNSIGNED(x)  TO_UNSIGNED_AGAIN(x)  /* Expand "x" */
+/* <-MISRA 19.7 */
+/* <-SEC M5.1.3 */
+
+/* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  TO_UNSIGNED_AGAIN(x)  (x##u)
+/* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Cast to unsigned type constant value
+*
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This can not avoid QAC warning. This macro is for count reviewed code automatically.
+*/
+INLINE uint32_t  R_ToUnsigned( int32_t const  ConstantInteger )
+{
+    return  (uint32_t) ConstantInteger;
+}
+
+
+/**
+* @brief   Cast to signed type constant value
+*
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This can not avoid QAC warning. This macro is for count reviewed code automatically.
+*/
+INLINE int32_t  R_ToSigned( uint32_t const  ConstantInteger )
+{
+    return  (int32_t) ConstantInteger;
+}
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_STATIC_AN_TAG_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/DebugBreak.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  DebugBreak.c
+* @brief   General Break Point
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#ifndef  R_OSPL_NDEBUG
+#include  <stdio.h>
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_DebugBreak
+************************************************************************/
+void  R_DebugBreak( const char_t *const  File, int_fast32_t const  Line )
+{
+#ifndef  R_OSPL_NDEBUG
+    if ( File == NULL ) {
+        printf( "in R_DebugBreak errnum_t:0x%X\n", Line );
+    } else {
+        printf( "in R_DebugBreak (%d) %s\n", Line, File );
+    }
+#else
+    R_UNREFERENCED_VARIABLE_2( File, Line );
+#endif
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/TOOLCHAIN_ARM/r_ospl_os_less_asm.S	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,151 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* $FileName: r_ospl_os_less_asm.s $
+;* $Module: OSPL $ $PublicVersion: 0.84 $ (=R_OSPL_VERSION)
+;* $Rev: 35 $
+;* $Date:: 2014-04-15 21:38:18 +0900#$
+;* Description : OS Porting Layer API
+;******************************************************************************/
+
+
+	AREA    |.text|, CODE, READONLY
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_Flush_Sub]
+;* Description  :
+;* Arguments    : None
+;* Return Value : None
+;******************************************************************************/
+
+	EXPORT  R_OSPL_MEMORY_Flush_Sub
+
+R_OSPL_MEMORY_Flush_Sub    FUNCTION
+
+	ARM
+
+	PUSH    {r4-r7}
+
+	MRC     p15, 1, r7, c0, c0, 1   ;// r7 = p15(CLIDR);  // [r4] CLIDR(LoC) * 2  // LoC: level of coherency
+	MOV     r4, r7, LSR #23         ;// r4 = r7 >> 23;    //   :
+	ANDS    r4, r4, #0xE            ;// r4 &= 0xE;        //   :
+	BEQ     Fin                     ;// if ( r4 == 0 ) goto Fin;  // if LoC == 0, no need to clean
+
+	MOV     r3, #0                  ;// for ( r3 = 0;  r3 < r4;  r3 += 2 ) { // [r3]: current_cache_level * 2
+Loop1
+	ADD     r2, r3, r3, LSR #1      ;// r2 = r3 + (r3 >> 1);  // r2 = current_cache_level * 3
+	MOV     r0, r7, LSR r2          ;// r0 = (r7 >> r2);  // r0 = CLIDR(Ctype#)
+	AND     r0, r0, #7              ;// r0 &= 7;          //  :
+	CMP     r0, #2                  ;// if ( r0 < 2 ) goto Continue1;
+	BLT     Continue1               ;//  :        // If no cache or only instruction cache at this level
+
+	MCR     p15, 2, r3, c0, c0, 0   ;// p15(CSSELR) = r3;    // CSSELR: Cache Size Selection Register
+	ISB                             ;// Guarantee MCR operation
+	MRC     p15, 1, r0, c0, c0, 0   ;// r0 = p15(CCSIDR);    // CCSIDR: Cache Size ID Registers
+	AND     r6, r0, #7              ;// r6 = r0 & 7;         // CCSIDR(LineSize): log2(cache_line_byte)-4
+	ADD     r6, r6, #4              ;// r6 += 4;             // [r6] log2(cache_line_byte)
+	LDR     r7, =0x3FF              ;// r7 = 0x3FF;          // [r7] CCSIDR(Associativity): associativity_value - 1
+	AND     r7, r7, r0, LSR #3      ;// r7 = r7 & r0 >> 3;   //   :
+	CLZ     r5, r7                  ;// r5 = CLZ( r7 );      // [r5] log2(WaySize), if exponential 2
+	LDR     r2, =0x7FFF             ;// r2 = 0x7FFF;         // CCSIDR(NumSets) : max number of the index size - 1
+	AND     r2, r2, r0, LSR #13     ;// r2 = r2 & r0 >> 13;  //  :
+	                                ;// for ( /*r2*/;   r2 >= 0;  r2 -= 1 ) {  // [r2] Set number
+Loop2
+	MOV     r1, r7                  ;// for ( r1 = r7;  r1 >= 0;  r1 -= 1 ) {  // [r1] Way number
+Loop3
+	ORR     r0, r3, r1, LSL r5      ;//     r0 = r3 | (r1 << r5)
+	ORR     r0, r0, r2, LSL r6      ;//             | (r2 << r6);
+	MCR     p15, 0, r0, c7, c14, 2  ;//     p15(DCCISW) = r0;  // Clean(WriteBack) and Invalidate
+	SUBS    r1, r1, #1              ;// }  /* End of r1 loop */
+	BGE     Loop3                   ;//  :
+	SUBS    r2, r2, #1              ;// }  /* End of r2 loop */
+	BGE     Loop2                   ;//  :
+Continue1
+	ADD     r3, r3, #2              ;// }  /* End of r3 loop */
+	CMP     r4, r3                  ;//  :
+	BGT     Loop1                   ;//  :
+
+Fin
+	DSB
+	POP    {r4-r7}
+	BX     lr
+
+	ENDFUNC
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_GetCacheLineSize]
+;* Description  :
+;* Arguments    : None
+;* Return Value : None
+;******************************************************************************/
+
+	EXPORT  R_OSPL_MEMORY_GetCacheLineSize
+
+R_OSPL_MEMORY_GetCacheLineSize    FUNCTION
+
+	ARM
+
+	MRC     p15, 1, r0, c0, c0, 0   ;// r0 = p15(CCSIDR);    // CCSIDR: Cache Size ID Registers
+	AND     r0, r0, #7              ;// r0 = r0 & 7;         // CCSIDR.LineSize: log2(cache_line_byte)-4
+	ADD     r0, r0, #4              ;// r0 += 4;             //
+	MOV     r1, #1                  ;// r0 = 1 << r0;        // [r0] cache_line_byte
+	MOV     r0, r1, LSL r0          ;    :
+
+	BX     lr
+
+	ENDFUNC
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_RangeFlush_Sub]
+;* Description  :
+;* Arguments    : r0: Start address
+;*              : r1: Over address (Last + 1)
+;*              : r2: Cache line size
+;* Return Value : None
+;******************************************************************************/
+
+	EXPORT  R_OSPL_MEMORY_RangeFlush_Sub
+
+R_OSPL_MEMORY_RangeFlush_Sub    FUNCTION
+
+	ARM
+
+Loop
+	CMP     r0, r1                  ;// for ( r0 = r0;  r0 < r1;  r0 += r2 ) {
+	BGE     Fin2                    ;//  :
+	MCR     p15, 0, r0, c7, c6, 1   ;//     p15(DCIMVAC) = r0;  // Invalidate
+	ADD     r0, r0, r2              ;// }
+	B       Loop                    ;//  :
+Fin2
+	DSB
+	BX     lr
+
+	ENDFUNC
+
+	END
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/TOOLCHAIN_GCC/r_ospl_os_less_asm.s	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,140 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* $FileName: r_ospl_os_less_asm.s $
+;* $Module: OSPL $ $PublicVersion: 0.83 $ (=R_OSPL_VERSION)
+;* $Rev: 35 $
+;* $Date:: 2014-04-15 21:38:18 +0900#$
+;* Description : OS Porting Layer API
+;******************************************************************************/
+
+
+@   PRESERVE8
+	.section  .text @, CODE, READONLY
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_Flush_Sub]
+;* Description  :
+;* Arguments    : None
+;* Return Value : None
+;******************************************************************************/
+
+	.global  R_OSPL_MEMORY_Flush_Sub
+
+R_OSPL_MEMORY_Flush_Sub:
+
+	PUSH    {r4-r7}
+
+	MRC     p15, 1, r7, c0, c0, 1   ;// r7 = p15(CLIDR);  // [r4] CLIDR(LoC) * 2  // LoC: level of coherency
+	MOV     r4, r7, LSR #23         ;// r4 = r7 >> 23;    //   :
+	ANDS    r4, r4, #0xE            ;// r4 &= 0xE;        //   :
+	BEQ     Fin                     ;// if ( r4 == 0 ) goto Fin;  // if LoC == 0, no need to clean
+
+	MOV     r3, #0                  ;// for ( r3 = 0;  r3 < r4;  r3 += 2 ) { // [r3]: current_cache_level * 2
+Loop1:
+	ADD     r2, r3, r3, LSR #1      ;// r2 = r3 + (r3 >> 1);  // r2 = current_cache_level * 3
+	MOV     r0, r7, LSR r2          ;// r0 = (r7 >> r2);  // r0 = CLIDR(Ctype#)
+	AND     r0, r0, #7              ;// r0 &= 7;          //  :
+	CMP     r0, #2                  ;// if ( r0 < 2 ) goto Continue1;
+	BLT     Continue1               ;//  :        // If no cache or only instruction cache at this level
+
+	MCR     p15, 2, r3, c0, c0, 0   ;// p15(CSSELR) = r3;    // CSSELR: Cache Size Selection Register
+	ISB                             ;// Guarantee MCR operation
+	MRC     p15, 1, r0, c0, c0, 0   ;// r0 = p15(CCSIDR);    // CCSIDR: Cache Size ID Registers
+	AND     r6, r0, #7              ;// r6 = r0 & 7;         // CCSIDR(LineSize): log2(cache_line_byte)-4
+	ADD     r6, r6, #4              ;// r6 += 4;             // [r6] log2(cache_line_byte)
+	LDR     r7, =0x3FF              ;// r7 = 0x3FF;          // [r7] CCSIDR(Associativity): associativity_value - 1
+	AND     r7, r7, r0, LSR #3      ;// r7 = r7 & r0 >> 3;   //   :
+	CLZ     r5, r7                  ;// r5 = CLZ( r7 );      // [r5] log2(WaySize), if exponential 2
+	LDR     r2, =0x7FFF             ;// r2 = 0x7FFF;         // CCSIDR(NumSets) : max number of the index size - 1
+	AND     r2, r2, r0, LSR #13     ;// r2 = r2 & r0 >> 13;  //  :
+	                                ;// for ( /*r2*/;   r2 >= 0;  r2 -= 1 ) {  // [r2] Set number
+Loop2:
+	MOV     r1, r7                  ;// for ( r1 = r7;  r1 >= 0;  r1 -= 1 ) {  // [r1] Way number
+Loop3:
+	ORR     r0, r3, r1, LSL r5      ;//     r0 = r3 | (r1 << r5)
+	ORR     r0, r0, r2, LSL r6      ;//             | (r2 << r6);
+	MCR     p15, 0, r0, c7, c14, 2  ;//     p15(DCCISW) = r0;  // Clean(WriteBack) and Invalidate
+	SUBS    r1, r1, #1              ;// }  /* End of r1 loop */
+	BGE     Loop3                   ;//  :
+	SUBS    r2, r2, #1              ;// }  /* End of r2 loop */
+	BGE     Loop2                   ;//  :
+Continue1:
+	ADD     r3, r3, #2              ;// }  /* End of r3 loop */
+	CMP     r4, r3                  ;//  :
+	BGT     Loop1                   ;//  :
+
+Fin:
+	DSB
+	POP    {r4-r7}
+	BX     lr
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_GetCacheLineSize]
+;* Description  :
+;* Arguments    : None
+;* Return Value : None
+;******************************************************************************/
+
+	.global  R_OSPL_MEMORY_GetCacheLineSize
+
+R_OSPL_MEMORY_GetCacheLineSize:
+
+	MRC     p15, 1, r0, c0, c0, 0   ;// r0 = p15(CCSIDR);    // CCSIDR: Cache Size ID Registers
+	AND     r0, r0, #7              ;// r0 = r0 & 7;         // CCSIDR.LineSize: log2(cache_line_byte)-4
+	ADD     r0, r0, #4              ;// r0 += 4;             //
+	MOV     r1, #1                  ;// r0 = 1 << r0;        // [r0] cache_line_byte
+	MOV     r0, r1, LSL r0          ;//    :
+
+	BX     lr
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_RangeFlush_Sub]
+;* Description  :
+;* Arguments    : r0: Start address
+;*              : r1: Over address (Last + 1)
+;*              : r2: Cache line size
+;* Return Value : None
+;******************************************************************************/
+
+	.global  R_OSPL_MEMORY_RangeFlush_Sub
+
+R_OSPL_MEMORY_RangeFlush_Sub:
+
+Loop:
+	CMP     r0, r1                  ;// for ( r0 = r0;  r0 < r1;  r0 += r2 ) {
+	BGE     Fin2                    ;//  :
+	MCR     p15, 0, r0, c7, c6, 1   ;//     p15(DCIMVAC) = r0;  // Invalidate
+	ADD     r0, r0, r2              ;// }
+	B       Loop                    ;//  :
+Fin2:
+	DSB
+	BX     lr
+
+	.END
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/inline_body.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,41 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  inline_body.c
+* @brief   Body of inline functions
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#define  R_OSPL_MAKE_INLINE_BODY
+#include  "Project_Config.h"
+#include  "r_ospl.h"
+#include  "iodefine.h" /* for inline function in "clib_registers.h" */
+#if defined(TARGET_RZA1H) /* mbed */
+#include  "clib_registers.h"
+#include  "clib_drivers.h"
+#include  "window_surfaces.h"
+#include  "RGA_Port.h"
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/locking.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,393 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking.c
+* @brief   Lock related FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#if R_OSPL_IS_PREEMPTION
+#include  "r_ospl_RTX_private.h"
+#endif
+#if IS_RZ_A1_BSP_USED
+#include  "dma_if.h"  /* R_DMA_Alloc */
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/** gs_ospl_mutex */
+#if R_OSPL_IS_PREEMPTION
+static osMutexId_t  gs_ospl_mutex;  /* gs_OSPL_Mutex */
+#endif
+
+
+/** g_bsp_Locks */
+BSP_CFG_USER_LOCKING_TYPE  g_bsp_Locks[ BSP_NUM_LOCKS ];
+
+
+/***********************************************************************
+* Implement: R_BSP_HardwareLock
+************************************************************************/
+bool_t  R_BSP_HardwareLock( mcu_lock_t const  HardwareIndex )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION( HardwareIndex );
+#else
+    bool_t  is_success;
+
+
+#if IS_RZ_A1_BSP_USED
+    if ( HardwareIndex >= BSP_LOCK_DMAC0  &&  HardwareIndex <= BSP_LOCK_DMAC15 ) {
+        int_fast32_t  channel_of_DMAC = HardwareIndex - BSP_LOCK_DMAC0;
+
+        channel_of_DMAC = R_DMA_Alloc( channel_of_DMAC, NULL );
+        IF ( channel_of_DMAC == -1 ) {
+            is_success = false;
+            goto fin;
+        }
+
+        is_success = true;
+        goto fin;
+    }
+#endif
+
+    IF_D ( R_CUT_IF_ALWAYS_FALSE( HardwareIndex < 0u  ||)  HardwareIndex >= R_COUNT_OF( g_bsp_Locks ) ) {
+        is_success = false;
+        goto fin;
+    }
+
+    is_success = R_BSP_SoftwareLock( &g_bsp_Locks[ HardwareIndex ] );
+    IF ( ! is_success ) {
+        goto fin;
+    }
+
+    is_success = true;
+fin:
+    return  is_success;
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_LockUnlockedChannel
+************************************************************************/
+#if ! BSP_CFG_USER_LOCKING_ENABLED
+errnum_t  R_OSPL_LockUnlockedChannel( int_fast32_t *out_ChannelNum,
+                                      mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax )
+{
+    errnum_t    e;
+    mcu_lock_t  hardware_index;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() == NULL ) {  /* If interrrupt context */
+        e = E_NOT_THREAD;
+        goto fin;
+    }
+    e= R_OSPL_Start_T_Lock();
+    if ( e != 0 ) {
+        R_OSPL_RaiseUnrecoverable( e );
+        goto fin;
+    }
+    is_lock = true;  /* T-Lock to "self" */
+#endif
+
+
+#if IS_RZ_A1_BSP_USED
+    if ( HardwareIndexMin == BSP_LOCK_DMAC0 ) {
+        int_fast32_t  channel_of_DMAC;
+
+        channel_of_DMAC = R_DMA_Alloc( DMA_ALLOC_CH, NULL );
+        IF ( channel_of_DMAC == -1 ) {
+            e = E_FEW_ARRAY;
+            goto fin;
+        }
+
+        *out_ChannelNum = channel_of_DMAC;
+        e = 0;
+        goto fin;
+    }
+#endif
+
+
+    for ( hardware_index = HardwareIndexMin;  hardware_index <= HardwareIndexMax;
+            hardware_index += 1 ) {
+        r_ospl_c_lock_t  *lock = &g_bsp_Locks[ hardware_index ];
+
+        if ( ! lock->IsLocked ) {
+            lock->IsLocked = true;
+            break;
+        }
+    }
+    IF ( hardware_index > HardwareIndexMax ) {
+        e=E_FEW_ARRAY;
+        goto fin;
+    }
+
+
+    *out_ChannelNum = hardware_index - HardwareIndexMin;
+
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+
+    return  e;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_BSP_HardwareUnlock
+************************************************************************/
+bool_t  R_BSP_HardwareUnlock( mcu_lock_t const  HardwareIndex )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION( HardwareIndex );
+#else
+    bool_t  is_success;
+
+
+#if IS_RZ_A1_BSP_USED
+    if ( HardwareIndex >= BSP_LOCK_DMAC0  &&  HardwareIndex <= BSP_LOCK_DMAC15 ) {
+        int_fast32_t  channel_of_DMAC = HardwareIndex - BSP_LOCK_DMAC0;
+        int_fast32_t  err2;
+
+        err2 = R_DMA_Free( channel_of_DMAC, NULL );
+        IF ( err2 != ESUCCESS ) {
+            is_success = false;
+            goto fin;
+        }
+
+        is_success = true;
+        goto fin;
+    }
+#endif
+
+
+    IF_D ( R_CUT_IF_ALWAYS_FALSE( HardwareIndex < 0u  ||)  HardwareIndex >= R_COUNT_OF( g_bsp_Locks ) ) {
+        is_success = false;
+        R_OSPL_RaiseUnrecoverable( E_FEW_ARRAY );
+        goto fin;
+    }
+
+    is_success = R_BSP_SoftwareUnlock( &g_bsp_Locks[ HardwareIndex ] );
+    IF ( ! is_success ) {
+        goto fin;
+    }
+
+    is_success = true;
+fin:
+    return  is_success;
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_SoftwareLock
+************************************************************************/
+bool_t  R_BSP_SoftwareLock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION( LockObject );
+#else
+    errnum_t  e;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        IF(e!=0) {
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "self" */
+    }
+#endif
+
+
+    e= R_OSPL_C_LOCK_Lock( LockObject );
+    if ( e == E_ACCESS_DENIED ) {
+        R_OSPL_CLEAR_ERROR();
+        goto fin;
+    }
+    IF(e) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+
+    return  (bool_t)( e == 0 );
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_SoftwareUnlock
+************************************************************************/
+bool_t  R_BSP_SoftwareUnlock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION( LockObject );
+#else
+    errnum_t  e;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        IF ( e != 0 ) {
+            R_OSPL_RaiseUnrecoverable( e );
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "self" */
+    }
+#endif
+
+
+    e= R_OSPL_C_LOCK_Unlock( LockObject );
+    if ( e == E_ACCESS_DENIED ) {
+        R_OSPL_CLEAR_ERROR();
+        goto fin;
+    }
+    IF(e) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+
+    return  (bool_t)( e == 0 );
+#endif
+}
+
+
+/**
+* @brief   The function callbacked from OSPL internal, when T-Lock started
+*
+* @par Parameters
+*    None
+* @return  Error Code. 0=No Error.
+*/
+#if R_OSPL_IS_PREEMPTION
+errnum_t  R_OSPL_Start_T_Lock(void)
+{
+    errnum_t    e;
+    osStatus_t  es;
+
+    osMutexDef( gs_ospl_mutex );
+
+    if ( gs_ospl_mutex == NULL ) {
+        gs_ospl_mutex = osMutexNew( osMutex( gs_ospl_mutex ) );
+        if ( gs_ospl_mutex == NULL ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+    }
+
+    es= osMutexAcquire( gs_ospl_mutex, osWaitForever );
+    if ( es == osErrorISR ) {
+        es = osOK;
+    }
+    if ( es != osOK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+#endif
+
+
+/**
+* @brief   The function callbacked from OSPL internal, when T-Lock ended
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+#if R_OSPL_IS_PREEMPTION
+void  R_OSPL_End_T_Lock(void)
+{
+    if ( gs_ospl_mutex != NULL ) {
+        osStatus_t rs;
+
+        rs= osMutexRelease( gs_ospl_mutex );
+        if ( rs == osErrorISR ) {
+            rs = osOK;
+        }
+        ASSERT_R( rs == osOK,  R_OSPL_RaiseUnrecoverable( E_OTHERS ) );
+    }
+}
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/mcu_interrupts.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,147 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  mcu_interrupts.c
+* @brief   Interrupt related FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "mcu_interrupts.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptWrite
+************************************************************************/
+bsp_int_err_t  R_BSP_InterruptWrite( bsp_int_src_t const  in_IRQ_Num,  bsp_int_cb_t const  in_Callback )
+{
+    uint32_t       er;
+    bsp_int_err_t  eb;
+    IRQn_Type      irq;  /* QAC 3441 */
+
+    if ( in_Callback == FIT_NO_FUNC ) {
+        irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );
+        er= InterruptHandlerUnregister( irq );
+        IF ( er != 0u ) {
+            eb=BSP_INT_ERR_INVALID_ARG;
+            goto fin;
+        }
+    } else {
+        irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );  /* QAC 3441 */
+        er= InterruptHandlerRegister( irq, in_Callback );
+        IF ( er != 0u ) {
+            eb=BSP_INT_ERR_INVALID_ARG;
+            goto fin;
+        }
+    }
+
+    eb = BSP_INT_SUCCESS;
+fin:
+    return  eb;
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptRead
+************************************************************************/
+bsp_int_err_t  R_BSP_InterruptRead( bsp_int_src_t const  in_IRQ_Num,  bsp_int_cb_t *const  out_Callback )
+{
+    R_UNREFERENCED_VARIABLE_2( in_IRQ_Num, out_Callback );
+    return  BSP_INT_ERR_UNSUPPORTED;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_OnInterruptForUnregistered
+************************************************************************/
+void  R_OSPL_OnInterruptForUnregistered( uint32_t const  int_sense )
+{
+    R_UNREFERENCED_VARIABLE( int_sense );
+    R_OSPL_RaiseUnrecoverable( E_OTHERS );
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptControl
+************************************************************************/
+bsp_int_err_t  R_BSP_InterruptControl( bsp_int_src_t const  in_IRQ_Num,  bsp_int_cmd_t const  in_Command,
+                                       void *const  in_NotUsed )
+{
+    bsp_int_err_t  eb;
+    IRQn_Type      irq;  /* QAC 3441 */
+
+    R_UNREFERENCED_VARIABLE( in_NotUsed );
+    R_IT_WILL_BE_NOT_CONST( in_NotUsed );
+
+    switch ( in_Command ) {
+        case  BSP_INT_CMD_INTERRUPT_ENABLE:
+
+            irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );
+            GIC_EnableIRQ( irq );
+            break;
+
+        default:
+            IF_DS( in_Command != BSP_INT_CMD_INTERRUPT_DISABLE ) {
+                eb=BSP_INT_ERR_INVALID_ARG;
+                goto fin;
+            }
+
+            irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );
+            GIC_DisableIRQ( irq );
+            break;
+    }
+
+    eb = BSP_INT_SUCCESS;
+fin:
+    return  eb;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/r_ospl_RTX.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,521 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_RTX.c
+* @brief   OS Porting Layer API for RTX
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "r_ospl_os_less_private.h"
+#include  "r_ospl_private.h"
+#include  "core_ca.h"
+#if R_OSPL_IS_PREEMPTION
+#include  "cmsis_os.h"
+#include  "r_ospl_RTX_private.h"
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  OS_ERROR_SIGNAL
+* @brief  CMSIS-RTOS defined immediate value
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  OS_ERROR_SIGNAL  0x80000000
+
+
+/**
+* @def  R_OSPL_EVENT_WATCH
+* @brief  Debug tool
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_OSPL_EVENT_WATCH  0  /* [R_OSPL_EVENT_WATCH] 0 or 1 */
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_OSPL_Initialize
+************************************************************************/
+errnum_t  R_OSPL_Initialize( const void *const  in_NullConfig )
+{
+    R_UNREFERENCED_VARIABLE( in_NullConfig );
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_THREAD_GetCurrentId
+************************************************************************/
+r_ospl_thread_id_t  R_OSPL_THREAD_GetCurrentId(void)
+{
+    return  osThreadGetId();
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Set
+************************************************************************/
+void  R_OSPL_EVENT_Set( r_ospl_thread_id_t const  ThreadId,  bit_flags32_t const  SetFlags )
+{
+    int32_t  ret;
+
+    if ( ThreadId != NULL ) {
+#if  R_OSPL_EVENT_WATCH
+        R_D_AddToIntLog( 0x70100000 + SetFlags );
+        R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+        R_D_AddToIntLog( (uintptr_t) ThreadId );
+#endif
+
+        ret = osSignalSet( (osThreadId_t) ThreadId, (int32_t) SetFlags );
+        ASSERT_D( (ret & OS_ERROR_SIGNAL) == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( ret );  /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Clear
+************************************************************************/
+void  R_OSPL_EVENT_Clear( r_ospl_thread_id_t const  ThreadId,  bit_flags32_t const  ClearFlags1 )
+{
+    int32_t  ret;
+
+    if ( ThreadId != NULL ) {
+        IF_D( ( ClearFlags1 & ~0xFFFF ) != 0 ) {
+            R_NOOP();
+        }
+
+#if  R_OSPL_EVENT_WATCH
+        R_D_AddToIntLog( 0x70C00000 + ClearFlags1 );
+        R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+        R_D_AddToIntLog( (uintptr_t) ThreadId );
+#endif
+
+        ret = osSignalClear( (osThreadId_t) ThreadId, (int32_t) ClearFlags1 );
+        /* "& 0xFFFF" is for avoiding error in osSignalClear */
+        ASSERT_D( (ret & OS_ERROR_SIGNAL) == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( ret );  /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Get
+************************************************************************/
+#if ( ! defined( osCMSIS )  ||  osCMSIS <= 0x10001 ) &&  R_OSPL_VERSION < 85
+bit_flags32_t  R_OSPL_EVENT_Get( r_ospl_thread_id_t const  ThreadId )
+{
+    int32_t  ret;
+
+    if ( ThreadId == NULL ) {
+        ret = 0;
+    } else {
+        ret = osSignalGet( (osThreadId_t) ThreadId );
+        ASSERT_D( (ret & OS_ERROR_SIGNAL) == 0,  R_NOOP() );
+    }
+
+    return  (bit_flags32_t) ret;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Wait
+************************************************************************/
+errnum_t  R_OSPL_EVENT_Wait( bit_flags32_t const  WaigingFlags,  bit_flags32_t *const  out_GotFlags,
+                             uint32_t const  Timeout_msec )
+{
+    errnum_t  e;
+    osEvent   event;
+
+    R_STATIC_ASSERT( R_OSPL_INFINITE == osWaitForever, "" );
+
+#if  R_OSPL_EVENT_WATCH
+    R_D_AddToIntLog( 0x70BE0000 + WaigingFlags );
+    R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+
+    {
+        static int tc;
+        if ( R_D_Counter( &tc, 0, NULL ) ) {
+            R_DEBUG_BREAK();
+        }
+    }
+#endif
+
+
+    event = osSignalWait( (int32_t) WaigingFlags, Timeout_msec );
+
+
+#if  R_OSPL_EVENT_WATCH
+    R_D_AddToIntLog( 0x70AF0000 );
+    R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+#endif
+
+    if ( (event.status == osOK) || (event.status == osEventTimeout) ) {
+        if ( out_GotFlags != NULL ) {
+            *out_GotFlags = R_OSPL_TIMEOUT;
+        }
+        IF ( event.status == osEventTimeout ) {
+            e=E_TIME_OUT;
+            goto fin;
+        }
+    } else {
+        ASSERT_R( event.status == osEventSignal,  e=E_OTHERS;  goto fin );
+
+        if ( out_GotFlags != NULL ) {
+            *out_GotFlags = (bit_flags32_t) event.value.signals;
+        }
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_SetInterruptPriority
+************************************************************************/
+errnum_t  R_OSPL_SetInterruptPriority( bsp_int_src_t const  IRQ_Num, int_fast32_t const  Priority )
+{
+    GIC_SetPriority( IRQ_Num, (uint32_t) Priority );
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_Flush
+************************************************************************/
+void  R_OSPL_MEMORY_Flush( r_ospl_flush_t const  FlushType )
+{
+    if ( FlushType == R_OSPL_FLUSH_WRITEBACK_INVALIDATE ) {
+#if 0
+        printf( "L1Flush\n" );
+#endif
+
+#if IS_RTX_USED
+        L1C_CleanInvalidateDCacheAll();
+#else
+#error
+#endif
+    } else if ( FlushType == R_OSPL_FLUSH_WRITEBACK_INVALIDATE_2ND ) {
+#if 0
+        printf( "PL310Flush\n" );
+#endif
+
+        L2C_CleanInvAllByWay();
+    } else {
+        ASSERT_D( false,  R_NOOP() );
+    }
+}
+
+
+/**
+* @brief   R_OSPL_Is1bitOnly_Fast32_Sub
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifndef  R_OSPL_NDEBUG
+static bool_t  R_OSPL_Is1bitOnly_Fast32_Sub( uint_fast32_t Value )
+{
+    if ( (Value & 0x0000FFFFu) == 0 ) {
+        Value >>= 16;
+    }
+    if ( (Value & 0x000000FFu) == 0 ) {
+        Value >>=  8;
+    }
+    if ( (Value & 0x0000000Fu) == 0 ) {
+        Value >>=  4;
+    }
+    if ( (Value & 0x00000003u) == 0 ) {
+        Value >>=  2;
+    }
+    if ( (Value & 0x00000001u) == 0 ) {
+        Value >>=  1;
+    }
+    return  ( Value == 1 );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_RangeFlush
+************************************************************************/
+errnum_t  R_OSPL_MEMORY_RangeFlush( r_ospl_flush_t const  FlushType,
+                                    const void *const  StartAddress,  size_t const  Length )
+{
+    errnum_t   e;
+    size_t     cache_line_size;
+    size_t     cache_line_mask;
+    uintptr_t  start;
+    uintptr_t  over;
+
+    ASSERT_R( FlushType == R_OSPL_FLUSH_INVALIDATE,  e=E_BAD_COMMAND_ID; goto fin );
+
+    cache_line_size = R_OSPL_MEMORY_GetCacheLineSize();
+    cache_line_mask = cache_line_size - 1u;
+    ASSERT_D( R_OSPL_Is1bitOnly_Fast32_Sub( cache_line_size ), e=E_OTHERS; goto fin );
+
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    ASSERT_R( ( (uintptr_t) StartAddress & cache_line_mask ) == 0u, e=E_OTHERS; goto fin );
+    ASSERT_R( ( Length & cache_line_mask ) == 0u, e=E_OTHERS; goto fin );
+
+    start = (uintptr_t) StartAddress;
+    over  = ((uintptr_t) StartAddress + Length) - 1u;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+
+    R_OSPL_MEMORY_RangeFlush_Sub( start, over, cache_line_size );
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_GetSpecification
+************************************************************************/
+void  R_OSPL_MEMORY_GetSpecification( r_ospl_memory_spec_t *const  out_MemorySpec )
+{
+    IF_DQ( out_MemorySpec == NULL ) {
+        goto fin;
+    }
+
+    out_MemorySpec->CacheLineSize = R_OSPL_MEMORY_GetCacheLineSize();
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_Delay
+************************************************************************/
+errnum_t  R_OSPL_Delay( uint32_t const  DelayTime_msec )
+{
+    errnum_t   e;
+    osStatus_t rs;
+    bool_t const    is_overflow = ( DelayTime_msec > R_OSPL_MAX_TIME_OUT );
+    uint32_t const  delay_parameter = DelayTime_msec + 1u;
+
+    ASSERT_D( ! is_overflow, R_NOOP() );
+    /* RTX 5.16: If delay_parameter = 100000, "osDelay" waits 65534 */
+
+    rs= osDelay( delay_parameter );
+    IF ( rs == osErrorISR ) {
+        e=E_NOT_THREAD;
+        R_OSPL_RaiseUnrecoverable( e );
+        goto fin;
+    }
+    IF ( IS( is_overflow ) ) {
+        e=E_TIME_OUT;
+        goto fin;
+    }
+
+    IF (
+        (rs != osOK) &&           /* for delay_parameter == 0 */
+        (rs != osEventTimeout) ) { /* for delay_parameter != 0 */
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Create
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Create( r_ospl_queue_t **out_self, r_ospl_queue_def_t *QueueDefine )
+{
+    errnum_t  e;
+    r_ospl_queue_t  *self = QueueDefine;
+
+    self->MailQId = osMailCreate( (osMailQDef_t *) QueueDefine->MailQDef, NULL );
+    IF ( self->MailQId == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    self->PublicStatus.UsedCount = 0;
+
+    *out_self = self;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_GetStatus
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_GetStatus( r_ospl_queue_t *self,  const r_ospl_queue_status_t **out_Status )
+{
+    *out_Status = &self->PublicStatus;
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Allocate
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Allocate( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec )
+{
+    errnum_t  e;
+    void     *address;
+
+    address = osMailAlloc( self->MailQId, Timeout_msec );
+    *(void **) out_Address = address;
+    IF ( address == NULL  &&  Timeout_msec > 0 ) {
+        if ( R_OSPL_THREAD_GetCurrentId() == NULL ) {
+            e=E_NOT_THREAD;
+        } else {
+            e=E_TIME_OUT;
+        }
+        goto fin;
+    }
+
+    R_OSPL_DisableAllInterrupt();
+    self->PublicStatus.UsedCount += 1;
+
+    e=0;
+    R_OSPL_EnableAllInterrupt();
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Put
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Put( r_ospl_queue_t *self,  void *Address )
+{
+    errnum_t    e;
+    osStatus_t  status;
+
+    status = osMailPut( self->MailQId, Address );
+    IF ( status != osOK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Get
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Get( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec )
+{
+    errnum_t  e;
+    osEvent   event;
+
+    event = osMailGet( self->MailQId, Timeout_msec );
+
+    if ( event.status != osOK ) {
+        IF ( event.status != osEventMail ) {
+            if ( event.status == osEventTimeout ) {
+                e = E_TIME_OUT;
+            } else if ( event.status == osErrorParameter ) {
+                if ( R_OSPL_THREAD_GetCurrentId() == NULL ) {
+                    e = E_NOT_THREAD;
+                } else {
+                    e = E_OTHERS;
+                }
+            } else {
+                e = E_OTHERS;
+            }
+            goto fin;
+        }
+    }
+
+    *(void **) out_Address = event.value.p;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Free
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Free( r_ospl_queue_t *self,  void *Address )
+{
+    errnum_t    e;
+    osStatus_t  status;
+
+    status = osMailFree( self->MailQId, Address );
+    IF ( status != osOK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    R_OSPL_DisableAllInterrupt();
+    self->PublicStatus.UsedCount -= 1;
+
+    e=0;
+    R_OSPL_EnableAllInterrupt();
+fin:
+    return  e;
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/r_ospl_debug.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,180 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_debug.c
+* @brief   Debug tools provided by OSPL.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "r_ospl_debug.h"
+#if R_OSPL_DEBUG_TOOL
+#include  <stdio.h>
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_debug_watch4_t
+* @brief  Watch context
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+#if R_OSPL_DEBUG_TOOL
+typedef struct st_r_ospl_debug_watch4_t  r_ospl_debug_watch4_t;
+struct st_r_ospl_debug_watch4_t {
+    volatile const uint32_t  *Address;
+    uint32_t  BreakValue;
+    bool_t    IsPrintf;
+};
+static r_ospl_debug_watch4_t  g_r_ospl_debug_watch4[ 10 ];
+#endif
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_D_Add
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Add( int_fast32_t IndexNum, volatile const void *in_Address, uint32_t BreakValue, bool_t IsPrintf )
+{
+    r_ospl_debug_watch4_t  *self = &g_r_ospl_debug_watch4[ IndexNum ];
+    int_t                   r;
+
+    R_OSPL_DisableAllInterrupt();
+
+    if ( IS( IsPrintf ) ) {
+        r= printf( "Debug_add( %d, 0x%08X )\n", IndexNum, (uintptr_t) in_Address );
+        R_UNREFERENCED_VARIABLE( r ); /* QAC 3200 : This is not error information */
+    }
+    self->Address = (uint32_t *) in_Address;
+    self->BreakValue = BreakValue;
+    self->IsPrintf = IsPrintf;
+
+    R_OSPL_EnableAllInterrupt();
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+
+/***********************************************************************
+* Implement: R_D_Watch
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Watch( int_fast32_t in_IndexNum )
+{
+    r_ospl_debug_watch4_t  *self = &g_r_ospl_debug_watch4[ in_IndexNum ];
+    int_t                   r;
+
+    R_OSPL_DisableAllInterrupt();
+
+    if ( self->Address != NULL ) {
+        if ( IS( self->IsPrintf ) ) {
+            r= printf( "Debug_watch( %d ): 0x%08X\n", in_IndexNum, (uintptr_t) *self->Address );
+            R_UNREFERENCED_VARIABLE( r ); /* QAC 3200 : This is not error information */
+            /* Cast of "uintptr_t" is for avoiding "format" warning of GNU_ARM */
+        }
+        if ( *self->Address == self->BreakValue ) {
+            R_DEBUG_BREAK();
+        }
+    }
+
+    R_OSPL_EnableAllInterrupt();
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+
+/***********************************************************************
+* Implement: R_D_AddToIntLog
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+#define  IntLogBreakID  -1   /* -1=not break */
+
+volatile uint_fast32_t  g_DebugVar[ g_DebugVarCount ];
+volatile int_fast32_t   g_IntLog[ g_IntLogCount ];
+volatile int_fast32_t   g_IntLogLength;
+
+void  R_D_AddToIntLog( int_fast32_t in_Value )  /* Add to g_IntLog, g_IntLogLength */
+{
+    g_IntLog[ (uint_fast32_t) g_IntLogLength % ( sizeof(g_IntLog) / sizeof(*g_IntLog) ) ] = in_Value;
+    if ( g_IntLogLength == IntLogBreakID ) {
+        R_DEBUG_BREAK();
+    }
+    g_IntLogLength += 1;
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+
+/***********************************************************************
+* Implement: R_D_Counter
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+bool_t  R_D_Counter( int_fast32_t *in_out_Counter, int_fast32_t TargetCount, char_t *in_Label )
+{
+    int_fast32_t  counter;
+    bool_t        is_stop;
+    int_t         r;
+
+    counter = *in_out_Counter;
+    counter += 1;
+    is_stop = ( counter == TargetCount );
+    if ( in_Label != NULL ) {
+        r= printf( "%s %d:\n", in_Label, counter );
+        R_UNREFERENCED_VARIABLE( r );  /* QAC 3200 : This is not error information */
+    } else {
+        if ( counter == 1 ) {
+            printf( "R_D_Counter address: 0x%08X\n", (uintptr_t) in_out_Counter );
+        }
+    }
+    *in_out_Counter = counter;
+
+    return  is_stop;
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/r_ospl_memory.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,436 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_memory.c
+* @brief   Memory map
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#ifdef R_OSPL_TEST_CODE
+#include  "r_ospl_test.h"
+#endif
+#include  "r_ospl_private.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  gs_address_table_line_t
+* @brief  gs_address_table_line_t
+*/
+typedef struct st_gs_address_table_line_t  gs_address_table_line_t;
+struct st_gs_address_table_line_t {
+
+    /** Address */
+    uintptr_t  Address;
+
+    /** Value */
+    int_fast32_t  Value;
+};
+
+
+/**
+* @struct  gs_address_table_line_c_t
+* @brief  gs_address_table_line_c_t
+*/
+typedef struct st_gs_address_table_line_c_t  gs_address_table_line_c_t;
+struct st_gs_address_table_line_c_t {
+
+    /** Address */
+    uintptr_t  Address;
+
+    /** Value */
+    r_ospl_axi_cache_attribute_t  Value;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* ->MISRA 17.4 : These are addresses */
+
+#define GS_MIRROR_SIZE    0x40000000u
+#define GS_CACHED_START   0x00000000u
+#define GS_CACHED_END     ( GS_CACHED_START + GS_MIRROR_SIZE )
+#define GS_UNCACHED_START 0x40000000u
+#define GS_UNCACHED_END   ( GS_UNCACHED_START + GS_MIRROR_SIZE )
+
+#define GS_IO_START       0x60A00000u
+
+/* From "scatter.scat" file */
+#if defined( RZ_A1L )
+#define LRAM_SIZE                   0x00300000u
+#else  /* RZ/A1H */
+#define LRAM_SIZE                   0x00A00000u
+#endif
+#define LRAM_START                  0x20000000u
+#define LRAM_END                    ( LRAM_START + LRAM_SIZE )
+#define UNUSED_UNCACHED_LRAM_START  0x60000000u
+#define UNCACHED_LRAM_END           ( UNUSED_UNCACHED_LRAM_START + LRAM_SIZE )
+
+/* <-MISRA 17.4 */
+
+#define  GS_EXTERNAL_START_0x00000000               0x00000000u
+#define  GS_EXTERNAL_SDRAM_START_0x08000000         0x08000000u
+#define  GS_INTERNAL_RAM_START_0x20000000           0x20000000u
+#define  GS_INTERNAL_REGISTERS_START_0x80000000     0x80000000u
+
+#if defined( RZ_A1L_EV_BOARD )
+#define  GS_SDRAM_SIZE  0x04000000u
+#else
+#define  GS_SDRAM_SIZE  0x08000000u
+#endif
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+#ifdef R_OSPL_TEST_CODE
+static  r_ospl_axi_envronment_t  gs_Environment;
+#endif
+
+
+/******************************************************************************
+* Implement: R_OSPL_ToPhysicalAddress
+******************************************************************************/
+errnum_t  R_OSPL_ToPhysicalAddress( const volatile void *in_Address, uintptr_t *out_PhysicalAddress )
+{
+    errnum_t  e;
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    uintptr_t const  address = (uintptr_t) in_Address;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+
+    IF_DQ( out_PhysicalAddress == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    *out_PhysicalAddress = address;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_ToCachedAddress
+******************************************************************************/
+errnum_t  R_OSPL_ToCachedAddress( const volatile void *in_Address, void *out_CachedAddress )
+{
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base */
+    errnum_t  e;
+#if  IS_MBED_USED
+    uintptr_t  address = (uintptr_t) in_Address;
+    const uintptr_t  uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
+#else
+    uintptr_t const  address = (uintptr_t) in_Address;
+#endif
+
+    IF_DQ( out_CachedAddress == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if  IS_MBED_USED
+    IF ( address < LRAM_START ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < LRAM_END ) {
+        e = 0;
+    } else IF ( address < UNUSED_UNCACHED_LRAM_START ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < UNCACHED_LRAM_END ) {
+        address -= uncached_from_cached;
+        e = 0;
+    } else {
+        e = E_ACCESS_DENIED;
+    }
+#else
+    IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base)  &&
+         (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
+        /* "BEGIN_OF_NOCACHE_RAM_BARRIER" is defined in "scatter.sct" file. */
+        /* Image$$ execution region symbols */
+        /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0377d/CHDFHJDJ.html */
+
+        e = E_ACCESS_DENIED;
+    }
+    else IF ( address >= UNUSED_UNCACHED_LRAM_START ) {
+        e = E_ACCESS_DENIED;
+    }
+    else {
+        e = 0;
+    }
+#endif
+
+    *(void **) out_CachedAddress = (void *) address;
+
+fin:
+    return  e;
+    /* <-QAC 0289 *//* <-QAC 1002 */
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_ToUncachedAddress
+******************************************************************************/
+errnum_t  R_OSPL_ToUncachedAddress( const volatile void *in_Address, void *out_UncachedAddress )
+{
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base */
+    errnum_t  e;
+#if  IS_MBED_USED
+#if  defined ( __GNUC__ ) && ! defined( __CC_ARM )
+    uintptr_t  address = (uintptr_t) in_Address;
+#else
+    uintptr_t  address = (uintptr_t) in_Address;
+    uintptr_t  nc_base = UNUSED_UNCACHED_LRAM_START;
+    const uintptr_t  uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
+#endif
+#else
+    uintptr_t const  address = (uintptr_t) in_Address;
+#endif
+
+    IF_DQ( out_UncachedAddress == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if  IS_MBED_USED
+#if  defined ( __GNUC__ ) && ! defined( __CC_ARM )
+    e = 0;
+#else
+    IF ( address < nc_base - uncached_from_cached ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < LRAM_END ) {
+        address += uncached_from_cached;
+        e = 0;
+    } else IF ( address < nc_base ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < UNCACHED_LRAM_END ) {
+        e = 0;
+    } else {
+        e = E_ACCESS_DENIED;
+    }
+#endif
+#else
+    IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base)  &&
+         (address < (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$ZI$$Limit) ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base)  &&
+              (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
+        e = 0;
+    } else IF ( R_CUT_IF_ALWAYS_TRUE( (address >= GS_CACHED_START)  &&)  (address < GS_CACHED_END) ) {
+        e = E_ACCESS_DENIED;
+    }
+    else IF ( (address >= UNUSED_UNCACHED_LRAM_START) && (address < GS_IO_START) ) {
+        e = E_ACCESS_DENIED;
+    }
+    else {
+        e = 0;
+    }
+#endif
+
+    *(void **) out_UncachedAddress = (void *) address;
+
+fin:
+    return  e;
+    /* <-QAC 0289 *//* <-QAC 1002 */
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_MEMORY_GetLevelOfFlush
+******************************************************************************/
+errnum_t  R_OSPL_MEMORY_GetLevelOfFlush( const void *in_Address, int_fast32_t *out_Level )
+{
+    uintptr_t  address = (uintptr_t) in_Address;
+
+#ifdef R_OSPL_TEST_CODE
+    if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
+#endif
+        static const gs_address_table_line_t  table[] = {
+            /* .Address                                       .Value */
+            { GS_EXTERNAL_START_0x00000000,                        0 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000,                  1 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE,  0 },
+            { GS_INTERNAL_RAM_START_0x20000000,                    1 },
+            { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE,        0 }
+        };
+
+
+        if ( address < table[1].Address ) {
+            *out_Level = table[0].Value;
+        } else if ( address < table[2].Address ) {
+            *out_Level = table[1].Value;
+        } else if ( address < table[3].Address ) {
+            *out_Level = table[2].Value;
+        } else if ( address < table[4].Address ) {
+            *out_Level = table[3].Value;
+        } else {
+            *out_Level = table[4].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
+
+#ifdef R_OSPL_TEST_CODE
+    } else {
+        static const gs_address_table_line_t  table[] = {
+            /* .Address                                       .Value */
+            { GS_EXTERNAL_START_0x00000000,                        0 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000,                  2 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE,  0 },
+            { GS_INTERNAL_RAM_START_0x20000000,                    1 },
+            { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE,        0 },
+            /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000,                 2 }, */
+            /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000 + GS_SDRAM_SIZE, 0 }, */
+            /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000,                   0 }, */
+            /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000 + LRAM_SIZE,       0 } */
+        };
+
+
+        ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
+
+        if ( address < table[1].Address ) {
+            *out_Level = table[0].Value;
+        } else if ( address < table[2].Address ) {
+            *out_Level = table[1].Value;
+        } else if ( address < table[3].Address ) {
+            *out_Level = table[2].Value;
+        } else if ( address < table[4].Address ) {
+            *out_Level = table[3].Value;
+        } else {
+            *out_Level = table[4].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
+    }
+#endif
+    return  0;
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_AXI_Get2ndCacheAttribute
+******************************************************************************/
+errnum_t  R_OSPL_AXI_Get2ndCacheAttribute( uintptr_t const  in_PhysicalAddress,
+        r_ospl_axi_cache_attribute_t *const  out_CacheAttribute )
+{
+    uintptr_t  address = in_PhysicalAddress;
+
+#ifdef R_OSPL_TEST_CODE
+    if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
+#endif
+        static const gs_address_table_line_c_t  table[] = {
+            /* .Address                                  .Value */
+            { GS_EXTERNAL_START_0x00000000,               R_OSPL_AXI_WRITE_BACK_W },
+            /*{ GS_EXTERNAL_SDRAM_START_0x08000000,       R_OSPL_AXI_WRITE_BACK_W },*/
+            { GS_INTERNAL_RAM_START_0x20000000,           R_OSPL_AXI_CACHE_ZERO },
+            /*{ GS_INTERNAL_REGISTERS_START_0x80000000,   R_OSPL_AXI_CACHE_ZERO }*/
+            /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
+        };
+
+
+        if ( address < table[1].Address ) {
+            *out_CacheAttribute = table[0].Value;
+        } else {
+            *out_CacheAttribute = table[1].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
+
+#ifdef R_OSPL_TEST_CODE
+    } else {
+        static const gs_address_table_line_c_t  table[] = {
+            /* .Address                                  .Value */
+            { GS_EXTERNAL_START_0x00000000,               R_OSPL_AXI_STRONGLY },
+            /*{ GS_EXTERNAL_SDRAM_START_0x08000000,       R_OSPL_AXI_STRONGLY },*/
+            { GS_INTERNAL_RAM_START_0x20000000,           R_OSPL_AXI_CACHE_ZERO },
+            /*{ GS_EXTERNAL_MIRROR_START_0x40000000,        R_OSPL_AXI_STRONGLY },*/
+            /*{ GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000,R_OSPL_AXI_STRONGLY },*/
+            /*{ GS_INTERNAL_RAM_MIRROR_START_0x60000000,    R_OSPL_AXI_CACHE_ZERO },*/
+            /*{ GS_INTERNAL_REGISTERS_START_0x80000000,   R_OSPL_AXI_CACHE_ZERO }*/
+            /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
+        };
+
+
+        ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
+
+        if ( address < table[1].Address ) {
+            *out_CacheAttribute = table[0].Value;
+        } else {
+            *out_CacheAttribute = table[1].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
+    }
+#endif
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_AXI_GetProtection
+************************************************************************/
+errnum_t  R_OSPL_AXI_GetProtection( uintptr_t const  in_PhysicalAddress,
+                                    r_ospl_axi_protection_t *const  out_Protection )
+{
+    *out_Protection = R_OSPL_AXI_NON_SECURE;  /* Same as CPU(TTB) NS bit */
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_AXI_SetEnvironment
+************************************************************************/
+#ifdef R_OSPL_TEST_CODE
+errnum_t  R_OSPL_AXI_SetEnvironment( r_ospl_axi_envronment_t in_Environment )
+{
+    gs_Environment = in_Environment;
+    return  0;
+}
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/porting/r_ospl_unrecoverable.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,80 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: r_ospl_unrecoverable.c $
+*    Unrecoverable State
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_OSPL_RaiseUnrecoverable
+************************************************************************/
+void  R_OSPL_RaiseUnrecoverable( errnum_t const  e )
+{
+    /* ->QAC 3204 */
+    volatile  bool_t  is_loop = true;
+    /* <-QAC 3204 */
+
+    R_OSPL_DisableAllInterrupt();
+
+    R_DebugBreak( NULL, e );
+
+    while ( IS( is_loop ) ) {
+        /* Infinite Loop. Set "is_loop" by the debugger */
+    }
+
+    R_OSPL_EnableAllInterrupt();
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/GraphicsFramework/ospl/src/r_ospl.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1613 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl.c
+* @brief   OS Porting Layer. Functions not depended on any environment.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "iodefine.h"
+#if defined(TARGET_RZ_A1XX)
+#include  "iobitmasks/cpg_iobitmask.h"
+#endif
+#include  "r_ospl_private.h"
+#include  "r_ospl_os_less_private.h"
+#include  "mbed_critical.h"
+#if R_OSPL_IS_PREEMPTION
+#include  "r_ospl_RTX_private.h"
+#endif
+#include  "locking.h"
+#ifdef __ICCARM__
+#include <intrinsics.h>
+#endif
+#ifdef  __GNUC__
+#if ! IS_MBED_USED
+#include  "irq.h"
+#endif
+#endif
+#if R_OSPL_DEBUG_TOOL
+#include  <stdio.h>
+#endif
+#ifndef R_OSPL_NDEBUG
+#include  <string.h>
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void  R_OSPL_TABLE_Search_Sub( const r_ospl_table_t *self,
+                                      const void *Key, r_ospl_table_searched_t *out_Searched );
+
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_error_t  *R_OSPL_GetCurrentThreadError_Sub( r_ospl_if_not_t TypeOfIfNot );
+#endif
+
+
+/**
+* @def  R_OSPL_DEFAULT_DEBUG_THREAD_COUNT
+* @brief  For until calling "R_OSPL_SET_DEBUG_WORK"
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+#define  R_OSPL_DEFAULT_DEBUG_THREAD_COUNT  2
+#endif
+
+
+/** For until calling "R_OSPL_SET_DEBUG_WORK" */
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_table_block_t  gs_thread_index_table_body[ R_OSPL_DEFAULT_DEBUG_THREAD_COUNT ];
+#endif
+
+
+/** For until calling "R_OSPL_SET_DEBUG_WORK" */
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_error_t  gs_error;
+#endif
+
+
+/** as <r_ospl_global_error_t> */
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+
+/* ->MISRA 8.7 : If not defined R_OSPL_ERROR_BREAK, this is referenced by only 1 function. */ /* ->SEC M2.2.1 */
+static r_ospl_global_error_t  gs_global_error =
+    /* <-MISRA 8.7 */ /* <-SEC M2.2.1 */
+{
+    {	                                  /* .ThreadIndexTable */
+        gs_thread_index_table_body,          /* .Area */
+        0,                                   /* .Count */
+        R_OSPL_DEFAULT_DEBUG_THREAD_COUNT,   /* .MaxCount */
+        NULL,                                /* .KeyCache */
+        0,                                   /* .IndexCache */
+        0,                                   /* .FirstFreeIndex */
+#if R_OSPL_IS_PREEMPTION
+        true                                 /* .Is_T_Lock */
+#endif
+    },
+    &gs_error,  /* .ErrorArray */
+
+#if R_OSPL_ERROR_BREAK
+    0,          /* .RaisedGlobalErrorID */  /* Necessary T-Lock */
+    0           /* .BreakGlobalErrorID */
+#endif
+};
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GetVersion
+************************************************************************/
+int32_t  R_OSPL_GetVersion(void)
+{
+    return  R_OSPL_VERSION;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_IsPreemption
+************************************************************************/
+bool_t  R_OSPL_IsPreemption(void)
+{
+    return  R_OSPL_IS_PREEMPTION;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_InitConst
+************************************************************************/
+void  R_OSPL_FLAG32_InitConst( volatile r_ospl_flag32_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->Flags = 0;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_Set
+************************************************************************/
+void  R_OSPL_FLAG32_Set( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  SetFlags )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->Flags |= SetFlags;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_Clear
+************************************************************************/
+void  R_OSPL_FLAG32_Clear( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  ClearFlags1 )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->Flags &= ~ClearFlags1;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_Get
+************************************************************************/
+bit_flags32_t  R_OSPL_FLAG32_Get( volatile const r_ospl_flag32_t *const  self )
+{
+    bit_flags32_t  return_value;
+
+    IF_DQ( self == NULL ) {
+        return_value = 0;
+        goto fin;
+    }
+
+    return_value = self->Flags;
+
+fin:
+    return  return_value;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_GetAndClear
+************************************************************************/
+bit_flags32_t  R_OSPL_FLAG32_GetAndClear( volatile r_ospl_flag32_t *const  self )
+{
+    bit_flags32_t  return_value;
+
+    IF_DQ( self == NULL ) {
+        return_value = 0;
+        goto fin;
+    }
+
+    return_value = self->Flags;
+    self->Flags = 0;
+
+fin:
+    return  return_value;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_ASYNC_CopyExceptAThread
+************************************************************************/
+void  R_OSPL_ASYNC_CopyExceptAThread( const r_ospl_async_t *const  Source,
+                                      r_ospl_async_t *const  Destination )
+{
+    IF_DQ( Destination == NULL ) {
+        goto fin;
+    }
+    IF_DQ( Source == NULL ) {
+        goto fin;
+    }
+
+    *Destination = *Source;
+    Destination->A_Thread = NULL;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EnableAllInterrupt
+************************************************************************/
+void  R_OSPL_EnableAllInterrupt(void)
+{
+    core_util_critical_section_exit();
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_DisableAllInterrupt
+************************************************************************/
+void  R_OSPL_DisableAllInterrupt(void)
+{
+    core_util_critical_section_enter();
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptsEnable
+************************************************************************/
+void  R_BSP_InterruptsEnable(void)
+{
+    core_util_critical_section_exit();
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptsDisable
+************************************************************************/
+void  R_BSP_InterruptsDisable(void)
+{
+    core_util_critical_section_enter();
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_LockChannel
+************************************************************************/
+errnum_t  R_OSPL_LockChannel( int_fast32_t ChannelNum, int_fast32_t *out_ChannelNum,
+                              mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax )
+{
+    errnum_t    e;
+    bool_t      is_success;
+    mcu_lock_t  hardware_index;
+
+    ASSERT_D( HardwareIndexMin <= HardwareIndexMax,  e=E_OTHERS; goto fin );
+
+    if ( ChannelNum == R_OSPL_UNLOCKED_CHANNEL ) {
+        ASSERT_D( out_ChannelNum != NULL,  e=E_OTHERS; goto fin );
+
+#if BSP_CFG_USER_LOCKING_ENABLED
+        for ( hardware_index = HardwareIndexMin;  hardware_index <= HardwareIndexMax;
+                hardware_index += 1 ) {
+            is_success = R_BSP_HardwareLock( hardware_index );
+            if ( is_success ) {
+                break;
+            }
+        }
+        IF ( hardware_index > HardwareIndexMax ) {
+            e=E_FEW_ARRAY;
+            goto fin;
+        }
+#else
+        e= R_OSPL_LockUnlockedChannel( out_ChannelNum,
+                                       HardwareIndexMin, HardwareIndexMax );
+        IF(e) {
+            goto fin;
+        }
+        out_ChannelNum = NULL;
+#endif
+    } else {
+        hardware_index = (mcu_lock_t)( HardwareIndexMin + ChannelNum );
+
+        IF_D ( hardware_index < HardwareIndexMin  ||  hardware_index > HardwareIndexMax ) {
+            e=E_FEW_ARRAY;
+            goto fin;
+        }
+
+        is_success = R_BSP_HardwareLock( hardware_index );
+        IF ( ! is_success ) {
+            e=E_ACCESS_DENIED;
+            goto fin;
+        }
+    }
+
+    if ( out_ChannelNum != NULL ) {
+        *out_ChannelNum = hardware_index - HardwareIndexMin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_UnlockChannel
+************************************************************************/
+errnum_t  R_OSPL_UnlockChannel( int_fast32_t ChannelNum,  errnum_t  e,
+                                mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax )
+{
+    bool_t      is_success;
+    mcu_lock_t  hardware_index;
+
+    ASSERT_D( HardwareIndexMin <= HardwareIndexMax,  e= R_OSPL_MergeErrNum( e, E_OTHERS ) );
+
+    hardware_index = (mcu_lock_t)( HardwareIndexMin + ChannelNum );
+
+    if ( hardware_index >= HardwareIndexMin  &&  hardware_index <= HardwareIndexMax ) {
+        is_success = R_BSP_HardwareUnlock( hardware_index );
+        IF ( ! is_success ) {
+            e= R_OSPL_MergeErrNum( e, E_ACCESS_DENIED );
+        }
+    }
+
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_C_LOCK_InitConst
+************************************************************************/
+void  R_OSPL_C_LOCK_InitConst( r_ospl_c_lock_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->IsLocked = false;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_C_LOCK_Lock
+************************************************************************/
+errnum_t  R_OSPL_C_LOCK_Lock( r_ospl_c_lock_t *const  self )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    IF ( R_OSPL_THREAD_GetCurrentId() == NULL ) {  /* Interrupt */
+        e = E_NOT_THREAD;
+        R_OSPL_RaiseUnrecoverable( e );
+        goto fin;
+    }
+
+    IF ( IS( self->IsLocked ) ) {
+        e=E_ACCESS_DENIED;
+        goto fin;
+    }
+
+    self->IsLocked = true;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_C_LOCK_Unlock
+************************************************************************/
+errnum_t  R_OSPL_C_LOCK_Unlock( r_ospl_c_lock_t *const  self )
+{
+    errnum_t  e;
+
+    if ( self != NULL ) {
+
+        IF ( R_OSPL_THREAD_GetCurrentId() == NULL ) {  /* Interrupt */
+            e = E_NOT_THREAD;
+            R_OSPL_RaiseUnrecoverable( e );
+            goto fin;
+        }
+
+        IF ( ! self->IsLocked ) {
+            /* Check not unlock the object that was initialized by other thread */
+            e = E_ACCESS_DENIED;
+            goto fin;
+        }
+
+        self->IsLocked = false;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_I_LOCK_LockStub
+************************************************************************/
+bool_t  R_OSPL_I_LOCK_LockStub( void *const  self_ )
+{
+    R_IT_WILL_BE_NOT_CONST( self_ );
+    R_UNREFERENCED_VARIABLE( self_ );
+    return  false;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_I_LOCK_UnlockStub
+************************************************************************/
+void  R_OSPL_I_LOCK_UnlockStub( void *const  self_ )
+{
+    R_IT_WILL_BE_NOT_CONST( self_ );
+    R_UNREFERENCED_VARIABLE( self_ );
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_I_LOCK_RequestFinalizeStub
+************************************************************************/
+void  R_OSPL_I_LOCK_RequestFinalizeStub( void *const  self_ )
+{
+    R_IT_WILL_BE_NOT_CONST( self_ );
+    R_UNREFERENCED_VARIABLE( self_ );
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_Barrier
+************************************************************************/
+void  R_OSPL_MEMORY_Barrier(void)
+{
+    /* ->QAC 1006 : asm */
+    __asm("DSB");
+    /* <-QAC 1006 */
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_InstructionSyncBarrier
+************************************************************************/
+void  R_OSPL_InstructionSyncBarrier(void)
+{
+    /* ->QAC 1006 : asm */
+    __asm("ISB");
+    /* <-QAC 1006 */
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_CALLER_Initialize
+************************************************************************/
+void  R_OSPL_CALLER_Initialize( r_ospl_caller_t *const  self,  r_ospl_async_t *const  Async,
+                                volatile void *const  PointerToState,  int_t const  StateValueOfOnInterrupting,
+                                void *const  I_Lock, const r_ospl_i_lock_vtable_t *const  I_LockVTable )
+{
+    ASSERT_D( Async != NULL,  R_NOOP() );
+    ASSERT_D( PointerToState != NULL,  R_NOOP() );
+    IF_DQ( self == NULL ) {}
+    else {
+        self->Async = Async;
+        self->PointerToState = (volatile int_fast32_t *) PointerToState;
+        self->StateValueOfOnInterrupting = StateValueOfOnInterrupting;
+        self->I_Lock = I_Lock;
+        self->I_LockVTable = I_LockVTable;
+    }
+
+#ifndef R_OSPL_NDEBUG
+    /* Set sentinel */
+    ASSERT_D( IS_ALL_BITS_NOT_SET( Async->Flags, R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK ),
+              R_NOOP() );
+    ASSERT_D( IS_ALL_BITS_NOT_SET( R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE,
+                                   ~R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK ),  R_NOOP() );
+
+    Async->Flags |= R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE;
+#endif
+}
+
+
+#if defined(TARGET_RZ_A1XX)
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_InitializeIfNot
+************************************************************************/
+errnum_t  R_OSPL_FTIMER_InitializeIfNot( r_ospl_ftimer_spec_t *const  out_Specification )
+{
+    /* ->SEC M1.11.1 : Can not const "is_initialized" because timing */
+    bool_t  is_initialized;
+    /* <-SEC M1.11.1 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    enum { bits_CST1_CST2 = 0x06 };
+#endif
+
+    /* ->QAC 0306 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+    struct st_ostm *const  reg_OSTM = &OSTM0;
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM1
+    struct st_ostm *const  reg_OSTM = &OSTM1;
+#endif
+    /* <-QAC 0306 */
+
+    /* ->QAC 0306 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+    R_OSPL_SET_TO_8_BIT_REGISTER( &CPG.STBCR5, CPG_STBCR5_MSTP51,
+                                  CPG_STBCR5_MSTP51_SHIFT, 0 );
+
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM1
+    R_OSPL_SET_TO_8_BIT_REGISTER( &CPG.STBCR5, CPG_STBCR5_MSTP50,
+                                  CPG_STBCR5_MSTP50_SHIFT, 0 );
+
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    R_OSPL_SET_TO_8_BIT_REGISTER( &CPG.STBCR3, CPG_STBCR3_MSTP33,
+                                  CPG_STBCR3_MSTP33_SHIFT, 0 );
+#endif
+
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    is_initialized = IS_ALL_BITS_NOT_SET( MTU2.TSTR, bits_CST1_CST2 );
+#else
+    is_initialized = ( (int_fast32_t) reg_OSTM->OSTMnTE == 0 );
+#endif
+    /* <-QAC 0306 */
+
+    if ( IS( is_initialized ) ) {  /* Integer Promotions */
+#if  R_OSPL_FTIMER_IS != R_OSPL_FTIMER_IS_MTU2_1_2
+        enum {  free_running_no_interrupt = 2 };
+#endif
+
+        R_OSPL_DisableAllInterrupt();
+
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+        {
+            enum { external_clock_TCLKD = 0x07u };
+
+            /* ->QAC 0306 */
+
+            /* Channel 1 */
+            MTU2.TCR_1  = (uint8_t) external_clock_TCLKD;  /* overflow of the timer2 */
+            MTU2.TMDR_1 = 0;
+            MTU2.TIOR_1 = 0;
+            MTU2.TIER_1 = 0;
+            MTU2.TSR_1  = 0;
+            MTU2.TCNT_1 = 0;
+
+            /* Channel 2 */
+            MTU2.TCR_2  = 0;  /* 33MHz */
+            MTU2.TMDR_2 = 0;
+            MTU2.TIOR_2 = 0;
+            MTU2.TIER_2 = 0;
+            MTU2.TSR_2  = 0;
+            MTU2.TCNT_2 = 0;
+
+            /* Timer start */
+            /* MTU2.TSTR |= bits_CST1_CST2; */
+            {
+                uint8_t const  value = MTU2.TSTR;
+                MTU2.TSTR = (uint8_t)( (uint_fast32_t) value | bits_CST1_CST2 );
+            } /* QAC 2100 */
+
+            /* <-QAC 0306 */
+        }
+#else
+        if ( (int_fast32_t) reg_OSTM->OSTMnTE == 0 ) {  /* Integer Promotions */
+            reg_OSTM->OSTMnCTL = free_running_no_interrupt;
+            reg_OSTM->OSTMnTS = 1;
+        }
+#endif
+
+        R_OSPL_EnableAllInterrupt();
+    }
+
+    R_OSPL_FTIMER_GetSpecification( out_Specification );
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_GetSpecification
+************************************************************************/
+void  R_OSPL_FTIMER_GetSpecification( r_ospl_ftimer_spec_t *const  out_Specification )
+{
+    if ( out_Specification != NULL ) {
+        enum { msec_numerator   = 1 };      /* SEC M1.10.1, QAC-3132 */
+        enum { msec_denominator = 33333 };  /* SEC M1.10.1, QAC-3132 */
+        static const uint32_t  max_count = 0xFFFFFFFFu;  /* SEC M1.10.1, QAC-3132 */
+        static const uint32_t  extension_of_count = (1000 * msec_denominator) / msec_numerator;
+        /* SEC M1.10.1, QAC-3132 */
+
+        out_Specification->msec_Numerator   = msec_numerator;
+        out_Specification->msec_Denominator = msec_denominator;
+        out_Specification->MaxCount = max_count;
+        out_Specification->ExtensionOfCount = extension_of_count;
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_Get
+************************************************************************/
+uint32_t  R_OSPL_FTIMER_Get(void)
+{
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    enum { num_16bit = 16 }; /* SEC M1.10.1, QAC-3132 */
+    /* ->QAC 0306 */
+
+    uint32_t  now_high = (uint32_t)(MTU2.TCNT_1);
+    uint32_t  not_low  = (uint32_t)(MTU2.TCNT_2);
+
+    while( now_high != (uint32_t)(MTU2.TCNT_1) ) {
+        /* If higher byte was changed while reading lower byte, re-read. */
+        now_high = (uint32_t)(MTU2.TCNT_1);
+        not_low  = (uint32_t)(MTU2.TCNT_2);
+    }
+
+    return  ( now_high << num_16bit ) | not_low;
+
+    /* <-QAC 0306 */
+#else
+
+    /* ->QAC 0306 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+    struct st_ostm *const  reg_OSTM = &OSTM0;
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM1
+    struct st_ostm *const  reg_OSTM = &OSTM1;
+#endif
+    /* <-QAC 0306 */
+
+    ASSERT_R( reg_OSTM->OSTMnCMP == 0x0000000u,  R_NOOP() );
+    /* If "OSTMnCMP != 0", OSTMnCNT is set from 0 to OSTMnCMP-1 */
+
+    return  reg_OSTM->OSTMnCNT;
+
+#endif
+}
+#endif /* TARGET_RZ_A1XX */
+
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_IsPast
+************************************************************************/
+errnum_t  R_OSPL_FTIMER_IsPast( const r_ospl_ftimer_spec_t *const  ts,
+                                uint32_t const  Now,  uint32_t const  TargetTime,  bool_t *const  out_IsPast )
+{
+    uint32_t const         target_minus_now = TargetTime - Now;
+    static const uint32_t  minus_flag = 0x80000000u;
+    errnum_t       e;
+    bool_t const   is_past = IS_BIT_SET( target_minus_now, minus_flag );
+
+    IF_DQ( ts == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_IsPast == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    if ( IS( is_past ) ) {
+        uint32_t const  now_minus_target = Now - TargetTime;
+
+        IF ( now_minus_target > ts->ExtensionOfCount ) {
+            e=E_TIME_OUT;
+            goto fin;
+        }
+    }
+
+    *out_IsPast = is_past;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_InitConst
+************************************************************************/
+void  R_OSPL_TABLE_InitConst( r_ospl_table_t *const  self,
+                              void *const  Area,  size_t const  AreaByteSize,  bool_t const  Is_T_Lock )
+{
+#if  ! defined( R_OSPL_NDEBUG ) ||  R_OSPL_IS_PREEMPTION
+    errnum_t  e;
+#endif
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+    IF_DQ( self == NULL ) {
+#ifndef R_OSPL_NDEBUG
+        e=E_OTHERS;
+#endif
+        goto fin;
+    }
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( Is_T_Lock ) ) {
+        if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+            e= R_OSPL_Start_T_Lock();
+            if(e!=0) {
+                goto fin;
+            }
+            is_lock = true;  /* T-Lock to "self" */
+        }
+    }
+#endif
+
+    self->Area       = Area;
+    self->Count      = 0;
+    self->MaxCount   = (int_fast32_t)( AreaByteSize / sizeof( r_ospl_table_block_t ) );
+    self->KeyCache   = NULL;
+    self->FirstFreeIndex = 0;
+#if R_OSPL_IS_PREEMPTION
+    self->Is_T_Lock  = Is_T_Lock;
+#else
+    R_UNREFERENCED_VARIABLE( Is_T_Lock );
+#endif
+
+    /* Set "self->Area[].NextFreeIndex" */
+    {
+        r_ospl_table_block_t *const  block_array = (r_ospl_table_block_t *) Area;
+        int_fast32_t                 index;
+        int_fast32_t const           max_index = self->MaxCount - 1;
+
+        IF_DQ( block_array == NULL ) {
+#ifndef R_OSPL_NDEBUG
+            e=E_OTHERS;
+#endif
+            goto fin;
+        }
+
+        for ( index = 0;  index < max_index;  index += 1 ) {
+            block_array[ index ].NextFreeIndex = (int16_t)( index + 1 );
+        }
+        block_array[ max_index ].NextFreeIndex = (int16_t) R_OSPL_TABLE_BLOCK_NO_NEXT;
+    }
+
+#ifndef R_OSPL_NDEBUG
+    e=0;
+#endif
+fin:
+    R_NOOP();/* for following all #if is false */
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_GetIndex
+************************************************************************/
+errnum_t  R_OSPL_TABLE_GetIndex( r_ospl_table_t *const  self,  const void *const  Key,
+                                 int_fast32_t *const  out_Index,  r_ospl_if_not_t const  TypeOfIfNot )
+{
+    errnum_t  e;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Index == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( self->Is_T_Lock ) ) {
+        if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+            e= R_OSPL_Start_T_Lock();
+            if(e!=0) {
+                goto fin;
+            }
+            is_lock = true;  /* T-Lock to "self" */
+        }
+    }
+#endif
+
+
+    if ( (Key == self->KeyCache)  &&  (self->Count >= 1) ) {
+        *out_Index = self->IndexCache;
+    } else {
+        r_ospl_table_searched_t      searched;
+        r_ospl_table_block_t *const  block_array = self->Area;
+        int_fast32_t                 found_index;
+
+        R_OSPL_TABLE_Search_Sub( self, Key, &searched );
+
+        if ( ! searched.IsFound ) {
+            int_fast32_t  so_index;  /* sorted_key_index */
+            int_fast32_t  first_index;  /* FirstFreeIndex */
+
+            if ( TypeOfIfNot == R_OSPL_ALLOCATE_IF_NOT ) {
+                if ( self->Count == self->MaxCount ) {
+                    e = E_FEW_ARRAY;
+                    goto fin;
+                }
+
+                /* Insert and Set "block_array[ searched.SortedKeyIndex ].Key" */
+                for ( so_index = self->Count - 1;
+                        so_index >= searched.SortedKeyIndex;
+                        so_index -= 1 ) {
+                    block_array[ so_index + 1 ].Key   = block_array[ so_index ].Key;
+                    block_array[ so_index + 1 ].Index = block_array[ so_index ].Index;
+                }
+                block_array[ searched.SortedKeyIndex ].Key = Key;
+                self->Count += 1;
+
+                /* Set "block_array[ searched.SortedKeyIndex ].Index" */
+                first_index = self->FirstFreeIndex;
+                block_array[ searched.SortedKeyIndex ].Index = (int16_t) first_index;
+                self->FirstFreeIndex = block_array[ first_index ].NextFreeIndex;
+                block_array[ first_index ].NextFreeIndex = R_OSPL_TABLE_BLOCK_USED;
+
+            } else if ( TypeOfIfNot == R_OSPL_ERROR_IF_NOT ) {
+                e = E_NOT_FOUND_SYMBOL;
+                goto fin;
+            } else { /* TypeOfIfNot == R_OSPL_DO_NOTHING_IF_NOT */
+                e = 0;
+                goto fin;
+            }
+            /* Don't use "IF", Because this function called from "IF". */
+        }
+
+        self->KeyCache = Key;
+        found_index = block_array[ searched.SortedKeyIndex ].Index;
+        self->IndexCache = found_index;
+        *out_Index = found_index;
+    }
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_Free
+************************************************************************/
+void  R_OSPL_TABLE_Free( r_ospl_table_t *const  self,  const void *const  Key )
+{
+#if  ! defined( R_OSPL_NDEBUG ) ||  R_OSPL_IS_PREEMPTION
+    errnum_t  e;
+#endif
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+    r_ospl_table_searched_t  searched;
+
+    IF_DQ( self == NULL ) {
+#ifndef R_OSPL_NDEBUG
+        e=0;
+#endif
+        goto fin;
+    }
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        if(e!=0) {
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "gs_global_error" */
+    }
+#endif
+
+    R_OSPL_TABLE_Search_Sub( self, Key, &searched );
+
+    if ( IS( searched.IsFound ) ) {
+        r_ospl_table_block_t *const  block_array = self->Area;
+        int_fast32_t                 so_index;  /* sorted_key_index */
+        int_fast32_t                 first_index;  /* FirstFreeIndex */
+        int_fast32_t const           count_ = self->Count;  /* _ is for MISRA 5.6 */
+
+        /* Set "FirstFreeIndex", ".NextFreeIndex" */
+        first_index = self->FirstFreeIndex;
+        self->FirstFreeIndex = block_array[ searched.SortedKeyIndex ].Index;
+        block_array[ self->FirstFreeIndex ].NextFreeIndex = (int16_t) first_index;
+
+        /* Remove one "r_ospl_table_block_t" */
+        /* Set "self->KeyCache" */
+        if ( searched.SortedKeyIndex < count_ ) {
+            for ( so_index = searched.SortedKeyIndex;  so_index < count_ ;  so_index += 1 ) {
+                block_array[ so_index ].Key   = block_array[ so_index + 1 ].Key;
+                block_array[ so_index ].Index = block_array[ so_index + 1 ].Index;
+            }
+            self->KeyCache   = block_array[ searched.SortedKeyIndex ].Key;
+            self->IndexCache = block_array[ searched.SortedKeyIndex ].Index;
+        } else if ( searched.SortedKeyIndex > 0 ) { /* searched.SortedKeyIndex >= 1 */
+            self->KeyCache   = block_array[ searched.SortedKeyIndex - 1 ].Key;
+            self->IndexCache = block_array[ searched.SortedKeyIndex - 1 ].Index;
+        } else {
+            self->KeyCache = NULL;
+        }
+        self->Count -= 1;
+    }
+
+#if  ! defined( R_OSPL_NDEBUG )
+    e=0;
+#endif
+fin:
+    R_NOOP();/* for following all #if is false */
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_Search_Sub
+************************************************************************/
+static void  R_OSPL_TABLE_Search_Sub( const r_ospl_table_t *const  self,
+                                      const void *const  Key,  r_ospl_table_searched_t *const  out_Searched )
+{
+    int_fast32_t     left;
+    int_fast32_t     right;
+    int_fast32_t     middle;
+    /* ->QAC 0306 : Sort by pointer value */
+    uintptr_t const  target_key = (uintptr_t) Key;
+    /* <-QAC 0306 */
+    uintptr_t        middle_key;
+    enum {           num_2 = 2 };  /* SEC M1.10.1, QAC-3132 */
+    r_ospl_table_block_t  *array;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+    IF_DQ( out_Searched == NULL ) {
+        goto fin;
+    }
+
+    array = self->Area;
+
+
+    if ( self->Count == 0 ) {
+        out_Searched->SortedKeyIndex = 0;
+        out_Searched->IsFound = false;
+    } else {
+        left = 0;
+        right = self->Count - 1;
+
+        while ( (right - left) >= num_2 ) {
+            middle = (int_fast32_t)( (uint_fast32_t)( right + left ) / num_2 );
+            /* ->QAC 0306 : Sort by pointer value */
+            middle_key = (uintptr_t) array[ middle ].Key;
+            /* <-QAC 0306 */
+
+            if ( target_key == middle_key ) {
+                out_Searched->SortedKeyIndex = middle;
+                out_Searched->IsFound = true;
+                goto fin;
+            } else if ( target_key <  middle_key ) {
+                right = (int_fast32_t)( middle - 1 );
+            } else {
+                left = (int_fast32_t)( middle + 1 );
+            }
+        }
+
+        /* ->QAC 0306 : Sort by pointer value */
+        if ( target_key == (uintptr_t) array[ left ].Key ) {
+            out_Searched->SortedKeyIndex = left;
+            out_Searched->IsFound = true;
+        } else if ( target_key == (uintptr_t) array[ right ].Key ) {
+            out_Searched->SortedKeyIndex = right;
+            out_Searched->IsFound = true;
+        } else if ( target_key < (uintptr_t) array[ left ].Key ) {
+            out_Searched->SortedKeyIndex = left;
+            out_Searched->IsFound = false;
+        } else if ( target_key > (uintptr_t) array[ right ].Key ) {
+            out_Searched->SortedKeyIndex = right + 1;
+            out_Searched->IsFound = false;
+        } else {
+            out_Searched->SortedKeyIndex = right;
+            out_Searched->IsFound = false;
+        }
+        /* <-QAC 0306 */
+    }
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_Print
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+void  R_OSPL_TABLE_Print( r_ospl_table_t *const  self )
+{
+    int_fast32_t  so_index;  /* sorted_key_index */
+    int_fast32_t  index;
+    r_ospl_table_block_t *const  array = self->Area;
+
+    printf( "R_OSPL_TABLE_Print: r_ospl_table_t 0x%08X\n", (uintptr_t) self );
+    printf( "    .Count = %d\n", self->Count );
+    for ( so_index = 0;  so_index < self->Count;  so_index += 1 ) {
+        printf( "    .Area[%d].Key, Index = 0x%08X, %d\n",
+                so_index,  (uintptr_t) array[ so_index ].Key,  array[ so_index ].Index );
+    }
+    printf( "    .FirstFreeIndex = %d\n", self->FirstFreeIndex );
+    for ( index = 0;  index < self->MaxCount;  index += 1 ) {
+        printf( "    .Area[%d].NextFreeIndex = %d\n", index,  array[ index ].NextFreeIndex );
+    }
+    printf( "        %d = R_OSPL_TABLE_BLOCK_NO_NEXT\n", R_OSPL_TABLE_BLOCK_NO_NEXT );
+    printf( "        %d = R_OSPL_TABLE_BLOCK_USED\n", R_OSPL_TABLE_BLOCK_USED );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_CallInterruptCallback
+************************************************************************/
+void  R_OSPL_CallInterruptCallback( const r_ospl_caller_t *const  self,
+                                    const r_ospl_interrupt_t *const  InterruptSource )
+{
+    errnum_t  e;
+    r_ospl_async_t  *async;
+#if ! R_OSPL_IS_PREEMPTION
+    r_ospl_master_t *const  gs_master = R_OSPL_GetPrivateContext();
+    r_ospl_thread_def_t  *current_thread = NULL;  /* NULL is for avoid QAC 3353 */
+#endif
+#if R_OSPL_ERROR_BREAK
+    static int_fast32_t  gs_nested_interrupt_level = 0;
+#endif
+
+#if R_OSPL_ERROR_BREAK
+    gs_nested_interrupt_level += 1;
+#endif
+
+#if ! R_OSPL_IS_PREEMPTION
+    IF_DQ( gs_master == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if R_OSPL_CPU_LOAD
+    e= gs_master->IdleCallback( R_OSPL_INTERRUPT_START );
+    IF(e) {
+        goto fin;
+    }
+#endif
+
+    current_thread = gs_master->CurrentThread;
+#endif
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( self->Async == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    async = self->Async;
+
+    ASSERT_D( ( async->Flags & R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK ) ==
+              R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE,  e=E_OTHERS; goto fin );
+    /* If failed, memory area of "Async" variable was overwritten by other variable. */
+    /* Reason of failed may be not disabled interrupt */
+    /* or not called "*_I_LOCK_Unlock()" disabling interrupt by "*_I_LOCK_Disable()". */
+
+    IF_DQ( self->PointerToState == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( async->InterruptCallback == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if ! R_OSPL_IS_PREEMPTION
+    gs_master->CurrentThread = NULL;  /* Interrupt */
+#endif
+
+    *self->PointerToState = self->StateValueOfOnInterrupting;
+
+
+
+    e= async->InterruptCallback( InterruptSource, self );  /* Main of callback */
+
+
+
+    if ( e != 0 ) {
+        if ( async->ReturnValue == 0 ) {
+            async->ReturnValue = e;
+        }
+        R_OSPL_CLEAR_ERROR();
+    }
+
+    e=0;
+fin:
+#if ! R_OSPL_IS_PREEMPTION
+    IF_DQ ( gs_master == NULL ) {}
+    else {
+        gs_master->CurrentThread = current_thread;
+
+#if R_OSPL_CPU_LOAD
+        {
+            errnum_t  ee;
+
+            ee= gs_master->IdleCallback( R_OSPL_INTERRUPT_END );
+            e= R_OSPL_MergeErrNum( e, ee );
+        }
+#endif
+    }
+#endif
+
+
+#if R_OSPL_ERROR_BREAK
+    gs_nested_interrupt_level -= 1;
+
+    if ( gs_nested_interrupt_level == 0 ) {
+        if ( gs_master != NULL ) {
+            current_thread = gs_master->CurrentThread;
+            gs_master->CurrentThread = NULL;
+        }
+
+
+        R_DEBUG_BREAK_IF_ERROR();
+
+
+        if ( gs_master != NULL ) {
+            gs_master->CurrentThread = current_thread;
+        }
+    }
+#endif
+    R_UNREFERENCED_VARIABLE( e );
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_SetErrNum
+************************************************************************/
+#if  R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_SetErrNum( errnum_t const  e )
+{
+    r_ospl_error_t  *err;
+
+    if ( e != 0 ) {
+
+        err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+        if ( err != NULL ) {
+            if ( err->ErrNum == 0 ) {
+                err->ErrNum = e;
+            }
+        }
+    }
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GetErrNum
+************************************************************************/
+#if  R_OSPL_TLS_ERROR_CODE
+errnum_t  R_OSPL_GetErrNum(void)
+{
+    errnum_t         e;
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+    if ( err != NULL ) {
+        e = err->ErrNum;
+    } else {
+        e = E_NO_DEBUG_TLS;
+    }
+
+    return  e;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_CLEAR_ERROR
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_CLEAR_ERROR(void)
+{
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_DO_NOTHING_IF_NOT );
+
+    if ( err != NULL ) {
+#if R_OSPL_ERROR_BREAK
+        err->IsError = false;
+#endif
+
+#if R_OSPL_TLS_ERROR_CODE
+        err->ErrNum = 0;
+#endif
+    }
+}
+#endif
+
+
+/**
+* @brief   Function part of error break
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_OSPL_ERROR_BREAK
+static bool_t  R_OSPL_OnRaisingError_Sub( const char_t *const  FilePath,
+        int_fast32_t const  LineNum );  /* QAC-3450 */
+static bool_t  R_OSPL_OnRaisingError_Sub( const char_t *const  FilePath,
+        int_fast32_t const  LineNum )
+{
+#if  ! defined( R_OSPL_NDEBUG ) ||  R_OSPL_IS_PREEMPTION
+    errnum_t         e;
+#endif
+    bool_t           is_break = false;
+#if R_OSPL_IS_PREEMPTION
+    bool_t           is_lock = false;
+#endif
+    r_ospl_error_t  *err;
+
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+
+    if ( err != NULL ) {
+        if ( IS( err->IsError ) ) {
+            is_break = false;
+        } else {
+#if R_OSPL_IS_PREEMPTION
+            if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+                e= R_OSPL_Start_T_Lock();
+                if(e!=0) {
+                    goto fin;
+                }
+                is_lock = true;  /* T-Lock to "gs_global_error" */
+            }
+#endif
+
+            gs_global_error.RaisedGlobalErrorID ++;
+            is_break = ( gs_global_error.RaisedGlobalErrorID ==
+                         gs_global_error.BreakGlobalErrorID );
+
+            err->IsError = true;
+            err->ErrorID = gs_global_error.RaisedGlobalErrorID;
+            err->FilePath = FilePath;
+            err->LineNum = LineNum;
+        }
+    }
+
+#ifndef R_OSPL_NDEBUG
+    e=0;
+#endif
+#if R_OSPL_IS_PREEMPTION
+fin:
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+    return  is_break;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_OnRaisingErrorForMISRA
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+bool_t  R_OSPL_OnRaisingErrorForMISRA( bool_t const  Condition,  const char_t *const  File,
+                                       int_t const  Line )
+{
+    if ( IS( Condition ) ) {
+        if ( R_OSPL_OnRaisingError_Sub( File, Line ) != 0 ) {
+            R_DebugBreak( File, Line );
+        }
+    }
+    return  Condition;
+}
+#endif
+
+
+/**
+* @brief   Function part of <R_DEBUG_BREAK_IF_ERROR>
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_DebugBreakIfError( const char_t *const  File,  int_t const  Line )
+{
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_DO_NOTHING_IF_NOT );
+
+    if ( err != NULL  &&  err->IsError ) {
+        /* See the value of "err->ErrorID" in watch window. */
+        /* Call R_OSPL_SET_BREAK_ERROR_ID( N ); at main function. */
+        printf( "<ERROR error_ID=\"0x%X\" file=\"%s(%d)\"/>\n",
+                err->ErrorID, err->FilePath, err->LineNum );
+        R_DebugBreak( File, Line );
+    }
+
+    R_OSPL_CLEAR_ERROR();
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GET_ERROR_ID
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+int_fast32_t  R_OSPL_GET_ERROR_ID(void)
+{
+    return  gs_global_error.RaisedGlobalErrorID;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_SET_BREAK_ERROR_ID
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_BREAK_ERROR_ID( int_fast32_t const  ErrorID )
+{
+#ifndef R_OSPL_NDEBUG
+    if ( gs_global_error.BreakGlobalErrorID != ErrorID ) {
+        printf( ">R_OSPL_SET_BREAK_ERROR_ID( %d );\n", ErrorID );
+    }
+#endif
+
+    gs_global_error.BreakGlobalErrorID = ErrorID;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GetCurrentThreadError
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+r_ospl_error_t  *R_OSPL_GetCurrentThreadError(void)
+{
+    return  R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+}
+#endif
+
+
+/**
+* @brief   GetCurrentThreadError
+*
+* @param   TypeOfIfNot <r_ospl_if_not_t>
+* @return  Error information of current thread
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_error_t  *R_OSPL_GetCurrentThreadError_Sub( r_ospl_if_not_t const  TypeOfIfNot )
+{
+    errnum_t            e;
+    int_fast32_t        index;
+    r_ospl_error_t     *err = NULL;
+    r_ospl_thread_id_t  th;  /* QAC 3441 */
+
+    index = R_OSPL_NO_INDEX;
+
+    th = R_OSPL_THREAD_GetCurrentId();
+    e= R_OSPL_TABLE_GetIndex( &gs_global_error.ThreadIndexTable, th, &index, TypeOfIfNot );
+    if ( e == E_FEW_ARRAY ) {
+#ifndef R_OSPL_NDEBUG
+        if ( gs_global_error.ThreadIndexTable.Area == gs_thread_index_table_body ) {
+            e = E_NO_DEBUG_TLS;
+        }
+#endif
+        goto fin;
+    }
+    if ( e != 0 ) {
+        goto fin;
+    }
+
+    if ( index != R_OSPL_NO_INDEX ) {
+        IF_DQ( gs_global_error.ErrorArray == NULL ) {
+#ifndef R_OSPL_NDEBUG
+            e=E_OTHERS;
+#endif
+            goto fin;
+        }
+        IF_DQ( index < -1 ) {
+#ifndef R_OSPL_NDEBUG
+            e=E_OTHERS;
+#endif
+            goto fin;
+        }
+
+        err = &gs_global_error.ErrorArray[ index ];
+    }
+
+#ifndef R_OSPL_NDEBUG
+    e=0;
+#endif
+fin:
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+        /* If e == 2 (E_FEW_ARRAY), Set big work area by "R_OSPL_SET_DEBUG_WORK". */
+        /* If e == 29 (E_NO_DEBUG_TLS), Call "R_OSPL_SET_DEBUG_WORK". */
+    }
+#endif
+
+    return  err;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_SET_DEBUG_WORK
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_DEBUG_WORK( void *const  WorkArea,  uint32_t const  WorkAreaSize )
+{
+    errnum_t               e;
+    int_fast32_t           count = WorkAreaSize / R_OSPL_DEBUG_WORK_1_SIZE;
+    uint8_t               *work = WorkArea;
+    r_ospl_table_block_t  *thread_index_array;
+    r_ospl_error_t        *error_array;
+    int_fast32_t           index;
+#if R_OSPL_IS_PREEMPTION
+    bool_t                 is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        if(e!=0) {
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "gs_global_error" */
+    }
+#endif
+
+
+    if ( gs_global_error.ThreadIndexTable.Area != gs_thread_index_table_body ) {
+        e = E_ACCESS_DENIED;
+        goto fin;
+    }
+
+    thread_index_array = (r_ospl_table_block_t *) &work[0];
+    error_array = (r_ospl_error_t *) &thread_index_array[ count ];
+    ASSERT_D( (uint8_t *) &error_array[ count ] <= &work[ WorkAreaSize ],  e=E_FEW_ARRAY; goto fin );
+
+    R_OSPL_TABLE_InitConst( &gs_global_error.ThreadIndexTable,
+                            thread_index_array,  count * sizeof( thread_index_array[0] ), true );
+
+    e= R_OSPL_TABLE_GetIndex( &gs_global_error.ThreadIndexTable,
+                              gs_thread_index_table_body[0].Key, &index, R_OSPL_ALLOCATE_IF_NOT );
+    if(e!=0) {
+        goto fin;
+    }
+
+    gs_global_error.ErrorArray = error_array;
+    gs_global_error.ErrorArray[ index ] = gs_error;
+
+#ifndef R_OSPL_NDEBUG
+    memset( gs_thread_index_table_body, 0xFE, sizeof(gs_thread_index_table_body) );
+    memset( &gs_error, 0xFE, sizeof(gs_error) );
+#endif
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_MODIFY_THREAD_LOCKED_COUNT
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  &&  R_OSPL_IS_PREEMPTION
+void  R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus )
+{
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+    if ( err != NULL ) {
+        err->ThreadLockedCount += Plus;
+    }
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GET_THREAD_LOCKED_COUNT
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  &&  R_OSPL_IS_PREEMPTION
+int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void)
+{
+    int_fast32_t  count;
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+    if ( err != NULL ) {
+        count = err->ThreadLockedCount;
+    } else {
+        count = 0;
+    }
+
+    return  count;
+}
+#endif
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/README.md	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,199 @@
+# **Mbed Library for GR-Boards**  mbed-gr-libs
+**Please see [here](README_JPN.md) for Japanese version.**  
+GR-PEACH, GR-LYCHEE and RZ/A2M board library group. The library includes the following functions.  
+* Connect camera and LCD
+* Connect USB memory and SD card
+* Cache control
+* JPEG conversion
+* RGA library (GR-PEACH only)
+* Audio playback
+* USB Host
+* ESP32 AT command library
+* DisplayApp (Image display on PC display with USB connection)
+* ASCII font
+* Communication speed of SD card
+* DRP (RZ/A2M only)
+
+
+## Connect camera and LCD
+By using ``EasyAttach_CameraAndLCD``, it is easy to connect the camera and the LCD.  
+Sample code : [GR-Boads_Camera_LCD_sample](https://github.com/d-kato/GR-Boads_Camera_LCD_sample)  
+Details : [EasyAttach_CameraAndLCD/README.md](EasyAttach_CameraAndLCD/README.md)
+
+
+## Connect USB memory and SD card
+By using ``SdUsbConnect class`` you can easily connect USB memory and SD card.  
+If both devices are inserted, connect to the device you detected earlier.
+```cpp
+#include "SdUsbConnect.h"
+
+int main() {
+  SdUsbConnect storage("storage");
+
+  // wait connect
+  storage.wait_connect();
+
+  while (1) {
+    // check connect
+    if (!storage.connected()) { // disconnect
+      printf("disconnect\r\n");
+      break;
+    }
+
+    FILE * fp = fopen("/storage/test.txt", "rb");
+    char buf[32];
+    fread(buf, sizeof(char), 32, fp);
+    printf("%s", buf);
+    fclose(fp);
+  }
+}
+```
+Sample code : [GR-Boards_Audio_WAV](https://github.com/d-kato/GR-Boards_Audio_WAV)  
+
+
+## Cache control
+When using DMA, you need to be conscious of cache control. DMA is an abbreviation of Direct Memory Access, and it accesses memory without CPU intervention.  
+When writing data using the CPU, such as `buf [0] = 0x01` or `memcpy (buf, data, 64)`, it write to the cache rather than the real memory.  
+If you try to transfer `buf` data with DMA in this state, the intended data can not be transferred because the actual memory has not been written yet.  
+Conversely, when accessing data transferred by DMA using the CPU, if dust remains on the cache, it reads dust on the cache instead of the actual memory.  
+When mbed code is used, both GR-PEACH and GR-LYCHEE prepare a 1 MB non-cacheable area (`NC_BSS` section).  
+When using DMA, using this non-cache memory makes control easier.  
+```cpp
+// non-cacheable
+#if defined(__ICCARM__)
+static uint8_t buf[64]@ ".mirrorram";
+#else
+static uint8_t buf[64]__attribute((section("NC_BSS")));
+#endif
+
+void dma_send_func() {
+  buf[0] = 0x01;
+  DMA_send(buf); // DMA send
+}
+
+void dma_recv_func() {
+  DMA_recv(buf); // DMA receive
+  printf("%d\r\n", buf[0]);
+}
+```
+
+If non-cache memory is not used, the following cache control is required.  
+It is necessary to align 32 bytes of memory for cache control and make the size a multiple of 32 bytes.  
+
+```cpp
+#include "dcache-control.h" // Add header for cache control
+
+// Always align memory to cache control to 32 bytes, make it multiple of 32 bytes
+#if defined(__ICCARM__)
+#pragma data_alignment=32
+static uint8_t buf[64];
+#else
+static uint8_t buf[64]__attribute((aligned(32)));
+#endif
+
+void dma_send_func() {
+  buf[0] = 0x01;
+  dcache_clean(buf, sizeof(buf)); // Write data on cache to real memory
+  DMA_send(buf); //DMA send
+}
+
+void dma_recv_func() {
+  dcache_invalid(buf, sizeof(buf)); // Discard the data on the cache in advance
+  DMA_recv(buf); //DMA receive
+  printf("%d\r\n", buf[0]);
+}
+```
+
+
+## JPEG conversion
+DMA is used for JPEG conversion. See above ``Cache control``.  
+Sample code : [GR-Boads_Camera_sample](https://github.com/d-kato/GR-Boads_Camera_sample)  
+Details : [GraphicsFramework](https://developer.mbed.org/teams/Renesas/code/GraphicsFramework/)
+
+
+## RGA library (GR-PEACH only)
+Details : [GraphicsFramework](https://developer.mbed.org/teams/Renesas/code/GraphicsFramework/)
+
+
+## Audio playback
+Using the ``EasyPlayback class`` you can easily playback audio.  
+Sample code : [GR-Boards_Audio_WAV](https://github.com/d-kato/GR-Boards_Audio_WAV)  
+
+
+## USB Host
+Official USB host function is not yet implemented in mbed OS. I changed USBHost used by mbed classic so that it can be used with mbed OS 5.  
+Details : [USBHost](https://developer.mbed.org/handbook/USBHost)  
+Supplement: The USBHostMSD class has been changed considerably according to the specification of mbed OS 5.4. Please refer to ``SdUsbConnect class`` for USB memory connection.  
+
+
+## ESP32 AT command library
+By using ``ESP32Interface class`` you can do WiFi communication.  
+Details : [TCPSocketWiFi_Example_for_ESP32](https://github.com/d-kato/TCPSocketWiFi_Example_for_ESP32)  
+
+
+## DisplayApp (Image display on PC display with USB connection)
+This is a library for displaying JPEG images in the GR-Board on the PC. Connect the USB cable to ``MicroUSB Connector (RZ/A1 Ch.0)``.  
+
+![](docs/img/usb0_and_button.jpg)  
+
+For RZ / A2M, connect to ``USB CH.0``.  
+If your PC isn't Windows10, you need to install the specified driver from the below URL.  
+
+https://os.mbed.com/handbook/USBSerial
+
+Unfortunately, since that is "Unsigned driver", you cannot install as is depending on your Windows version. Since the setting method is different for each PC, please search with "Unsigned driver" keyword on the search site.  
+
+Applications for PC can be downloaded from the following.  
+* [For Windows](http://gadget.renesas.com/software/displayapp.zip)  
+* [For Mac](http://gadget.renesas.com/software/DisplayApp.app.zip)  
+
+Example  
+```cpp
+#include "DisplayApp.h"
+#include "mbed.h"
+
+static uint8_t jpeg_image[] = {/* JPEG image data */};
+
+int main() {
+    DisplayApp display_app;
+
+    while (1) {
+        display_app.SendJpeg(&jpeg_image[0], sizeof(jpeg_image));
+        wait(1);
+    }
+}
+```
+
+
+## ASCII font
+By using ``AsciiFont class`` you can draw ASCII code characters.  
+
+```cpp
+#include "mbed.h"
+#include "AsciiFont.h"
+
+#define WIDTH           (12)
+#define HEIGHT          (16)
+#define BYTE_PER_PIXEL  (1u)
+#define STRIDE          (((WIDTH * BYTE_PER_PIXEL) + 7u) & ~7u) //multiple of 8
+
+uint8_t text_field[STRIDE * HEIGHT];
+
+int main() {
+    AsciiFont ascii_font(text_field, WIDTH, HEIGHT, STRIDE, BYTE_PER_PIXEL);
+
+    ascii_font.Erase(0xcc);  // Erase text field
+    ascii_font.DrawStr("AB", 0, 0, 0x11, 1);
+    ascii_font.DrawChar('C', AsciiFont::CHAR_PIX_WIDTH, AsciiFont::CHAR_PIX_HEIGHT, 0x22, 1);
+}
+```
+
+## Communication speed of SD card
+RZ/A2M communicates with SD speed class. If you need HS speed class or UHS speed class with RZ/A2M, please contact us from [here](https://www.renesas.com/jp/en/support/contact.html).  
+GR-PEACH and GR-LYCHEE access an SD Card using SPI bus.  
+Please refer to ``SdUsbConnect class`` for connection.  
+
+
+## DRP (RZ/A2M only)
+DRP(Dynamically Reconfigurable Processor) is the programmable hardware which have both the flexibility of software and the speed of hardware. The firmware which define processing, can be renewed immediately.  
+Please see ``drp-for-mbed/TARGET_RZ_A2XX/r_drp/doc`` for details.  

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/README_JPN.md	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,197 @@
+# **Mbed GRボード用ライブラリ**  mbed-gr-libs
+GR-PEACH、GR-LYCHEE、RZ/A2Mボード用のライブラリ群です。ライブラリには以下の機能が含まれます。  
+* カメラとLCDの接続
+* USBメモリとSDカードの接続
+* キャッシュ制御
+* JPEG変換
+* RGAライブラリ (GR-PEACHのみ)
+* オーディオ再生
+* USBホスト
+* ESP32 ATコマンド用ライブラリ
+* DisplayApp (USB接続でPCディスプレイに画像表示)
+* ASCIIフォント
+* SDカードの通信速度
+* DRP (RZ/A2Mのみ)
+
+## カメラとLCDの接続
+``EasyAttach_CameraAndLCD``を使うことで、カメラとLCDの接続を簡単に行うことができます。  
+サンプルコード：[GR-Boads_Camera_LCD_sample](https://github.com/d-kato/GR-Boads_Camera_LCD_sample)  
+詳細は [EasyAttach_CameraAndLCD/README.md](EasyAttach_CameraAndLCD/README.md) を参照ください。
+
+
+## USBメモリとSDカードの接続
+``SdUsbConnectクラス``を使うことで、USBメモリとSDカードの接続を簡単に行うことができます。  
+両方のデバイスが挿入されている場合は、先に検出した方のデバイスに接続します。
+```cpp
+#include "SdUsbConnect.h"
+
+int main() {
+  SdUsbConnect storage("storage");
+
+  // 接続待ち
+  storage.wait_connect();
+
+  while (1) {
+    // 接続確認
+    if (!storage.connected()) { // 切断
+      printf("disconnect\r\n");
+      break;
+    }
+
+    FILE * fp = fopen("/storage/test.txt", "rb");
+    char buf[32];
+    fread(buf, sizeof(char), 32, fp);
+    printf("%s", buf);
+    fclose(fp);
+  }
+}
+```
+サンプルコード：[GR-Boards_Audio_WAV](https://github.com/d-kato/GR-Boards_Audio_WAV)  
+
+
+## キャッシュ制御
+DMAを使用する際はキャッシュ制御を意識する必要があります。DMAは、Direct Memory Accessの略で、CPUを介さずにメモリにアクセスします。  
+`buf[0] = 0x01;`や`memcpy(buf, data, 64)`など、CPUを使ったデータ書き込みを行う場合、通常は実メモリではなくキャッシュへの書き込みが行われます。  
+この状態で`buf`のデータをDMAで転送しようとした場合、まだ実メモリには書き込みが行われていないため、意図したデータの転送ができません。  
+また逆に、DMAで転送されたデータに対してCPUを使ったアクセスをする場合、キャッシュ上にゴミが残ったままですと実メモリではなくキャッシュ上のゴミを読み込んでしまいます。  
+mbedコードを使用する場合、GR-PEACH、GR-LYCHEEは共に、1MBの非キャッシュ領域(`NC_BSS`セクション)を用意しています。  
+DMAを使用する場合はこの非キャッシュメモリを使用すると制御が楽になります。  
+```cpp
+//非キャッシュメモリ
+#if defined(__ICCARM__)
+static uint8_t buf[64]@ ".mirrorram";
+#else
+static uint8_t buf[64]__attribute((section("NC_BSS")));
+#endif
+
+void dma_send_func() {
+  buf[0] = 0x01;
+  DMA_send(buf); //DMA送信
+}
+
+void dma_recv_func() {
+  DMA_recv(buf); //DMA受信
+  printf("%d\r\n", buf[0]);
+}
+```
+
+非キャッシュメモリをを使用しない場合は、以下のようなキャッシュ制御が必要となります。  
+キャッシュ制御を行うメモリは必ず32byteアラインにし、サイズを32byteの倍数にしておく必要があります。
+
+```cpp
+#include "dcache-control.h" //★キャッシュ制御用のヘッダを追加
+
+//通常メモリに配置 キャッシュ制御を行うメモリは必ず32byteにアライン、32byteの倍数にする
+#if defined(__ICCARM__)
+#pragma data_alignment=32
+static uint8_t buf[64];
+#else
+static uint8_t buf[64]__attribute((aligned(32)));
+#endif
+
+void dma_send_func() {
+  buf[0] = 0x01;
+  dcache_clean(buf, sizeof(buf)); //★キャッシュ上のデータを実メモリに書き込む
+  DMA_send(buf); //DMA送信
+}
+
+void dma_recv_func() {
+  dcache_invalid(buf, sizeof(buf)); //★あらかじめキャッシュ上のデータを破棄しておく
+  DMA_recv(buf); //DMA受信
+  printf("%d\r\n", buf[0]);
+}
+```
+
+
+## JPEG変換
+JPEG変換にはDMAが使用されます。上記``キャッシュ制御`` を参照ください。  
+その他の詳細は[GraphicsFramework](https://developer.mbed.org/teams/Renesas/code/GraphicsFramework/)を参照ください。  
+サンプルコード：[GR-Boads_Camera_sample](https://github.com/d-kato/GR-Boads_Camera_sample)  
+
+
+## RGAライブラリ(GR-PEACHのみ)
+[GraphicsFramework](https://developer.mbed.org/teams/Renesas/code/GraphicsFramework/)を参照ください。
+
+
+## オーディオ再生
+``EasyPlaybackクラス``を使うことで、簡単にオーディオを再生することができます。  
+サンプルコード：[GR-Boards_Audio_WAV](https://github.com/d-kato/GR-Boards_Audio_WAV)  
+
+
+## USBホスト
+mbed OSではオフィシャルのUSBホスト機能はまだ実装されていません。mbed classicで使用していたUSBHostをmbed OS 5で使用できるように変更しています。  
+詳細は[USBHost](https://developer.mbed.org/handbook/USBHost)を参照ください。  
+補足：USBHostMSDクラスはmbed OS 5.4の仕様に合わせて大幅に変更しています。USBメモリ接続の際は``SdUsbConnectクラス``を参照ください。  
+
+
+## ESP32 ATコマンド用ライブラリ
+``ESP32Interfaceクラス``を使うことで、WiFi通信を行うことができます。  
+詳細は[TCPSocketWiFi_Example_for_ESP32](https://github.com/d-kato/TCPSocketWiFi_Example_for_ESP32)を参照ください。  
+
+
+## DisplayApp (USB接続でPCディスプレイに画像表示)
+GR-Board内のJPEG画像をPC上に表示するためのライブラリです。GR-BoardとPCをUSBで接続して使用します。USBケーブルは``MicroUSB Connector(RZ/A1 Ch.0)``に接続してください。  
+
+![](docs/img/usb0_and_button.jpg)  
+
+RZ/A2Mの場合は``USBチャネル1``に接続してください。  
+Windows10以外ご使用の場合、ドライバのインストールが必要となります。下記サイトのからドライバーをダウンロードできます。  
+
+https://os.mbed.com/handbook/USBSerial
+
+但し、「署名なしドライバ」となっていますので、お使いのWindowsバージョンによってはそのままインストールすることはできません。お使いのPC毎に設定方法が異なるため、検索サイトで「署名なしドライバ」で検索してください。  
+
+PC用アプリは以下よりダウンロードできます。  
+* [For Windows](http://gadget.renesas.com/software/displayapp.zip)  
+* [For Mac](http://gadget.renesas.com/software/DisplayApp.app.zip)  
+
+使用例
+```cpp
+#include "DisplayApp.h"
+#include "mbed.h"
+
+static uint8_t jpeg_image[] = {/* JPEG image data */};
+
+int main() {
+    DisplayApp display_app;
+
+    while (1) {
+        display_app.SendJpeg(&jpeg_image[0], sizeof(jpeg_image));
+        wait(1);
+    }
+}
+```
+
+
+## ASCIIフォント
+``AsciiFontクラス``を使うことで、ASCIIコードの文字を描画できます。  
+
+```cpp
+#include "mbed.h"
+#include "AsciiFont.h"
+
+#define WIDTH           (12)
+#define HEIGHT          (16)
+#define BYTE_PER_PIXEL  (1u)
+#define STRIDE          (((WIDTH * BYTE_PER_PIXEL) + 7u) & ~7u) //multiple of 8
+
+uint8_t text_field[STRIDE * HEIGHT];
+
+int main() {
+    AsciiFont ascii_font(text_field, WIDTH, HEIGHT, STRIDE, BYTE_PER_PIXEL);
+
+    ascii_font.Erase(0xcc);  // Erase text field
+    ascii_font.DrawStr("AB", 0, 0, 0x11, 1);
+    ascii_font.DrawChar('C', AsciiFont::CHAR_PIX_WIDTH, AsciiFont::CHAR_PIX_HEIGHT, 0x22, 1);
+}
+```
+
+## SDカードの通信速度
+RZ/A2MはSDスピードクラスで通信を行います。RZ/A2MでHSスピードクラス、または、UHSスピードクラスが必要な方は、[こちら]((https://www.renesas.com/jp/ja/support/contact.html)よりお問合せください。  
+GR-PEACH、GR-LYCHEEは SPIバスを使ってSDカードにアクセスします。  
+接続については``SdUsbConnectクラス``を参照ください。  
+
+
+## DRP (RZ/A2Mのみ)
+DRP(Dynamically Reconfigurable Processor)はソフトウェアの柔軟さとハードウェアの高速性を兼ね備えたプログラマブルハードウェアです。処理を定義するファームウェアの書き換えが瞬間に行えます。  
+詳しくは ``drp-for-mbed/TARGET_RZ_A2XX/r_drp/doc`` を参照ください。  

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/TARGET_RZ_A1XX/dma_if.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,412 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.h
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver interface headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_IF_H
+#define DMA_IF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_errno.h"
+#include "r_typedefs.h"
+#include "ioif_aio.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/*************************************************************************
+ User Includes
+*************************************************************************/
+
+/*************************************************************************
+ Defines
+*************************************************************************/
+
+/* for searching free channel */
+#define DMA_ALLOC_CH  (-1)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* Number od DMA channel */
+typedef enum
+{
+    DMA_CH_0 = 0,
+    DMA_CH_1 = 1,
+    DMA_CH_2 = 2,
+    DMA_CH_3 = 3,
+    DMA_CH_4 = 4,
+    DMA_CH_5 = 5,
+    DMA_CH_6 = 6,
+    DMA_CH_7 = 7,
+    DMA_CH_8 = 8,
+    DMA_CH_9 = 9,
+    DMA_CH_10 = 10,
+    DMA_CH_11 = 11,
+    DMA_CH_12 = 12,
+    DMA_CH_13 = 13,
+    DMA_CH_14 = 14,
+    DMA_CH_15 = 15,
+    DMA_CH_NUM = 16  /* Number of DMA channel */
+} dma_ch_num_t;
+
+/* Unit Size of DMA transfer */
+typedef enum
+{
+    DMA_UNIT_MIN =(-1),
+    DMA_UNIT_1 = 0,   /* Unit Size of DMA transfer = 1byte */
+    DMA_UNIT_2 = 1,   /* Unit Size of DMA transfer = 2byte */
+    DMA_UNIT_4 = 2,   /* Unit Size of DMA transfer = 4byte */
+    DMA_UNIT_8 = 3,   /* Unit Size of DMA transfer = 8byte */
+    DMA_UNIT_16 = 4,  /* Unit Size of DMA transfer = 16byte */
+    DMA_UNIT_32 = 5,  /* Unit Size of DMA transfer = 32byte */
+    DMA_UNIT_64 = 6,  /* Unit Size of DMA transfer = 64byte */
+    DMA_UNIT_128 = 7, /* Unit Size of DMA transfer = 128byte */
+    DMA_UNIT_MAX = 8
+} dma_unit_size_t;
+
+/* DMA transfer resource */
+typedef enum
+{
+    DMA_RS_OSTIM0     = 0x023,   /* OS Timer ch0 */
+    DMA_RS_OSTIM1     = 0x027,   /* OS Timer ch1 */
+    DMA_RS_TGI0A      = 0x043,   /* Multi Function Timer Pulse Unit2 ch0 */
+    DMA_RS_TGI1A      = 0x047,   /* Multi Function Timer Pulse Unit2 ch1  */
+    DMA_RS_TGI2A      = 0x04B,   /* Multi Function Timer Pulse Unit2 ch2  */
+    DMA_RS_TGI3A      = 0x04F,   /* Multi Function Timer Pulse Unit2 ch3  */
+    DMA_RS_TGI4A      = 0x053,   /* Multi Function Timer Pulse Unit2 ch4  */
+    DMA_RS_TXI0       = 0x061,   /* FIFO Serial Communication Interface ch0 (TX) */
+    DMA_RS_RXI0       = 0x062,   /* FIFO Serial Communication Interface ch0 (RX) */
+    DMA_RS_TXI1       = 0x065,   /* FIFO Serial Communication Interface ch1 (TX) */
+    DMA_RS_RXI1       = 0x066,   /* FIFO Serial Communication Interface ch1 (RX) */
+    DMA_RS_TXI2       = 0x069,   /* FIFO Serial Communication Interface ch2 (TX) */
+    DMA_RS_RXI2       = 0x06A,   /* FIFO Serial Communication Interface ch2 (RX) */
+    DMA_RS_TXI3       = 0x06D,   /* FIFO Serial Communication Interface ch3 (TX) */
+    DMA_RS_RXI3       = 0x06E,   /* FIFO Serial Communication Interface ch3 (RX) */
+    DMA_RS_TXI4       = 0x071,   /* FIFO Serial Communication Interface ch4 (TX) */
+    DMA_RS_RXI4       = 0x072,   /* FIFO Serial Communication Interface ch4 (RX) */
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_TXI5       = 0x075,   /* FIFO Serial Communication Interface ch5 (TX) */
+    DMA_RS_RXI5       = 0x076,   /* FIFO Serial Communication Interface ch5 (RX) */
+    DMA_RS_TXI6       = 0x079,   /* FIFO Serial Communication Interface ch6 (TX) */
+    DMA_RS_RXI6       = 0x07A,   /* FIFO Serial Communication Interface ch6 (RX) */
+    DMA_RS_TXI7       = 0x07D,   /* FIFO Serial Communication Interface ch7 (TX) */
+    DMA_RS_RXI7       = 0x07E,   /* FIFO Serial Communication Interface ch7 (RX) */
+#endif /* mbed */
+    DMA_RS_USB0_DMA0  = 0x083,   /* USB Module0 ch0 */
+    DMA_RS_USB0_DMA1  = 0x087,   /* USB Module0 ch1 */
+    DMA_RS_USB1_DMA0  = 0x08B,   /* USB Module1 ch0 */
+    DMA_RS_USB1_DMA1  = 0x08F,   /* USB Module1 ch1 */
+    DMA_RS_ADEND      = 0x093,   /* A/D Converter */
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_IEBBTD     = 0x0A3,   /* IEBus Controller (Data interrupt) */
+    DMA_RS_IEBBTV     = 0x0A7,   /* IEBus Controller (Vector interrupt) */
+    DMA_RS_IREADY     = 0x0AB,   /* CD-Rom Decoder */
+    DMA_RS_FLDT       = 0x0B3,   /* NAND Memory Controller (Data) */
+#endif /* mbed */
+    DMA_RS_SDHI_0T    = 0x0C1,   /* SD Host Interface0 (TX) */
+    DMA_RS_SDHI_0R    = 0x0C2,   /* SD Host Interface0 (RX) */
+    DMA_RS_SDHI_1T    = 0x0C5,   /* SD Host Interface1 (RX) */
+    DMA_RS_SDHI_1R    = 0x0C6,   /* SD Host Interface1 (TX) */
+    DMA_RS_MMCT       = 0x0C9,   /* MMC Host Interface (TX) */
+    DMA_RS_MMCR       = 0x0CA,   /* MMC Host Interface (RX) */
+    DMA_RS_SSITXI0    = 0x0E1,   /* SSIF0 (TX) */
+    DMA_RS_SSIRXI0    = 0x0E2,   /* SSIF0 (RX) */
+    DMA_RS_SSITXI1    = 0x0E5,   /* SSIF1 (TX) */
+    DMA_RS_SSIRXI1    = 0x0E6,   /* SSIF1 (RX) */
+    DMA_RS_SSIRTI2    = 0x0EB,   /* SSIF2 (TX) */
+    DMA_RS_SSITXI3    = 0x0ED,   /* SSIF2 (RTX) */
+    DMA_RS_SSIRXI3    = 0x0EE,   /* SSIF3 (TX) */
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_SSIRTI4    = 0x0F3,   /* SSIF4 (RTX) */
+    DMA_RS_SSITXI5    = 0x0F5,   /* SSIF5 (TX) */
+    DMA_RS_SSIRXI5    = 0x0F6,   /* SSIF5 (RX) */
+#endif /* mbed */
+    DMA_RS_SCUTXI0    = 0x101,   /* SCUX (FFD0) */
+    DMA_RS_SCURXI0    = 0x102,   /* SCUX (FFU0) */
+    DMA_RS_SCUTXI1    = 0x105,   /* SCUX (FFD1) */
+    DMA_RS_SCURXI1    = 0x106,   /* SCUX (FFU1) */
+    DMA_RS_SCUTXI2    = 0x109,   /* SCUX (FFD2) */
+    DMA_RS_SCURXI2    = 0x10A,   /* SCUX (FFU2) */
+    DMA_RS_SCUTXI3    = 0x10D,   /* SCUX (FFD3) */
+    DMA_RS_SCURXI3    = 0x10E,   /* SCUX (FFU3) */
+    DMA_RS_SPTI0      = 0x121,   /* SPI0 (TX) */
+    DMA_RS_SPRI0      = 0x122,   /* SPI0 (RX) */
+    DMA_RS_SPTI1      = 0x125,   /* SPI1 (TX) */
+    DMA_RS_SPRI1      = 0x126,   /* SPI1 (RX) */
+    DMA_RS_SPTI2      = 0x129,   /* SPI2 (TX) */
+    DMA_RS_SPRI2      = 0x12A,   /* SPI2 (RX) */
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_SPTI3      = 0x12B,   /* SPI3 (TX) */
+    DMA_RS_SPRI3      = 0x12E,   /* SPI3 (RX) */
+    DMA_RS_SPTI4      = 0x131,   /* SPI4 (TX) */
+    DMA_RS_SPRI4      = 0x132,   /* SPI4 (RX) */
+#endif /* mbed */
+    DMA_RS_SPDIFTXI   = 0x141,   /* SPDIF (TX) */
+    DMA_RS_SPDIFRXI   = 0x142,   /* SPDIF (RX) */
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_CMI1       = 0x147,   /* Motor Control PWM Timer ch1 */
+    DMA_RS_CMI2       = 0x14B,   /* Motor Control PWM Timer ch2 */
+    DMA_RS_MLBCI      = 0x14F,   /* Media Local Bus */
+    DMA_RS_SGDEI0     = 0x153,   /* Sound Generator0 */
+    DMA_RS_SGDEI1     = 0x157,   /* Sound Generator1 */
+    DMA_RS_SGDEI2     = 0x15B,   /* Sound Generator2 */
+    DMA_RS_SGDEI3     = 0x15F,   /* Sound Generator3 */
+#endif /* mbed */
+    DMA_RS_SCITXI0    = 0x169,   /* Serial Communication Interface ch0 (TX) */
+    DMA_RS_SCIRXI0    = 0x16A,   /* Serial Communication Interface ch0 (RX) */
+    DMA_RS_SCITXI1    = 0x16D,   /* Serial Communication Interface ch1 (TX) */
+    DMA_RS_SCIRXI1    = 0x16E,   /* Serial Communication Interface ch1 (RX) */
+    DMA_RS_TI0        = 0x181,   /* IIC ch0 (TX) */
+    DMA_RS_RI0        = 0x182,   /* IIC ch0 (RX) */
+    DMA_RS_TI1        = 0x185,   /* IIC ch1 (TX) */
+    DMA_RS_RI1        = 0x186,   /* IIC ch1 (RX) */
+    DMA_RS_TI2        = 0x189,   /* IIC ch2 (TX) */
+    DMA_RS_RI2        = 0x18A,   /* IIC ch2 (RX) */
+    DMA_RS_TI3        = 0x18D,   /* IIC ch3 (TX) */
+    DMA_RS_RI3        = 0x18E,   /* IIC ch3 (RX) */
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_LIN0_INT_T = 0x1A1,   /* LIN0 (TX) */
+    DMA_RS_LIN0_INT_R = 0x1A2,   /* LIN0 (RX) */
+    DMA_RS_LIN1_INT_T = 0x1A5,   /* LIN1 (TX) */
+    DMA_RS_LIN1_INT_R = 0x1A6,   /* LIN1 (RX) */
+    DMA_RS_IFEI0      = 0x1B1,   /* Pixel Format Converter ch0 (TX) */
+    DMA_RS_OFFI0      = 0x1B2,   /* Pixel Format Converter ch0 (TX) */
+    DMA_RS_IFEI1      = 0x1B5,   /* Pixel Format Converter ch1 (RX) */
+    DMA_RS_OFFI1      = 0x1B6    /* Pixel Format Converter ch1 (TX) */
+#endif /* mbed */
+} dma_res_select_t;
+
+/* DMA transfer direction */
+typedef enum
+{
+    DMA_REQ_MIN =(-1),
+    DMA_REQ_SRC = 0, /* Read DMA */
+    DMA_REQ_DES = 1, /* Write DMA */
+    DMA_REQ_MAX = 2
+} dma_req_dir_t;
+
+/* Address count direction */
+typedef enum
+{
+    DMA_ADDR_MIN = (-1),
+    DMA_ADDR_INCREMENT = 0, /* Address Count Increment */
+    DMA_ADDR_FIX = 1,       /* Address Count Fix */
+    DMA_ADDR_MAX = 2
+} dma_addr_cnt_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Init Parameter */
+typedef struct
+{
+    bool_t   channel[DMA_CH_NUM]; /* Set enable channel */
+    AIOCB    *p_aio;              /* set callback function (DMA error interrupt) */
+}dma_drv_init_t;
+
+/* DMA Setup Parameter */
+typedef struct
+{
+    dma_res_select_t   resource;     /* DMA Transfer Resource */
+    dma_req_dir_t      direction;    /* DMA Transfer Direction */
+    dma_unit_size_t    dst_width;    /* DMA Transfer Unit Size (Destination) */
+    dma_unit_size_t    src_width;    /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     dst_cnt;      /* DMA Address Count (Destination) */
+    dma_addr_cnt_t     src_cnt;      /* DMA Address Count (Source) */
+    AIOCB              *p_aio;       /* set callback function (DMA end interrupt) */
+#if(1) /* mbed */
+    uint8_t            int_level;
+#endif
+} dma_ch_setup_t;
+
+/* DMA Transfer Paramter */
+typedef struct
+{
+    void       *src_addr;    /* Sorce Address */
+    void       *dst_addr;    /* Destination Address */
+    uint32_t   count;        /* DMA Transfer Size */
+} dma_trans_data_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+/***********************************************************************************
+* ingroup API
+* This function initializes the driver and must be called at system start
+* up, prior to any required DMA functionality being available. This function
+* also sets the enable or disable for each DMA channel and DMA error call back
+* function.
+*
+* param [in] p_dma_init_param - parameter of ch enable and DMA error callback function.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully initialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function shutdown the driver, making DMA functionality is no longer available.
+* It can be carried out only in calse of all channel free.
+*
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully uninitialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_UnInit(int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function allocates a DMA channel.
+* When channel is (-1), it looking for a free channel
+* When set channel to DMA channel number, a set channel is allocated
+*
+* param [in] channel     - allocate channel. (when channel is (-1), it looking for a
+*                           free channel.)
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval channel number - successfully allocated.
+* retval -1             - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function close a DMA channel.
+*
+* param [in] channel     - close channel.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully allocate.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Free(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer parameter.
+* before calling R_DMA_Start(), please carry out this function.
+*
+* param [in] channel     - set up channel.
+* param [in] p_ch_setup  - DMA transfer parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully setup.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer address and start DMA.
+*
+* param [in] channel     - DMA start channel.
+* param [in] p_ch_setup  - DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a continous DMA transfer address and start continuous DMA.
+*
+* param [in] channel     - continuous DMA start channel.
+* param [in] p_ch_setup  - continuous DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully continuous DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                            int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function cancel DMA transfer.
+* Continous DMA also stops at the same time.
+* Please call this function during DMA transfer.
+*
+* param [in] channel     - chancel DMA start channel.
+* param [out] p_remain   - remain sizei of DMA transfer.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully cancel.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno);
+
+
+/***********************************************************************************
+* ingroup API
+* This function get DMA driver version.
+*
+* param none
+*
+* retval driver version
+***********************************************************************************/
+
+extern uint16_t R_DMA_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* DMA_IF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/TARGET_RZ_A1XX/scux_if.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,503 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux_if.h
+* $Rev: $
+* $Date::                           $
+* @brief         SCUX Driver IOIF API header
+******************************************************************************/
+
+#ifndef SCUX_IF_H
+#define SCUX_IF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_errno.h"
+#include "r_typedefs.h"
+#if(1) /* mbed */
+#include "ioif_aio.h"
+#include "misratypes.h"
+#include "R_BSP_mbed_fns.h"
+#include "R_BSP_ScuxDef.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* Number of SCUX channel */
+typedef enum
+{
+    SCUX_CH_0 = 0,
+    SCUX_CH_1 = 1,
+    SCUX_CH_2 = 2,
+    SCUX_CH_3 = 3,
+    SCUX_CH_NUM = 4  /* Number of SCUX channel */
+} scux_ch_num_t;
+#endif /* end mbed */
+
+/* SCUX route setting */
+typedef enum
+{
+#if defined(TARGET_RZA1H) /* mbed */
+    /* mem to mem */
+    SCUX_ROUTE_SRC_MEM_MIN = 0x1000,
+    SCUX_ROUTE_SRC0_MEM    = 0x1001,
+    SCUX_ROUTE_SRC1_MEM    = 0x1002,
+    SCUX_ROUTE_SRC2_MEM    = 0x1003,
+    SCUX_ROUTE_SRC3_MEM    = 0x1004,
+    SCUX_ROUTE_SRC_MEM_MAX = 0x1005,
+    /* mem to SSIF */
+    SCUX_ROUTE_SRC_SSIF_MIN = 0x2000,
+    SCUX_ROUTE_SRC0_SSIF0   = 0x2001,
+    SCUX_ROUTE_SRC0_SSIF012 = 0x2002,
+    SCUX_ROUTE_SRC0_SSIF3   = 0x2003,
+    SCUX_ROUTE_SRC0_SSIF345 = 0x2004,
+    SCUX_ROUTE_SRC1_SSIF0   = 0x2005,
+    SCUX_ROUTE_SRC1_SSIF012 = 0x2006,
+    SCUX_ROUTE_SRC1_SSIF3   = 0x2007,
+    SCUX_ROUTE_SRC1_SSIF345 = 0x2008,    
+    SCUX_ROUTE_SRC2_SSIF1   = 0x2009,
+    SCUX_ROUTE_SRC2_SSIF4   = 0x200A,
+    SCUX_ROUTE_SRC3_SSIF2   = 0x200B,
+    SCUX_ROUTE_SRC3_SSIF5   = 0x200C,
+    SCUX_ROUTE_SRC_SSIF_MAX = 0x200D,
+    /* mem to NIX to SSIF */
+    SCUX_ROUTE_SRC_MIX_SSIF_MIN  = 0x3000,
+    SCUX_ROUTE_SRC0_MIX_SSIF0   = 0x3001,
+    SCUX_ROUTE_SRC0_MIX_SSIF012 = 0x3002,
+    SCUX_ROUTE_SRC0_MIX_SSIF3   = 0x3003,
+    SCUX_ROUTE_SRC0_MIX_SSIF345 = 0x3004,
+    SCUX_ROUTE_SRC1_MIX_SSIF0   = 0x3005,
+    SCUX_ROUTE_SRC1_MIX_SSIF012 = 0x3006,
+    SCUX_ROUTE_SRC1_MIX_SSIF3   = 0x3007,
+    SCUX_ROUTE_SRC1_MIX_SSIF345 = 0x3008,   
+    SCUX_ROUTE_SRC2_MIX_SSIF0   = 0x3009,
+    SCUX_ROUTE_SRC2_MIX_SSIF012 = 0x300A,
+    SCUX_ROUTE_SRC2_MIX_SSIF3   = 0x300B,
+    SCUX_ROUTE_SRC2_MIX_SSIF345 = 0x300C,
+    SCUX_ROUTE_SRC3_MIX_SSIF0   = 0x300D,
+    SCUX_ROUTE_SRC3_MIX_SSIF012 = 0x300E,
+    SCUX_ROUTE_SRC3_MIX_SSIF3   = 0x300F,
+    SCUX_ROUTE_SRC3_MIX_SSIF345 = 0x3010,   
+    SCUX_ROUTE_SRC_MIX_SSIF_MAX = 0x3011
+#else
+    /* mem to mem */
+    SCUX_ROUTE_SRC_MEM_MIN = 0x1000,
+    SCUX_ROUTE_SRC0_MEM    = 0x1001,
+    SCUX_ROUTE_SRC1_MEM    = 0x1002,
+    SCUX_ROUTE_SRC2_MEM    = 0x1003,
+    SCUX_ROUTE_SRC3_MEM    = 0x1004,
+    SCUX_ROUTE_SRC_MEM_MAX = 0x1005,
+    /* mem to SSIF */
+    SCUX_ROUTE_SRC_SSIF_MIN = 0x2000,
+    SCUX_ROUTE_SRC0_SSIF0   = 0x2001,
+    SCUX_ROUTE_SRC0_SSIF012 = 0x2002,
+    SCUX_ROUTE_SRC0_SSIF3   = 0x2003,
+    SCUX_ROUTE_SRC1_SSIF0   = 0x2004,
+    SCUX_ROUTE_SRC1_SSIF012 = 0x2005,
+    SCUX_ROUTE_SRC1_SSIF3   = 0x2006,
+    SCUX_ROUTE_SRC2_SSIF1   = 0x2007,
+    SCUX_ROUTE_SRC3_SSIF2   = 0x2008,
+    SCUX_ROUTE_SRC_SSIF_MAX = 0x2009,
+    /* mem to MIX to SSIF */
+    SCUX_ROUTE_SRC_MIX_SSIF_MIN  = 0x3000,
+    SCUX_ROUTE_SRC0_MIX_SSIF0   = 0x3001,
+    SCUX_ROUTE_SRC0_MIX_SSIF012 = 0x3002,
+    SCUX_ROUTE_SRC0_MIX_SSIF3   = 0x3003,
+    SCUX_ROUTE_SRC1_MIX_SSIF0   = 0x3004,
+    SCUX_ROUTE_SRC1_MIX_SSIF012 = 0x3005,
+    SCUX_ROUTE_SRC1_MIX_SSIF3   = 0x3006,
+    SCUX_ROUTE_SRC2_MIX_SSIF0   = 0x3007,
+    SCUX_ROUTE_SRC2_MIX_SSIF012 = 0x3008,
+    SCUX_ROUTE_SRC2_MIX_SSIF3   = 0x3009,
+    SCUX_ROUTE_SRC3_MIX_SSIF0   = 0x300A,
+    SCUX_ROUTE_SRC3_MIX_SSIF012 = 0x300B,
+    SCUX_ROUTE_SRC3_MIX_SSIF3   = 0x300C,
+    SCUX_ROUTE_SRC_MIX_SSIF_MAX = 0x300D
+#endif /* mbed */
+} scux_route_t;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* used audio channel number setting */
+typedef enum
+{
+    SCUX_USE_CH_1 = 1,   /* used audio channel number is 1 */
+    SCUX_USE_CH_2 = 2,   /* used audio channel number is 2 */
+    SCUX_USE_CH_4 = 4,   /* used audio channel number is 4 */
+    SCUX_USE_CH_6 = 6,   /* used audio channel number is 6 */
+    SCUX_USE_CH_8 = 8    /* used audio channel number is 8 */
+} scux_use_channel_t;
+#endif /* end mbed */
+
+/* select audio channel number setting */
+typedef enum
+{
+    SCUX_AUDIO_CH_MIN = -1,
+    SCUX_AUDIO_CH_0 = 0,   /* select audio channel number is 0 */
+    SCUX_AUDIO_CH_1 = 1,   /* select audio channel number is 1 */
+    SCUX_AUDIO_CH_2 = 2,   /* select audio channel number is 2 */
+    SCUX_AUDIO_CH_3 = 3,   /* select audio channel number is 3 */
+    SCUX_AUDIO_CH_4 = 4,   /* select audio channel number is 4 */
+    SCUX_AUDIO_CH_5 = 5,   /* select audio channel number is 5 */
+    SCUX_AUDIO_CH_6 = 6,   /* select audio channel number is 6 */
+    SCUX_AUDIO_CH_7 = 7,   /* select audio channel number is 7 */
+    SCUX_AUDIO_CH_MAX = 8
+} scux_audio_channel_t;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* SCUX data word length */
+typedef enum
+{
+    SCUX_DATA_LEN_MIN      =(-1),
+    SCUX_DATA_LEN_24       = 0,   /* data word length is 24bit */
+    SCUX_DATA_LEN_16       = 1,   /* data word length is 16bit */
+    SCUX_DATA_LEN_16_TO_24 = 2,   /* data word length is 24bit */
+    SCUX_DATA_LEN_MAX      = 3
+} scux_data_word_len_t;
+#endif /* end mbed */
+
+/* SSIF PIN mode setting */
+typedef enum
+{
+    SCUX_PIN_MODE_MIN          =(-1),
+    SCUX_PIN_MODE_INDEPEND     = 0,   /* PIN mode is independent */
+    SCUX_PIN_MODE_SLAVE_SLAVE  = 1,   /* PIN mode is slave-slave */
+    SCUX_PIN_MODE_MASTER_SLAVE = 2,   /* PIN mode is master-slave */
+    SCUX_PIN_MODE_MAX = 3
+} scux_pin_mode_t;
+
+/* SCUX sampling rate */
+typedef enum
+{
+    SCUX_SYNC_RATE_8      = 8000,    /* 8KHz */
+    SCUX_SYNC_RATE_11_025 = 11025,   /* 11.025KHz */
+    SCUX_SYNC_RATE_12     = 12000,   /* 12KHz */
+    SCUX_SYNC_RATE_16     = 16000,   /* 16KHz */
+    SCUX_SYNC_RATE_22_05  = 22050,   /* 22.05KHz */
+    SCUX_SYNC_RATE_24     = 24000,   /* 24KHz */
+    SCUX_SYNC_RATE_32     = 32000,   /* 32KHz */
+    SCUX_SYNC_RATE_44_1   = 44100,   /* 44.1KHz */
+    SCUX_SYNC_RATE_48     = 48000,   /* 48KHz */
+    SCUX_SYNC_RATE_64     = 64000,   /* 64KHz */
+    SCUX_SYNC_RATE_88_2   = 88200,   /* 88.2KHz */
+    SCUX_SYNC_RATE_96     = 96000    /* 96KHz */
+} scux_src_sync_rate_t;
+
+/* SCUX clock source setting */
+typedef enum
+{
+    SCUX_CLK_MIN  =(-1),
+    SCUX_CLK_AUDIO_CLK  = 0,   /* clock source is AUDIO_CLK */
+    SCUX_CLK_AUDIO_X1   = 1,   /* clock source is AUDIO_X1 */
+    SCUX_CLK_MLB_CLK    = 2,   /* clock source is MLB_CLK */
+    SCUX_CLK_USB_X1     = 3,   /* clock source is USB_X1 */
+    SCUX_CLK_CLKP1_2    = 4,   /* clock source is surrounding clock */
+    SCUX_CLK_MTU_TIOC3A = 5,   /* clock source is TIOC3A */
+    SCUX_CLK_MTU_TIOC4A = 6,   /* clock source is TIOC4A */
+    SCUX_CLK_SSIF0_WS   = 8,   /* clock source is SSIF0 WS */
+    SCUX_CLK_SSIF1_WS   = 9,   /* clock source is SSIF1 WS */
+    SCUX_CLK_SSIF2_WS   = 10,   /* clock source is SSIF2 WS */
+    SCUX_CLK_SSIF3_WS   = 11,  /* clock source is SSIF3 WS */
+#if defined(TARGET_RZA1H) /* mbed */
+    SCUX_CLK_SSIF4_WS   = 12,  /* clock source is SSIF4 WS */
+    SCUX_CLK_SSIF5_WS   = 13,  /* clock source is SSIF5 WS */
+#endif /* mbed */
+    SCUX_CLK_MAX
+} scux_src_clk_source_t;
+
+/* SCUX delay mode setting */
+typedef enum
+{
+    SCUX_DELAY_MIN         =(-1),
+    SCUX_DELAY_NORMAL      = 0,    /* Delay mode is normal */
+    SCUX_DELAY_LOW_DELAY1  = 1,    /* Delay mode is Low Delay1 */
+    SCUX_DELAY_LOW_DELAY2  = 2,    /* Delay mode is Low Delay2 */
+    SCUX_DELAY_MAX         = 3
+} scux_src_delay_mode_t;
+
+/* DVU ramp time setting */
+typedef enum
+{
+    SCUX_DVU_TIME_MIN  =(-1),
+    SCUX_DVU_TIME_128DB_1STEP      = 0,   /* volume change 128DB among 1 step */
+    SCUX_DVU_TIME_64DB_1STEP       = 1,   /* volume change 64DB among 1 step */
+    SCUX_DVU_TIME_32DB_1STEP       = 2,   /* volume change 32DB among 1 step */
+    SCUX_DVU_TIME_16DB_1STEP       = 3,   /* volume change 16DB among 1 step */
+    SCUX_DVU_TIME_8DB_1STEP        = 4,   /* volume change 8DB among 1 step */
+    SCUX_DVU_TIME_4DB_1STEP        = 5,   /* volume change 4DB among 1 step */
+    SCUX_DVU_TIME_2DB_1STEP        = 6,   /* volume change 2DB among 1 step */
+    SCUX_DVU_TIME_1DB_1STEP        = 7,   /* volume change 1DB among 1 step */
+    SCUX_DVU_TIME_0_5DB_1STEP      = 8,   /* volume change 0.5DB among 1 step */
+    SCUX_DVU_TIME_0_25DB_1STEP     = 9,   /* volume change 0.25DB among 1 step */
+    SCUX_DVU_TIME_0_125DB_1STEP    = 10,  /* volume change 0.125DB among 1 step */
+    SCUX_DVU_TIME_0_125DB_2STEP    = 11,  /* volume change 0.125DB among 2 step */
+    SCUX_DVU_TIME_0_125DB_4STEP    = 12,  /* volume change 0.125DB among 4 step */
+    SCUX_DVU_TIME_0_125DB_8STEP    = 13,  /* volume change 0.125DB among 8 step */
+    SCUX_DVU_TIME_0_125DB_16STEP   = 14,  /* volume change 0.125DB among 16 step */
+    SCUX_DVU_TIME_0_125DB_32STEP   = 15,  /* volume change 0.125DB among 32 step */
+    SCUX_DVU_TIME_0_125DB_64STEP   = 16,  /* volume change 0.125DB among 64 step */
+    SCUX_DVU_TIME_0_125DB_128STEP  = 17,  /* volume change 0.125DB among 128 step */
+    SCUX_DVU_TIME_0_125DB_256STEP  = 18,  /* volume change 0.125DB among 256 step */
+    SCUX_DVU_TIME_0_125DB_512STEP  = 19,  /* volume change 0.125DB among 512 step */
+    SCUX_DVU_TIME_0_125DB_1024STEP = 20,  /* volume change 0.125DB among 1024 step */
+    SCUX_DVU_TIME_0_125DB_2048STEP = 21,  /* volume change 0.125DB among 2048 step */
+    SCUX_DVU_TIME_0_125DB_4096STEP = 22,  /* volume change 0.125DB among 4096 step */
+    SCUX_DVU_TIME_0_125DB_8192STEP = 23,  /* volume change 0.125DB among 8192 step */
+    SCUX_DVU_TIME_MAX              = 24
+} scux_dvu_ramp_time_t;
+
+/* MIX ramp time setting */
+typedef enum
+{
+    SCUX_MIX_TIME_MIN            =(-1),
+    SCUX_MIX_TIME_128DB_1STEP    = 0,    /* volume change 128DB among 1 step */
+    SCUX_MIX_TIME_64DB_1STEP     = 1,    /* volume change 64DB among 1 step */
+    SCUX_MIX_TIME_32DB_1STEP     = 2,    /* volume change 32DB among 1 step */
+    SCUX_MIX_TIME_16DB_1STEP     = 3,    /* volume change 16DB among 1 step */
+    SCUX_MIX_TIME_8DB_1STEP      = 4,    /* volume change 8DB among 1 step */
+    SCUX_MIX_TIME_4DB_1STEP      = 5,    /* volume change 4DB among 1 step */
+    SCUX_MIX_TIME_2DB_1STEP      = 6,    /* volume change 2DB among 1 step */
+    SCUX_MIX_TIME_1DB_1STEP      = 7,    /* volume change 1DB among 1 step */
+    SCUX_MIX_TIME_0_5DB_1STEP    = 8,    /* volume change 0.5DB among 1 step */
+    SCUX_MIX_TIME_0_25DB_1STEP   = 9,    /* volume change 0.25DB among 1 step */
+    SCUX_MIX_TIME_0_125DB_1STEP  = 10,   /* volume change 0.125DB among 1 step */
+    SCUX_MIX_TIME_MAX            = 11
+} scux_mix_ramp_time_t;
+
+/* SSIF channels */
+typedef enum
+{
+    SCUX_SSIF_CH_0    = 0,    /* volume change 128DB among 1 step */
+    SCUX_SSIF_CH_1    = 1,    /* volume change 64DB among 1 step */
+    SCUX_SSIF_CH_2    = 2,    /* volume change 32DB among 1 step */
+    SCUX_SSIF_CH_3    = 3,    /* volume change 16DB among 1 step */
+#if defined(TARGET_RZA1H) /* mbed */
+    SCUX_SSIF_CH_4    = 4,    /* volume change 8DB among 1 step */
+    SCUX_SSIF_CH_5    = 5,    /* volume change 4DB among 1 step */
+#endif /* mbed */
+    SCUX_SSIF_CH_NUM
+} scux_ssif_ch_num_t;
+
+/* SSIF channels */
+typedef enum
+{
+    SCUX_SSIF_SYSTEM_LEN_MIN   = 0,
+    SCUX_SSIF_SYSTEM_LEN_16    = 1,    /* SSIF system word length is 16bit */
+    SCUX_SSIF_SYSTEM_LEN_24    = 2,    /* SSIF system word length is 24bit */
+    SCUX_SSIF_SYSTEM_LEN_32    = 3,    /* SSIF system word length is 32bit */
+    SCUX_SSIF_SYSTEM_LEN_48    = 4,    /* SSIF system word length is 48bit */
+    SCUX_SSIF_SYSTEM_LEN_64    = 5,    /* SSIF system word length is 64bit */
+    SCUX_SSIF_SYSTEM_LEN_128   = 6,    /* SSIF system word length is 128bit */
+    SCUX_SSIF_SYSTEM_LEN_256   = 7,    /* SSIF system word length is 256bit */
+    SCUX_SSIF_SYSTEM_LEN_MAX   = 8
+} scux_ssif_system_len_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* SCUX IOCTL function code */
+#define SCUX_IOCTL_MIN                 (-1)
+#define SCUX_IOCTL_SET_START           0   /* start transfer */
+#define SCUX_IOCTL_SET_FLUSH_STOP      1   /* set flush stop function */
+#define SCUX_IOCTL_SET_CLEAR_STOP      2   /* set clear stop function */
+#define SCUX_IOCTL_SET_ROUTE           3   /* set route parameter */
+#define SCUX_IOCTL_SET_PIN_CLK         4   /* set pin clock parameter */
+#define SCUX_IOCTL_SET_PIN_MODE        5   /* set pin mode parameter */
+#define SCUX_IOCTL_SET_SRC_CFG         6   /* set SRC parameter */
+#define SCUX_IOCTL_SET_DVU_CFG         7   /* set DVU parameter */
+#define SCUX_IOCTL_SET_DVU_DIGI_VOL    8   /* set dgital volume parameter */
+#define SCUX_IOCTL_SET_DVU_RAMP_VOL    9   /* set ramp volume parameter */
+#define SCUX_IOCTL_SET_ZEROCROSS_MUTE  10  /* set zerocross mute paramter */
+#define SCUX_IOCTL_SET_STOP_MUTE       11  /* set mute stop */
+#define SCUX_IOCTL_SET_MIX_CFG         12  /* set MIX parameter */
+#define SCUX_IOCTL_SET_MIX_VOL         13  /* set MIX volume parameter */
+#define SCUX_IOCTL_SET_SSIF_CFG        14  /* set SSIF parameter */
+#define SCUX_IOCTL_GET_WRITE_STAT      15  /* get write status */
+#define SCUX_IOCTL_GET_READ_STAT       16  /* get read status */
+#define SCUX_IOCTL_GET_DVU_STAT        17  /* get DVU status */
+#define SCUX_IOCTL_GET_MUTE_STAT       18  /* get MUTE status */
+#define SCUX_IOCTL_GET_MIX_STAT        19  /* get MIX status */
+#define SCUX_IOCTL_MAX                 20
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* SCUX status */
+#define SCUX_STAT_STOP    0  /* request regstration isn't start */
+#define SCUX_STAT_IDLE    1  /* request isn't receied */
+#define SCUX_STAT_TRANS   2  /* under data transfer execution */
+#endif /* end mbed */
+
+/* DVU status */
+#define SCUX_DVU_STAT_MUTE          0  /* DVU volume is mute */
+#define SCUX_DVU_STAT_RAMP_DOWN     1  /* DVU volume is ramp down */
+#define SCUX_DVU_STAT_RAMP_UP       2  /* DVU volume is ramp up */
+#define SCUX_DVU_STAT_RAMP_FIXED    3  /* DVU volume change is stop */
+#define SCUX_DVU_STAT_ORIGINAL_SIZE 4  /* DVU volume is original size */
+
+/* MIX status */
+#define SCUX_MIX_STAT_RAMP_FIXED  0  /* MIX volume change is stop */
+#define SCUX_MIX_STAT_RAMP_DOWN   1  /* MIX volume is ramp down */
+#define SCUX_MIX_STAT_RAMP_UP     2  /* MIX volume is ramp up */
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* SSIF channel synchronous setting */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    scux_pin_mode_t        pin_mode;          /* SSIF sync setting */
+} scux_ssif_pin_mode_t;
+
+/* SSIF AUDIO_CLK source parameters */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    scux_src_clk_source_t  pin_clk;           /* AUDIO_CLK source */
+} scux_ssif_pin_clk_t;
+
+/* SSIF parameters */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    bool_t                 mode_master;       /* master mode / slave mode select */
+    bool_t                 select_audio_clk;  /* AUDIO_X1 / AUDIO_CLK select */
+    scux_ssif_system_len_t system_word;       /* system word length */
+    bool_t                 sck_polarity_rise; /* SCK polarity type select */
+    bool_t                 ws_polarity_high;  /* WS polarity type select */
+    bool_t                 padding_high;      /* padding type select */
+    bool_t                 serial_data_align; /* serial data alingment type select */
+    bool_t                 ws_delay;          /* WS delay type select */
+    bool_t                 use_noise_cancel;  /* noise cancel ON / OFF select */
+    bool_t                 use_tdm;           /* TDM mode ON / OFF select */
+} scux_ssif_cfg_t;
+
+/* MIX parameters */
+typedef struct
+{
+    bool_t               mixmode_ramp;                          /* ramp mode / step mpde select */
+    scux_mix_ramp_time_t up_period;                             /* ramp up period */
+    scux_mix_ramp_time_t down_period;                           /* ramp down period */
+    uint32_t             mix_vol[SCUX_CH_NUM];                  /* MIX volume value */
+    scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
+} scux_mix_cfg_t;
+
+/* zerocross mute parameters */
+typedef struct
+{
+    bool_t               zc_mute_enable[SCUX_AUDIO_CH_MAX];     /* zerocross mute enable setting */
+    void                 (*pcallback[SCUX_AUDIO_CH_MAX])(void); /* callback pointer for zerocross */
+} scux_zc_mute_t;
+
+/* ramp volume parameters */
+typedef struct
+{
+    bool_t               ramp_vol_enable[SCUX_AUDIO_CH_MAX];  /* ramp volume enable setting */
+    scux_dvu_ramp_time_t up_period;                           /* ramp up period */
+    scux_dvu_ramp_time_t down_period;                         /* ramp down period */
+    uint32_t             ramp_vol;                            /* ramp volume value */
+    uint32_t             ramp_wait_time;                      /* wait time for volume change */
+} scux_dvu_ramp_vol_t;
+
+/* digital volume parameters */
+typedef struct
+{
+    bool_t               digi_vol_enable;             /* digital volume enable setting */
+    uint32_t             digi_vol[SCUX_AUDIO_CH_MAX]; /* digital volume value */
+} scux_dvu_digi_vol_t;
+
+/* DVU parameters */
+typedef struct
+{
+    bool_t               dvu_enable;          /* DVU enable setting */
+    scux_dvu_digi_vol_t  dvu_digi_vol;        /* digital volume setting */
+    scux_dvu_ramp_vol_t  dvu_ramp_vol;        /* ramp volume setting */
+    scux_zc_mute_t       dvu_zc_mute;         /* zerocross mute setting */
+} scux_dvu_cfg_t;
+
+/* SRC parameters */
+typedef struct
+{
+    bool_t                src_enable;          /* SRC enable setting */
+    scux_use_channel_t    use_ch;              /* used data channel setting */
+    scux_data_word_len_t  word_len;            /* used word length setting */
+    bool_t                mode_sync;           /* sync mode/async mode select */
+    scux_src_sync_rate_t  input_rate_sync;     /* input rate on sync mode */
+    scux_src_clk_source_t input_clk_async;      /* input clock source on async mode */
+    uint32_t              input_div_async;     /* input divide rate on async mode */
+    scux_src_sync_rate_t  output_rate_sync;    /* output rate on sync mode */
+    scux_src_clk_source_t output_clk_async;    /* output clock source on async mode */
+    uint32_t              output_div_async;    /* output divide rate on async mode */
+    uint32_t              input_ws;            /* input WS frequency */
+    uint32_t              output_ws;           /* output WS frequency */
+    uint32_t              freq_tioc3a;         /* frequency of TIOC3A */
+    uint32_t              freq_tioc4a;         /* frequency of TIOC4A */
+    scux_src_delay_mode_t delay_mode;          /* delay mode setting */
+    uint32_t              wait_sample;         /* wait time setting */
+    uint8_t               min_rate_percentage; /* minimum rate setting */
+    scux_audio_channel_t  select_in_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
+} scux_src_cfg_t;
+
+/* SCUX setup parameter */
+typedef struct
+{
+    bool_t           enabled;               /* channel used flag */
+    uint8_t          int_level;             /* interrupt priority */
+    scux_route_t     route;                 /* reoute setting */
+    scux_src_cfg_t   src_cfg;               /* SRC parameters */
+} scux_channel_cfg_t;
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#if(1) /* mbed */
+RBSP_MBED_FNS* R_SCUX_MakeCbTbl_mbed(void);
+#else  /* not mbed */
+IOIF_DRV_API* R_SCUX_MakeCbTbl(void);
+#endif /* end mbed */
+
+extern uint16_t R_SCUX_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SCUX_IF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/TARGET_RZ_A2XX/dma_if.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,406 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.h
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver interface headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_IF_H
+#define DMA_IF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_errno.h"
+#include "r_typedefs.h"
+#include "ioif_aio.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/*************************************************************************
+ User Includes
+*************************************************************************/
+
+/*************************************************************************
+ Defines
+*************************************************************************/
+
+/* for searching free channel */
+#define DMA_ALLOC_CH  (-1)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* Number od DMA channel */
+typedef enum
+{
+    DMA_CH_0 = 0,
+    DMA_CH_1 = 1,
+    DMA_CH_2 = 2,
+    DMA_CH_3 = 3,
+    DMA_CH_4 = 4,
+    DMA_CH_5 = 5,
+    DMA_CH_6 = 6,
+    DMA_CH_7 = 7,
+    DMA_CH_8 = 8,
+    DMA_CH_9 = 9,
+    DMA_CH_10 = 10,
+    DMA_CH_11 = 11,
+    DMA_CH_12 = 12,
+    DMA_CH_13 = 13,
+    DMA_CH_14 = 14,
+    DMA_CH_15 = 15,
+    DMA_CH_NUM = 16  /* Number of DMA channel */
+} dma_ch_num_t;
+
+/* Unit Size of DMA transfer */
+typedef enum
+{
+    DMA_UNIT_MIN =(-1),
+    DMA_UNIT_1 = 0,   /* Unit Size of DMA transfer = 1byte */
+    DMA_UNIT_2 = 1,   /* Unit Size of DMA transfer = 2byte */
+    DMA_UNIT_4 = 2,   /* Unit Size of DMA transfer = 4byte */
+    DMA_UNIT_8 = 3,   /* Unit Size of DMA transfer = 8byte */
+    DMA_UNIT_16 = 4,  /* Unit Size of DMA transfer = 16byte */
+    DMA_UNIT_32 = 5,  /* Unit Size of DMA transfer = 32byte */
+    DMA_UNIT_64 = 6,  /* Unit Size of DMA transfer = 64byte */
+    DMA_UNIT_128 = 7, /* Unit Size of DMA transfer = 128byte */
+    DMA_UNIT_MAX = 8
+} dma_unit_size_t;
+
+/* DMA transfer resource */
+typedef enum
+{
+#if(1)
+    DMA_RS_OSTIM0     = 0x023,   /* OS Timer ch0 */
+    DMA_RS_OSTIM1     = 0x027,   /* OS Timer ch1 */
+    DMA_RS_OSTIM2     = 0x02B,   /* OS Timer ch2 */
+    DMA_RS_TGI0A      = 0x043,   /* Multi Function Timer Pulse Unit3 ch0 A */
+    DMA_RS_TGI0B      = 0x047,   /* Multi Function Timer Pulse Unit3 ch0 B */
+    DMA_RS_TGI0C      = 0x04B,   /* Multi Function Timer Pulse Unit3 ch0 C */
+    DMA_RS_TGI0D      = 0x04F,   /* Multi Function Timer Pulse Unit3 ch0 D */
+    DMA_RS_TGI1A      = 0x053,   /* Multi Function Timer Pulse Unit3 ch1 A */
+    DMA_RS_TGI1B      = 0x057,   /* Multi Function Timer Pulse Unit3 ch1 B */
+    DMA_RS_TGI2A      = 0x05B,   /* Multi Function Timer Pulse Unit3 ch2 A */
+    DMA_RS_TGI2B      = 0x05F,   /* Multi Function Timer Pulse Unit3 ch2 B */
+    DMA_RS_TGI3A      = 0x063,   /* Multi Function Timer Pulse Unit3 ch3 A */
+    DMA_RS_TGI3B      = 0x067,   /* Multi Function Timer Pulse Unit3 ch3 B */
+    DMA_RS_TGI3C      = 0x06B,   /* Multi Function Timer Pulse Unit3 ch3 C */
+    DMA_RS_TGI3D      = 0x06F,   /* Multi Function Timer Pulse Unit3 ch3 D */
+    DMA_RS_TGI4A      = 0x073,   /* Multi Function Timer Pulse Unit3 ch4 A */
+    DMA_RS_TGI4B      = 0x077,   /* Multi Function Timer Pulse Unit3 ch4 B */
+    DMA_RS_TGI4C      = 0x07B,   /* Multi Function Timer Pulse Unit3 ch4 C */
+    DMA_RS_TGI4D      = 0x07F,   /* Multi Function Timer Pulse Unit3 ch4 D */
+    DMA_RS_TGI4V      = 0x083,   /* Multi Function Timer Pulse Unit3 ch4 V */
+
+
+
+
+    DMA_RS_SSITXI0    = 0x271,   /* SSIF0 (TX) */
+    DMA_RS_SSIRXI0    = 0x272,   /* SSIF0 (RX) */
+    DMA_RS_SSITXI1    = 0x275,   /* SSIF1 (TX) */
+    DMA_RS_SSIRXI1    = 0x276,   /* SSIF1 (RX) */
+    DMA_RS_SSIRTI2    = 0x27B,   /* SSIF2 (TX) */
+    DMA_RS_SSITXI3    = 0x27D,   /* SSIF2 (RTX) */
+    DMA_RS_SSIRXI3    = 0x27E,   /* SSIF3 (TX) */
+
+    DMA_RS_SPDIFRXI   = 0x283,   /* SPDIF (RX) */
+    DMA_RS_SPDIFTXI   = 0x287,   /* SPDIF (TX) */
+
+#else
+    DMA_RS_OSTIM0     = 0x023,   /* OS Timer ch0 */
+    DMA_RS_OSTIM1     = 0x027,   /* OS Timer ch1 */
+    DMA_RS_TGI0A      = 0x043,   /* Multi Function Timer Pulse Unit2 ch0 */
+    DMA_RS_TGI1A      = 0x047,   /* Multi Function Timer Pulse Unit2 ch1  */
+    DMA_RS_TGI2A      = 0x04B,   /* Multi Function Timer Pulse Unit2 ch2  */
+    DMA_RS_TGI3A      = 0x04F,   /* Multi Function Timer Pulse Unit2 ch3  */
+    DMA_RS_TGI4A      = 0x053,   /* Multi Function Timer Pulse Unit2 ch4  */
+    DMA_RS_TXI0       = 0x061,   /* FIFO Serial Communication Interface ch0 (TX) */
+    DMA_RS_RXI0       = 0x062,   /* FIFO Serial Communication Interface ch0 (RX) */
+    DMA_RS_TXI1       = 0x065,   /* FIFO Serial Communication Interface ch1 (TX) */
+    DMA_RS_RXI1       = 0x066,   /* FIFO Serial Communication Interface ch1 (RX) */
+    DMA_RS_TXI2       = 0x069,   /* FIFO Serial Communication Interface ch2 (TX) */
+    DMA_RS_RXI2       = 0x06A,   /* FIFO Serial Communication Interface ch2 (RX) */
+    DMA_RS_TXI3       = 0x06D,   /* FIFO Serial Communication Interface ch3 (TX) */
+    DMA_RS_RXI3       = 0x06E,   /* FIFO Serial Communication Interface ch3 (RX) */
+    DMA_RS_TXI4       = 0x071,   /* FIFO Serial Communication Interface ch4 (TX) */
+    DMA_RS_RXI4       = 0x072,   /* FIFO Serial Communication Interface ch4 (RX) */
+    DMA_RS_USB0_DMA0  = 0x083,   /* USB Module0 ch0 */
+    DMA_RS_USB0_DMA1  = 0x087,   /* USB Module0 ch1 */
+    DMA_RS_USB1_DMA0  = 0x08B,   /* USB Module1 ch0 */
+    DMA_RS_USB1_DMA1  = 0x08F,   /* USB Module1 ch1 */
+    DMA_RS_ADEND      = 0x093,   /* A/D Converter */
+    DMA_RS_SDHI_0T    = 0x0C1,   /* SD Host Interface0 (TX) */
+    DMA_RS_SDHI_0R    = 0x0C2,   /* SD Host Interface0 (RX) */
+    DMA_RS_SDHI_1T    = 0x0C5,   /* SD Host Interface1 (RX) */
+    DMA_RS_SDHI_1R    = 0x0C6,   /* SD Host Interface1 (TX) */
+    DMA_RS_MMCT       = 0x0C9,   /* MMC Host Interface (TX) */
+    DMA_RS_MMCR       = 0x0CA,   /* MMC Host Interface (RX) */
+    DMA_RS_SSITXI0    = 0x0E1,   /* SSIF0 (TX) */
+    DMA_RS_SSIRXI0    = 0x0E2,   /* SSIF0 (RX) */
+    DMA_RS_SSITXI1    = 0x0E5,   /* SSIF1 (TX) */
+    DMA_RS_SSIRXI1    = 0x0E6,   /* SSIF1 (RX) */
+    DMA_RS_SSIRTI2    = 0x0EB,   /* SSIF2 (TX) */
+    DMA_RS_SSITXI3    = 0x0ED,   /* SSIF2 (RTX) */
+    DMA_RS_SSIRXI3    = 0x0EE,   /* SSIF3 (TX) */
+    DMA_RS_SCUTXI0    = 0x101,   /* SCUX (FFD0) */
+    DMA_RS_SCURXI0    = 0x102,   /* SCUX (FFU0) */
+    DMA_RS_SCUTXI1    = 0x105,   /* SCUX (FFD1) */
+    DMA_RS_SCURXI1    = 0x106,   /* SCUX (FFU1) */
+    DMA_RS_SCUTXI2    = 0x109,   /* SCUX (FFD2) */
+    DMA_RS_SCURXI2    = 0x10A,   /* SCUX (FFU2) */
+    DMA_RS_SCUTXI3    = 0x10D,   /* SCUX (FFD3) */
+    DMA_RS_SCURXI3    = 0x10E,   /* SCUX (FFU3) */
+    DMA_RS_SPTI0      = 0x121,   /* SPI0 (TX) */
+    DMA_RS_SPRI0      = 0x122,   /* SPI0 (RX) */
+    DMA_RS_SPTI1      = 0x125,   /* SPI1 (TX) */
+    DMA_RS_SPRI1      = 0x126,   /* SPI1 (RX) */
+    DMA_RS_SPTI2      = 0x129,   /* SPI2 (TX) */
+    DMA_RS_SPRI2      = 0x12A,   /* SPI2 (RX) */
+    DMA_RS_SPDIFTXI   = 0x141,   /* SPDIF (TX) */
+    DMA_RS_SPDIFRXI   = 0x142,   /* SPDIF (RX) */
+    DMA_RS_SCITXI0    = 0x169,   /* Serial Communication Interface ch0 (TX) */
+    DMA_RS_SCIRXI0    = 0x16A,   /* Serial Communication Interface ch0 (RX) */
+    DMA_RS_SCITXI1    = 0x16D,   /* Serial Communication Interface ch1 (TX) */
+    DMA_RS_SCIRXI1    = 0x16E,   /* Serial Communication Interface ch1 (RX) */
+    DMA_RS_TI0        = 0x181,   /* IIC ch0 (TX) */
+    DMA_RS_RI0        = 0x182,   /* IIC ch0 (RX) */
+    DMA_RS_TI1        = 0x185,   /* IIC ch1 (TX) */
+    DMA_RS_RI1        = 0x186,   /* IIC ch1 (RX) */
+    DMA_RS_TI2        = 0x189,   /* IIC ch2 (TX) */
+    DMA_RS_RI2        = 0x18A,   /* IIC ch2 (RX) */
+    DMA_RS_TI3        = 0x18D,   /* IIC ch3 (TX) */
+    DMA_RS_RI3        = 0x18E,   /* IIC ch3 (RX) */
+#endif
+} dma_res_select_t;
+
+/* DMA transfer direction */
+typedef enum
+{
+    DMA_REQ_MIN =(-1),
+    DMA_REQ_SRC = 0, /* Read DMA */
+    DMA_REQ_DES = 1, /* Write DMA */
+    DMA_REQ_MAX = 2
+} dma_req_dir_t;
+
+/* Address count direction */
+typedef enum
+{
+    DMA_ADDR_MIN = (-1),
+    DMA_ADDR_INCREMENT = 0, /* Address Count Increment */
+    DMA_ADDR_FIX = 1,       /* Address Count Fix */
+    DMA_ADDR_MAX = 2
+} dma_addr_cnt_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Init Parameter */
+typedef struct
+{
+    bool_t   channel[DMA_CH_NUM]; /* Set enable channel */
+    AIOCB    *p_aio;              /* set callback function (DMA error interrupt) */
+}dma_drv_init_t;
+
+/* DMA Setup Parameter */
+typedef struct
+{
+    dma_res_select_t   resource;     /* DMA Transfer Resource */
+    dma_req_dir_t      direction;    /* DMA Transfer Direction */
+    dma_unit_size_t    dst_width;    /* DMA Transfer Unit Size (Destination) */
+    dma_unit_size_t    src_width;    /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     dst_cnt;      /* DMA Address Count (Destination) */
+    dma_addr_cnt_t     src_cnt;      /* DMA Address Count (Source) */
+    AIOCB              *p_aio;       /* set callback function (DMA end interrupt) */
+#if(1) /* mbed */
+    uint8_t            int_level;
+#endif
+} dma_ch_setup_t;
+
+/* DMA Transfer Paramter */
+typedef struct
+{
+    void       *src_addr;    /* Sorce Address */
+    void       *dst_addr;    /* Destination Address */
+    uint32_t   count;        /* DMA Transfer Size */
+} dma_trans_data_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+/***********************************************************************************
+* ingroup API
+* This function initializes the driver and must be called at system start
+* up, prior to any required DMA functionality being available. This function
+* also sets the enable or disable for each DMA channel and DMA error call back
+* function.
+*
+* param [in] p_dma_init_param - parameter of ch enable and DMA error callback function.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully initialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function shutdown the driver, making DMA functionality is no longer available.
+* It can be carried out only in calse of all channel free.
+*
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully uninitialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_UnInit(int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function allocates a DMA channel.
+* When channel is (-1), it looking for a free channel
+* When set channel to DMA channel number, a set channel is allocated
+*
+* param [in] channel     - allocate channel. (when channel is (-1), it looking for a
+*                           free channel.)
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval channel number - successfully allocated.
+* retval -1             - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function close a DMA channel.
+*
+* param [in] channel     - close channel.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully allocate.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Free(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer parameter.
+* before calling R_DMA_Start(), please carry out this function.
+*
+* param [in] channel     - set up channel.
+* param [in] p_ch_setup  - DMA transfer parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully setup.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer address and start DMA.
+*
+* param [in] channel     - DMA start channel.
+* param [in] p_ch_setup  - DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a continous DMA transfer address and start continuous DMA.
+*
+* param [in] channel     - continuous DMA start channel.
+* param [in] p_ch_setup  - continuous DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully continuous DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                            int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function cancel DMA transfer.
+* Continous DMA also stops at the same time.
+* Please call this function during DMA transfer.
+*
+* param [in] channel     - chancel DMA start channel.
+* param [out] p_remain   - remain sizei of DMA transfer.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully cancel.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno);
+
+
+/***********************************************************************************
+* ingroup API
+* This function get DMA driver version.
+*
+* param none
+*
+* retval driver version
+***********************************************************************************/
+
+extern uint16_t R_DMA_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* DMA_IF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/TARGET_RZ_A2XX/spdif_if.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,163 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : spdif_if.h
+* $Rev: $
+* $Date::                           $
+* Description  : SPDIF Driver API header
+******************************************************************************/
+
+#ifndef SPDIF_IF_H
+#define SPDIF_IF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+
+#include "r_typedefs.h"
+#include "r_errno.h"
+#if(1) /* mbed */
+#include "misratypes.h"
+#include "aioif.h"
+#include "R_BSP_mbed_fns.h"
+#include "R_BSP_SpdifDef.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if(1) /* mbed */
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+
+extern RBSP_MBED_FNS* R_SPDIF_MakeCbTbl_mbed(void);
+#else  /* not mbed */
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#define SPDIF_NUM_CHANS       (1u)    /**< Number of SPDIF channels */
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+/** CTRL:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SPDIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SPDIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} spdif_chcfg_cks_t; 
+
+/** CTRL:RASS,TASS(Audio bit length) */
+typedef enum
+{
+    SPDIF_CFG_AUDIO_BIT_16 = 0,   /**< Audio bit length 16 */
+    SPDIF_CFG_AUDIO_BIT_20 = 1,   /**< Audio bit length 20 */
+    SPDIF_CFG_AUDIO_BIT_24 = 2    /**< Audio bit length 24 */
+} spdif_chcfg_audio_bit_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+/** This structure contains the configuration settings */
+typedef struct
+{
+    bool_t                          enabled;             /**< The enable flag for the channel       */
+    uint8_t                         int_level;           /**< Interrupt priority for the channel    */
+    spdif_chcfg_cks_t               clk_select;          /**< CTRL-CKS : Audio clock select         */
+    spdif_chcfg_audio_bit_t         audio_bit_tx;        /**< CTRL-TASS : Audio bit length          */
+    spdif_chcfg_audio_bit_t         audio_bit_rx;        /**< CTRL-RASS : Audio bit length          */
+    bool                            tx_u_data_enabled;   /**< CTRL-RASS : Audio bit length          */
+} spdif_channel_cfg_t;
+
+typedef struct
+{
+    uint32_t                        Lch;                 /**< Channel Status bit Lch    */
+    uint32_t                        Rch;                 /**< Channel Status bit Rch    */
+} spdif_channel_status_t;
+
+typedef struct
+{
+    uint32_t a_buff[SPDIF_AUDIO_BUFFSIZE];               /**< Audio Buffer */
+    uint32_t u_buff[SPDIF_USER_BUFFSIZE];                /**< User Buffer */
+    uint32_t s_buff[SPDIF_NUMOF_CH];                     /**< Channel Status Buffer */
+} spdif_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SPDIF_CONFIG_CHANNEL        (0)
+#define SPDIF_SET_CHANNEL_STATUS    (1)
+#define SPDIF_GET_CHANNEL_STATUS    (2)
+#define SPDIF_SET_TRANS_AUDIO_BIT   (3)
+#define SPDIF_SET_RECV_AUDIO_BIT    (4)
+
+/******************************************************************************
+ External Data
+ *****************************************************************************/
+
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+/**
+* @ingroup API
+*
+* This function returns a pointer to the function table of the SPDIF driver.
+* This is intended to be used as a parameter in the ioif_start_device function.
+*
+* @retval IOIF_DRV_API* - Pointer to the table of functions supported by the
+* driver.
+*
+*/
+extern IOIF_DRV_API *R_SPDIF_MakeCbTbl(void);
+#endif /* end mbed */
+
+extern int_t R_SPDIF_Userdef_InitPinMux(void);
+
+extern uint16_t R_SPDIF_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SPDIF_IF_H */
+/*EOF*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/aioif.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,49 @@
+/******************************************************************************
+ *
+ * $Rev: $
+ * $Date::                           $
+ *
+ * Description : ITRON support functions for IOIF Asynchronous I/O header file
+ *
+ * (C) Copyright RENESAS ELECTRONICS EUROPE Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+#ifndef AIOIF_H
+#define AIOIF_H
+
+#include <ioif_aio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct AHF_S
+{
+    struct aiocb *head;
+    struct aiocb *tail;
+    uint32_t flags;
+    osMutexId_t semid; /* Source Merge 08-81 */
+    osMutexAttr_t* p_cmtx;
+    int32_t saved_int_mask;
+} AHF_S;
+
+#define AHF_CREATESEM   0x1 /* create a semaphore for locking */ /* Source Merge 08-82 */
+#define AHF_LOCKSEM     0x2 /* use a semaphore for locking */    /* Source Merge 08-82 */
+#define AHF_LOCKINT     0x4 /* use interrupts for locking */
+
+/* AHF (Asynchronous Helper Functions */
+int32_t ahf_create (AHF_S * const ahf, const uint32_t f); /* Source Merge 08-83 */
+void ahf_destroy (AHF_S const * const ahf);
+void ahf_addtail (AHF_S * const ahf, struct aiocb * const aio); /* Source Merge 08-04 */
+struct aiocb *ahf_removehead (AHF_S * const ahf);
+int32_t ahf_remove (AHF_S *ahf, struct aiocb *aio);
+struct aiocb *ahf_peekhead (AHF_S * const ahf);
+void ahf_cancelall (AHF_S * const ahf);
+void ahf_complete (AHF_S *ahf, struct aiocb * const aio);
+int32_t ahf_cancel (AHF_S * const ahf, struct aiocb * const aio);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/bsp_drv_cmn.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,45 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          bsp_drv_cmn.h
+* $Rev: $
+* $Date::                           $
+* @brief         BSP Section settings
+******************************************************************************/
+
+#ifndef BSP_DRV_CMN_H
+#define BSP_DRV_CMN_H
+
+#if(1) /* mbed */
+#else  /* not mbed */
+#if defined (__CC_ARM)          /* ARM Compiler */
+
+#pragma arm section code="CODE_RDRV"
+#pragma arm section rodata="CONST_RDRV"
+#pragma arm section rwdata="DATA_RDRV"
+#pragma arm section zidata="BSS_RDRV"
+
+#endif /* __CC_ARM */
+#endif /* end mbed */
+
+#endif /* BSP_DRV_CMN_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/bsp_util.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          bsp_util.h
+* $Rev: $
+* $Date::                           $
+* @brief         BSP Utilities
+******************************************************************************/
+
+#ifndef BSP_UTIL_H
+#define BSP_UTIL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+/* ->MISRA 20.9,This header is no problem because it's based upon the standard of the ANSI. */
+#include <stdio.h>
+/* <-MISRA 20.9 */
+#include "bsp_util.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+int32_t R_ExceptionalMode(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BSP_UTIL_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/ioif_aio.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: $
+ * $Date::                           $
+ *
+ * Description : ioif_aio header file
+ *
+ * Copyright (C) 2009,2012 Renesas Electronics Corporation. All rights reserved.
+ *****************************************************************************/
+
+#ifndef IOIF_AIO_H
+#define IOIF_AIO_H
+
+/*************************************************************************
+ System Includes
+*************************************************************************/
+
+#include <cmsis_os.h>
+#include <posix_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*************************************************************************
+ User Includes
+*************************************************************************/
+
+/*************************************************************************
+ Defines
+*************************************************************************/
+
+/* sigev_notify values */
+
+#define SIGEV_NONE      (1) /**< No notification */
+#define SIGEV_THREAD    (2) /**< A notification function is called in the driver's context */
+#define SIGEV_EVENT     (3) /**< An event flag is set */
+#define SIGEV_CALLBACK  (4) /**< An inter-process callback is made */
+
+/*************************************************************************
+ Constant Macros
+*************************************************************************/
+
+/*************************************************************************
+ Function Macros
+*************************************************************************/
+
+/*************************************************************************
+ Typedefs
+*************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+typedef void *      pthread_attr_t;     /**< unsupported */
+#endif /* end mbed */
+
+union sigval
+{
+    int             sival_int;          /**< Integer interpretation */
+    void *          sival_ptr;          /**< Pointer interpretation */
+};
+
+struct sigevent
+{
+    int             sigev_notify;       /**< SIGEV_NONE, SIGEV_THREAD, SIGEV_EVENT */
+    int             sigev_signo;        /**< signal or callback fp */
+    union sigval    sigev_value;        /**< user defined value to pass */
+    void            (*sigev_notify_function) (union sigval);
+                                        /**< notification function */
+};
+
+struct aiocb
+{
+    /* Implementation specific stuff */
+    struct aiocb *  pNext;              /**< next aio request */
+    struct aiocb *  pPrev;              /**< previous aio request */
+    ssize_t         aio_return;         /**< return value of operation */
+    int             aio_complete;       /**< non-zero when op is completed */
+
+    /* User parameters */
+    int             aio_fildes;         /**< FD for asynchronous op */
+    off_t           aio_offset;         /**< Absolute offset to seek to */
+    volatile void*  aio_buf;            /**< Buffer to read from/write to */
+    size_t          aio_nbytes;         /**< Number of bytes to read/write */
+    struct sigevent aio_sigevent;       /**< Signal to deliver */
+
+    /* Private implementation specific function pointer used by IOIF. Application should not set. */
+    ssize_t (*aio_iofn)(void *,void *,size_t,int);  /* synchronous I/O function */
+};
+typedef struct aiocb AIOCB;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+struct timespec
+{
+    time_t   tv_sec;            /* Seconds.  */
+    long int tv_nsec;           /* Nanoseconds.  */
+};
+#endif /* end mbed */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/misratypes.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,189 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2009-2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: $
+ * $Date::                           $
+ *
+ * Description : Types for MISRA compliant C code.
+ *
+ *****************************************************************************/
+
+#ifndef _MISRATYPES_H_INCLUDED_
+#define _MISRATYPES_H_INCLUDED_
+
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+#include <cmsis_os.h>
+
+/***********************************************************************************
+ User Includes
+***********************************************************************************/
+#include "r_typedefs.h"
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************************
+ Constant Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Function Macros
+***********************************************************************************/
+
+/* Use this macro for an unused function argument */
+#define UNUSED_ARG(var)  (void)unused_arg(&(var))
+
+/* Use this macro to check is a value of any type is an error code */
+#define ISERROR(val) iserror((int32_t)(val))
+
+/* Use this macro when assigning a function for a task */
+#define TO_FP_FUNCTION(val) to_fp_function(val)
+
+/***********************************************************************************
+ Typedefs
+***********************************************************************************/
+
+typedef void (*funcptr_t)(void);
+
+/***********************************************************************************
+ Enumerated Types
+***********************************************************************************/
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+/* These functions are inlined by the SHC compiler in an optimise=1 build */
+static const void* unused_arg(const void* const var);
+static void *error_to_ptr(int32_t er);
+static bool_t iserror(int32_t ser);
+static funcptr_t to_fp_function(void (*val)(int32_t));
+
+/***********************************************************************************
+ Inline Functions
+***********************************************************************************/
+
+/**********************************************************************************
+Function Name:  unused_arg
+Description:    Used to prevent unused argument warnings from QA-C.
+                This function will be inlined by the SHC compiler and generate no code.
+                Use this function via the UNUSED_ARG macro.
+
+Parameters:     Pointer to unused argument
+
+Return value:   Passed in argument.
+***********************************************************************************/
+#if   defined (__CC_ARM)
+#pragma inline unused_arg
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static inline const void* unused_arg(const void* const var)
+{
+    return var;
+}
+
+/**********************************************************************************
+Function Name:  iserror
+Description:    Check if a value is an error code.  This is used instead of the HIOS
+                iserrno macro as that generates many warnings in QA-C.
+                This function will be inlined by the SHC compiler.
+                Use this function via the ISERROR macro.
+
+Parameters:     Value to check for error code
+
+Return value:   Non-zero if the value is an error code
+***********************************************************************************/
+
+#if   defined (__CC_ARM)
+#pragma inline iserror
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static inline bool_t iserror(const int32_t ser)
+{
+    uint32_t er = (uint32_t) ser;
+    return er >= 0xffffff80u;
+}
+
+/**********************************************************************************
+Function Name:  error_to_ptr
+Description:    Convert an error code to a pointer so we can return an error from
+                IOIF driver functions such as open and initialise without getting
+                warnings from QA-C.
+                This function will be inlined by the SHC compiler.
+
+Parameters:     Error code
+
+Return value:   Error code converted to a pointer
+***********************************************************************************/
+#if   defined (__CC_ARM)
+#pragma inline error_to_ptr
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static inline void *error_to_ptr(const int32_t er)
+{
+    return (void*) er;
+}
+
+/**********************************************************************************
+Function Name:  to_fp_function
+Description:    Converts a void (*fn)(VP_INT) function pointer to a FP function pointer
+                without getting warnings from QA-C.
+                This function will be inlined by the SHC compiler.
+
+Parameters:     Function pointer as void (*fn)(VP_INT)
+
+Return value:   Functino pointer as a FP
+***********************************************************************************/
+#if   defined (__CC_ARM)
+#pragma inline to_fp_function
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static inline funcptr_t to_fp_function(void (*val)(int32_t))
+{
+    /* QA-C will generate an error for this line as we are casting
+     * between different function pointer types.
+     */
+    return (funcptr_t)val;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MISRATYPES_H_INCLUDED_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/posix_types.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,153 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2009,2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: $
+ * $Date::                           $
+ *
+ * Description : POSIX types
+ *
+ *****************************************************************************/
+
+#ifndef POSIXTYPES_H_INCLUDED
+#define POSIXTYPES_H_INCLUDED
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+
+
+/***********************************************************************************
+ User Includes
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* From <unistd.h> */
+#ifndef SEEK_SET
+#define SEEK_SET        0           /* from the biginning of file */
+#define SEEK_CUR        1           /* from the current position in file */
+#define SEEK_END        2           /* from the end of file */
+#endif
+
+/* <unistd.h> POSIX Standard: 2.10 file descriptors for stdin, stdout,
+  stderr not included with SHC. Therefore defined below. */
+#ifndef STDIN_FILENO
+    #define STDIN_FILENO (0)
+#endif
+
+#ifndef STDOUT_FILENO
+    #define STDOUT_FILENO (1)
+#endif
+
+#ifndef STDERR_FILENO
+    #define STDERR_FILENO (2)
+#endif
+
+
+/* These values must be as defined under open in the compiler manual
+ * otherwise the buffered file functions fopen() etc. will not work.
+ */
+#if(1) /* mbed */
+#define O_ACCMODE_RBSP  00000007
+#define O_RDONLY_RBSP   00000001
+#define O_WRONLY_RBSP   00000002
+#define O_RDWR_RBSP     00000004
+#else  /* not mbed */
+#define O_ACCMODE       00000007
+#define O_RDONLY        00000001
+#define O_WRONLY        00000002
+#define O_RDWR          00000004
+#define O_CREAT         00000010
+#define O_EXCL          00000020
+#define O_TRUNC         00000040
+#define O_APPEND        00002000
+#define O_NONBLOCK      00004000
+#define O_SYNC          00010000
+#endif /* end mbed */
+
+/***********************************************************************************
+ Constant Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Function Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Typedefs and Structures
+***********************************************************************************/
+
+/* The POSIX standard states that:-
+    mode_t                              shall be an integer type.
+    nlink_t, uid_t, gid_t, and id_t     shall be integer types.
+    blkcnt_t and off_t                  shall be signed integer types.
+    fsblkcnt_t, fsfilcnt_t, and ino_t   shall be defined as unsigned integer types.
+    size_t                              shall be an unsigned integer type.
+    blksize_t, pid_t, and ssize_t       shall be signed integer types.
+    time_t and clock_t                  shall be integer or real-floating types.
+*/
+
+#if(1) /* mbed */
+#ifndef off_t
+typedef long off_t;
+#endif
+#ifndef ssize_t
+typedef int ssize_t;
+#endif
+#else  /* not mbed */
+typedef int fsid_t;
+typedef long time_t;    /* Time in seconds. */
+typedef long long off_t;
+typedef unsigned int mode_t;
+typedef unsigned int ino_t;
+typedef int nlink_t;
+typedef int uid_t;
+typedef int gid_t;
+typedef int dev_t;
+typedef int ssize_t;
+#endif /* end mbed */
+
+#if !defined(__cplusplus) && defined(__STRICT_ANSI__)
+#if defined (__GNUC__)
+typedef unsigned int size_t;
+#else /*__GNUC__*/
+typedef unsigned long size_t;
+#endif/*__GNUC__*/
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/r_errno.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,146 @@
+/*******************************************************************************
+ *
+ * $Rev: $
+ * $Date::                           $
+ *
+ * Description : errno for POSIX IEEE Std 1003.1-2001
+ *
+ * (C) Copyright RENESAS ELECTRONICS Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+#ifndef SDK_ERRNO
+#define SDK_ERRNO
+
+/* Include std headers to override _errno with SDK version */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <math.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _REENTRANT 1
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+/* SDK errno extension, SDK returns 0 as success, and -1 when errno set */
+#define ESUCCESS    (0)
+#define EERROR      (-1)
+
+#if(1) /* mbed */
+#define EBADF_RBSP       (-17) /* Bad file descriptor */
+#define EINVAL_RBSP      (-28) /* Invalid argument */
+#define ENOMEM_RBSP      (-33) /* No memory available */
+#define ENOENT_RBSP      (-42) /* No such file or directory */
+#define EACCES_RBSP      (-64) /* Access denied */
+#define EBUSY_RBSP       (-67) /* Device or resource busy */
+#define ECANCELED_RBSP   (-68) /* Operation was cancelled */
+#define EIO_RBSP         (-74) /* Input or Output error (possibly recoverable)*/
+#define EMFILE_RBSP      (-76) /* Too many open files */
+#define ENOSPC_RBSP      (-84) /* No space available on device */
+#define ENOTSUP_RBSP     (-87) /* Not supported */
+#define EPERM_RBSP       (-90) /* Operation not permitted */
+#define EFAULT_RBSP      (-97) /* Section fault, bad address */
+#define EOVERFLOW_RBSP  (-117) /* Value too large to store in data type */
+#else  /* not mbed */
+#define EBADF       (-17) /* Bad file descriptor */
+#define EINVAL      (-28) /* Invalid argument */
+#define ENOMEM      (-33) /* No memory available */
+#define ENOLCK      (-34) /* No lock available */
+#define ENOENT      (-42) /* No such file or directory */
+#define ETIMEDOUT   (-50) /* Timed out */
+#define EACCES      (-64) /* Access denied */
+#define EAGAIN      (-65) /* Resource unavailable. Try again */
+#define EBUSY       (-67) /* Device or resource busy */
+#define ECANCELED   (-68) /* Operation was cancelled */
+#define EDOM        (-69) /* Maths argument out of domain */
+#define EEXIST      (-70) /* File, directory or mount exists */
+#define EFBIG       (-71) /* File too big */
+#define EINPROGRESS (-72) /* Operation in progress */
+#define EIO         (-74) /* Input or Output error (possibly recoverable)*/
+#define EISDIR      (-75) /* Is a directory */
+#define EMFILE      (-76) /* Too many open files */
+#define ENAMETOOLONG (-77) /* File name too long */
+#define ENFILE      (-78) /* Too many files are open in the system */
+#define ENOBUFS     (-79) /* No buffers available */
+#define ENODEV      (-80) /* Not a valid device */
+#define ENOSPC      (-84) /* No space available on device */
+#define ENOTDIR     (-85) /* Not a directory */
+#define ENOTEMPTY   (-86) /* Directory not empty */
+#define ENOTSUP     (-87) /* Not supported */
+#define ENOTTY      (-88) /* No TTY available */
+#define ENXIO       (-89) /* Not valid IO address or device (unrecoverable)*/
+#define EPERM       (-90) /* Operation not permitted */
+#define EROFS       (-91) /* Read only file system */
+#define ESPIPE      (-92) /* Invalid seek on pipe */
+#define EXDEV       (-93) /* Device cross linked */
+#define ENOTSOCK    (-94) /* Not a socket */
+#define EMSGSIZE    (-95) /* Message too large */
+#define EINTR       (-96) /* Function interrupted */
+#define EFAULT      (-97) /* Section fault, bad address */
+#define EPIPE       (-98) /* Broken pipe */
+#define EALREADY    (-99) /* Connection already started */
+#define EDESTADDRREQ (-100) /* Destination address requred */
+#define EPROTOTYPE  (-101) /* Wrong protocol or codec type */
+#define ENOPROTOOPT (-102) /* Protocol or codec not available */
+#define EPROTONOSUPPORT (-103) /* Protocol or codec not supported */
+#define EOPNOTSUPP  (-104) /* Operation not supported */
+#define EAFNOSUPPORT (-105) /* Address family not supported */
+#define EADDRINUSE  (-106) /* Address already in use */
+#define EADDRNOTAVAIL (-107) /* Address not available */
+#define ECONNRESET  (-108) /* Connection reset */
+#define EISCONN     (-109) /* Connected */
+#define ENOTCONN    (-110) /* Not connected */
+#define ECONNREFUSED (-112) /* Connection refused */
+#define EPROCLIM    (-113) /* Too many processes */
+#define EUSERS      (-114) /* Too many users */
+#define EDEADLK     (-115) /* Resource deadlock would occur */
+#define EPROTO      (-116) /* Protocol or codec error */
+#define EOVERFLOW   (-117) /* Value too large to store in data type */
+#define ESRCH       (-118) /* No such task */
+#define EILSEQ      (-119) /* Illegal byte sequence format */
+#define EBADMSG     (-120) /* Bad message */
+#define ENOSYS      (-121) /* Function not supported */
+#define ECRC        (-122) /* CRC failure */
+#define EEOF        (-123) /* Position is End Of File */
+#define ESEEKPASTEND (-124) /* Seek past EOF */
+#define EMEDIUMTYPE (-127) /* Wrong medium type */
+#define ENOMEDIUM   (-128) /* No medium present */
+#define ESEEKRANGE  (-129) /* seek setting error */  /* Source Merge 11-1 */
+#endif /* end mbed */
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+/* errno is a macro so it is re-entrant (per thread/task value) - this
+ * definition works with SH C libs.  The errno returns an l-value so
+ * it can be used on the left of an assignment as it is legal for an
+ * application to assign to errno.
+ *
+ * Note: Application code should not call ioif_get_errno directly. All
+ * access to errno should be made using the POSIX "errno" macro.
+*/
+extern int *ioif_get_errno(void);
+
+/* Remove SHC definitions so SDK can be used instead */
+#ifdef _errno
+    #undef _errno
+#endif
+
+#define _errno (*ioif_get_errno())
+
+#ifndef  errno
+    #define  errno _errno
+#endif
+
+#define iserrno(e)((unsigned int)(e) >= 0xffffff80UL)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_inc/ssif_if.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,282 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif_if.h
+* $Rev: $
+* $Date::                           $
+* Description  : SSIF Driver API header
+******************************************************************************/
+
+#ifndef SSIF_IF_H
+#define SSIF_IF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+
+#include "r_typedefs.h"
+#include "r_errno.h"
+#if(1) /* mbed */
+#include "misratypes.h"
+#include "aioif.h"
+#include "R_BSP_mbed_fns.h"
+#include "R_BSP_SsifDef.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if(1) /* mbed */
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+
+extern RBSP_MBED_FNS* R_SSIF_MakeCbTbl_mbed(void);
+#else  /* not mbed */
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIF_NUM_CHANS       (6u)    /**< Number of SSIF channels */
+
+#define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u)        /* Disable SSIRDR->STRMDIN0 route */
+#define SSIF_CFG_ENABLE_ROMDEC_DIRECT  (0xDEC0DEC1u) /* Enable  SSIRDR->STRMDIN0 route */
+#else /* mbed */
+#define SSIF_NUM_CHANS       (4u)    /**< Number of SSIF channels */
+#endif /* mbed */
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+
+/** SSICR:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SSIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SSIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} ssif_chcfg_cks_t;
+
+/** SSICR:CHNL(Audio channels per system word) */
+typedef enum
+{
+    SSIF_CFG_MULTI_CH_1 = 0,     /**< 1ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_2 = 1,     /**< 2ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_3 = 2,     /**< 3ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_4 = 3      /**< 4ch within systemword (on tdm=0) */
+} ssif_chcfg_multi_ch_t;
+
+/** SSICR:DWL(Data word length) */
+typedef enum
+{
+    SSIF_CFG_DATA_WORD_8  = 0,   /**< Data word length 8  */
+    SSIF_CFG_DATA_WORD_16 = 1,   /**< Data word length 16 */
+    SSIF_CFG_DATA_WORD_18 = 2,   /**< Data word length 18 */
+    SSIF_CFG_DATA_WORD_20 = 3,   /**< Data word length 20 */
+    SSIF_CFG_DATA_WORD_22 = 4,   /**< Data word length 22 */
+    SSIF_CFG_DATA_WORD_24 = 5,   /**< Data word length 24 */
+    SSIF_CFG_DATA_WORD_32 = 6    /**< Data word length 32 */
+} ssif_chcfg_data_word_t;
+
+/** SSICR:SWL(System word length) */
+typedef enum
+{
+    SSIF_CFG_SYSTEM_WORD_8   = 0,    /**< System word length 8   */
+    SSIF_CFG_SYSTEM_WORD_16  = 1,    /**< System word length 16  */
+    SSIF_CFG_SYSTEM_WORD_24  = 2,    /**< System word length 24  */
+    SSIF_CFG_SYSTEM_WORD_32  = 3,    /**< System word length 32  */
+    SSIF_CFG_SYSTEM_WORD_48  = 4,    /**< System word length 48  */
+    SSIF_CFG_SYSTEM_WORD_64  = 5,    /**< System word length 64  */
+    SSIF_CFG_SYSTEM_WORD_128 = 6,    /**< System word length 128 */
+    SSIF_CFG_SYSTEM_WORD_256 = 7     /**< System word length 256 */
+} ssif_chcfg_system_word_t;
+
+/** SSICR:SCKP(Clock polarity) */
+typedef enum
+{
+    SSIF_CFG_FALLING = 0,    /**< Falling edge */
+    SSIF_CFG_RISING  = 1     /**< Rising edge  */
+} ssif_chcfg_clock_pol_t;
+
+/** SSICR:SWSP(Word select polarity) */
+typedef enum
+{
+    SSIF_CFG_WS_LOW  = 0,    /**< Low for ther 1st channel(not TDM) */
+    SSIF_CFG_WS_HIGH = 1     /**< High for the 1st channel(not TDM) */
+} ssif_chcfg_ws_pol_t;
+
+/** SSICR:SPDP(Serial padding polarity) */
+typedef enum
+{
+    SSIF_CFG_PADDING_LOW  = 0,   /**< Padding bits are low  */
+    SSIF_CFG_PADDING_HIGH = 1    /**< Padding bits are high */
+} ssif_chcfg_padding_pol_t;
+
+/** SSICR:SDTA(Serial data alignment) */
+typedef enum
+{
+    SSIF_CFG_DATA_FIRST    = 0,  /**< Data first         */
+    SSIF_CFG_PADDING_FIRST = 1   /**< Padding bits first */
+} ssif_chcfg_serial_alignment_t;
+
+/** SSICR:PDTA(Parallel data alignment) */
+typedef enum
+{
+    SSIF_CFG_LEFT  = 0,  /**< Left aligned  */
+    SSIF_CFG_RIGHT = 1   /**< Right aligned */
+} ssif_chcfg_parallel_alignment_t;
+
+/** SSICR:DEL(Serial data delay) */
+typedef enum
+{
+    SSIF_CFG_DELAY    = 0,   /**< 1 clock delay */
+    SSIF_CFG_NO_DELAY = 1    /**< No delay      */
+} ssif_chcfg_ws_delay_t;
+
+/** SSICR:CKDV(Serial oversampling clock division ratio) */
+typedef enum
+{
+    SSIF_CFG_CKDV_BITS_1   = 0,
+    SSIF_CFG_CKDV_BITS_2   = 1,
+    SSIF_CFG_CKDV_BITS_4   = 2,
+    SSIF_CFG_CKDV_BITS_8   = 3,
+    SSIF_CFG_CKDV_BITS_16  = 4,
+    SSIF_CFG_CKDV_BITS_32  = 5,
+    SSIF_CFG_CKDV_BITS_64  = 6,
+    SSIF_CFG_CKDV_BITS_128 = 7,
+    SSIF_CFG_CKDV_BITS_6   = 8,
+    SSIF_CFG_CKDV_BITS_12  = 9,
+    SSIF_CFG_CKDV_BITS_24  = 10,
+    SSIF_CFG_CKDV_BITS_48  = 11,
+    SSIF_CFG_CKDV_BITS_96  = 12
+} ssif_chcfg_ckdv_t;
+
+
+/** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
+    SSIF_CFG_ENABLE_NOISE_CANCEL  = 1  /**< Use noise cancel function     */
+} ssif_chcfg_noise_cancel_t;
+
+
+/** SSITDMR:TDM(TDM mode) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_TDM = 0,   /**< not TDM mode */
+    SSIF_CFG_ENABLE_TDM  = 1    /**< set TDM mode */
+} ssif_chcfg_tdm_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+#if defined(TARGET_RZA1H) /* mbed */
+typedef struct
+{
+    uint32_t    mode;               /* Enable/Disable SSIRDR->STRMDIN0 route */
+    void        (*p_cbfunc)(void);  /* SSIF error callback function          */
+} ssif_chcfg_romdec_t;
+
+#endif /* mbed */
+/**< This structure contains the configuration settings */
+typedef struct
+{
+    bool_t                          enabled;             /* The enable flag for the channel       */
+    uint8_t                         int_level;           /* Interrupt priority for the channel    */
+    bool_t                          slave_mode;          /* Mode of operation                     */
+    uint32_t                        sample_freq;         /* Audio Sampling frequency(Hz)          */
+    ssif_chcfg_cks_t                clk_select;          /* SSICR-CKS : Audio clock select        */
+    ssif_chcfg_multi_ch_t           multi_ch;            /* SSICR-CHNL: Audio channels per system word */
+    ssif_chcfg_data_word_t          data_word;           /* SSICR-DWL : Data word length          */
+    ssif_chcfg_system_word_t        system_word;         /* SSICR-SWL : System word length        */
+    ssif_chcfg_clock_pol_t          bclk_pol;            /* SSICR-SCKP: Bit Clock polarity        */
+    ssif_chcfg_ws_pol_t             ws_pol;              /* SSICR-SWSP: Word Clock polarity       */
+    ssif_chcfg_padding_pol_t        padding_pol;         /* SSICR-SPDP: Padding polarity          */
+    ssif_chcfg_serial_alignment_t   serial_alignment;    /* SSICR-SDTA: Serial data alignment     */
+    ssif_chcfg_parallel_alignment_t parallel_alignment;  /* SSICR-PDTA: Parallel data alignment   */
+    ssif_chcfg_ws_delay_t           ws_delay;            /* SSICR-DEL : Serial clock delay        */
+    ssif_chcfg_noise_cancel_t       noise_cancel;        /* GPIO-SNCR : Noise cancel              */
+    ssif_chcfg_tdm_t                tdm_mode;            /* SSITDMR-TDM: TDM mode                 */
+#if defined(TARGET_RZA1H) /* mbed */
+    ssif_chcfg_romdec_t             romdec_direct;       /* DMA : SSIRDR->STRMDIN0 route settings */
+#endif /* mbed */
+} ssif_channel_cfg_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SSIF_CONFIG_CHANNEL        (7)
+#define SSIF_GET_STATUS           (13)
+
+
+/******************************************************************************
+ External Data
+ *****************************************************************************/
+
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+/**
+* @ingroup API
+*
+* This function returns a pointer to the function table of the SSIF driver.
+* This is intended to be used as a parameter in the ioif_start_device function.
+*
+* @retval IOIF_DRV_API* - Pointer to the table of functions supported by the
+* driver.
+*
+*/
+extern IOIF_DRV_API *R_SSIF_MakeCbTbl(void);
+#endif /* end mbed */
+
+extern int_t R_SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl);
+
+extern int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch);
+extern int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div);
+
+extern uint16_t R_SSIF_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SSIF_IF_H */
+/*EOF*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/dma/dma.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1527 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.c
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver internal functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "dma.h"
+#include "aioif.h"
+#include "iodefine.h"
+#include "mbed_critical.h"
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* driver management infrmation */
+static dma_info_drv_t gb_info_drv;
+
+/******************************************************************************
+Private function define (interrupt handler)
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void);
+static void R_DMA_End1InterruptHandler(void);
+static void R_DMA_End2InterruptHandler(void);
+static void R_DMA_End3InterruptHandler(void);
+static void R_DMA_End4InterruptHandler(void);
+static void R_DMA_End5InterruptHandler(void);
+static void R_DMA_End6InterruptHandler(void);
+static void R_DMA_End7InterruptHandler(void);
+static void R_DMA_End8InterruptHandler(void);
+static void R_DMA_End9InterruptHandler(void);
+static void R_DMA_End10InterruptHandler(void);
+static void R_DMA_End11InterruptHandler(void);
+static void R_DMA_End12InterruptHandler(void);
+static void R_DMA_End13InterruptHandler(void);
+static void R_DMA_End14InterruptHandler(void);
+static void R_DMA_End15InterruptHandler(void);
+static void R_DMA_ErrInterruptHandler(void);
+static void R_DMA_EndHandlerProcess(const int_t channel);
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+
+static void  DMA_OpenChannel(const int_t channel);
+
+/******************************************************************************
+* Function Name: DMA_GetDrvInstance
+* Description : Get pointer of gb_info_drv.
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void)
+{
+
+    return &gb_info_drv;
+}
+
+/******************************************************************************
+End of function DMA_GetDrv_Instance
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetDrvChInfo
+* Description : Get pointer of gb_info_drv.info_ch[channel].
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_ch_t *DMA_GetDrvChInfo(const int_t channel)
+{
+
+    return &gb_info_drv.info_ch[channel];
+}
+
+/******************************************************************************
+End of function DMA_GetDrvChInfo
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Initialize
+* Description : Initialize DMA driver.
+* Arguments : *p_dma_init_param -
+*                  Pointer of init parameters.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Registering handler failed.
+******************************************************************************/
+
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param)
+{
+    int_t    retval = ESUCCESS;
+    int_t    ch_count;
+    uint32_t error_code;
+    bool_t   init_check_flag;
+
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for each channel */
+    static volatile struct st_dmac_n *gb_dma_ch_register_addr_table[DMA_CH_NUM] =
+        { &DMAC0,
+          &DMAC1,
+          &DMAC2,
+          &DMAC3,
+          &DMAC4,
+          &DMAC5,
+          &DMAC6,
+          &DMAC7,
+          &DMAC8,
+          &DMAC9,
+          &DMAC10,
+          &DMAC11,
+          &DMAC12,
+          &DMAC13,
+          &DMAC14,
+          &DMAC15
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for common register */
+    static volatile struct st_dmaccommon_n *gb_dma_common_register_addr_table[DMA_CH_NUM] =
+        { &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+
+    /* ->MISRA 11.3, 11.4 This cast is needed for register access. */
+    /* address table of register set for DMARS */
+    static volatile uint32_t *gb_dmars_register_addr_table[DMA_CH_NUM] =
+        { &DMACDMARS0,
+          &DMACDMARS0,
+          &DMACDMARS1,
+          &DMACDMARS1,
+          &DMACDMARS2,
+          &DMACDMARS2,
+          &DMACDMARS3,
+          &DMACDMARS3,
+          &DMACDMARS4,
+          &DMACDMARS4,
+          &DMACDMARS5,
+          &DMACDMARS5,
+          &DMACDMARS6,
+          &DMACDMARS6,
+          &DMACDMARS7,
+          &DMACDMARS7
+        };
+    /* <-MISRA 11.3, 11.4 */
+
+    /* Interrpt handlers table */
+    static const IRQHandler gb_dma_int_handler_table[DMA_CH_NUM] =
+        { &R_DMA_End0InterruptHandler, /* DMA end interrupt for ch0 - ch15 */
+          &R_DMA_End1InterruptHandler,
+          &R_DMA_End2InterruptHandler,
+          &R_DMA_End3InterruptHandler,
+          &R_DMA_End4InterruptHandler,
+          &R_DMA_End5InterruptHandler,
+          &R_DMA_End6InterruptHandler,
+          &R_DMA_End7InterruptHandler,
+          &R_DMA_End8InterruptHandler,
+          &R_DMA_End9InterruptHandler,
+          &R_DMA_End10InterruptHandler,
+          &R_DMA_End11InterruptHandler,
+          &R_DMA_End12InterruptHandler,
+          &R_DMA_End13InterruptHandler,
+          &R_DMA_End14InterruptHandler,
+          &R_DMA_End15InterruptHandler
+        };
+
+    /* Interrupt numbers table */
+    static const IRQn_Type gb_dma_int_num_table[DMA_CH_NUM] =
+        { DMAINT0_IRQn, /* DMA end interrupt for ch0 - ch15 */
+          DMAINT1_IRQn,
+          DMAINT2_IRQn,
+          DMAINT3_IRQn,
+          DMAINT4_IRQn,
+          DMAINT5_IRQn,
+          DMAINT6_IRQn,
+          DMAINT7_IRQn,
+          DMAINT8_IRQn,
+          DMAINT9_IRQn,
+          DMAINT10_IRQn,
+          DMAINT11_IRQn,
+          DMAINT12_IRQn,
+          DMAINT13_IRQn,
+          DMAINT14_IRQn,
+          DMAINT15_IRQn
+        };
+
+    /* element of p_dma_init_param is copied to element of gb_info_drv */
+    gb_info_drv.p_err_aio = p_dma_init_param->p_aio;
+
+    /* set DMA error interrupt number */
+    gb_info_drv.err_irq_num = DMAERR_IRQn;
+
+    /* init channel management information */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        /* set channel number */
+        gb_info_drv.info_ch[ch_count].ch = ch_count;
+
+        /* set DMA end interrupt number */
+        gb_info_drv.info_ch[ch_count].end_irq_num = gb_dma_int_num_table[ch_count];
+
+        /* init next DMA setting flag */
+        gb_info_drv.info_ch[ch_count].next_dma_flag = false;
+
+        if (1U == ((uint32_t)ch_count & CHECK_ODD_EVEN_MASK))
+        {
+            /* set shift number when channel is odd value */
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_ODD_CH;
+            /* set mask value when channel is odd value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_ODD_CH;
+        }
+        else
+        {
+            /* set shift number when channel is even value */
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_EVEN_CH;
+            /* set mask value when channel is even value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_EVEN_CH;
+        }
+
+        /* init DMA setup flag */
+        gb_info_drv.info_ch[ch_count].setup_flag = false;
+
+        /* ->MISRA 11.4 This cast is needed for register access. */
+        /* set DMA register address for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg = gb_dma_ch_register_addr_table[ch_count];
+        /* set common resgiter for channel 0 - 7 */
+        gb_info_drv.info_ch[ch_count].p_dma_common_reg = gb_dma_common_register_addr_table[ch_count];
+        /* <-MISRA 11.4 */
+
+        /* set DMARS register for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_dmars_reg = gb_dmars_register_addr_table[ch_count];
+    }
+
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   N0SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   N1SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   N0DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   N1DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   N0TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   N1TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = CHCTRL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  CHCFG_INIT_VALUE;
+        /* set DMA interval = 0 */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = CHITVL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  CHEXT_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   NXLA_INIT_VALUE;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg)   =   DMARS_INIT_VALUE;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    /* set interrupt output : pulse,
+       set round robin mode  */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+    /* init common resgiter for channel 8 - 15 */
+    /* set interrupt output : pulse,
+       set round robin mode */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+
+    if (ESUCCESS == retval)
+    {
+        /* DMA end interrupt handler register */
+        init_check_flag = false;
+        ch_count = 0;
+        while (false == init_check_flag)
+        {
+            error_code = InterruptHandlerRegister(gb_info_drv.info_ch[ch_count].end_irq_num,
+                                                  gb_dma_int_handler_table[ch_count]
+                                                  );
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+                init_check_flag = true;
+            }
+            if ((DMA_CH_NUM - 1) == ch_count)
+            {
+                init_check_flag = true;
+            }
+            ch_count++;
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* DMA error interrupt handler register */
+            error_code = InterruptHandlerRegister(gb_info_drv.err_irq_num,
+                                                  &R_DMA_ErrInterruptHandler
+                                                 );
+#if(1) /* mbed */
+            GIC_SetPriority(gb_info_drv.err_irq_num, 0x80);
+#endif
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+            }
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* set DMA end interrupt level & priority */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            /* set interrupt level (set edge trigger, 1-N model) */
+            GIC_SetConfiguration(gb_info_drv.info_ch[ch_count].end_irq_num, 3);
+        }
+        /* set DMA error interrupt level (set edge trgger, 1-N model) */
+        GIC_SetConfiguration(gb_info_drv.err_irq_num, 3);
+        /* DMA error interrupt enable */
+        GIC_EnableIRQ(gb_info_drv.err_irq_num);
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* set channel status */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            if ((bool_t)false != p_dma_init_param->channel[ch_count])
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_INIT;
+            }
+            else
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+            }
+        }
+        /* set driver status to DMA_DRV_INIT */
+        gb_info_drv.drv_stat = DMA_DRV_INIT;
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_Initialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_UnInitialize
+* Description : UnInitialize DMA driver.
+* Arguments : None.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Unregistering handler failed
+******************************************************************************/
+
+int_t DMA_UnInitialize(void)
+{
+    int_t            retval = ESUCCESS;
+    int_t            ch_count;
+    uint32_t         error_code;
+    bool_t           uninit_check_flag;
+
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  0;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   0;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = 0;
+    /* init common resgiter for channel 8 - 15 */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = 0;
+
+    /* uninit DMA interrupt */
+    ch_count = 0;
+    uninit_check_flag = false;
+    while (false == uninit_check_flag)
+    {
+        /* disable DMA end interrupt */
+        GIC_DisableIRQ(gb_info_drv.info_ch[ch_count].end_irq_num);
+
+        /* unregister DMA end interrupt handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.info_ch[ch_count].end_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+            uninit_check_flag = true;
+        }
+        if ((DMA_CH_NUM - 1) == ch_count)
+        {
+            uninit_check_flag = true;
+        }
+        ch_count++;
+    }
+    if (ESUCCESS == retval)
+    {
+        /* disable DMA error interrupt */
+        GIC_DisableIRQ(gb_info_drv.err_irq_num);
+
+        /* unregister DMA interrupt error handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.err_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* set channel status to DMA_CH_UNINIT */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+        }
+        /* set driver status to DMA_DRV_UNINIT*/
+        gb_info_drv.drv_stat = DMA_DRV_UNINIT;
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_UnInitialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_OpenChannel
+* Description : DMA channel open.
+*               Set DMA channel status to DMA_CH_OPEN.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+******************************************************************************/
+
+static void DMA_OpenChannel(const int_t channel)
+{
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_OpenChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFreeChannel
+* Description : Find free DMA channel and Get DMA channel.
+* Arguments : None
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     EMFILE_RBSP : When looking for a free channel, but a free
+*                              channel didn't exist.
+******************************************************************************/
+
+int_t DMA_GetFreeChannel(void)
+{
+    int_t           retval = EFAULT_RBSP;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           ch_alloc;
+    bool_t          ch_stat_check_flag;
+
+    /* looking for free channel */
+    ch_stat_check_flag = false;
+    ch_alloc = 0;
+    while (false == ch_stat_check_flag)
+    {
+        dma_info_ch = DMA_GetDrvChInfo(ch_alloc);
+
+        if (false == ch_stat_check_flag)
+        {
+            if (DMA_CH_INIT == dma_info_ch->ch_stat)
+            {
+                DMA_OpenChannel(ch_alloc);
+                retval = ch_alloc;
+                ch_stat_check_flag = true;
+            }
+            if (false ==  ch_stat_check_flag)
+            {
+                ch_alloc++;
+                /* not detected free channel */
+                if (DMA_CH_NUM == ch_alloc)
+                {
+                    /* set error return value */
+                    retval = EMFILE_RBSP;
+                    ch_stat_check_flag = true;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFreeChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFixedChannel
+* Description : Get specified DMA channel number.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     EBUSY : It has been allocated already in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in
+*                             dma_stat_ch_t.
+******************************************************************************/
+
+int_t DMA_GetFixedChannel(const int_t channel)
+{
+    int_t           retval = ESUCCESS;
+    dma_info_ch_t   *dma_info_ch;
+
+    /* allocate the specified number */
+    dma_info_ch = DMA_GetDrvChInfo(channel);
+
+    if (ESUCCESS == retval)
+    {
+        if (DMA_CH_INIT == dma_info_ch->ch_stat)
+        {
+            DMA_OpenChannel(channel);
+            /* return alloc channel number */
+            retval = channel;
+        }
+        else
+        {
+#if(1) /* mbed */
+            retval = EERROR;
+#else
+            /* set error return value */
+            switch (dma_info_ch->ch_stat)
+            {
+                case DMA_CH_UNINIT:
+                    retval = ENOTSUP;
+                break;
+                /* These 2 cases are intentionally combined. */
+                case DMA_CH_OPEN:
+                case DMA_CH_TRANSFER:
+                    retval = EBUSY;
+                break;
+
+                default:
+                    retval = EFAULT;
+                break;
+
+            }
+#endif
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFixedChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_CloseChannel
+* Description : DMA channel close.
+*               Set DMA channel status to DMA_CH_INIT.
+* Arguments : channel -
+*                  Close channel number.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_CloseChannel(const int_t channel)
+{
+    /* clear DMARS register */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) &= gb_info_drv.info_ch[channel].mask_dmars;
+
+    /* set channel status to DMA_CH_INIT */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_INIT;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_CloseChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Setparam
+* Description : Set DMA transfer parameter to Register.
+* Arguments : channel -
+*                  Set up channel number.
+*             *p_ch_setup -
+*                  Set up parameters.
+*             *p_ch_cfg -
+*                  DMA channel config table parameters.
+*             *reqd
+*                  set vaule for REQD bit on CHCFG
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetParam(const int_t channel, const dma_ch_setup_t *const p_ch_setup,
+                  const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd)
+{
+    uint32_t  chcfg_sel;
+    uint32_t  value_dmars;
+
+#if(1) /* mbed */
+    GIC_SetPriority(gb_info_drv.info_ch[channel].end_irq_num, p_ch_setup->int_level);
+#endif
+
+    /* set DMA transfer parameter to DMA channel infomation */
+    gb_info_drv.info_ch[channel].resource =  p_ch_setup->resource;
+    gb_info_drv.info_ch[channel].direction = p_ch_setup->direction;
+    gb_info_drv.info_ch[channel].src_width = p_ch_setup->src_width;
+    gb_info_drv.info_ch[channel].src_cnt =   p_ch_setup->src_cnt;
+    gb_info_drv.info_ch[channel].dst_width = p_ch_setup->dst_width;
+    gb_info_drv.info_ch[channel].dst_cnt =   p_ch_setup->dst_cnt;
+    gb_info_drv.info_ch[channel].p_end_aio = p_ch_setup->p_aio;
+
+    /* set DMARS value and protect non change bit */
+    value_dmars = *(gb_info_drv.info_ch[channel].p_dma_dmars_reg);
+    value_dmars = ((value_dmars & gb_info_drv.info_ch[channel].mask_dmars) |
+                   (uint32_t)(p_ch_cfg->dmars << gb_info_drv.info_ch[channel].shift_dmars));
+    /* set DMARS register value */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) = value_dmars;
+
+    /* set CHCFG regsiter */
+    if (channel < HIGH_COMMON_REG_OFFSET)
+    {
+        chcfg_sel = (uint32_t)channel;
+    }
+    else
+    {
+        chcfg_sel = (uint32_t)(channel - HIGH_COMMON_REG_OFFSET);
+    }
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n
+        = ((uint32_t)CHCFG_FIXED_VALUE |
+           /* ->MISRA 21.1 ,IPA R2.4.1 The value of every parameter won't be minus.
+              and the value after a shift will be less than 0x80000000 certainly.
+           */
+           (((uint32_t)p_ch_setup->dst_cnt << CHCFG_SHIFT_DAD) & CHCFG_MASK_DAD) |
+           (((uint32_t)p_ch_setup->src_cnt << CHCFG_SHIFT_SAD) & CHCFG_MASK_SAD) |
+           (((uint32_t)p_ch_setup->dst_width << CHCFG_SHIFT_DDS) & CHCFG_MASK_DDS) |
+           (((uint32_t)p_ch_setup->src_width << CHCFG_SHIFT_SDS) & CHCFG_MASK_SDS) |
+           /* <-MISRA 21.1, IPA R2.4.1 */
+           p_ch_cfg->tm |
+           p_ch_cfg->lvl |
+           reqd |
+           chcfg_sel);
+
+    /* set setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = true;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_BusParam
+* Description : Set bus parameter for DMA.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t src_bus_addr = (uint32_t)p_dma_data->src_addr;
+    uint32_t dst_bus_addr = (uint32_t)p_dma_data->dst_addr;
+    uint32_t chext_value = (CHEXT_SET_DPR_NON_SECURE | CHEXT_SET_SPR_NON_SECURE);
+
+    /* set bus parameter for SRC */
+    if ((DMA_EXTERNAL_BUS_END >= src_bus_addr)           ||
+        ((DMA_EXTERNAL_BUS_MIRROR_START <= src_bus_addr) &&
+         (DMA_EXTERNAL_BUS_MIRROR_END >= src_bus_addr)))
+
+    {
+        chext_value |= CHEXT_SET_SCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_SCA_STRONG;
+    }
+
+    /* set bus parameter for DST */
+    if ((DMA_EXTERNAL_BUS_END >= dst_bus_addr)           ||
+        ((DMA_EXTERNAL_BUS_MIRROR_START <= dst_bus_addr) &&
+         (DMA_EXTERNAL_BUS_MIRROR_END >= dst_bus_addr)))
+
+    {
+        chext_value |= CHEXT_SET_DCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_DCA_STRONG;
+    }
+
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHEXT_n = chext_value;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_BusParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetData
+* Description : Set DMA transfer address to Register.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+*             next_register_set -
+*                  Number of next register set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                          const uint32_t next_register_set)
+{
+    if (0U == next_register_set)
+    {
+        /* set DMA transfer address parameters to next register set0 */
+        gb_info_drv.info_ch[channel].src_addr0 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr0 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count0 =    p_dma_data->count;
+
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0TB_n = p_dma_data->count;
+    }
+    else
+    {
+        /* set DMA transfer address parameters to next regiter set1 */
+        gb_info_drv.info_ch[channel].src_addr1 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr1 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count1 =    p_dma_data->count;
+
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1TB_n = p_dma_data->count;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetData
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetNextData
+* Description : Set continuous DMA transfer setting.
+* Arguments : channel -
+*                  Set continuous DMA transfer channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t  next_register_set;
+
+    /* check number of next register set for next DMA transfer */
+    /* The reverse number in current number is set in next regsiter set of next DMA. */
+    if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_SR))
+    {
+        next_register_set = 1U;
+    }
+    else
+    {
+        next_register_set = 0U;
+    }
+
+    /* set DMA transfer address for next DMA */
+    DMA_SetData(channel, p_dma_data, next_register_set);
+
+    /* start setting for next DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)(CHCFG_SET_REN | CHCFG_SET_RSW);
+
+    /* set flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = true;
+
+    /* auto restart continous DMA */
+    if ((0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN)) &&
+        (false == gb_info_drv.info_ch[channel].setup_flag))
+    {
+        /* auto restart DMA */
+        DMA_SetData(channel, p_dma_data, 0);
+        DMA_Start(channel, true);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Nextdata
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Start
+* Description : Start DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*           :restart_flag -
+*                  Flag of DMA continous transfer auto restart.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Start(const int_t channel, const bool_t restart_flag)
+{
+    if (false != restart_flag)
+    {
+        /* clear continous DMA setting */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &=
+        ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL | CHCFG_SET_REN);
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+    }
+
+    /* clear setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = false;
+
+    /* reset DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SWRST;
+
+    /* clear mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~((uint32_t)CHCFG_SET_DEM);
+
+    GIC_EnableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+    /* start DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SETEN;
+
+    /* set channel status to DMA_CH_TRANSFER */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_TRANSFER;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Start
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Stop
+* Description : Stop DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*             *p_remain -
+*                  Remain data size of DMA transfer.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Stop(const int_t channel, uint32_t * const p_remain)
+{
+    uint32_t  stop_wait_cnt;
+
+    /* disable DMA end interrupt */
+    GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+    /* stop DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_CLREN;
+
+    /* wait DMA stop */
+    stop_wait_cnt = 0;
+    while ((0 != (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_TACT)) &&
+           (DMA_STOP_WAIT_MAX_CNT > stop_wait_cnt))
+    {
+        stop_wait_cnt++;
+    }
+
+    if (DMA_STOP_WAIT_MAX_CNT <= stop_wait_cnt)
+    {
+        /* NON_NOTICE_ASSERT: wait count is abnormal value (usually, a count is set to 0 or 1) */
+    }
+
+    /* get remain data size */
+    *p_remain = gb_info_drv.info_ch[channel].p_dma_ch_reg->CRTB_n;
+
+    /* set mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+
+    /* clear setting of continuous DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+
+    /* clear TC, END bit */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+
+    /* clear flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = false;
+
+    /* interrupt clear, if interrupt occured already */
+    GIC_ClearPendingIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Stop
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetErrCode
+* Description : Set error code to error code pointer.
+*               If error code pointer is NULL, nothing is done.
+* Arguments : error_code -
+*                  Error code.
+*             *p_errno -
+*                  Pointer of set error code.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetErrCode(const int_t error_code, int32_t * const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetErrCode
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_ErrInterruptHandler
+* Description : DMA error interrupt handler.
+*               Notify error information to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB member.
+******************************************************************************/
+
+static void R_DMA_ErrInterruptHandler(void)
+{
+    uint32_t dstat_er_0_7;
+    uint32_t dstat_er_8_15;
+
+    if (NULL != gb_info_drv.p_err_aio)
+    {
+        /* get error channel number */
+        dstat_er_0_7  = gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DSTAT_ER_0_7;
+        dstat_er_8_15 = gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DSTAT_ER_0_7;
+
+        /* set error infrmation */
+        gb_info_drv.p_err_aio->aio_sigevent.sigev_value.sival_int = (int_t)(dstat_er_0_7 | (dstat_er_8_15 << HIGH_COMMON_REG_OFFSET));
+
+        /* set error code (EIO_RBSP) */
+        gb_info_drv.p_err_aio->aio_return = EIO_RBSP;
+
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.p_err_aio);
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+
+}
+
+/******************************************************************************
+End of function R_DMA_ErrInteruuptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End0InterruptHandler
+* Description : DMA end interrupt handler for channel 0.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_0);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End0InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End1InterruptHandler
+* Description : DMA end interrupt handler for channel 1.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End1InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_1);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End1InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End2InterruptHandler
+* Description : DMA end interrupt handler for channel 2.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End2InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_2);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End2InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End3InterruptHandler
+* Description : DMA end interrupt handler for channel 3.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End3InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_3);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End3InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End4InterruptHandler
+* Description : DMA end interrupt handler for channel 4.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End4InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_4);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End4InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End5InterruptHandler
+* Description : DMA end interrupt handler for channel 5.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End5InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_5);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End5InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End6InterruptHandler
+* Description : DMA end interrupt handler for channel 6.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End6InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_6);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End6InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End7InterruptHandler
+* Description : DMA end interrupt handler for channel 7.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End7InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_7);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End7InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End8InterruptHandler
+* Description : DMA end interrupt handler for channel 8.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End8InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_8);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End8InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End9InterruptHandler
+* Description : DMA end interrupt handler for channel 9.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End9InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_9);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End9InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End10InterruptHandler
+* Description : DMA end interrupt handler for channel 10.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End10InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_10);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End10InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End11InterruptHandler
+* Description : DMA end interrupt handler for channel 11.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End11InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_11);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End11InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End12InterruptHandler
+* Description : DMA end interrupt handler for channel 12.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End12InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_12);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End12InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End13InterruptHandler
+* Description : DMA end interrupt handler for channel 13.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End13InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_13);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End13InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End14InterruptHandler
+* Description : DMA end interrupt handler for channel 14.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End14InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_14);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End14InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End15InterruptHandler
+* Description : DMA end interrupt handler for channel 15.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End15InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_15);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End15InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_EndHandlerProcess
+* Description : DMA end interrupt handler process carry out.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+__INLINE static void R_DMA_EndHandlerProcess(const int_t channel)
+{
+    bool_t   store_next_dma_flag;
+
+    if (NULL != gb_info_drv.info_ch[channel].p_end_aio)
+    {
+        /* disable all irq */
+        core_util_critical_section_enter();
+
+        /* store next_dma_flag */
+        store_next_dma_flag = gb_info_drv.info_ch[channel].next_dma_flag;
+
+        /* clear flag wich indicates that next DMA transfer set already */
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+
+        if (false == store_next_dma_flag)
+        {
+            /* DMA transfer complete */
+            /* mask DMA end interrupt */
+            GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+            /* set channel status to DMA_CH_OPEN */
+            gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+
+            /* set mask of DMA transfer end */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+
+            /* clear setting of continuous DMA */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+
+            /* check EN bit is clear */
+            if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN))
+            {
+                /* set error code (ESUCCESS) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+            }
+            else
+            {
+                /* set error code (EIO_RBSP) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = EIO_RBSP;
+            }
+        }
+        else
+        {
+            /* set next DMA already */
+            /* set error code (ESUCCESS) */
+            gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+        }
+
+        /* clear TC, END bit */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+
+        core_util_critical_section_exit();
+
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.info_ch[channel].p_end_aio);
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function R_DMA_EndHandlerProcess
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/dma/dma.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,266 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.h
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver internal headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_H
+#define DMA_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "dma_if.h"
+#include "cmsis.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Number of channel configure table */
+#if defined(TARGET_RZA1H) /* mbed */
+#define DMA_CH_CONFIG_TABLE_NUM  (95U)
+#else /* mbed */
+#define DMA_CH_CONFIG_TABLE_NUM  (63U)
+#endif /* mbed */
+
+/* Magic Number */
+#define SHIFT_DMARS_EVEN_CH      (0U)  /* Shift Value for DMARS Register access in Even ch */
+#define SHIFT_DMARS_ODD_CH       (16U) /* Shift Value for DMARS Register access in Odd ch */
+#define MASK_DMARS_EVEN_CH       (0xFFFF0000U) /* Mask value for DMARS Register in Even ch */
+#define MASK_DMARS_ODD_CH        (0x0000FFFFU) /* Mask value for DMARS Register in Odd ch */
+#define HIGH_COMMON_REG_OFFSET   (8)  /* for Common Register Access in ch 0-8 */
+#define CHECK_ODD_EVEN_MASK      (0x00000001U)  /* for check value of odd or even */
+#define DMA_STOP_WAIT_MAX_CNT    (10U) /* Loop count for DMA stop (usually, a count is set to 0 or 1) */
+
+/* Register Set Value */
+/* Init Value */
+#define N0SA_INIT_VALUE      (0U)          /* HW init value */
+#define N1SA_INIT_VALUE      (0U)          /* HW init value */
+#define N0DA_INIT_VALUE      (0U)          /* HW init value */
+#define N1DA_INIT_VALUE      (0U)          /* HW init value */
+#define N0TB_INIT_VALUE      (0U)          /* HW init value */
+#define N1TB_INIT_VALUE      (0U)          /* HW init value */
+#define CHCTRL_INIT_VALUE    (0U)          /* HW init value */
+#define CHCFG_INIT_VALUE     (0x01000000U) /* interrupt disable */
+#define CHITVL_INIT_VALUE    (0U)          /* DMA interval = 0 */
+#define CHEXT_INIT_VALUE     (0U)          /* HW init value */
+#define NXLA_INIT_VALUE      (0U)          /* HW init value */
+#define DCTRL_INIT_VALUE     (0x00000001U) /* interrupt output : pulse, round robin mode */
+#define DMARS_INIT_VALUE     (0U)          /* HW init value */
+/* Fixed Setting for CHCFG */
+#define CHCFG_FIXED_VALUE    (0x00000020U) /* register mode, not buffer sweep, interrupt detect when high pulse */
+
+/* Bit Value & Mask */
+/* CHSTAT */
+#define CHSTAT_MASK_SR         (0x00000080U)
+#define CHSTAT_MASK_END        (0x00000020U)
+#define CHSTAT_MASK_ER         (0x00000010U)
+#define CHSTAT_MASK_TACT       (0x00000004U)
+#define CHSTAT_MASK_EN         (0x00000001U)
+/* CHCTRL */
+#define CHCTRL_SET_CLRTC       (0x00000040U)
+#define CHCTRL_SET_CLREND      (0x00000020U)
+#define CHCTRL_SET_SWRST       (0x00000008U)
+#define CHCTRL_SET_CLREN       (0x00000002U)
+#define CHCTRL_SET_SETEN       (0x00000001U)
+/* CHCFG */
+#define CHCFG_SET_REN          (0x40000000U)
+#define CHCFG_MASK_REN         (0x40000000U)
+#define CHCFG_SET_RSW          (0x20000000U)
+#define CHCFG_MASK_RSW         (0x20000000U)
+#define CHCFG_SET_RSEL         (0x10000000U)
+#define CHCFG_MASK_RSEL        (0x10000000U)
+#define CHCFG_SET_DEM          (0x01000000U)
+#define CHCFG_MASK_DEM         (0x01000000U)
+#define CHCFG_MASK_DAD         (0x00200000U)
+#define CHCFG_MASK_SAD         (0x00100000U)
+#define CHCFG_MASK_DDS         (0x000f0000U)
+#define CHCFG_MASK_SDS         (0x0000f000U)
+#define CHCFG_SET_AM_LEVEL     (0x00000100U)
+#define CHCFG_SET_AM_BUS_CYCLE (0x00000200U)
+#define CHCFG_MASK_AM          (0x00000700U)
+#define CHCFG_SET_LVL_EDGE     (0x00000000U)
+#define CHCFG_SET_LVL_LEVEL    (0x00000040U)
+#define CHCFG_MASK_LVL         (0x00000040U)
+#define CHCFG_SET_REQD_SRC     (0x00000000U)
+#define CHCFG_SET_REQD_DST     (0x00000008U)
+#define CHCFG_MASK_REQD        (0x00000008U)
+#define CHCFG_SHIFT_DAD        (21U)
+#define CHCFG_SHIFT_SAD        (20U)
+#define CHCFG_SHIFT_DDS        (16U)
+#define CHCFG_SHIFT_SDS        (12U)
+/* CHEXT */
+#define CHEXT_SET_DCA_NORMAL      (0x00003000U)
+#define CHEXT_SET_DCA_STRONG      (0x00000000U)
+#define CHEXT_SET_DPR_NON_SECURE  (0x00000200U)
+#define CHEXT_SET_SCA_NORMAL      (0x00000030U)
+#define CHEXT_SET_SCA_STRONG      (0x00000000U)
+#define CHEXT_SET_SPR_NON_SECURE  (0x00000002U)
+
+
+/* REQD value in CHCFG is undecided on config table */
+/* used case of a resource is the same and two or more direction value exists.  */
+#define CHCFG_REQD_UNDEFINED   DMA_REQ_MAX
+
+/* Address of area which is the target of setting change */
+#define DMA_EXTERNAL_BUS_START         (0x00000000U)
+#define DMA_EXTERNAL_BUS_END           (0x1FFFFFFFU)
+#define DMA_EXTERNAL_BUS_MIRROR_START  (0x40000000U)
+#define DMA_EXTERNAL_BUS_MIRROR_END    (0x5FFFFFFFU)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* DRV Status */
+typedef enum
+{
+    DMA_DRV_UNINIT = 0,   /* Uninit */
+    DMA_DRV_INIT   = 1    /* Init */
+} dma_stat_drv_t;
+
+/* Channel Status */
+typedef enum
+{
+    DMA_CH_UNINIT   = 0,   /* Uninit */
+    DMA_CH_INIT     = 1,   /* Init */
+    DMA_CH_OPEN     = 2,   /* Open */
+    DMA_CH_TRANSFER = 4    /* Transfer */
+} dma_stat_ch_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Register (Common) */
+typedef struct
+{
+    volatile uint32_t  dctrl;
+    volatile uint32_t  dstat_en;
+    volatile uint32_t  dstat_er;
+    volatile uint32_t  dstat_end;
+    volatile uint32_t  dstat_tc;
+    volatile uint32_t  dstat_sus;
+} dma_reg_common_t;
+
+/* DMA Register (every Channel) */
+typedef struct
+{
+    volatile uint32_t  n0sa;
+    volatile uint32_t  n0da;
+    volatile uint32_t  n0tb;
+    volatile uint32_t  n1sa;
+    volatile uint32_t  n1da;
+    volatile uint32_t  n1tb;
+    volatile uint32_t  crsa;
+    volatile uint32_t  crda;
+    volatile uint32_t  crtb;
+    volatile uint32_t  chstat;
+    volatile uint32_t  chctrl;
+    volatile uint32_t  chcfg;
+    volatile uint32_t  chitvl;
+    volatile uint32_t  chext;
+    volatile uint32_t  nxla;
+    volatile uint32_t  crla;
+} dma_reg_ch_t;
+
+/* Information of Channel */
+typedef struct
+{
+    int_t              ch;                /* Channel Number */
+    dma_stat_ch_t      ch_stat;           /* Channel Status */
+    dma_res_select_t   resource;          /* DMA Transfer Resource */
+    dma_req_dir_t      direction;         /* DMA Transfer Direction */
+    dma_unit_size_t    src_width;         /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     src_cnt;           /* DMA Address Count (Source) */
+    dma_unit_size_t    dst_width;         /* DMA Transfer Unit Size (Destination) */
+    dma_addr_cnt_t     dst_cnt;           /* DMA Address Count (Destination) */
+    void               *src_addr0;        /* Sorce Address (Next Register Set 0)*/
+    void               *dst_addr0;        /* Destination Address (Next Register Set 0)*/
+    uint32_t           count0;            /* DMA Transfer Size (Next Register Set 0)*/
+    void               *src_addr1;        /* Sorce Address (Next Register Set 1)*/
+    void               *dst_addr1;        /* Destination Address (Next Register Set 1)*/
+    uint32_t           count1;            /* DMA Transfer Size (Next Register Set 1)*/
+    IRQn_Type          end_irq_num;       /* DMA end interrupt number */
+    AIOCB              *p_end_aio;        /* set callback function (DMA end interrupt) */
+    bool_t             next_dma_flag;     /* Setting Flag of Continous DMA */
+    uint32_t           shift_dmars;       /* set SHIFT_DMARS_ODD_CH or SHIFT_DMARS_EVEN_CH */
+    uint32_t           mask_dmars;        /* set MASK_DMA_ODD_CH or MASK_DMARS_EVEN_CH */
+    bool_t             setup_flag;        /* incdicate called DMA_Setup() flag */
+    volatile struct st_dmac_n       *p_dma_ch_reg;     /* DMA Register for every channel */
+    volatile struct st_dmaccommon_n *p_dma_common_reg; /* DMA Register for common */
+    volatile uint32_t           *p_dma_dmars_reg;  /* DMARS Regsiter */
+} dma_info_ch_t;
+
+/* Information of Driver */
+typedef struct
+{
+    dma_stat_drv_t  drv_stat;            /* DRV Status */
+    AIOCB           *p_err_aio;          /* set callback function (DMA error interrupt) */
+    IRQn_Type       err_irq_num;         /* DMA error interrupt number */
+    dma_info_ch_t   info_ch[DMA_CH_NUM]; /* Enable Channel */
+} dma_info_drv_t;
+
+/* DMA Channel Configure Table */
+typedef struct
+{
+    dma_res_select_t   dmars;             /* Set Value for DMARS Register */
+    uint32_t           tm;                /* Set Value for TM Bit (CHCFG Register) */
+    uint32_t           lvl;               /* Set Value for LVL Bit (CHCFG Register) */
+    uint32_t           reqd;              /* Set Value for REQD (CHCFG Register) */
+} dma_ch_cfg_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void);
+dma_info_ch_t  *DMA_GetDrvChInfo(const int_t channel);
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param);
+int_t DMA_UnInitialize(void);
+int_t DMA_GetFreeChannel(void);
+int_t DMA_GetFixedChannel(const int_t channel);
+void  DMA_CloseChannel(const int_t channel);
+void  DMA_SetParam(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                   const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd);
+void  DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                 const uint32_t next_register_set);
+void  DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_Start(const int_t channel, const bool_t restart_flag);
+void  DMA_Stop(const int_t channel, uint32_t * const p_remain);
+void  DMA_SetErrCode(const int_t error_code, int32_t * const p_errno);
+
+#endif /* DMA_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/dma/dma_if.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.c
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver interface functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "dma.h"
+#include  "mbed_critical.h"
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Init
+* @brie          Init DMA driver.
+*                Check parameter in this function.
+*
+*                Description:<br>
+*
+* @param[in]     p_dma_init_param :Point of driver init parameter.
+* @param[in,out] p_errno          :Pointer of error code.
+*                                  When pointer is NULL, it isn't set error code.
+*                                  error code -
+*                                  OS error num : Registering handler failed.
+*                                  EPERM_RBSP : Pointer of callback function which called in DMA 
+*                                          error interrupt handler is NULL.
+*                                  EFAULT_RBSP : dma_init_param is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called.  */
+int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t         retval = ESUCCESS;
+    int_t         result_init;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    if (NULL == p_dma_init_param)
+    {
+        /* set error return value */
+        retval = (EERROR);
+        DMA_SetErrCode(EFAULT_RBSP, p_errno);
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+        if (NULL == p_dma_init_param->p_aio)
+        /* <-MISRA 1.2 */
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(EPERM_RBSP, p_errno);
+        }
+    }
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    if (ESUCCESS == retval)
+    {
+        result_init = DMA_Initialize(p_dma_init_param);
+        if (ESUCCESS != result_init)
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(result_init, p_errno);
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Init
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_UnInit
+* @brie          UnInit DMA driver.
+*                Check parameter in this function.
+*
+*                Description:<br>
+*
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           OS error num : Unegistering handler failed.
+*                           EACCES_RBSP : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY_RBSP : It has been allocated already in channel.
+*                           EFAULT_RBSP : Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_UnInit(int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    int_t          result_uninit;
+    dma_info_drv_t *dma_info_drv;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          ch_count;
+    bool_t         ch_stat_check_flag;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    dma_info_drv = DMA_GetDrvInstance();
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check driver status */
+    if (ESUCCESS == retval)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EACCES_RBSP, p_errno);
+        }
+        else
+        {
+            ch_stat_check_flag = false;
+            ch_count = 0;
+            while (false == ch_stat_check_flag)
+            {
+                /* check channel status */
+                dma_info_ch = DMA_GetDrvChInfo(ch_count);
+                if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
+                    (DMA_CH_INIT != dma_info_ch->ch_stat))
+                {
+                    /*  set error return value */
+                    retval = EERROR;
+                    /* check channel status is busy */
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        /* These 2 cases are intentionally combined. */
+                        case DMA_CH_OPEN:
+                        case DMA_CH_TRANSFER:
+                            DMA_SetErrCode(EBUSY_RBSP, p_errno);
+                        break;
+
+                        default:
+                            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+                        break;
+                    }
+                }
+
+                if ((DMA_CH_NUM - 1) == ch_count)
+                {
+                    /* channel status check end */
+                    ch_stat_check_flag = true;
+                }
+                ch_count++;
+            }
+        }
+        /* uninitialize DMA */
+        if (ESUCCESS == retval)
+        {
+            result_uninit = DMA_UnInitialize();
+            if (ESUCCESS != result_uninit)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(result_uninit, p_errno);
+            }
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_UnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Alloc
+* @brie          Open DMA channel.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Open channel number.
+*                           If channel is (-1), it looking for free chanel and allocate.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EINVAL_RBSP : Value of the ch is outside the range of DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
+*                           EACCES_RBSP : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY_RBSP : It has been allocated already in channel.
+*                           EMFILE_RBSP : When looking for a free channel, but a free channel didn't exist.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    int_t           ercd = ESUCCESS;
+    int_t           get_ch_num;
+    dma_info_drv_t  *dma_info_drv;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* check driver status */
+    dma_info_drv = DMA_GetDrvInstance();
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    if (ESUCCESS == ercd)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            ercd =  EACCES_RBSP;
+        }
+        else
+        {
+            /* check channel of argment */
+            if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
+            {
+                if (DMA_ALLOC_CH == channel)
+                {
+                    get_ch_num = DMA_GetFreeChannel();
+                }
+                else
+                {
+                    get_ch_num = DMA_GetFixedChannel(channel);
+                }
+
+                /* check return number or error number */
+                if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
+                {
+                    /* set channel number to return value */
+                    retval = get_ch_num;
+                }
+                else
+                {
+                    /* set error code to error value */
+                    ercd = get_ch_num;
+                }
+            }
+            else
+            {
+                /* set error return value */
+                ercd =  EINVAL_RBSP;
+            }
+        }
+    }
+
+    /* occured error check */
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+        DMA_SetErrCode(ercd, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Alloc
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Free
+* @brie          Close DMA channel.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Close channel number.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EACCES_RBSP : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY_RBSP : It has been start DMA transfer in channel.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    dma_info_drv_t  *dma_info_drv;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+         /* check driver status */
+        dma_info_drv = DMA_GetDrvInstance();
+
+        if (ESUCCESS == retval)
+        {
+            /* check driver status */
+            if (DMA_DRV_INIT == dma_info_drv->drv_stat)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        DMA_CloseChannel(channel);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                            break;
+
+                            case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                            break;
+
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+            else
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EACCES_RBSP, p_errno);
+
+            }
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Free
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Setup
+* @brie          Setup DMA transfer parameter.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Setup channel number.
+* @param[in]     p_ch_setup:Set up parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY_RBSP : It has been start DMA transfer in channel.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EPERM_RBSP : The value in p_ch_setup isn't in the right range.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_ch_setup is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t            retval = ESUCCESS;
+    dma_info_ch_t    *dma_info_ch;
+    int_t            error_code;
+    uint32_t         cfg_table_count;
+    dma_ch_cfg_t     ch_cfg_set_table;
+    uint32_t         set_reqd;
+    bool_t           check_table_flag;
+
+    /* Resouce Configure Set Table */
+    static const dma_ch_cfg_t ch_cfg_table[DMA_CH_CONFIG_TABLE_NUM] =
+    {
+        {DMA_RS_OSTIM0,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_OSTIM1,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI0A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI1A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI2A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI3A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI4A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#if (DMA_CH_CONFIG_TABLE_NUM >= 95) /* mbed */
+        {DMA_RS_TXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#endif /* mbed */
+        {DMA_RS_USB0_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB0_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_ADEND,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#if (DMA_CH_CONFIG_TABLE_NUM >= 95) /* mbed */
+        {DMA_RS_IEBBTD,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IEBBTV,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IREADY,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_FLDT,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+#endif /* mbed */
+        {DMA_RS_SDHI_0T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_0R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SDHI_1T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_1R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_MMCT,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MMCR,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI2,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI3,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI3,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#if (DMA_CH_CONFIG_TABLE_NUM >= 95) /* mbed */
+        {DMA_RS_SSIRTI4,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI5,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI5,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#endif /* mbed */
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#if (DMA_CH_CONFIG_TABLE_NUM >= 95) /* mbed */
+        {DMA_RS_SPTI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#endif /* mbed */
+        {DMA_RS_SPDIFTXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPDIFRXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+#if (DMA_CH_CONFIG_TABLE_NUM >= 95) /* mbed */
+        {DMA_RS_CMI1,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_CMI2,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MLBCI,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SGDEI0,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI1,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI2,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI3,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+#endif /* mbed */
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+#if (DMA_CH_CONFIG_TABLE_NUM < 95) /* mbed */
+        {DMA_RS_RI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  }
+#else /* mbed */
+        {DMA_RS_RI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN0_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN0_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN1_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN1_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  }
+#endif /* mbed */
+    };
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    /* dummy init set_reqd */
+    set_reqd = CHCFG_REQD_UNDEFINED;
+    ch_cfg_set_table = ch_cfg_table[0];
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_ch_setup)
+        {
+            /* check setup parameter */
+            /* check AIOCB pointer */
+            if (NULL == p_ch_setup->p_aio)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM_RBSP, p_errno);
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for destination */
+                if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) ||
+                    ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for source */
+                if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) ||
+                    ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for destination */
+                if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) ||
+                    ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for source */
+                if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) ||
+                    ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer direction */
+                if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) ||
+                    ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer resouce */
+                check_table_flag = false;
+                cfg_table_count = 0;
+                while (false == check_table_flag)
+                {
+                    if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
+                    {
+                        /* check reqd is undefined */
+                        if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
+                        {
+                            /* set reqd value on fixed value */
+                            if (DMA_REQ_SRC == p_ch_setup->direction)
+                            {
+                                set_reqd = CHCFG_SET_REQD_SRC;
+                            }
+                            else
+                            {
+                                set_reqd = CHCFG_SET_REQD_DST;
+                            }
+                        }
+                        else
+                        {
+                            /* set reqd value in channel config table */
+                            set_reqd = ch_cfg_table[cfg_table_count].reqd;
+                        }
+                        /* set channel config table address for DMA_SetParam() */
+                        ch_cfg_set_table = ch_cfg_table[cfg_table_count];
+                        check_table_flag = true;
+                    }
+                    if (false == check_table_flag)
+                    {
+                        /* resource value did not exist in channel config table */
+                        if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EPERM_RBSP, p_errno);
+                            check_table_flag = true;
+                        }
+                        cfg_table_count++;
+                    }
+                }
+            }
+
+            /* disable all irq */
+            core_util_critical_section_enter();
+
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set up parameter */
+                        DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                            break;
+
+                            case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                            break;
+
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+
+            core_util_critical_section_exit();
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_SetParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Start
+* @brie          Start DMA transfer.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :DMA start channel number.
+* @param[in]     p_dma_data:DMA address parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY_RBSP : It has been start DMA transfer in channel.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EPERM_RBSP : The value in p_ch_setup isn't in the right range.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM_RBSP, p_errno);
+            }
+
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set bus paramter for DMA */
+                        DMA_BusParam(channel, p_dma_data);
+                        /* set up address parameter */
+                        /* Next register set is 0 */
+                        DMA_SetData(channel, p_dma_data, 0);
+                        /* DMA transfer start */
+                        DMA_Start(channel, false);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                             break;
+
+                             case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                             break;
+
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                             break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Start
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_NextData
+* @brie          Set continous DMA mode.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Continuous DMA channel number.
+* @param[in,out] p_dma_data:DMA address parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY_RBSP : It has been set continous DMA transfer.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EPERM_RBSP : The value in p_ch_setup isn't in the right range.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                     int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM_RBSP, p_errno);
+            }
+
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
+                        (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
+                    {
+                        if (false == dma_info_ch->next_dma_flag)
+                        {
+                            /* set up address parameter for continous DMA*/
+                            DMA_SetNextData(channel, p_dma_data);
+                        }
+                        else
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EBUSY_RBSP, p_errno);
+                        }
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                            break;
+
+                            case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_NextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Cancel
+* @brie          Cancel DMA transfer.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Cancel DMA channel number.
+* @param[in]    p_remain   :Remain data size of DMA transfer when it stopping.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT or DMA_CH_OPEN. (DMA stopped)
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_remain is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        /* check whether p_remain is NULL */
+        if (NULL != p_remain)
+        {
+            dma_info_ch = DMA_GetDrvChInfo(channel);
+
+            if (ESUCCESS == retval)
+            {
+                if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
+                {
+                    /* set up address parameter for continous DMA*/
+                    DMA_Stop(channel, p_remain);
+                }
+                else
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        case DMA_CH_UNINIT:
+                            error_code = ENOTSUP_RBSP;
+                        break;
+
+                        case DMA_CH_INIT:
+                            error_code = EBADF_RBSP;
+                        break;
+
+                        case DMA_CH_OPEN:
+                            error_code = EBADF_RBSP;
+                        break;
+
+                        default:
+                            error_code = EFAULT_RBSP;
+                        break;
+                    }
+                    DMA_SetErrCode(error_code, p_errno);
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Cancel
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/dma/dma_ver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         dma_ver.c
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "dma_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define DMA_DRV_VER_MAJOR  (2u)
+#define DMA_DRV_VER_MINOR  (2u)
+
+#define DMA_DRV_VER_MASK   (0xFFu)
+#define DMA_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_GetVersion
+* @brief         Get DMA driver version.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_DMA_GetVersion(void)
+{
+    const uint16_t version =
+        ((DMA_DRV_VER_MAJOR & DMA_DRV_VER_MASK) << DMA_DRV_VER_SHIFT)
+        | (DMA_DRV_VER_MINOR & DMA_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_DMA_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux.c
+* $Rev: $
+* $Date::                           $
+* @brief        SCUX Driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include "mbed_critical.h"
+
+#if(1) /* mbed */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define INIT_WAIT_TIME_MSEC (1)
+#define INIT_WAIT_NUM       (1000U)
+
+#endif /* end mbed */
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/* ->MISRA 8.8 This description is based on the way to fill out OS defined. */
+/* ->IPA M2.2.2, MISRA 8.10 This description is based on the way to fill out OS defined. */
+osSemaphoreDef(scux_ch0_access);
+osSemaphoreDef(scux_ch1_access);
+osSemaphoreDef(scux_ch2_access);
+osSemaphoreDef(scux_ch3_access);
+
+osSemaphoreDef(scux_ssif_ch0_access);
+osSemaphoreDef(scux_ssif_ch1_access);
+osSemaphoreDef(scux_ssif_ch2_access);
+osSemaphoreDef(scux_ssif_ch3_access);
+#if defined(TARGET_RZA1H) /* mbed */
+osSemaphoreDef(scux_ssif_ch4_access);
+osSemaphoreDef(scux_ssif_ch5_access);
+#endif /* mbed */
+
+osSemaphoreDef(scux_shared_access);
+/* <-MISRA 8.10, IPA M2.2.2 */
+/* <-MISRA 8.8 */
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* driver management infrmation */
+static scux_info_drv_t gb_scux_info_drv = {
+    SCUX_DRV_UNINIT,
+    {
+        {SCUX_CH_0, false, 0, SCUX_CH_UNINIT}, /* ch0 */
+        {SCUX_CH_1, false, 0, SCUX_CH_UNINIT}, /* ch1 */
+        {SCUX_CH_2, false, 0, SCUX_CH_UNINIT}, /* ch2 */
+        {SCUX_CH_3, false, 0, SCUX_CH_UNINIT}  /* ch3 */
+    }
+};
+
+/* SSIF management information */
+static scux_ssif_info_t gb_scux_ssif_info[SCUX_SSIF_CH_NUM];
+
+/* ->MISRA 11.3, 11.4 11.5 This cast is needed for register access. */
+/* address table of register set for each SCUX channel */
+static scux_reg_info_t p_scux_ch_reg_addr_table[SCUX_CH_NUM] = {
+    {
+        &SCUX_FROM_DVUIR_DVU0_0,
+        &SCUX_FROM_SRCIR0_2SRC0_0,
+        &SCUX_FROM_FFUIR_FFU0_0,
+        &SCUX_FROM_FFDIR_FFD0_0,
+        &SCUX_FROM_OPCIR_OPC0_0,
+        &SCUX_FROM_IPCIR_IPC0_0,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBAR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD0_CIM,
+        &SCUXDMATU0_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL0_CIM,
+        &SCUXFUTSEL0_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL0_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_1,
+        &SCUX_FROM_SRCIR0_2SRC0_0,
+        &SCUX_FROM_FFUIR_FFU0_1,
+        &SCUX_FROM_FFDIR_FFD0_1,
+        &SCUX_FROM_OPCIR_OPC0_1,
+        &SCUX_FROM_IPCIR_IPC0_1,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBBR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD1_CIM,
+        &SCUXDMATU1_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL1_CIM,
+        &SCUXFUTSEL1_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL1_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_2,
+        &SCUX_FROM_SRCIR0_2SRC0_1,
+        &SCUX_FROM_FFUIR_FFU0_2,
+        &SCUX_FROM_FFDIR_FFD0_2,
+        &SCUX_FROM_OPCIR_OPC0_2,
+        &SCUX_FROM_IPCIR_IPC0_2,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBCR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD2_CIM,
+        &SCUXDMATU2_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL2_CIM,
+        &SCUXFUTSEL2_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL2_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_3,
+        &SCUX_FROM_SRCIR0_2SRC0_1,
+        &SCUX_FROM_FFUIR_FFU0_3,
+        &SCUX_FROM_FFDIR_FFD0_3,
+        &SCUX_FROM_OPCIR_OPC0_3,
+        &SCUX_FROM_IPCIR_IPC0_3,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBDR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD3_CIM,
+        &SCUXDMATU3_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL3_CIM,
+        &SCUXFUTSEL3_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL3_CIM,
+        &SCUXMIXRSEL_CIM
+    }
+};
+/* <-MISRA 11.3, 11.4 11.5 */
+
+/* ->MISRA 11.3 This cast is needed for register access. */
+/* address table of register set for each SSIF channel */
+static volatile struct st_ssif * const p_scux_ssif_ch_reg_addr[SCUX_SSIF_CH_NUM] =
+{
+    &SSIF0,
+    &SSIF1,
+    &SSIF2,
+    &SSIF3,
+#if defined(TARGET_RZA1H) /* mbed */
+    &SSIF4,
+    &SSIF5
+#endif /* mbed */
+};
+/* <-MISRA 11.3 */
+
+/* SCUX semaphore table define */
+static const osSemaphoreAttr_t * const p_semdef_ch_scux_access[SCUX_CH_NUM] =
+{
+    osSemaphore(scux_ch0_access),
+    osSemaphore(scux_ch1_access),
+    osSemaphore(scux_ch2_access),
+    osSemaphore(scux_ch3_access)
+};
+
+/* SSIF semaphore table define */
+static const osSemaphoreAttr_t * const p_semdef_ch_scux_ssif_access[SCUX_SSIF_CH_NUM] =
+{
+    osSemaphore(scux_ssif_ch0_access),
+    osSemaphore(scux_ssif_ch1_access),
+    osSemaphore(scux_ssif_ch2_access),
+    osSemaphore(scux_ssif_ch3_access),
+#if defined(TARGET_RZA1H) /* mbed */
+    osSemaphore(scux_ssif_ch4_access),
+    osSemaphore(scux_ssif_ch5_access)
+#endif /* mbed */
+};
+
+/* write DMA resource define */
+static const dma_res_select_t gb_dma_res_select_tx[SCUX_CH_NUM] =
+{
+    DMA_RS_SCUTXI0,
+    DMA_RS_SCUTXI1,
+    DMA_RS_SCUTXI2,
+    DMA_RS_SCUTXI3
+};
+
+/* read DMA resource define */
+static const dma_res_select_t gb_dma_res_select_rx[SCUX_CH_NUM] =
+{
+    DMA_RS_SCURXI0,
+    DMA_RS_SCURXI1,
+    DMA_RS_SCURXI2,
+    DMA_RS_SCURXI3
+};
+
+/* write dummy data buffer */
+static uint8_t gb_scux_write_dummy_buf[SCUX_DUMMY_BUF_SIZE];
+
+/* read dummy data buffer */
+static uint8_t gb_scux_read_dummy_buf[SCUX_DUMMY_BUF_SIZE];
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+
+static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT]);
+static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch);
+static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag);
+static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch);
+#if(1) /* mbed */
+static int_t SCUX_CmnUnInitialize(void);
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_GetDrvInstance
+* @brief         Get pointer of gb_scux_info_drv.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        pointer of gb_scux_info_drv -
+*                  driver instance.
+******************************************************************************/
+
+scux_info_drv_t *SCUX_GetDrvInstance(void)
+{
+
+    return &gb_scux_info_drv;
+}
+
+/******************************************************************************
+End of function SCUX_GetDrv_Instance
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_GetDrvChInfo
+* @brief         gb_scux_info_drv.info_ch[channel].
+*
+*                Description:<br>
+*
+* @param[in]     channel information number.
+* @retval        pointer of gb_scux_info_drv -
+*                  pointer of channel information.
+******************************************************************************/
+
+scux_info_ch_t *SCUX_GetDrvChInfo(const int_t channel)
+{
+
+    return &gb_scux_info_drv.info_ch[channel];
+}
+
+/******************************************************************************
+End of function SCUX_GetDrvChInfo
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_GetSsifChInfo
+* @brief         gb_scux_ssif_info.channel.
+*
+*                Description:<br>
+*
+* @param[in]     SSIF channel number.
+* @retval        pointer of gb_scux_ssif_info -
+*                  pointer of SSIF information.
+******************************************************************************/
+
+scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel)
+{
+
+    return &gb_scux_ssif_info[channel];
+}
+
+/******************************************************************************
+End of function SCUX_GetSsifChInfo
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_InitializeOne
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :initialize channel number.
+* @param[in]     p_scux_init_param :Initialize parameter for SCUX. 
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+*                    error code -
+*                       ENOMEM_RBSP : Making semaphore is failed.
+*                       EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param)
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    scux_ch_count;
+    int_t    audio_ch_count;
+    scux_ssif_ch_num_t    ssif_ch_count;
+    uint32_t cpg_value;
+    bool_t   init_shared_flag = false;
+    volatile uint8_t dummy_buf;
+    uint32_t scux_init_count;
+    int_t    uninit_ercd;
+    bool_t   init_start_flag = false;
+    bool_t   uninit_all_flag = false;
+    uint32_t i;
+
+    if (NULL == p_scux_init_param)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else if (false == p_scux_init_param->enabled)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* init channel management information */
+        scux_ch_count = channel;
+
+        for (i = 0; ((i < INIT_WAIT_NUM) && (false == init_start_flag)); i++)
+        {
+            core_util_critical_section_enter();
+
+            if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
+            {
+                /* already scux driver shared information is initialized */
+                init_shared_flag = true;
+
+                /* enable the channel */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+
+                init_start_flag = true;
+            }
+            else if (SCUX_DRV_UNINIT == gb_scux_info_drv.drv_stat)
+            {
+                /* change the status to scux initialization running */
+                gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+
+                for (scux_init_count = SCUX_CH_0; scux_init_count < SCUX_CH_NUM; scux_init_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_init_count].enabled = false;
+                    gb_scux_info_drv.info_ch[scux_init_count].ch_stat = SCUX_CH_UNINIT;
+
+                    gb_scux_info_drv.info_ch[scux_init_count].sem_ch_scux_access = NULL;
+                }
+
+                for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                {
+                    gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+                }
+
+                gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+
+                /* enable the channel */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+
+                init_start_flag = true;
+            }
+            else
+            {
+                /* do nothing : SCUX_DRV_INIT_RUNNING */
+            }
+
+            core_util_critical_section_exit();
+
+            if (false == init_start_flag)
+            {
+                /* wait for the change of drv_stat to SCUX_DRV_INIT */
+                (void)osDelay(INIT_WAIT_TIME_MSEC);
+            }
+        }
+
+        if (false == init_start_flag)
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            {
+    
+                /* copy parameter */
+                /* set interrupt parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param->int_level;
+                        
+                /* set route parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param->route;
+                
+                /* set SRC paramter */
+                SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param->src_cfg);
+                
+                /* init SCUX parameter */
+                if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
+                }
+                else
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
+                
+                /* init DVU parameter */
+                for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false; 
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
+             
+                if (false == init_shared_flag)
+                {
+                    /* init MIX parameter */
+                    gb_scux_info_drv.shared_info.mix_setup = false;
+                    gb_scux_info_drv.shared_info.mix_run_ch = 0U;
+                    gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
+                    
+                    /* init SSIF parameter */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
+                        gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
+                        gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
+                        gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
+                    }
+                    
+                    /* init regsiter store value */
+                    gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
+                }
+            
+                /* set register address */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
+                                       
+                if (false == init_shared_flag) {
+                    core_util_critical_section_enter();
+
+                    /* supply clock for SCUX */
+                    cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
+                    CPG.STBCR8 = (uint8_t)cpg_value;
+                    dummy_buf = CPG.STBCR8;
+#if(1) /* mbed */
+                    (void)dummy_buf;
+#endif
+                    
+                    core_util_critical_section_exit();
+
+                    /* software reset */
+                    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+                    SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
+                }
+                
+                /* init DVU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+                
+                /* init SRC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
+                
+                /* init FFU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+                
+                /* init FFD register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                
+                /* init OPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+    
+                /* init IPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+    
+                /* init MIX register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+                
+                /* init CIM register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                
+                /* init shared register */
+                if (false == init_shared_flag)
+                {
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+                }
+                
+                if (false == init_shared_flag)
+                {
+                    /* set SSIF register */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
+                    }
+                }
+            
+                /* set  semaphore parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreNew(0xffff, 1, p_semdef_ch_scux_access[scux_ch_count]);
+                if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                     retval = ENOMEM_RBSP;
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++) 
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreNew(0xffff, 1, p_semdef_ch_scux_ssif_access[ssif_ch_count]);
+                        if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+                        {
+                            retval = ENOMEM_RBSP;
+                        }
+                    }
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreNew(0xffff, 1, osSemaphore(scux_shared_access));
+                    if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
+                    {
+                        retval = ENOMEM_RBSP;
+                    }
+                }
+                
+                
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
+            }
+
+            if (ESUCCESS != retval)
+            {
+                /* uninit each resouces */
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+
+                if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                    /* semaphore delete */
+                    sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set error return value */
+                        retval = EFAULT_RBSP;
+                    }
+
+                    gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+                }
+
+                core_util_critical_section_enter();
+
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+
+                for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
+                {
+                    if (false != gb_scux_info_drv.info_ch[i].enabled)
+                    {
+                        break;
+                    }
+                }
+
+                if (SCUX_CH_NUM == i)
+                {
+                    gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+                    uninit_all_flag = true;
+                }
+
+                core_util_critical_section_exit();
+
+                if (false != uninit_all_flag)
+                {
+                    /* uninitialize driver infomation */
+                    uninit_ercd = SCUX_CmnUnInitialize();
+                    if (ESUCCESS != uninit_ercd)
+                    {
+                        retval = uninit_ercd;
+                    }
+
+                    gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+                }
+            }
+            else
+            {
+                gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_InitializeOne
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_UnInitializeOne
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :unInitialize channel number.
+* @retval        None.
+******************************************************************************/
+void SCUX_UnInitializeOne(const int_t channel)
+{
+    osStatus sem_ercd;
+    int_t    ercd;
+    int_t    scux_ch_count;
+    int_t    ssif_ch_count;
+    bool_t   uninit_all_flag = false;
+    uint32_t i;
+
+    scux_ch_count = channel;
+    if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+    {
+        /* check ch_stat whether going transfer */
+        if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) && 
+            (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
+            (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
+        {
+            /* The exclusive access control (interrupt disabled) starts */
+            core_util_critical_section_enter();
+
+            /* This exclusive access control ends in the SCUX_IoctlClearStop */
+            /* call the __enable_irq in the SCUX_IoctlClearStop */
+            ercd = SCUX_IoctlClearStop(scux_ch_count);
+            if (ESUCCESS != ercd)
+            {
+                /* NON_NOTICE_ASSERT: SCUX stop failed */
+            }
+            
+            ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
+            if (ESUCCESS != ercd)
+            {
+                 /* NON_NOTICE_ASSERT: DMA release failed */
+            }
+        }
+    }
+    
+    if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+    {
+        if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
+        {
+            /* NON_NOTICE_ASSERT: abnormal status */
+        }
+        
+        /* uninit each resouces */
+        gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+        
+        if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+        {
+            /* delete each semaphore  */
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+
+            sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+
+            gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+        }
+        
+        /* delete queue */
+        ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+        ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+    }
+
+    core_util_critical_section_enter();
+
+    gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+
+    for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
+    {
+        if (false != gb_scux_info_drv.info_ch[i].enabled)
+        {
+            break;
+        }
+    }
+
+    if (SCUX_CH_NUM == i)
+    {
+        if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
+        {
+            gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+            uninit_all_flag = true;
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    if (false != uninit_all_flag)
+    {
+        for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+        {
+            if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+            {
+                sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* NON_NOTICE_ASSERT: semaphore error */
+                }
+            }
+        }
+
+        if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
+        {
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+        }
+
+        /* uninitialize driver infomation */
+        (void)SCUX_CmnUnInitialize();
+
+        gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+    }
+}
+
+/******************************************************************************
+End of function SCUX_UnInitializeOne
+******************************************************************************/
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_Initialize
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*
+* @param[in]     p_scux_init_param :Initialize parameter for SCUX.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+*                    error code -
+*                       ENOMEM_RBSP : Making semaphore is failed.
+*                       EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param)
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    scux_ch_count;
+    int_t    audio_ch_count;
+    scux_ssif_ch_num_t    ssif_ch_count;
+    uint32_t cpg_value;
+    bool_t   init_shared_flag = false;
+    volatile uint8_t dummy_buf;
+
+    if (NULL == p_scux_init_param)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* init channel management information */
+        for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+        {
+            if (false == p_scux_init_param[scux_ch_count].enabled)
+            {
+                /* set disable parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            }
+            else
+            {
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+
+                /* copy parameter */
+                /* set interrupt parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param[scux_ch_count].int_level;
+
+                /* set route parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param[scux_ch_count].route;
+
+                /* set SRC paramter */
+                SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param[scux_ch_count].src_cfg);
+
+                /* init SCUX parameter */
+                if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
+                }
+                else
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
+
+                /* init DVU parameter */
+                for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false;
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
+
+                if (false == init_shared_flag)
+                {
+                    /* init MIX parameter */
+                    gb_scux_info_drv.shared_info.mix_setup = false;
+                    gb_scux_info_drv.shared_info.mix_run_ch = 0U;
+                    gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
+
+                    /* init SSIF parameter */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
+                        gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
+                        gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
+                        gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
+                    }
+
+                    /* init regsiter store value */
+                    gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
+                }
+
+                /* set register address */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
+
+                if (false == init_shared_flag) {
+                    core_util_critical_section_enter();
+
+                    /* supply clock for SCUX */
+                    cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
+                    CPG.STBCR8 = (uint8_t)cpg_value;
+                    dummy_buf = CPG.STBCR8;
+#if(1) /* mbed */
+                    (void)dummy_buf;
+#endif
+
+                    core_util_critical_section_exit();
+
+                    /* software reset */
+                    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+                    SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
+                }
+
+                /* init DVU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+
+                /* init SRC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
+
+                /* init FFU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+
+                /* init FFD register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+
+                /* init OPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+
+                /* init IPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+
+                /* init MIX register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+
+                /* init CIM register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+
+                /* init shared register */
+                if (false == init_shared_flag)
+                {
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+                }
+
+                if (false == init_shared_flag)
+                {
+                    /* set SSIF register */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
+                    }
+                }
+
+                /* set  semaphore parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreNew(0xffff, 1, p_semdef_ch_scux_access[scux_ch_count]);
+                if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                     retval = ENOMEM_RBSP;
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreNew(0xffff, 1, p_semdef_ch_scux_ssif_access[ssif_ch_count]);
+                        if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+                        {
+                            retval = ENOMEM_RBSP;
+                        }
+                    }
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreNew(0xffff, 1, osSemaphore(scux_shared_access));
+                    if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
+                    {
+                        retval = ENOMEM_RBSP;
+                    }
+                }
+
+                if (false == init_shared_flag)
+                {
+                    init_shared_flag = true;
+                }
+
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
+            }
+        }
+    }
+
+    if (ESUCCESS != retval)
+    {
+        for (scux_ch_count = SCUX_SSIF_CH_0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+        {
+            if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+            {
+                /* semaphore delete */
+                sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set error return value */
+                    retval = EFAULT_RBSP;
+                }
+
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            }
+        }
+
+        for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+        {
+            sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                retval = EFAULT_RBSP;
+            }
+        }
+
+        sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* set error return value */
+            retval = EFAULT_RBSP;
+        }
+
+        gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+    }
+    else
+    {
+        gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_Initialize
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_UnInitialize
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*
+* @param[in]     None.
+* @retval        None.
+******************************************************************************/
+void SCUX_UnInitialize(void)
+{
+    osStatus sem_ercd;
+    int_t    ercd;
+    int_t    scux_ch_count;
+    int_t    ssif_ch_count;
+    uint32_t cpg_value;
+
+    for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+    {
+        if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+        {
+            /* check ch_stat whether going transfer */
+            if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
+                (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
+                (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
+            {
+                core_util_critical_section_enter();
+
+                /* This exclusive access control ends in the SCUX_IoctlClearStop */
+                ercd = SCUX_IoctlClearStop(scux_ch_count);
+                if (ESUCCESS != ercd)
+                {
+                    /* NON_NOTICE_ASSERT: SCUX stop failed */
+                }
+
+                ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
+                if (ESUCCESS != ercd)
+                {
+                     /* NON_NOTICE_ASSERT: DMA release failed */
+                }
+            }
+        }
+    }
+
+    /* software reset */
+    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+
+    for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+    {
+        if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+        {
+            if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
+            {
+                /* NON_NOTICE_ASSERT: abnormal status */
+            }
+
+            /* uninit each resouces */
+            gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+
+            /* delete each semaphore  */
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+
+            sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+
+            gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+
+            /* delete queue */
+            ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+            ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+            ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+            ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+        }
+    }
+
+    for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+    {
+        sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* NON_NOTICE_ASSERT: semaphore error */
+        }
+
+        sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* NON_NOTICE_ASSERT: semaphore error */
+        }
+
+        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+    }
+
+    sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
+    /* semaphore error check */
+    if (osOK != sem_ercd)
+    {
+        /* NON_NOTICE_ASSERT: semaphore error */
+    }
+
+    sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+    /* semaphore error check */
+    if (osOK != sem_ercd)
+    {
+        /* NON_NOTICE_ASSERT: semaphore error */
+    }
+
+    gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+
+    core_util_critical_section_enter();
+
+    /* stop clock for SCUX */
+    cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
+    CPG.STBCR8 = (uint8_t)cpg_value;
+
+    core_util_critical_section_exit();
+
+    gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+}
+
+/******************************************************************************
+End of function SCUX_UnInitialize
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_OpenChannel
+* @brief         Open SCUX driver channel.
+*
+*                Description:<br>
+*
+* @param[in]     channel:open channel number.
+* @param[in]     flags:specifies the access mode whether the channel is
+*                      opened for a read or a write
+* @retval        ESUCCESS: Operation successful.
+*                ENOMEM_RBSP: Create queue is failed.
+*                EMFILE_RBSP: Allocate DMA ch for write is failed.
+******************************************************************************/
+
+int_t SCUX_OpenChannel(const int_t channel, const int_t flags)
+{
+    int_t    retval;
+
+    /* create write request queue */
+    retval = ahf_create(&gb_scux_info_drv.info_ch[channel].tx_que, AHF_LOCKINT);
+    if (ESUCCESS != retval)
+    {
+        retval = ENOMEM_RBSP;
+    }
+    else
+    {
+        /* create read request queue */
+        retval = ahf_create(&gb_scux_info_drv.info_ch[channel].rx_que, AHF_LOCKINT);
+        if (ESUCCESS != retval)
+        {
+            retval = ENOMEM_RBSP;
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        SCUX_InterruptInit(channel);
+
+        /* init channel information parameter */
+        gb_scux_info_drv.info_ch[channel].open_flags = flags;
+        gb_scux_info_drv.info_ch[channel].p_tx_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_tx_next_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_rx_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_rx_next_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info1 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info2 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info3 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_flush_callback = NULL;
+        gb_scux_info_drv.info_ch[channel].p_tx_dummy_data = &gb_scux_write_dummy_buf[0];
+        gb_scux_info_drv.info_ch[channel].p_rx_dummy_data = &gb_scux_read_dummy_buf[0];
+
+        /* get DMA channel for write */
+        gb_scux_info_drv.info_ch[channel].dma_tx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
+        if (EERROR == gb_scux_info_drv.info_ch[channel].dma_tx_ch)
+        {
+            retval = EMFILE_RBSP;
+        }
+        else
+        {
+            gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_STOP;
+        }
+
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_OpenChannel
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CloseChannel
+* @brief         Close SCUX driver channel.
+*
+*                Description:<br>
+*
+* @param[in]     channel: SCUX channel number.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t  SCUX_CloseChannel(const int_t channel)
+{
+    int_t    retval = ESUCCESS;
+    int_t    ercd;
+
+    /* check ch_stat whether going transfer */
+    if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
+        (SCUX_CH_INIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
+        (SCUX_CH_STOP != gb_scux_info_drv.info_ch[channel].ch_stat))
+    {
+        core_util_critical_section_enter();
+
+        /* This exclusive access control ends in the SCUX_IoctlClearStop */
+        ercd = SCUX_IoctlClearStop(channel);
+        if (ESUCCESS != ercd)
+        {
+            retval = EFAULT_RBSP;
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* delete queue */
+        ahf_cancelall(&gb_scux_info_drv.info_ch[channel].tx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[channel].tx_que);
+        ahf_cancelall(&gb_scux_info_drv.info_ch[channel].rx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[channel].rx_que);
+
+        SCUX_InterruptUninit(channel);
+
+        ercd = R_DMA_Free(gb_scux_info_drv.info_ch[channel].dma_tx_ch, NULL);
+        if (ESUCCESS != ercd)
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            /* reset error status */
+            gb_scux_info_drv.info_ch[channel].err_stat_backup = ESUCCESS;
+            /* set channel status to open */
+            gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_INIT;
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CloseChannel
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckParam
+* @brief         Check SCUX parameter.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES_RBSP : DVU setting isn't performed when DVU is used.
+*                EACCES_RBSP : MIX setting isn't performed when MIX is used.
+*                EACCES_RBSP : SSIF setting isn't performed when SSIF is used.
+*                EPERM_RBSP : Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT] = {SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH};
+    bool_t use_mix_flag = false;
+
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* check route parameter */
+        if (((SCUX_ROUTE_SRC_MEM_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MEM_MAX <= p_scux_info_ch->route_set)) &&
+            ((SCUX_ROUTE_SRC_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_SSIF_MAX <= p_scux_info_ch->route_set)) &&
+            ((SCUX_ROUTE_SRC_MIX_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MIX_SSIF_MAX <= p_scux_info_ch->route_set)))
+        {
+            retval = EPERM_RBSP;
+        }
+        else
+        {
+            /* check route whether include SCUX channel */
+            switch (p_scux_info_ch->channel)
+            {
+                case SCUX_CH_0:
+                    if ((SCUX_ROUTE_SRC0_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC0_SSIF0 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC0_SSIF3 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC0_SSIF012 != p_scux_info_ch->route_set)     &&
+#if defined(TARGET_RZA1H) /* mbed */
+                        (SCUX_ROUTE_SRC0_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC0_SSIF345 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF345 != p_scux_info_ch->route_set))
+#else /* mbed */
+                        (SCUX_ROUTE_SRC0_MIX_SSIF012 != p_scux_info_ch->route_set))
+#endif /* mbed */
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                break;
+
+                case SCUX_CH_1:
+                    if ((SCUX_ROUTE_SRC1_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC1_SSIF0 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC1_SSIF3 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC1_SSIF012 != p_scux_info_ch->route_set)     &&
+#if defined(TARGET_RZA1H) /* mbed */
+                        (SCUX_ROUTE_SRC1_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC1_SSIF345 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF345 != p_scux_info_ch->route_set))
+#else /* mbed */
+                        (SCUX_ROUTE_SRC1_MIX_SSIF012 != p_scux_info_ch->route_set))
+#endif /* mbed */
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                break;
+
+                case SCUX_CH_2:
+                    if ((SCUX_ROUTE_SRC2_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC2_SSIF1 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+#if defined(TARGET_RZA1H) /* mbed */
+                        (SCUX_ROUTE_SRC2_SSIF4 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF345 != p_scux_info_ch->route_set))
+#else /* mbed */
+                        (SCUX_ROUTE_SRC2_MIX_SSIF012 != p_scux_info_ch->route_set))
+#endif /* mbed */
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                break;
+
+                case SCUX_CH_3:
+                    if ((SCUX_ROUTE_SRC3_MEM != p_scux_info_ch->route_set)          &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF0 != p_scux_info_ch->route_set)    &&
+                        (SCUX_ROUTE_SRC3_SSIF2 != p_scux_info_ch->route_set)        &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF3 != p_scux_info_ch->route_set)    &&
+#if defined(TARGET_RZA1H) /* mbed */
+                        (SCUX_ROUTE_SRC3_SSIF5 != p_scux_info_ch->route_set)        &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF012 != p_scux_info_ch->route_set)  &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF345 != p_scux_info_ch->route_set))
+#else /* mbed */
+                        (SCUX_ROUTE_SRC3_MIX_SSIF012 != p_scux_info_ch->route_set))
+#endif /* mbed */
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                break;
+
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                    retval = EFAULT_RBSP;
+                break;
+
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* set using SSIF channel and MIX information */
+            switch (p_scux_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* do nothing, when mem to mem route is setting */
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_1;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_4;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_2;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_5;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+#endif /* mbed */
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                    retval = EPERM_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            if (false != p_scux_info_ch->src_cfg.src_enable)
+            {
+                retval = SCUX_CheckSrcParam(p_scux_info_ch, ssif_ch);
+            }
+            else
+            {
+                if (false != p_scux_info_ch->src_cfg.mode_sync)
+                {
+                    /* src disable is async mode only */
+                    retval = EPERM_RBSP;
+                }
+            }
+        }
+
+        if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
+        {
+            /* check parameter for SSIF direct route */
+            if ((ESUCCESS == retval) && (false != p_scux_info_ch->dvu_cfg.dvu_enable))
+            {
+                retval = SCUX_CheckDvuParam(p_scux_info_ch);
+            }
+
+            if (ESUCCESS == retval)
+            {
+                retval = SCUX_CheckSsifParam(p_scux_info_ch, ssif_ch, use_mix_flag);
+            }
+
+            if ((ESUCCESS == retval) && (false != use_mix_flag))
+            {
+                retval = SCUX_CheckMixParam(p_scux_info_ch);
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSrcParam
+* @brief         Check SRC parameter and set rate parameter to SCUX information.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @param[in]     use_mix_flag : Flag of Using MIX .
+* @retval        ESUCCESS : Parameter is no problems.
+*                EPERM_RBSP : Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT])
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_arrange_num;
+    uint32_t rate_sample_ratio;
+    uint32_t max_conv_rate;
+    uint32_t min_conv_rate = 0;
+    uint32_t freq_value = 0;
+    int_t audio_ch;
+    uint32_t max_rate;
+
+    if ((NULL == p_scux_info_ch) || (NULL == ssif_ch))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* check use ch */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_1 == p_scux_info_ch->channel))
+        {
+            if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) &&
+                (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch) &&
+                (SCUX_USE_CH_4 != p_scux_info_ch->src_cfg.use_ch) &&
+                (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch) &&
+                (SCUX_USE_CH_8 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+        else
+        {
+            /* on SCUX2, SCUX3, enable audio channel is only 1ch and 2ch */
+            if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* if using SSIF, 1ch audio channel is disabled */
+            if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]) && (SCUX_USE_CH_1 == p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* if  mutiple SSIF channel and enable TDM mode, only 2ch audio channel is enabled */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    if (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm)
+                    {
+                        if (SCUX_USE_CH_2 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+                }
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* multiple SSIF ch check (multiple SSIF is used SSIF2) */
+            if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) && (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check word length */
+            if ((SCUX_DATA_LEN_MIN >= p_scux_info_ch->src_cfg.word_len) || (SCUX_DATA_LEN_MAX <= p_scux_info_ch->src_cfg.word_len))
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check delay mode */
+            if ((SCUX_DELAY_MIN >= p_scux_info_ch->src_cfg.delay_mode) || (SCUX_DELAY_MAX <= p_scux_info_ch->src_cfg.delay_mode))
+            {
+                retval = EPERM_RBSP;
+            }
+            else
+            {
+                /* enable audio channel is less than 2ch when delay mode is enabled */
+                if ((SCUX_DELAY_NORMAL != p_scux_info_ch->src_cfg.delay_mode) && (SCUX_USE_CH_2 < p_scux_info_ch->src_cfg.use_ch))
+                {
+                    retval = EPERM_RBSP;
+                }
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check rate setting */
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                /* check input rate */
+                if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.input_rate_sync)  ||
+                    (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.input_rate_sync))
+                {
+                    /* enable rate is less than 66KHz on 6ch */
+                    if ((SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch) &&
+                        ((SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                         (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
+                    {
+                        retval = EPERM_RBSP;
+                    }
+
+                    /* enable rate is less than 49KHz on 8ch */
+                    if ((SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch) &&
+                        ((SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync)   ||
+                         (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                         (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                }
+                else
+                {
+                    retval = EPERM_RBSP;
+                }
+
+                if (ESUCCESS == retval) {
+                    /* check output rate */
+                    if ((SCUX_SYNC_RATE_8   == p_scux_info_ch->src_cfg.output_rate_sync)  ||
+                        (SCUX_SYNC_RATE_16   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_24   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_32   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_48   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_96   == p_scux_info_ch->src_cfg.output_rate_sync))
+                    {
+                        /* enable rate is less than 66KHz on 6ch, enable rate is less than 49KHz on 8ch  */
+                        if ((SCUX_USE_CH_6 <= p_scux_info_ch->src_cfg.use_ch) &&
+                            (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+                    else
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    p_scux_info_ch->input_rate = p_scux_info_ch->src_cfg.input_rate_sync;
+                    p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_rate_sync;
+                }
+            }
+            else
+            {
+                /* async mode */
+                /* check input rate */
+                /* get input source clock */
+                switch (p_scux_info_ch->src_cfg.input_clk_async)
+                {
+                    case SCUX_CLK_AUDIO_CLK :
+                        freq_value = SCUX_AUDIO_CLK;
+                    break;
+
+                    case SCUX_CLK_AUDIO_X1 :
+                        freq_value = SCUX_AUDIO_X1;
+                    break;
+
+                    case SCUX_CLK_MLB_CLK :
+                        freq_value = SCUX_MLB_CLK;
+                    break;
+
+                    case SCUX_CLK_USB_X1 :
+                        freq_value = SCUX_USB_X1;
+                    break;
+
+                    case SCUX_CLK_CLKP1_2 :
+                        freq_value = SCUX_CLKLP1_DIV2;
+                    break;
+
+                    case SCUX_CLK_MTU_TIOC3A :
+                        freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    break;
+
+                    case SCUX_CLK_MTU_TIOC4A :
+                        freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    break;
+
+                    case SCUX_CLK_SSIF0_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF1_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF2_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF3_WS :
+#if defined(TARGET_RZA1H) /* mbed */
+                        /* fall through */
+                    case SCUX_CLK_SSIF4_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF5_WS :
+#endif /* mbed */
+                        freq_value = p_scux_info_ch->src_cfg.input_ws;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    break;
+
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EPERM_RBSP;
+                    break;
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    /* check devide rate and devide source clock */
+                    /* check source clock isn't SSIF WS signal */
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+#if defined(TARGET_RZA1H) /* mbed */
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+#else /* mbed */
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async))
+#endif /* mbed */
+                    {
+                        if ((0U != (p_scux_info_ch->src_cfg.input_div_async % SCUX_EVEN_VALUE_DIV)) ||
+                            (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.input_div_async))
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                        else
+                        {
+                            if (0U == p_scux_info_ch->src_cfg.input_div_async)
+                            {
+                                /* 0 is a same size */
+                                p_scux_info_ch->input_rate = freq_value;
+                            }
+                            else{
+                                p_scux_info_ch->input_rate = freq_value / p_scux_info_ch->src_cfg.input_div_async;
+                            }
+                        }
+                    }
+                    else
+                    {
+                        p_scux_info_ch->input_rate = freq_value;
+                    }
+
+                    if (ESUCCESS == retval)
+                    {
+                        /* check input frequency is enable range */
+                        if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH6;
+                        }
+                        else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH8;
+                        }
+                        else
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH1_4;
+                        }
+
+                        if ((SCUX_MIN_FREQ > p_scux_info_ch->input_rate) ||
+                           (max_rate < p_scux_info_ch->input_rate))
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    /* if output route is SSIF direct route ,WS signal frequency is used */
+                    if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
+                    {
+                        if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.output_ws)  ||
+                            (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.output_ws))
+                        {
+                            p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_ws;
+                        }
+                        else
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+                    else
+                    {
+                        /* check output rate (mem to mem)*/
+                        /* get output source clock */
+                        switch (p_scux_info_ch->src_cfg.output_clk_async)
+                        {
+                            case SCUX_CLK_AUDIO_CLK :
+                                freq_value = SCUX_AUDIO_CLK;
+                            break;
+
+                            case SCUX_CLK_AUDIO_X1 :
+                                freq_value = SCUX_AUDIO_X1;
+                            break;
+
+                            case SCUX_CLK_MLB_CLK :
+                                freq_value = SCUX_MLB_CLK;
+                            break;
+
+                            case SCUX_CLK_USB_X1 :
+                                freq_value = SCUX_USB_X1;
+                            break;
+
+                            case SCUX_CLK_CLKP1_2 :
+                                freq_value = SCUX_CLKLP1_DIV2;
+                            break;
+
+                            case SCUX_CLK_MTU_TIOC3A :
+                                freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM_RBSP;
+                                }
+                            break;
+
+                            case SCUX_CLK_MTU_TIOC4A :
+                                freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM_RBSP;
+                                }
+                            break;
+
+                            case SCUX_CLK_SSIF0_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF1_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF2_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF3_WS :
+#if defined(TARGET_RZA1H) /* mbed */
+                                /* fall through */
+                            case SCUX_CLK_SSIF4_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF5_WS :
+#endif /* mbed */
+                                freq_value = p_scux_info_ch->src_cfg.output_ws;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM_RBSP;
+                                }
+                            break;
+
+                            default :
+                                /* error check is gone when route is other than SSIF */
+                                if (SCUX_ROUTE_SSIF != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                                {
+                                    retval = EPERM_RBSP;
+                                }
+                            break;
+                        }
+                    }
+
+                    if (ESUCCESS == retval)
+                    {
+                        /* check devide rate on only except for SSIF route, MISRA R1.1 mesure */
+                        if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+#if defined(TARGET_RZA1H) /* mbed */
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
+                            (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
+#else /* mbed */
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async))
+#endif /* mbed */
+                        {
+                            if ((0U != (p_scux_info_ch->src_cfg.output_div_async % SCUX_EVEN_VALUE_DIV)) ||
+                                (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.output_div_async))
+                            {
+                                retval = EPERM_RBSP;
+                            }
+                        }
+                    }
+
+                    if (ESUCCESS == retval)
+                    {
+                        /* check source clock isn't SSIF WS signal */
+                        if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+#if defined(TARGET_RZA1H) /* mbed */
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
+                            (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
+#else /* mbed */
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async))
+#endif /* mbed */
+                        {
+                            if (0U == p_scux_info_ch->src_cfg.output_div_async)
+                            {
+                                /* 0 is a same size */
+                                p_scux_info_ch->output_rate = freq_value;
+                            }
+                            else
+                            {
+                                p_scux_info_ch->output_rate = freq_value / p_scux_info_ch->src_cfg.output_div_async;
+                            }
+                        }
+                        else
+                        {
+                            p_scux_info_ch->output_rate = freq_value;
+                        }
+                        /* check input frequency is enable range */
+                        if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH6;
+                        }
+                        else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH8;
+                        }
+                        else
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH1_4;
+                        }
+
+                        if ((SCUX_MIN_FREQ > p_scux_info_ch->output_rate) ||
+                            (max_rate < p_scux_info_ch->output_rate))
+                        {
+                            retval = EPERM_RBSP;
+                        }
+
+                    }
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check convert rate range */
+                max_conv_rate = SCUX_MAX_CONV_RATE;
+                switch (p_scux_info_ch->src_cfg.delay_mode)
+                {
+                    case SCUX_DELAY_NORMAL :
+                        switch (p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            case SCUX_USE_CH_1 :
+                                /* fall through */
+                            case SCUX_USE_CH_2 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH1_2;
+                            break;
+
+                            case SCUX_USE_CH_4 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH4;
+                            break;
+
+                            case SCUX_USE_CH_6 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH6;
+                            break;
+
+                            case SCUX_USE_CH_8 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH8;
+                            break;
+
+                            default :
+                                /* NOTREACHED on At the time of a normal performance */
+                                retval = EPERM_RBSP;
+                            break;
+                        }
+                    break;
+
+                    case SCUX_DELAY_LOW_DELAY1 :
+                        min_conv_rate = SCUX_MIN_CONV_RATE_DELAY1;
+                    break;
+
+                    case SCUX_DELAY_LOW_DELAY2 :
+                        min_conv_rate = SCUX_MIN_CONV_RATE_DELAY2;
+                    break;
+
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EPERM_RBSP;
+                    break;
+                }
+
+                rate_sample_ratio = ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate);
+                if ((min_conv_rate > rate_sample_ratio) || (max_conv_rate < rate_sample_ratio))
+                {
+                    retval = EPERM_RBSP;
+                }
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check wait time */
+            if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->src_cfg.wait_sample)
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check min rate ratio */
+            if ((SCUX_MIN_RATE_MIN_PAERCENTAGE > (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) ||
+                (SCUX_MIN_RATE_MAX_PAERCENTAGE < (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage))
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check input data position */
+            for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+            {
+                if ((SCUX_AUDIO_CH_MIN >= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]) ||
+                    (SCUX_AUDIO_CH_MAX <= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]))
+                {
+                    retval = EPERM_RBSP;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSrcParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckDvuParam
+* @brief         Check DVU parameter.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES_RBSP : DVU setting isn't performed when DVU is used.
+*                EPERM_RBSP : Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    int_t audio_ch;
+    uint32_t enable_ch_flag = false;
+
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (false == p_scux_info_ch->dvu_setup)
+        {
+            retval = EACCES_RBSP;
+        }
+        else
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
+            {
+                /* check digital volume value */
+                if (false !=  p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
+                {
+                    /* check digital volume value */
+                    for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+                    {
+                        if (SCUX_MAX_DIGITAL_VOLUME < p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+                }
+
+                /* check ramp volume value */
+                for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+                {
+                    enable_ch_flag |= (uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch];
+                }
+
+                if ((ESUCCESS == retval) && (false != (bool_t)enable_ch_flag))
+                {
+                    /* check ramp up period */
+                    if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
+                        (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
+                    {
+                        retval = EPERM_RBSP;
+                    }
+
+                    if (ESUCCESS == retval)
+                    {
+                        /* check ramp down period */
+                        if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
+                            (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+
+                    if (ESUCCESS == retval)
+                    {
+                        /* check ramp volume */
+                        if (SCUX_MAX_RAMP_VOLUME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+
+                    if (ESUCCESS != retval)
+                    {
+                        /* check wait time */
+                        if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
+                        {
+                            retval = EPERM_RBSP;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckDvuParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSsifParam
+* @brief         Check SSIF parameter.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @param[in]     use_mix_flag : Flag of Using MIX .
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES_RBSP : SSIF setting isn't performed when SSIF is used.
+*                EACCES_RBSP : SSIF channel is already used.
+*                EACCES_RBSP : When use MIX, it is a setup which does not agree in a route setup.
+*                EPERM_RBSP : Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag)
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_arrange_num;
+    uint32_t mix_ssif_ch_bit = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch) || (NULL == ssif_ch))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (false == use_mix_flag)
+        {
+            /* used SSIF channel check no used MIX route */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    /* check SSIF is already setup */
+                    if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
+                    {
+                        retval = EACCES_RBSP;
+                    }
+                    else
+                    {
+                        /* used SSIF channel is checked by other SCUX channel */
+                        if (0 != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel)
+                        {
+                            retval = EACCES_RBSP;
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* used SSIF channel check on MIX route */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    /* clear SCUX_SSIF_use_mix_flag and get SSIF channel number */
+                    mix_ssif_ch_bit |= (1U << ssif_ch[ssif_arrange_num]);
+                    /* check SSIF is already setup */
+                    if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
+                    {
+                        retval = EACCES_RBSP;
+                    }
+                }
+            }
+            if (ESUCCESS == retval)
+            {
+                /* used SSIF channel check, on MIX route check */
+                if (0U != p_info_drv->shared_info.mix_ssif_ch)
+                {
+                    /* In the MIX setup for the and after 2times, it is checked that same SSIF ch on 1st setting is set up */
+                    if (p_info_drv->shared_info.mix_ssif_ch != mix_ssif_ch_bit)
+                    {
+                        retval = EACCES_RBSP;
+                    }
+                }
+                else
+                {
+                    /*It checks that SSIF channel is not used once on first MIX setup */
+                    if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
+                    {
+                        if ((0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel) ||
+                            (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]].scux_channel) ||
+                            (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]].scux_channel))
+                        {
+                            retval = EACCES_RBSP;
+                        }
+                    }
+                    else
+                    {
+                        if (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel)
+                        {
+                            retval = EACCES_RBSP;
+                        }
+                    }
+                }
+            }
+        }
+
+        /* each SSIF parameter check */
+        for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+        {
+            /* used SSIF channel check, on SSIF direct route check */
+            if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+            {
+
+                /* check system word */
+                if ((gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word <= SCUX_SSIF_SYSTEM_LEN_MIN) ||
+                    (gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word >= SCUX_SSIF_SYSTEM_LEN_MAX))
+                {
+                    retval = EPERM_RBSP;
+                }
+                else
+                {
+                    /* check system word >= data word */
+                    /* The combination applicable to error only of data word of 24bit and system word of 16bit */
+                    if ((SCUX_DATA_LEN_16 != p_scux_info_ch->src_cfg.word_len) &&
+                        (SCUX_SSIF_SYSTEM_LEN_16 == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word))
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    /* if multiple channel is used, TDM is disable */
+                    if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) &&
+                        (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm))
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                }
+                if (ESUCCESS == retval)
+                {
+                    retval = SCUX_CheckSsifClockDiv(p_scux_info_ch, ssif_ch[ssif_arrange_num]);
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel
+                    = (int_t)((uint32_t)gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel | (1U << p_scux_info_ch->channel));
+                }
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* set SSIF information structure pointer */
+            if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
+            {
+                p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
+                p_scux_info_ch->p_ssif_info2 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]];
+                p_scux_info_ch->p_ssif_info3 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]];
+            }
+            else
+            {
+                p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
+                p_scux_info_ch->p_ssif_info2 = NULL;
+                p_scux_info_ch->p_ssif_info3 = NULL;
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSsifParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckMixParam
+* @brief         Check MIX parameter.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES_RBSP : MIX setting isn't performed when MIX is used.
+*                EPERM_RBSP : Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    int_t scux_ch;
+    int_t audio_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (false == p_info_drv->shared_info.mix_setup)
+        {
+            retval = EACCES_RBSP;
+        }
+        else
+        {
+            if (false != p_info_drv->shared_info.mixmode_ramp)
+            {
+                /* check ramp up time */
+                if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.up_period) ||
+                    (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.up_period))
+                {
+                    retval = EPERM_RBSP;
+                }
+
+                /* check ramp down time */
+                if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.down_period) ||
+                    (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.down_period))
+                {
+                    retval = EPERM_RBSP;
+                }
+            }
+
+            /* check MIX volume */
+            for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (SCUX_CH_NUM > scux_ch)); scux_ch++)
+            {
+                /* register set on the channel itself which sets up or channel which has already MIX operated */
+                if ((scux_ch == p_scux_info_ch->channel) ||
+                    (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
+                {
+                    if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                }
+            }
+
+            /* check output data position */
+            for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+            {
+                /* check min rate ratio */
+                if ((SCUX_AUDIO_CH_MIN >= p_info_drv->shared_info.select_out_data_ch[audio_ch]) ||
+                    (SCUX_AUDIO_CH_MAX <= p_info_drv->shared_info.select_out_data_ch[audio_ch]))
+                {
+                    retval = EPERM_RBSP;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckMixParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_StrNLen
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*                if string is longer than maxlen, this function return maxlen
+* @param[in]     p_str      :pointer of string
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        'number of characters in the string' or 'maxlen'
+******************************************************************************/
+size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen)
+{
+    size_t ret_len;
+
+    if (NULL == p_str)
+    {
+        /* character string does not exist */
+        ret_len = 0;
+    }
+    else
+    {
+        /* ->IPA P1.3.1 Even if a sign is positive, even a negative is no problem. */
+        for (ret_len = 0; (maxlen != 0U) && (*p_str != '\0'); ret_len++)
+        /* <-IPA P1.3.1 */
+        {
+            maxlen--;
+            p_str++;
+        }
+    }
+
+    return ret_len;
+}
+
+/******************************************************************************
+End of function SCUX_StrNLen
+******************************************************************************/
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_CmnUnInitialize
+* @brief         uninitialize driver infomation.
+*
+*                Description:<br>
+*                
+* @param[in]     None.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+static int_t SCUX_CmnUnInitialize(void)
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    ssif_ch_count;
+    uint32_t cpg_value;
+    volatile uint8_t dummy_buf;
+
+    /* software reset */
+    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+
+    for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+    {
+        if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+        {
+            sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                 retval = EFAULT_RBSP;
+            }
+
+            gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+        }
+    }
+
+    if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
+    {
+        sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* set error return value */
+            retval = EFAULT_RBSP;
+        }
+
+        gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+    }
+
+    core_util_critical_section_enter();
+
+    /* stop clock for SCUX */
+    cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
+    CPG.STBCR8 = (uint8_t)cpg_value;
+    dummy_buf = CPG.STBCR8;
+#if(1) /* mbed */
+    (void)dummy_buf;
+#endif
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CmnUnInitialize
+******************************************************************************/
+#endif /* end mbed */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,797 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux.h
+* $Rev: $
+* $Date::                           $
+* @brief         Sample driver internal header
+******************************************************************************/
+
+#ifndef SCUX_H
+#define SCUX_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "scux_if.h"
+#include "scux_int.h"
+#include "aioif.h"
+#include "iodefine.h"
+#include "cmsis.h"
+#include "dma_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* SCUX Register Set Value */
+/* Init Value */
+/* IPC */
+#define IPCIR_IPC0_INIT_VALUE      (0x00000001U)
+#define IPSLR_IPC0_INIT_VALUE      (0x00000000U)
+/* OPC */
+#define OPCIR_OPC0_INIT_VALUE      (0x00000001U)
+#define OPSLR_OPC0_INIT_VALUE      (0x00000000U)
+/* FFD */
+#define FFDIR_FFD0_INIT_VALUE      (0x00000001U)
+#define FDAIR_FFD0_INIT_VALUE      (0x00000000U)
+#define DRQSR_FFD0_INIT_VALUE      (0x00000000U)
+#define FFDPR_FFD0_INIT_VALUE      (0x00000000U)
+#define FFDBR_FFD0_INIT_VALUE      (0x00000000U)
+#define DEVMR_FFD0_INIT_VALUE      (0x00000000U)
+#define DEVCR_FFD0_INIT_VALUE      (0x00000000U)
+/* FFU */
+#define FFUIR_FFU0_INIT_VALUE      (0x00000001U)
+#define FUAIR_FFU0_INIT_VALUE      (0x00000000U)
+#define URQSR_FFU0_INIT_VALUE      (0x00000000U)
+#define FFUPR_FFU0_INIT_VALUE      (0x00000000U)
+#define UEVMR_FFU0_INIT_VALUE      (0x00000000U)
+#define UEVCR_FFU0_INIT_VALUE      (0x00000000U)
+/* SRC */
+#define SRCIR_2SRC0_INIT_VALUE     (0x00000001U)
+#define SADIR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCBR_2SRC0_INIT_VALUE     (0x00000000U)
+#define IFSCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define IFSVR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define MNFSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define BFSSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define WATSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SEVMR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SEVCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCIRR_2SRC0_INIT_VALUE    (0x00000001U)
+/* DVU */
+#define DVUIR_DVU0_INIT_VALUE      (0x00000001U)
+#define VADIR_DVU0_INIT_VALUE      (0x00000000U)
+#define DVUBR_DVU0_INIT_VALUE      (0x00000000U)
+#define DVUCR_DVU0_INIT_VALUE      (0x00000000U)
+#define ZCMCR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRCTR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRPDR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRDBR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRWTR_DVU0_INIT_VALUE      (0x00000000U)
+#define VOL_N_R_DVU0_INIT_VALUE    (0x00000000U)
+#define DVUER_DVU0_INIT_VALUE      (0x00000000U)
+#define VEVMR_DVU0_INIT_VALUE      (0x00000000U)
+#define VEVCR_DVU0_INIT_VALUE      (0x00000000U)
+/* MIX */
+#define MIXIR_MIX0_0_INIT_VALUE    (0x00000001U)
+#define MADIR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MIXBR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MIXMR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MVPDR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MDB_N_R_MIX0_0_INIT_VALUE  (0x00000000U)
+#define MDBER_MIX0_0_INIT_VALUE    (0x00000000U)
+/* CIM */
+#define SWRSR_CIM_INIT_VALUE       (0x00000001U)
+#define DMACR_CIM_INIT_VALUE       (0x00000000U)
+#define SSIRSEL_CIM_INIT_VALUE     (0x00000000U)
+#define FDTSEL_CIM_INIT_VALUE      (0x00000000U)
+#define FUTSEL_CIM_INIT_VALUE      (0x00000000U)
+#define SSIPMD_CIM_INIT_VALUE      (0x00000000U)
+#define SSICTRL_CIM_INIT_VALUE     (0x00000000U)
+#define SRCRSEL_CIM_INIT_VALUE     (0x76543210U)
+#define MIXRSEL_CIM_INIT_VALUE     (0x76543210U)
+
+/* SCUX bit value & mask & fixed setting */
+
+/* IPC */
+#define IPCIR_IPC0_INIT_SET           (1U << 0)
+
+#define IPSLR_IPC_PASS_SEL_MASK       (7U << 0)
+#define IPSLR_IPC_PASS_SEL_SET_ASYNC  (3U << 0)
+#define IPSLR_IPC_PASS_SEL_SET_SYNC   (4U << 0)
+
+/* OPC */
+#define OPCIR_OPC0_INIT_SET           (1U << 0)
+
+#define OPSLR_OPC_PASS_SEL_MASK       (7U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_DIRECT (1U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_ASYNC  (3U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_SYNC   (4U << 0)
+
+/* FFD */
+#define FFDIR_FFD0_INIT_SET           (1U << 0)
+
+#define FDAIR_FFD0_CHNUM_MASK         (0x0FU << 0)
+
+#define DRQSR_FFD0_SIZE_MASK          (0x0FU << 0)
+
+#define FFDPR_FFD0_PASS_SET_ASYNC     (1U << 0)
+#define FFDPR_FFD0_PASS_SET_SYNC      (2U << 0)
+
+#define FFDBR_FFD0_BOOT_SET           (1U << 0)
+
+#define DEVMR_FFD0_DEVMUF_SET         (1U << 31)
+#define DEVMR_FFD0_DEVMOF_SET         (1U << 30)
+#define DEVMR_FFD0_DEVMOL_SET         (1U << 29)
+#define DEVMR_FFD0_DEVMIUF_SET        (1U << 28)
+#define DEVMR_FFD0_DEVMRQ_SET         (1U << 15)
+
+#define DEVCR_FFD0_DEVCUF_MASK        (1U << 31)
+#define DEVCR_FFD0_DEVCUF_SET         (1U << 31)
+#define DEVCR_FFD0_DEVCOF_MASK        (1U << 30)
+#define DEVCR_FFD0_DEVCOF_SET         (1U << 30)
+#define DEVCR_FFD0_DEVCOL_MASK        (1U << 29)
+#define DEVCR_FFD0_DEVCOL_SET         (1U << 29)
+#define DEVCR_FFD0_DEVCIUF_MASK       (1U << 28)
+#define DEVCR_FFD0_DEVCIUF_SET        (1U << 28)
+#define DEVCR_FFD0_DEVCRQ_MASK        (1U << 15)
+#define DEVCR_FFD0_DEVCRQ_SET         (1U << 15)
+
+/* FFU */
+#define FFUIR_FFU0_INIT_SET           (1U << 0)
+
+#define FUAIR_FFU0_CHNUM_MASK         (0x0FU << 0)
+
+#define URQSR_FFU0_SIZE_MASK          (0x0FU << 0)
+
+#define FFUPR_FFU0_PASS_SET_ASYNC     (1U << 0)
+#define FFUPR_FFU0_PASS_SET_SYNC      (2U << 0)
+
+#define UEVMR_FFU0_UEVMUF_SET         (1U << 31)
+#define UEVMR_FFU0_UEVMOF_SET         (1U << 30)
+#define UEVMR_FFU0_UEVMOL_SET         (1U << 29)
+#define UEVMR_FFU0_UEVMRQ_SET         (1U << 15)
+
+#define UEVCR_FFU0_UEVCUF_MASK        (1U << 31)
+#define UEVCR_FFU0_UEVCUF_SET         (1U << 31)
+#define UEVCR_FFU0_UEVCOF_MASK        (1U << 30)
+#define UEVCR_FFU0_UEVCOF_SET         (1U << 30)
+#define UEVCR_FFU0_UEVCOL_MASK        (1U << 29)
+#define UEVCR_FFU0_UEVCOL_SET         (1U << 29)
+#define UEVCR_FFU0_UEVCRQ_MASK        (1U << 15)
+#define UEVCR_FFU0_UEVCRQ_SET         (1U << 15)
+
+/* SRC */
+#define SRCIR_2SRC0_INIT_SET          (1U << 0)
+
+#define SADIR_2SRC0_CHNUM_MASK        (0x0FU << 0)
+#define SADIR_2SRC0_OTBL_MASK         (0x1FU << 16)
+#define SADIR_2SRC0_OTBL_SET_24BIT    (0x0U << 16)
+#define SADIR_2SRC0_OTBL_SET_16BIT    (0x8U << 16)
+
+#define SRCBR_2SRC0_BYPASS_SET        (0x1U << 0)
+
+#define IFSCR_2SRC0_INTIFSEN_SET      (0x1U << 0)
+
+#define IFSVR_2SRC0_INTIFS_MASK       (0x0FFFFFFFU << 0)
+
+#define SRCCR_2SRC0_BASE_VALUE        (0x00010110U)
+#define SRCCR_2SRC0_WATMD_SET         (1U << 20)
+#define SRCCR_2SRC0_BUFMD_SET         (1U << 12)
+#define SRCCR_2SRC0_SRCMD_SET         (1U << 0)
+
+#define MNFSR_2SRC0_MINFS_MASK        (0x0FFFFFFFU << 0)
+
+#define BFSSR_2SRC0_BUFDATA_MASK      (0x3FFU << 16)
+#define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 (0x80U << 16)
+#define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 (0x40U << 16)
+#define BFSSR_2SRC0_BUFIN_MASK        (0x0FU << 0)
+#define BFSSR_2SRC0_BUFIN_SET_DELAY_MODE (0x05U << 0)
+
+#define WATSR_2SRC0_WTIME_MASK        (0xFFFFFFU << 0)
+
+#define SEVMR_2SRC0_EVMUF_SET         (1U << 31)
+#define SEVMR_2SRC0_EVMOF_SET         (1U << 30)
+
+#define SEVCR_2SRC0_EVCUF_MASK        (1U << 31)
+#define SEVCR_2SRC0_EVCUF_SET         (1U << 31)
+#define SEVCR_2SRC0_EVCOF_MASK        (1U << 30)
+#define SEVCR_2SRC0_EVCOF_SET         (1U << 30)
+
+#define SRCIRR_2SRC0_INIT_SET         (1U << 0)
+
+#define DVUIR_DVU0_INIT_SET           (1U << 0)
+
+#define VADIR_DVU0_OTBL_MASK          (0x1FU << 16)
+#define VADIR_DVU0_OTBL_SET_24BIT     (0x0U << 16)
+#define VADIR_DVU0_OTBL_SET_16BIT     (0x8U << 16)
+#define VADIR_DVU0_CHNUM_MASK         (0x0FU << 0)
+
+#define DVUBR_DVU0_BYPASS_SET         (0x1U << 0)
+
+#define DVUCR_DVU0_VVMD_SET           (1U << 8)
+#define DVUCR_DVU0_VRMD_SET           (1U << 4)
+#define DVUCR_DVU0_ZCMD_SET           (1U << 0)
+
+#define ZCMCR_DVU0_ZCEN_SET           (1U << 0)
+
+#define VRCTR_DVU0_VREN_SET           (1U << 0)
+
+#define VRPDR_DVU0_VRPDUP_SHIFT       (8U)
+#define VRPDR_DVU0_VRPDUP_MASK        (0x1F << VRPDR_DVU0_VRPDUP_SHIFT)
+#define VRPDR_DVU0_VRPDDW_SHIFT       (0U)
+#define VRPDR_DVU0_VRPDDW_MASK        (0x1F << VRPDR_DVU0_VRPDDW_SHIFT)
+
+#define VRDBR_DVU0_VRDB_MASK          (0x3FFU << 0)
+
+#define VRWTR_DVU0_VRWT_MASK          (0xFFFFFFU << 0)
+
+#define VOL_N_R_DVU_VOLVAL_MASK       (0xFFFFFFU << 0)
+
+#define DVUER_DVU0_DVUEN_SET          (1U << 0)
+
+#define DVUSR_DVU0_ZSTS_N_SHIFT       (16U)
+#define DVUSR_DVU0_ZSTS_N_MASK        (1U << DVUSR_DVU0_ZSTS_N_SHIFT)
+#define DVUSR_DVU0_ZSTS_MASK          (0xFFU << DVUSR_DVU0_ZSTS_N_SHIFT)
+#define DVUSR_DVU0_VRSTS_MASK         (7U << 0)
+#define DVUSR_DVU0_VRSTS_VOL_FIX      (4U << 0)
+
+#define VEVMR_DVU0_VEVMZCM_SET        (1U << 24)
+
+#define VEVCR_DVU0_VEVCZCM_SET        (1U << 24)
+
+/* MIX */
+#define MIXIR_MIX0_INIT_SET           (1U << 0)
+
+#define MADIR_MIX0_CHNUM_MASK         (0x0FU << 0)
+
+#define MIXMR_MIX0_MIXMODE_SET        (1U << 0)
+
+#define MVPDR_MIX0_MXPDUP_SHIFT       (8U)
+#define MVPDR_MIX0_MXPDUP_MASK        (0x0FU << MVPDR_MIX0_MXPDUP_SHIFT)
+#define MVPDR_MIX0_MXPDDW_SHIFT       (0U)
+#define MVPDR_MIX0_MXPDDW_MASK        (0x0FU << MVPDR_MIX0_MXPDDW_SHIFT)
+
+#define MDB_N_R_MIX0_MIXDB_N_MASK     (0x3FFU <<0)
+
+#define MDBER_MIX0_MIXDBEN_SET        (1U << 0)
+
+#define MIXSR_MIX0_MIXSTS_MASK        (3U << 0)
+
+/* CIM */
+#define SWRSR_CIM_SWRST_SET           (1U << 0)
+
+#define DMACR_CIM_DMAMDFFU_N_SET      (1U << 4)
+#define DMACR_CIM_DMAMDFFD_N_SET      (1U << 0)
+
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIRSEL_CIM_SOSEL5_MASK       (3U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC3_SET   (0U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC1_SET   (1U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC0_SET   (2U << 20)
+#define SSIRSEL_CIM_SOSEL5_MIX_SET    (3U << 20)
+#define SSIRSEL_CIM_SOSEL4_MASK       (3U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC2_SET   (0U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC1_SET   (1U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC0_SET   (2U << 16)
+#define SSIRSEL_CIM_SOSEL4_MIX_SET    (3U << 16)
+#endif /* mbed */
+#define SSIRSEL_CIM_SOSEL3_MASK       (3U << 12)
+#define SSIRSEL_CIM_SOSEL3_SRC1_SET   (0U << 12)
+#define SSIRSEL_CIM_SOSEL3_SRC0_SET   (1U << 12)
+#define SSIRSEL_CIM_SOSEL3_MIX_SET    (2U << 12)
+#define SSIRSEL_CIM_SOSEL2_MASK       (3U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC3_SET   (0U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC0_SET   (1U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC1_SET   (2U << 8)
+#define SSIRSEL_CIM_SOSEL2_MIX_SET    (3U << 8)
+#define SSIRSEL_CIM_SOSEL1_MASK       (3U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC2_SET   (0U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC0_SET   (1U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC1_SET   (2U << 4)
+#define SSIRSEL_CIM_SOSEL1_MIX_SET    (3U << 4)
+#define SSIRSEL_CIM_SOSEL0_MASK       (3U << 0)
+#define SSIRSEL_CIM_SOSEL0_SRC0_SET   (0U << 0)
+#define SSIRSEL_CIM_SOSEL0_SRC1_SET   (1U << 0)
+#define SSIRSEL_CIM_SOSEL0_MIX_SET    (2U << 0)
+
+#define FDTSEL_CIM_SCKDIV_SHIFT       (16U)
+#define FDTSEL_CIM_SCKDIV_MASK        (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT)
+#define FDTSEL_CIM_DIVEN_MASK         (1U << 8)
+#define FDTSEL_CIM_DIVEN_SET          (1U << 8)
+#define FDTSEL_CIM_MTUSEL_MASK        (1U << 4)
+#define FDTSEL_CIM_MTUSEL_SET_TIOC3A  (0U << 4)
+#define FDTSEL_CIM_MTUSEL_SET_TIOC4A  (1U << 4)
+#define FDTSEL_CIM_SCKSEL_MASK        (0x0FU << 0)
+#define FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U)
+#define FDTSEL_CIM_SCKSEL_AUDIO_X1_SET  (1U)
+#define FDTSEL_CIM_SCKSEL_MLB_CLK_SET   (2U)
+#define FDTSEL_CIM_SCKSEL_USB_X1_SET    (3U)
+#define FDTSEL_CIM_SCKSEL_CLKP1_2_SET   (4U)
+#define FDTSEL_CIM_SCKSEL_MTUSEL2_SET   (5U)
+#define FDTSEL_CIM_SCKSEL_SSIF0_WS_SET  (8U)
+#define FDTSEL_CIM_SCKSEL_SSIF1_WS_SET  (9U)
+#define FDTSEL_CIM_SCKSEL_SSIF2_WS_SET  (10U)
+#define FDTSEL_CIM_SCKSEL_SSIF3_WS_SET  (11U)
+#if defined(TARGET_RZA1H) /* mbed */
+#define FDTSEL_CIM_SCKSEL_SSIF4_WS_SET  (12U)
+#define FDTSEL_CIM_SCKSEL_SSIF5_WS_SET  (13U)
+#endif /* mbed */
+
+#define FUTSEL_CIM_SCKDIV_SHIFT         (16U)
+#define FUTSEL_CIM_SCKDIV_MASK          (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT)
+#define FUTSEL_CIM_DIVEN_MASK           (1U << 8)
+#define FUTSEL_CIM_DIVEN_SET            (1U << 8)
+#define FUTSEL_CIM_MTUSEL_MASK          (1U << 4)
+#define FUTSEL_CIM_MTUSEL_SET_TIOC3A    (0U << 4)
+#define FUTSEL_CIM_MTUSEL_SET_TIOC4A    (1U << 4)
+#define FUTSEL_CIM_SCKSEL_MASK          (0x0FU << 0)
+#define FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U)
+#define FUTSEL_CIM_SCKSEL_AUDIO_X1_SET  (1U)
+#define FUTSEL_CIM_SCKSEL_MLB_CLK_SET   (2U)
+#define FUTSEL_CIM_SCKSEL_USB_X1_SET    (3U)
+#define FUTSEL_CIM_SCKSEL_CLKP1_2_SET   (4U)
+#define FUTSEL_CIM_SCKSEL_MTUSEL2_SET   (5U)
+#define FUTSEL_CIM_SCKSEL_SSIF0_WS_SET  (8U)
+#define FUTSEL_CIM_SCKSEL_SSIF1_WS_SET  (9U)
+#define FUTSEL_CIM_SCKSEL_SSIF2_WS_SET  (10U)
+#define FUTSEL_CIM_SCKSEL_SSIF3_WS_SET  (11U)
+#if defined(TARGET_RZA1H) /* mbed */
+#define FUTSEL_CIM_SCKSEL_SSIF4_WS_SET  (12U)
+#define FUTSEL_CIM_SCKSEL_SSIF5_WS_SET  (13U)
+#endif /* mbed */
+
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIPMD_CIM_SSI5CKS_MASK     (1U << 21)
+#define SSIPMD_CIM_SSI5CKS_SET      (1U << 21)
+#define SSIPMD_CIM_SSI4CKS_MASK     (1U << 20)
+#define SSIPMD_CIM_SSI4CKS_SET      (1U << 20)
+#endif /* mbed */
+#define SSIPMD_CIM_SSI3CKS_MASK     (1U << 19)
+#define SSIPMD_CIM_SSI3CKS_SET      (1U << 19)
+#define SSIPMD_CIM_SSI2CKS_MASK     (1U << 18)
+#define SSIPMD_CIM_SSI2CKS_SET      (1U << 18)
+#define SSIPMD_CIM_SSI1CKS_MASK     (1U << 17)
+#define SSIPMD_CIM_SSI1CKS_SET      (1U << 17)
+#define SSIPMD_CIM_SSI0CKS_MASK     (1U << 16)
+#define SSIPMD_CIM_SSI0CKS_SET      (1U << 16)
+#define SSIPMD_CIM_SSI3PMD_SHIFT    (14U)
+#define SSIPMD_CIM_SSI3PMD_MASK     (3U << SSIPMD_CIM_SSI3PMD_SHIFT)
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIPMD_CIM_SSI345EN_MASK    (1U << 12)
+#define SSIPMD_CIM_SSI345EN_SET     (1U << 12)
+#define SSIPMD_CIM_SSI4PMD_SHIFT    (10U)
+#define SSIPMD_CIM_SSI4PMD_MASK     (3U << SSIPMD_CIM_SSI4PMD_SHIFT)
+#define SSIPMD_CIM_SSI5PMD_SHIFT    (8U)
+#define SSIPMD_CIM_SSI5PMD_MASK     (3U << SSIPMD_CIM_SSI5PMD_SHIFT)
+#endif /* mbed */
+#define SSIPMD_CIM_SSI012EN_MASK    (1U << 4)
+#define SSIPMD_CIM_SSI012EN_SET     (1U << 4)
+#define SSIPMD_CIM_SSI2PMD_SHIFT    (2U)
+#define SSIPMD_CIM_SSI2PMD_MASK     (3U << SSIPMD_CIM_SSI2PMD_SHIFT)
+#define SSIPMD_CIM_SSI1PMD_SHIFT    (0U)
+#define SSIPMD_CIM_SSI1PMD_MASK     (3U << SSIPMD_CIM_SSI1PMD_SHIFT)
+
+#define SSICTRL_CIM_SSI3TX_SET      (1U << 30)
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSICTRL_CIM_SSI4TX_SET      (1U << 29)
+#define SSICTRL_CIM_SSI5TX_SET      (1U << 28)
+#define SSICTRL_CIM_SSI345TEN_SET   (1U << 17)
+#endif /* mbed */
+#define SSICTRL_CIM_SSI0TX_SET      (1U << 14)
+#define SSICTRL_CIM_SSI1TX_SET      (1U << 13)
+#define SSICTRL_CIM_SSI2TX_SET      (1U << 12)
+#define SSICTRL_CIM_SSI012TEN_SET   (1U << 1)
+
+#define SRCRSEL_CIM_PLACE_N_MASK    (7U)
+#define SRCRSEL_CIM_PLACE_N_SHIFT   (4U)
+
+#define MIXRSEL_CIM_PLACE_N_MASK    (7U)
+#define MIXRSEL_CIM_PLACE_N_SHIFT   (4U)
+
+
+/* SSIF Register Set Value */
+/* Init Value */
+#define SCUX_SSICR_INIT_VALUE       (0x00000000U)
+#define SCUX_SSIFCR_INIT_VALUE      (0x00000000U)
+#define SCUX_SSIFTDR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSITDMR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSIFCCR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSIFCMR_INIT_VALUE     (0x00000000U)
+
+/* SSIF bit value & mask & fixed setting */
+#define SCUX_SSICR_CKS_SET              (1U << 30)
+#define SCUX_SSICR_TUIEN_SET            (1U << 29)
+#define SCUX_SSICR_TOIEN_SET            (1U << 28)
+#define SCUX_SSICR_RUIEN_SET            (1U << 27)
+#define SCUX_SSICR_ROIEN_SET            (1U << 26)
+#define SCUX_SSICR_CHNL_SET_1CH         (0U << 22)
+#define SCUX_SSICR_CHNL_SET_2CH         (1U << 22)
+#define SCUX_SSICR_CHNL_SET_3CH         (2U << 22)
+#define SCUX_SSICR_CHNL_SET_4CH         (3U << 22)
+#define SCUX_SSICR_DWL_16BIT_SET        (1U << 19)
+#define SCUX_SSICR_DWL_24BIT_SET        (5U << 19)
+#define SCUX_SSICR_SWL_SHIFT            (16U)
+#define SCUX_SSICR_SCKD_SET             (1U << 15)
+#define SCUX_SSICR_SWSD_SET             (1U << 14)
+#define SCUX_SSICR_SCKP_SET             (1U << 13)
+#define SCUX_SSICR_SWSP_SET             (1U << 12)
+#define SCUX_SSICR_SPDP_SET             (1U << 11)
+#define SCUX_SSICR_SDTA_SET             (1U << 10)
+#define SCUX_SSICR_DEL_SET              (1U << 8)
+#define SCUX_SSICR_CKDV_SHIFT           (4U)
+#define SCUX_SSICR_TEN_SET              (1U << 1)
+
+#define SCUX_SSITDMR_CONT_SET           (1U << 8)
+#define SCUX_SSITDMR_TDM_SET            (1U << 0)
+
+/* SCUX fixed value */
+#define SCUX_RATE_CONVERT_CALC_VALUE     (0x400000U)
+#define SCUX_CALC_MINFS_VALUE            (100U)
+#define SCUX_MAX_DIV_CLK                 (2046U)
+#define SCUX_MIN_RATE_MIN_PAERCENTAGE    (90U)
+#define SCUX_MIN_RATE_MAX_PAERCENTAGE    (98U)
+#define SCUX_MIN_RATE_DENOMINATOR        (100U)
+#define SCUX_MAX_WAIT_TIME               (0xFFFFFFU)
+#define SCUX_MAX_DIGITAL_VOLUME          (0x7FFFFFU)
+#define SCUX_MAX_RAMP_VOLUME             (0x3FFU)
+#define SCUX_RATE_INT_CONV_VALUE         (1000U)
+#define SCUX_ADJUST_REST_VALUE           (1U)
+#define SCUX_MAX_CONV_RATE               (16000U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH1_2  (125U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH4    (250U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH6    (375U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH8    (500U)
+#define SCUX_MIN_CONV_RATE_DELAY1        (500U)
+#define SCUX_MIN_CONV_RATE_DELAY2        (1000U)
+#define SCUX_MIN_FREQ                    (1000U)
+#define SCUX_MAX_FREQ_CH1_4              (96000U)
+#define SCUX_MAX_FREQ_CH6                (66000U)
+#define SCUX_MAX_FREQ_CH8                (49000U)
+#define SCUX_PROC_DELAY_NONE             (0U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH1    (641U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH2    (321U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH4    (161U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH6    (102U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH8    (81U)
+#define SCUX_PROCESS_DELAY_1_CH1_2       (81U)
+#define SCUX_PROCESS_DELAY_2_CH1_2       (49U)
+#define SCUX_LOGIC_DELAY_BYPASS_ON       (1U)
+#define SCUX_LOGIC_DELAY_BYPASS_OFF      (3U)
+#if defined(TARGET_RZA1H) /* mbed */
+#define SCUX_AUDIO_X1                    (22579200U)
+#else
+#define SCUX_AUDIO_X1                    (12000000U)
+#endif
+#define SCUX_AUDIO_CLK                   (0U)
+#define SCUX_MLB_CLK                     (66670000U)
+#define SCUX_USB_X1                      (48000000U)
+#define SCUX_CLKLP1_DIV2                 (33335000U)
+#define SCUX_SYSTEMWORD_16               (16U)
+#define SCUX_SYSTEMWORD_24               (24U)
+#define SCUX_SYSTEMWORD_32               (32U)
+#define SCUX_SYSTEMWORD_48               (48U)
+#define SCUX_SYSTEMWORD_64               (64U)
+#define SCUX_SYSTEMWORD_128              (128U)
+#define SCUX_SYSTEMWORD_256              (256U)
+#define SCUX_SSIF_CLK_DIV1               (1U)
+#define SCUX_SSIF_CLK_DIV2               (2U)
+#define SCUX_SSIF_CLK_DIV4               (4U)
+#define SCUX_SSIF_CLK_DIV8               (8U)
+#define SCUX_SSIF_CLK_DIV16              (16U)
+#define SCUX_SSIF_CLK_DIV32              (32U)
+#define SCUX_SSIF_CLK_DIV64              (64U)
+#define SCUX_SSIF_CLK_DIV128             (128U)
+#define SCUX_SSIF_CLK_DIV6               (6U)
+#define SCUX_SSIF_CLK_DIV12              (12U)
+#define SCUX_SSIF_CLK_DIV24              (24U)
+#define SCUX_SSIF_CLK_DIV48              (48U)
+#define SCUX_SSIF_CLK_DIV96              (96U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH0    (0U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH1    (1U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH2    (2U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH3    (3U)
+#if defined(TARGET_RZA1H) /* mbed */
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH4    (4U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH5    (5U)
+#endif /* mbed */
+#define SCUX_DUMMY_BUF_SIZE              (4096U)
+#define SCUX_GET_ROUTE_MASK              (0xF000)
+#define SCUX_ROUTE_MEM_TO_MEM            (0x1000)
+#define SCUX_ROUTE_SSIF                  (0x2000)
+#define SCUX_ROUTE_MIX                   (0x3000)
+#define SCUX_FIFO_SIZE_CH0_1             (1024U)
+#define SCUX_FIFO_SIZE_CH2_3             (256U)
+#define SCUX_SSIF_NO_USE_CH              (0xFFFFU)
+#define SCUX_SSIF_USE_MIX_BIT            (0x1000U)
+#define SRC_MOD_SRC0                     (0U)
+#define SRC_MOD_SRC1                     (1U)
+#define SCUX_EVEN_VALUE_DIV              (2U)
+#define SCUX_SSIF_NUM_CH_ARRANGEMENT     (3U)
+#define SCUX_SSIF_CH_ARRANGEMENT1        (0U)
+#define SCUX_SSIF_CH_ARRANGEMENT2        (1U)
+#define SCUX_SSIF_CH_ARRANGEMENT3        (2U)
+#define SCUX_DMA_UNIT_SIZE16             (2U)
+#define SCUX_DMA_UNIT_SIZE24             (4U)
+#define SCUX_HALF_SIZE_VALUE             (2U)
+#define SCUX_RAMP_WAIT_MAX               (10U)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* DRV Status */
+typedef enum
+{
+    SCUX_DRV_UNINIT = 0,   /* Uninit */
+#if(1) /* mbed */
+    SCUX_DRV_INIT_RUNNING = 1, /* Init running */
+    SCUX_DRV_INIT         = 2  /* Init */
+#else  /* not mbed */
+    SCUX_DRV_INIT   = 1    /* Init */
+#endif /* end mbed */
+} scux_stat_drv_t;
+
+/* Channel Status */
+typedef enum
+{
+    SCUX_CH_UNINIT         = 0,   /* Uninit */
+    SCUX_CH_INIT           = 1,   /* Init */
+    SCUX_CH_STOP           = 2,   /* Open (request can't be received) */
+    SCUX_CH_TRANS_IDLE     = 4,   /* Open (request is not received) */
+    SCUX_CH_TRANS_RD       = 8,   /* Transfer (read only) */
+    SCUX_CH_TRANS_WR       = 16,  /* Transfer (read only) */
+    SCUX_CH_TRANS_RDWR     = 32,  /* Transfer (read & write) */
+    SCUX_CH_STOP_WAIT      = 64,  /* Transfer (wait flush stop) */
+    SCUX_CH_STOP_WAIT_IDLE = 128  /* Transfer (wait flush stop and request is not received */
+} scux_stat_ch_t;
+
+/* fifo size */
+typedef enum
+{
+    SCUX_FIFO_REQ_SIZE_256_64 = 0, /* fifo size is 256 data (SRC0, 1) and 64 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_128_32 = 1, /* fifo size is 128 data (SRC0, 1) and 32 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_64_16  = 2, /* fifo size is 64 data (SRC0, 1) and 16 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_32_8   = 3, /* fifo size is 32 data (SRC0, 1) and 8 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_16_4   = 4, /* fifo size is 16 data (SRC0, 1) and 4 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_8_2    = 5, /* fifo size is 8 data (SRC0, 1) and 2 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_4_1    = 6, /* fifo size is 4 data (SRC0, 1) and 1 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_2      = 7, /* fifo size is 2 data (SRC0, 1) */
+    SCUX_FIFO_REQ_SIZE_1      = 8  /* fifo size is 1 data (SRC0, 1) */
+} scux_fifo_req_size_t;
+
+/* SSIF over sampling clock divide rate */
+typedef enum
+{
+    SCUX_SSIF_CKDIV_1      = 0,   /* divide rate 1/1 */
+    SCUX_SSIF_CKDIV_2      = 1,   /* divide rate 1/2 */
+    SCUX_SSIF_CKDIV_4      = 2,   /* divide rate 1/4 */
+    SCUX_SSIF_CKDIV_8      = 3,   /* divide rate 1/8 */
+    SCUX_SSIF_CKDIV_16     = 4,   /* divide rate 1/16 */
+    SCUX_SSIF_CKDIV_32     = 5,   /* divide rate 1/32 */
+    SCUX_SSIF_CKDIV_64     = 6,   /* divide rate 1/64 */
+    SCUX_SSIF_CKDIV_128    = 7,   /* divide rate 1/128 */
+    SCUX_SSIF_CKDIV_6      = 8,   /* divide rate 1/6 */
+    SCUX_SSIF_CKDIV_12     = 9,   /* divide rate 1/12 */
+    SCUX_SSIF_CKDIV_24     = 10,  /* divide rate 1/24 */
+    SCUX_SSIF_CKDIV_48     = 11,  /* divide rate 1/48 */
+    SCUX_SSIF_CKDIV_96     = 12   /* divide rate 1/96 */
+} scux_ssif_ckdiv_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* Information of SCUX register */
+typedef struct
+{
+    struct st_scux_from_dvuir_dvu0_n            *p_dvu_reg;      /* DVU register */
+    struct st_scux_from_srcir0_2src0_n          *p_src_reg;      /* SRC register */
+    struct st_scux_from_ffuir_ffu0_n            *p_ffu_reg;      /* FFU register */
+    struct st_scux_from_ffdir_ffd0_n            *p_ffd_reg;      /* FFD register */
+    struct st_scux_from_opcir_opc0_n            *p_opc_reg;      /* OPC register */
+    struct st_scux_from_ipcir_ipc0_n            *p_ipc_reg;      /* IPC register */
+    volatile uint32_t                           *mixir_mix0_0;   /* MIXIR_MIX0_0 register */
+    volatile uint32_t                           *madir_mix0_0;   /* MADIR_MIX0_0 register */
+    volatile uint32_t                           *mixbr_mix0_0;   /* MIXBR_MIX0_0 register */
+    volatile uint32_t                           *mixmr_mix0_0;   /* MIXMR_MIX0_0 register */
+    volatile uint32_t                           *mvpdr_mix0_0;   /* MVPDR_MIX0_0 register */
+    volatile uint32_t                           *mdb_n_r_mix0_0; /* MDBAR_MIX0_0 - MDBDR_MIX0_0 register */
+    volatile uint32_t                           *mdber_mix0_0;   /* MDBER_MIX0_0 register */
+    volatile uint32_t                           *mixsr_mix0_0;   /* MIXSR_MIX0_0 register */
+    volatile uint32_t                           *swrsr_cim;      /* SWRSR_CIM register */
+    volatile uint32_t                           *dmacr_cim;      /* DMACR_CIM register */
+    volatile uint32_t                           *dmatd_n_cim;    /* DMATD0_CIM - DMATD3_CIM register */
+    volatile uint32_t                           *dmatu_n_cim;    /* DMATU0_CIM - DMATU3_CIM register */
+    volatile uint32_t                           *ssirsel_cim;    /* SSIRSEL_CIM register */
+    volatile uint32_t                           *fdtsel_n_cim;   /* FDTSEL0_CIM - FDTSEL3_CIM register */
+    volatile uint32_t                           *futsel_n_cim;   /* FUTSEL0_CIM - FUTSEL3_CIM register */
+    volatile uint32_t                           *ssipmd_cim;     /* SSIPMD_CIM register */
+    volatile uint32_t                           *ssictrl_cim;    /* SSICTRL_CIM register */
+    volatile uint32_t                           *srcrsel_n_cim;  /* SRCRSEL0_CIM - SRCRSEL3_CIM register */
+    volatile uint32_t                           *mixrsel_cim;    /* MIXRSEL_CIM register */
+} scux_reg_info_t;
+
+/* Information of SSIF */
+typedef struct
+{
+    bool_t                  ssif_enable;              /* USE SSIF flag */
+    bool_t                  ssif_setup;               /* SSIF setup complete flag */
+    osSemaphoreId_t         sem_ch_scux_ssif_access;  /* SSIF info semaphore */
+    int_t                   scux_channel;             /* SCUX ch which is using SSIF */
+    scux_src_clk_source_t   pin_clk;                  /* AUDIO_CLK source */
+    scux_pin_mode_t         pin_mode;                 /* SSIF sync setting */
+    scux_pin_mode_t         pin_mode_backup;          /* back up of SSIF sync setting */
+    scux_ssif_cfg_t         ssif_cfg;                 /* SSIF parameters */
+    scux_ssif_ckdiv_t       clk_div;                  /* Over sampling clock divide rate */
+    volatile struct st_ssif *p_scux_ssif_reg;         /* SSIF register */
+} scux_ssif_info_t;
+
+/* Information of Driver */
+typedef struct
+{
+    osSemaphoreId_t      sem_shared_access;        /* Shared info semaphore */
+    bool_t               mix_setup;                /* MIX setup complete flag */
+    uint32_t             mix_run_ch;               /* MIX used channel */
+    uint32_t             mix_ssif_ch;              /* SSIF channel on used MIX */
+    bool_t               mixmode_ramp;             /* Ramp mode / Step mode select */
+    scux_mix_ramp_time_t up_period;                /* Ramp up period */
+    scux_mix_ramp_time_t down_period;              /* Ramp down period */
+    uint32_t             mix_vol[SCUX_CH_NUM];     /* MIX volume value */
+    scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* Audio data position setting */
+    uint32_t             ssictrl_cim_value;        /* SSICTRL_CIM register (write only) value */
+} scux_shared_info_t;
+
+/* Information of Channel */
+typedef struct
+{
+    int_t              channel;                    /* Channel Number */
+    bool_t             enabled;                    /* Used channel flag */
+    int_t              open_flags;                 /* Read/write flag */
+    scux_stat_ch_t     ch_stat;                    /* Channel Status */
+    osSemaphoreId_t    sem_ch_scux_access;         /* Channel Semaphore */
+    AHF_S              tx_que;                     /* Write request queue */
+    AHF_S              rx_que;                     /* Read request queue */
+    AIOCB              *p_tx_aio;                  /* Write request information pointer */
+    AIOCB              *p_tx_next_aio;             /* Next write request information pointer */
+    AIOCB              *p_rx_aio;                  /* Read request information pointer */
+    AIOCB              *p_rx_next_aio;             /* Next read request information pointer */
+    uint8_t            int_level;                  /* Interrupt priority */
+    IRQn_Type          int_num[SCUX_INT_MAX];      /* Each interrupt number */
+    int_t              dma_tx_ch;                  /* Write DMA channel */
+    int_t              dma_rx_ch;                  /* Read DMA channel */
+    dma_res_select_t   dma_resource_tx;            /* Write DMA resource */
+    dma_res_select_t   dma_resource_rx;            /* Read DMA resource */
+    uint32_t           dma_tx_current_size;        /* Current write DMA size */
+    uint32_t           dma_tx_next_size;           /* Next write DMA size */
+    uint32_t           dma_rx_current_size;        /* Current read DMA size */
+    uint32_t           dma_rx_next_size;           /* Next read DMA size */
+    dma_ch_setup_t     dma_tx_setup;               /* Write DMA paramtter */
+    dma_ch_setup_t     dma_rx_setup;               /* Read DMA paramtter */
+    scux_reg_info_t    *p_scux_reg;                /* SCUX register information */
+    scux_route_t       route_set;                  /* SCUX route paramter */
+    scux_src_cfg_t     src_cfg;                    /* SRC parameter */
+    scux_dvu_cfg_t     dvu_cfg;                    /* DVU parameter */
+    bool_t             dvu_setup;                  /* DVU setup complete flag */
+    uint32_t           dvu_mute_stat;              /* DVU mute status */
+    scux_ssif_info_t   *p_ssif_info1;              /* SSIF channel information1  */
+    scux_ssif_info_t   *p_ssif_info2;              /* SSIF channel information2  */
+    scux_ssif_info_t   *p_ssif_info3;              /* SSIF channel information3  */
+    void               (*p_flush_callback)(int_t ercd);   /* Call back pointer for flush stop */
+    bool_t             first_tx_flag;              /* First write data transfer flag */
+    bool_t             first_rx_flag;              /* First read data transfer flag */
+    bool_t             first_ramp_flag;            /* First ramp setting flag */
+    volatile uint8_t   *p_tx_dummy_data;           /* Write dummy data buffer pointer */
+    volatile uint8_t   *p_rx_dummy_data;           /* Read dummy data buffer pointer */
+    uint32_t           flush_stop_size;            /* Needed transfer size for flush stop */
+    uint32_t           fifo_size;                  /* Fifo size */
+    uint32_t           fifo_req_size;              /* Fifo request size */
+    uint32_t           last_dummy_size;            /* Last dummy data size for flush stop */
+    uint32_t           tx_fifo_total_size;         /* Total data size of write request size / FIFO size */
+    uint32_t           rx_fifo_total_size;         /* Total data size of read request size / FIFO size */
+    bool_t             tx_dummy_run_flag;          /* Dummy data transfer flag */
+    bool_t             cancel_operate_flag;        /* indicate cancel operation */
+    bool_t             restart_ramp_flag;          /* ramp restart flag after cancel operation */
+    uint32_t           input_rate;                 /* Input rate */
+    uint32_t           output_rate;                /* Output rate */
+    uint32_t           futsel_cim_value;           /* FUTSEL_CIM register value (write only) */
+    int_t              err_stat_backup;            /* SCUX HW error status backup */
+} scux_info_ch_t;
+
+/* Information of Driver */
+typedef struct
+{
+    scux_stat_drv_t    drv_stat;              /* DRV status */
+    scux_info_ch_t     info_ch[SCUX_CH_NUM];  /* CH status */
+    scux_shared_info_t shared_info;           /* shared resource information */
+} scux_info_drv_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+scux_info_drv_t *SCUX_GetDrvInstance(void);
+scux_info_ch_t  *SCUX_GetDrvChInfo(const int_t channel);
+scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel);
+#if(1) /* mbed */
+int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param);
+void SCUX_UnInitializeOne(const int_t channel);
+#endif /* end mbed */
+int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param);
+void SCUX_UnInitialize(void);
+int_t SCUX_OpenChannel(const int_t channel, const int_t flags);
+int_t SCUX_CloseChannel(const int_t channel);
+int_t SCUX_IoctlTransStart(const int_t channel);
+int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t ercd));
+int_t SCUX_IoctlClearStop(const int_t channel);
+void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route);
+int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param);
+int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param);
+void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param);
+void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param);
+int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param);
+int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param);
+int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param);
+int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel);
+int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param);
+int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol);
+int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t *const p_ssif_param);
+void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat);
+void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat);
+void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat);
+void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat);
+void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat);
+int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio);
+int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio);
+int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio);
+int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio);
+int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio);
+int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size);
+void  SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetMixVolRegister(const int_t channel);
+int_t SCUX_CheckSsifClockDiv(const scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch_num);
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch);
+size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen);
+
+#endif /* SCUX_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux_board.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,734 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_board.c
+* $Rev: $
+* $Date::                           $
+* @brief        SCUX functions depending on borad
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSsifClockDiv
+* @brief         Check SSIF clock divide rate.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EPERM_RBSP : Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CheckSsifClockDiv(const scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch_num)
+{
+    int_t retval = ESUCCESS;
+    uint32_t input_clk;
+    uint32_t dot_clk;
+    uint32_t n_syswd_per_smp;
+    uint32_t syswd_len =0;
+    uint32_t smp_freq;
+    uint32_t result;
+    uint32_t division;
+    scux_ssif_info_t * p_ssif_ch;
+
+    p_ssif_ch = SCUX_GetSsifChInfo((int_t)ssif_ch_num);
+
+    if ((NULL == p_scux_info_ch) || (NULL == p_ssif_ch))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (false == p_ssif_ch->ssif_cfg.mode_master)
+        {
+            /* In slave mode, a temporary value is to SCUX_SSIF_CKDIV_1 (0) */
+            p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_1;
+        }
+        else
+        {
+            /* check only SSIF master mode */
+            /* get source clock */
+            if (false == p_ssif_ch->ssif_cfg.select_audio_clk)
+            {
+                input_clk = SCUX_AUDIO_X1;
+            }
+            else
+            {
+                input_clk = SCUX_AUDIO_CLK;
+            }
+
+            if (0u == input_clk)
+            {
+                retval = EPERM_RBSP;
+            }
+
+            if (ESUCCESS == retval)
+            {
+                switch (p_ssif_ch->ssif_cfg.system_word)
+                {
+                    case SCUX_SSIF_SYSTEM_LEN_16 :
+                        syswd_len = SCUX_SYSTEMWORD_16;
+                    break;
+
+                    case SCUX_SSIF_SYSTEM_LEN_24 :
+                        syswd_len = SCUX_SYSTEMWORD_24;
+                    break;
+
+                    case SCUX_SSIF_SYSTEM_LEN_32 :
+                        syswd_len = SCUX_SYSTEMWORD_32;
+                    break;
+
+                    case SCUX_SSIF_SYSTEM_LEN_48 :
+                        syswd_len = SCUX_SYSTEMWORD_48;
+                    break;
+
+                    case SCUX_SSIF_SYSTEM_LEN_64 :
+                        syswd_len = SCUX_SYSTEMWORD_64;
+                    break;
+
+                    case SCUX_SSIF_SYSTEM_LEN_128 :
+                        syswd_len = SCUX_SYSTEMWORD_128;
+                    break;
+
+                    case SCUX_SSIF_SYSTEM_LEN_256 :
+                        syswd_len = SCUX_SYSTEMWORD_256;
+                    break;
+
+                    default :
+                        retval = EPERM_RBSP;
+                    break;
+                }
+
+                smp_freq = p_scux_info_ch->src_cfg.output_ws;
+
+                if (false == p_ssif_ch->ssif_cfg.use_tdm)
+                {
+                    n_syswd_per_smp = SCUX_USE_CH_2;
+                }
+                else
+                {
+                    n_syswd_per_smp = p_scux_info_ch->src_cfg.use_ch;
+                }
+
+                dot_clk = syswd_len * n_syswd_per_smp * smp_freq;
+                if (0u == dot_clk)
+                {
+                    retval = EPERM_RBSP;
+                }
+                else
+                {
+                    /* check if input audio clock can be divided by dotclock */
+                    result = input_clk % dot_clk;
+
+                    if (0U != result)
+                    {
+                        /* cannot create dotclock from input audio clock */
+                        retval = EPERM_RBSP;
+                    }
+                    else
+                    {
+                        division = input_clk / dot_clk;
+
+                        switch (division)
+                        {
+                            case SCUX_SSIF_CLK_DIV1:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_1;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV2:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_2;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV4:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_4;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV8:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_8;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV16:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_16;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV32:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_32;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV64:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_64;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV128:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_128;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV6:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_6;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV12:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_12;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV24:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_24;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV48:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_48;
+                            break;
+
+                            case SCUX_SSIF_CLK_DIV96:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_96;
+                            break;
+
+                            default:
+                                retval = EPERM_RBSP;
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSsifClockDiv
+******************************************************************************/
+
+#if(1) /* mbed */
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch)
+{
+    UNUSED_ARG(ssif_ch);
+
+    return;
+}
+#else  /* not mbed */
+
+#if defined(TARGET_RZA1H) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_SetupSsifGpio
+* @brief         GPIO of SSIF module setup.
+
+*                Description:<br>
+*                R7S72100 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: Working with SSIF5<br>
+*                Channel settings<br>
+*                  SSIF0    : Fully connected to WM8978<br>
+*                  SSIF1    : Read only (NC:SSITxD1) connected to CD Deck<br>
+*                  SSIF2    : No connection<br>
+*                  SSIF3    : Write only (NC:SSIRxD3) connected to AK4353<br>
+*                  SSIF4    : Fully connected to AK4353<br>
+*                  SSIF5    : Fully connected to HCI
+*                
+* @param[in]     ssif_ch :SSIF channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch)
+{
+    switch (ssif_ch)
+    {
+        case SCUX_SSIF_CH_0:
+            /* SSISCK0(P4_4, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N4);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS0(P4_5, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N5);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD0(P4_6, Alternative Mode 5,Input) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N6);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD0(P4_7, Alternative Mode 5,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N7);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N7);
+        break;
+
+        case SCUX_SSIF_CH_1:
+            /* SSISCK1(P3_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS1(P3_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC3 |=  (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD1(P3_6, Alternative Mode 3,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD1:  no connection */
+        break;
+
+        case SCUX_SSIF_CH_2:
+            /* SSISCK2:  no connection */
+            /* SSIWS2:   no connection */
+            /* SSIDATA2: no connection */
+            break;
+
+        case SCUX_SSIF_CH_3:
+            /* SSISCK3(P4_12, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N12);
+
+            GPIO.PIPC4  |= (uint16_t) GPIO_BIT_N12;
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS3(P4_13, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N13);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIRxD3:  no connection */
+
+            /* SSITxD3(P4_15, Alternative Mode 6,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N15);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N15);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N15);
+        break;
+
+        case SCUX_SSIF_CH_4:
+            /* SSISCK4(P11_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS4(P11_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC11  |= (uint16_t) GPIO_BIT_N5;
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIDATA4(P11_6, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N6);
+        break;
+
+        case SCUX_SSIF_CH_5:
+            /* SSISCK5(P2_4, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS5(P2_5, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD5(P2_6, Alternative Mode 4,Input) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD5(P2_7, Alternative Mode 4,Output) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM2    &= (uint16_t)~(GPIO_BIT_N7);
+
+            /* AUDIO_CLK(P3_1, Alternative Mode 6,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N1);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFC3   |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PFCE3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFCAE3 |= (uint16_t) (GPIO_BIT_N1);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N1);
+        break;
+
+        default:
+            /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+            /* <-IPA R3.5.2 */
+            /* NOTREACHED on At the time of a normal performance */
+        break;
+    }
+
+    return;
+}
+#else /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_SetupSsifGpio
+* @brief         GPIO of SSIF module setup.
+
+*                Description:<br>
+*                R7S72103 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: This port is not set.
+*                             (If you don't use EtherAVB, don't need to set.)
+*                Channel settings<br>
+*                  SSIF0    : No connection<br>
+*                  SSIF1    : Fully connected to AK4353<br>
+*                  SSIF2    : Fully connected to WM8978<br>
+*                  SSIF3    : No connection<br>
+*
+* @param[in]     ssif_ch :SSIF channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch)
+{
+    switch (ssif_ch)
+    {
+        case SCUX_SSIF_CH_0:
+            /* SSISCK0:  no connection */
+            /* SSIWS0:   no connection */
+            /* SSIRxD0:  no connection */
+            /* SSITxD0:  no connection */
+        break;
+
+        case SCUX_SSIF_CH_1:
+            /* SSISCK1:  P7_8, Alt2(001), Input/Output */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N8);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N8);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N8);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N8);
+
+            GPIO.PIPC7  |= (uint16_t) (GPIO_BIT_N8);
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N8);
+
+            /* SSIWS1:   P7_9, Alt2(001), Input/Output */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N9);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N9);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N9);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N9);
+
+            GPIO.PIPC7  |= (uint16_t) (GPIO_BIT_N9);
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N9);
+
+            /* SSIRxD1:  P7_11, Alt2(001), Input */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N11);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N11);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N11);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N11);
+
+            GPIO.PIPC7  |= (uint16_t) (GPIO_BIT_N11);
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N11);
+
+            /* SSITxD1:  P7_10, Alt2(001), Output */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N10);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N10);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N10);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N10);
+
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N10);
+            GPIO.PM7    &= (uint16_t)~(GPIO_BIT_N10);
+        break;
+
+        case SCUX_SSIF_CH_2:
+            /* SSISCK2:  P6_12, Alt4(011), Input/Output */
+            GPIO.PIBC6  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM6    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC6   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC6  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFC6   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE6  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCAE6 &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PIPC6  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC6   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS2:   P6_13, Alt4(011), Input/Output */
+            GPIO.PIBC6  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM6    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC6   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC6  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFC6   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE6  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCAE6 &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PIPC6  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC6   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIDATA2: P6_14, Alt4(011), Input/Output */
+            GPIO.PIBC6  &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PM6    |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PMC6   &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PIPC6  &= (uint16_t)~(GPIO_BIT_N14);
+
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PFC6   |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PFCE6  |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PFCAE6 &= (uint16_t)~(GPIO_BIT_N14);
+
+            GPIO.PIPC6  |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PMC6   |= (uint16_t) (GPIO_BIT_N14);
+            break;
+
+        case SCUX_SSIF_CH_3:
+            /* SSISCK3:  no connection */
+            /* SSIWS3:   no connection */
+            /* SSIRxD3:  no connection */
+            /* SSITxD3:  no connection */
+        break;
+
+        default:
+            /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+            /* <-IPA R3.5.2 */
+            /* NOTREACHED on At the time of a normal performance */
+        break;
+    }
+
+    return;
+}
+#endif /* mbed */
+#endif /* mbed */
+
+/******************************************************************************
+End of function SCUX_SetupSsifGpio
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux_dev.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,4963 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_dev.c
+* $Rev: $
+* $Date::                           $
+* @brief        SCUX device control functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include  "mbed_critical.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* SSIF clock mask register table define */
+static const uint32_t gb_cpg_scux_ssif_stbcr_bit[SCUX_SSIF_CH_NUM] =
+{
+    CPG_STBCR11_BIT_MSTP115,    /* SSIF0 */
+    CPG_STBCR11_BIT_MSTP114,    /* SSIF1 */
+    CPG_STBCR11_BIT_MSTP113,    /* SSIF2 */
+    CPG_STBCR11_BIT_MSTP112,    /* SSIF3 */
+#if defined(TARGET_RZA1H) /* mbed */
+    CPG_STBCR11_BIT_MSTP111,    /* SSIF4 */
+    CPG_STBCR11_BIT_MSTP110     /* SSIF5 */
+#endif /* mbed */
+};
+
+/* SSIF software reset register table define */
+static const uint32_t gb_cpg_scux_ssif_swrst_bit[SCUX_SSIF_CH_NUM] =
+{
+    CPG_SWRSTCR1_BIT_SRST16,    /* SSIF0 */
+    CPG_SWRSTCR1_BIT_SRST15,    /* SSIF1 */
+    CPG_SWRSTCR1_BIT_SRST14,    /* SSIF2 */
+    CPG_SWRSTCR1_BIT_SRST13,    /* SSIF3 */
+#if defined(TARGET_RZA1H) /* mbed */
+    CPG_SWRSTCR1_BIT_SRST12,    /* SSIF4 */
+    CPG_SWRSTCR1_BIT_SRST11     /* SSIF5 */
+#endif /* mbed */
+};
+
+/* SSIF noise cancel register table define */
+static const uint32_t gb_cpg_scux_ssif_sncr_bit[SCUX_SSIF_CH_NUM] =
+{
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH0,  /* SSIF0 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH1,  /* SSIF1 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH2,  /* SSIF2 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH3,  /* SSIF3 */
+#if defined(TARGET_RZA1H) /* mbed */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH4,  /* SSIF4 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH5   /* SSIF5 */
+#endif /* mbed */
+};
+
+/* AIOCB information for DMA */
+static AIOCB gb_scux_write_dma_aio[SCUX_CH_NUM];
+static AIOCB gb_scux_read_dma_aio[SCUX_CH_NUM];
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+
+static void  SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_DMA_CopyRxCallBack(union sigval const param);
+static void  SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxCallBack(union sigval const param);
+static void  SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxCallBack(union sigval const param);
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyWriteStart
+* @brief         Start write request (mem->mem).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    uint32_t         dma_src_addr;
+#if(1) /* mbed */
+    int32_t          ret;
+#else
+    int_t            ret;
+#endif
+
+    if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_tx_aio = p_write_aio;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+            p_scux_info_ch->first_tx_flag = false;
+
+            /* cast uint8_t pointer from void pointer */
+            dma_src_addr = (uint32_t)p_write_aio->aio_buf;
+
+            /* set 1st DMA parameter */
+            dma_address_param.src_addr = (void *)dma_src_addr;
+            dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_write_aio->aio_nbytes;
+
+            dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                /* enable interrupt */
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET |
+                                                                       DEVMR_FFD0_DEVMOF_SET |
+                                                                       DEVMR_FFD0_DEVMOL_SET |
+                                                                       DEVMR_FFD0_DEVMIUF_SET);
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                /* start clock devide on async mode */
+                if (false == p_scux_info_ch->src_cfg.mode_sync)
+                {
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+#if defined(TARGET_RZA1H) /* mbed */
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+#else /* mbed */
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async))
+#endif /* mbed */
+                    {
+                        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                    }
+                }
+                /* update channel status */
+                switch (p_scux_info_ch->ch_stat)
+                {
+                    case SCUX_CH_UNINIT :
+                        /* fall through */
+                    case SCUX_CH_INIT :
+                        /* fall through */
+                    case SCUX_CH_STOP :
+                        retval = EBADF_RBSP;
+                    break;
+
+                    case SCUX_CH_TRANS_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                    break;
+
+                    case SCUX_CH_TRANS_RD :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
+                    break;
+
+                    case SCUX_CH_TRANS_WR :
+                        /* fall through */
+                    case SCUX_CH_TRANS_RDWR :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT_IDLE :
+                        /* do nothing, stats isn't updated */
+                    break;
+
+                    default :
+                        retval = EFAULT_RBSP;
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectWriteStart
+* @brief         Start write request(SSIF direct route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    dma_trans_data_t next_dma_address_param;
+    uint32_t         dma_src_addr;
+#if(1) /* mbed */
+    int32_t          ret;
+#else
+    int_t            ret;
+#endif
+    uint32_t         ramp_wait_cnt = 0;
+
+    if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = p_write_aio;
+            p_scux_info_ch->first_tx_flag = true;
+
+            /* cast uint8_t pointer from void pointer */
+            dma_src_addr = (uint32_t)p_write_aio->aio_buf;
+
+            /* set 2nd DMA parameter */
+            next_dma_address_param.src_addr = (void *)(dma_src_addr + (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE));
+            next_dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+            next_dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
+            if (0U != (p_write_aio->aio_nbytes % SCUX_HALF_SIZE_VALUE))
+            {
+                /* last data ,when even value size */
+                next_dma_address_param.count++;
+            }
+            dma_retval = R_DMA_NextData(p_scux_info_ch->dma_tx_ch, &next_dma_address_param, &ret);
+
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                p_scux_info_ch->dma_tx_next_size = next_dma_address_param.count;
+                /* set 1st DMA parameter */
+                dma_address_param.src_addr = (void *)dma_src_addr;
+                dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+                dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
+
+                dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
+                if (ESUCCESS != dma_retval)
+                {
+                    retval = EFAULT_RBSP;
+                }
+                else
+                {
+                    p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                    /* enable interrupt */
+                    p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET |
+                                                                           DEVMR_FFD0_DEVMOF_SET |
+                                                                           DEVMR_FFD0_DEVMOL_SET |
+                                                                           DEVMR_FFD0_DEVMIUF_SET);
+                    p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                    *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+
+                    switch (p_scux_info_ch->ch_stat)
+                    {
+                        case SCUX_CH_UNINIT :
+                            /* fall through */
+                        case SCUX_CH_INIT :
+                            /* fall through */
+                        case SCUX_CH_STOP :
+                            /* fall through */
+                            retval = EBADF_RBSP;
+                        break;
+
+                        case SCUX_CH_TRANS_IDLE :
+                            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                        break;
+
+                        case SCUX_CH_TRANS_RD :
+                            /* read function disabled */
+                            retval = EFAULT_RBSP;
+                        break;
+
+                        case SCUX_CH_TRANS_WR :
+                            /* do nothing, stats isn't updated */
+                        break;
+
+                        case SCUX_CH_TRANS_RDWR :
+                            /* read function disabled */
+                            retval = EFAULT_RBSP;
+                        break;
+
+                        case SCUX_CH_STOP_WAIT :
+                            /* do nothing, stats isn't updated */
+                        break;
+
+                        case SCUX_CH_STOP_WAIT_IDLE :
+                            /* read function disabled */
+                            retval = EFAULT_RBSP;
+                        break;
+
+                        default :
+                            /* NOTREACHED on At the time of a normal performance */
+                            retval = EFAULT_RBSP;
+                        break;
+                    }
+
+                    /* set ramp setting */
+                    if (false == p_scux_info_ch->first_ramp_flag)
+                    {
+                        while((DVUSR_DVU0_VRSTS_VOL_FIX != (p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK)) &&
+                              (SCUX_RAMP_WAIT_MAX > ramp_wait_cnt))
+                        {
+                            ramp_wait_cnt++;
+                        }
+                        if (SCUX_RAMP_WAIT_MAX <= ramp_wait_cnt)
+                        {
+                            retval = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+                            SCUX_SetRampVolRegister(p_scux_info_ch);
+                            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+                            p_scux_info_ch->first_ramp_flag = true;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_DirectWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyReadStart
+* @brief         Start read request(mem -> mem).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_read_aio:Read request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    uint32_t         dma_dst_addr;
+
+    if ((NULL == p_scux_info_ch) || (NULL == p_read_aio))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_rx_ch, &p_scux_info_ch->dma_rx_setup, NULL);
+
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_rx_aio = p_read_aio;
+            p_scux_info_ch->p_rx_next_aio = NULL;
+            p_scux_info_ch->first_rx_flag = false;
+
+            /* cast uint8_t pointer from void pointer */
+            dma_dst_addr = (uint32_t)p_read_aio->aio_buf;
+
+            /* set 1st DMA parameter */
+            dma_address_param.src_addr = (void *)p_scux_info_ch->p_scux_reg->dmatu_n_cim;
+            dma_address_param.dst_addr = (void *)dma_dst_addr;
+            dma_address_param.count = p_read_aio->aio_nbytes;
+
+            dma_retval = R_DMA_Start(p_scux_info_ch->dma_rx_ch, &dma_address_param, NULL);
+
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                /* enable interrupt */
+                p_scux_info_ch->dma_rx_current_size = dma_address_param.count;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = (UEVMR_FFU0_UEVMUF_SET |
+                                                                       UEVMR_FFU0_UEVMOF_SET |
+                                                                       UEVMR_FFU0_UEVMOL_SET);
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = DEVCR_FFD0_INIT_VALUE;
+                /* start clock devide on async mode */
+                if (false == p_scux_info_ch->src_cfg.mode_sync)
+                {
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+#if defined(TARGET_RZA1H) /* mbed */
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+#else /* mbed */
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async))
+#endif /* mbed */
+                    {
+                        p_scux_info_ch->futsel_cim_value |= FUTSEL_CIM_DIVEN_SET;
+                        *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+                    }
+                }
+                /* update channel status */
+
+                switch (p_scux_info_ch->ch_stat)
+                {
+                    case SCUX_CH_UNINIT :
+                        /* fall through */
+                    case SCUX_CH_INIT :
+                        /* fall through */
+                    case SCUX_CH_STOP :
+                        /* fall through */
+                        retval = EBADF_RBSP;
+                    break;
+
+                    case SCUX_CH_TRANS_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RD;
+                    break;
+
+                    case SCUX_CH_TRANS_RD :
+                        /* do nothing, stats isn't updated */
+                    break;
+
+                    case SCUX_CH_TRANS_WR :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
+                    break;
+
+                    case SCUX_CH_TRANS_RDWR :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT :
+                        /* do nothing, stats isn't updated */
+                    break;
+
+                    case SCUX_CH_STOP_WAIT_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    break;
+
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EFAULT_RBSP;
+                    break;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyReadStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_FlushWriteStart
+* @brief         Start dummy write for FIFO flush.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    dma_trans_data_t dma_address_param;
+
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (0U != p_scux_info_ch->flush_stop_size)
+        {
+            retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+
+            if (ESUCCESS != retval)
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                /* trans dummy data size is FIFO size unit */
+                if (p_scux_info_ch->flush_stop_size >= p_scux_info_ch->fifo_size)
+                {
+                    dma_address_param.count = p_scux_info_ch->fifo_size;
+                    p_scux_info_ch->flush_stop_size -= p_scux_info_ch->fifo_size;
+                }
+                else
+                {
+                    /* last data is fraction of FIFO size */
+                    dma_address_param.count = p_scux_info_ch->flush_stop_size;
+                    p_scux_info_ch->flush_stop_size = 0;
+                }
+
+                dma_address_param.src_addr = (void *)(p_scux_info_ch->p_tx_dummy_data);
+                dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+
+                retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, NULL);
+                if (ESUCCESS != retval)
+                {
+                    retval = EFAULT_RBSP;
+                }
+                else
+                {
+                    p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+
+                    p_scux_info_ch->tx_dummy_run_flag = true;
+
+                    if ((SCUX_CH_TRANS_RD == p_scux_info_ch->ch_stat) || (SCUX_CH_TRANS_IDLE == p_scux_info_ch->ch_stat))
+                    {
+                        /* restart write operation when write is stopped */
+                        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET |
+                                                                               DEVMR_FFD0_DEVMOF_SET |
+                                                                               DEVMR_FFD0_DEVMOL_SET |
+                                                                               DEVMR_FFD0_DEVMIUF_SET);
+                        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0
+                        = DEVCR_FFD0_INIT_VALUE;
+                        /* start clock devide on async mode or SSIF direct route setting */
+                        if (false == p_scux_info_ch->src_cfg.mode_sync)
+                        {
+                            if((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+#if defined(TARGET_RZA1H) /* mbed */
+                               (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async)) 
+#else /* mbed */
+                               (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async))
+#endif /* mbed */
+                            {
+                                *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_FlushWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyCancelSpecific
+* @brief         Cancel specific request(mem->mem).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     *p_cancel_aio : Cancel request information.
+* @retval        ESUCCESS : Operation successful.
+*                EBUSY_RBSP  : Cancel requst is on going.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dummy_retval;
+
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        core_util_critical_section_enter();
+
+        /* check cancel request */
+        if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_rx_aio == p_cancel_aio))
+        {
+            retval = EBUSY_RBSP;
+        }
+        else
+        {
+            /* request don't going */
+            dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+            dummy_retval = ahf_cancel(&p_scux_info_ch->rx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_CopyCancelSpecific
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectCancelSpecific
+* @brief         Cancel specific request(SSIF direct route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     *p_cancel_aio : Cancel request information.
+* @retval        ESUCCESS : Operation successful.
+*                EBUSY_RBSP  : Cancel requst is on going.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dummy_retval;
+
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        core_util_critical_section_enter();
+
+        /* check cancel request */
+        if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_tx_next_aio == p_cancel_aio))
+        {
+            retval = EBUSY_RBSP;
+        }
+        else
+        {
+            /* request don't going */
+            dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_DirectCancelSpecific
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyCancelAll
+* @brief         Cancel all request(mem->mem).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+#if(1) /* mbed */
+    int32_t  dma_ercd;
+#else
+    int_t    dma_ercd;
+#endif
+    int_t    dma_retval;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        core_util_critical_section_enter();
+
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF_RBSP, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF_RBSP != dma_ercd))
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+        }
+
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF_RBSP, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF_RBSP != dma_ercd))
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size;
+            p_scux_info_ch->dma_rx_current_size = 0;
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* return write request */
+            if (NULL !=  p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ECANCELED_RBSP;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+
+            /* return read request */
+            if (NULL != p_scux_info_ch->p_rx_aio)
+            {
+                p_scux_info_ch->p_rx_aio->aio_return = ECANCELED_RBSP;
+                ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio);
+            }
+
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            ahf_cancelall(&p_scux_info_ch->rx_que);
+
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_rx_aio = NULL;
+
+            SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size);
+            p_scux_info_ch->cancel_operate_flag = true;
+
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                SCUX_SyncStopHw(p_scux_info_ch);
+                SCUX_InitHw(p_scux_info_ch);
+                SCUX_SetupSrc(p_scux_info_ch);
+                SCUX_SyncStartHw(p_scux_info_ch);
+            }
+            else
+            {
+                SCUX_AsyncStopHw(p_scux_info_ch);
+                SCUX_InitHw(p_scux_info_ch);
+                SCUX_SetupSrc(p_scux_info_ch);
+                SCUX_AsyncStartHw(p_scux_info_ch);
+            }
+
+            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_scux_info_ch->p_flush_callback = NULL;
+
+            p_scux_info_ch->tx_fifo_total_size = 0;
+            p_scux_info_ch->rx_fifo_total_size = 0;
+
+            p_scux_info_ch->cancel_operate_flag = false;
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyCancelAll
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectCancelAll
+* @brief         Cancel all request(SSIF direct route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+#if(1) /* mbed */
+    int32_t  dma_ercd;
+#else
+    int_t    dma_ercd;
+#endif
+    int_t    dma_retval;
+    uint32_t tx_remain_size = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        core_util_critical_section_enter();
+
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF_RBSP, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF_RBSP != dma_ercd))
+        {
+            retval = EFAULT_RBSP;
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+
+            if (NULL != p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ECANCELED_RBSP;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED_RBSP;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+
+            SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, 0);
+
+            p_scux_info_ch->cancel_operate_flag = true;
+            p_scux_info_ch->restart_ramp_flag = true;
+
+            SCUX_AsyncStopHw(p_scux_info_ch);
+
+            SCUX_InitHw(p_scux_info_ch);
+            SCUX_SetupSsif(p_scux_info_ch);
+            SCUX_SetupSrc(p_scux_info_ch);
+            SCUX_SetupDvu(p_scux_info_ch);
+            SCUX_AsyncStartHw(p_scux_info_ch);
+
+            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_scux_info_ch->p_flush_callback = NULL;
+
+            p_scux_info_ch->tx_fifo_total_size = 0;
+            p_scux_info_ch->rx_fifo_total_size = 0;
+            p_scux_info_ch->dvu_mute_stat = 0;
+            p_scux_info_ch->first_ramp_flag = false;
+            p_scux_info_ch->cancel_operate_flag = false;
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_DirectCancelAll
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_AdjustAccessFifo
+* @brief         Fifo is Cleared.
+*
+*                Description:<br>
+*
+* @param[in]     p_scux_info_ch:channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size)
+{
+    uint32_t dummy_data_size;
+    uint32_t request_data_size;
+    uint32_t access_size = SCUX_DMA_UNIT_SIZE16;
+    uint32_t dummy_read_data;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+        switch (p_scux_info_ch->src_cfg.word_len)
+        {
+            case SCUX_DATA_LEN_24 :
+                access_size = SCUX_DMA_UNIT_SIZE24;
+            break;
+
+            case SCUX_DATA_LEN_16 :
+                /* fall through */
+            case SCUX_DATA_LEN_16_TO_24 :
+                access_size = SCUX_DMA_UNIT_SIZE16;
+            break;
+
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET |
+                                                                 DEVMR_FFD0_DEVMOF_SET |
+                                                                 DEVMR_FFD0_DEVMOL_SET |
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        /* access count is adjusted for tx DMA remain size */
+        if (0U != tx_remain_size)
+        {
+            for (dummy_data_size = 0; dummy_data_size < tx_remain_size; dummy_data_size += access_size )
+            {
+                *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
+            }
+        }
+
+        /* access count is adjusted for tx total remain size */
+        if (0U != (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
+        {
+            request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
+            for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
+            {
+                *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
+            }
+        }
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = 0;
+        *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+            switch (p_scux_info_ch->src_cfg.word_len)
+            {
+                case SCUX_DATA_LEN_16 :
+                    access_size = SCUX_DMA_UNIT_SIZE16;
+                break;
+
+                case SCUX_DATA_LEN_24 :
+                    /* fall through */
+                case SCUX_DATA_LEN_16_TO_24 :
+                    access_size = SCUX_DMA_UNIT_SIZE24;
+                break;
+
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET |
+                                                                     UEVMR_FFU0_UEVMOF_SET |
+                                                                     UEVMR_FFU0_UEVMOL_SET);
+            /* access count is adjusted for rx DMA remain size */
+            if (0U != rx_remain_size)
+            {
+                for (dummy_data_size = 0; dummy_data_size < rx_remain_size; dummy_data_size += access_size )
+                {
+                    dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
+                    UNUSED_ARG(dummy_read_data);
+                }
+            }
+
+            /* access count is adjusted for rx total remain size */
+            if (0U != (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
+            {
+                request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
+
+                for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
+                {
+                    dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
+                    UNUSED_ARG(dummy_read_data);
+                }
+            }
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = 0;
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AdjustAccessFifo
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrc
+* @brief         SRC HW setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t process_delay = 0;
+    uint32_t data_size;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (false != p_scux_info_ch->src_cfg.src_enable)
+        {
+            /* check delay mode and enabled audio channel */
+            switch (p_scux_info_ch->src_cfg.delay_mode)
+            {
+                case SCUX_DELAY_NORMAL :
+                    switch (p_scux_info_ch->src_cfg.use_ch)
+                    {
+                        case SCUX_USE_CH_1 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH1;
+                        break;
+
+                        case SCUX_USE_CH_2 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH2;
+                        break;
+
+                        case SCUX_USE_CH_4 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH4;
+                        break;
+
+                        case SCUX_USE_CH_6 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH6;
+                        break;
+
+                        case SCUX_USE_CH_8 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH8;
+                        break;
+
+                        default :
+                            /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                            /* <-IPA R3.5.2 */
+                            /* NOTREACHED on At the time of a normal performance */
+                        break;
+                    }
+                break;
+
+                case SCUX_DELAY_LOW_DELAY1 :
+                    process_delay = SCUX_PROCESS_DELAY_1_CH1_2;
+                break;
+
+                case SCUX_DELAY_LOW_DELAY2 :
+                    process_delay = SCUX_PROCESS_DELAY_2_CH1_2;
+                break;
+
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+
+            /* set dummy data size for flush */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                data_size = sizeof(uint16_t);
+            }
+            else
+            {
+                data_size = sizeof(uint32_t);
+            }
+
+            process_delay = (process_delay * ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate));
+            if (0U != (process_delay % SCUX_RATE_INT_CONV_VALUE))
+            {
+                /* A redundant value is added that delay size below a decimal point may come out */
+                process_delay = ((process_delay / SCUX_RATE_INT_CONV_VALUE) + SCUX_ADJUST_REST_VALUE);
+            }
+            else
+            {
+                process_delay = (process_delay / SCUX_RATE_INT_CONV_VALUE);
+            }
+
+            p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * (process_delay + SCUX_LOGIC_DELAY_BYPASS_OFF)));
+            if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
+            {
+                /* set even value */
+                p_scux_info_ch->flush_stop_size++;
+            }
+        }
+        else
+        {
+            /* set dummy data size for flush */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                data_size = sizeof(uint16_t);
+            }
+            else
+            {
+                data_size = sizeof(uint32_t);
+            }
+
+            p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * SCUX_LOGIC_DELAY_BYPASS_ON));
+            if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
+            {
+                /* set even value */
+                p_scux_info_ch->flush_stop_size++;
+            }
+        }
+
+        p_scux_info_ch->tx_dummy_run_flag = false;
+
+        /* set FFD & FFU parameter depend on the combination of route and sync mode */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_SYNC;
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_ASYNC;
+            }
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = 0;
+            p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_DIRECT;
+        }
+
+        /* set route CIM register for SSIF channel and MIX */
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                /* do nothing, when mem to mem route is setting */
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC0_SET;
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC0_SET | SSIRSEL_CIM_SOSEL1_SRC0_SET | SSIRSEL_CIM_SOSEL2_SRC0_SET);
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC0_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC0_SET | SSIRSEL_CIM_SOSEL4_SRC0_SET | SSIRSEL_CIM_SOSEL5_SRC0_SET);
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC1_SET;
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC1_SET | SSIRSEL_CIM_SOSEL1_SRC1_SET | SSIRSEL_CIM_SOSEL2_SRC1_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC1_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC1_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC1_SET | SSIRSEL_CIM_SOSEL4_SRC1_SET | SSIRSEL_CIM_SOSEL5_SRC1_SET);
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL1_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL1_SRC2_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL4_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL4_SRC2_SET;
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL2_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL2_SRC3_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL5_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL5_SRC3_SET;
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+#endif /* mbed */
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                 /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+
+        SCUX_SetupDataPosition(p_scux_info_ch);
+
+        /* set route SSICTRL register for each route */
+        if (false == p_scux_info_ch->src_cfg.mode_sync)
+        {
+            switch (p_scux_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* do nothing, when mem to mem route is setting */
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_SSIF345 :
+#endif /* mbed */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_SSIF345 :
+#endif /* mbed */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI1TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI4TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI2TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI5TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+#endif /* mbed */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+#endif /* mbed */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+#endif /* mbed */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+#endif /* mbed */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+
+        SCUX_SetupSrcClk(p_scux_info_ch);
+
+        /* set pin mode for each route */
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF0 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF012 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+#endif /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC1_SSIF0 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF012 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+#endif /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC1_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+#endif /* mbed */
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+#else /* mbed */
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+            break;
+#endif /* mbed */
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+#endif /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+#endif /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+#endif /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                /* fall through */
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+#endif /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                }
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+#if defined(TARGET_RZA1H) /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+#else /* mbed */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET);
+#endif /* mbed */
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+#endif /* mbed */
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+
+        SCUX_SetupFifo(p_scux_info_ch);
+        SCUX_SetupSrcFunction(p_scux_info_ch);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSrc
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupDataPosition
+* @brief         Audio data position setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t audio_place = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* set data posion for SRC */
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            audio_place |= (((uint32_t)p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch] & SRCRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * SRCRSEL_CIM_PLACE_N_SHIFT));
+        }
+        *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = audio_place;
+
+        /* set data position for MIX */
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            if (0U == p_info_drv->shared_info.mix_run_ch)
+            {
+                audio_place = 0;
+                for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+                {
+                    audio_place |= (((uint32_t)p_info_drv->shared_info.select_out_data_ch[audio_ch] & MIXRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * MIXRSEL_CIM_PLACE_N_SHIFT));
+                }
+                *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = audio_place;
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDataPosition
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrcClk
+* @brief         SRC clock setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t fdtsel_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* set input timing clock */
+        if (false == p_scux_info_ch->src_cfg.mode_sync)
+        {
+            /* get value of register setting */
+            switch (p_scux_info_ch->src_cfg.input_clk_async)
+            {
+
+                case SCUX_CLK_AUDIO_CLK :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
+                                   FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
+                break;
+
+                case SCUX_CLK_AUDIO_X1 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
+                                   FDTSEL_CIM_SCKSEL_AUDIO_X1_SET);
+                break;
+
+                case SCUX_CLK_MLB_CLK :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
+                                   FDTSEL_CIM_SCKSEL_MLB_CLK_SET);
+                break;
+
+                case SCUX_CLK_USB_X1 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
+                                   FDTSEL_CIM_SCKSEL_USB_X1_SET);
+                break;
+
+                case SCUX_CLK_CLKP1_2 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
+                                   FDTSEL_CIM_SCKSEL_CLKP1_2_SET);
+                break;
+
+                case SCUX_CLK_MTU_TIOC3A :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
+                                    FDTSEL_CIM_SCKSEL_MTUSEL2_SET |
+                                    FDTSEL_CIM_MTUSEL_SET_TIOC3A);
+                break;
+
+                case SCUX_CLK_MTU_TIOC4A :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) |
+                                    FDTSEL_CIM_SCKSEL_MTUSEL2_SET |
+                                    FDTSEL_CIM_MTUSEL_SET_TIOC4A);
+                break;
+
+                case SCUX_CLK_SSIF0_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF0_WS_SET;
+                break;
+
+                case SCUX_CLK_SSIF1_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF1_WS_SET;
+                break;
+
+                case SCUX_CLK_SSIF2_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF2_WS_SET;
+                break;
+
+                case SCUX_CLK_SSIF3_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF3_WS_SET;
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_CLK_SSIF4_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF4_WS_SET;
+                break;
+
+                case SCUX_CLK_SSIF5_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF5_WS_SET;
+                break;
+
+#endif /* mbed */
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+            *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = fdtsel_value;
+        }
+
+        /* set output timing clock on MIX */
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->futsel_cim_value = (((0 << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                (((uint32_t)p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num | FUTSEL_CIM_SCKSEL_SSIF0_WS_SET) & FUTSEL_CIM_SCKSEL_MASK));
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+        }
+        else if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* set output timing clock on other MIX */
+            if (false == p_scux_info_ch->src_cfg.mode_sync)
+            {
+                switch (p_scux_info_ch->src_cfg.output_clk_async)
+                {
+                    case SCUX_CLK_AUDIO_CLK :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                            FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
+                    break;
+
+                    case SCUX_CLK_AUDIO_X1 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                            FUTSEL_CIM_SCKSEL_AUDIO_X1_SET);
+                    break;
+
+                    case SCUX_CLK_MLB_CLK :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                            FUTSEL_CIM_SCKSEL_MLB_CLK_SET);
+                    break;
+
+                    case SCUX_CLK_USB_X1 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                            FUTSEL_CIM_SCKSEL_USB_X1_SET);
+                    break;
+
+                    case SCUX_CLK_CLKP1_2 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                            FUTSEL_CIM_SCKSEL_CLKP1_2_SET);
+                    break;
+
+                    case SCUX_CLK_MTU_TIOC3A :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                            FUTSEL_CIM_SCKSEL_MTUSEL2_SET |
+                                                            FUTSEL_CIM_MTUSEL_SET_TIOC3A);
+                    break;
+
+                    case SCUX_CLK_MTU_TIOC4A :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) |
+                                                            FUTSEL_CIM_SCKSEL_MTUSEL2_SET |
+                                                            FUTSEL_CIM_MTUSEL_SET_TIOC4A);
+                    break;
+
+                    case SCUX_CLK_SSIF0_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF0_WS_SET;
+                    break;
+
+                    case SCUX_CLK_SSIF1_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF1_WS_SET;
+                    break;
+
+                    case SCUX_CLK_SSIF2_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF2_WS_SET;
+                    break;
+
+                    case SCUX_CLK_SSIF3_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF3_WS_SET;
+                    break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                    case SCUX_CLK_SSIF4_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF4_WS_SET;
+                    break;
+
+                    case SCUX_CLK_SSIF5_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF5_WS_SET;
+                    break;
+
+#endif /* mbed */
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+            }
+        }
+        else
+        {
+            /* do nothing for SSIF route */
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSrcClk
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupFifo
+* @brief         SRC FIFO setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* set FFD register */
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = p_scux_info_ch->src_cfg.use_ch;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = SCUX_FIFO_REQ_SIZE_128_32;
+
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+
+        /* set FFU register */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = p_scux_info_ch->src_cfg.use_ch;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = SCUX_FIFO_REQ_SIZE_128_32;
+
+            GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+        }
+
+        p_scux_info_ch->tx_fifo_total_size = 0;
+        p_scux_info_ch->rx_fifo_total_size = 0;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupFifo
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrcFunction
+* @brief         SRC function setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch)
+{
+    float32_t ifs_calc_value;
+    uint32_t ifs_value;
+    uint32_t sadir_value;
+    uint32_t srccr_value = 0;
+    uint32_t bfssr_value;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (false == p_scux_info_ch->src_cfg.src_enable)
+        {
+            /* set bypass mode */
+            if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
+            }
+        }
+        else
+        {
+            /* calculate sampling rate convert rate parameter */
+            ifs_calc_value = ((float32_t)p_scux_info_ch->input_rate / (float32_t)p_scux_info_ch->output_rate);
+            /* ->IPA R2.4.1 float value is intentionall casted to uint32_t value, because it is resigter value. */
+            ifs_value = (uint32_t)(ifs_calc_value * (float32_t)SCUX_RATE_CONVERT_CALC_VALUE);
+            /* <-IPA R2.4.1 */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_16BIT);
+            }
+            else
+            {
+                sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_24BIT);
+            }
+
+            /* setting of sync mode bit */
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                /* set sync mode */
+                srccr_value |= SRCCR_2SRC0_SRCMD_SET;
+            }
+            else
+            {
+                /* set async mode (bit clear) */
+                srccr_value &= ~SRCCR_2SRC0_SRCMD_SET;
+            }
+
+            /* setting of buffer for delay mode */
+            if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* delay normal setting (bit clear) */
+                srccr_value &= ~SRCCR_2SRC0_BUFMD_SET;
+            }
+            else
+            {
+                /* delay setting (bit set) */
+                srccr_value |= SRCCR_2SRC0_BUFMD_SET;
+            }
+
+            /* setting enable bit for wait mode */
+            if ((0U == p_scux_info_ch->src_cfg.wait_sample) || (false != p_scux_info_ch->cancel_operate_flag))
+            {
+                /* clear wait mode enable bit when wait value is 0 or cancel operatin on going */
+                srccr_value &= ~SRCCR_2SRC0_WATMD_SET;
+            }
+            else
+            {
+                /* set wait mode enable bit when wait value is other than 0 */
+                srccr_value |= SRCCR_2SRC0_WATMD_SET;
+            }
+
+            /* setting buffer value for delay mode */
+            if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* set 0 to BFSSR register on delay normal */
+                bfssr_value = 0;
+            }
+            else if (SCUX_DELAY_LOW_DELAY1 == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* set delay mode 1 setting to BFSSR register on delay mode1 */
+                bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 & BFSSR_2SRC0_BUFDATA_MASK) |
+                               (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
+            }
+            else
+            {
+                /* set delay mode 2 setting to BFSSR register on delay mode2 */
+                bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 & BFSSR_2SRC0_BUFDATA_MASK) |
+                               (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
+            }
+
+            /* set register */
+            if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = sadir_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = ifs_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage)
+                                                                         / SCUX_CALC_MINFS_VALUE);
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
+                p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = bfssr_value;
+                if (false != p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set 0 to register compulsorily when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = 0U;
+                }
+                else
+                {
+                    /* set wait value to register when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
+                }
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = sadir_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = ifs_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage)
+                                                                         / SCUX_CALC_MINFS_VALUE);
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
+                p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = bfssr_value;
+                if (false != p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set 0 to register compulsorily when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = 0U;
+                }
+                else
+                {
+                    /* set wait value to register when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSrcFunction
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupDvu
+* @brief         DVU module setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) |
+                                                                   VADIR_DVU0_OTBL_SET_16BIT);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) |
+                                                                   VADIR_DVU0_OTBL_SET_24BIT);
+        }
+
+        if (false == p_scux_info_ch->dvu_cfg.dvu_enable)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 |= DVUBR_DVU0_BYPASS_SET;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 &= ~DVUBR_DVU0_BYPASS_SET;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDvu
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupDvuVolume
+* @brief         DVU volume setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t vrctr_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* init DVU module */
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 &= ~DVUIR_DVU0_INIT_SET;
+        if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
+        {
+            /* set digital volume */
+            SCUX_SetDigiVolRegister(p_scux_info_ch);
+
+            /* dummy setting to volume ramp */
+            for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+            {
+                vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VRMD_SET;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
+
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = 0;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = 0;
+
+            /* set zerocross mute */
+            SCUX_SetZerocrossMuteRegister(p_scux_info_ch);
+
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDvu
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupMix
+* @brief         MIX module setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t scux_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */
+        if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+        {
+            *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = ((uint32_t)p_scux_info_ch->src_cfg.use_ch & MADIR_MIX0_CHNUM_MASK);
+            *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) &= ~MIXIR_MIX0_INIT_SET;
+        }
+
+        for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+        {
+            /* register set on the channel itself which sets up or channel which has already MIX operated */
+            if ((scux_ch == p_scux_info_ch->channel) ||
+                (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
+            {
+                SCUX_SetMixVolRegister(scux_ch);
+            }
+        }
+
+        /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */
+        if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+        {
+            *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+
+            if (false != p_info_drv->shared_info.mixmode_ramp)
+            {
+                /* set ramp mode */
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXMR_MIX0_MIXMODE_SET;
+                *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = (uint32_t)((((uint32_t)p_info_drv->shared_info.up_period << MVPDR_MIX0_MXPDUP_SHIFT) & MVPDR_MIX0_MXPDUP_MASK) |
+                                                              (((uint32_t)p_info_drv->shared_info.down_period << MVPDR_MIX0_MXPDDW_SHIFT) & MVPDR_MIX0_MXPDDW_MASK));
+            }
+            else
+            {
+                /* set step mode */
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) &= ~MIXMR_MIX0_MIXMODE_SET;
+            }
+
+            *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
+        }
+        /* set bit SCUX channel which useing MIX */
+        p_info_drv->shared_info.mix_run_ch |= (1U << p_scux_info_ch->channel);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupMix
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSsif
+* @brief         SSIF module setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_ssif_info_t *p_set_ssif;
+    volatile uint8_t dummy_buf;
+    uint32_t ssif_arrange_num;
+    uint32_t ssicr_value = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
+        {
+            switch (ssif_arrange_num)
+            {
+                case SCUX_SSIF_CH_ARRANGEMENT1:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info1;
+                break;
+
+                case SCUX_SSIF_CH_ARRANGEMENT2:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info2;
+                break;
+
+                case SCUX_SSIF_CH_ARRANGEMENT3:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info3;
+                break;
+
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+
+            /* check wherher SSIF pointer 1, 2, 3 is NULL */
+            if (NULL != p_set_ssif)
+            {
+                /* check SSIF is used on other MIX SCUX channel */
+                if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
+                {
+                    if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch |= (1U << p_set_ssif->ssif_cfg.ssif_ch_num);
+                    }
+
+                    core_util_critical_section_enter();
+
+                    /* input clock */
+                    CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    dummy_buf = CPGSTBCR11;
+
+                    /* SSIF rest */
+                    CPGSWRSTCR1 |= (uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num];
+                    dummy_buf = CPGSWRSTCR1;
+
+                    CPGSWRSTCR1 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    dummy_buf = CPGSWRSTCR1;
+#if(1) /* mbed */
+                    (void)dummy_buf;
+#endif
+
+                    core_util_critical_section_exit();
+
+                    SCUX_SetupSsifGpio(p_set_ssif->ssif_cfg.ssif_ch_num);
+
+                    /* if mode is master mode, WS continue mode is enabled */
+                    if (false != p_set_ssif->ssif_cfg.mode_master)
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_CONT_SET;
+                    }
+                    else
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_CONT_SET;
+                    }
+
+                    /* TDM mode is set according to use_tdm */
+                    if (false != p_set_ssif->ssif_cfg.use_tdm)
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_TDM_SET;
+                    }
+                    else
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_TDM_SET;
+                    }
+
+                    /* over sample clock is set according to select_audio_clk */
+                    /* if select_audio_clk is 0, set AUDIO_X1 */
+                    /* if select_audio_clk is 0, set AUDIO_CLK */
+                    if (false != p_set_ssif->ssif_cfg.select_audio_clk)
+                    {
+                        ssicr_value |= SCUX_SSICR_CKS_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_CKS_SET;
+                    }
+
+                    if (NULL == p_scux_info_ch->p_ssif_info2)
+                    {
+                        /* in case single channel, SSIF channel is set as use_ch kinds */
+                        switch (p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            case SCUX_USE_CH_1:
+                                /* NOTREACHED on At the time of a normal performance */
+                            break;
+
+                            case SCUX_USE_CH_2:
+                                /* if TDM mode is used on audio 2ch , error occured in SCUX_CheckSrcParam */
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
+                            break;
+
+                            case SCUX_USE_CH_4:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_2CH;
+                            break;
+
+                            case SCUX_USE_CH_6:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_3CH;
+                            break;
+
+                            case SCUX_USE_CH_8:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_4CH;
+                            break;
+
+                            default :
+                                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                                /* <-IPA R3.5.2 */
+                                /* NOTREACHED on At the time of a normal performance */
+                            break;
+                        }
+                    }
+                    else
+                    {
+                        /* in case multi channel, SSIF channel is set 1ch compulsorily */
+                        ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
+                    }
+
+                    /* set data word */
+                    if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+                    {
+                        ssicr_value |= SCUX_SSICR_DWL_16BIT_SET;
+                    }
+                    else
+                    {
+                        ssicr_value |= SCUX_SSICR_DWL_24BIT_SET;
+                    }
+
+                    ssicr_value |= ((uint32_t)p_set_ssif->ssif_cfg.system_word << SCUX_SSICR_SWL_SHIFT);
+
+
+                    if (SCUX_PIN_MODE_INDEPEND == p_set_ssif->pin_mode)
+                    {
+                        /* in case pin synchronization is slave, SSIF mode is set mode following mode_master */
+                        if (false != p_set_ssif->ssif_cfg.mode_master)
+                        {
+                            ssicr_value |= (SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                        }
+                        else
+                        {
+                            ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                        }
+                    }
+                    else
+                    {
+                        /* in case pin synchronization is slave, SSIF mode is set slave mode compulsorily */
+                        ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                    }
+
+                    /* set serial bit clock polarity */
+                    if (false != p_set_ssif->ssif_cfg.sck_polarity_rise)
+                    {
+                        ssicr_value |= SCUX_SSICR_SCKP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SCKP_SET;
+                    }
+
+                    /* set WS signal polarity */
+                    if (false != p_set_ssif->ssif_cfg.ws_polarity_high)
+                    {
+                        ssicr_value |= SCUX_SSICR_SWSP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SWSP_SET;
+                    }
+
+                    /* set serial padding polarity */
+                    if (false != p_set_ssif->ssif_cfg.padding_high)
+                    {
+                        ssicr_value |= SCUX_SSICR_SPDP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SPDP_SET;
+                    }
+
+                    /* set serial data align polarity */
+                    if (false != p_set_ssif->ssif_cfg.serial_data_align)
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SDTA_SET;
+                    }
+                    else
+                    {
+                        ssicr_value |= SCUX_SSICR_SDTA_SET;
+                    }
+
+                    /* set WS delay setting */
+                    if (false == p_set_ssif->ssif_cfg.ws_delay)
+                    {
+                        ssicr_value |= SCUX_SSICR_DEL_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_DEL_SET;
+                    }
+
+                    /* set SSIF devide rate */
+                    ssicr_value |= ((uint32_t)p_set_ssif->clk_div << SCUX_SSICR_CKDV_SHIFT);
+
+                    p_set_ssif->p_scux_ssif_reg->SSICR = ssicr_value;
+
+                    /* set noise cancel setting */
+                    if ((false == p_set_ssif->ssif_cfg.mode_master) && (false != p_set_ssif->ssif_cfg.use_noise_cancel))
+                    {
+                        GPIO.SNCR |= (1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    }
+                    else
+                    {
+                        GPIO.SNCR &= ~(1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    }
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSsif
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupDma
+* @brief         DMA setup.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+    AIOCB    *dma_aio;
+    uint32_t dmacr_cim_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        dma_aio = &gb_scux_write_dma_aio[p_scux_info_ch->channel];
+        /* dummy data write start */
+        dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+        dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_DirectTxCallBack;
+        }
+        else
+        {
+            dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyTxCallBack;
+        }
+        p_scux_info_ch->dma_tx_setup.resource = p_scux_info_ch->dma_resource_tx;
+        p_scux_info_ch->dma_tx_setup.direction = DMA_REQ_DES;
+
+        switch (p_scux_info_ch->src_cfg.word_len)
+        {
+            case SCUX_DATA_LEN_16 :
+                /* fall through */
+            case SCUX_DATA_LEN_16_TO_24 :
+                p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_2;
+                p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_2;
+            break;
+
+            case SCUX_DATA_LEN_24 :
+                p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_4;
+                p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_4;
+            break;
+
+            default :
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+
+        p_scux_info_ch->dma_tx_setup.dst_cnt = DMA_ADDR_FIX;
+        p_scux_info_ch->dma_tx_setup.src_cnt = DMA_ADDR_INCREMENT;
+        p_scux_info_ch->dma_tx_setup.p_aio = dma_aio;
+#if(1) /* mbed */
+        p_scux_info_ch->dma_tx_setup.int_level = p_scux_info_ch->int_level;
+#endif
+
+        /* get read DMA channel */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->dma_rx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
+            if (EERROR == p_scux_info_ch->dma_rx_ch)
+            {
+                retval = EMFILE_RBSP;
+            }
+            else
+            {
+                dma_aio = &gb_scux_read_dma_aio[p_scux_info_ch->channel];
+                dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
+                dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyRxCallBack;
+                p_scux_info_ch->dma_rx_setup.resource = p_scux_info_ch->dma_resource_rx;
+                p_scux_info_ch->dma_rx_setup.direction = DMA_REQ_SRC;
+
+                switch (p_scux_info_ch->src_cfg.word_len)
+                {
+                    case SCUX_DATA_LEN_16 :
+                        p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_2;
+                        p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_2;
+                    break;
+
+                    case SCUX_DATA_LEN_24 :
+                        /* fall through */
+                    case SCUX_DATA_LEN_16_TO_24 :
+                        p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_4;
+                        p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_4;
+                    break;
+
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+
+                p_scux_info_ch->dma_rx_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                p_scux_info_ch->dma_rx_setup.src_cnt = DMA_ADDR_FIX;
+                p_scux_info_ch->dma_rx_setup.p_aio = dma_aio;
+#if(1) /* mbed */
+                p_scux_info_ch->dma_rx_setup.int_level = p_scux_info_ch->int_level;
+#endif
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            dmacr_cim_value = *(p_scux_info_ch->p_scux_reg->dmacr_cim);
+            /* set write DMA param */
+            dmacr_cim_value |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+
+            /* set read DMA param */
+            if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                dmacr_cim_value |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) = dmacr_cim_value;
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDma
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_InitHw
+* @brief         Initialize HW .
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_ssif_info_t *p_set_ssif;
+    uint32_t ssif_arrange_num;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* init FFD register */
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+        *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+            p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+            p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+        }
+
+        /* init FFU register */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+            p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+
+            for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
+            {
+                switch (ssif_arrange_num)
+                {
+                    case SCUX_SSIF_CH_ARRANGEMENT1:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info1;
+                    break;
+
+                    case SCUX_SSIF_CH_ARRANGEMENT2:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info2;
+                    break;
+
+                    case SCUX_SSIF_CH_ARRANGEMENT3:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info3;
+                    break;
+
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+
+                if (NULL != p_set_ssif)
+                {
+                    /* check SSIF is used on other MIX SCUX channel */
+                    if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
+                    {
+                        /* init SSIF register */
+                        p_set_ssif->p_scux_ssif_reg->SSICR = SCUX_SSICR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCR = SCUX_SSIFCR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFTDR = SCUX_SSIFTDR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR = SCUX_SSITDMR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCCR = SCUX_SSIFCCR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCMR = SCUX_SSIFCMR_INIT_VALUE;
+                    }
+                }
+            }
+        }
+
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */
+            if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+            {
+                *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InitHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SyncStartHw
+* @brief         Start Hw on sync mode.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
+
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
+
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
+
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SyncStartHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_AsyncStartHw
+* @brief         Start Hw on async mode.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
+
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
+        }
+
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
+
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            SCUX_SetupDvuVolume(p_scux_info_ch);
+
+            if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                SCUX_SetupMix(p_scux_info_ch);
+            }
+        }
+
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
+
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* check used SSIF is only 1 ch */
+            if (NULL == p_scux_info_ch->p_ssif_info2)
+            {
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR |= SCUX_SSICR_TEN_SET;
+            }
+            else
+            {
+                if (SCUX_SSIF_CH_0 == p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  |= SSICTRL_CIM_SSI012TEN_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                }
+#if defined(TARGET_RZA1H) /* mbed */
+                else
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI345TEN_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                }
+#endif /* mbed */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AsyncStartHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SyncStopHw
+* @brief         Stop Hw on sync mode.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET |
+                                                                 UEVMR_FFU0_UEVMOF_SET |
+                                                                 UEVMR_FFU0_UEVMOL_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET |
+                                                                 DEVMR_FFD0_DEVMOF_SET |
+                                                                 DEVMR_FFD0_DEVMOL_SET |
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
+
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+        }
+
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
+
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SyncStopHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_AsyncStopHw
+* @brief         Stop Hw on async mode.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t  scux_check_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    uint32_t  ssipmd_mask_ssif2 = 0;
+    uint32_t  ssipmd_mask_ssif3 = 0;
+    uint32_t  ssipmd_shift_ssif2 = 0;
+    uint32_t  ssipmd_shift_ssif3 = 0;
+    uint32_t  ssipmd_reg;
+    scux_info_ch_t *p_pair_scux_ch;
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET |
+                                                                     UEVMR_FFU0_UEVMOF_SET |
+                                                                     UEVMR_FFU0_UEVMOL_SET);
+            GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+            p_scux_info_ch->futsel_cim_value &= ~FUTSEL_CIM_DIVEN_SET;
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
+        }
+
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
+
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_info_drv->shared_info.mix_run_ch &= ~(1U << p_scux_info_ch->channel);
+        }
+
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                /* do nothing, when mem to mem route is setting */
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;
+
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC1_SSIF345 : 
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI1TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI4TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI2TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI5TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#endif /* mbed */
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+#endif /* mbed */
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* do nothing, when mem to mem route is setting */
+            break;
+        }
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET |
+                                                                 DEVMR_FFD0_DEVMOF_SET |
+                                                                 DEVMR_FFD0_DEVMOL_SET |
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+
+        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) &= ~FDTSEL_CIM_DIVEN_SET;
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
+
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET |
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+        }
+
+        /* if pair channel is stopped, common SRC unit is initialized */
+        if (SCUX_CH_0 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_1);
+        }
+        else if (SCUX_CH_1 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_0);
+        }
+        else if (SCUX_CH_2 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_3);
+        }
+        else
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_2);
+        }
+
+        if (NULL != p_pair_scux_ch)
+        {
+            if ((SCUX_CH_UNINIT == p_pair_scux_ch->ch_stat) ||
+                (SCUX_CH_INIT == p_pair_scux_ch->ch_stat)   ||
+                (SCUX_CH_STOP == p_pair_scux_ch->ch_stat))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
+                GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+            }
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 |= DVUIR_DVU0_INIT_SET;
+
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = 0;
+            GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
+
+            scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info1->scux_channel;
+            scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+            p_scux_info_ch->p_ssif_info1->scux_channel = (int_t)scux_check_ch;
+            if (0 == p_scux_info_ch->p_ssif_info1->scux_channel)
+            {
+                core_util_critical_section_enter();
+
+                /* clock mask on all used SSIF channel shutdown */
+                CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num]);
+
+                core_util_critical_section_exit();
+            }
+
+            if (NULL != p_scux_info_ch->p_ssif_info2)
+            {
+                /* clear multiple SSIF setting */
+                scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info2->scux_channel;
+                scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+                p_scux_info_ch->p_ssif_info2->scux_channel = (int_t)scux_check_ch;
+                p_scux_info_ch->p_ssif_info2->pin_mode = p_scux_info_ch->p_ssif_info2->pin_mode_backup;
+
+                switch (p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num)
+                {
+                    case SCUX_SSIF_CH_1 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI1PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI1PMD_SHIFT;
+                    break;
+
+                    case SCUX_SSIF_CH_2 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI2PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI2PMD_SHIFT;
+                    break;
+
+                    case SCUX_SSIF_CH_3 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI3PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI3PMD_SHIFT;
+                    break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                    case SCUX_SSIF_CH_4 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI4PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI4PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_5 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI5PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI5PMD_SHIFT;
+                    break;
+
+#endif /* mbed */
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+
+                scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info3->scux_channel;
+                scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+                p_scux_info_ch->p_ssif_info3->scux_channel = (int_t)scux_check_ch;
+                p_scux_info_ch->p_ssif_info3->pin_mode = p_scux_info_ch->p_ssif_info3->pin_mode_backup;
+
+                switch (p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num)
+                {
+                    case SCUX_SSIF_CH_1 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI1PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI1PMD_SHIFT;
+                    break;
+
+                    case SCUX_SSIF_CH_2 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI2PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI2PMD_SHIFT;
+                    break;
+
+                    case SCUX_SSIF_CH_3 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI3PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI3PMD_SHIFT;
+                    break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                    case SCUX_SSIF_CH_4 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI4PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI4PMD_SHIFT;
+                    break;
+
+                    case SCUX_SSIF_CH_5 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI5PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI5PMD_SHIFT;
+                    break;
+
+#endif /* mbed */
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                ssipmd_reg = *(p_scux_info_ch->p_scux_reg->ssipmd_cim);
+                ssipmd_reg &= ~(ssipmd_mask_ssif2 | ssipmd_mask_ssif3);
+
+                /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg |
+                                                        ((uint32_t)p_scux_info_ch->p_ssif_info2->pin_mode << ssipmd_shift_ssif2) |
+                                                        ((uint32_t)p_scux_info_ch->p_ssif_info3->pin_mode << ssipmd_shift_ssif3));
+                /* <-IPA R2.4.1 */
+
+                if (0 == p_scux_info_ch->p_ssif_info2->scux_channel)
+                {
+                    core_util_critical_section_enter();
+
+                    /* clock mask */
+                    CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num]);
+
+                    core_util_critical_section_exit();
+                }
+
+                if (0 == p_scux_info_ch->p_ssif_info3->scux_channel)
+                {
+                    core_util_critical_section_enter();
+
+                    CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num]);
+
+                    core_util_critical_section_exit();
+                }
+
+                if (false == p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set NULL to SSIF information when cancel not on going */
+                    p_scux_info_ch->p_ssif_info2 = NULL;
+                    p_scux_info_ch->p_ssif_info3 = NULL;
+                }
+            }
+            if (false == p_scux_info_ch->cancel_operate_flag)
+            {
+                /* set NULL to SSIF information when cancel not on going */
+                p_scux_info_ch->p_ssif_info1 = NULL;
+            }
+
+            if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXIR_MIX0_INIT_SET;
+                    *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AsyncStopHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetDigiVolRegister
+* @brief         Set digital volume register.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        none.
+******************************************************************************/
+
+void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check and set digital volume */
+        if (false != p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VVMD_SET;
+
+            for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+            {
+                switch (audio_ch)
+                {
+                    case SCUX_AUDIO_CH_0 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    case SCUX_AUDIO_CH_1 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    case SCUX_AUDIO_CH_2 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    case SCUX_AUDIO_CH_3 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    case SCUX_AUDIO_CH_4 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    case SCUX_AUDIO_CH_5 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    case SCUX_AUDIO_CH_6 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    case SCUX_AUDIO_CH_7 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+            }
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_VVMD_SET;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetDigiVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetRampVolRegister
+* @brief         Set ramp volume register.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        none.
+******************************************************************************/
+
+void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t vrctr_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch])
+            {
+                vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+            else
+            {
+                vrctr_value &= ~(VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+        }
+
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
+
+        if (false == p_scux_info_ch->restart_ramp_flag)
+        {
+            /* set ramp paramteter to register when timming isn't restart after cancel */
+            /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) |
+                                                                  (((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
+            /* <-IPA R2.4.1 */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time & VRWTR_DVU0_VRWT_MASK);
+        }
+        else
+        {
+            /* set fatest ramp parameter to register when timming is restart after cancel */
+            /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
+            /* when restart ,volume is changed immedeatly */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) |
+                                                                  (((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
+            /* <-IPA R2.4.1 */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0U;
+            p_scux_info_ch->restart_ramp_flag = false;
+        }
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetRampVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetZerocrossMuteRegister
+* @brief         Set zerocross mute register.
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    audio_ch;
+    uint32_t zcmcr_value = 0;
+    uint32_t vevmr_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch])
+            {
+                zcmcr_value |= (ZCMCR_DVU0_ZCEN_SET << audio_ch);
+                vevmr_value |= (VEVMR_DVU0_VEVMZCM_SET << audio_ch);
+            }
+            else
+            {
+                zcmcr_value &= ~(ZCMCR_DVU0_ZCEN_SET << audio_ch);
+                vevmr_value &= ~(VEVMR_DVU0_VEVMZCM_SET << audio_ch);
+            }
+        }
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = zcmcr_value;
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = vevmr_value;
+
+        if (0U != zcmcr_value)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_ZCMD_SET;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_ZCMD_SET;
+        }
+
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetZerocrossMuteRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetMixVolRegister
+* @brief         Set MIX volume register.
+*
+*                Description:<br>
+*
+* @param[in]     channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetMixVolRegister(const int_t channel)
+{
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+        *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = p_info_drv->shared_info.mix_vol[channel];
+        *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetMixVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_RxCallBack
+* @brief         Read request callback (mem to mem).
+*
+*                Description:<br>
+*
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_CopyRxCallBack(union sigval const param)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            p_info_ch->p_rx_aio->aio_return = (ssize_t)p_info_ch->p_rx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+            p_info_ch->first_rx_flag = false;
+        }
+
+        p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+        p_info_ch->dma_rx_current_size = 0;
+        p_info_ch->p_rx_aio = ahf_removehead(&p_info_ch->rx_que);
+
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            /* set nect data read */
+            dma_address_param.src_addr = (void *)p_info_ch->p_scux_reg->dmatu_n_cim;
+            dma_address_param.dst_addr = (void *)(p_info_ch->p_rx_aio->aio_buf);
+            dma_address_param.count = p_info_ch->p_rx_aio->aio_nbytes;
+
+            retval = R_DMA_Start(p_info_ch->dma_rx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_rx_current_size = dma_address_param.count;
+            }
+        }
+        else
+        {
+            switch (p_info_ch->ch_stat)
+            {
+                case SCUX_CH_UNINIT :
+                    /* fall through */
+                case SCUX_CH_INIT :
+                    /* fall through */
+                case SCUX_CH_STOP :
+                    /* fall through */
+                case SCUX_CH_TRANS_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+
+                case SCUX_CH_TRANS_RD :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                break;
+
+                case SCUX_CH_TRANS_WR :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+
+                case SCUX_CH_TRANS_RDWR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                break;
+
+                case SCUX_CH_STOP_WAIT :
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                break;
+
+                case SCUX_CH_STOP_WAIT_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+
+                default :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyRxCallBack
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CommonTxNextDummyData
+* @brief         Set next dummy data for flush (mem to mem , SSIF direct route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+
+        retval = SCUX_FlushWriteStart(p_info_ch);
+        if (ESUCCESS != retval)
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CommonTxNextDummyData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxEndFlush
+* @brief         End of flush operation (mem to mem route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+#if(1) /* mbed */
+    int32_t  dma_ercd;
+#else
+    int_t dma_ercd;
+#endif
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* finish send dummy data process, and SCUX stop process */
+        retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF_RBSP, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF_RBSP != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+
+        retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF_RBSP, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF_RBSP != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+        else
+        {
+            retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+        p_info_ch->dma_rx_current_size = 0;
+
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            /* in case NULL, dummy data read */
+            p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size);
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+        }
+        ahf_cancelall(&p_info_ch->rx_que);
+        p_info_ch->p_rx_aio = NULL;
+
+        SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size);
+
+        if (false != p_info_ch->src_cfg.mode_sync)
+        {
+            SCUX_SyncStopHw(p_info_ch);
+        }
+        else
+        {
+            SCUX_AsyncStopHw(p_info_ch);
+        }
+
+        p_info_ch->ch_stat = SCUX_CH_STOP;
+        if (NULL != p_info_ch->p_flush_callback)
+        {
+            p_info_ch->p_flush_callback(ESUCCESS);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxEndFlush
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxNextRemainData
+* @brief         Set next remain data for flush (mem to mem route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* send remain tx data prcess for flush */
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+        }
+
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+        p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
+
+        if (NULL == p_info_ch->p_tx_aio)
+        {
+            retval = SCUX_FlushWriteStart(p_info_ch);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        else
+        {
+            dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
+            dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
+
+            retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = dma_address_param.count;
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxNextRemainData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxNextData
+* @brief         Set next data for normal operation (mem to mem route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* normal send process */
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+        }
+
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+        p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
+
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
+            dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
+
+            retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = dma_address_param.count;
+            }
+        }
+        else
+        {
+            switch (p_info_ch->ch_stat)
+            {
+                case SCUX_CH_UNINIT :
+                    /* fall through */
+                case SCUX_CH_INIT :
+                    /* fall through */
+                case SCUX_CH_STOP :
+                    /* fall through */
+                case SCUX_CH_TRANS_IDLE :
+                    /* fall through */
+                case SCUX_CH_TRANS_RD :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+
+                case SCUX_CH_TRANS_WR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                break;
+
+                case SCUX_CH_TRANS_RDWR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_RD;
+                break;
+
+                case SCUX_CH_STOP_WAIT :
+                    /* fall through */
+                case SCUX_CH_STOP_WAIT_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxNextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxCallBack
+* @brief         Write request callback (mem to mem route).
+*
+*                Description:<br>
+*
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_CopyTxCallBack(union sigval const param)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            /* data flush process */
+            if (false != p_info_ch->tx_dummy_run_flag)
+            {
+                if (0U == p_info_ch->flush_stop_size)
+                {
+                    SCUX_DMA_CopyTxEndFlush(p_info_ch);
+                }
+                else
+                {
+                    SCUX_DMA_CommonTxNextDummyData(p_info_ch);
+                }
+            }
+            else
+            {
+                SCUX_DMA_CopyTxNextRemainData(p_info_ch);
+            }
+        }
+        else
+        {
+            SCUX_DMA_CopyTxNextData(p_info_ch);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxCallBack
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxEndFlush
+* @brief         End of flush operation (SSIF Direct route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+#if(1) /* mbed */
+    int32_t  dma_ercd;
+#else
+    int_t dma_ercd;
+#endif
+    uint32_t tx_remain_size = 0;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* finish send dummy data process, and SCUX stop process */
+        retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF_RBSP, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF_RBSP != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+
+        SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, 0);
+
+        SCUX_AsyncStopHw(p_info_ch);
+
+        p_info_ch->ch_stat = SCUX_CH_STOP;
+        if (NULL != p_info_ch->p_flush_callback)
+        {
+            p_info_ch->p_flush_callback(ESUCCESS);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxEndFlush
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxNextRemainData
+* @brief         Set next remain data for flush (SSIF Direct route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_next_address_param;
+    int_t retval;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+            p_info_ch->first_tx_flag = false;
+        }
+
+
+        /* send remain tx data prcess for flush */
+        p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
+        p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+
+        if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
+        {
+           /* 1.
+            * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
+            * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
+            * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
+            * p_info_ch->dma_tx_next_size.
+            * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
+            * on Next DMA.
+            */
+            dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
+            dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
+
+            retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+                p_info_ch->dma_tx_next_size = dma_next_address_param.count;
+            }
+        }
+        else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+           /* 2.
+            * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
+            * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
+            * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size
+            * are updated to restart DMA value.
+            */
+            retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        else if ((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 3.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, all request finished, and flush data write start.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to flush DMA value.
+             */
+
+            retval = SCUX_FlushWriteStart(p_info_ch);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        else
+        {
+           /* 4.
+            * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
+            * Since, Nothing new aio request, and processing of 2. or 3. is performed
+            * in the next loop.
+            * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
+            * p_info_ch->dma_tx_next_size.
+            */
+
+            p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+            p_info_ch->dma_tx_next_size = 0;
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxNextRemainData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxNextData
+* @brief         Set next data normal operation (SSIF Direct route).
+*
+*                Description:<br>
+*
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_next_address_param;
+    int_t retval;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+            p_info_ch->first_tx_flag = false;
+        }
+
+        /* normal send process */
+        p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
+
+        if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
+        {
+            /* 1.
+             * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
+.            * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
+             * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
+             * p_info_ch->dma_tx_next_size.
+             * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
+             * on Next DMA.
+             */
+            dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
+            dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
+
+            retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+                p_info_ch->dma_tx_next_size = dma_next_address_param.count;
+            }
+        }
+        else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 2.
+             * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
+             * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size
+             * are updated to restart DMA value.
+             */
+
+            retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        else if((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 3.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, all request finished, and status is made to change IDLE.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to 0.
+             */
+            p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_info_ch->dma_tx_current_size = 0;
+
+        }
+        else
+        {
+            /* 4.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
+             * Since, Nothing new aio request, and processing of 2. or 3. is performed
+             * in the next loop.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to the value of
+             * p_info_ch->dma_tx_next_size.
+             */
+
+            p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+            p_info_ch->dma_tx_next_size = 0;
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxNextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxCallBack
+* @brief         Write request callback (SSIF Direct route).
+*
+*                Description:<br>
+*
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void SCUX_DMA_DirectTxCallBack(union sigval const param)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat)
+        {
+            /* data flush process */
+            if (false != p_info_ch->tx_dummy_run_flag)
+            {
+                if (0U == p_info_ch->flush_stop_size)
+                {
+                    SCUX_DMA_DirectTxEndFlush(p_info_ch);
+                }
+                else
+                {
+                    SCUX_DMA_CommonTxNextDummyData(p_info_ch);
+                }
+            }
+            else
+            {
+                SCUX_DMA_DirectTxNextRemainData(p_info_ch);
+            }
+        }
+        else
+        {
+            SCUX_DMA_DirectTxNextData(p_info_ch);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirextTxCallBack
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux_if.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1817 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_if.c
+* $Rev: $
+* $Date::                           $
+* @brief        SCUX Driver interface functions
+
+*******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include "bsp_util.h"
+#include "mbed_critical.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SCUX_PATH_CH0 "\\0"    /**< channel 0 pathname */
+#define SCUX_PATH_CH1 "\\1"    /**< channel 1 pathname */
+#define SCUX_PATH_CH2 "\\2"    /**< channel 2 pathname */
+#define SCUX_PATH_CH3 "\\3"    /**< channel 3 pathname */
+#define MAX_PATH_SEARCH_LEN (32U)
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+static IOIF_DRV_API gb_ioif_scux_cb_table;
+#endif /* end mbed */
+
+static const char_t* const p_gb_device_name[SCUX_CH_NUM] =
+{
+    SCUX_PATH_CH0,
+    SCUX_PATH_CH1,
+    SCUX_PATH_CH2,
+    SCUX_PATH_CH3
+};
+
+/******************************************************************************
+Private global driver semaphore informationn
+******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+static void *R_SCUX_InitOne(const int_t channel, const void * const p_config_data, int32_t * const p_errno); 
+static int_t R_SCUX_UnInitOne(const int_t channel, const void* const p_driver_instance, int32_t * const p_errno);
+#else
+static void* R_SCUX_Init(void * p_config_data, int32_t * const p_errno);
+static int_t R_SCUX_UnInit(void *p_driver_instance, int32_t * const p_errno);
+#endif /* end mbed */
+static int_t R_SCUX_Open(void * const p_driver_instance, const char_t * p_path_name, const int_t flags, int_t mode, int32_t * const p_errno);
+static int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno);
+static int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno);
+static int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static void  SCUX_SetErrCode(const int_t error_code, int32_t * const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_MakeCbTbl_mbed
+* @brief         Returns the SCUX driver callback function table.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        pointer of sample driver callback table
+******************************************************************************/
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+RBSP_MBED_FNS* R_SCUX_MakeCbTbl_mbed(void)
+/* <-IPA M1.1.1 */
+{
+    static RBSP_MBED_FNS scux_apitbl_mbed;
+
+    scux_apitbl_mbed.initialise_one   = &R_SCUX_InitOne;
+    scux_apitbl_mbed.uninitialise_one = &R_SCUX_UnInitOne;
+    scux_apitbl_mbed.open             = &R_SCUX_Open;
+    scux_apitbl_mbed.close            = &R_SCUX_Close;
+    scux_apitbl_mbed.ioctl            = &R_SCUX_Ioctl;
+    scux_apitbl_mbed.write_a          = &R_SCUX_WriteAsync;
+    scux_apitbl_mbed.read_a           = &R_SCUX_ReadAsync;
+    scux_apitbl_mbed.cancel           = &R_SCUX_Cancel;
+
+    return &scux_apitbl_mbed;
+}
+/******************************************************************************
+End of function R_SCUX_MakeCbTbl_mbed
+******************************************************************************/
+#else
+/**************************************************************************//**
+* Function Name: R_SCUX_MakeCbTbl
+* @brief         Returns the SCUX driver callback function table.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        pointer of sample driver callback table
+******************************************************************************/
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+IOIF_DRV_API* R_SCUX_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    IOIF_DRV_API* const p_api = &gb_ioif_scux_cb_table;
+
+    /* ->MISRA 16.4, IPA M4.5.1 This description is based on the way to fill out OS defined. */
+    p_api->family = IOIF_SERIAL_FAMILY;
+    p_api->fns.serial.initialise   = &R_SCUX_Init;
+    p_api->fns.serial.uninitialise = &R_SCUX_UnInit;
+    p_api->fns.serial.open         = &R_SCUX_Open;
+    p_api->fns.serial.close        = &R_SCUX_Close;
+    p_api->fns.serial.ioctl        = &R_SCUX_Ioctl;
+    p_api->fns.serial.write_a      = &R_SCUX_WriteAsync;
+    p_api->fns.serial.read_a       = &R_SCUX_ReadAsync;
+    p_api->fns.serial.cancel       = &R_SCUX_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+
+    return p_api;
+}
+
+/******************************************************************************
+End of function R_SCUX_MakeCbTbl
+******************************************************************************/
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, nothing is done.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SCUX_SetErrCode(int_t error_code, int32_t * const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function R_SCUX_SetErrCode
+******************************************************************************/
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_InitOne
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*
+* @param[in]     channel    :Initialize channel number.
+* @param[in]     p_config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            ENOMEM_RBSP : Making semaphore failed.
+*                            EBUSY_RBSP  : SCUX driver has been initialized already.
+*                            EFAULT_RBSP : p_config_data is NULL.
+*                            EFAULT_RBSP : Internal error is occured.
+* @retval        other than (-1)
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static void *R_SCUX_InitOne(const int_t channel, const void * const p_config_data, int32_t * const p_errno) 
+{
+    int_t         ercd;
+    void          *ret;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t  * p_info_ch;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else if ((SCUX_CH_0 > channel) || ( SCUX_CH_NUM <= channel))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        p_info_ch = SCUX_GetDrvChInfo(channel);
+
+        if (NULL == p_info_ch)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else if (false != p_info_ch->enabled)
+        {
+            ercd = EBUSY_RBSP;
+        }
+        else
+        {
+            if (NULL == p_config_data)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                /* init SCUX driver */
+                ercd = SCUX_InitializeOne(channel, (const scux_channel_cfg_t *)p_config_data);
+            }
+        }
+    }
+
+    if (ESUCCESS == ercd)
+    {
+        ret = (void *)p_info_drv;
+    }
+    else
+    {
+        ret = (void *)(EERROR);
+    }
+
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+/******************************************************************************
+End of function R_SCUX_InitOne
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_UnInitOne
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :Uninitialize channel number.
+* @param[in]     p_driver_instance :which was returned by R_SCUX_Init
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            EBADF_RBSP : Driver status isn't SCUX_DRV_INIT.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->MISRA 16.7 'p_driver_instance' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+static int_t R_SCUX_UnInitOne(const int_t channel, const void* const p_driver_instance, int32_t * const p_errno)
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t            retval = ESUCCESS;
+    int_t            ercd = ESUCCESS;
+    scux_info_drv_t  * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t   * p_info_ch;
+
+    UNUSED_ARG(p_driver_instance);
+    
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else if ((SCUX_CH_0 > channel) || ( SCUX_CH_NUM <= channel))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EBADF_RBSP;
+        }
+        else
+        {
+            p_info_ch = SCUX_GetDrvChInfo(channel);
+
+            if (NULL == p_info_ch)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else if (false == p_info_ch->enabled)
+            {
+                ercd = EBADF_RBSP;
+            }
+            else
+            {
+                SCUX_UnInitializeOne(channel);
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_UnInitOne
+******************************************************************************/
+#else  /* not mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_Init
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*
+* @param[in]     p_config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            ENOMEM : Making semaphore failed.
+*                            EBUSY  : SCUX driver has been initialized already.
+*                            EFAULT : p_config_data is NULL.
+*                            EFAULT : Internal error is occured.
+* @retval        other than (-1)
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->MISRA 16.7 'p_config_data' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+static void *R_SCUX_Init(void * p_config_data, int32_t * const p_errno)
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t         ercd;
+    void          *ret;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_UNINIT != p_info_drv->drv_stat)
+        {
+            ercd = EBUSY;
+        }
+        else
+        {
+            if (NULL == p_config_data)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                /* init SCUX driver */
+                ercd = SCUX_Initialize((scux_channel_cfg_t *)p_config_data);
+            }
+        }
+    }
+
+    if (ESUCCESS == ercd)
+    {
+        ret = (void *)p_info_drv;
+    }
+    else
+    {
+        ret = (void *)(EERROR);
+    }
+
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+End of function R_SCUX_Init
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_UnInit
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*
+* @param[in]     p_driver_instance :which was returned by R_SCUX_Init
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            EBADF : Driver status isn't SCUX_DRV_INIT.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->MISRA 16.7 'p_driver_instance' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+static int_t R_SCUX_UnInit(void* p_driver_instance, int32_t * const p_errno)
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t            retval = ESUCCESS;
+    int_t            ercd = ESUCCESS;
+    scux_info_drv_t  * const p_info_drv = SCUX_GetDrvInstance();
+
+    UNUSED_ARG(p_driver_instance);
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EBADF;
+        }
+        else
+        {
+            SCUX_UnInitialize();
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+End of function R_SCUX_UnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Open
+* @brief         Open SCUX Channel.
+*
+*                Description:<br>
+*
+* @param[in]     p_driver_instance:which was returned by R_SCUX_Init()
+* @param[in]     p_path_name   :device Name
+* @param[in]     flags         :specifies the access mode whether the channel is
+*                               opened for a read or a write
+* @param[in]     mode          :specifies the permissions to use in case a new file
+*                               is created (not used for serial family driver)
+* @param[in,out] p_errno       :pointer of error code
+*                               error code -
+*                               ENOMEM_RBSP : Craeaton of IOIF queue is failed.
+*                               ENOENT_RBSP : Pathname is incorrect length.
+*                               ENOENT_RBSP : Channel information is NULL.
+*                               EACCES_RBSP : Setting to flag is other than O_WRONLY_RBSP or O_RDWR_RBSP
+*                               EMFILE_RBSP : Allocation of write DMA channel is failed.
+*                               ENOTSUP_RBSP : Channel is not support.
+*                               EFAULT_RBSP : Internal error is occured.
+*
+* @retval        Except ERROR -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->IPA M1.11.1 This description is based on the way to fill out OS defined. */
+static int_t R_SCUX_Open(void * const p_driver_instance, const char_t * p_path_name, const int_t flags, int_t mode , int32_t * const p_errno)
+/* <-IPA M1.11.1 */
+{
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t  sem_wait_ercd;
+    void* p_channel_handle;
+    scux_info_drv_t * const p_info_drv = (scux_info_drv_t *)p_driver_instance;
+    scux_info_ch_t *p_info_ch = NULL;
+    uint32_t open_channel;
+    size_t pathname_len;
+    size_t compare_len;
+
+    UNUSED_ARG(mode);
+
+    /* check driver instance */
+    if (NULL == p_driver_instance)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (NULL == p_info_drv)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    /* check path name */
+    if (ESUCCESS == ercd)
+    {
+        if (NULL == p_info_drv)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (NULL == p_path_name)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                /* check length of path name */
+                pathname_len = SCUX_StrNLen(p_path_name, MAX_PATH_SEARCH_LEN);
+                if ( (0U == pathname_len) || (MAX_PATH_SEARCH_LEN == pathname_len) )
+                {
+                    ercd = ENOENT_RBSP;
+                }
+                else
+                {
+                    for (open_channel = 0; ((open_channel < SCUX_CH_NUM) && (NULL == p_info_ch)); open_channel++)
+                    {
+                        /* Avoid reading beyond the end of the shortest of the two strings */
+                        compare_len = SCUX_StrNLen(p_gb_device_name[open_channel], MAX_PATH_SEARCH_LEN);
+                        if (pathname_len < compare_len)
+                        {
+                            compare_len = pathname_len;
+                        }
+
+                        if (0 == strncmp(p_path_name, p_gb_device_name[open_channel], compare_len))
+                        {
+                            if (NULL != p_info_drv->info_ch)
+                            {
+                                p_info_ch = &p_info_drv->info_ch[open_channel]; /* found a match */
+                            }
+                        }
+                    }
+
+                    if (NULL == p_info_ch)
+                    {
+                        ercd = ENOENT_RBSP; /* Pathname not recognised */
+                    }
+                }
+            }
+        }
+    }
+
+    if (NULL != p_info_ch)
+    {
+        if (ESUCCESS == ercd)
+        {
+            if ((O_WRONLY_RBSP != flags) && (O_RDWR_RBSP != flags))
+            {
+                ercd = EACCES_RBSP;
+            }
+
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+            sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = ENOTSUP_RBSP;
+                }
+
+                if (ESUCCESS == ercd)
+                {
+                    if (SCUX_CH_INIT != p_info_ch->ch_stat)
+                    {
+                        ercd = EBUSY_RBSP;
+                    }
+                }
+
+                if (ESUCCESS == ercd)
+                {
+                    ercd = SCUX_OpenChannel(p_info_ch->channel, flags);
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS == ercd)
+    {
+        p_channel_handle = (void*)p_info_ch;
+    }
+    else
+    {
+        p_channel_handle = (void*)EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return (int_t)p_channel_handle;
+}
+
+/******************************************************************************
+End of function R_SCUX_Open
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Close
+* @brief         Close SCUX Channel.
+*
+*                Description:<br>
+*
+* @param[in]     p_fd:which was returned by R_SCUX_Init()
+* @param[in,out] p_errno:pointer of error code
+*                        error code -
+*                           EFAULT_RBSP : Internal error is occured.
+*
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int32_t sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+            sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_UNINIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_INIT == p_info_ch->ch_stat))
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+
+                if (ESUCCESS == ercd)
+                {
+                    /* close channel */
+                    ercd = SCUX_CloseChannel(p_info_ch->channel);
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                    ercd = EFAULT_RBSP;
+            }
+
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_Close
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ioctl
+* @brief         SCUX driver IOCTL function.
+*
+*                Description:<br>
+*
+* @param[in]     p_fd: pointer of SCUX handler
+* @param[in]     request:IOCTL request code
+* @param[in]     p_buf  :Data buffer for IOCTL request code.
+* @param[in,out] p_errno:pointer of error code
+*                        error code -
+*                           EINVAL_RBSP : IOCTL request code is unexpected value.
+*                           EFAULT_RBSP : Internal error is occured.
+*                           other value : The value depending on IOCTL request code.
+*                                         Refer to the function of scux_ioctl.c for those meanings.
+*
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int32_t sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+            if (0 == R_ExceptionalMode())
+            {
+                sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* <-MISRA 1.2 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set error return value */
+                    ercd = EFAULT_RBSP;
+                }
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_UNINIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_INIT == p_info_ch->ch_stat))
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+
+            }
+
+            if (0 == R_ExceptionalMode())
+            {
+                sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set error return value */
+                    ercd = EFAULT_RBSP;
+                }
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SCUX_IOCTL_SET_START:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+                            }
+                            else
+                            {
+                                ercd = SCUX_IoctlTransStart(p_info_ch->channel);
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_FLUSH_STOP:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            /* check p_Buf */
+                            if (NULL == p_buf)
+                            {
+                                ercd = EFAULT_RBSP;
+                            }
+                            else
+                            {
+                                core_util_critical_section_enter();
+                                if (SCUX_CH_STOP == p_info_ch->ch_stat)
+                                {
+                                    ercd = EBUSY_RBSP;
+                                }
+
+                                /* The mesure to MISRA 1.1 , SEC P1.1.1 */
+                                if (ESUCCESS != ercd)
+                                {
+                                    /* enable all irq when ch_stat is SCUX_CH_STOP */
+                                    core_util_critical_section_exit();
+                                }
+
+                                if (ESUCCESS == ercd)
+                                {
+                                    /* ->MISRA 11.1 Since it is necessary to register a callback function,
+                                    the cast from a void pointer is performed intentionally. */
+                                    ercd = SCUX_IoctlFlushStop(p_info_ch->channel, (void ( *)(int_t))p_buf);
+                                    /* <-MISRA 11.1 */
+                                }
+
+                            }
+                        }
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_CLEAR_STOP:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            core_util_critical_section_enter();
+                            if (SCUX_CH_STOP == p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+
+                                core_util_critical_section_exit();
+                            }
+                            else
+                            {
+                                /* This exclusive access control ends in the SCUX_IoctlClearStop */
+                                ercd = SCUX_IoctlClearStop(p_info_ch->channel);
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_ROUTE:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT_RBSP;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetRoute(p_info_ch->channel, *(scux_route_t *)p_buf);
+                                }
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_PIN_CLK:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT_RBSP;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetPinClk(p_info_ch->channel, (scux_ssif_pin_clk_t *)p_buf);
+                                }
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_PIN_MODE:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT_RBSP;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetPinMode(p_info_ch->channel, (scux_ssif_pin_mode_t *)p_buf);
+                                }
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_SRC_CFG:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT_RBSP;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetSrcCfg(p_info_ch->channel, (scux_src_cfg_t *)p_buf);
+                                }
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_DVU_CFG:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT_RBSP;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetDvuCfg(p_info_ch->channel, (scux_dvu_cfg_t *)p_buf);
+                                }
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_DVU_DIGI_VOL:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuDigiVol(p_info_ch->channel, (scux_dvu_digi_vol_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_DVU_RAMP_VOL:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuRampVol(p_info_ch->channel, (scux_dvu_ramp_vol_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_ZEROCROSS_MUTE:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuZerocrossMute(p_info_ch->channel, (scux_zc_mute_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_STOP_MUTE:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetStopMute(p_info_ch->channel, *(uint32_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_MIX_CFG:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetMixCfg((scux_mix_cfg_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_MIX_VOL:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetMixVol(p_info_ch->channel, *(uint32_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_SET_SSIF_CFG:
+
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                        sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY_RBSP;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT_RBSP;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetSsifCfg((scux_ssif_cfg_t *)p_buf);
+                                }
+                            }
+                        }
+
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT_RBSP;
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_GET_WRITE_STAT:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetWriteStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_GET_READ_STAT:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetReadStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_GET_DVU_STAT:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetDvuStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_GET_MUTE_STAT:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetMuteStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+
+                    break;
+
+                    case SCUX_IOCTL_GET_MIX_STAT:
+
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetMixStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+
+                    break;
+
+                    default:
+                        ercd = EINVAL_RBSP;
+                    break;
+                }
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Ioctl
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_WriteAsync
+* @brief         SCUX driver asynchronous write.
+*
+*                Description:<br>
+*
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_Open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EBADF_RBSP : Channel status isn't SCUX_CH_STOP or SCUX_CH_STOP_WAIT.
+*                               EINVAL_RBSP : p_fd is NULL.
+*                               EINVAL_RBSP : write size is 0.
+*                               EFAULT_RBSP : Internal error is occured.
+*
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int_t sem_ercd;
+    int32_t  sem_wait_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_ch) || (NULL == p_aio) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (0U == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+            sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                core_util_critical_section_enter();
+
+                if (ESUCCESS != p_info_ch->err_stat_backup)
+                {
+                    /* set error code */
+                    ercd = p_info_ch->err_stat_backup;
+                }
+                else
+                {
+                    switch (p_info_ch->ch_stat)
+                    {
+                        case SCUX_CH_UNINIT :
+                            /* fall through */
+                        case SCUX_CH_INIT :
+                            ercd = EFAULT_RBSP;
+                        break;
+
+                        case SCUX_CH_STOP :
+                            ercd = EBADF_RBSP;
+                        break;
+
+                        case SCUX_CH_TRANS_IDLE :
+                            /* fall through */
+                        case SCUX_CH_TRANS_RD :
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectWriteStart(p_info_ch, p_aio);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyWriteStart(p_info_ch, p_aio);
+                            }
+                        break;
+
+                        case SCUX_CH_TRANS_WR :
+                            /* fall through */
+                        case SCUX_CH_TRANS_RDWR :
+                            ahf_addtail(&p_info_ch->tx_que, p_aio);
+                        break;
+
+                        case SCUX_CH_STOP_WAIT :
+                            /* fall through */
+                        case SCUX_CH_STOP_WAIT_IDLE :
+                            ercd = EBADF_RBSP;
+                        break;
+
+                        default :
+                            ercd = EFAULT_RBSP;
+                        break;
+                    }
+                }
+
+                core_util_critical_section_exit();
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+
+}
+
+/******************************************************************************
+End of function R_SCUX_WriteAsync
+******************************************************************************/
+/**************************************************************************//**
+* Function Name: R_SCUX_ReadAsync
+* @brief         SCUX driver asynchronous read.
+*
+*                Description:<br>
+*
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EBADF_RBSP : Channel status isn't SCUX_CH_STOP or SCUX_CH_STOP_WAIT.
+*                               EINVAL_RBSP : read size is 0.
+*                               EACCES_RBSP : Request for write only mode channel.
+*                               EACCES_RBSP : Route setting is unexpected.
+*                               EFAULT_RBSP : Internal error is occured.
+*
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t sem_wait_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_ch) || (NULL == p_info_drv) || (NULL == p_aio))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (0U == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+            sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                if (O_WRONLY_RBSP == (p_info_ch->open_flags & O_ACCMODE_RBSP))
+                {
+                    ercd = EACCES_RBSP;
+                }
+            }
+
+            if (ESUCCESS == ercd)
+            {
+
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    ercd = EACCES_RBSP;
+                }
+
+                if (ESUCCESS == ercd)
+                {
+                    core_util_critical_section_enter();
+
+                    if (ESUCCESS != p_info_ch->err_stat_backup)
+                    {
+                        /* set error code */
+                        ercd = p_info_ch->err_stat_backup;
+                    }
+                    else
+                    {
+                        switch (p_info_ch->ch_stat)
+                        {
+                            case SCUX_CH_UNINIT :
+                                /* fall through */
+                            case SCUX_CH_INIT :
+                                ercd = EFAULT_RBSP;
+                            break;
+
+                            case SCUX_CH_STOP :
+                                ercd = EBADF_RBSP;
+                            break;
+
+                            case SCUX_CH_TRANS_IDLE :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;
+
+                            case SCUX_CH_TRANS_RD :
+                                ahf_addtail(&p_info_ch->rx_que, p_aio);
+                            break;
+
+                            case SCUX_CH_TRANS_WR :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;
+
+                            case SCUX_CH_TRANS_RDWR :
+                                /* fall through */
+                            case SCUX_CH_STOP_WAIT :
+                                ahf_addtail(&p_info_ch->rx_que, p_aio);
+                            break;
+
+                            case SCUX_CH_STOP_WAIT_IDLE :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;
+
+                            default :
+                                ercd = EFAULT_RBSP;
+                            break;
+                        }
+                    }
+
+                    core_util_critical_section_exit();
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+
+}
+
+/******************************************************************************
+End of function R_SCUX_ReadAsync
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Cancel
+* @brief         Request cancel.
+*
+*                Description:<br>
+*
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EFAULT_RBSP : Internal error is occured.
+*
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t sem_wait_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+            sem_wait_ercd = osSemaphoreAcquire(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_INIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_UNINIT == p_info_ch->ch_stat))
+                    {
+                        /* It should not becomde status */
+                        ercd = EFAULT_RBSP;
+                    }
+                    else if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) ||
+                              (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat) ||
+                              (SCUX_CH_STOP == p_info_ch->ch_stat))
+                    {
+                        /* busy error on flush waiting */
+                        ercd = EBADF_RBSP;
+                    }
+                    else
+                    {
+                        if (NULL == p_aio)
+                        {
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectCancelAll(p_info_ch);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyCancelAll(p_info_ch);
+                            }
+                        }
+                        else
+                        {
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectCancelSpecific(p_info_ch, p_aio);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyCancelSpecific(p_info_ch, p_aio);
+                            }
+                        }
+                    }
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_Cancel
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux_int.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,888 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_int.c
+* $Rev: $
+* $Date::                           $
+* @brief        SCUX Driver interrupt functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "scux.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void R_SCUX_Fdi0InterruptHandler(void);
+static void R_SCUX_Fdi1InterruptHandler(void);
+static void R_SCUX_Fdi2InterruptHandler(void);
+static void R_SCUX_Fdi3InterruptHandler(void);
+static void R_SCUX_FdiHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Fui0InterruptHandler(void);
+static void R_SCUX_Fui1InterruptHandler(void);
+static void R_SCUX_Fui2InterruptHandler(void);
+static void R_SCUX_Fui3InterruptHandler(void);
+static void R_SCUX_FuiHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Dvi0InterruptHandler(void);
+static void R_SCUX_Dvi1InterruptHandler(void);
+static void R_SCUX_Dvi2InterruptHandler(void);
+static void R_SCUX_Dvi3InterruptHandler(void);
+static void R_SCUX_DviHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Ai0InterruptHandler(void);
+static void R_SCUX_Ai1InterruptHandler(void);
+static void R_SCUX_AiHandlerProcess(const uint32_t src_channel);
+
+static void R_SCUX_ErrHandlerProcess(scux_info_ch_t * const p_scux_info_ch, const int_t ercd);
+
+/**************************************************************************//**
+* Function Name: SCUX_InterruptInit
+* @brief         Initialize SCUX interrupts.
+*
+*                Description:<br>
+*
+* @param[in] channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_InterruptInit(const int_t channel)
+{
+    uint32_t int_type;
+    uint32_t ercd;
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+
+    /* interrupt information table define */
+    static const scux_info_int_t scux_int_info[SCUX_CH_NUM][SCUX_INT_MAX] =
+    {
+        {                                                                 /* ch0 */
+            {&R_SCUX_Fdi0InterruptHandler, SCUFDI0_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui0InterruptHandler, SCUFUI0_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi0InterruptHandler, SCUDVI0_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai0InterruptHandler,  SCUAI0_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch1 */
+            {&R_SCUX_Fdi1InterruptHandler, SCUFDI1_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui1InterruptHandler, SCUFUI1_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi1InterruptHandler, SCUDVI1_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai0InterruptHandler,  SCUAI0_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch2 */
+            {&R_SCUX_Fdi2InterruptHandler, SCUFDI2_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui2InterruptHandler, SCUFUI2_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi2InterruptHandler, SCUDVI2_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai1InterruptHandler,  SCUAI1_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch3 */
+            {&R_SCUX_Fdi3InterruptHandler, SCUFDI3_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui3InterruptHandler, SCUFUI3_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi3InterruptHandler, SCUDVI3_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai1InterruptHandler,  SCUAI1_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        }
+    };
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (int_type = SCUX_INT_FDI; int_type < SCUX_INT_MAX; int_type++)
+        {
+            ercd = InterruptHandlerRegister(scux_int_info[channel][int_type].int_num,
+                                     scux_int_info[channel][int_type].int_handler
+                                     );
+
+            if (0U != ercd)
+            {
+                /* NON_NOTICE_ASSERT: interrupt handler regist error */
+            }
+
+            /* set interrupt level (1-N model) */
+            GIC_SetConfiguration(scux_int_info[channel][int_type].int_num, 1);
+
+            /* set interrupt priority */
+            GIC_SetPriority(scux_int_info[channel][int_type].int_num, p_scux_info_ch->int_level);
+
+            /* get interrupt number */
+            p_scux_info_ch->int_num[int_type] = scux_int_info[channel][int_type].int_num;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InterrptInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_InterruptUntinit
+* @brief         Uninitialize SCUX interrupts.
+*
+*                Description:<br>
+*
+* @param[in/out] channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_InterruptUninit(const int_t channel)
+{
+    uint32_t int_type;
+    uint32_t ercd;
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (int_type = SCUX_INT_FDI; int_type < SCUX_INT_MAX; int_type++)
+        {
+            GIC_DisableIRQ(p_scux_info_ch->int_num[int_type]);
+            ercd = InterruptHandlerUnregister(p_scux_info_ch->int_num[int_type]);
+
+            if (0U != ercd)
+            {
+                /* NON_NOTICE_ASSERT: interrupt handler unregist error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InterruptUnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi0InterruptHandler
+* @brief         FDI interrupt handler on channel 0.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi0InterruptHandler(void)
+{
+
+    R_SCUX_FdiHandlerProcess(SCUX_CH_0);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi1InterruptHandler
+* @brief         FDI interrupt handler on channel 1.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi1InterruptHandler(void)
+{
+
+    R_SCUX_FdiHandlerProcess(SCUX_CH_1);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi2InterruptHandler
+* @brief         FDI interrupt handler on channel 2.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi2InterruptHandler(void)
+{
+
+    R_SCUX_FdiHandlerProcess(SCUX_CH_2);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi3InterruptHandler
+* @brief         FDI interrupt handler on channel 3.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi3InterruptHandler(void)
+{
+
+    R_SCUX_FdiHandlerProcess(SCUX_CH_3);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_FdiHandlerProcess
+* @brief         Processing FDI interrupt handler.
+*
+*                Description:<br>
+*
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_FdiHandlerProcess(const scux_ch_num_t channel)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+    int_t ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check error type */
+        if ((p_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 & DEVCR_FFD0_DEVCOL_MASK) != 0)
+        {
+            /* critical error (over lap) */
+            ercd = EIO_RBSP;
+        }
+        else
+        {
+            /* be returned error (FFD under flow, over flow) */
+            ercd = EOVERFLOW_RBSP;
+        }
+
+        p_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 &= ~(DEVCR_FFD0_DEVCUF_SET |
+                                                            DEVCR_FFD0_DEVCOF_SET |
+                                                            DEVCR_FFD0_DEVCOL_SET |
+                                                            DEVCR_FFD0_DEVCIUF_SET);
+
+        R_SCUX_ErrHandlerProcess(p_info_ch, ercd);
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_FdiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui0InterruptHandler
+* @brief         FUI interrupt handler on channel 0.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui0InterruptHandler(void)
+{
+
+    R_SCUX_FuiHandlerProcess(SCUX_CH_0);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui1InterruptHandler
+* @brief         FUI interrupt handler on channel 1.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui1InterruptHandler(void)
+{
+
+    R_SCUX_FuiHandlerProcess(SCUX_CH_1);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui2InterruptHandler
+* @brief         FUI interrupt handler on channel 2.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui2InterruptHandler(void)
+{
+
+    R_SCUX_FuiHandlerProcess(SCUX_CH_2);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui3InterruptHandler
+* @brief         FUI interrupt handler on channel 3.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui3InterruptHandler(void)
+{
+
+    R_SCUX_FuiHandlerProcess(SCUX_CH_3);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_FuiHandlerProcess
+* @brief         Processing FUI interrupt handler.
+*
+*                Description:<br>
+*
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_FuiHandlerProcess(const scux_ch_num_t channel)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+    int_t ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check error type */
+        if ((p_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 & UEVCR_FFU0_UEVCOL_MASK) != 0)
+        {
+            /* critical error (over lap) */
+            ercd = EIO_RBSP;
+        }
+        else
+        {
+            /* be returned error (FFU under flow, over flow) */
+            ercd = EOVERFLOW_RBSP;
+        }
+
+        p_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 &= ~(UEVCR_FFU0_UEVCUF_SET |
+                                                            UEVCR_FFU0_UEVCOF_SET |
+                                                            UEVCR_FFU0_UEVCOL_SET);
+
+        R_SCUX_ErrHandlerProcess(p_info_ch, ercd);
+
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_FuiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi0InterruptHandler
+* @brief         DVI interrupt handler on channel 0.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi0InterruptHandler(void)
+{
+
+    R_SCUX_DviHandlerProcess(SCUX_CH_0);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi1InterruptHandler
+* @brief         DVI interrupt handler on channel 1.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi1InterruptHandler(void)
+{
+
+    R_SCUX_DviHandlerProcess(SCUX_CH_1);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi2InterruptHandler
+* @brief         DVI interrupt handler on channel 2.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi2InterruptHandler(void)
+{
+
+    R_SCUX_DviHandlerProcess(SCUX_CH_2);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi3InterruptHandler
+* @brief         DVI interrupt handler on channel 3.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi3InterruptHandler(void)
+{
+
+    R_SCUX_DviHandlerProcess(SCUX_CH_3);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_DviHandlerProcess
+* @brief         Processing DVI interrupt handler.
+*
+*                Description:<br>
+*
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_DviHandlerProcess(const scux_ch_num_t channel)
+{
+    uint32_t stat_zerocross;
+    int_t    ch_zerocross;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        stat_zerocross = p_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0;
+
+        for (ch_zerocross = 0; ch_zerocross <= p_info_ch->src_cfg.use_ch; ch_zerocross++)
+        {
+            /* check zerocross bit */
+            if (0U != (stat_zerocross & (VEVCR_DVU0_VEVCZCM_SET << ch_zerocross)))
+            {
+                p_info_ch->dvu_mute_stat |= (1U << ch_zerocross);
+                if (NULL != p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[ch_zerocross])
+                {
+                    /* callback function */
+                    p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[ch_zerocross]();
+                }
+            }
+            p_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 &= ~stat_zerocross;
+        }
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_DviHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ai0InterruptHandler
+* @brief         AI interrupt handler on channel 0.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Ai0InterruptHandler(void)
+{
+
+    R_SCUX_AiHandlerProcess(SRC_MOD_SRC0);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Ai0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ai1InterruptHandler
+* @brief         AI interrupt handler on channel 1.
+*
+*                Description:<br>
+*
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Ai1InterruptHandler(void)
+{
+
+    R_SCUX_AiHandlerProcess(SRC_MOD_SRC1);
+
+}
+
+/******************************************************************************
+End of function R_SCUX_Ai1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_AiHandlerProcess
+* @brief         Processing AI interrupt handler.
+*
+*                Description:<br>
+*
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_AiHandlerProcess(const uint32_t src_channel)
+{
+    scux_info_ch_t *p_info_ch_check;
+    scux_info_ch_t *p_info_ch;
+
+    if (SRC_MOD_SRC0 == src_channel)
+    {
+        p_info_ch_check = SCUX_GetDrvChInfo(SCUX_CH_0);
+        if (NULL == p_info_ch_check)
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0)
+            {
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_0);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET |
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW_RBSP);
+                }
+            }
+
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0)
+            {
+
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_1);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET |
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW_RBSP);
+                }
+            }
+        }
+    }
+    else
+    {
+        p_info_ch_check = SCUX_GetDrvChInfo(SCUX_CH_2);
+        if (NULL == p_info_ch_check)
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0)
+            {
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_2);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET |
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW_RBSP);
+                }
+            }
+
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0)
+            {
+
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_3);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET |
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW_RBSP);
+                }
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function R_SCUX_AiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_ErrHandlerProcess
+* @brief         Error processing on interrupt handler.
+*
+*                Description:<br>
+*
+* @param[in] p_scux_info_ch:SCUX channel information.
+* @param[in] ercd:return error code.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_ErrHandlerProcess(scux_info_ch_t * const p_scux_info_ch, const int_t ercd)
+{
+    int_t retval;
+#if(1) /* mbed */
+    int32_t dma_retval;
+#else
+    int_t dma_retval;
+#endif
+    scux_stat_ch_t old_stat;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_retval);
+        /* DMA stop check, (when dma_retval is EBADF_RBSP, DMA stopped already) */
+        if ((ESUCCESS != retval) && (EBADF_RBSP != dma_retval))
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+        }
+
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_retval);
+
+            /* DMA stop check, (when dma_retval is EBADF_RBSP, DMA stopped already) */
+            if ((ESUCCESS != retval) && (EBADF_RBSP != dma_retval))
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size;
+                p_scux_info_ch->dma_rx_current_size = 0;
+            }
+
+            retval = R_DMA_Free(p_scux_info_ch->dma_rx_ch, NULL);
+
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+
+        SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size);
+        /* stop HW */
+        if (false != p_scux_info_ch->src_cfg.mode_sync)
+        {
+            SCUX_SyncStopHw(p_scux_info_ch);
+        }
+        else
+        {
+            SCUX_AsyncStopHw(p_scux_info_ch);
+        }
+
+        if (false == p_scux_info_ch->first_tx_flag)
+        {
+            /* return callback on normal operation */
+            if (NULL != p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                if (NULL == p_scux_info_ch->p_tx_aio)
+                {
+                    p_scux_info_ch->p_tx_next_aio->aio_return = ercd;
+                }
+                else
+                {
+                    p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED_RBSP;
+                }
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+        }
+        else
+        {
+            /* return callback on first operation */
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                p_scux_info_ch->p_tx_next_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            else
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+        }
+
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* if request is nothing, aio is NULL */
+            if (NULL != p_scux_info_ch->p_rx_aio)
+            {
+                p_scux_info_ch->p_rx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->rx_que);
+            p_scux_info_ch->p_rx_aio = NULL;
+        }
+        old_stat = p_scux_info_ch->ch_stat;
+        p_scux_info_ch->ch_stat = SCUX_CH_STOP;
+        if ((SCUX_CH_STOP_WAIT == old_stat) || (SCUX_CH_STOP_WAIT_IDLE == old_stat))
+        {
+            if (NULL != p_scux_info_ch->p_flush_callback)
+            {
+                p_scux_info_ch->p_flush_callback(ercd);
+            }
+        }
+
+        /* set error status */
+        p_scux_info_ch->err_stat_backup = ercd;
+    }
+}
+
+/******************************************************************************
+End of function R_SCUX_ErrHandlerProcess
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux_int.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,83 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux_int.h
+* $Rev: $
+* $Date::                           $
+* @brief         SCUX driver interrupt header
+******************************************************************************/
+
+#ifndef SCUX_INT_H
+#define SCUX_INT_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "scux.h"
+#include "cmsis.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* Interrupt types */
+typedef enum
+{
+    SCUX_INT_FDI  = 0,   /* FDI interrupt */
+    SCUX_INT_FUI  = 1,   /* FUI interrupt */
+    SCUX_INT_DVI  = 2,   /* DVI interrupt */
+    SCUX_INT_AI   = 3,   /* AI interrupt */
+    SCUX_INT_MAX  = 4
+} scux_int_type_t;
+
+/* Interrupt level */
+typedef enum
+{
+    SCUX_INT_LEVEL = 0,   /* Level interrupt */
+    SCUX_INT_EDGE  = 1    /* Edge interrupt */
+} scux_int_leve_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+/* Table Information of Interrupt */
+typedef struct
+{
+    IRQHandler       int_handler;          /* Interrupt handler */
+    IRQn_Type        int_num;              /* Interrupt number */
+    scux_int_leve_t  info_level;           /* Edge or level  */
+} scux_info_int_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+void SCUX_InterruptInit(const int_t channel);
+void SCUX_InterruptUninit(const int_t channel);
+
+#endif /* SCUX_INT_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux_ioctl.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2513 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_ioctl.c
+* $Rev: $
+* $Date::                           $
+* @brief        SCUX Driver ioctl functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include "bsp_util.h"
+#include  "mbed_critical.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlTransStart
+* @brief         SCUX transfer start.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     p_scux_addr_param:address parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EACCES_RBSP : DVU setup isn't carried out when using DVU.
+*                EACCES_RBSP : MIX setup isn't carried out when using MIX.
+*                EACCES_RBSP : SSIF setup isn't carried out when using SSIF.
+*                EACCES_RBSP : SSIF channel is already used.
+*                EACCES_RBSP : When use MIX, it is a setup which does not agree in a route setup.
+*                EBUSY_RBSP : It has already transmitted.
+*                EMFILE_RBSP : Allocate DMA ch for read is failed.
+*                EPERM_RBSP : Transfer parameter is unexpected.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_IoctlTransStart(const int_t channel)
+{
+    int32_t          sem_wait_ercd;
+    int_t            retval = ESUCCESS;
+    uint32_t         ssif_sem_ch = 0;
+    int_t            ssif_ch;
+    osStatus         sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_ssif_info_t  * p_ssif_ch_num[SCUX_SSIF_CH_NUM];
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    /* for processing for the measure against MISRA R1.1 and IPA R3.2.2 */
+    for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++)
+    {
+        p_ssif_ch_num[ssif_ch] = SCUX_GetSsifChInfo(ssif_ch);
+    }
+    if ((NULL == p_info_drv) || (NULL == p_info_ch))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* check using MIX route */
+        if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+            sem_wait_ercd = osSemaphoreAcquire(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT_RBSP;
+            }
+        }
+
+        if ((SCUX_ROUTE_SSIF == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) ||
+            (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)))
+        {
+            /* check using SSIF route */
+            /* mode is async mode only when SSIF direvct route */
+            p_info_ch->src_cfg.mode_sync = false;
+            switch (p_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+#endif /* mbed */
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+#endif /* mbed */
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            retval = SCUX_CheckParam(p_info_ch);
+
+            if (ESUCCESS == retval)
+            {
+                core_util_critical_section_enter();
+                SCUX_InitHw(p_info_ch);
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    SCUX_SetupSsif(p_info_ch);
+                }
+
+                SCUX_SetupSrc(p_info_ch);
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    SCUX_SetupDvu(p_info_ch);
+                }
+
+                retval = SCUX_SetupDma(p_info_ch);
+
+                if (ESUCCESS == retval)
+                {
+                    if (false != p_info_ch->src_cfg.mode_sync)
+                    {
+                        SCUX_SyncStartHw(p_info_ch);
+                    }
+                    else
+                    {
+                        SCUX_AsyncStartHw(p_info_ch);
+                    }
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                    p_info_ch->p_flush_callback = NULL;
+
+                    p_info_ch->dma_tx_current_size = 0;
+                    p_info_ch->dma_rx_current_size = 0;
+                    p_info_ch->tx_fifo_total_size = 0;
+                    p_info_ch->rx_fifo_total_size = 0;
+
+                    p_info_ch->p_tx_aio = NULL;
+                    p_info_ch->p_rx_aio = NULL;
+                    p_info_ch->p_tx_next_aio = NULL;
+                    p_info_ch->p_rx_next_aio = NULL;
+                    p_info_ch->dvu_mute_stat = 0;
+                    p_info_ch->first_ramp_flag = false;
+                    p_info_ch->cancel_operate_flag = false;
+                    p_info_ch->restart_ramp_flag = false;
+                    p_info_ch->err_stat_backup = ESUCCESS;
+                }
+
+                core_util_critical_section_exit();
+            }
+        }
+
+        for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++)
+        {
+            if (0U != (ssif_sem_ch & (1U << ssif_ch)))
+            {
+                p_ssif_ch = p_ssif_ch_num[ssif_ch];
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT_RBSP;
+                    p_info_ch->ch_stat = SCUX_CH_STOP;
+                }
+            }
+        }
+
+        /* check using MIX route */
+        if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT_RBSP;
+                p_info_ch->ch_stat = SCUX_CH_STOP;
+            }
+        }
+    }
+
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_IoctlTransStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlFlushStop
+* @brief         Set flush stop paramter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     (*callback)(void):callback function pointer.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t))
+{
+    int_t retval = ESUCCESS;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* mem to mem route */
+            if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat))
+            {
+                /* Flush process is performed only when dummy buffer transmission has not been started yet */
+                if (false == p_info_ch->tx_dummy_run_flag)
+                {
+                    /* start flush write */
+                    retval = SCUX_FlushWriteStart(p_info_ch);
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    /* memory to memory route */
+                    if (SCUX_CH_TRANS_RD == p_info_ch->ch_stat)
+                    {
+                        p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    }
+                    else
+                    {
+                        p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                    }
+                    p_info_ch->p_flush_callback = callback;
+                }
+            }
+            else
+            {
+                /* on going write process */
+                /* status is SCUX_CH_TRANS_WR, SCUX_CH_TRANS_RDWR, SCUX_CH_STOP_WAIT, SCUX_CH_STOP_WAIT_IDLE */
+                if (SCUX_CH_TRANS_RDWR == p_info_ch->ch_stat)
+                {
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                }
+                if (SCUX_CH_TRANS_WR == p_info_ch->ch_stat)
+                {
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                }
+
+                p_info_ch->p_flush_callback = callback;
+            }
+        }
+        else
+        {
+            /* SSIF direct route */
+            if (SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat)
+            {
+                /* Flush process is performed only when dummy buffer transmission has not been started yet */
+                if (false == p_info_ch->tx_dummy_run_flag)
+                {
+                    /* start flush write */
+                    retval = SCUX_FlushWriteStart(p_info_ch);
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    /* memory to memory route */
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    p_info_ch->p_flush_callback = callback;
+                }
+            }
+            else
+            {
+                /* on going write process */
+                p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                p_info_ch->p_flush_callback = callback;
+
+            }
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlFlushStop
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlClearStop
+* @brief         Set flush stop paramter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlClearStop(const int_t channel)
+{
+    int_t retval = ESUCCESS;
+#if(1) /* mbed */
+    int32_t dma_ercd;
+#else
+    int_t dma_ercd;
+#endif
+    int_t dma_retval;
+    scux_stat_ch_t old_stat;
+    uint32_t rx_remain_size = 0;
+    uint32_t tx_remain_size = 0;
+
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT_RBSP;
+        core_util_critical_section_exit();
+    }
+    else
+    {
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* memory to memory route */
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF_RBSP, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF_RBSP != dma_ercd))
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+                p_info_ch->dma_tx_current_size = 0;
+            }
+
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF_RBSP, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF_RBSP != dma_ercd))
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+                p_info_ch->dma_rx_current_size = 0;
+
+                dma_retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL);
+                if (ESUCCESS != dma_retval)
+                {
+                    retval = EFAULT_RBSP;
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* return write request */
+                if (NULL !=  p_info_ch->p_tx_aio)
+                {
+                    p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                    ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                }
+
+                /* return read request */
+                if (NULL != p_info_ch->p_rx_aio)
+                {
+                    p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size);
+                    ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+                }
+
+                ahf_cancelall(&p_info_ch->tx_que);
+                ahf_cancelall(&p_info_ch->rx_que);
+
+                p_info_ch->p_tx_aio = NULL;
+                p_info_ch->p_rx_aio = NULL;
+            }
+        }
+        else
+        {
+            /* SSIF direct route */
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF_RBSP, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF_RBSP != dma_ercd))
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+                p_info_ch->dma_tx_current_size = 0;
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* return the request after 2nd */
+                if (false == p_info_ch->first_tx_flag)
+                {
+                    /* return current aio request */
+                    if (NULL !=  p_info_ch->p_tx_aio)
+                    {
+                        p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                    }
+                    /* return next aio request */
+                    if (NULL != p_info_ch->p_tx_next_aio)
+                    {
+                        p_info_ch->p_tx_next_aio->aio_return = ECANCELED_RBSP;
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                    }
+                }
+                else
+                {
+                    /* return the 1st request  */
+                    if (NULL == p_info_ch->p_tx_aio)
+                    {
+                        /* return the first half part of a 1st request */
+                        if (NULL != p_info_ch->p_tx_next_aio)
+                        {
+                            p_info_ch->p_tx_next_aio->aio_return
+                            = (ssize_t)((p_info_ch->p_tx_next_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE) - tx_remain_size);
+                            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                        }
+                    }
+                    else
+                    {
+                        /* return the second half part of a 1st request */
+                        p_info_ch->p_tx_aio->aio_return
+                        = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+
+                        /* in case of the next request is acquired */
+                        if (NULL != p_info_ch->p_tx_next_aio)
+                        {
+                            p_info_ch->p_tx_next_aio->aio_return = ECANCELED_RBSP;
+                            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                        }
+                    }
+                }
+                ahf_cancelall(&p_info_ch->tx_que);
+
+                p_info_ch->p_tx_aio = NULL;
+                p_info_ch->p_tx_next_aio = NULL;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size);
+            if (false != p_info_ch->src_cfg.mode_sync)
+            {
+                SCUX_SyncStopHw(p_info_ch);
+            }
+            else
+            {
+                SCUX_AsyncStopHw(p_info_ch);
+            }
+
+            old_stat = p_info_ch->ch_stat;
+            p_info_ch->ch_stat = SCUX_CH_STOP;
+
+            core_util_critical_section_exit();
+
+            if ((SCUX_CH_STOP_WAIT == old_stat) || (SCUX_CH_STOP_WAIT_IDLE == old_stat))
+            {
+                p_info_ch->p_flush_callback(ECANCELED_RBSP);
+                p_info_ch->p_flush_callback = NULL;
+            }
+        }
+        else
+        {
+            core_util_critical_section_exit();
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlClearStop
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetRoute
+* @brief         Set SCUX data transfer route.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     route:route parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->route_set = route;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetRoute
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetPinClk
+* @brief         Set clock source for AUDIO_CLK pin.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_pin_clk_param:clock source parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM_RBSP:Parameter is unexpected value.
+*                EFAULT_RBSP:Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param)
+{
+    int_t retval = ESUCCESS;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_clk_param))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* check SSIF channel number */
+        if (SCUX_SSIF_CH_NUM > p_pin_clk_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_clk_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT_RBSP;
+                }
+                else
+                {
+                    /* check clock source parameter */
+                    if ((SCUX_CLK_AUDIO_CLK == p_pin_clk_param->pin_clk) || (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk))
+                    {
+                        p_ssif_ch->pin_clk = p_pin_clk_param->pin_clk;
+                    }
+                    else
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                }
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT_RBSP;
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        if (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk)
+                        {
+                            /* set MLB_CLK */
+                            *(p_info_ch->p_scux_reg->ssipmd_cim) |= (SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num);
+                        }
+                        else
+                        {
+                            /* set AUDIO_CLK */
+                            *(p_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num);
+                        }
+                    }
+
+                    sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM_RBSP;
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetPinClk
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetPinMode
+* @brief         Set synchronous setting for each SSIP pin.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_pin_mode_param:synchronous setting parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM_RBSP:Parameter is unexpected value.
+*                EFAUT:Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param)
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssipmd_reg;
+    uint32_t ssipmd_mask = 0;
+    uint32_t ssipmd_shift = 0;
+    osStatus sem_ercd;
+    int32_t  sem_wait_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_mode_param))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* check SSIF channel number (disable setting for SSIF0) */
+        if (SCUX_SSIF_CH_NUM > p_pin_mode_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_mode_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT_RBSP;
+                }
+                else
+                {
+                    /* check clock source parameter */
+                    if ((SCUX_PIN_MODE_MIN < p_pin_mode_param->pin_mode) || (SCUX_PIN_MODE_MAX > p_pin_mode_param->pin_mode))
+                    {
+                        p_ssif_ch->pin_mode = p_pin_mode_param->pin_mode;
+                    }
+                    else
+                    {
+                        retval = EPERM_RBSP;
+                    }
+                }
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT_RBSP;
+                }
+
+                if (ESUCCESS == retval)
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                    sem_wait_ercd = osSemaphoreAcquire(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                    else
+                    {
+                        /* pin_mode setup to SSIF0 does not exist */
+                        if (SCUX_SSIF_CH_0 != p_pin_mode_param->ssif_ch_num)
+                        {
+                            switch (p_pin_mode_param->ssif_ch_num)
+                            {
+                                case SCUX_SSIF_CH_1 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI1PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI1PMD_SHIFT;
+                                break;
+
+                                case SCUX_SSIF_CH_2 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI2PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI2PMD_SHIFT;
+                                break;
+
+                                case SCUX_SSIF_CH_3 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI3PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI3PMD_SHIFT;
+                                break;
+
+#if defined(TARGET_RZA1H) /* mbed */
+                                case SCUX_SSIF_CH_4 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI4PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI4PMD_SHIFT;
+                                break;
+
+                                case SCUX_SSIF_CH_5 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI5PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI5PMD_SHIFT;
+                                break;
+
+#endif /* mbed */
+                                default :
+                                    /* SCUX channel is 6 oe more */
+                                    retval = EPERM_RBSP;
+                                break;
+                            }
+
+                            if (ESUCCESS == retval)
+                            {
+                                ssipmd_reg = *(p_info_ch->p_scux_reg->ssipmd_cim);
+                                ssipmd_reg &= ~ssipmd_mask;
+
+                                /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */
+                                *(p_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg | ((uint32_t)p_pin_mode_param->pin_mode << ssipmd_shift));
+                                /* <-IPA R2.4.1 */
+                            }
+                        }
+                    }
+
+                    sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM_RBSP;
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetPinMode
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetSrcCfg
+* @brief         Set SRC paramter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_src_param:SRC parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param)
+{
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_src_param))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->src_cfg.src_enable = p_src_param->src_enable;
+        p_info_ch->src_cfg.use_ch = p_src_param->use_ch;
+        p_info_ch->src_cfg.word_len = p_src_param->word_len;
+        p_info_ch->src_cfg.mode_sync = p_src_param->mode_sync;
+        p_info_ch->src_cfg.input_rate_sync = p_src_param->input_rate_sync;
+        p_info_ch->src_cfg.input_clk_async = p_src_param->input_clk_async;
+        p_info_ch->src_cfg.input_div_async = p_src_param->input_div_async;
+        p_info_ch->src_cfg.output_rate_sync = p_src_param->output_rate_sync;
+        p_info_ch->src_cfg.output_clk_async = p_src_param->output_clk_async;
+        p_info_ch->src_cfg.output_div_async = p_src_param->output_div_async;
+        p_info_ch->src_cfg.delay_mode = p_src_param->delay_mode;
+        p_info_ch->src_cfg.wait_sample = p_src_param->wait_sample;
+        p_info_ch->src_cfg.min_rate_percentage = p_src_param->min_rate_percentage;
+        p_info_ch->src_cfg.output_ws = p_src_param->output_ws;
+        p_info_ch->src_cfg.input_ws = p_src_param->input_ws;
+        p_info_ch->src_cfg.freq_tioc3a = p_src_param->freq_tioc3a;
+        p_info_ch->src_cfg.freq_tioc4a = p_src_param->freq_tioc4a;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->src_cfg.select_in_data_ch[audio_ch] = p_src_param->select_in_data_ch[audio_ch];
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetSrcCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuCfg
+* @brief         Set DVU parameter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:DVU parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param)
+{
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_dvu_param))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->dvu_cfg.dvu_enable = p_dvu_param->dvu_enable;
+
+        /* digital volume setting */
+        p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_dvu_param->dvu_digi_vol.digi_vol_enable;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_dvu_param->dvu_digi_vol.digi_vol[audio_ch];
+        }
+
+        /* ramp volume setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_dvu_param->dvu_ramp_vol.ramp_vol_enable[audio_ch];
+        }
+        p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_dvu_param->dvu_ramp_vol.up_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_dvu_param->dvu_ramp_vol.down_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_dvu_param->dvu_ramp_vol.ramp_vol;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_dvu_param->dvu_ramp_vol.ramp_wait_time;
+
+        /* zerocross mute setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch] = p_dvu_param->dvu_zc_mute.zc_mute_enable[audio_ch];
+            p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_dvu_param->dvu_zc_mute.pcallback[audio_ch];
+        }
+
+        p_info_ch->dvu_setup = true;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuDigiVol
+* @brief         Set Digital volume parameter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:Digital volume parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM_RBSP:Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param)
+{
+    int_t retval = ESUCCESS;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_digi_vol_param))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* digital volume setting */
+        p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_digi_vol_param->digi_vol_enable;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_digi_vol_param->digi_vol[audio_ch];
+        }
+
+        /* check digital volume */
+#if(1) /* mbed */
+        for (audio_ch = SCUX_AUDIO_CH_0; ((ESUCCESS == retval) && ((int)audio_ch < (int)p_info_ch->src_cfg.use_ch)); audio_ch++)
+#else
+        for (audio_ch = SCUX_AUDIO_CH_0; ((ESUCCESS == retval) && (audio_ch < p_info_ch->src_cfg.use_ch)); audio_ch++)
+#endif
+        {
+            if (SCUX_MAX_DIGITAL_VOLUME < p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            core_util_critical_section_enter();
+
+            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+            {
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+
+                /* set parameter for register */
+                SCUX_SetDigiVolRegister(p_info_ch);
+
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            }
+
+            core_util_critical_section_exit();
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuDigiVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuRampVol
+* @brief         Set Digital volume parameter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:Digital volume parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM_RBSP:Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param)
+{
+    int_t retval = ESUCCESS;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_ramp_vol_param))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ramp volume setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_ramp_vol_param->ramp_vol_enable[audio_ch];
+        }
+        p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_ramp_vol_param->up_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_ramp_vol_param->down_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_ramp_vol_param->ramp_vol;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_ramp_vol_param->ramp_wait_time;
+
+        /* check ramp volume */
+        /* check ramp down period */
+        if ((p_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
+            (p_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
+        {
+               retval = EPERM_RBSP;
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check ramp up period */
+            if ((p_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
+                (p_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* check ramp volume */
+            if (SCUX_MAX_RAMP_VOLUME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS != retval)
+        {
+            /* check wait time */
+            if (SCUX_MAX_WAIT_TIME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
+            {
+                retval = EPERM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            core_util_critical_section_enter();
+
+            if ((SCUX_CH_STOP != p_info_ch->ch_stat) && (false != p_info_ch->first_ramp_flag))
+            {
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+
+                /* set parameter for register */
+                SCUX_SetRampVolRegister(p_info_ch);
+
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            }
+
+            /* an updating setting is used when a seting is updated before the first request is going */
+            p_info_ch->restart_ramp_flag = false;
+
+            core_util_critical_section_exit();
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuRampVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuZerocrossMute
+* @brief         Set zerocross mute parameter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_zc_mute_param:zerocross mute parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM_RBSP:Parameter is unexpected value.
+*                EPERM_RBSP:Rewrite callback pointer while waiting zerocross.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param)
+{
+    int_t retval = ESUCCESS;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_zc_mute_param))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* set zerocross mute paramter */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch]= p_zc_mute_param->zc_mute_enable[audio_ch];
+            p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_zc_mute_param->pcallback[audio_ch];
+        }
+
+        core_util_critical_section_enter();
+
+        if (SCUX_CH_STOP != p_info_ch->ch_stat)
+        {
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+
+            /* set parameter for register */
+            SCUX_SetZerocrossMuteRegister(p_info_ch);
+
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuZerocrossMute
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetStopMute
+* @brief         Stop mute.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     audio_channel:Audio channel number.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM_RBSP:Parameter is unexpected value.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel)
+{
+    int_t retval = ESUCCESS;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (audio_channel >= (uint32_t)p_info_ch->src_cfg.use_ch)
+        {
+            retval = EPERM_RBSP;
+        }
+
+        if (ESUCCESS == retval)
+        {
+            core_util_critical_section_enter();
+
+            p_info_ch->dvu_mute_stat &= ~(1U << audio_channel);
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_channel] = false;
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+            p_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 &= ~(ZCMCR_DVU0_ZCEN_SET << audio_channel);
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+
+            core_util_critical_section_exit();
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetStopMute
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetMixCfg
+* @brief         Set MIX parameter.
+*
+*                Description:<br>
+*
+* @param[in]     *p_mix_param:MIX parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EPERM_RBSP : Transfer parameter is unexpected.
+*                EFAULT_RBSP : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param)
+{
+    int_t retval = ESUCCESS;
+    int_t scux_ch;
+    int_t audio_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if ((NULL == p_info_drv) || (NULL == p_mix_param))
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        core_util_critical_section_enter();
+
+        p_info_drv->shared_info.mixmode_ramp = p_mix_param->mixmode_ramp;
+        p_info_drv->shared_info.up_period = p_mix_param->up_period;
+        p_info_drv->shared_info.down_period = p_mix_param->down_period;
+        for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+        {
+            p_info_drv->shared_info.mix_vol[scux_ch] = p_mix_param->mix_vol[scux_ch];
+        }
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_drv->shared_info.select_out_data_ch[audio_ch] = p_mix_param->select_out_data_ch[audio_ch];
+        }
+
+        for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (scux_ch < SCUX_CH_NUM)); scux_ch++)
+        {
+            /* check going channel number */
+            if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch)))
+            {
+                /* check ramp volume */
+                if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
+                {
+                    retval = EPERM_RBSP;
+                }
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+            {
+                /* check going channel number */
+                if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch)))
+                {
+                    /* set parameter for register */
+                    SCUX_SetMixVolRegister(scux_ch);
+                }
+            }
+
+            p_info_drv->shared_info.mix_setup = true;
+        }
+        else
+        {
+            p_info_drv->shared_info.mix_setup = false;
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetMixVol
+* @brief         Set MIX volume.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     mix_vol:MIX volume.
+* @retval        ESUCCESS : Operation successful.
+*                EPERM_RBSP : Transfer parameter is unexpected.
+*                EFAULT_RBSP: Internel error si occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol)
+{
+    int_t retval = ESUCCESS;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if (NULL == p_info_drv)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+        if (0 == R_ExceptionalMode())
+        {
+            sem_wait_ercd = osSemaphoreAcquire(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT_RBSP;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            p_info_drv->shared_info.mix_vol[channel] = mix_vol;
+
+            core_util_critical_section_enter();
+
+            /* check going channel number */
+            if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << channel)))
+            {
+                /* check ramp volume */
+                if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[channel])
+                {
+                    retval = EPERM_RBSP;
+                }
+                else
+                {
+                    /* set parameter for register */
+                    SCUX_SetMixVolRegister(channel);
+                }
+            }
+
+            core_util_critical_section_exit();
+        }
+
+        if (0 == R_ExceptionalMode())
+        {
+            sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT_RBSP;
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetSsifCfg
+* @brief         Set SSIF parameter.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     p_ssif_param:SSIF parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EBADF_RBSP : SSIF channel has already used on other SCUX channel.
+*                EPERM_RBSP : Transfer parameter is unexpected.
+*                EFAULT_RBSP: Internel error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t * const p_ssif_param)
+{
+    int_t retval = ESUCCESS;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+
+    if (NULL == p_ssif_param)
+    {
+        retval = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SCUX_SSIF_CH_NUM > p_ssif_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_ssif_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT_RBSP;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/
+                sem_wait_ercd = osSemaphoreAcquire(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT_RBSP;
+                }
+                else
+                {
+                    if (0 != p_ssif_ch->scux_channel)
+                    {
+                        retval = EBADF_RBSP;
+                    }
+                    else
+                    {
+                        p_ssif_ch->ssif_cfg.ssif_ch_num = p_ssif_param->ssif_ch_num;
+                        p_ssif_ch->ssif_cfg.mode_master = p_ssif_param->mode_master;
+                        p_ssif_ch->ssif_cfg.select_audio_clk = p_ssif_param->select_audio_clk;
+                        p_ssif_ch->ssif_cfg.system_word = p_ssif_param->system_word;
+                        p_ssif_ch->ssif_cfg.sck_polarity_rise = p_ssif_param->sck_polarity_rise;
+                        p_ssif_ch->ssif_cfg.ws_polarity_high = p_ssif_param->ws_polarity_high;
+                        p_ssif_ch->ssif_cfg.padding_high = p_ssif_param->padding_high;
+                        p_ssif_ch->ssif_cfg.serial_data_align = p_ssif_param->serial_data_align;
+                        p_ssif_ch->ssif_cfg.ws_delay = p_ssif_param->ws_delay;
+                        p_ssif_ch->ssif_cfg.use_noise_cancel = p_ssif_param->use_noise_cancel;
+                        p_ssif_ch->ssif_cfg.use_tdm = p_ssif_param->use_tdm;
+                        p_ssif_ch->ssif_setup = true;
+                    }
+                }
+
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT_RBSP;
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM_RBSP;
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetWriteStat
+* @brief         Get write request status.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_write_stat:Write request status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_write_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        core_util_critical_section_enter();
+
+        if ((SCUX_CH_STOP == p_info_ch->ch_stat) ||
+            (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) ||
+            (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            *p_write_stat = SCUX_STAT_STOP;
+        }
+        else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat))
+        {
+            *p_write_stat = SCUX_STAT_IDLE;
+        }
+        else
+        {
+            *p_write_stat = SCUX_STAT_TRANS;
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetWriteStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetReadStat
+* @brief         Get read request status.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_read_stat:Read request status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    core_util_critical_section_enter();
+
+    if ((NULL == p_info_ch) || (NULL == p_read_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_CH_STOP == p_info_ch->ch_stat)
+        {
+            *p_read_stat = SCUX_STAT_STOP;
+        }
+        else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) ||
+                 (SCUX_CH_TRANS_WR == p_info_ch->ch_stat) ||
+                 (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            *p_read_stat = SCUX_STAT_IDLE;
+        }
+        else
+        {
+            *p_read_stat = SCUX_STAT_TRANS;
+        }
+
+        core_util_critical_section_exit();
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetReadStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetDvuStat
+* @brief         Get DVU status.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_stat:DVU status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_dvu_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *p_dvu_stat = (p_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetDvuStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetMuteStat
+* @brief         Get MUTE status.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_mute_stat:MUTE status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_mute_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        core_util_critical_section_enter();
+
+        *p_mute_stat = p_info_ch->dvu_mute_stat;
+
+        core_util_critical_section_exit();
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetMuteStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetMixStat
+* @brief         Get MIX status.
+*
+*                Description:<br>
+*
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_mix_stat:MIX status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_ch) || (NULL == p_mix_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *p_mix_stat = (*(p_info_ch->p_scux_reg->mixsr_mix0_0) & MIXSR_MIX0_MIXSTS_MASK);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetMixStat
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/scux/scux_ver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         scux_ver.c
+* $Rev: $
+* $Date::                           $
+* @brief        SCUX Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "scux_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define SCUX_DRV_VER_MAJOR  (2u)
+#define SCUX_DRV_VER_MINOR  (2u)
+
+#define SCUX_DRV_VER_MASK   (0xFFu)
+#define SCUX_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_GetVersion
+* @brief         Get SCUX driver version.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SCUX_GetVersion(void)
+{
+    const uint16_t version =
+        ((SCUX_DRV_VER_MAJOR & SCUX_DRV_VER_MASK) << SCUX_DRV_VER_SHIFT)
+        | (SCUX_DRV_VER_MINOR & SCUX_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SCUX_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1495 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "cmsis.h"
+#include "mbed_critical.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+/* ->MISRA 8.8, MISRA 8.10, IPA M2.2.2 : These declare statements are dependent on CMSIS-RTOS */
+osSemaphoreDef(ssif_ch0_access);
+osSemaphoreDef(ssif_ch1_access);
+osSemaphoreDef(ssif_ch2_access);
+osSemaphoreDef(ssif_ch3_access);
+#if defined(TARGET_RZA1H) /* mbed */
+osSemaphoreDef(ssif_ch4_access);
+osSemaphoreDef(ssif_ch5_access);
+#endif /* mbed */
+/* <-MISRA 8.8, MISRA 8.10, IPA M2.2.2 */
+
+#if(1) /* mbed */
+static ssif_info_drv_t g_ssif_info_drv;
+
+ssif_info_drv_t * SSIF_GetDrvInstanc(void) {
+    return &g_ssif_info_drv;
+}
+#else
+ssif_info_drv_t g_ssif_info_drv;
+#endif
+
+volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS] = SSIF_ADDRESS_LIST;
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch);
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch);
+static void SSIF_Reset(const uint32_t ssif_ch);
+
+static const uint32_t gb_cpg_stbcr_bit[SSIF_NUM_CHANS] =
+{
+    CPG_STBCR11_BIT_MSTP115,    /* SSIF0 */
+    CPG_STBCR11_BIT_MSTP114,    /* SSIF1 */
+    CPG_STBCR11_BIT_MSTP113,    /* SSIF2 */
+    CPG_STBCR11_BIT_MSTP112,    /* SSIF3 */
+#if defined(TARGET_RZA1H) /* mbed */
+    CPG_STBCR11_BIT_MSTP111,    /* SSIF4 */
+    CPG_STBCR11_BIT_MSTP110     /* SSIF5 */
+#endif /* mbed */
+};
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: SSIF_InitialiseOne
+* @brief         Initialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     channel    :channel number
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data)
+{
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else if (false == p_cfg_data->enabled)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[channel];
+        p_info_ch->channel = channel;
+        p_info_ch->enabled = p_cfg_data->enabled;
+
+        /* copy config data to channel info */
+        ercd = SSIF_UpdateChannelConfig(p_info_ch, p_cfg_data);
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_InitChannel(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            SSIF_InterruptInit(channel, p_cfg_data->int_level);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitialiseOne
+* @brief         UnInitialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     channel    :channel number
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SSIF_UnInitialiseOne(const int_t channel)
+{
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    p_info_ch = &g_ssif_info_drv.info_ch[channel];
+
+    if (false != p_info_ch->enabled)
+    {
+        SSIF_UnInitChannel(p_info_ch);
+    }
+
+    return ercd;
+}
+
+#endif /* end mbed */
+/******************************************************************************
+* Function Name: SSIF_Initialise
+* @brief         Initialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data)
+{
+    uint32_t        ssif_ch;
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        for (ssif_ch = 0; (ssif_ch < SSIF_NUM_CHANS) && (ESUCCESS == ercd); ssif_ch++)
+        {
+            p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+            p_info_ch->channel = ssif_ch;
+            p_info_ch->enabled = p_cfg_data[ssif_ch].enabled;
+
+            if (false != p_info_ch->enabled)
+            {
+                /* copy config data to channel info */
+                ercd = SSIF_UpdateChannelConfig(p_info_ch, &p_cfg_data[ssif_ch]);
+
+                if (ESUCCESS == ercd)
+                {
+                    ercd = SSIF_InitChannel(p_info_ch);
+                }
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+            {
+                p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+                if (false != p_info_ch->enabled)
+                {
+                    SSIF_InterruptInit(ssif_ch, p_cfg_data[ssif_ch].int_level);
+                }
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitialise
+* @brief         UnInitialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SSIF_UnInitialise(void)
+{
+    uint32_t        ssif_ch;
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+        if (false != p_info_ch->enabled)
+        {
+            SSIF_UnInitChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_EnableChannel
+* @brief         Enable the SSIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    uint32_t ssif_ch;
+    volatile uint8_t dummy_buf;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            /* check channel open flag(duplex) */
+            if ((O_RDWR_RBSP == p_info_ch->openflag)
+                && (false == p_info_ch->is_full_duplex))
+            {
+                ercd = EINVAL_RBSP;
+            }
+
+#if defined(TARGET_RZA1H) /* mbed */
+            /* check channel open flag(romdec direct input) */
+            if (ESUCCESS == ercd)
+            {
+                if ((O_RDONLY_RBSP != p_info_ch->openflag)
+                    && (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                        == p_info_ch->romdec_direct.mode))
+                {
+                    ercd = EINVAL_RBSP;
+                }
+            }
+
+#endif /* mbed */
+            /* enable the SSIF clock */
+            if (ESUCCESS == ercd)
+            {
+                core_util_critical_section_enter();
+
+                /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+                CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_stbcr_bit[ssif_ch]);
+                /* <-IPA R2.4.2 */
+                dummy_buf = CPGSTBCR11;
+#if(1) /* mbed */
+                (void)dummy_buf;
+#endif
+
+                core_util_critical_section_exit();
+            }
+
+            /* configure channel hardware */
+            if (ESUCCESS == ercd)
+            {
+                /* software reset */
+                SSIF_Reset(ssif_ch);
+
+                /* Set control parameters */
+                ercd = SSIF_SetCtrlParams(p_info_ch);
+            }
+
+            /* allocate and setup/start DMA transfer */
+            if (ESUCCESS == ercd)
+            {
+                ercd = SSIF_InitDMA(p_info_ch);
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableChannel
+* @brief         Disable the SSIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   ret = ESUCCESS;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ret = EFAULT_RBSP;
+        }
+        else
+        {
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* free DMA resources */
+            SSIF_UnInitDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */
+
+            /* disable ssif clock */
+            core_util_critical_section_enter();
+
+            /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+            CPGSTBCR11 |= (uint8_t)gb_cpg_stbcr_bit[ssif_ch];
+            /* <-IPA R2.4.2 */
+
+            core_util_critical_section_exit();
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_curr->aio_return = ECANCELED;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_next->aio_return = ECANCELED_RBSP;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_curr->aio_return = ECANCELED;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_next->aio_return = ECANCELED;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ErrorRecovery
+* @brief         Restart the SSIF channel
+*
+*                Description:<br>
+*                When normal mode<br>
+*                  Stop and restart DMA transfer.<br>
+*                When ROMDEC direct input mode<br>
+*                  Stop DMA transfer, and execute callback function.<br>
+*                Note: This function execute in interrupt context.
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+void SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   ercd = ESUCCESS;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            /* disable DMA end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR &= ~((uint32_t)SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE);
+
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* pause DMA transfer */
+            SSIF_CancelDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_curr->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_next->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_curr->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_next->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+
+        /* configure channel hardware */
+        if (ESUCCESS == ercd)
+        {
+            /* software reset */
+            SSIF_Reset(ssif_ch);
+
+            /* Set control parameters */
+            ercd = SSIF_SetCtrlParams(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+#if defined(TARGET_RZA1H) /* mbed */
+            if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                != p_info_ch->romdec_direct.mode)
+            {
+                /* setup/restart DMA transfer */
+                ercd = SSIF_RestartDMA(p_info_ch);
+            }
+            else
+            {
+                /* execute callback function */
+                if (NULL != p_info_ch->romdec_direct.p_cbfunc)
+                {
+                    (*p_info_ch->romdec_direct.p_cbfunc)();
+                }
+            }
+#else /* mbed */
+            /* setup/restart DMA transfer */
+            ercd = SSIF_RestartDMA(p_info_ch);
+#endif /* mbed */
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        /* NON_NOTICE_ASSERT: cannot restart channel */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncIo
+* @brief         Enqueue asynchronous read/write request
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block of read/write request
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (SSIF_ASYNC_W == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->tx_que, p_aio);
+        }
+        else if (SSIF_ASYNC_R == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->rx_que, p_aio);
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: illegal request type */
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncCancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block to cancel or NULL to cancel all.
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    int32_t ioif_ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (NULL == p_aio)
+        {
+            ahf_cancelall(&p_info_ch->tx_que);
+            ahf_cancelall(&p_info_ch->rx_que);
+        }
+        else
+        {
+            ioif_ret = ahf_cancel(&p_info_ch->tx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+
+            ioif_ret = ahf_cancel(&p_info_ch->rx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_ConfigChannel
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                                const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t    ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* stop DMA transfer */
+        ercd = SSIF_DisableChannel(p_info_ch);
+
+        if (ESUCCESS == ercd)
+        {
+            /* copy config data to channel info */
+            ercd = SSIF_UpdateChannelConfig(p_info_ch, p_ch_cfg);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* restart DMA transfer */
+            ercd = SSIF_EnableChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_GetStatus
+* @brief         Get a value of SSISR register.
+*
+*                Description:<br>
+*
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status)
+{
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_status))
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        *p_status = g_ssireg[p_info_ch->channel]->SSISR;
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(bits)
+******************************************************************************/
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_swl[SSIF_CFG_SYSTEM_WORD_256+1] = {
+        8,      /* SSIF_CFG_SYSTEM_WORD_8   */
+        16,     /* SSIF_CFG_SYSTEM_WORD_16  */
+        24,     /* SSIF_CFG_SYSTEM_WORD_24  */
+        32,     /* SSIF_CFG_SYSTEM_WORD_32  */
+        48,     /* SSIF_CFG_SYSTEM_WORD_48  */
+        64,     /* SSIF_CFG_SYSTEM_WORD_64  */
+        128,    /* SSIF_CFG_SYSTEM_WORD_128 */
+        256     /* SSIF_CFG_SYSTEM_WORD_256 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_swl[ssicr_swl];
+}
+
+/******************************************************************************
+* Function Name: SSIF_DWLtoLen
+* @brief         Convert SSICR:DWL bits to data word length
+*
+*                Description:<br>
+*
+* @param[in]     ssicr_dwl  :SSICR register DWL field value(0 to 6)
+* @retval        8 to 32    :data word length(bits)
+******************************************************************************/
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_dwl[SSIF_CFG_DATA_WORD_32+1] = {
+        8,   /* SSIF_CFG_DATA_WORD_8  */
+        16,  /* SSIF_CFG_DATA_WORD_16 */
+        18,  /* SSIF_CFG_DATA_WORD_18 */
+        20,  /* SSIF_CFG_DATA_WORD_20 */
+        22,  /* SSIF_CFG_DATA_WORD_22 */
+        24,  /* SSIF_CFG_DATA_WORD_24 */
+        32   /* SSIF_CFG_DATA_WORD_32 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_dwl[ssicr_dwl];
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_InitChannel
+* @brief         Initialize for the SSIF channel
+*
+*                Description:<br>
+*                Create semaphore and queue for channel.<br>
+*                And setup SSIF pin.
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    uint32_t ssif_ch;
+    int_t ercd = ESUCCESS;
+    static const osSemaphoreAttr_t* semdef_access[SSIF_NUM_CHANS] =
+    {
+        osSemaphore(ssif_ch0_access),
+        osSemaphore(ssif_ch1_access),
+        osSemaphore(ssif_ch2_access),
+        osSemaphore(ssif_ch3_access),
+#if defined(TARGET_RZA1H) /* mbed */
+        osSemaphore(ssif_ch4_access),
+        osSemaphore(ssif_ch5_access)
+#endif /* mbed */
+    };
+    static const bool_t is_duplex_ch[SSIF_NUM_CHANS] =
+    {
+        true,   /* SSIF0 is full duplex channel */
+        true,   /* SSIF1 is full duplex channel */
+        false,  /* SSIF2 is half duplex channel */
+        true,   /* SSIF3 is full duplex channel */
+#if defined(TARGET_RZA1H) /* mbed */
+        false,  /* SSIF4 is half duplex channel */
+        true    /* SSIF5 is full duplex channel */
+#endif /* mbed */
+    };
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        p_info_ch->is_full_duplex = is_duplex_ch[ssif_ch];
+
+        /* Create sem_access semaphore */
+        p_info_ch->sem_access = osSemaphoreNew(0xffff, 1, semdef_access[ssif_ch]);
+
+        if (NULL == p_info_ch->sem_access)
+        {
+            ercd = ENOMEM_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->tx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->rx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* set channel initialize */
+            p_info_ch->openflag = 0;
+
+            p_info_ch->p_aio_tx_curr = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_tx_next = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_rx_curr = NULL;       /* rx request pointer */
+            p_info_ch->p_aio_rx_next = NULL;       /* rx request pointer */
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = R_SSIF_Userdef_InitPinMux(ssif_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+        }
+        else
+        {
+            if (NULL != p_info_ch->sem_access)
+            {
+                os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+                if (osOK != os_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected semaphore error */
+                }
+                p_info_ch->sem_access = NULL;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitChannel
+* @brief         Uninitialise the SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+        {
+            /* NON_NOTICE_ASSERT: unexpected channel status */
+        }
+
+        p_info_ch->ch_stat = SSIF_CHSTS_UNINIT;
+
+        SSIF_DisableErrorInterrupt(ssif_ch);
+
+        core_util_critical_section_enter();
+
+        /* delete the tx queue */
+        ahf_cancelall(&p_info_ch->tx_que);
+        ahf_destroy(&p_info_ch->tx_que);
+
+        /* delete the rx queue */
+        ahf_cancelall(&p_info_ch->rx_que);
+        ahf_destroy(&p_info_ch->rx_que);
+
+        /* delete the private semaphore */
+        os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+        if (osOK != os_ret)
+        {
+            /* NON_NOTICE_ASSERT: unexpected semaphore error */
+        }
+
+        SSIF_InterruptShutdown(ssif_ch);
+
+        core_util_critical_section_exit();
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UpdateChannelConfig
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ercd = SSIF_CheckChannelCfg(p_ch_cfg);
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->slave_mode = p_ch_cfg->slave_mode;
+
+            if (false != p_info_ch->slave_mode)
+            {
+                /* slave mode */
+                p_info_ch->clock_direction = SSIF_CFG_CLOCK_IN;
+                p_info_ch->ws_direction = SSIF_CFG_WS_IN;
+            }
+            else
+            {
+                /* master mode */
+                p_info_ch->clock_direction = SSIF_CFG_CLOCK_OUT;
+                p_info_ch->ws_direction = SSIF_CFG_WS_OUT;
+
+                /* when master mode, always disable noise cancel */
+                p_info_ch->noise_cancel = SSIF_CFG_DISABLE_NOISE_CANCEL;
+            }
+
+            p_info_ch->sample_freq        = p_ch_cfg->sample_freq;
+
+            p_info_ch->clk_select         = p_ch_cfg->clk_select;
+            p_info_ch->multi_ch           = p_ch_cfg->multi_ch;
+            p_info_ch->data_word          = p_ch_cfg->data_word;
+            p_info_ch->system_word        = p_ch_cfg->system_word;
+            p_info_ch->bclk_pol           = p_ch_cfg->bclk_pol;
+            p_info_ch->ws_pol             = p_ch_cfg->ws_pol;
+            p_info_ch->padding_pol        = p_ch_cfg->padding_pol;
+            p_info_ch->serial_alignment   = p_ch_cfg->serial_alignment;
+            p_info_ch->parallel_alignment = p_ch_cfg->parallel_alignment;
+            p_info_ch->ws_delay           = p_ch_cfg->ws_delay;
+            p_info_ch->noise_cancel       = p_ch_cfg->noise_cancel;
+            p_info_ch->tdm_mode           = p_ch_cfg->tdm_mode;
+#if defined(TARGET_RZA1H) /* mbed */
+            p_info_ch->romdec_direct.mode     = p_ch_cfg->romdec_direct.mode;
+            p_info_ch->romdec_direct.p_cbfunc = p_ch_cfg->romdec_direct.p_cbfunc;
+#endif /* mbed */
+
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* check combination of parameters */
+                if ((SSIF_CFG_MULTI_CH_1 == p_info_ch->multi_ch)
+                    || (SSIF_CFG_WS_HIGH == p_info_ch->ws_pol))
+                {
+                    ercd = EINVAL_RBSP;
+                }
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_CheckWordSize(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->slave_mode)
+            {
+                /* Master: call user own clock setting function */
+                ercd = R_SSIF_Userdef_SetClockDiv(p_ch_cfg, &p_info_ch->clk_div);
+            }
+            else
+            {
+                /* Slave: set dummy value for clear */
+                p_info_ch->clk_div = SSIF_CFG_CKDV_BITS_1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetCtrlParams
+* @brief         Set SSIF configuration to hardware.
+*
+*                Description:<br>
+*                Update SSICR register.
+* @param[in]     p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t ret = ESUCCESS;
+    uint32_t ssif_ch;
+    static const uint32_t gpio_sncr_bit[SSIF_NUM_CHANS] =
+    {
+        GPIO_SNCR_BIT_SSI0NCE,  /* SSIF0 */
+        GPIO_SNCR_BIT_SSI1NCE,  /* SSIF1 */
+        GPIO_SNCR_BIT_SSI2NCE,  /* SSIF2 */
+        GPIO_SNCR_BIT_SSI3NCE,  /* SSIF3 */
+#if defined(TARGET_RZA1H) /* mbed */
+        GPIO_SNCR_BIT_SSI4NCE,  /* SSIF4 */
+        GPIO_SNCR_BIT_SSI5NCE   /* SSIF5 */
+#endif /* mbed */
+    };
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* ALL CLEAR */
+        g_ssireg[ssif_ch]->SSICR = 0u;
+        g_ssireg[ssif_ch]->SSISR = 0u;
+        g_ssireg[ssif_ch]->SSIFCCR = 0u;
+
+        g_ssireg[ssif_ch]->SSICR = (uint32_t)(
+             ((uint32_t)(p_info_ch->clk_select)         << SSIF_CR_SHIFT_CKS) |
+             ((uint32_t)(p_info_ch->multi_ch)           << SSIF_CR_SHIFT_CHNL) |
+             ((uint32_t)(p_info_ch->data_word)          << SSIF_CR_SHIFT_DWL) |
+             ((uint32_t)(p_info_ch->system_word)        << SSIF_CR_SHIFT_SWL) |
+             ((uint32_t)(p_info_ch->bclk_pol)           << SSIF_CR_SHIFT_SCKP) |
+             ((uint32_t)(p_info_ch->ws_pol)             << SSIF_CR_SHIFT_SWSP) |
+             ((uint32_t)(p_info_ch->padding_pol)        << SSIF_CR_SHIFT_SPDP) |
+             ((uint32_t)(p_info_ch->serial_alignment)   << SSIF_CR_SHIFT_SDTA) |
+             ((uint32_t)(p_info_ch->parallel_alignment) << SSIF_CR_SHIFT_PDTA) |
+             ((uint32_t)(p_info_ch->ws_delay)           << SSIF_CR_SHIFT_DEL) |
+             ((uint32_t)(p_info_ch->clock_direction)    << SSIF_CR_SHIFT_SCKD) |
+             ((uint32_t)(p_info_ch->ws_direction)       << SSIF_CR_SHIFT_SWSD) |
+             ((uint32_t)(p_info_ch->clk_div)            << SSIF_CR_SHIFT_CKDV)
+             );
+
+        g_ssireg[ssif_ch]->SSITDMR = ((uint32_t)(p_info_ch->tdm_mode) << SSIF_TDMR_SHIFT_TDM);
+
+        /* change SNCR register: enter exclusive */
+        core_util_critical_section_enter();
+
+        if ((SSIF_CFG_ENABLE_NOISE_CANCEL == p_info_ch->noise_cancel)
+            && (false != p_info_ch->slave_mode))
+        {
+            /* ENABLE_NOISE_CANCEL && slave mode */
+            GPIO.SNCR |= (uint32_t)gpio_sncr_bit[ssif_ch];
+        }
+        else
+        {
+            /* DISABLE_NOISE_CANCEL || master mode */
+            GPIO.SNCR &= ~((uint32_t)gpio_sncr_bit[ssif_ch]);
+        }
+
+        /* change SNCR register: exit exclusive */
+        core_util_critical_section_exit();
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckChannelCfg
+* @brief         Check channel configuration parameters are valid or not.
+*
+*                Description:<br>
+*
+* @param[in]     p_ch_cfg     :channel configuration
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_ch_cfg)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        switch (p_ch_cfg->clk_select)
+        {
+        case SSIF_CFG_CKS_AUDIO_X1:
+            /* fall through */
+        case SSIF_CFG_CKS_AUDIO_CLK:
+            /* do nothing */
+            break;
+        default:
+            ret = EINVAL_RBSP;
+            break;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->multi_ch)
+            {
+            case SSIF_CFG_MULTI_CH_1:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_2:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_3:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_4:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->data_word)
+            {
+            case SSIF_CFG_DATA_WORD_8:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_16:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_18:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_20:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_22:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_24:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_32:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->system_word)
+            {
+            case SSIF_CFG_SYSTEM_WORD_8:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_16:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_24:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_32:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_48:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_64:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_128:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_256:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->bclk_pol)
+            {
+            case SSIF_CFG_FALLING:
+                /* fall through */
+            case SSIF_CFG_RISING:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_pol)
+            {
+            case SSIF_CFG_WS_LOW:
+                /* fall through */
+            case SSIF_CFG_WS_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->padding_pol)
+            {
+            case SSIF_CFG_PADDING_LOW:
+                /* fall through */
+            case SSIF_CFG_PADDING_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->serial_alignment)
+            {
+            case SSIF_CFG_DATA_FIRST:
+                /* fall through */
+            case SSIF_CFG_PADDING_FIRST:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->parallel_alignment)
+            {
+            case SSIF_CFG_LEFT:
+                /* fall through */
+            case SSIF_CFG_RIGHT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_delay)
+            {
+            case SSIF_CFG_DELAY:
+                /* fall through */
+            case SSIF_CFG_NO_DELAY:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->noise_cancel)
+            {
+            case SSIF_CFG_DISABLE_NOISE_CANCEL:
+                /* fall through */
+            case SSIF_CFG_ENABLE_NOISE_CANCEL:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->tdm_mode)
+            {
+            case SSIF_CFG_DISABLE_TDM:
+                /* fall through */
+            case SSIF_CFG_ENABLE_TDM:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+#if defined(TARGET_RZA1H) /* mbed */
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->romdec_direct.mode)
+            {
+            case SSIF_CFG_DISABLE_ROMDEC_DIRECT:
+                /* fall through */
+            case SSIF_CFG_ENABLE_ROMDEC_DIRECT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+#endif /* mbed */
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckWordSize
+* @brief         Check system word size whether that is valid or not.
+*
+*                Description:<br>
+*                if system_words couldn't involve specified number of<br>
+*                data_words then error.
+* @param[in]     p_info_ch    :channel object
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t ssicr_chnl;
+    uint32_t dw_per_sw;
+    uint32_t datawd_len;
+    uint32_t syswd_len;
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        ssicr_chnl = p_info_ch->multi_ch;
+        /* ->MISRA 13.7 : This is verbose error check by way of precaution */
+        if (SSIF_CFG_MULTI_CH_4 < ssicr_chnl)
+        /* <-MISRA 13.7 */
+        {
+            ret = EINVAL_RBSP;
+        }
+        else
+        {
+            /* data_words number per system_words */
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* When TDM Mode data_word number per system_words fixed to 1 */
+                dw_per_sw = 1u;
+            }
+            else
+            {
+                /* When not TDM data_word number per system_words depends CHNL */
+                dw_per_sw = ssicr_chnl + 1u;
+            }
+
+            /* size of data_words */
+            datawd_len = (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+            if (0u == datawd_len)
+            {
+                ret = EINVAL_RBSP;
+            }
+            else
+            {
+                /* size of system_words */
+                syswd_len = (uint32_t)SSIF_SWLtoLen(p_info_ch->system_word);
+
+                if (syswd_len < (datawd_len * dw_per_sw))
+                {
+                    ret = EINVAL_RBSP;
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Reset
+* @brief         SSIF software reset
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch       :SSIF channel
+* @retval        none
+******************************************************************************/
+static void SSIF_Reset(const uint32_t ssif_ch)
+{
+    uint8_t dummy_read_u8;
+    static const uint32_t cpg_swrst_bit[SSIF_NUM_CHANS] =
+    {
+        CPG_SWRSTCR1_BIT_SRST16,    /* SSIF0 */
+        CPG_SWRSTCR1_BIT_SRST15,    /* SSIF1 */
+        CPG_SWRSTCR1_BIT_SRST14,    /* SSIF2 */
+        CPG_SWRSTCR1_BIT_SRST13,    /* SSIF3 */
+#if defined(TARGET_RZA1H) /* mbed */
+        CPG_SWRSTCR1_BIT_SRST12,    /* SSIF4 */
+        CPG_SWRSTCR1_BIT_SRST11     /* SSIF5 */
+#endif /* mbed */
+    };
+
+    /* change register: enter exclusive */
+    core_util_critical_section_enter();
+
+    /* SW Reset ON */
+    /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */
+    CPGSWRSTCR1 |= (uint8_t)cpg_swrst_bit[ssif_ch];
+    dummy_read_u8 = CPGSWRSTCR1;
+    /* <-IPA R2.4.2 */
+    UNUSED_ARG(dummy_read_u8);
+
+    /* SW Reset OFF */
+    /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */
+    CPGSWRSTCR1 &= (uint8_t)~((uint8_t)cpg_swrst_bit[ssif_ch]);
+    dummy_read_u8 = CPGSWRSTCR1;
+    /* <-IPA R2.4.2 */
+    UNUSED_ARG(dummy_read_u8);
+
+    /* change register: exit exclusive */
+    core_util_critical_section_exit();
+
+    return;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,278 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif.h
+* $Rev: $
+* $Date::                           $
+* Description  : SSIF driver functions header
+******************************************************************************/
+
+#ifndef SSIF_H
+#define SSIF_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "aioif.h"
+#include "iodefine.h"
+#include "ssif_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIF_CHNUM_4    (4u)
+#define SSIF_CHNUM_5    (5u)
+#endif /* mbed */
+
+#define SSIF_CHSTR_0 "\\0"
+#define SSIF_CHSTR_1 "\\1"
+#define SSIF_CHSTR_2 "\\2"
+#define SSIF_CHSTR_3 "\\3"
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIF_CHSTR_4 "\\4"
+#define SSIF_CHSTR_5 "\\5"
+#endif /* mbed */
+
+#define SSIF_MAX_PATH_LEN           (32u)
+
+#define SSIF_CR_SHIFT_CKS   (30u)
+#define SSIF_CR_SHIFT_TUIEN (29u)
+#define SSIF_CR_SHIFT_TOIEN (28u)
+#define SSIF_CR_SHIFT_RUIEN (27u)
+#define SSIF_CR_SHIFT_ROIEN (26u)
+#define SSIF_CR_SHIFT_IIEN  (25u)
+#define SSIF_CR_SHIFT_CHNL  (22u)
+#define SSIF_CR_SHIFT_DWL   (19u)
+#define SSIF_CR_SHIFT_SWL   (16u)
+#define SSIF_CR_SHIFT_SCKD  (15u)
+#define SSIF_CR_SHIFT_SWSD  (14u)
+#define SSIF_CR_SHIFT_SCKP  (13u)
+#define SSIF_CR_SHIFT_SWSP  (12u)
+#define SSIF_CR_SHIFT_SPDP  (11u)
+#define SSIF_CR_SHIFT_SDTA  (10u)
+#define SSIF_CR_SHIFT_PDTA  ( 9u)
+#define SSIF_CR_SHIFT_DEL   ( 8u)
+#define SSIF_CR_SHIFT_CKDV  ( 4u)
+#define SSIF_CR_SHIFT_MUEN  ( 3u)
+#define SSIF_CR_SHIFT_TEN   ( 1u)
+#define SSIF_CR_SHIFT_REN   ( 0u)
+
+#define SSIF_CR_BIT_CKS     (1u << SSIF_CR_SHIFT_CKS)
+#define SSIF_CR_BIT_TUIEN   (1u << SSIF_CR_SHIFT_TUIEN)
+#define SSIF_CR_BIT_TOIEN   (1u << SSIF_CR_SHIFT_TOIEN)
+#define SSIF_CR_BIT_RUIEN   (1u << SSIF_CR_SHIFT_RUIEN)
+#define SSIF_CR_BIT_ROIEN   (1u << SSIF_CR_SHIFT_ROIEN)
+#define SSIF_CR_BIT_IIEN    (1u << SSIF_CR_SHIFT_IIEN)
+#define SSIF_CR_BITS_CHNL   (3u << SSIF_CR_SHIFT_CHNL)
+#define SSIF_CR_BITS_DWL    (7u << SSIF_CR_SHIFT_DWL)
+#define SSIF_CR_BITS_SWL    (7u << SSIF_CR_SHIFT_SWL)
+#define SSIF_CR_BIT_SCKD    (1u << SSIF_CR_SHIFT_SCKD)
+#define SSIF_CR_BIT_SWSD    (1u << SSIF_CR_SHIFT_SWSD)
+#define SSIF_CR_BIT_SCKP    (1u << SSIF_CR_SHIFT_SCKP)
+#define SSIF_CR_BIT_SWSP    (1u << SSIF_CR_SHIFT_SWSP)
+#define SSIF_CR_BIT_SPDP    (1u << SSIF_CR_SHIFT_SPDP)
+#define SSIF_CR_BIT_SDTA    (1u << SSIF_CR_SHIFT_SDTA)
+#define SSIF_CR_BIT_PDTA    (1u << SSIF_CR_SHIFT_PDTA)
+#define SSIF_CR_BIT_DEL     (1u << SSIF_CR_SHIFT_DEL)
+#define SSIF_CR_BITS_CKDV   (0xfu << SSIF_CR_SHIFT_CKDV)
+#define SSIF_CR_BIT_MUEN    (1u << SSIF_CR_SHIFT_MUEN)
+#define SSIF_CR_BIT_TEN     (1u << SSIF_CR_SHIFT_TEN)
+#define SSIF_CR_BIT_REN     (1u << SSIF_CR_SHIFT_REN)
+#define SSIF_CR_INT_ERR_MASK    (SSIF_CR_BIT_TUIEN | SSIF_CR_BIT_TOIEN | SSIF_CR_BIT_RUIEN | SSIF_CR_BIT_ROIEN)
+
+#define SSIF_SR_SHIFT_TUIRQ (29u)
+#define SSIF_SR_SHIFT_TOIRQ (28u)
+#define SSIF_SR_SHIFT_RUIRQ (27u)
+#define SSIF_SR_SHIFT_ROIRQ (26u)
+#define SSIF_SR_SHIFT_IIRQ  (25u)
+#define SSIF_SR_SHIFT_IDST  ( 0u)
+
+#define SSIF_SR_BIT_TUIRQ   (1u << SSIF_SR_SHIFT_TUIRQ)
+#define SSIF_SR_BIT_TOIRQ   (1u << SSIF_SR_SHIFT_TOIRQ)
+#define SSIF_SR_BIT_RUIRQ   (1u << SSIF_SR_SHIFT_RUIRQ)
+#define SSIF_SR_BIT_ROIRQ   (1u << SSIF_SR_SHIFT_ROIRQ)
+#define SSIF_SR_BIT_IIRQ    (1u << SSIF_SR_SHIFT_IIRQ)
+#define SSIF_SR_BIT_IDST    (1u << SSIF_SR_SHIFT_IDST)
+#define SSIF_SR_INT_ERR_MASK    (SSIF_SR_BIT_TUIRQ | SSIF_SR_BIT_TOIRQ | SSIF_SR_BIT_RUIRQ | SSIF_SR_BIT_ROIRQ)
+
+#define SSIF_FCR_SHIFT_TIE      (3u)
+#define SSIF_FCR_SHIFT_RIE      (2u)
+#define SSIF_FCR_SHIFT_TFRST    (1u)
+#define SSIF_FCR_SHIFT_RFRST    (0u)
+
+#define SSIF_FCR_BIT_TIE   (1u << SSIF_FCR_SHIFT_TIE)
+#define SSIF_FCR_BIT_RIE   (1u << SSIF_FCR_SHIFT_RIE)
+#define SSIF_FCR_BIT_TFRST (1u << SSIF_FCR_SHIFT_TFRST)
+#define SSIF_FCR_BIT_RFRST (1u << SSIF_FCR_SHIFT_RFRST)
+
+#define SSIF_TDMR_SHIFT_CONT    (8u)
+#define SSIF_TDMR_SHIFT_TDM     (0u)
+
+#define SSIF_TDMR_BIT_CONT (1u << SSIF_TDMR_SHIFT_CONT)
+#define SSIF_TDMR_BIT_TDM  (1u << SSIF_TDMR_SHIFT_TDM)
+
+/* noise canceled bit */
+#define GPIO_SNCR_BIT_SSI5NCE  (1u << 5)
+#define GPIO_SNCR_BIT_SSI4NCE  (1u << 4)
+#define GPIO_SNCR_BIT_SSI3NCE  (1u << 3)
+#define GPIO_SNCR_BIT_SSI2NCE  (1u << 2)
+#define GPIO_SNCR_BIT_SSI1NCE  (1u << 1)
+#define GPIO_SNCR_BIT_SSI0NCE  (1u << 0)
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+typedef enum {
+    SSIF_DRVSTS_UNINIT = 0,
+    SSIF_DRVSTS_INIT
+} ssif_drv_stat_t;
+
+typedef enum
+{
+    SSIF_CHSTS_UNINIT = 0,
+    SSIF_CHSTS_INIT,
+    SSIF_CHSTS_OPEN
+} ssif_ch_stat_t;
+
+typedef enum
+{
+    SSIF_ASYNC_W = 0,
+    SSIF_ASYNC_R
+} ssif_rw_mode_t;
+
+/** Serial bit clock direction */
+typedef enum
+{
+    SSIF_CFG_CLOCK_IN  = 0,  /**< Clock IN - Slave mode */
+    SSIF_CFG_CLOCK_OUT = 1   /**< Clock OUT - Master mode */
+} ssif_chcfg_clock_dir_t;
+
+
+/** Serial word select direction */
+typedef enum
+{
+    SSIF_CFG_WS_IN  = 0,     /**< Word select IN - Slave mode */
+    SSIF_CFG_WS_OUT = 1      /**< Word select OUT - Master mode */
+} ssif_chcfg_ws_dir_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+typedef struct ssif_info_ch
+{
+    uint32_t    channel;
+    bool_t      enabled;
+    bool_t      slave_mode;
+    uint32_t    sample_freq;
+    ssif_ch_stat_t ch_stat;
+    osSemaphoreId_t sem_access;
+    AHF_S       tx_que;
+    AHF_S       rx_que;
+    int_t       dma_rx_ch;
+    int_t       dma_tx_ch;
+    bool_t      is_full_duplex;         /* full/half duplex */
+    int_t       openflag;
+    AIOCB*      p_aio_tx_curr;
+    AIOCB*      p_aio_tx_next;
+    AIOCB*      p_aio_rx_curr;
+    AIOCB*      p_aio_rx_next;
+    ssif_chcfg_cks_t                clk_select;
+    ssif_chcfg_multi_ch_t           multi_ch;
+    ssif_chcfg_data_word_t          data_word;
+    ssif_chcfg_system_word_t        system_word;
+    ssif_chcfg_clock_dir_t          clock_direction;
+    ssif_chcfg_ws_dir_t             ws_direction;
+    ssif_chcfg_clock_pol_t          bclk_pol;
+    ssif_chcfg_ws_pol_t             ws_pol;
+    ssif_chcfg_padding_pol_t        padding_pol;
+    ssif_chcfg_serial_alignment_t   serial_alignment;
+    ssif_chcfg_parallel_alignment_t parallel_alignment;
+    ssif_chcfg_ws_delay_t           ws_delay;
+    ssif_chcfg_noise_cancel_t       noise_cancel;
+    ssif_chcfg_tdm_t                tdm_mode;
+    ssif_chcfg_ckdv_t               clk_div;
+#if defined(TARGET_RZA1H) /* mbed */
+    ssif_chcfg_romdec_t             romdec_direct;
+#endif /* mbed */
+#if(1) /* mbed */
+    uint8_t     int_level;
+#endif
+} ssif_info_ch_t;
+
+
+typedef struct ssif_info_drv
+{
+    ssif_drv_stat_t drv_stat;
+    ssif_info_ch_t  info_ch[SSIF_NUM_CHANS];
+} ssif_info_drv_t;
+
+extern volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS];
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialiseOne(const int_t channel);
+#endif /* end mbed */
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialise(void);
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch);
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch);
+void  SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch);
+
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                const ssif_channel_cfg_t* const p_ch_cfg);
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status);
+
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch);
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch);
+
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl);
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl);
+
+#if(1) /* mbed */
+extern ssif_info_drv_t * SSIF_GetDrvInstanc(void);
+#else
+extern ssif_info_drv_t g_ssif_info_drv;
+#endif /* end mbed */
+
+#endif /* SSIF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif_cfg.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,729 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_cfg.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver userown functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "dma_if.h"
+#include "ssif_if.h"
+#include "iodefine.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/***** Audio Clock Source Configurations *****/
+#if defined(TARGET_RZA1H) /* mbed */
+/* AUDIO_X1 : Connect to CPU Board X8(22579200Hz) */
+#define SSIF_AUDIO_X1  (22579200u)
+#else
+/* AUDIO_X1 : Connect to CPU Board X8(12000000Hz) */
+#define SSIF_AUDIO_X1  (12000000u)
+#endif
+
+/* AUDIO_CLK: Connect to option board J7(no clock on board) */
+#define SSIF_AUDIO_CLK (0u)
+
+/* SSICR CKDV divieded value */
+#define SSIF_AUDIO_CLK_DIV_1    (1u)
+#define SSIF_AUDIO_CLK_DIV_2    (2u)
+#define SSIF_AUDIO_CLK_DIV_4    (4u)
+#define SSIF_AUDIO_CLK_DIV_8    (8u)
+#define SSIF_AUDIO_CLK_DIV_16   (16u)
+#define SSIF_AUDIO_CLK_DIV_32   (32u)
+#define SSIF_AUDIO_CLK_DIV_64   (64u)
+#define SSIF_AUDIO_CLK_DIV_128  (128u)
+#define SSIF_AUDIO_CLK_DIV_6    (6u)
+#define SSIF_AUDIO_CLK_DIV_12   (12u)
+#define SSIF_AUDIO_CLK_DIV_24   (24u)
+#define SSIF_AUDIO_CLK_DIV_48   (48u)
+#define SSIF_AUDIO_CLK_DIV_96   (96u)
+
+/* SSIF channel number */
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIF_CHNUM_4    (4u)
+#define SSIF_CHNUM_5    (5u)
+#endif /* mbed */
+
+/* misc constant value */
+#define SSIF_I2S_LR_CH  (2u)
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+#if(1) /* mbed */
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+    UNUSED_ARG(ssif_ch);
+
+    return ESUCCESS;
+}
+#else  /* not mbed */
+#include  "mbed_critical.h"
+
+#if defined(TARGET_RZA1H) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_InitPinMux
+* @brief         This function initialise pin multiplex settings.
+*
+*                Description:<br>
+*                R7S72100 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: Working with SSIF5<br>
+*                Channel settings<br>
+*                  SSIF0    : Fully connected to WM8978<br>
+*                  SSIF1    : Read only (NC:SSITxD1) connected to CD Deck<br>
+*                  SSIF2    : No connection<br>
+*                  SSIF3    : Write only (NC:SSIRxD3) connected to AK4353<br>
+*                  SSIF4    : Fully connected to AK4353<br>
+*                  SSIF5    : Fully connected to HCI
+* @param[in]     ssif_ch      :channel number.
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+    int_t ercd = ESUCCESS;
+
+    core_util_critical_section_enter();
+
+    /* -> IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 16bit register. */
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            /* SSISCK0(P4_4, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N4);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS0(P4_5, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N5);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD0(P4_6, Alternative Mode 5,Input) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N6);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD0(P4_7, Alternative Mode 5,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N7);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N7);
+            break;
+
+        case SSIF_CHNUM_1:
+            /* SSISCK1(P3_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS1(P3_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC3 |=  (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD1(P3_6, Alternative Mode 3,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD1:  no connection */
+            break;
+
+        case SSIF_CHNUM_2:
+            /* SSISCK2:  no connection */
+            /* SSIWS2:   no connection */
+            /* SSIDATA2: no connection */
+            break;
+
+        case SSIF_CHNUM_3:
+            /* SSISCK3(P4_12, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N12);
+
+            GPIO.PIPC4  |= (uint16_t) GPIO_BIT_N12;
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS3(P4_13, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N13);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIRxD3:  no connection */
+
+            /* SSITxD3(P4_15, Alternative Mode 6,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N15);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N15);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N15);
+            break;
+
+        case SSIF_CHNUM_4:
+            /* SSISCK4(P11_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS4(P11_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC11  |= (uint16_t) GPIO_BIT_N5;
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIDATA4(P11_6, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N6);
+            break;
+
+        case SSIF_CHNUM_5:
+            /* SSISCK5(P2_4, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS5(P2_5, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD5(P2_6, Alternative Mode 4,Input) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD5(P2_7, Alternative Mode 4,Output) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM2    &= (uint16_t)~(GPIO_BIT_N7);
+
+            /* AUDIO_CLK(P3_1, Alternative Mode 6,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N1);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFC3   |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PFCE3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFCAE3 |= (uint16_t) (GPIO_BIT_N1);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N1);
+            break;
+
+        default:
+            ercd = EINVAL;
+            break;
+    }
+    /* <- IPA R2.4.2 */
+
+    core_util_critical_section_exit();
+
+    return ercd;
+}
+#else /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_InitPinMux
+* @brief         This function initialise pin multiplex settings.
+*
+*                Description:<br>
+*                R7S72103 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: This port is not set.
+*                             (If you don't use EtherAVB, don't need to set.)
+*                Channel settings<br>
+*                  SSIF0    : No connection<br>
+*                  SSIF1    : Fully connected to AK4353<br>
+*                  SSIF2    : Fully connected to WM8978<br>
+*                  SSIF3    : No connection<br>
+* @param[in]     ssif_ch      :channel number.
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+    int_t ercd = ESUCCESS;
+
+    core_util_critical_section_enter();
+
+    /* -> IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 16bit register. */
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            /* SSISCK0:  no connection */
+            /* SSIWS0:   no connection */
+            /* SSIRxD0:  no connection */
+            /* SSITxD0:  no connection */
+
+            break;
+
+        case SSIF_CHNUM_1:
+            /* SSISCK1:  P7_8, Alt2(001), Input/Output */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N8);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N8);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N8);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N8);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N8);
+
+            GPIO.PIPC7  |= (uint16_t) (GPIO_BIT_N8);
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N8);
+
+            /* SSIWS1:   P7_9, Alt2(001), Input/Output */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N9);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N9);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N9);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N9);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N9);
+
+            GPIO.PIPC7  |= (uint16_t) (GPIO_BIT_N9);
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N9);
+
+            /* SSIRxD1:  P7_11, Alt2(001), Input */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N11);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N11);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N11);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N11);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N11);
+
+            GPIO.PIPC7  |= (uint16_t) (GPIO_BIT_N11);
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N11);
+
+            /* SSITxD1:  P7_10, Alt2(001), Output */
+            GPIO.PIBC7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PM7    |= (uint16_t) (GPIO_BIT_N10);
+            GPIO.PMC7   &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PIPC7  &= (uint16_t)~(GPIO_BIT_N10);
+
+            GPIO.PBDC7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PFC7   |= (uint16_t) (GPIO_BIT_N10);
+            GPIO.PFCE7  &= (uint16_t)~(GPIO_BIT_N10);
+            GPIO.PFCAE7 &= (uint16_t)~(GPIO_BIT_N10);
+
+            GPIO.PMC7   |= (uint16_t) (GPIO_BIT_N10);
+            GPIO.PM7    &= (uint16_t)~(GPIO_BIT_N10);
+            break;
+
+        case SSIF_CHNUM_2:
+            /* SSISCK2:  P6_12, Alt4(011), Input/Output */
+            GPIO.PIBC6  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM6    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC6   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC6  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFC6   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE6  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCAE6 &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PIPC6  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC6   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS2:   P6_13, Alt4(011), Input/Output */
+            GPIO.PIBC6  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM6    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC6   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC6  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFC6   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE6  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCAE6 &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PIPC6  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC6   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIDATA2: P6_14, Alt4(011), Input/Output */
+            GPIO.PIBC6  &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PM6    |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PMC6   &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PIPC6  &= (uint16_t)~(GPIO_BIT_N14);
+
+            GPIO.PBDC6  &= (uint16_t)~(GPIO_BIT_N14);
+            GPIO.PFC6   |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PFCE6  |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PFCAE6 &= (uint16_t)~(GPIO_BIT_N14);
+
+            GPIO.PIPC6  |= (uint16_t) (GPIO_BIT_N14);
+            GPIO.PMC6   |= (uint16_t) (GPIO_BIT_N14);
+            break;
+
+        case SSIF_CHNUM_3:
+            /* SSISCK3:  no connection */
+            /* SSIWS3:   no connection */
+            /* SSIRxD3:  no connection */
+            /* SSITxD3:  no connection */
+            break;
+
+        default:
+            ercd = EINVAL;
+            break;
+    }
+    /* <- IPA R2.4.2 */
+
+    core_util_critical_section_exit();
+
+    return ercd;
+}
+#endif /* end mbed */
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_SetClockDiv
+* @brief         This function make a value of divieded audio clock.
+*
+*                Description:<br>
+*
+* @param[in]     p_ch_cfg     :pointer of channel configuration parameter.
+* @param[in,out] p_clk_div    :pointer of SSICR register CKDV value
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div)
+{
+    uint32_t input_clk;
+    uint32_t dot_clk;
+    uint32_t n_syswd_per_smp;
+    uint32_t syswd_len;
+    uint32_t smp_freq;
+    uint32_t result;
+    uint32_t division;
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_ch_cfg) || (NULL == p_clk_div))
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SSIF_CFG_CKS_AUDIO_X1 == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_X1;
+        }
+        else if (SSIF_CFG_CKS_AUDIO_CLK == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_CLK;
+        }
+        else
+        {
+            input_clk = 0u;
+        }
+
+        if (0u == input_clk)
+        {
+            ret = EINVAL_RBSP;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            syswd_len = (uint32_t)R_SSIF_SWLtoLen(p_ch_cfg->system_word);
+            smp_freq = p_ch_cfg->sample_freq;
+
+            if (SSIF_CFG_DISABLE_TDM == p_ch_cfg->tdm_mode)
+            {
+                /* I2S format has 2 system_words */
+                n_syswd_per_smp = SSIF_I2S_LR_CH;
+            }
+            else
+            {
+                /* TDM frame has [(CHNL+1) * 2] system_words */
+                n_syswd_per_smp = (((uint32_t)p_ch_cfg->multi_ch) + 1) * SSIF_I2S_LR_CH;
+            }
+
+            dot_clk = syswd_len * n_syswd_per_smp * smp_freq;
+
+            if (0u == dot_clk)
+            {
+                ret = EINVAL_RBSP;
+            }
+            else
+            {
+                /* check if input audio clock can be divided by dotclock */
+                result = input_clk % dot_clk;
+
+                if (0u != result)
+                {
+                    /* cannot create dotclock from input audio clock */
+                    ret = EINVAL_RBSP;
+                }
+                else
+                {
+                    division = input_clk / dot_clk;
+
+                    switch (division)
+                    {
+                    case SSIF_AUDIO_CLK_DIV_1:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_1;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_2:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_2;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_4:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_4;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_8:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_8;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_16:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_16;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_32:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_32;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_64:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_64;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_128:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_128;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_6:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_6;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_12:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_12;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_24:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_24;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_48:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_48;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_96:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_96;
+                        break;
+                    default:
+                        ret = EINVAL_RBSP;
+                        break;
+                    }
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif_dma.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,795 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_dma.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver DMA functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "dma_if.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_DUMMY_DMA_BUF_SIZE (4096u)
+
+/*
+ * The common multiple of 2, 4, 6, 8, 12, 24 and 32
+ * which are all sampling sizes
+ */
+#define SSIF_DUMMY_DMA_TRN_SIZE (4032u)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+static void SSIF_DMA_TxCallback(union sigval param);
+static void SSIF_DMA_RxCallback(union sigval param);
+
+static const dma_res_select_t gb_ssif_dma_tx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSITXI0,
+    DMA_RS_SSITXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSITXI3,
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_SSIRTI4,
+    DMA_RS_SSITXI5
+#endif /* mbed */
+};
+
+static const dma_res_select_t gb_ssif_dma_rx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSIRXI0,
+    DMA_RS_SSIRXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSIRXI3,
+#if defined(TARGET_RZA1H) /* mbed */
+    DMA_RS_SSIRTI4,
+    DMA_RS_SSIRXI5
+#endif /* mbed */
+};
+
+static AIOCB gb_ssif_dma_tx_end_aiocb[SSIF_NUM_CHANS];
+static AIOCB gb_ssif_dma_rx_end_aiocb[SSIF_NUM_CHANS];
+
+static dma_trans_data_t gb_ssif_txdma_dummy_trparam[SSIF_NUM_CHANS];
+static dma_trans_data_t gb_ssif_rxdma_dummy_trparam[SSIF_NUM_CHANS];
+
+static uint32_t ssif_tx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE / sizeof(uint32_t)];
+static uint32_t ssif_rx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE / sizeof(uint32_t)];
+
+/******************************************************************************
+* Function Name: SSIF_InitDMA
+* @brief         Allocate and Setup DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* allocate DMA Channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                p_info_ch->dma_tx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_tx_ch = -1;
+                    ercd = ENOMEM_RBSP;
+                }
+                else
+                {
+                    p_info_ch->dma_tx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* allocate DMA Channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                p_info_ch->dma_rx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_rx_ch = -1;
+                    ercd = ENOMEM_RBSP;
+                }
+                else
+                {
+                    p_info_ch->dma_rx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR_RBSP == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL_RBSP;
+            }
+        }
+
+        /* cleanup dma resources when error occured */
+        if (ESUCCESS != ercd)
+        {
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_tx_ch = -1;
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_rx_ch = -1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitDMA
+* @brief         Free DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_tx_ch = -1;
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_rx_ch = -1;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_RestartDMA
+* @brief         Setup DMA_CH for specified SSIF channel(without allocate)
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR_RBSP == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL_RBSP;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CancelDMA
+* @brief         Pause DMA transfer for specified SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_DMA_TxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_TxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+#if(1) /* mbed */
+    int32_t ercd = ESUCCESS;
+#else
+    int_t ercd = ESUCCESS;
+#endif
+    int_t ret;
+
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_tx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_tx_curr->aio_return = (ssize_t)p_info_ch->p_aio_tx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_tx_curr = p_info_ch->p_aio_tx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_tx_next = ahf_removehead(&p_info_ch->tx_que);
+
+        if (NULL != p_info_ch->p_aio_tx_next)
+        {
+            /* add user request */
+            dma_data_next.dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+            dma_data_next.src_addr = (void*)p_info_ch->p_aio_tx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_tx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DMA_RxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_RxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+#if(1) /* mbed */
+    int32_t ercd = ESUCCESS;
+#else
+    int_t ercd = ESUCCESS;
+#endif
+    int_t ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_rx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_rx_curr->aio_return = (ssize_t)p_info_ch->p_aio_rx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_rx_curr = p_info_ch->p_aio_rx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_rx_next = ahf_removehead(&p_info_ch->rx_que);
+
+        if (NULL != p_info_ch->p_aio_rx_next)
+        {
+            /* add user request */
+            dma_data_next.src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+            dma_data_next.dst_addr = (void*)p_info_ch->p_aio_rx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_rx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif_if.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,948 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_if.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver interface functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "cmsis_os.h"
+#if(1) /* mbed */
+#include "r_bsp_cmn.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+#include "ssif.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+#if(1) /* mbed */
+static ssif_drv_stat_t ch_drv_stat[SSIF_NUM_CHANS] = {SSIF_DRVSTS_UNINIT};
+
+static void* R_SSIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno);
+static int_t R_SSIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno);
+#else  /* not mbed */
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno);
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno);
+#endif /* end mbed */
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno);
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno);
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno);
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* p_aio, int32_t* const p_errno);
+
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen);
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen);
+static void   SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_MakeCbTbl_mbed
+* @brief         Make the SSIF driver function callback table
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of SSIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+RBSP_MBED_FNS* R_SSIF_MakeCbTbl_mbed(void)
+/* <-IPA M1.1.1 */
+{
+    static RBSP_MBED_FNS ssif_apitbl_mbed;
+
+    ssif_apitbl_mbed.initialise_one   = &R_SSIF_InitOne;
+    ssif_apitbl_mbed.uninitialise_one = &R_SSIF_UnInitOne;
+    ssif_apitbl_mbed.open             = &R_SSIF_Open;
+    ssif_apitbl_mbed.close            = &R_SSIF_Close;
+    ssif_apitbl_mbed.ioctl            = &R_SSIF_Ioctl;
+    ssif_apitbl_mbed.read_a           = &R_SSIF_ReadAsync;
+    ssif_apitbl_mbed.write_a          = &R_SSIF_WriteAsync;
+    ssif_apitbl_mbed.cancel           = &R_SSIF_Cancel;
+
+    return &ssif_apitbl_mbed;
+}
+#else  /* not mbed */
+/******************************************************************************
+* Function Name: R_SSIF_MakeCbTbl
+* @brief         Make the SSIF driver function callback table
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        pointer of SSIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+IOIF_DRV_API* R_SSIF_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    static IOIF_DRV_API ssif_apitbl;
+
+    /* ->MISRA 16.4, IPA M4.5.1 : This is IOIF library API type definitnon that can't be modified. */
+    ssif_apitbl.family = IOIF_SERIAL_FAMILY;
+    ssif_apitbl.fns.serial.initialise   = &R_SSIF_Init;
+    ssif_apitbl.fns.serial.uninitialise = &R_SSIF_UnInit;
+    ssif_apitbl.fns.serial.open         = &R_SSIF_Open;
+    ssif_apitbl.fns.serial.close        = &R_SSIF_Close;
+    ssif_apitbl.fns.serial.ioctl        = &R_SSIF_Ioctl;
+    ssif_apitbl.fns.serial.read_a       = &R_SSIF_ReadAsync;
+    ssif_apitbl.fns.serial.write_a      = &R_SSIF_WriteAsync;
+    ssif_apitbl.fns.serial.cancel       = &R_SSIF_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+
+    return &ssif_apitbl;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(byte)
+******************************************************************************/
+int_t R_SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    return SSIF_SWLtoLen(ssicr_swl);
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_InitOne
+* @brief         Initialise the SSIF driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel     :channel number
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SSIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+#if(1) /* mbed */
+    else if ((uint32_t)channel >= SSIF_NUM_CHANS)
+#else
+    else if (channel >= SSIF_NUM_CHANS)
+#endif
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+#if(1) /* mbed */
+        ssif_info_drv_t* const p_info_drv = SSIF_GetDrvInstanc();
+        p_info_drv->drv_stat = SSIF_DRVSTS_INIT;
+#else
+        g_ssif_info_drv.drv_stat = SSIF_DRVSTS_INIT;
+#endif /* end mbed */
+        ch_drv_stat[channel] = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_InitialiseOne(channel, (const ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+#if(1) /* mbed */
+            p_ret = (void*)p_info_drv;
+#else
+            p_ret = (void*)&g_ssif_info_drv;
+#endif /* end mbed */
+        }
+        else
+        {
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_UnInitOne
+* @brief         Uninitialise the SSIF deiver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel         :channel number
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SSIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SSIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+
+    if (NULL == driver_instance)
+    {
+        ercd = EFAULT_RBSP;
+    }
+#if(1) /* mbed */
+    else if ((uint32_t)channel >= SSIF_NUM_CHANS)
+#else
+    else if (channel >= SSIF_NUM_CHANS)
+#endif
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != ch_drv_stat[channel])
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialiseOne(channel);
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+#else  /* not mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Init
+* @brief         Initialise the SSIF driver.
+*
+*                Description:<br>
+*
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (SSIF_DRVSTS_UNINIT != g_ssif_info_drv.drv_stat)
+    {
+        ercd = EBUSY;
+    }
+    else
+    {
+        g_ssif_info_drv.drv_stat = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_Initialise((ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+            p_ret = (void*)&g_ssif_info_drv;
+        }
+        else
+        {
+            g_ssif_info_drv.drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_UnInit
+* @brief         Uninitialise the SSIF deiver.
+*
+*                Description:<br>
+*
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SSIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+    ssif_info_drv_t* const p_info_drv   = driver_instance;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialise();
+            p_info_drv->drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Open
+* @brief         Open an SSIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_drv_instance :driver instance which was returned by<br>
+                                 R_SSIF_Init
+* @param[in]     p_path_name    :string of channel
+* @param[in]     flags          :access mode whether the channel is opened<br>
+                                 for a read or a write
+* @param[in]     mode           :not used
+* @param[in,out] p_errno        :pointer of error code
+* @retval        not EERROR     :channel handle
+* @retval        EERROR         :Failure.
+******************************************************************************/
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno)
+{
+    uint32_t ssif_ch;
+    void* p_channelHandle;
+    size_t len;
+    size_t req_path_len;
+    ssif_info_drv_t* const p_info_drv = p_driver_instance;
+    ssif_info_ch_t* p_info_ch = NULL;
+    int_t ret;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+    static const char_t* const ch_name_string[SSIF_NUM_CHANS] =
+    {
+        SSIF_CHSTR_0,
+        SSIF_CHSTR_1,
+        SSIF_CHSTR_2,
+        SSIF_CHSTR_3,
+#if defined(TARGET_RZA1H) /* mbed */
+        SSIF_CHSTR_4,
+        SSIF_CHSTR_5
+#endif /* mbed */
+    };
+
+    UNUSED_ARG(mode);
+
+    if ((NULL == p_info_drv) || (NULL == p_path_name))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        req_path_len = strlen(p_path_name);
+        if (0u == req_path_len)
+        {
+            ercd = ENOENT_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* Serch the same pathname */
+            for (ssif_ch = 0u; (ssif_ch < SSIF_NUM_CHANS) && (p_info_ch == NULL); ssif_ch++)
+            {
+                len = SSIF_StrnLen(ch_name_string[ssif_ch], SSIF_MAX_PATH_LEN);
+
+                if (req_path_len < len)
+                {
+                    len = req_path_len;
+                }
+
+                if (0 == SSIF_Strncmp(p_path_name, ch_name_string[ssif_ch], len))
+                {
+                    /* found a match */
+                    p_info_ch = &p_info_drv->info_ch[ssif_ch];
+                }
+            }
+        }
+    }
+
+    if (NULL == p_info_ch)
+    {
+        ercd = ENOENT_RBSP;
+    }
+    else
+    {
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->enabled)
+            {
+                ercd = ENOTSUP_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+            {
+                ercd = EBADF_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                p_info_ch->openflag = flags;
+                p_info_ch->p_aio_tx_curr = NULL;
+                p_info_ch->p_aio_rx_curr = NULL;
+
+                ercd = SSIF_EnableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_OPEN;
+                }
+            }
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    else
+    {
+        p_channelHandle = (void*)p_info_ch;
+        ret = (int_t)p_channelHandle;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Close
+* @brief         Close an SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, NULL);
+
+                ercd = SSIF_DisableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+                }
+            }
+
+            /* Relese semaphore */
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Ioctl
+* @brief         IOCTL function of the SSIF deiver
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     request    :IOCTL request code
+* @param[in,out] p_buf      :Meaning depends upon request.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT_RBSP;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SSIF_CONFIG_CHANNEL:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ssif_channel_cfg_t* const ch_info = (ssif_channel_cfg_t*)p_buf;
+                            ercd = SSIF_IOCTL_ConfigChannel(p_info_ch, ch_info);
+                        }
+                        break;
+                    }
+
+                    case SSIF_GET_STATUS:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SSIF_IOCTL_GetStatus(p_info_ch, (uint32_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    default:
+                    {
+                        ercd = EINVAL_RBSP;
+                        break;
+                    }
+                } /* switch */
+            }
+        }
+
+        os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+        if (osOK != os_ercd)
+        {
+            ercd = EFAULT_RBSP;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_WriteAsync
+* @brief         Enqueue asynchronous write request
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of write request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (((uint32_t)O_RDONLY_RBSP) == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP))
+        {
+            ercd = EACCES_RBSP;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL_RBSP;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_W;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_ReadAsync
+* @brief         Enqueue asynchronous read request
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of read request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+#if defined(TARGET_RZA1H) /* mbed */
+        if ((O_WRONLY_RBSP == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP))
+            || (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                == p_info_ch->romdec_direct.mode))
+#else /* mbed */
+        if ((O_WRONLY_RBSP == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP)))
+#endif /* mbed */
+        {
+            ercd = EACCES_RBSP;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL_RBSP;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_R;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Cancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block to cancel or NULL to cancel all.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, p_aio);
+            }
+
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_StrnLen
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*
+* @param[in]     p_str      :pointer of string.
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        < maxlen   :number of characters in the string
+* @retval        maxlen     :string is longer than maxlen
+******************************************************************************/
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen)
+{
+    size_t len;
+
+    if (NULL == p_str)
+    {
+        len = 0;
+    }
+    else
+    {
+        for (len = 0; len < maxlen; len++)
+        {
+            if ((int_t)p_str[len] == '\0')
+            {
+                break;
+            }
+        }
+    }
+
+    return len;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Strncmp
+* @brief         Compare two strings
+*
+*                Description:<br>
+*
+* @param[in]     p_str1     :pointer of string1
+* @param[in]     p_str2     :pointer of string2
+* @param[in]     maxlen     :maximum length of comparison
+* @retval        zero       :strings are same.
+* @retval        non zero   :strings are different.
+******************************************************************************/
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen)
+{
+    int32_t result = 0;
+    uint32_t index;
+
+    if ((NULL == p_str1) || (NULL == p_str2))
+    {
+        result = -1;
+    }
+    else
+    {
+        for (index = 0; index < maxlen; index++)
+        {
+            /* compare charctor */
+            result = ((int_t)p_str1[index]) - ((int_t)p_str2[index]);
+            if ((result != 0)
+                || ((int_t)p_str1[index] == '\0')
+                || ((int_t)p_str2[index] == '\0'))
+            {
+                /* "charactor mismatch" or "end of string" */
+                break;
+            }
+        }
+    }
+
+    return result;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, do nothing.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif_int.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,366 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_int.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver interrupt functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "ssif_int.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_INT_PER_CH     (4u)
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+
+static void SSIF_ERI0_Handler(void);
+static void SSIF_ERI1_Handler(void);
+static void SSIF_ERI2_Handler(void);
+static void SSIF_ERI3_Handler(void);
+#if defined(TARGET_RZA1H) /* mbed */
+static void SSIF_ERI4_Handler(void);
+static void SSIF_ERI5_Handler(void);
+#endif /* mbed */
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch);
+
+/******************************************************************************
+* Function Name: SSIF_InterruptInit
+* @brief         Initialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Enable interrupt and register interrupt handler.
+* @param[in]     ssif_ch    :SSIF channel
+* @param[in]     int_level  :GIC priority level of interrupt
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            ret = InterruptHandlerRegister(SSII0_IRQn, &SSIF_ERI0_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII0_IRQn, int_level);
+            GIC_SetPriority(SSIRXI0_IRQn, int_level);
+            GIC_SetPriority(SSITXI0_IRQn, int_level);
+            GIC_EnableIRQ(SSII0_IRQn);
+            GIC_EnableIRQ(SSIRXI0_IRQn);
+            GIC_EnableIRQ(SSITXI0_IRQn);
+            break;
+        case SSIF_CHNUM_1:
+            ret = InterruptHandlerRegister(SSII1_IRQn, &SSIF_ERI1_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII1_IRQn, int_level);
+            GIC_SetPriority(SSIRXI1_IRQn, int_level);
+            GIC_SetPriority(SSITXI1_IRQn, int_level);
+            GIC_EnableIRQ(SSII1_IRQn);
+            GIC_EnableIRQ(SSIRXI1_IRQn);
+            GIC_EnableIRQ(SSITXI1_IRQn);
+            break;
+        case SSIF_CHNUM_2:
+            ret = InterruptHandlerRegister(SSII2_IRQn, &SSIF_ERI2_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII2_IRQn, int_level);
+            GIC_SetPriority(SSIRTI2_IRQn, int_level);
+            GIC_EnableIRQ(SSII2_IRQn);
+            GIC_EnableIRQ(SSIRTI2_IRQn);
+            break;
+        case SSIF_CHNUM_3:
+            ret = InterruptHandlerRegister(SSII3_IRQn, &SSIF_ERI3_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII3_IRQn, int_level);
+            GIC_SetPriority(SSIRXI3_IRQn, int_level);
+            GIC_SetPriority(SSITXI3_IRQn, int_level);
+            GIC_EnableIRQ(SSII3_IRQn);
+            GIC_EnableIRQ(SSIRXI3_IRQn);
+            GIC_EnableIRQ(SSITXI3_IRQn);
+            break;
+#if defined(TARGET_RZA1H) /* mbed */
+        case SSIF_CHNUM_4:
+            ret = InterruptHandlerRegister(SSII4_IRQn, &SSIF_ERI4_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII4_IRQn, int_level);
+            GIC_SetPriority(SSIRTI4_IRQn, int_level);
+            GIC_EnableIRQ(SSII4_IRQn);
+            GIC_EnableIRQ(SSIRTI4_IRQn);
+            break;
+        case SSIF_CHNUM_5:
+            ret = InterruptHandlerRegister(SSII5_IRQn, &SSIF_ERI5_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII5_IRQn, int_level);
+            GIC_SetPriority(SSIRXI5_IRQn, int_level);
+            GIC_SetPriority(SSITXI5_IRQn, int_level);
+            GIC_EnableIRQ(SSII5_IRQn);
+            GIC_EnableIRQ(SSIRXI5_IRQn);
+            GIC_EnableIRQ(SSITXI5_IRQn);
+            break;
+#endif /* mbed */
+        /* ->IPA R3.5.2 : There is nothing to do when unusual conditons. */
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_InterruptShutdown
+* @brief         Uninitialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Disable interrupt and unregister interrupt handler
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptShutdown(const uint32_t ssif_ch)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            GIC_DisableIRQ(SSII0_IRQn);
+            GIC_DisableIRQ(SSIRXI0_IRQn);
+            GIC_DisableIRQ(SSITXI0_IRQn);
+            ret = InterruptHandlerUnregister(SSII0_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_1:
+            GIC_DisableIRQ(SSII1_IRQn);
+            GIC_DisableIRQ(SSIRXI1_IRQn);
+            GIC_DisableIRQ(SSITXI1_IRQn);
+            ret = InterruptHandlerUnregister(SSII1_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_2:
+            GIC_DisableIRQ(SSII2_IRQn);
+            GIC_DisableIRQ(SSIRTI2_IRQn);
+            ret = InterruptHandlerUnregister(SSII2_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_3:
+            GIC_DisableIRQ(SSII3_IRQn);
+            GIC_DisableIRQ(SSIRXI3_IRQn);
+            GIC_DisableIRQ(SSITXI3_IRQn);
+            ret = InterruptHandlerUnregister(SSII3_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+#if defined(TARGET_RZA1H) /* mbed */
+        case SSIF_CHNUM_4:
+            GIC_DisableIRQ(SSII4_IRQn);
+            GIC_DisableIRQ(SSIRTI4_IRQn);
+            ret = InterruptHandlerUnregister(SSII4_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_5:
+            GIC_DisableIRQ(SSII5_IRQn);
+            GIC_DisableIRQ(SSIRXI5_IRQn);
+            GIC_DisableIRQ(SSITXI5_IRQn);
+            ret = InterruptHandlerUnregister(SSII5_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+#endif /* mbed */
+        /* ->IPA R3.5.2 : There is nothing to do when unusual conditons. */
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_EnableErrorInterrupt
+* @brief         Enable the SSIF channel error interrupt
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* clear error status */
+    g_ssireg[ssif_ch]->SSISR = 0u;
+
+    /* enable error interrupt */
+    g_ssireg[ssif_ch]->SSICR |= SSIF_CR_INT_ERR_MASK;
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableErrorInterrupt
+* @brief         Disable the SSIF channel error interrupt
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* disable error interrupt */
+    g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_INT_ERR_MASK);
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ERI<n>_Handler
+* @brief         SSIF error interrupt handler per channel
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI0_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_0);
+    return;
+}
+
+static void SSIF_ERI1_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_1);
+    return;
+}
+
+static void SSIF_ERI2_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_2);
+    return;
+}
+
+static void SSIF_ERI3_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_3);
+    return;
+}
+
+#if defined(TARGET_RZA1H) /* mbed */
+static void SSIF_ERI4_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_4);
+    return;
+}
+
+static void SSIF_ERI5_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_5);
+    return;
+}
+
+#endif /* mbed */
+/******************************************************************************
+* Function Name: SSIF_ERI_Handler
+* @brief         SSIF error interrupt handler common function
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch)
+{
+#if(1) /* mbed */
+    ssif_info_drv_t* const p_info_drv = SSIF_GetDrvInstanc();
+    ssif_info_ch_t* const p_info_ch = &p_info_drv->info_ch[ssif_ch];
+#else
+    ssif_info_ch_t* const p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+#endif /* end mbed */
+
+    if (0u != (g_ssireg[ssif_ch]->SSISR & SSIF_SR_INT_ERR_MASK))
+    {
+        /* Restart or Callback */
+        SSIF_ErrorRecovery(p_info_ch);
+    }
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif_int.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif_int.h
+* $Rev: $
+* $Date::                           $
+* Description  : SSIF driver interrupt functions header
+******************************************************************************/
+
+#ifndef SSIF_INT_H
+#define SSIF_INT_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level);
+void SSIF_InterruptShutdown(const uint32_t ssif_ch);
+
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch);
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch);
+
+#endif /* SSIF_INT_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A1XX/ssif/ssif_ver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         ssif_ver.c
+* $Rev: $
+* $Date::                           $
+* @brief        SSIF Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "ssif_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define SSIF_DRV_VER_MAJOR  (2u)
+#define SSIF_DRV_VER_MINOR  (1u)
+
+#define SSIF_DRV_VER_MASK   (0xFFu)
+#define SSIF_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SSIF_GetVersion
+* @brief         Get SSIF driver version.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SSIF_GetVersion(void)
+{
+    const uint16_t version =
+        ((SSIF_DRV_VER_MAJOR & SSIF_DRV_VER_MASK) << SSIF_DRV_VER_SHIFT)
+        | (SSIF_DRV_VER_MINOR & SSIF_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SSIF_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/dma/dma.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1522 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.c
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver internal functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "dma.h"
+#include "aioif.h"
+#include "iodefine.h"
+#include "mbed_critical.h"
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* driver management infrmation */
+static dma_info_drv_t gb_info_drv;
+
+/******************************************************************************
+Private function define (interrupt handler)
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void);
+static void R_DMA_End1InterruptHandler(void);
+static void R_DMA_End2InterruptHandler(void);
+static void R_DMA_End3InterruptHandler(void);
+static void R_DMA_End4InterruptHandler(void);
+static void R_DMA_End5InterruptHandler(void);
+static void R_DMA_End6InterruptHandler(void);
+static void R_DMA_End7InterruptHandler(void);
+static void R_DMA_End8InterruptHandler(void);
+static void R_DMA_End9InterruptHandler(void);
+static void R_DMA_End10InterruptHandler(void);
+static void R_DMA_End11InterruptHandler(void);
+static void R_DMA_End12InterruptHandler(void);
+static void R_DMA_End13InterruptHandler(void);
+static void R_DMA_End14InterruptHandler(void);
+static void R_DMA_End15InterruptHandler(void);
+static void R_DMA_ErrInterruptHandler(void);
+static void R_DMA_EndHandlerProcess(const int_t channel);
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+
+static void  DMA_OpenChannel(const int_t channel);
+
+/******************************************************************************
+* Function Name: DMA_GetDrvInstance
+* Description : Get pointer of gb_info_drv.
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void)
+{
+
+    return &gb_info_drv;
+}
+
+/******************************************************************************
+End of function DMA_GetDrv_Instance
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetDrvChInfo
+* Description : Get pointer of gb_info_drv.info_ch[channel].
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_ch_t *DMA_GetDrvChInfo(const int_t channel)
+{
+
+    return &gb_info_drv.info_ch[channel];
+}
+
+/******************************************************************************
+End of function DMA_GetDrvChInfo
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Initialize
+* Description : Initialize DMA driver.
+* Arguments : *p_dma_init_param -
+*                  Pointer of init parameters.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Registering handler failed.
+******************************************************************************/
+
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param)
+{
+    int_t    retval = ESUCCESS;
+    int_t    ch_count;
+    uint32_t error_code;
+    bool_t   init_check_flag;
+
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for each channel */
+    static volatile struct st_dmac_n *gb_dma_ch_register_addr_table[DMA_CH_NUM] =
+        { &(*(struct st_dmac_n *)&DMAC0.N0SA_0S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_1S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_2S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_3S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_4S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_5S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_6S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_7S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_8S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_9S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_10S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_11S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_12S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_13S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_14S.LONG),
+          &(*(struct st_dmac_n *)&DMAC0.N0SA_15S.LONG)
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for common register */
+    static volatile struct st_dmaccommon_n *gb_dma_common_register_addr_table[DMA_CH_NUM] =
+        { &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_0_7S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG),
+          &(*(struct st_dmaccommon_n *)&DMAC0.DCTRL_8_15S.LONG)
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+
+    /* ->MISRA 11.3, 11.4 This cast is needed for register access. */
+    /* address table of register set for DMARS */
+    static volatile unsigned long *gb_dmars_register_addr_table[DMA_CH_NUM] =
+        { &DMAC0.DMARS0S.LONG,
+          &DMAC0.DMARS0S.LONG,
+          &DMAC0.DMARS1S.LONG,
+          &DMAC0.DMARS1S.LONG,
+          &DMAC0.DMARS2S.LONG,
+          &DMAC0.DMARS2S.LONG,
+          &DMAC0.DMARS3S.LONG,
+          &DMAC0.DMARS3S.LONG,
+          &DMAC0.DMARS4S.LONG,
+          &DMAC0.DMARS4S.LONG,
+          &DMAC0.DMARS5S.LONG,
+          &DMAC0.DMARS5S.LONG,
+          &DMAC0.DMARS6S.LONG,
+          &DMAC0.DMARS6S.LONG,
+          &DMAC0.DMARS7S.LONG,
+          &DMAC0.DMARS7S.LONG
+        };
+    /* <-MISRA 11.3, 11.4 */
+
+    /* Interrpt handlers table */
+    static const IRQHandler gb_dma_int_handler_table[DMA_CH_NUM] =
+        { &R_DMA_End0InterruptHandler, /* DMA end interrupt for ch0 - ch15 */
+          &R_DMA_End1InterruptHandler,
+          &R_DMA_End2InterruptHandler,
+          &R_DMA_End3InterruptHandler,
+          &R_DMA_End4InterruptHandler,
+          &R_DMA_End5InterruptHandler,
+          &R_DMA_End6InterruptHandler,
+          &R_DMA_End7InterruptHandler,
+          &R_DMA_End8InterruptHandler,
+          &R_DMA_End9InterruptHandler,
+          &R_DMA_End10InterruptHandler,
+          &R_DMA_End11InterruptHandler,
+          &R_DMA_End12InterruptHandler,
+          &R_DMA_End13InterruptHandler,
+          &R_DMA_End14InterruptHandler,
+          &R_DMA_End15InterruptHandler
+        };
+
+    /* Interrupt numbers table */
+    static const IRQn_Type gb_dma_int_num_table[DMA_CH_NUM] =
+        { DMAINT0_IRQn, /* DMA end interrupt for ch0 - ch15 */
+          DMAINT1_IRQn,
+          DMAINT2_IRQn,
+          DMAINT3_IRQn,
+          DMAINT4_IRQn,
+          DMAINT5_IRQn,
+          DMAINT6_IRQn,
+          DMAINT7_IRQn,
+          DMAINT8_IRQn,
+          DMAINT9_IRQn,
+          DMAINT10_IRQn,
+          DMAINT11_IRQn,
+          DMAINT12_IRQn,
+          DMAINT13_IRQn,
+          DMAINT14_IRQn,
+          DMAINT15_IRQn
+        };
+
+    /* element of p_dma_init_param is copied to element of gb_info_drv */
+    gb_info_drv.p_err_aio = p_dma_init_param->p_aio;
+
+    /* set DMA error interrupt number */
+    gb_info_drv.err_irq_num = DMAERR0_IRQn;
+
+    /* init channel management information */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        /* set channel number */
+        gb_info_drv.info_ch[ch_count].ch = ch_count;
+
+        /* set DMA end interrupt number */
+        gb_info_drv.info_ch[ch_count].end_irq_num = gb_dma_int_num_table[ch_count];
+
+        /* init next DMA setting flag */
+        gb_info_drv.info_ch[ch_count].next_dma_flag = false;
+
+        if (1U == ((uint32_t)ch_count & CHECK_ODD_EVEN_MASK))
+        {
+            /* set shift number when channel is odd value */
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_ODD_CH;
+            /* set mask value when channel is odd value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_ODD_CH;
+        }
+        else
+        {
+            /* set shift number when channel is even value */
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_EVEN_CH;
+            /* set mask value when channel is even value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_EVEN_CH;
+        }
+
+        /* init DMA setup flag */
+        gb_info_drv.info_ch[ch_count].setup_flag = false;
+
+        /* ->MISRA 11.4 This cast is needed for register access. */
+        /* set DMA register address for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg = gb_dma_ch_register_addr_table[ch_count];
+        /* set common resgiter for channel 0 - 7 */
+        gb_info_drv.info_ch[ch_count].p_dma_common_reg = gb_dma_common_register_addr_table[ch_count];
+        /* <-MISRA 11.4 */
+
+        /* set DMARS register for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_dmars_reg = gb_dmars_register_addr_table[ch_count];
+    }
+
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   N0SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   N1SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   N0DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   N1DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   N0TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   N1TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = CHCTRL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  CHCFG_INIT_VALUE;
+        /* set DMA interval = 0 */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = CHITVL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  CHEXT_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   NXLA_INIT_VALUE;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg)   =   DMARS_INIT_VALUE;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    /* set interrupt output : pulse,
+       set round robin mode  */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+    /* init common resgiter for channel 8 - 15 */
+    /* set interrupt output : pulse,
+       set round robin mode */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+
+    if (ESUCCESS == retval)
+    {
+        /* DMA end interrupt handler register */
+        init_check_flag = false;
+        ch_count = 0;
+        while (false == init_check_flag)
+        {
+            error_code = InterruptHandlerRegister(gb_info_drv.info_ch[ch_count].end_irq_num,
+                                                  gb_dma_int_handler_table[ch_count]
+                                                  );
+//            GIC_SetPriority(gb_info_drv.info_ch[ch_count].end_irq_num, 0x80);
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+                init_check_flag = true;
+            }
+            if ((DMA_CH_NUM - 1) == ch_count)
+            {
+                init_check_flag = true;
+            }
+            ch_count++;
+        }
+
+        if (ESUCCESS == retval)
+        {
+            /* DMA error interrupt handler register */
+            error_code = InterruptHandlerRegister(gb_info_drv.err_irq_num,
+                                                  &R_DMA_ErrInterruptHandler
+                                                 );
+#if(1) /* mbed */
+            GIC_SetPriority(gb_info_drv.err_irq_num, 0x80);
+#endif
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+            }
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* set DMA end interrupt level & priority */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            /* set interrupt level (set edge trigger, 1-N model) */
+            GIC_SetConfiguration(gb_info_drv.info_ch[ch_count].end_irq_num, 3);
+        }
+        /* set DMA error interrupt level (set edge trgger, 1-N model) */
+        GIC_SetConfiguration(gb_info_drv.err_irq_num, 3);
+        /* DMA error interrupt enable */
+        GIC_EnableIRQ(gb_info_drv.err_irq_num);
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* set channel status */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            if ((bool_t)false != p_dma_init_param->channel[ch_count])
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_INIT;
+            }
+            else
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+            }
+        }
+        /* set driver status to DMA_DRV_INIT */
+        gb_info_drv.drv_stat = DMA_DRV_INIT;
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_Initialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_UnInitialize
+* Description : UnInitialize DMA driver.
+* Arguments : None.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Unregistering handler failed
+******************************************************************************/
+
+int_t DMA_UnInitialize(void)
+{
+    int_t            retval = ESUCCESS;
+    int_t            ch_count;
+    uint32_t         error_code;
+    bool_t           uninit_check_flag;
+
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  0;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   0;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = 0;
+    /* init common resgiter for channel 8 - 15 */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = 0;
+
+    /* uninit DMA interrupt */
+    ch_count = 0;
+    uninit_check_flag = false;
+    while (false == uninit_check_flag)
+    {
+        /* disable DMA end interrupt */
+        GIC_DisableIRQ(gb_info_drv.info_ch[ch_count].end_irq_num);
+
+        /* unregister DMA end interrupt handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.info_ch[ch_count].end_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+            uninit_check_flag = true;
+        }
+        if ((DMA_CH_NUM - 1) == ch_count)
+        {
+            uninit_check_flag = true;
+        }
+        ch_count++;
+    }
+    if (ESUCCESS == retval)
+    {
+        /* disable DMA error interrupt */
+        GIC_DisableIRQ(gb_info_drv.err_irq_num);
+
+        /* unregister DMA interrupt error handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.err_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* set channel status to DMA_CH_UNINIT */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+        }
+        /* set driver status to DMA_DRV_UNINIT*/
+        gb_info_drv.drv_stat = DMA_DRV_UNINIT;
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_UnInitialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_OpenChannel
+* Description : DMA channel open.
+*               Set DMA channel status to DMA_CH_OPEN.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+******************************************************************************/
+
+static void DMA_OpenChannel(const int_t channel)
+{
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_OpenChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFreeChannel
+* Description : Find free DMA channel and Get DMA channel.
+* Arguments : None
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     EMFILE_RBSP : When looking for a free channel, but a free
+*                              channel didn't exist.
+******************************************************************************/
+
+int_t DMA_GetFreeChannel(void)
+{
+    int_t           retval = EFAULT_RBSP;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           ch_alloc;
+    bool_t          ch_stat_check_flag;
+
+    /* looking for free channel */
+    ch_stat_check_flag = false;
+    ch_alloc = 0;
+    while (false == ch_stat_check_flag)
+    {
+        dma_info_ch = DMA_GetDrvChInfo(ch_alloc);
+
+        if (false == ch_stat_check_flag)
+        {
+            if (DMA_CH_INIT == dma_info_ch->ch_stat)
+            {
+                DMA_OpenChannel(ch_alloc);
+                retval = ch_alloc;
+                ch_stat_check_flag = true;
+            }
+            if (false ==  ch_stat_check_flag)
+            {
+                ch_alloc++;
+                /* not detected free channel */
+                if (DMA_CH_NUM == ch_alloc)
+                {
+                    /* set error return value */
+                    retval = EMFILE_RBSP;
+                    ch_stat_check_flag = true;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFreeChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFixedChannel
+* Description : Get specified DMA channel number.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     EBUSY : It has been allocated already in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in
+*                             dma_stat_ch_t.
+******************************************************************************/
+
+int_t DMA_GetFixedChannel(const int_t channel)
+{
+    int_t           retval = ESUCCESS;
+    dma_info_ch_t   *dma_info_ch;
+
+    /* allocate the specified number */
+    dma_info_ch = DMA_GetDrvChInfo(channel);
+
+    if (ESUCCESS == retval)
+    {
+        if (DMA_CH_INIT == dma_info_ch->ch_stat)
+        {
+            DMA_OpenChannel(channel);
+            /* return alloc channel number */
+            retval = channel;
+        }
+        else
+        {
+#if(1) /* mbed */
+            retval = EERROR;
+#else
+            /* set error return value */
+            switch (dma_info_ch->ch_stat)
+            {
+                case DMA_CH_UNINIT:
+                    retval = ENOTSUP;
+                break;
+                /* These 2 cases are intentionally combined. */
+                case DMA_CH_OPEN:
+                case DMA_CH_TRANSFER:
+                    retval = EBUSY;
+                break;
+
+                default:
+                    retval = EFAULT;
+                break;
+
+            }
+#endif
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFixedChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_CloseChannel
+* Description : DMA channel close.
+*               Set DMA channel status to DMA_CH_INIT.
+* Arguments : channel -
+*                  Close channel number.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_CloseChannel(const int_t channel)
+{
+    /* clear DMARS register */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) &= gb_info_drv.info_ch[channel].mask_dmars;
+
+    /* set channel status to DMA_CH_INIT */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_INIT;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_CloseChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Setparam
+* Description : Set DMA transfer parameter to Register.
+* Arguments : channel -
+*                  Set up channel number.
+*             *p_ch_setup -
+*                  Set up parameters.
+*             *p_ch_cfg -
+*                  DMA channel config table parameters.
+*             *reqd
+*                  set vaule for REQD bit on CHCFG
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetParam(const int_t channel, const dma_ch_setup_t *const p_ch_setup,
+                  const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd)
+{
+    uint32_t  chcfg_sel;
+    uint32_t  value_dmars;
+
+#if(1) /* mbed */
+    GIC_SetPriority(gb_info_drv.info_ch[channel].end_irq_num, p_ch_setup->int_level);
+#endif
+
+    /* set DMA transfer parameter to DMA channel infomation */
+    gb_info_drv.info_ch[channel].resource =  p_ch_setup->resource;
+    gb_info_drv.info_ch[channel].direction = p_ch_setup->direction;
+    gb_info_drv.info_ch[channel].src_width = p_ch_setup->src_width;
+    gb_info_drv.info_ch[channel].src_cnt =   p_ch_setup->src_cnt;
+    gb_info_drv.info_ch[channel].dst_width = p_ch_setup->dst_width;
+    gb_info_drv.info_ch[channel].dst_cnt =   p_ch_setup->dst_cnt;
+    gb_info_drv.info_ch[channel].p_end_aio = p_ch_setup->p_aio;
+
+    /* set DMARS value and protect non change bit */
+    value_dmars = *(gb_info_drv.info_ch[channel].p_dma_dmars_reg);
+    value_dmars = ((value_dmars & gb_info_drv.info_ch[channel].mask_dmars) |
+                   (uint32_t)(p_ch_cfg->dmars << gb_info_drv.info_ch[channel].shift_dmars));
+    /* set DMARS register value */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) = value_dmars;
+
+    /* set CHCFG regsiter */
+    if (channel < HIGH_COMMON_REG_OFFSET)
+    {
+        chcfg_sel = (uint32_t)channel;
+    }
+    else
+    {
+        chcfg_sel = (uint32_t)(channel - HIGH_COMMON_REG_OFFSET);
+    }
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n
+        = ((uint32_t)CHCFG_FIXED_VALUE |
+           /* ->MISRA 21.1 ,IPA R2.4.1 The value of every parameter won't be minus.
+              and the value after a shift will be less than 0x80000000 certainly.
+           */
+           (((uint32_t)p_ch_setup->dst_cnt << CHCFG_SHIFT_DAD) & CHCFG_MASK_DAD) |
+           (((uint32_t)p_ch_setup->src_cnt << CHCFG_SHIFT_SAD) & CHCFG_MASK_SAD) |
+           (((uint32_t)p_ch_setup->dst_width << CHCFG_SHIFT_DDS) & CHCFG_MASK_DDS) |
+           (((uint32_t)p_ch_setup->src_width << CHCFG_SHIFT_SDS) & CHCFG_MASK_SDS) |
+           /* <-MISRA 21.1, IPA R2.4.1 */
+           p_ch_cfg->tm |
+           p_ch_cfg->lvl |
+           reqd |
+           chcfg_sel);
+
+    /* set setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = true;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_BusParam
+* Description : Set bus parameter for DMA.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t src_bus_addr = (uint32_t)p_dma_data->src_addr;
+    uint32_t dst_bus_addr = (uint32_t)p_dma_data->dst_addr;
+    uint32_t chext_value = (CHEXT_SET_DPR_NON_SECURE | CHEXT_SET_SPR_NON_SECURE);
+
+    /* set bus parameter for SRC */
+    if (DMA_EXTERNAL_BUS_END >= src_bus_addr)
+    {
+        chext_value |= CHEXT_SET_SCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_SCA_STRONG;
+    }
+
+    /* set bus parameter for DST */
+    if (DMA_EXTERNAL_BUS_END >= dst_bus_addr)
+    {
+        chext_value |= CHEXT_SET_DCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_DCA_STRONG;
+    }
+
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHEXT_n = chext_value;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_BusParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetData
+* Description : Set DMA transfer address to Register.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+*             next_register_set -
+*                  Number of next register set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                          const uint32_t next_register_set)
+{
+    if (0U == next_register_set)
+    {
+        /* set DMA transfer address parameters to next register set0 */
+        gb_info_drv.info_ch[channel].src_addr0 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr0 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count0 =    p_dma_data->count;
+
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0TB_n = p_dma_data->count;
+    }
+    else
+    {
+        /* set DMA transfer address parameters to next regiter set1 */
+        gb_info_drv.info_ch[channel].src_addr1 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr1 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count1 =    p_dma_data->count;
+
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1TB_n = p_dma_data->count;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetData
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetNextData
+* Description : Set continuous DMA transfer setting.
+* Arguments : channel -
+*                  Set continuous DMA transfer channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t  next_register_set;
+
+    /* check number of next register set for next DMA transfer */
+    /* The reverse number in current number is set in next regsiter set of next DMA. */
+    if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_SR))
+    {
+        next_register_set = 1U;
+    }
+    else
+    {
+        next_register_set = 0U;
+    }
+
+    /* set DMA transfer address for next DMA */
+    DMA_SetData(channel, p_dma_data, next_register_set);
+
+    /* start setting for next DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)(CHCFG_SET_REN | CHCFG_SET_RSW);
+
+    /* set flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = true;
+
+    /* auto restart continous DMA */
+    if ((0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN)) &&
+        (false == gb_info_drv.info_ch[channel].setup_flag))
+    {
+        /* auto restart DMA */
+        DMA_SetData(channel, p_dma_data, 0);
+        DMA_Start(channel, true);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Nextdata
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Start
+* Description : Start DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*           :restart_flag -
+*                  Flag of DMA continous transfer auto restart.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Start(const int_t channel, const bool_t restart_flag)
+{
+    if (false != restart_flag)
+    {
+        /* clear continous DMA setting */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &=
+        ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL | CHCFG_SET_REN);
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+    }
+
+    /* clear setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = false;
+
+    /* reset DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SWRST;
+
+    /* clear mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~((uint32_t)CHCFG_SET_DEM);
+
+    GIC_EnableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+    /* start DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SETEN;
+
+    /* set channel status to DMA_CH_TRANSFER */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_TRANSFER;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Start
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Stop
+* Description : Stop DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*             *p_remain -
+*                  Remain data size of DMA transfer.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Stop(const int_t channel, uint32_t * const p_remain)
+{
+    uint32_t  stop_wait_cnt;
+
+    /* disable DMA end interrupt */
+    GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+    /* stop DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_CLREN;
+
+    /* wait DMA stop */
+    stop_wait_cnt = 0;
+    while ((0 != (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_TACT)) &&
+           (DMA_STOP_WAIT_MAX_CNT > stop_wait_cnt))
+    {
+        stop_wait_cnt++;
+    }
+
+    if (DMA_STOP_WAIT_MAX_CNT <= stop_wait_cnt)
+    {
+        /* NON_NOTICE_ASSERT: wait count is abnormal value (usually, a count is set to 0 or 1) */
+    }
+
+    /* get remain data size */
+    *p_remain = gb_info_drv.info_ch[channel].p_dma_ch_reg->CRTB_n;
+
+    /* set mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+
+    /* clear setting of continuous DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+
+    /* clear TC, END bit */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+
+    /* clear flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = false;
+
+    /* interrupt clear, if interrupt occured already */
+    GIC_ClearPendingIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Stop
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetErrCode
+* Description : Set error code to error code pointer.
+*               If error code pointer is NULL, nothing is done.
+* Arguments : error_code -
+*                  Error code.
+*             *p_errno -
+*                  Pointer of set error code.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetErrCode(const int_t error_code, int32_t * const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetErrCode
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_ErrInterruptHandler
+* Description : DMA error interrupt handler.
+*               Notify error information to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB member.
+******************************************************************************/
+
+static void R_DMA_ErrInterruptHandler(void)
+{
+    uint32_t dstat_er_0_7;
+    uint32_t dstat_er_8_15;
+
+    if (NULL != gb_info_drv.p_err_aio)
+    {
+        /* get error channel number */
+        dstat_er_0_7  = gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DSTAT_ER_0_7;
+        dstat_er_8_15 = gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DSTAT_ER_0_7;
+
+        /* set error infrmation */
+        gb_info_drv.p_err_aio->aio_sigevent.sigev_value.sival_int = (int_t)(dstat_er_0_7 | (dstat_er_8_15 << HIGH_COMMON_REG_OFFSET));
+
+        /* set error code (EIO_RBSP) */
+        gb_info_drv.p_err_aio->aio_return = EIO_RBSP;
+
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.p_err_aio);
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+
+}
+
+/******************************************************************************
+End of function R_DMA_ErrInteruuptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End0InterruptHandler
+* Description : DMA end interrupt handler for channel 0.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_0);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End0InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End1InterruptHandler
+* Description : DMA end interrupt handler for channel 1.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End1InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_1);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End1InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End2InterruptHandler
+* Description : DMA end interrupt handler for channel 2.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End2InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_2);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End2InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End3InterruptHandler
+* Description : DMA end interrupt handler for channel 3.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End3InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_3);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End3InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End4InterruptHandler
+* Description : DMA end interrupt handler for channel 4.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End4InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_4);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End4InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End5InterruptHandler
+* Description : DMA end interrupt handler for channel 5.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End5InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_5);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End5InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End6InterruptHandler
+* Description : DMA end interrupt handler for channel 6.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End6InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_6);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End6InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End7InterruptHandler
+* Description : DMA end interrupt handler for channel 7.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End7InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_7);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End7InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End8InterruptHandler
+* Description : DMA end interrupt handler for channel 8.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End8InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_8);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End8InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End9InterruptHandler
+* Description : DMA end interrupt handler for channel 9.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End9InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_9);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End9InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End10InterruptHandler
+* Description : DMA end interrupt handler for channel 10.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End10InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_10);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End10InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End11InterruptHandler
+* Description : DMA end interrupt handler for channel 11.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End11InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_11);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End11InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End12InterruptHandler
+* Description : DMA end interrupt handler for channel 12.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End12InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_12);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End12InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End13InterruptHandler
+* Description : DMA end interrupt handler for channel 13.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End13InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_13);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End13InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End14InterruptHandler
+* Description : DMA end interrupt handler for channel 14.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End14InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_14);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End14InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End15InterruptHandler
+* Description : DMA end interrupt handler for channel 15.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+static void R_DMA_End15InterruptHandler(void)
+{
+
+    R_DMA_EndHandlerProcess(DMA_CH_15);
+
+}
+
+/******************************************************************************
+End of function R_DMA_End15InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_EndHandlerProcess
+* Description : DMA end interrupt handler process carry out.
+*               It's processed to DMA complete and notify DMA transfer finished
+*               to the module function which called DMA driver.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+*                Note: store error code (EIO_RBSP) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO_RBSP -
+*                     DMA transfer don't stopped.
+******************************************************************************/
+
+__INLINE static void R_DMA_EndHandlerProcess(const int_t channel)
+{
+    bool_t   store_next_dma_flag;
+
+    if (NULL != gb_info_drv.info_ch[channel].p_end_aio)
+    {
+        /* disable all irq */
+        core_util_critical_section_enter();
+
+        /* store next_dma_flag */
+        store_next_dma_flag = gb_info_drv.info_ch[channel].next_dma_flag;
+
+        /* clear flag wich indicates that next DMA transfer set already */
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+
+        if (false == store_next_dma_flag)
+        {
+            /* DMA transfer complete */
+            /* mask DMA end interrupt */
+            GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+
+            /* set channel status to DMA_CH_OPEN */
+            gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+
+            /* set mask of DMA transfer end */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+
+            /* clear setting of continuous DMA */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+
+            /* check EN bit is clear */
+            if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN))
+            {
+                /* set error code (ESUCCESS) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+            }
+            else
+            {
+                /* set error code (EIO_RBSP) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = EIO_RBSP;
+            }
+        }
+        else
+        {
+            /* set next DMA already */
+            /* set error code (ESUCCESS) */
+            gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+        }
+
+        /* clear TC, END bit */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+
+        core_util_critical_section_exit();
+
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.info_ch[channel].p_end_aio);
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function R_DMA_EndHandlerProcess
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/dma/dma.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,288 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.h
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver internal headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_H
+#define DMA_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "dma_if.h"
+#include "cmsis.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Magic Number */
+#define SHIFT_DMARS_EVEN_CH      (0U)  /* Shift Value for DMARS Register access in Even ch */
+#define SHIFT_DMARS_ODD_CH       (16U) /* Shift Value for DMARS Register access in Odd ch */
+#define MASK_DMARS_EVEN_CH       (0xFFFF0000U) /* Mask value for DMARS Register in Even ch */
+#define MASK_DMARS_ODD_CH        (0x0000FFFFU) /* Mask value for DMARS Register in Odd ch */
+#define HIGH_COMMON_REG_OFFSET   (8)  /* for Common Register Access in ch 0-8 */
+#define CHECK_ODD_EVEN_MASK      (0x00000001U)  /* for check value of odd or even */
+#define DMA_STOP_WAIT_MAX_CNT    (10U) /* Loop count for DMA stop (usually, a count is set to 0 or 1) */
+
+/* Register Set Value */
+/* Init Value */
+#define N0SA_INIT_VALUE      (0U)          /* HW init value */
+#define N1SA_INIT_VALUE      (0U)          /* HW init value */
+#define N0DA_INIT_VALUE      (0U)          /* HW init value */
+#define N1DA_INIT_VALUE      (0U)          /* HW init value */
+#define N0TB_INIT_VALUE      (0U)          /* HW init value */
+#define N1TB_INIT_VALUE      (0U)          /* HW init value */
+#define CHCTRL_INIT_VALUE    (0U)          /* HW init value */
+#define CHCFG_INIT_VALUE     (0x01000000U) /* interrupt disable */
+#define CHITVL_INIT_VALUE    (0U)          /* DMA interval = 0 */
+#define CHEXT_INIT_VALUE     (0U)          /* HW init value */
+#define NXLA_INIT_VALUE      (0U)          /* HW init value */
+#define DCTRL_INIT_VALUE     (0x00000001U) /* interrupt output : pulse, round robin mode */
+#define DMARS_INIT_VALUE     (0U)          /* HW init value */
+/* Fixed Setting for CHCFG */
+#define CHCFG_FIXED_VALUE    (0x00000020U) /* register mode, not buffer sweep, interrupt detect when high pulse */
+
+/* Bit Value & Mask */
+/* CHSTAT */
+#define CHSTAT_MASK_SR         (0x00000080U)
+#define CHSTAT_MASK_END        (0x00000020U)
+#define CHSTAT_MASK_ER         (0x00000010U)
+#define CHSTAT_MASK_TACT       (0x00000004U)
+#define CHSTAT_MASK_EN         (0x00000001U)
+/* CHCTRL */
+#define CHCTRL_SET_CLRTC       (0x00000040U)
+#define CHCTRL_SET_CLREND      (0x00000020U)
+#define CHCTRL_SET_SWRST       (0x00000008U)
+#define CHCTRL_SET_CLREN       (0x00000002U)
+#define CHCTRL_SET_SETEN       (0x00000001U)
+/* CHCFG */
+#define CHCFG_SET_REN          (0x40000000U)
+#define CHCFG_MASK_REN         (0x40000000U)
+#define CHCFG_SET_RSW          (0x20000000U)
+#define CHCFG_MASK_RSW         (0x20000000U)
+#define CHCFG_SET_RSEL         (0x10000000U)
+#define CHCFG_MASK_RSEL        (0x10000000U)
+#define CHCFG_SET_DEM          (0x01000000U)
+#define CHCFG_MASK_DEM         (0x01000000U)
+#define CHCFG_MASK_DAD         (0x00200000U)
+#define CHCFG_MASK_SAD         (0x00100000U)
+#define CHCFG_MASK_DDS         (0x000f0000U)
+#define CHCFG_MASK_SDS         (0x0000f000U)
+#define CHCFG_SET_AM_LEVEL     (0x00000100U)
+#define CHCFG_SET_AM_BUS_CYCLE (0x00000200U)
+#define CHCFG_MASK_AM          (0x00000700U)
+#define CHCFG_SET_LVL_EDGE     (0x00000000U)
+#define CHCFG_SET_LVL_LEVEL    (0x00000040U)
+#define CHCFG_MASK_LVL         (0x00000040U)
+#define CHCFG_SET_REQD_SRC     (0x00000000U)
+#define CHCFG_SET_REQD_DST     (0x00000008U)
+#define CHCFG_MASK_REQD        (0x00000008U)
+#define CHCFG_SHIFT_DAD        (21U)
+#define CHCFG_SHIFT_SAD        (20U)
+#define CHCFG_SHIFT_DDS        (16U)
+#define CHCFG_SHIFT_SDS        (12U)
+/* CHEXT */
+#define CHEXT_SET_DCA_NORMAL      (0x00003000U)
+#define CHEXT_SET_DCA_STRONG      (0x00000000U)
+#define CHEXT_SET_DPR_NON_SECURE  (0x00000200U)
+#define CHEXT_SET_SCA_NORMAL      (0x00000030U)
+#define CHEXT_SET_SCA_STRONG      (0x00000000U)
+#define CHEXT_SET_SPR_NON_SECURE  (0x00000002U)
+
+
+/* REQD value in CHCFG is undecided on config table */
+/* used case of a resource is the same and two or more direction value exists.  */
+#define CHCFG_REQD_UNDEFINED   DMA_REQ_MAX
+
+/* Address of area which is the target of setting change */
+#define DMA_EXTERNAL_BUS_START         (0x00000000U)
+#define DMA_EXTERNAL_BUS_END           (0x6FFFFFFFU)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* DRV Status */
+typedef enum
+{
+    DMA_DRV_UNINIT = 0,   /* Uninit */
+    DMA_DRV_INIT   = 1    /* Init */
+} dma_stat_drv_t;
+
+/* Channel Status */
+typedef enum
+{
+    DMA_CH_UNINIT   = 0,   /* Uninit */
+    DMA_CH_INIT     = 1,   /* Init */
+    DMA_CH_OPEN     = 2,   /* Open */
+    DMA_CH_TRANSFER = 4    /* Transfer */
+} dma_stat_ch_t;
+
+struct st_dmac_n
+{
+    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
+    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
+    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
+    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
+    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
+    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
+    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
+    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
+    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
+    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
+    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
+    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
+    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
+    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
+    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
+    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
+};
+
+struct st_dmaccommon_n
+{
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy1[12];                             /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+};
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Register (Common) */
+typedef struct
+{
+    volatile uint32_t  dctrl;
+    volatile uint32_t  dstat_en;
+    volatile uint32_t  dstat_er;
+    volatile uint32_t  dstat_end;
+    volatile uint32_t  dstat_tc;
+    volatile uint32_t  dstat_sus;
+} dma_reg_common_t;
+
+/* DMA Register (every Channel) */
+typedef struct
+{
+    volatile uint32_t  n0sa;
+    volatile uint32_t  n0da;
+    volatile uint32_t  n0tb;
+    volatile uint32_t  n1sa;
+    volatile uint32_t  n1da;
+    volatile uint32_t  n1tb;
+    volatile uint32_t  crsa;
+    volatile uint32_t  crda;
+    volatile uint32_t  crtb;
+    volatile uint32_t  chstat;
+    volatile uint32_t  chctrl;
+    volatile uint32_t  chcfg;
+    volatile uint32_t  chitvl;
+    volatile uint32_t  chext;
+    volatile uint32_t  nxla;
+    volatile uint32_t  crla;
+} dma_reg_ch_t;
+
+/* Information of Channel */
+typedef struct
+{
+    int_t              ch;                /* Channel Number */
+    dma_stat_ch_t      ch_stat;           /* Channel Status */
+    dma_res_select_t   resource;          /* DMA Transfer Resource */
+    dma_req_dir_t      direction;         /* DMA Transfer Direction */
+    dma_unit_size_t    src_width;         /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     src_cnt;           /* DMA Address Count (Source) */
+    dma_unit_size_t    dst_width;         /* DMA Transfer Unit Size (Destination) */
+    dma_addr_cnt_t     dst_cnt;           /* DMA Address Count (Destination) */
+    void               *src_addr0;        /* Sorce Address (Next Register Set 0)*/
+    void               *dst_addr0;        /* Destination Address (Next Register Set 0)*/
+    uint32_t           count0;            /* DMA Transfer Size (Next Register Set 0)*/
+    void               *src_addr1;        /* Sorce Address (Next Register Set 1)*/
+    void               *dst_addr1;        /* Destination Address (Next Register Set 1)*/
+    uint32_t           count1;            /* DMA Transfer Size (Next Register Set 1)*/
+    IRQn_Type          end_irq_num;       /* DMA end interrupt number */
+    AIOCB              *p_end_aio;        /* set callback function (DMA end interrupt) */
+    bool_t             next_dma_flag;     /* Setting Flag of Continous DMA */
+    uint32_t           shift_dmars;       /* set SHIFT_DMARS_ODD_CH or SHIFT_DMARS_EVEN_CH */
+    uint32_t           mask_dmars;        /* set MASK_DMA_ODD_CH or MASK_DMARS_EVEN_CH */
+    bool_t             setup_flag;        /* incdicate called DMA_Setup() flag */
+    volatile struct st_dmac_n       *p_dma_ch_reg;     /* DMA Register for every channel */
+    volatile struct st_dmaccommon_n *p_dma_common_reg; /* DMA Register for common */
+    volatile uint32_t           *p_dma_dmars_reg;  /* DMARS Regsiter */
+} dma_info_ch_t;
+
+/* Information of Driver */
+typedef struct
+{
+    dma_stat_drv_t  drv_stat;            /* DRV Status */
+    AIOCB           *p_err_aio;          /* set callback function (DMA error interrupt) */
+    IRQn_Type       err_irq_num;         /* DMA error interrupt number */
+    dma_info_ch_t   info_ch[DMA_CH_NUM]; /* Enable Channel */
+} dma_info_drv_t;
+
+/* DMA Channel Configure Table */
+typedef struct
+{
+    dma_res_select_t   dmars;             /* Set Value for DMARS Register */
+    uint32_t           tm;                /* Set Value for TM Bit (CHCFG Register) */
+    uint32_t           lvl;               /* Set Value for LVL Bit (CHCFG Register) */
+    uint32_t           reqd;              /* Set Value for REQD (CHCFG Register) */
+} dma_ch_cfg_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void);
+dma_info_ch_t  *DMA_GetDrvChInfo(const int_t channel);
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param);
+int_t DMA_UnInitialize(void);
+int_t DMA_GetFreeChannel(void);
+int_t DMA_GetFixedChannel(const int_t channel);
+void  DMA_CloseChannel(const int_t channel);
+void  DMA_SetParam(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                   const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd);
+void  DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                 const uint32_t next_register_set);
+void  DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_Start(const int_t channel, const bool_t restart_flag);
+void  DMA_Stop(const int_t channel, uint32_t * const p_remain);
+void  DMA_SetErrCode(const int_t error_code, int32_t * const p_errno);
+
+#endif /* DMA_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/dma/dma_if.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1005 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.c
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver interface functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "dma.h"
+#include  "mbed_critical.h"
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Init
+* @brie          Init DMA driver.
+*                Check parameter in this function.
+*
+*                Description:<br>
+*
+* @param[in]     p_dma_init_param :Point of driver init parameter.
+* @param[in,out] p_errno          :Pointer of error code.
+*                                  When pointer is NULL, it isn't set error code.
+*                                  error code -
+*                                  OS error num : Registering handler failed.
+*                                  EPERM_RBSP : Pointer of callback function which called in DMA 
+*                                          error interrupt handler is NULL.
+*                                  EFAULT_RBSP : dma_init_param is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called.  */
+int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t         retval = ESUCCESS;
+    int_t         result_init;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    if (NULL == p_dma_init_param)
+    {
+        /* set error return value */
+        retval = (EERROR);
+        DMA_SetErrCode(EFAULT_RBSP, p_errno);
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+        if (NULL == p_dma_init_param->p_aio)
+        /* <-MISRA 1.2 */
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(EPERM_RBSP, p_errno);
+        }
+    }
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    if (ESUCCESS == retval)
+    {
+        result_init = DMA_Initialize(p_dma_init_param);
+        if (ESUCCESS != result_init)
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(result_init, p_errno);
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Init
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_UnInit
+* @brie          UnInit DMA driver.
+*                Check parameter in this function.
+*
+*                Description:<br>
+*
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           OS error num : Unegistering handler failed.
+*                           EACCES_RBSP : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY_RBSP : It has been allocated already in channel.
+*                           EFAULT_RBSP : Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_UnInit(int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    int_t          result_uninit;
+    dma_info_drv_t *dma_info_drv;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          ch_count;
+    bool_t         ch_stat_check_flag;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    dma_info_drv = DMA_GetDrvInstance();
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check driver status */
+    if (ESUCCESS == retval)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EACCES_RBSP, p_errno);
+        }
+        else
+        {
+            ch_stat_check_flag = false;
+            ch_count = 0;
+            while (false == ch_stat_check_flag)
+            {
+                /* check channel status */
+                dma_info_ch = DMA_GetDrvChInfo(ch_count);
+                if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
+                    (DMA_CH_INIT != dma_info_ch->ch_stat))
+                {
+                    /*  set error return value */
+                    retval = EERROR;
+                    /* check channel status is busy */
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        /* These 2 cases are intentionally combined. */
+                        case DMA_CH_OPEN:
+                        case DMA_CH_TRANSFER:
+                            DMA_SetErrCode(EBUSY_RBSP, p_errno);
+                        break;
+
+                        default:
+                            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+                        break;
+                    }
+                }
+
+                if ((DMA_CH_NUM - 1) == ch_count)
+                {
+                    /* channel status check end */
+                    ch_stat_check_flag = true;
+                }
+                ch_count++;
+            }
+        }
+        /* uninitialize DMA */
+        if (ESUCCESS == retval)
+        {
+            result_uninit = DMA_UnInitialize();
+            if (ESUCCESS != result_uninit)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(result_uninit, p_errno);
+            }
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_UnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Alloc
+* @brie          Open DMA channel.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Open channel number.
+*                           If channel is (-1), it looking for free chanel and allocate.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EINVAL_RBSP : Value of the ch is outside the range of DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
+*                           EACCES_RBSP : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY_RBSP : It has been allocated already in channel.
+*                           EMFILE_RBSP : When looking for a free channel, but a free channel didn't exist.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    int_t           ercd = ESUCCESS;
+    int_t           get_ch_num;
+    dma_info_drv_t  *dma_info_drv;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* check driver status */
+    dma_info_drv = DMA_GetDrvInstance();
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    if (ESUCCESS == ercd)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            ercd =  EACCES_RBSP;
+        }
+        else
+        {
+            /* check channel of argment */
+            if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
+            {
+                if (DMA_ALLOC_CH == channel)
+                {
+                    get_ch_num = DMA_GetFreeChannel();
+                }
+                else
+                {
+                    get_ch_num = DMA_GetFixedChannel(channel);
+                }
+
+                /* check return number or error number */
+                if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
+                {
+                    /* set channel number to return value */
+                    retval = get_ch_num;
+                }
+                else
+                {
+                    /* set error code to error value */
+                    ercd = get_ch_num;
+                }
+            }
+            else
+            {
+                /* set error return value */
+                ercd =  EINVAL_RBSP;
+            }
+        }
+    }
+
+    /* occured error check */
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+        DMA_SetErrCode(ercd, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Alloc
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Free
+* @brie          Close DMA channel.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Close channel number.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EACCES_RBSP : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY_RBSP : It has been start DMA transfer in channel.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    dma_info_drv_t  *dma_info_drv;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+         /* check driver status */
+        dma_info_drv = DMA_GetDrvInstance();
+
+        if (ESUCCESS == retval)
+        {
+            /* check driver status */
+            if (DMA_DRV_INIT == dma_info_drv->drv_stat)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        DMA_CloseChannel(channel);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                            break;
+
+                            case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                            break;
+
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+            else
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EACCES_RBSP, p_errno);
+
+            }
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Free
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Setup
+* @brie          Setup DMA transfer parameter.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Setup channel number.
+* @param[in]     p_ch_setup:Set up parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY_RBSP : It has been start DMA transfer in channel.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EPERM_RBSP : The value in p_ch_setup isn't in the right range.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_ch_setup is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t            retval = ESUCCESS;
+    dma_info_ch_t    *dma_info_ch;
+    int_t            error_code;
+    uint32_t         cfg_table_count;
+    dma_ch_cfg_t     ch_cfg_set_table;
+    uint32_t         set_reqd;
+    bool_t           check_table_flag;
+
+    /* Resouce Configure Set Table */
+    static const dma_ch_cfg_t ch_cfg_table[] =
+    {
+        {DMA_RS_SSITXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI2,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI3,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI3,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+
+        {DMA_RS_SPDIFRXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPDIFTXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+    };
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    /* dummy init set_reqd */
+    set_reqd = CHCFG_REQD_UNDEFINED;
+    ch_cfg_set_table = ch_cfg_table[0];
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_ch_setup)
+        {
+            /* check setup parameter */
+            /* check AIOCB pointer */
+            if (NULL == p_ch_setup->p_aio)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM_RBSP, p_errno);
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for destination */
+                if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) ||
+                    ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for source */
+                if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) ||
+                    ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for destination */
+                if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) ||
+                    ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for source */
+                if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) ||
+                    ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer direction */
+                if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) ||
+                    ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM_RBSP, p_errno);
+                }
+            }
+
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer resouce */
+                check_table_flag = false;
+                cfg_table_count = 0;
+                while (false == check_table_flag)
+                {
+                    if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
+                    {
+                        /* check reqd is undefined */
+                        if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
+                        {
+                            /* set reqd value on fixed value */
+                            if (DMA_REQ_SRC == p_ch_setup->direction)
+                            {
+                                set_reqd = CHCFG_SET_REQD_SRC;
+                            }
+                            else
+                            {
+                                set_reqd = CHCFG_SET_REQD_DST;
+                            }
+                        }
+                        else
+                        {
+                            /* set reqd value in channel config table */
+                            set_reqd = ch_cfg_table[cfg_table_count].reqd;
+                        }
+                        /* set channel config table address for DMA_SetParam() */
+                        ch_cfg_set_table = ch_cfg_table[cfg_table_count];
+                        check_table_flag = true;
+                    }
+                    if (false == check_table_flag)
+                    {
+                        /* resource value did not exist in channel config table */
+                        if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EPERM_RBSP, p_errno);
+                            check_table_flag = true;
+                        }
+                        cfg_table_count++;
+                    }
+                }
+            }
+
+            /* disable all irq */
+            core_util_critical_section_enter();
+
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set up parameter */
+                        DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                            break;
+
+                            case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                            break;
+
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+
+            core_util_critical_section_exit();
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_SetParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Start
+* @brie          Start DMA transfer.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :DMA start channel number.
+* @param[in]     p_dma_data:DMA address parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY_RBSP : It has been start DMA transfer in channel.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EPERM_RBSP : The value in p_ch_setup isn't in the right range.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM_RBSP, p_errno);
+            }
+
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set bus paramter for DMA */
+                        DMA_BusParam(channel, p_dma_data);
+                        /* set up address parameter */
+                        /* Next register set is 0 */
+                        DMA_SetData(channel, p_dma_data, 0);
+                        /* DMA transfer start */
+                        DMA_Start(channel, false);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                             break;
+
+                             case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                             break;
+
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                             break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Start
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_NextData
+* @brie          Set continous DMA mode.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Continuous DMA channel number.
+* @param[in,out] p_dma_data:DMA address parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT.
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY_RBSP : It has been set continous DMA transfer.
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EPERM_RBSP : The value in p_ch_setup isn't in the right range.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data,
+                     int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM_RBSP, p_errno);
+            }
+
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+
+                if (ESUCCESS == retval)
+                {
+                    if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
+                        (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
+                    {
+                        if (false == dma_info_ch->next_dma_flag)
+                        {
+                            /* set up address parameter for continous DMA*/
+                            DMA_SetNextData(channel, p_dma_data);
+                        }
+                        else
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EBUSY_RBSP, p_errno);
+                        }
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP_RBSP;
+                            break;
+
+                            case DMA_CH_INIT:
+                                error_code = EBADF_RBSP;
+                            break;
+
+                            default:
+                                error_code = EFAULT_RBSP;
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_NextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Cancel
+* @brie          Cancel DMA transfer.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Cancel DMA channel number.
+* @param[in]    p_remain   :Remain data size of DMA transfer when it stopping.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF_RBSP : Channel status is DMA_CH_INIT or DMA_CH_OPEN. (DMA stopped)
+*                           EINVAL_RBSP : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           ENOTSUP_RBSP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT_RBSP: Channel status is besides the status definded in dma_stat_ch_t. p_remain is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+    core_util_critical_section_enter();
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        /* check whether p_remain is NULL */
+        if (NULL != p_remain)
+        {
+            dma_info_ch = DMA_GetDrvChInfo(channel);
+
+            if (ESUCCESS == retval)
+            {
+                if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
+                {
+                    /* set up address parameter for continous DMA*/
+                    DMA_Stop(channel, p_remain);
+                }
+                else
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        case DMA_CH_UNINIT:
+                            error_code = ENOTSUP_RBSP;
+                        break;
+
+                        case DMA_CH_INIT:
+                            error_code = EBADF_RBSP;
+                        break;
+
+                        case DMA_CH_OPEN:
+                            error_code = EBADF_RBSP;
+                        break;
+
+                        default:
+                            error_code = EFAULT_RBSP;
+                        break;
+                    }
+                    DMA_SetErrCode(error_code, p_errno);
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT_RBSP, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL_RBSP, p_errno);
+    }
+
+    core_util_critical_section_exit();
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Cancel
+******************************************************************************/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/dma/dma_ver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         dma_ver.c
+* $Rev: $
+* $Date::                           $
+* @brief        DMA Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "dma_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define DMA_DRV_VER_MAJOR  (2u)
+#define DMA_DRV_VER_MINOR  (2u)
+
+#define DMA_DRV_VER_MASK   (0xFFu)
+#define DMA_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_GetVersion
+* @brief         Get DMA driver version.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_DMA_GetVersion(void)
+{
+    const uint16_t version =
+        ((DMA_DRV_VER_MAJOR & DMA_DRV_VER_MASK) << DMA_DRV_VER_SHIFT)
+        | (DMA_DRV_VER_MINOR & DMA_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_DMA_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/mmu/mmu_init.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,51 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mmu_init.c
+* $Rev: 175 $
+* $Date:: 2017-12-22 19:13:06 +0900#$
+* Description :
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "mmu_init.h"
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_MMU_VAtoPA
+* Description  : Convert virtual address to physical address
+* Arguments    : uint32_t   vaddr  ; I : virtual address to be convert
+* Return Value : physical address
+******************************************************************************/
+uint32_t R_MMU_VAtoPA(uint32_t vaddr)
+{
+    return vaddr;
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/mmu/mmu_init.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,38 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mmu_init.h
+* $Rev: 175 $
+* $Date:: 2017-12-22 19:13:06 +0900#$
+* Description :
+******************************************************************************/
+#ifndef __MMU_INIT_H
+#define __MMU_INIT_H
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+extern uint32_t R_MMU_VAtoPA( uint32_t address );
+
+#endif /* __MMU_INIT_H */
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/spdif/spdif.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1368 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : spdif.c
+* $Rev: $
+* $Date::                           $
+* Description : SPDIF driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "spdif.h"
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "cmsis.h"
+#include "mbed_critical.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* SPDIF CTRL Register VALUE */
+/* b21     RDE      - Receiver DMA Enable                         - 0  : Disable             */
+/* b20     TDE      - Transmitter DMA Enable                      - 0  : Disable             */
+/* b19     NCSI     - New Channel Status Information              - 0  : Not present         */
+/* b18     AOS      - Audio Only Samples                          - 1  : Not user data       */
+/* b17     RME      - Receiver Module Enable                      - 0  : Disable             */
+/* b16     TME      - Transmitter Module Enable                   - 0  : Disable             */
+/* b15     REIE     - Receiver Error Interrupt Enable             - 1  : Enable              */
+/* b14     TEIE     - Transmitter Error Interrupt Enable          - 1  : Enable              */
+/* b13     UBOI     - User Buffer Overrun Interrupt Enable        - 1  : Enable              */
+/* b12     UBUI     - User Buffer Underrun Interrupt Enable       - 1  : Enable              */
+/* b11     CREI     - Clock Recovery Error Interrupt Enable       - 1  : Enable              */
+/* b10     PAEI     - Parity Error Interrupt Enable               - 1  : Enable              */
+/* b9      PREI     - Preamble Error Interrupt Enable             - 1  : Enable              */
+/* b8      CSEI     - Channel Status Error Interrupt Enable       - 1  : Enable              */
+/* b7      ABOI     - Audio Buffer Overrun Interrupt Enable       - 1  : Enable              */
+/* b6      ABUI     - Audio Buffer Underrun Interrupt Enable      - 1  : Enable              */
+/* b5      RUII     - Receiver User Information Interrupt Enable  - 0  : Disable             */
+/* b4      TUII     - Transmitter User Information Interrupt Enable 0  : Disable             */
+/* b3      RCSI     - Receiver Channel Status Interrupt Enable    - 0  : Disable             */
+/* b2      RCBI     - Receiver Channel Buffer Interrupt Enable    - 0  : Disable             */
+/* b1      TCSI     - Transmitter Channel Status Interrupt Enable - 0  : Disable             */
+/* b0      TCBI     - Transmitter Channel Buffer Interrupt Enable - 0  : Disable             */
+#define SPDIF_CTRL_BASE_INIT_VALUE  (0x0004FFC0uL)
+
+
+#define SPDIF_UPDATA_WAIT   (250u)
+
+    /* Status Register
+    b31:b30 Reserved - Read only bit       - 00:
+    b29:b28 CLAC     - Clock Accuracy      - 01:   Level 1 (50 ppm)
+    b27:b24 FS       - Sample Frequency    - 0000: 44.1kHz
+    b23:b20 CHNO     - Channel Number      - 0001: Left (0010: Right)
+    b19:b16 SRCNO    - Source Number       - 0000:
+    b15:b8  CATCD    - Category Code       - 00000000: General 2-channel format
+    b7:b6   Reserved - Read only bit       - 00: 
+    b5:b1   CTL      - Control             - 0:  2 channel Audio, 
+                                             00: Disable preemphasis
+                                             0:  Disable copy
+                                             0:  LPCM
+    b0      Reserved - Read only bit       - 0: */
+#define SPDIF_STATUS_LCH                    (0x10100000u)
+#define SPDIF_STATUS_RCH                    (0x10200000u)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+/* ->MISRA 8.8, MISRA 8.10, IPA M2.2.2 : These declare statements are dependent on CMSIS-RTOS */
+osSemaphoreDef(spdif_ch0_access);
+/* <-MISRA 8.8, MISRA 8.10, IPA M2.2.2 */
+
+#if(1) /* mbed */
+static spdif_info_drv_t g_spdif_info_drv;
+
+spdif_info_drv_t * SPDIF_GetDrvInstanc(void) {
+    return &g_spdif_info_drv;
+}
+#else
+spdif_info_drv_t g_spdif_info_drv;
+#endif
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static int_t SPDIF_InitChannel(spdif_info_ch_t* const p_info_ch);
+static void SPDIF_UnInitChannel(spdif_info_ch_t* const p_info_ch);
+static int_t SPDIF_SetCtrlParams(const spdif_info_ch_t* const p_info_ch);
+static int_t SPDIF_CheckChannelCfg(const spdif_channel_cfg_t* const p_ch_cfg);
+static void SPDIF_Handler(void);
+static void SPDIF_UserInfoRegSetWait(void);
+static void SPDIF_ChannelStatusRegSet(const spdif_info_ch_t* const p_info_ch);
+static void SPDIF_ChannelStatusRegSetWait(void);
+static void SPDIF_ChannelStatusRegGet(spdif_info_ch_t* const p_info_ch);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: SPDIF_InitialiseOne
+* @brief         Initialize the SPDIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     channel    :channel number
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_InitialiseOne(const int_t channel, const spdif_channel_cfg_t* const p_cfg_data)
+{
+    int_t           ercd = ESUCCESS;
+    spdif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else if (false == p_cfg_data->enabled)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        p_info_ch = &g_spdif_info_drv.info_ch;
+        p_info_ch->enabled = p_cfg_data->enabled;
+
+        /* copy config data to channel info */
+        ercd = SPDIF_CheckChannelCfg(p_cfg_data);
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->clk_select         = p_cfg_data->clk_select;
+            p_info_ch->audio_bit_tx       = p_cfg_data->audio_bit_tx;
+            p_info_ch->audio_bit_rx       = p_cfg_data->audio_bit_rx;
+            p_info_ch->int_level          = p_cfg_data->int_level;
+            p_info_ch->tx_u_data_enabled  = p_cfg_data->tx_u_data_enabled;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SPDIF_InitChannel(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            InterruptHandlerRegister(SPDIFI_IRQn, &SPDIF_Handler);
+            GIC_SetPriority(SPDIFI_IRQn, p_cfg_data->int_level);
+            GIC_EnableIRQ(SPDIFI_IRQn);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_UnInitialiseOne
+* @brief         UnInitialize the SPDIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     channel    :channel number
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SPDIF_UnInitialiseOne(const int_t channel)
+{
+    const int_t     ercd = ESUCCESS;
+    spdif_info_ch_t* p_info_ch;
+
+    p_info_ch = &g_spdif_info_drv.info_ch;
+
+    if (false != p_info_ch->enabled)
+    {
+        SPDIF_UnInitChannel(p_info_ch);
+    }
+
+    return ercd;
+}
+#else
+/******************************************************************************
+* Function Name: SPDIF_Initialise
+* @brief         Initialize the SPDIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_Initialise(const spdif_channel_cfg_t* const p_cfg_data)
+{
+    int_t           ercd = ESUCCESS;
+    spdif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        p_info_ch = &g_spdif_info_drv.info_ch;
+        p_info_ch->enabled = p_cfg_data.enabled;
+
+        if (false != p_info_ch->enabled)
+        {
+            /* copy config data to channel info */
+            ercd = SPDIF_CheckChannelCfg(p_ch_cfg);
+            if (ESUCCESS == ercd)
+            {
+                p_info_ch->clk_select         = p_cfg_data->clk_select;
+                p_info_ch->audio_bit_tx       = p_cfg_data->audio_bit_tx;
+                p_info_ch->audio_bit_rx       = p_cfg_data->audio_bit_rx;
+                p_info_ch->int_level          = p_cfg_data->int_level;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                ercd = SPDIF_InitChannel(p_info_ch);
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch = &g_spdif_info_drv.info_ch;
+
+            if (false != p_info_ch->enabled)
+            {
+                InterruptHandlerRegister(SPDIFI_IRQn, &SPDIF_Handler);
+                GIC_SetPriority(SPDIFI_IRQn, p_cfg_data.int_level);
+                GIC_EnableIRQ(SPDIFI_IRQn);
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_UnInitialise
+* @brief         UnInitialize the SPDIF driver's internal data
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SPDIF_UnInitialise(void)
+{
+    const int_t     ercd = ESUCCESS;
+    spdif_info_ch_t* p_info_ch;
+
+    p_info_ch = &g_spdif_info_drv.info_ch;
+
+    if (false != p_info_ch->enabled)
+    {
+        SPDIF_UnInitChannel(p_info_ch);
+    }
+
+    return ercd;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: SPDIF_EnableChannel
+* @brief         Enable the SPDIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_EnableChannel(spdif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    volatile uint8_t dummy_buf_8;
+    volatile uint32_t dummy_buf_32;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* enable the SPDIF clock */
+        if (ESUCCESS == ercd)
+        {
+            core_util_critical_section_enter();
+
+            /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+            CPG.STBCR9.BYTE &= (uint8_t)~0x02;
+            /* <-IPA R2.4.2 */
+            dummy_buf_8 = CPG.STBCR9.BYTE;
+            (void)dummy_buf_8;
+
+            core_util_critical_section_exit();
+        }
+
+        /* configure channel hardware */
+        if (ESUCCESS == ercd)
+        {
+            /* Set control parameters */
+            ercd = SPDIF_SetCtrlParams(p_info_ch);
+        }
+
+
+        if (O_RDONLY_RBSP != p_info_ch->openflag)
+        {
+            /* ==== Disable interrupt ==== */
+            /* ----  Disable interrupt (User data empty) ----  */
+            SPDIF.CTRL.BIT.TUII = 0;
+
+            /* ----  Disable interrupt (Channel Status empty) ----  */
+            SPDIF.CTRL.BIT.TCSI = 0;
+
+            /* ==== SPDIF Tx Enable ==== */
+            SPDIF.CTRL.BIT.TME = 1;
+
+            /* ==== Channel status information ==== */
+            /* Be sure to write data in the order of (1) TLCS and TRCS and (2) TUI. */
+            /* Write to the data register */
+            SPDIF_ChannelStatusRegSet(p_info_ch);
+            SPDIF_ChannelStatusRegSetWait();
+
+            /* ==== User information ==== */
+            /* ---- Enable user information ---- */
+            if (p_info_ch->tx_u_data_enabled == false)
+            {
+                SPDIF.CTRL.BIT.AOS = 1;
+            }
+            else
+            {
+                SPDIF.CTRL.BIT.AOS = 0;
+            }
+
+            /* ==== Enable interrupt ==== */
+            /* ----  Enable interrupt (Channel Status empty) ----  */
+            SPDIF.CTRL.BIT.TCSI = 1;
+
+            /* ----  Enable interrupt (User data empty) ----  */
+            SPDIF.CTRL.BIT.TUII = 1;
+        }
+
+        if (O_WRONLY_RBSP != p_info_ch->openflag)
+        {
+            /* ==== Status Clear(dummy read) ==== */
+            dummy_buf_32 = SPDIF.RUI.LONG;
+            dummy_buf_32 = SPDIF.RLCS.LONG;
+            dummy_buf_32 = SPDIF.RRCS.LONG;
+            dummy_buf_32 = SPDIF.RDAD.LONG;
+            (void)dummy_buf_32;
+
+            /* ==== Enable interrupt ==== */
+            /* ---- Enable interrupt (Channel Status full) ---- */
+            SPDIF.CTRL.BIT.RCSI = 1;
+
+            /* ----  Enable interrupt (User data full) ----  */
+            SPDIF.CTRL.BIT.RUII = 1;
+
+            SPDIF.CTRL.BIT.RDE = 1;
+            SPDIF.CTRL.BIT.RME = 1;
+        }
+
+        /* allocate and setup/start DMA transfer */
+        if (ESUCCESS == ercd)
+        {
+            ercd = SPDIF_InitDMA(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_DisableChannel
+* @brief         Disable the SPDIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_DisableChannel(spdif_info_ch_t* const p_info_ch)
+{
+    int_t   ret = ESUCCESS;
+    volatile uint8_t dummy_buf_8;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ---- Reset the register ---- */
+        /* STAT - Status Register  */
+        /* CTRL - Control Register */
+        SPDIF.STAT.LONG = 0x00000000;
+        SPDIF.CTRL.LONG = 0x00000000;
+
+        /* free DMA resources */
+        SPDIF_UnInitDMA(p_info_ch);
+
+        /* disable spdif clock */
+        core_util_critical_section_enter();
+
+        /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+        CPG.STBCR9.BYTE |= (uint8_t)0x02;
+        /* <-IPA R2.4.2 */
+        dummy_buf_8 = CPG.STBCR9.BYTE;
+        (void)dummy_buf_8;
+        core_util_critical_section_exit();
+
+        /* cancel event to ongoing request */
+        if (NULL != p_info_ch->p_aio_tx_curr)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_tx_curr->aio_return = -1;
+#else
+            p_info_ch->p_aio_tx_curr->aio_return = ECANCELED;
+#endif
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+            p_info_ch->p_aio_tx_curr = NULL;
+        }
+        if (NULL != p_info_ch->p_aio_tx_next)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_tx_next->aio_return = -1;
+#else
+            p_info_ch->p_aio_tx_next->aio_return = ECANCELED;
+#endif
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+            p_info_ch->p_aio_tx_next = NULL;
+        }
+        if (NULL != p_info_ch->p_aio_rx_curr)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_rx_curr->aio_return = -1;
+#else
+            p_info_ch->p_aio_rx_curr->aio_return = ECANCELED;
+#endif
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+            p_info_ch->p_aio_rx_curr = NULL;
+        }
+        if (NULL != p_info_ch->p_aio_rx_next)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_rx_next->aio_return = -1;
+#else
+            p_info_ch->p_aio_rx_next->aio_return = ECANCELED;
+#endif
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+            p_info_ch->p_aio_rx_next = NULL;
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_ErrorRecovery
+* @brief         Restart the SPDIF channel
+*
+*                Description:<br>
+*                When normal mode<br>
+*                  Stop and restart DMA transfer.<br>
+*                When ROMDEC direct input mode<br>
+*                  Stop DMA transfer, and execute callback function.<br>
+*                Note: This function execute in interrupt context.
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+void SPDIF_ErrorRecovery_tx(spdif_info_ch_t* const p_info_ch)
+{
+    int_t   ercd = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* disable DMA end interrupt */
+        SPDIF.CTRL.LONG &= ~(SPDIF_CTRL_TME | SPDIF_CTRL_TDE);
+
+        /* pause DMA transfer */
+        SPDIF_CancelDMA(p_info_ch, O_WRONLY_RBSP);
+
+        /* cancel event to ongoing request */
+        if (NULL != p_info_ch->p_aio_tx_curr)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_tx_curr->aio_return = -1;
+#else
+            p_info_ch->p_aio_tx_curr->aio_return = EIO;
+#endif
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+            p_info_ch->p_aio_tx_curr = NULL;
+        }
+        if (NULL != p_info_ch->p_aio_tx_next)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_tx_next->aio_return = -1;
+#else
+            p_info_ch->p_aio_tx_next->aio_return = EIO;
+#endif
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+            p_info_ch->p_aio_tx_next = NULL;
+        }
+
+        /* setup/restart DMA transfer */
+        ercd = SPDIF_RestartDMA(p_info_ch, O_WRONLY_RBSP);
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        /* NON_NOTICE_ASSERT: cannot restart channel */
+    }
+
+    return;
+}
+
+void SPDIF_ErrorRecovery_rx(spdif_info_ch_t* const p_info_ch)
+{
+    int_t   ercd = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* disable DMA end interrupt */
+        SPDIF.CTRL.LONG &= ~(SPDIF_CTRL_RME | SPDIF_CTRL_RDE);
+
+        /* pause DMA transfer */
+        SPDIF_CancelDMA(p_info_ch, O_RDONLY_RBSP);
+
+        /* cancel event to ongoing request */
+        if (NULL != p_info_ch->p_aio_rx_curr)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_rx_curr->aio_return = -1;
+#else
+            p_info_ch->p_aio_rx_curr->aio_return = EIO;
+#endif
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+            p_info_ch->p_aio_rx_curr = NULL;
+        }
+        if (NULL != p_info_ch->p_aio_rx_next)
+        {
+#if(1) /* mbed */
+            p_info_ch->p_aio_rx_next->aio_return = -1;
+#else
+            p_info_ch->p_aio_rx_next->aio_return = EIO;
+#endif
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+            p_info_ch->p_aio_rx_next = NULL;
+        }
+        /* setup/restart DMA transfer */
+        ercd = SPDIF_RestartDMA(p_info_ch, O_RDONLY_RBSP);
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        /* NON_NOTICE_ASSERT: cannot restart channel */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_PostAsyncIo
+* @brief         Enqueue asynchronous read/write request
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block of read/write request
+* @retval        none
+******************************************************************************/
+void SPDIF_PostAsyncIo(spdif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if ((SPDIF_ASYNC_W == p_aio->aio_return)
+         || (SPDIF_ASYNC_STRUCT_W == p_aio->aio_return))
+        {
+            ahf_addtail(&p_info_ch->tx_que, p_aio);
+        }
+        else if ((SPDIF_ASYNC_R == p_aio->aio_return)
+              || (SPDIF_ASYNC_STRUCT_R == p_aio->aio_return))
+        {
+            ahf_addtail(&p_info_ch->rx_que, p_aio);
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: illegal request type */
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_PostAsyncCancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block to cancel or NULL to cancel all.
+* @retval        none
+******************************************************************************/
+void SPDIF_PostAsyncCancel(spdif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    int32_t ioif_ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (NULL == p_aio)
+        {
+            ahf_cancelall(&p_info_ch->tx_que);
+            ahf_cancelall(&p_info_ch->rx_que);
+        }
+        else
+        {
+            ioif_ret = ahf_cancel(&p_info_ch->tx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+
+            ioif_ret = ahf_cancel(&p_info_ch->rx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_IOCTL_ConfigChannel
+* @brief         Save configuration to the SPDIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SPDIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_IOCTL_ConfigChannel(spdif_info_ch_t* const p_info_ch,
+                                const spdif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t    ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* stop DMA transfer */
+        ercd = SPDIF_DisableChannel(p_info_ch);
+
+        if (ESUCCESS == ercd)
+        {
+            /* copy config data to channel info */
+            ercd = SPDIF_CheckChannelCfg(p_ch_cfg);
+            if (ESUCCESS == ercd)
+            {
+                p_info_ch->clk_select         = p_ch_cfg->clk_select;
+                p_info_ch->audio_bit_tx       = p_ch_cfg->audio_bit_tx;
+                p_info_ch->audio_bit_rx       = p_ch_cfg->audio_bit_rx;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* restart DMA transfer */
+            ercd = SPDIF_EnableChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_IOCTL_SetChannelStatus
+* @brief         Set a value of Channel Status.
+*
+*                Description:<br>
+*
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_IOCTL_SetChannelStatus(spdif_info_ch_t* const p_info_ch,
+                                   spdif_channel_status_t* const p_channel_status)
+{
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_channel_status))
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        p_info_ch->ch_sts[0] = p_channel_status->Lch;
+        p_info_ch->ch_sts[1] = p_channel_status->Rch;
+        ahf_addtail(&p_info_ch->tx_que, &p_info_ch->s_aio_set_ch_sts);
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_IOCTL_SetChannelStatus
+* @brief         Get a value of Channel Status.
+*
+*                Description:<br>
+*
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_IOCTL_GetChannelStatus(spdif_info_ch_t* const p_info_ch,
+                                   spdif_channel_status_t* const p_channel_status)
+{
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_channel_status))
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        p_channel_status->Lch = p_info_ch->rlcs;
+        p_channel_status->Rch = p_info_ch->rrcs;
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_IOCTL_SetTransAudioBit
+* @brief         Set a value of Channel Status.
+*
+*                Description:<br>
+*
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_IOCTL_SetTransAudioBit(spdif_info_ch_t* const p_info_ch,
+                                   spdif_chcfg_audio_bit_t sudio_bit)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        switch (sudio_bit)
+        {
+        case SPDIF_CFG_AUDIO_BIT_16:
+            /* fall through */
+        case SPDIF_CFG_AUDIO_BIT_20:
+            /* fall through */
+        case SPDIF_CFG_AUDIO_BIT_24:
+            /* do nothing */
+            break;
+        default:
+            ret = EINVAL_RBSP;
+            break;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            p_info_ch->audio_bit_tx = sudio_bit;
+            SPDIF.CTRL.BIT.TASS = p_info_ch->audio_bit_tx;
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_IOCTL_SetRecvAudioBit
+* @brief         Set a value of Channel Status.
+*
+*                Description:<br>
+*
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_IOCTL_SetRecvAudioBit(spdif_info_ch_t* const p_info_ch,
+                                   spdif_chcfg_audio_bit_t sudio_bit)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        switch (sudio_bit)
+        {
+        case SPDIF_CFG_AUDIO_BIT_16:
+            /* fall through */
+        case SPDIF_CFG_AUDIO_BIT_20:
+            /* fall through */
+        case SPDIF_CFG_AUDIO_BIT_24:
+            /* do nothing */
+            break;
+        default:
+            ret = EINVAL_RBSP;
+            break;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            p_info_ch->audio_bit_rx = sudio_bit;
+            SPDIF.CTRL.BIT.RASS = p_info_ch->audio_bit_rx;
+        }
+    }
+
+    return ret;
+}
+
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SPDIF_InitChannel
+* @brief         Initialize for the SPDIF channel
+*
+*                Description:<br>
+*                Create semaphore and queue for channel.<br>
+*                And setup SPDIF pin.
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SPDIF_InitChannel(spdif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    int_t ercd = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* Create sem_access semaphore */
+        p_info_ch->sem_access = osSemaphoreNew(0xffff, 1, osSemaphore(spdif_ch0_access));
+
+        if (NULL == p_info_ch->sem_access)
+        {
+            ercd = ENOMEM_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->tx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->rx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* set channel initialize */
+            p_info_ch->openflag = 0;
+
+            p_info_ch->p_aio_tx_curr = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_tx_next = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_rx_curr = NULL;       /* rx request pointer */
+            p_info_ch->p_aio_rx_next = NULL;       /* rx request pointer */
+
+            p_info_ch->tlcs = SPDIF_STATUS_LCH;
+            p_info_ch->trcs = SPDIF_STATUS_RCH;
+            p_info_ch->rlcs = 0;
+            p_info_ch->rrcs = 0;
+
+            p_info_ch->s_aio_set_ch_sts.aio_fildes = 0;
+            p_info_ch->s_aio_set_ch_sts.aio_buf    = &p_info_ch->ch_sts[0];
+            p_info_ch->s_aio_set_ch_sts.aio_nbytes = 0;
+            p_info_ch->s_aio_set_ch_sts.aio_offset = 0;
+            p_info_ch->s_aio_set_ch_sts.aio_return = SPDIF_ASYNC_SET_CH_STS;
+            p_info_ch->s_aio_set_ch_sts.aio_sigevent.sigev_notify = SIGEV_NONE;
+            p_info_ch->s_aio_set_ch_sts.aio_sigevent.sigev_value.sival_ptr = (void*)NULL;
+            p_info_ch->s_aio_set_ch_sts.aio_sigevent.sigev_notify_function = NULL;
+            p_info_ch->ch_sts_set_req = false;
+            p_info_ch->ch_sts[0] = SPDIF_STATUS_LCH;
+            p_info_ch->ch_sts[1] = SPDIF_STATUS_RCH;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = R_SPDIF_Userdef_InitPinMux();
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->ch_stat = SPDIF_CHSTS_INIT;
+        }
+        else
+        {
+            if (NULL != p_info_ch->sem_access)
+            {
+                os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+                if (osOK != os_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected semaphore error */
+                }
+                p_info_ch->sem_access = NULL;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_UnInitChannel
+* @brief         Uninitialise the SPDIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+static void SPDIF_UnInitChannel(spdif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        p_info_ch->ch_stat = SPDIF_CHSTS_UNINIT;
+
+        SPDIF.CTRL.LONG = 0;
+
+        core_util_critical_section_enter();
+
+        /* delete the tx queue */
+        ahf_cancelall(&p_info_ch->tx_que);
+        ahf_destroy(&p_info_ch->tx_que);
+
+        /* delete the rx queue */
+        ahf_cancelall(&p_info_ch->rx_que);
+        ahf_destroy(&p_info_ch->rx_que);
+
+        /* delete the private semaphore */
+        os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+        if (osOK != os_ret)
+        {
+            /* NON_NOTICE_ASSERT: unexpected semaphore error */
+        }
+
+        GIC_DisableIRQ(SPDIFI_IRQn);
+        InterruptHandlerUnregister(SPDIFI_IRQn);
+
+        core_util_critical_section_exit();
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_SetCtrlParams
+* @brief         Set SPDIF configuration to hardware.
+*
+*                Description:<br>
+*                Update SSICR register.
+* @param[in]     p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SPDIF_SetCtrlParams(const spdif_info_ch_t* const p_info_ch)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ---- Reset the register ---- */
+        /* STAT - Status Register  */
+        /* CTRL - Control Register */
+        SPDIF.STAT.LONG = 0x00000000;
+        SPDIF.CTRL.LONG = 0x00000000;
+
+        /* ---- CTRL Register Setting ---- */
+        SPDIF.CTRL.LONG = (SPDIF_CTRL_BASE_INIT_VALUE
+                        | (p_info_ch->clk_select << SPDIF_CTRL_CKS_SHIFT)
+                        | (p_info_ch->audio_bit_rx << SPDIF_CTRL_RASS_SHIFT)
+                        | (p_info_ch->audio_bit_tx << SPDIF_CTRL_TASS_SHIFT)
+#if(0) //test debug
+                        | (SPDIF_CTRL_PB)
+#endif
+                        );
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_CheckChannelCfg
+* @brief         Check channel configuration parameters are valid or not.
+*
+*                Description:<br>
+*
+* @param[in]     p_ch_cfg     :channel configuration
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SPDIF_CheckChannelCfg(const spdif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_ch_cfg)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        switch (p_ch_cfg->clk_select)
+        {
+        case SPDIF_CFG_CKS_AUDIO_X1:
+            /* fall through */
+        case SPDIF_CFG_CKS_AUDIO_CLK:
+            /* do nothing */
+            break;
+        default:
+            ret = EINVAL_RBSP;
+            break;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->audio_bit_tx)
+            {
+            case SPDIF_CFG_AUDIO_BIT_16:
+                /* fall through */
+            case SPDIF_CFG_AUDIO_BIT_20:
+                /* fall through */
+            case SPDIF_CFG_AUDIO_BIT_24:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->audio_bit_rx)
+            {
+            case SPDIF_CFG_AUDIO_BIT_16:
+                /* fall through */
+            case SPDIF_CFG_AUDIO_BIT_20:
+                /* fall through */
+            case SPDIF_CFG_AUDIO_BIT_24:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_Handler
+* @brief         SPDIF error interrupt handler per channel
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        none
+******************************************************************************/
+static void SPDIF_Handler(void)
+{
+#if(1) /* mbed */
+    spdif_info_drv_t* const p_info_drv = SPDIF_GetDrvInstanc();
+    spdif_info_ch_t* const p_info_ch = &p_info_drv->info_ch;
+#else
+    spdif_info_ch_t* const p_info_ch = &g_spdif_info_drv.info_ch;
+#endif /* end mbed */
+    volatile uint32_t dummy_buf_32;
+    uint32_t status;
+    bool     err_flg;
+
+    err_flg = false;
+
+    /* ==== Read the status ==== */
+    status = SPDIF.STAT.LONG;
+
+    /* ==== Transmitter Error interrupt ==== */
+    if ((status & (SPDIF_STAT_UBU | SPDIF_STAT_CSE | SPDIF_STAT_ABU)) != 0u)
+    {
+        err_flg = true;
+        SPDIF_ErrorRecovery_tx(p_info_ch);
+    }
+
+    /* ==== Receiver Error interrupt ==== */
+    if ((status & ( SPDIF_STAT_UBO  |
+                    SPDIF_STAT_CE   |
+                    SPDIF_STAT_PARE |
+                    SPDIF_STAT_PREE |
+                    SPDIF_STAT_ABO) ) != 0u)
+    {
+        err_flg = true;
+        SPDIF_ErrorRecovery_rx(p_info_ch);
+    }
+
+    if (false == err_flg)
+    {
+        /* ==== Transmitter Channel Status interrupt (CSTX) ==== */
+        if ((status & SPDIF_STAT_CSTX) != 0u)
+        {
+            SPDIF.CTRL.BIT.NCSI = 0;
+            SPDIF_ChannelStatusRegSet(p_info_ch);
+            SPDIF_ChannelStatusRegSetWait();
+        }
+
+        /* ==== Transmitter User Information interrupt (TUIR) ==== */
+        if ((status & SPDIF_STAT_TUIR) != 0u)
+        {
+            /* ---- Write the user data ---- */
+            SPDIF_UserInfoRegSet(p_info_ch);
+            SPDIF_UserInfoRegSetWait();
+        }
+
+        /* ==== Receiver User Information Interrupt (RUIR) ==== */
+        if ((status & SPDIF_STAT_RUIR) != 0u)
+        {
+            /* ---- Read the user data ---- */
+            (void)SPDIF_UserInfoRegGet(p_info_ch);
+        }
+
+        /* ==== Receiver Channel Status Interrupt (CSRX) ==== */
+        if ((status & SPDIF_STAT_CSRX) != 0u)
+        {
+            /* ---- Read the status data ---- */
+            SPDIF_ChannelStatusRegGet(p_info_ch);
+        }
+    }
+
+    /* Wait to clear request */
+    dummy_buf_32 = SPDIF.STAT.LONG;
+    (void)dummy_buf_32;
+
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: SPDIF_UserInfoRegSet
+* Description  : This function set User Infomation
+* Arguments    : none
+* Return Value : DEVDRV_SUCCESS -
+*                    User information registration success
+*                DEVDRV_ERROR -
+*                    User information registration error
+*                DEVDRV_QUEUE_EMPTY -
+*                    Since queue is empty, default user information is registered. 
+*******************************************************************************/
+void SPDIF_UserInfoRegSet(spdif_info_ch_t* const p_info_ch)
+{
+    if ((p_info_ch->p_aio_tx_next != NULL)
+     && (p_info_ch->p_aio_tx_next->aio_return == SPDIF_ASYNC_STRUCT_W))
+    {
+        spdif_t * p_wk_spdif = (spdif_t*)p_info_ch->p_aio_tx_next->aio_buf;
+        SPDIF.TUI.LONG = p_wk_spdif->u_buff[p_info_ch->tu_idx];
+        p_info_ch->tu_idx++;
+        if (p_info_ch->tu_idx >= SPDIF_USER_BUFFSIZE)
+        {
+            p_info_ch->tu_idx = 0;
+        }
+    }
+    else
+    {
+        SPDIF.TUI.LONG = 0x00000000;
+    }
+}
+
+/*******************************************************************************
+* Function Name: SPDIF_UserInfoRegSetWait
+* Description  : This function wait until Transmission module user info register
+*                becomes to the full.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+static void SPDIF_UserInfoRegSetWait(void)
+{
+    uint32_t counter;
+
+    /* ---- Wait ---- */
+    for (counter = 0; counter < SPDIF_UPDATA_WAIT; counter++)
+    {
+        if (SPDIF.STAT.BIT.TUIR == 0)
+        {
+            /* Wait for the TUIR bit is cleared */
+            /* maximum of one frame is completed*/
+            break;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: SPDIF_UserInfoRegGet
+* Description  : This function get User Infomation
+* Arguments    : none
+* Return Value : DEVDRV_SUCCESS -
+*                    User Infomation registration success
+*                DEVDRV_ERROR -
+*                    Operation error
+*                DEVDRV_QUEUE_EMPTY -
+*                    queue is empty, Operation error. 
+*******************************************************************************/
+void SPDIF_UserInfoRegGet(spdif_info_ch_t* const p_info_ch)
+{
+    volatile uint32_t dummy_buf_32;
+
+    if ((p_info_ch->p_aio_rx_next != NULL)
+     && (p_info_ch->p_aio_rx_next->aio_return == SPDIF_ASYNC_STRUCT_R))
+    {
+        spdif_t * p_wk_spdif = (spdif_t*)p_info_ch->p_aio_rx_next->aio_buf;
+        p_wk_spdif->u_buff[p_info_ch->ru_idx] = SPDIF.RUI.LONG;
+        p_info_ch->ru_idx++;
+        if (p_info_ch->ru_idx >= SPDIF_USER_BUFFSIZE)
+        {
+            p_info_ch->ru_idx = 0;
+        }
+    }
+    else
+    {
+        dummy_buf_32 = SPDIF.RUI.LONG;
+        (void)dummy_buf_32;
+    }
+}
+
+/*******************************************************************************
+* Function Name: SPDIF_ChannelStatusRegSet
+* Description  : This function set Channel Status information
+* Arguments    : none
+* Return Value : DEVDRV_SUCCESS -
+*                    Channel Status registration success
+*                DEVDRV_QUEUE_EMPTY -
+*                    Since queue is empty, default Channel Status information is registered. 
+*******************************************************************************/
+static void SPDIF_ChannelStatusRegSet(const spdif_info_ch_t* const p_info_ch)
+{
+    SPDIF.TLCS.LONG = p_info_ch->tlcs;
+    SPDIF.TRCS.LONG = p_info_ch->trcs;
+}
+
+/*******************************************************************************
+* Function Name: SPDIF_ChannelStatusRegSetWait
+* Description  : This function wait until transmission module channel status register
+*                becomes to the full.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+static void SPDIF_ChannelStatusRegSetWait(void)
+{
+    uint32_t counter;
+
+    /* ---- Wait ---- */
+    for (counter = 0; counter < SPDIF_UPDATA_WAIT; counter++)
+    {
+        if (SPDIF.STAT.BIT.CSTX == 0)
+        {
+            /* Wait for register full */
+            break;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: SPDIF_ChannelStatusRegGet
+* Description  : This function get Channel Status
+* Arguments    : none
+* Return Value : DEVDRV_SUCCESS -
+*                    Channel Status Infomation registration success
+*                DEVDRV_ERROR -
+*                    Operation error
+*                DEVDRV_QUEUE_EMPTY -
+*                    queue is empty, Operation error. 
+*******************************************************************************/
+static void SPDIF_ChannelStatusRegGet(spdif_info_ch_t* const p_info_ch)
+{
+    /* ==== Get Channel Status  ==== */
+    p_info_ch->rlcs = SPDIF.RLCS.LONG;
+    p_info_ch->rrcs = SPDIF.RRCS.LONG;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/spdif/spdif.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,166 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : spdif.h
+* $Rev: $
+* $Date::                           $
+* Description  : SPDIF driver functions header
+******************************************************************************/
+
+#ifndef SPDIF_H
+#define SPDIF_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "aioif.h"
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "spdif_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SPDIF_CHNUM_0    (0u)
+
+#define SPDIF_CHSTR_0 "\\0"
+
+#define SPDIF_MAX_PATH_LEN           (32u)
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+typedef enum {
+    SPDIF_DRVSTS_UNINIT = 0,
+    SPDIF_DRVSTS_INIT
+} spdif_drv_stat_t;
+
+typedef enum
+{
+    SPDIF_CHSTS_UNINIT = 0,
+    SPDIF_CHSTS_INIT,
+    SPDIF_CHSTS_OPEN
+} spdif_ch_stat_t;
+
+typedef enum
+{
+    SPDIF_ASYNC_W = 0,
+    SPDIF_ASYNC_R,
+    SPDIF_ASYNC_STRUCT_W,
+    SPDIF_ASYNC_STRUCT_R,
+    SPDIF_ASYNC_SET_CH_STS
+} spdif_rw_mode_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+typedef struct spdif_info_ch
+{
+    uint32_t    channel;
+    bool_t      enabled;
+    uint32_t    sample_freq;
+    spdif_ch_stat_t ch_stat;
+    osSemaphoreId_t sem_access;
+    AHF_S       tx_que;
+    AHF_S       rx_que;
+    int_t       dma_rx_ch;
+    int_t       dma_tx_ch;
+    int_t       openflag;
+    AIOCB*      p_aio_tx_curr;
+    AIOCB*      p_aio_tx_next;
+    AIOCB*      p_aio_rx_curr;
+    AIOCB*      p_aio_rx_next;
+    AIOCB       s_aio_set_ch_sts;
+    uint32_t    ch_sts[2];
+    bool_t      ch_sts_set_req;
+    spdif_chcfg_cks_t               clk_select;          /**< CTRL-CKS : Audio clock select         */
+    spdif_chcfg_audio_bit_t         audio_bit_tx;        /**< CTRL-TASS : Audio bit length          */
+    spdif_chcfg_audio_bit_t         audio_bit_rx;        /**< CTRL-RASS : Audio bit length          */
+    bool_t      tx_u_data_enabled;
+    uint32_t    tlcs;
+    uint32_t    trcs;
+    uint32_t    rlcs;
+    uint32_t    rrcs;
+    uint32_t    tu_idx;
+    uint32_t    ru_idx;
+    uint8_t     int_level;
+} spdif_info_ch_t;
+
+
+typedef struct spdif_info_drv
+{
+    spdif_drv_stat_t drv_stat;
+    spdif_info_ch_t  info_ch;
+} spdif_info_drv_t;
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+int_t SPDIF_InitialiseOne(const int_t channel, const spdif_channel_cfg_t* const p_cfg_data);
+int_t SPDIF_UnInitialiseOne(const int_t channel);
+#endif /* end mbed */
+int_t SPDIF_Initialise(const spdif_channel_cfg_t* const p_cfg_data);
+int_t SPDIF_UnInitialise(void);
+int_t SPDIF_EnableChannel(spdif_info_ch_t* const p_info_ch);
+int_t SPDIF_DisableChannel(spdif_info_ch_t* const p_info_ch);
+void  SPDIF_ErrorRecovery(spdif_info_ch_t* const p_info_ch);
+
+void SPDIF_PostAsyncIo(spdif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+void SPDIF_PostAsyncCancel(spdif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+
+int_t SPDIF_IOCTL_ConfigChannel(spdif_info_ch_t* const p_info_ch,
+                const spdif_channel_cfg_t* const p_ch_cfg);
+int_t SPDIF_IOCTL_SetChannelStatus(spdif_info_ch_t* const p_info_ch,
+                                   spdif_channel_status_t* const p_channel_status);
+int_t SPDIF_IOCTL_GetChannelStatus(spdif_info_ch_t* const p_info_ch,
+                                   spdif_channel_status_t* const p_channel_status);
+int_t SPDIF_IOCTL_SetTransAudioBit(spdif_info_ch_t* const p_info_ch,
+                                   spdif_chcfg_audio_bit_t sudio_bit);
+int_t SPDIF_IOCTL_SetRecvAudioBit(spdif_info_ch_t* const p_info_ch,
+                                   spdif_chcfg_audio_bit_t sudio_bit);
+
+int_t SPDIF_InitDMA(spdif_info_ch_t* const p_info_ch);
+void SPDIF_UnInitDMA(spdif_info_ch_t* const p_info_ch);
+void SPDIF_CancelDMA(const spdif_info_ch_t* const p_info_ch, int_t openflag);
+int_t SPDIF_RestartDMA(spdif_info_ch_t* const p_info_ch, int_t openflag);
+
+void SPDIF_UserInfoRegSet(spdif_info_ch_t* const p_info_ch);;
+void SPDIF_UserInfoRegGet(spdif_info_ch_t* const p_info_ch);
+
+
+#if(1) /* mbed */
+extern spdif_info_drv_t * SPDIF_GetDrvInstanc(void);
+#else
+extern spdif_info_drv_t g_spdif_info_drv;
+#endif /* end mbed */
+
+#endif /* SPDIF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/spdif/spdif_cfg.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,51 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : spdif_cfg.c
+* $Rev: $
+* $Date::                           $
+* Description : SPDIF driver userown functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "spdif_if.h"
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+int_t R_SPDIF_Userdef_InitPinMux(void)
+{
+    return ESUCCESS;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/spdif/spdif_dma.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,796 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : spdif_dma.c
+* $Rev: $
+* $Date::                           $
+* Description : SPDIF driver DMA functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "spdif.h"
+#include "iodefine.h"
+#include "iobitmask.h"
+#include "dma_if.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SPDIF_DUMMY_DMA_TRN_SIZE (192u * 2u * 4u)
+#define SPDIF_DUMMY_DMA_BUF_SIZE (SPDIF_DUMMY_DMA_TRN_SIZE + sizeof(uint32_t) - 1)
+
+#define SPDIF_STAT_READ_ONLY (0xFFFFC03FuL)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+static void SPDIF_DMA_TxCallback(union sigval param);
+static void SPDIF_DMA_RxCallback(union sigval param);
+
+static AIOCB gb_spdif_dma_tx_end_aiocb;
+static AIOCB gb_spdif_dma_rx_end_aiocb;
+
+static dma_trans_data_t gb_spdif_txdma_dummy_trparam;
+static dma_trans_data_t gb_spdif_rxdma_dummy_trparam;
+
+static uint32_t spdif_tx_dummy_buf[SPDIF_DUMMY_DMA_BUF_SIZE / sizeof(uint32_t)];
+static uint32_t spdif_rx_dummy_buf[SPDIF_DUMMY_DMA_BUF_SIZE / sizeof(uint32_t)];
+
+/******************************************************************************
+* Function Name: SPDIF_InitDMA
+* @brief         Allocate and Setup DMA_CH for specified SPDIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_InitDMA(spdif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* allocate DMA Channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                p_info_ch->dma_tx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_tx_ch = -1;
+                    ercd = ENOMEM_RBSP;
+                }
+                else
+                {
+                    p_info_ch->dma_tx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* allocate DMA Channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                p_info_ch->dma_rx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_rx_ch = -1;
+                    ercd = ENOMEM_RBSP;
+                }
+                else
+                {
+                    p_info_ch->dma_rx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_spdif_dma_tx_end_aiocb;
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SPDIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = DMA_RS_SPDIFTXI;
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+                dma_ch_setup.int_level = p_info_ch->int_level;
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_spdif_dma_rx_end_aiocb;
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SPDIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = DMA_RS_SPDIFRXI;
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.int_level = p_info_ch->int_level;
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_spdif_txdma_dummy_trparam.src_addr = (void*)&spdif_tx_dummy_buf[0];
+                gb_spdif_txdma_dummy_trparam.dst_addr = (void*)&SPDIF.TDAD.LONG;
+                gb_spdif_txdma_dummy_trparam.count = SPDIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_spdif_txdma_dummy_trparam, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_spdif_txdma_dummy_trparam, &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_spdif_rxdma_dummy_trparam.src_addr = (void*)&SPDIF.RDAD.LONG;
+                gb_spdif_rxdma_dummy_trparam.dst_addr = (void*)&spdif_rx_dummy_buf[0];
+                gb_spdif_rxdma_dummy_trparam.count = SPDIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_spdif_rxdma_dummy_trparam, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_spdif_rxdma_dummy_trparam, &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* enable spdif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            /* enable end interrupt */
+            if (O_RDWR_RBSP == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                SPDIF.STAT.LONG &= ~(SPDIF_STAT_READ_ONLY | SPDIF_STAT_UBU | SPDIF_STAT_CSE | SPDIF_STAT_ABU |
+                                     SPDIF_STAT_UBO | SPDIF_STAT_CE | SPDIF_STAT_PARE | SPDIF_STAT_PREE | SPDIF_STAT_ABO);
+                SPDIF.CTRL.LONG |= (SPDIF_CTRL_TME | SPDIF_CTRL_TDE | SPDIF_CTRL_RME | SPDIF_CTRL_RDE);
+            }
+            else if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                SPDIF.STAT.LONG &= ~(SPDIF_STAT_READ_ONLY | SPDIF_STAT_UBU | SPDIF_STAT_CSE | SPDIF_STAT_ABU);
+                SPDIF.CTRL.LONG |= (SPDIF_CTRL_TME | SPDIF_CTRL_TDE);
+            }
+            else if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                SPDIF.STAT.LONG &= ~(SPDIF_STAT_READ_ONLY | SPDIF_STAT_UBO | SPDIF_STAT_CE | SPDIF_STAT_PARE | SPDIF_STAT_PREE | SPDIF_STAT_ABO);
+                SPDIF.CTRL.LONG |= (SPDIF_CTRL_RME | SPDIF_CTRL_RDE);
+            }
+            else
+            {
+                ercd = EINVAL_RBSP;
+            }
+        }
+
+        /* cleanup dma resources when error occured */
+        if (ESUCCESS != ercd)
+        {
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_tx_ch = -1;
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_rx_ch = -1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_UnInitDMA
+* @brief         Free DMA_CH for specified SPDIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SPDIF_UnInitDMA(spdif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_tx_ch = -1;
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_rx_ch = -1;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_RestartDMA
+* @brief         Setup DMA_CH for specified SPDIF channel(without allocate)
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SPDIF_RestartDMA(spdif_info_ch_t* const p_info_ch, int_t openflag)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_spdif_dma_tx_end_aiocb;
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SPDIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = DMA_RS_SPDIFTXI;
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+                dma_ch_setup.int_level = p_info_ch->int_level;
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_spdif_dma_rx_end_aiocb;
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SPDIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = DMA_RS_SPDIFRXI;
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+                dma_ch_setup.int_level = p_info_ch->int_level;
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != openflag)
+            {
+                /* setup short dummy transfer */
+                gb_spdif_txdma_dummy_trparam.src_addr = (void*)&spdif_tx_dummy_buf[0];
+                gb_spdif_txdma_dummy_trparam.dst_addr = (void*)&SPDIF.TDAD.LONG;
+                gb_spdif_txdma_dummy_trparam.count = SPDIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_spdif_txdma_dummy_trparam, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_spdif_txdma_dummy_trparam, &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != openflag)
+            {
+                /* setup short dummy transfer */
+                gb_spdif_rxdma_dummy_trparam.src_addr = (void*)&SPDIF.RDAD.LONG;
+                gb_spdif_rxdma_dummy_trparam.dst_addr = (void*)&spdif_rx_dummy_buf[0];
+                gb_spdif_rxdma_dummy_trparam.count = SPDIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_spdif_rxdma_dummy_trparam, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_spdif_rxdma_dummy_trparam, &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* enable spdif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            /* enable end interrupt */
+            if (O_RDWR_RBSP == openflag)
+            {
+                /* start write and read DMA at the same time */
+                SPDIF.STAT.LONG &= ~(SPDIF_STAT_UBU | SPDIF_STAT_CSE | SPDIF_STAT_ABU);
+                SPDIF.STAT.LONG &= ~(SPDIF_STAT_UBO | SPDIF_STAT_CE | SPDIF_STAT_PARE | SPDIF_STAT_PREE | SPDIF_STAT_ABO);
+                SPDIF.CTRL.LONG |= (SPDIF_CTRL_TME | SPDIF_CTRL_TDE | SPDIF_CTRL_RME | SPDIF_CTRL_RDE);
+            }
+            else if (O_WRONLY_RBSP == openflag)
+            {
+                /* start write DMA only */
+                SPDIF.STAT.LONG &= ~(SPDIF_STAT_UBU | SPDIF_STAT_CSE | SPDIF_STAT_ABU);
+                SPDIF.CTRL.LONG |= (SPDIF_CTRL_TME | SPDIF_CTRL_TDE);
+            }
+            else if (O_RDONLY_RBSP == openflag)
+            {
+                /* start read DMA only */
+                SPDIF.STAT.LONG &= ~(SPDIF_STAT_UBO | SPDIF_STAT_CE | SPDIF_STAT_PARE | SPDIF_STAT_PREE | SPDIF_STAT_ABO);
+                SPDIF.CTRL.LONG |= (SPDIF_CTRL_RME | SPDIF_CTRL_RDE);
+            }
+            else
+            {
+                ercd = EINVAL_RBSP;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_CancelDMA
+* @brief         Pause DMA transfer for specified SPDIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SPDIF_CancelDMA(const spdif_info_ch_t* const p_info_ch, int_t openflag)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (O_RDONLY_RBSP != openflag) {
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+        }
+
+        if (O_WRONLY_RBSP != openflag) {
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SPDIF_DMA_TxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SPDIF_DMA_TxCallback(const union sigval param)
+{
+    spdif_info_ch_t* const p_info_ch = param.sival_ptr;
+    dma_trans_data_t dma_data_next;
+#if(1) /* mbed */
+    int32_t ercd = ESUCCESS;
+#else
+    int_t ercd = ESUCCESS;
+#endif
+    int_t ret;
+    AIOCB* p_aio_work;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if ((p_info_ch->p_aio_tx_next != NULL)
+         && (p_info_ch->ch_sts_set_req != false)) {
+            p_info_ch->ch_sts_set_req = false;
+            if ((p_info_ch->tlcs != p_info_ch->ch_sts[0])
+             || (p_info_ch->trcs != p_info_ch->ch_sts[1])) {
+	            p_info_ch->tlcs = p_info_ch->ch_sts[0];
+	            p_info_ch->trcs = p_info_ch->ch_sts[1];
+                SPDIF.CTRL.BIT.NCSI = 1;
+            }
+        }
+        if ((p_info_ch->p_aio_tx_next != NULL)
+         && (p_info_ch->p_aio_tx_next->aio_return == SPDIF_ASYNC_STRUCT_W)) {
+            spdif_t * p_wk_spdif = (spdif_t*)p_info_ch->p_aio_tx_next->aio_buf;
+
+            if ((p_info_ch->tlcs != p_wk_spdif->s_buff[0])
+             || (p_info_ch->trcs != p_wk_spdif->s_buff[1])) {
+                p_info_ch->tlcs = p_wk_spdif->s_buff[0];
+                p_info_ch->trcs = p_wk_spdif->s_buff[1];
+                SPDIF.CTRL.BIT.NCSI = 1;
+            }
+        }
+        if (NULL == p_info_ch->p_aio_tx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_tx_curr->aio_return = (ssize_t)p_info_ch->p_aio_tx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_tx_curr = p_info_ch->p_aio_tx_next;
+
+        /* get next request(It's maybe NULL) */
+        while (1) {
+            p_aio_work = ahf_removehead(&p_info_ch->tx_que);
+            if ((p_aio_work == NULL)
+             || (p_aio_work->aio_return != SPDIF_ASYNC_SET_CH_STS)) {
+                break;
+            } else {
+                p_info_ch->ch_sts_set_req = true;
+                ahf_complete(&p_info_ch->tx_que, p_aio_work);
+            }
+        }
+        p_info_ch->p_aio_tx_next = p_aio_work;
+
+        p_info_ch->tu_idx = 0;
+        SPDIF_UserInfoRegSet(p_info_ch);
+
+        if (NULL != p_info_ch->p_aio_tx_next)
+        {
+            /* add user request */
+            if (p_info_ch->p_aio_tx_next->aio_return == SPDIF_ASYNC_STRUCT_W) {
+                dma_data_next.src_addr = (void*)(((spdif_t*)p_info_ch->p_aio_tx_next->aio_buf)->a_buff);
+                p_info_ch->p_aio_tx_next->aio_nbytes = SPDIF_AUDIO_BUFFSIZE * 4;
+            } else {
+                dma_data_next.src_addr = (void*)p_info_ch->p_aio_tx_next->aio_buf;
+            }
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_tx_next->aio_nbytes;
+            dma_data_next.dst_addr = (void*)&SPDIF.TDAD.LONG;
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_spdif_txdma_dummy_trparam, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_DMA_RxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SPDIF_DMA_RxCallback(const union sigval param)
+{
+    spdif_info_ch_t* const p_info_ch = param.sival_ptr;
+    dma_trans_data_t dma_data_next;
+#if(1) /* mbed */
+    int32_t ercd = ESUCCESS;
+#else
+    int_t ercd = ESUCCESS;
+#endif
+    int_t ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        SPDIF_UserInfoRegGet(p_info_ch);
+        if (NULL == p_info_ch->p_aio_rx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+            if (p_info_ch->p_aio_rx_curr->aio_return == SPDIF_ASYNC_STRUCT_R) {
+                spdif_t * p_wk_spdif = (spdif_t*)p_info_ch->p_aio_rx_curr->aio_buf;
+
+                p_wk_spdif->s_buff[0] = p_info_ch->rlcs;
+                p_wk_spdif->s_buff[1] = p_info_ch->rrcs;
+            }
+
+            /* return aio complete */
+            p_info_ch->p_aio_rx_curr->aio_return = (ssize_t)p_info_ch->p_aio_rx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_rx_curr = p_info_ch->p_aio_rx_next;
+        p_info_ch->ru_idx = 0;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_rx_next = ahf_removehead(&p_info_ch->rx_que);
+
+        if (NULL != p_info_ch->p_aio_rx_next)
+        {
+            /* add user request */
+            if (p_info_ch->p_aio_rx_next->aio_return == SPDIF_ASYNC_STRUCT_R) {
+                dma_data_next.dst_addr = (void*)(((spdif_t*)p_info_ch->p_aio_rx_next->aio_buf)->a_buff);
+                p_info_ch->p_aio_rx_next->aio_nbytes = SPDIF_AUDIO_BUFFSIZE * 4;
+            } else {
+                dma_data_next.dst_addr = (void*)p_info_ch->p_aio_rx_next->aio_buf;
+            }
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_rx_next->aio_nbytes;
+            dma_data_next.src_addr = (void*)&SPDIF.RDAD.LONG;
+
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_spdif_rxdma_dummy_trparam, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/spdif/spdif_if.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,966 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : spdif_if.c
+* $Rev: $
+* $Date::                           $
+* Description : SPDIF driver interface functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "cmsis_os.h"
+#if(1) /* mbed */
+#include "r_bsp_cmn.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+#include "spdif.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+#if(1) /* mbed */
+static spdif_drv_stat_t ch_drv_stat[SPDIF_NUM_CHANS] = {SPDIF_DRVSTS_UNINIT};
+
+static void* R_SPDIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno);
+static int_t R_SPDIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno);
+#else  /* not mbed */
+static void* R_SPDIF_Init(void* const config_data, int32_t* const p_errno);
+static int_t R_SPDIF_UnInit(void* const driver_instance, int32_t* const p_errno);
+#endif /* end mbed */
+static int_t R_SPDIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno);
+static int_t R_SPDIF_Close(void* const p_fd, int32_t* const p_errno);
+static int_t R_SPDIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno);
+static int_t R_SPDIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SPDIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SPDIF_Cancel(void* const p_fd, AIOCB* p_aio, int32_t* const p_errno);
+
+static size_t SPDIF_StrnLen(const char_t p_str[], const size_t maxlen);
+static int32_t SPDIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen);
+static void   SPDIF_SetErrCode(const int_t error_code, int32_t* const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SPDIF_MakeCbTbl_mbed
+* @brief         Make the SPDIF driver function callback table
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of SPDIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+RBSP_MBED_FNS* R_SPDIF_MakeCbTbl_mbed(void)
+/* <-IPA M1.1.1 */
+{
+    static RBSP_MBED_FNS spdif_apitbl_mbed;
+
+    spdif_apitbl_mbed.initialise_one   = &R_SPDIF_InitOne;
+    spdif_apitbl_mbed.uninitialise_one = &R_SPDIF_UnInitOne;
+    spdif_apitbl_mbed.open             = &R_SPDIF_Open;
+    spdif_apitbl_mbed.close            = &R_SPDIF_Close;
+    spdif_apitbl_mbed.ioctl            = &R_SPDIF_Ioctl;
+    spdif_apitbl_mbed.read_a           = &R_SPDIF_ReadAsync;
+    spdif_apitbl_mbed.write_a          = &R_SPDIF_WriteAsync;
+    spdif_apitbl_mbed.cancel           = &R_SPDIF_Cancel;
+
+    return &spdif_apitbl_mbed;
+}
+#else  /* not mbed */
+/******************************************************************************
+* Function Name: R_SPDIF_MakeCbTbl
+* @brief         Make the SPDIF driver function callback table
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        pointer of SPDIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+IOIF_DRV_API* R_SPDIF_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    static IOIF_DRV_API spdif_apitbl;
+
+    /* ->MISRA 16.4, IPA M4.5.1 : This is IOIF library API type definitnon that can't be modified. */
+    spdif_apitbl.family = IOIF_SERIAL_FAMILY;
+    spdif_apitbl.fns.serial.initialise   = &R_SPDIF_Init;
+    spdif_apitbl.fns.serial.uninitialise = &R_SPDIF_UnInit;
+    spdif_apitbl.fns.serial.open         = &R_SPDIF_Open;
+    spdif_apitbl.fns.serial.close        = &R_SPDIF_Close;
+    spdif_apitbl.fns.serial.ioctl        = &R_SPDIF_Ioctl;
+    spdif_apitbl.fns.serial.read_a       = &R_SPDIF_ReadAsync;
+    spdif_apitbl.fns.serial.write_a      = &R_SPDIF_WriteAsync;
+    spdif_apitbl.fns.serial.cancel       = &R_SPDIF_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+
+    return &spdif_apitbl;
+}
+#endif /* end mbed */
+
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SPDIF_InitOne
+* @brief         Initialise the SPDIF driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel     :channel number
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SPDIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+#if(1) /* mbed */
+    else if ((uint32_t)channel >= SPDIF_NUM_CHANS)
+#else
+    else if (channel >= SPDIF_NUM_CHANS)
+#endif
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+#if(1) /* mbed */
+        spdif_info_drv_t* const p_info_drv = SPDIF_GetDrvInstanc();
+        p_info_drv->drv_stat = SPDIF_DRVSTS_INIT;
+#else
+        g_spdif_info_drv.drv_stat = SPDIF_DRVSTS_INIT;
+#endif /* end mbed */
+        ch_drv_stat[channel] = SPDIF_DRVSTS_INIT;
+
+        ercd = SPDIF_InitialiseOne(channel, (const spdif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+#if(1) /* mbed */
+            p_ret = (void*)p_info_drv;
+#else
+            p_ret = (void*)&g_spdif_info_drv;
+#endif /* end mbed */
+        }
+        else
+        {
+            ch_drv_stat[channel] = SPDIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SPDIF_UnInitOne
+* @brief         Uninitialise the SPDIF deiver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel         :channel number
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SPDIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SPDIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+
+    if (NULL == driver_instance)
+    {
+        ercd = EFAULT_RBSP;
+    }
+#if(1) /* mbed */
+    else if ((uint32_t)channel >= SPDIF_NUM_CHANS)
+#else
+    else if (channel >= SPDIF_NUM_CHANS)
+#endif
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SPDIF_DRVSTS_INIT != ch_drv_stat[channel])
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            ercd = SPDIF_UnInitialiseOne(channel);
+            ch_drv_stat[channel] = SPDIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+#else  /* not mbed */
+
+/******************************************************************************
+* Function Name: R_SPDIF_Init
+* @brief         Initialise the SPDIF driver.
+*
+*                Description:<br>
+*
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SPDIF_Init(void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (SPDIF_DRVSTS_UNINIT != g_spdif_info_drv.drv_stat)
+    {
+        ercd = EBUSY;
+    }
+    else
+    {
+        g_spdif_info_drv.drv_stat = SPDIF_DRVSTS_INIT;
+
+        ercd = SPDIF_Initialise((spdif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+            p_ret = (void*)&g_spdif_info_drv;
+        }
+        else
+        {
+            g_spdif_info_drv.drv_stat = SPDIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SPDIF_UnInit
+* @brief         Uninitialise the SPDIF deiver.
+*
+*                Description:<br>
+*
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SPDIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SPDIF_UnInit(void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+    spdif_info_drv_t* const p_info_drv   = driver_instance;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SPDIF_DRVSTS_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            ercd = SPDIF_UnInitialise();
+            p_info_drv->drv_stat = SPDIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SPDIF_Open
+* @brief         Open an SPDIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_drv_instance :driver instance which was returned by<br>
+                                 R_SPDIF_Init
+* @param[in]     p_path_name    :string of channel
+* @param[in]     flags          :access mode whether the channel is opened<br>
+                                 for a read or a write
+* @param[in]     mode           :not used
+* @param[in,out] p_errno        :pointer of error code
+* @retval        not EERROR     :channel handle
+* @retval        EERROR         :Failure.
+******************************************************************************/
+static int_t R_SPDIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno)
+{
+    void* p_channelHandle;
+    size_t len;
+    size_t req_path_len;
+    spdif_info_drv_t* const p_info_drv = p_driver_instance;
+    spdif_info_ch_t* p_info_ch = NULL;
+    int_t ret;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    UNUSED_ARG(mode);
+
+    if ((NULL == p_info_drv) || (NULL == p_path_name))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        req_path_len = strlen(p_path_name);
+        if (0u == req_path_len)
+        {
+            ercd = ENOENT_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SPDIF_DRVSTS_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            len = SPDIF_StrnLen(SPDIF_CHSTR_0, SPDIF_MAX_PATH_LEN);
+
+            if (req_path_len < len)
+            {
+                len = req_path_len;
+            }
+
+            if (0 == SPDIF_Strncmp(p_path_name, SPDIF_CHSTR_0, len))
+            {
+                /* found a match */
+                p_info_ch = &p_info_drv->info_ch;
+            }
+        }
+    }
+
+    if (NULL == p_info_ch)
+    {
+        ercd = ENOENT_RBSP;
+    }
+    else
+    {
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->enabled)
+            {
+                ercd = ENOTSUP_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SPDIF_CHSTS_INIT != p_info_ch->ch_stat)
+            {
+                ercd = EBADF_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                p_info_ch->openflag = flags;
+                p_info_ch->p_aio_tx_curr = NULL;
+                p_info_ch->p_aio_rx_curr = NULL;
+
+                ercd = SPDIF_EnableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SPDIF_CHSTS_OPEN;
+                }
+            }
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    else
+    {
+        p_channelHandle = (void*)p_info_ch;
+        ret = (int_t)p_channelHandle;
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SPDIF_Close
+* @brief         Close an SPDIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SPDIF_Open
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SPDIF_Close(void* const p_fd, int32_t* const p_errno)
+{
+    spdif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (SPDIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                SPDIF_PostAsyncCancel(p_info_ch, NULL);
+
+                ercd = SPDIF_DisableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SPDIF_CHSTS_INIT;
+                }
+            }
+
+            /* Relese semaphore */
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SPDIF_Ioctl
+* @brief         IOCTL function of the SPDIF deiver
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SPDIF_Open
+* @param[in]     request    :IOCTL request code
+* @param[in,out] p_buf      :Meaning depends upon request.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SPDIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno)
+{
+    spdif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SPDIF_CHSTS_OPEN != p_info_ch->ch_stat)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT_RBSP;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SPDIF_CONFIG_CHANNEL:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            spdif_channel_cfg_t* const ch_info = (spdif_channel_cfg_t*)p_buf;
+                            ercd = SPDIF_IOCTL_ConfigChannel(p_info_ch, ch_info);
+                        }
+                        break;
+                    }
+
+                    case SPDIF_SET_CHANNEL_STATUS:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SPDIF_IOCTL_SetChannelStatus(p_info_ch, (spdif_channel_status_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    case SPDIF_GET_CHANNEL_STATUS:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SPDIF_IOCTL_GetChannelStatus(p_info_ch, (spdif_channel_status_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    case SPDIF_SET_TRANS_AUDIO_BIT:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SPDIF_IOCTL_SetTransAudioBit(p_info_ch, *(spdif_chcfg_audio_bit_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    case SPDIF_SET_RECV_AUDIO_BIT:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SPDIF_IOCTL_SetRecvAudioBit(p_info_ch, *(spdif_chcfg_audio_bit_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    default:
+                    {
+                        ercd = EINVAL_RBSP;
+                        break;
+                    }
+                } /* switch */
+            }
+        }
+
+        os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+        if (osOK != os_ercd)
+        {
+            ercd = EFAULT_RBSP;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SPDIF_WriteAsync
+* @brief         Enqueue asynchronous write request
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SPDIF_Open
+* @param[in]     p_aio      :aio control block of write request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SPDIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    spdif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (((uint32_t)O_RDONLY_RBSP) == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP))
+        {
+            ercd = EACCES_RBSP;
+        }
+        else if ((0u == p_aio->aio_nbytes) && (p_aio->aio_buf == NULL))
+        {
+            ercd = EINVAL_RBSP;
+        }
+        else
+        {
+            if (0u == p_aio->aio_nbytes)
+            {
+                p_aio->aio_return = SPDIF_ASYNC_STRUCT_W;
+            }
+            else
+            {
+                p_aio->aio_return = SPDIF_ASYNC_W;
+            }
+            SPDIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SPDIF_ReadAsync
+* @brief         Enqueue asynchronous read request
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SPDIF_Open
+* @param[in]     p_aio      :aio control block of read request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SPDIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    spdif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if ((O_WRONLY_RBSP == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP)))
+        {
+            ercd = EACCES_RBSP;
+        }
+        else if ((0u == p_aio->aio_nbytes) && (p_aio->aio_buf == NULL))
+        {
+            ercd = EINVAL_RBSP;
+        }
+        else
+        {
+            if (0u == p_aio->aio_nbytes)
+            {
+                p_aio->aio_return = SPDIF_ASYNC_STRUCT_R;
+            }
+            else
+            {
+                p_aio->aio_return = SPDIF_ASYNC_R;
+            }
+            SPDIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SPDIF_Cancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SPDIF_Open
+* @param[in]     p_aio      :aio control block to cancel or NULL to cancel all.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SPDIF_Cancel(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    spdif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (SPDIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                SPDIF_PostAsyncCancel(p_info_ch, p_aio);
+            }
+
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SPDIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_StrnLen
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*
+* @param[in]     p_str      :pointer of string.
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        < maxlen   :number of characters in the string
+* @retval        maxlen     :string is longer than maxlen
+******************************************************************************/
+static size_t SPDIF_StrnLen(const char_t p_str[], const size_t maxlen)
+{
+    size_t len;
+
+    if (NULL == p_str)
+    {
+        len = 0;
+    }
+    else
+    {
+        for (len = 0; len < maxlen; len++)
+        {
+            if ((int_t)p_str[len] == '\0')
+            {
+                break;
+            }
+        }
+    }
+
+    return len;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_Strncmp
+* @brief         Compare two strings
+*
+*                Description:<br>
+*
+* @param[in]     p_str1     :pointer of string1
+* @param[in]     p_str2     :pointer of string2
+* @param[in]     maxlen     :maximum length of comparison
+* @retval        zero       :strings are same.
+* @retval        non zero   :strings are different.
+******************************************************************************/
+static int32_t SPDIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen)
+{
+    int32_t result = 0;
+    uint32_t index;
+
+    if ((NULL == p_str1) || (NULL == p_str2))
+    {
+        result = -1;
+    }
+    else
+    {
+        for (index = 0; index < maxlen; index++)
+        {
+            /* compare charctor */
+            result = ((int_t)p_str1[index]) - ((int_t)p_str2[index]);
+            if ((result != 0)
+                || ((int_t)p_str1[index] == '\0')
+                || ((int_t)p_str2[index] == '\0'))
+            {
+                /* "charactor mismatch" or "end of string" */
+                break;
+            }
+        }
+    }
+
+    return result;
+}
+
+/******************************************************************************
+* Function Name: SPDIF_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, do nothing.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SPDIF_SetErrCode(const int_t error_code, int32_t* const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/spdif/spdif_ver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         spdif_ver.c
+* $Rev: $
+* $Date::                           $
+* @brief        SPDIF Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "spdif_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V0.01 -> MAJOR=0, MINOR=01 */
+#define SPDIF_DRV_VER_MAJOR  (0u)
+#define SPDIF_DRV_VER_MINOR  (1u)
+
+#define SPDIF_DRV_VER_MASK   (0xFFu)
+#define SPDIF_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SPDIF_GetVersion
+* @brief         Get SPDIF driver version.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SPDIF_GetVersion(void)
+{
+    const uint16_t version =
+        ((SPDIF_DRV_VER_MAJOR & SPDIF_DRV_VER_MASK) << SPDIF_DRV_VER_SHIFT)
+        | (SPDIF_DRV_VER_MINOR & SPDIF_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SPDIF_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1443 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "cmsis.h"
+#include "mbed_critical.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+/* ->MISRA 8.8, MISRA 8.10, IPA M2.2.2 : These declare statements are dependent on CMSIS-RTOS */
+osSemaphoreDef(ssif_ch0_access);
+osSemaphoreDef(ssif_ch1_access);
+osSemaphoreDef(ssif_ch2_access);
+osSemaphoreDef(ssif_ch3_access);
+/* <-MISRA 8.8, MISRA 8.10, IPA M2.2.2 */
+
+#if(1) /* mbed */
+static ssif_info_drv_t g_ssif_info_drv;
+
+ssif_info_drv_t * SSIF_GetDrvInstanc(void) {
+    return &g_ssif_info_drv;
+}
+#else
+ssif_info_drv_t g_ssif_info_drv;
+#endif
+
+volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS] = {
+    &SSIF0, &SSIF1, &SSIF2, &SSIF3
+};
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch);
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch);
+static void SSIF_Reset(const uint32_t ssif_ch);
+
+static const uint32_t gb_cpg_stbcr_bit[SSIF_NUM_CHANS] =
+{
+    0x08,    /* SSIF0 */
+    0x04,    /* SSIF1 */
+    0x02,    /* SSIF2 */
+    0x01     /* SSIF3 */
+};
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: SSIF_InitialiseOne
+* @brief         Initialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     channel    :channel number
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data)
+{
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else if (false == p_cfg_data->enabled)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[channel];
+        p_info_ch->channel = channel;
+        p_info_ch->enabled = p_cfg_data->enabled;
+
+        /* copy config data to channel info */
+        ercd = SSIF_UpdateChannelConfig(p_info_ch, p_cfg_data);
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_InitChannel(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            SSIF_InterruptInit(channel, p_cfg_data->int_level);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitialiseOne
+* @brief         UnInitialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     channel    :channel number
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SSIF_UnInitialiseOne(const int_t channel)
+{
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    p_info_ch = &g_ssif_info_drv.info_ch[channel];
+
+    if (false != p_info_ch->enabled)
+    {
+        SSIF_UnInitChannel(p_info_ch);
+    }
+
+    return ercd;
+}
+
+#endif /* end mbed */
+/******************************************************************************
+* Function Name: SSIF_Initialise
+* @brief         Initialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data)
+{
+    uint32_t        ssif_ch;
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        for (ssif_ch = 0; (ssif_ch < SSIF_NUM_CHANS) && (ESUCCESS == ercd); ssif_ch++)
+        {
+            p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+            p_info_ch->channel = ssif_ch;
+            p_info_ch->enabled = p_cfg_data[ssif_ch].enabled;
+
+            if (false != p_info_ch->enabled)
+            {
+                /* copy config data to channel info */
+                ercd = SSIF_UpdateChannelConfig(p_info_ch, &p_cfg_data[ssif_ch]);
+
+                if (ESUCCESS == ercd)
+                {
+                    ercd = SSIF_InitChannel(p_info_ch);
+                }
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+            {
+                p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+                if (false != p_info_ch->enabled)
+                {
+                    SSIF_InterruptInit(ssif_ch, p_cfg_data[ssif_ch].int_level);
+                }
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitialise
+* @brief         UnInitialize the SSIF driver's internal data
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SSIF_UnInitialise(void)
+{
+    uint32_t        ssif_ch;
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+        if (false != p_info_ch->enabled)
+        {
+            SSIF_UnInitChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_EnableChannel
+* @brief         Enable the SSIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    uint32_t ssif_ch;
+    volatile uint8_t dummy_buf;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            /* check channel open flag(duplex) */
+            if ((O_RDWR_RBSP == p_info_ch->openflag)
+                && (false == p_info_ch->is_full_duplex))
+            {
+                ercd = EINVAL_RBSP;
+            }
+
+#if defined(TARGET_RZA1H) /* mbed */
+            /* check channel open flag(romdec direct input) */
+            if (ESUCCESS == ercd)
+            {
+                if ((O_RDONLY_RBSP != p_info_ch->openflag)
+                    && (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                        == p_info_ch->romdec_direct.mode))
+                {
+                    ercd = EINVAL_RBSP;
+                }
+            }
+
+#endif /* mbed */
+            /* enable the SSIF clock */
+            if (ESUCCESS == ercd)
+            {
+                core_util_critical_section_enter();
+
+                /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+                CPG.STBCR7.BYTE &= (uint8_t)~((uint8_t)gb_cpg_stbcr_bit[ssif_ch]);
+                /* <-IPA R2.4.2 */
+                dummy_buf = CPG.STBCR7.BYTE;
+#if(1) /* mbed */
+                (void)dummy_buf;
+#endif
+
+                core_util_critical_section_exit();
+            }
+
+            /* configure channel hardware */
+            if (ESUCCESS == ercd)
+            {
+                g_ssireg[ssif_ch]->SSIFCR.BIT.AUCKE = 1;
+
+                /* software reset */
+                SSIF_Reset(ssif_ch);
+
+                /* Set control parameters */
+                ercd = SSIF_SetCtrlParams(p_info_ch);
+            }
+
+            /* allocate and setup/start DMA transfer */
+            if (ESUCCESS == ercd)
+            {
+                ercd = SSIF_InitDMA(p_info_ch);
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableChannel
+* @brief         Disable the SSIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   ret = ESUCCESS;
+    uint32_t ssif_ch;
+    volatile uint8_t dummy_buf;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ret = EFAULT_RBSP;
+        }
+        else
+        {
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR.LONG &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR.LONG |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR.LONG;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR.LONG &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* free DMA resources */
+            SSIF_UnInitDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR.LONG = 0u; /* ALL CLEAR */
+
+            g_ssireg[ssif_ch]->SSIFCR.BIT.AUCKE = 0;
+
+            /* disable ssif clock */
+            core_util_critical_section_enter();
+
+            /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+            CPG.STBCR7.BYTE |= (uint8_t)gb_cpg_stbcr_bit[ssif_ch];
+            /* <-IPA R2.4.2 */
+            dummy_buf = CPG.STBCR7.BYTE;
+            (void)dummy_buf;
+            core_util_critical_section_exit();
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_curr->aio_return = ECANCELED;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_next->aio_return = ECANCELED;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_curr->aio_return = ECANCELED;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_next->aio_return = ECANCELED;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ErrorRecovery
+* @brief         Restart the SSIF channel
+*
+*                Description:<br>
+*                When normal mode<br>
+*                  Stop and restart DMA transfer.<br>
+*                When ROMDEC direct input mode<br>
+*                  Stop DMA transfer, and execute callback function.<br>
+*                Note: This function execute in interrupt context.
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+void SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   ercd = ESUCCESS;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            /* disable DMA end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR.LONG &= ~((uint32_t)SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE);
+
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR.LONG &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR.LONG |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR.LONG;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR.LONG &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* pause DMA transfer */
+            SSIF_CancelDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR.LONG = 0u; /* ALL CLEAR */
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_curr->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_tx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_tx_next->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_curr->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_curr->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+#if(1) /* mbed */
+                p_info_ch->p_aio_rx_next->aio_return = -1;
+#else
+                p_info_ch->p_aio_rx_next->aio_return = EIO;
+#endif
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+
+        /* configure channel hardware */
+        if (ESUCCESS == ercd)
+        {
+            /* software reset */
+            SSIF_Reset(ssif_ch);
+
+            /* Set control parameters */
+            ercd = SSIF_SetCtrlParams(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+#if defined(TARGET_RZA1H) /* mbed */
+            if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                != p_info_ch->romdec_direct.mode)
+            {
+                /* setup/restart DMA transfer */
+                ercd = SSIF_RestartDMA(p_info_ch);
+            }
+            else
+            {
+                /* execute callback function */
+                if (NULL != p_info_ch->romdec_direct.p_cbfunc)
+                {
+                    (*p_info_ch->romdec_direct.p_cbfunc)();
+                }
+            }
+#else /* mbed */
+            /* setup/restart DMA transfer */
+            ercd = SSIF_RestartDMA(p_info_ch);
+#endif /* mbed */
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        /* NON_NOTICE_ASSERT: cannot restart channel */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncIo
+* @brief         Enqueue asynchronous read/write request
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block of read/write request
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (SSIF_ASYNC_W == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->tx_que, p_aio);
+        }
+        else if (SSIF_ASYNC_R == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->rx_que, p_aio);
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: illegal request type */
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncCancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block to cancel or NULL to cancel all.
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    int32_t ioif_ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (NULL == p_aio)
+        {
+            ahf_cancelall(&p_info_ch->tx_que);
+            ahf_cancelall(&p_info_ch->rx_que);
+        }
+        else
+        {
+            ioif_ret = ahf_cancel(&p_info_ch->tx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+
+            ioif_ret = ahf_cancel(&p_info_ch->rx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_ConfigChannel
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                                const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t    ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* stop DMA transfer */
+        ercd = SSIF_DisableChannel(p_info_ch);
+
+        if (ESUCCESS == ercd)
+        {
+            /* copy config data to channel info */
+            ercd = SSIF_UpdateChannelConfig(p_info_ch, p_ch_cfg);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* restart DMA transfer */
+            ercd = SSIF_EnableChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_GetStatus
+* @brief         Get a value of SSISR register.
+*
+*                Description:<br>
+*
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status)
+{
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_status))
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        *p_status = g_ssireg[p_info_ch->channel]->SSISR.LONG;
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(bits)
+******************************************************************************/
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_swl[SSIF_CFG_SYSTEM_WORD_256+1] = {
+        8,      /* SSIF_CFG_SYSTEM_WORD_8   */
+        16,     /* SSIF_CFG_SYSTEM_WORD_16  */
+        24,     /* SSIF_CFG_SYSTEM_WORD_24  */
+        32,     /* SSIF_CFG_SYSTEM_WORD_32  */
+        48,     /* SSIF_CFG_SYSTEM_WORD_48  */
+        64,     /* SSIF_CFG_SYSTEM_WORD_64  */
+        128,    /* SSIF_CFG_SYSTEM_WORD_128 */
+        256     /* SSIF_CFG_SYSTEM_WORD_256 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_swl[ssicr_swl];
+}
+
+/******************************************************************************
+* Function Name: SSIF_DWLtoLen
+* @brief         Convert SSICR:DWL bits to data word length
+*
+*                Description:<br>
+*
+* @param[in]     ssicr_dwl  :SSICR register DWL field value(0 to 6)
+* @retval        8 to 32    :data word length(bits)
+******************************************************************************/
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_dwl[SSIF_CFG_DATA_WORD_32+1] = {
+        8,   /* SSIF_CFG_DATA_WORD_8  */
+        16,  /* SSIF_CFG_DATA_WORD_16 */
+        18,  /* SSIF_CFG_DATA_WORD_18 */
+        20,  /* SSIF_CFG_DATA_WORD_20 */
+        22,  /* SSIF_CFG_DATA_WORD_22 */
+        24,  /* SSIF_CFG_DATA_WORD_24 */
+        32   /* SSIF_CFG_DATA_WORD_32 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_dwl[ssicr_dwl];
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_InitChannel
+* @brief         Initialize for the SSIF channel
+*
+*                Description:<br>
+*                Create semaphore and queue for channel.<br>
+*                And setup SSIF pin.
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    uint32_t ssif_ch;
+    int_t ercd = ESUCCESS;
+    static const osSemaphoreAttr_t* semdef_access[SSIF_NUM_CHANS] =
+    {
+        osSemaphore(ssif_ch0_access),
+        osSemaphore(ssif_ch1_access),
+        osSemaphore(ssif_ch2_access),
+        osSemaphore(ssif_ch3_access)
+    };
+    static const bool_t is_duplex_ch[SSIF_NUM_CHANS] =
+    {
+        true,   /* SSIF0 is full duplex channel */
+        true,   /* SSIF1 is full duplex channel */
+        false,  /* SSIF2 is half duplex channel */
+        true    /* SSIF3 is full duplex channel */
+    };
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        p_info_ch->is_full_duplex = is_duplex_ch[ssif_ch];
+
+        /* Create sem_access semaphore */
+        p_info_ch->sem_access = osSemaphoreNew(0xffff, 1, semdef_access[ssif_ch]);
+
+        if (NULL == p_info_ch->sem_access)
+        {
+            ercd = ENOMEM_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->tx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->rx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* set channel initialize */
+            p_info_ch->openflag = 0;
+
+            p_info_ch->p_aio_tx_curr = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_tx_next = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_rx_curr = NULL;       /* rx request pointer */
+            p_info_ch->p_aio_rx_next = NULL;       /* rx request pointer */
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = R_SSIF_Userdef_InitPinMux(ssif_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+        }
+        else
+        {
+            if (NULL != p_info_ch->sem_access)
+            {
+                os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+                if (osOK != os_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected semaphore error */
+                }
+                p_info_ch->sem_access = NULL;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitChannel
+* @brief         Uninitialise the SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+        {
+            /* NON_NOTICE_ASSERT: unexpected channel status */
+        }
+
+        p_info_ch->ch_stat = SSIF_CHSTS_UNINIT;
+
+        SSIF_DisableErrorInterrupt(ssif_ch);
+
+        core_util_critical_section_enter();
+
+        /* delete the tx queue */
+        ahf_cancelall(&p_info_ch->tx_que);
+        ahf_destroy(&p_info_ch->tx_que);
+
+        /* delete the rx queue */
+        ahf_cancelall(&p_info_ch->rx_que);
+        ahf_destroy(&p_info_ch->rx_que);
+
+        /* delete the private semaphore */
+        os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+        if (osOK != os_ret)
+        {
+            /* NON_NOTICE_ASSERT: unexpected semaphore error */
+        }
+
+        SSIF_InterruptShutdown(ssif_ch);
+
+        core_util_critical_section_exit();
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UpdateChannelConfig
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ercd = SSIF_CheckChannelCfg(p_ch_cfg);
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->slave_mode = p_ch_cfg->slave_mode;
+
+            if (false != p_info_ch->slave_mode)
+            {
+                /* slave mode */
+                p_info_ch->master_enable = SSIF_CFG_SLAVE_MODE;
+            }
+            else
+            {
+                /* master mode */
+                p_info_ch->master_enable = SSIF_CFG_MASTER_MODE;
+
+                /* when master mode, always disable noise cancel */
+                p_info_ch->noise_cancel = SSIF_CFG_DISABLE_NOISE_CANCEL;
+            }
+
+            p_info_ch->sample_freq        = p_ch_cfg->sample_freq;
+
+            if (p_ch_cfg->clk_select == SSIF_CFG_CKS_AUDIO_CLK) {
+                p_info_ch->clk_select     = 0;
+            } else {
+                p_info_ch->clk_select     = 1;
+            }
+            p_info_ch->multi_ch           = p_ch_cfg->multi_ch;
+            p_info_ch->data_word          = p_ch_cfg->data_word;
+            p_info_ch->system_word        = p_ch_cfg->system_word;
+            p_info_ch->bclk_pol           = p_ch_cfg->bclk_pol;
+            p_info_ch->ws_pol             = p_ch_cfg->ws_pol;
+            p_info_ch->padding_pol        = p_ch_cfg->padding_pol;
+            p_info_ch->serial_alignment   = p_ch_cfg->serial_alignment;
+            p_info_ch->parallel_alignment = p_ch_cfg->parallel_alignment;
+            p_info_ch->ws_delay           = p_ch_cfg->ws_delay;
+            p_info_ch->noise_cancel       = p_ch_cfg->noise_cancel;
+            p_info_ch->tdm_mode           = p_ch_cfg->tdm_mode;
+#if defined(TARGET_RZA1H) /* mbed */
+            p_info_ch->romdec_direct.mode     = p_ch_cfg->romdec_direct.mode;
+            p_info_ch->romdec_direct.p_cbfunc = p_ch_cfg->romdec_direct.p_cbfunc;
+#endif /* mbed */
+
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* check combination of parameters */
+                if ((SSIF_CFG_MULTI_CH_1 == p_info_ch->multi_ch)
+                    || (SSIF_CFG_WS_HIGH == p_info_ch->ws_pol))
+                {
+                    ercd = EINVAL_RBSP;
+                }
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_CheckWordSize(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->slave_mode)
+            {
+                /* Master: call user own clock setting function */
+                ercd = R_SSIF_Userdef_SetClockDiv(p_ch_cfg, &p_info_ch->clk_div);
+            }
+            else
+            {
+                /* Slave: set dummy value for clear */
+                p_info_ch->clk_div = SSIF_CFG_CKDV_BITS_1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetCtrlParams
+* @brief         Set SSIF configuration to hardware.
+*
+*                Description:<br>
+*                Update SSICR register.
+* @param[in]     p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t ret = ESUCCESS;
+    uint32_t ssif_ch;
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* ALL CLEAR */
+        g_ssireg[ssif_ch]->SSICR.LONG = 0u;
+        g_ssireg[ssif_ch]->SSISR.LONG = 0u;
+
+        g_ssireg[ssif_ch]->SSICR.LONG = (uint32_t)(
+             ((uint32_t)(p_info_ch->clk_select)         << SSIF_CR_SHIFT_CKS) |
+             ((uint32_t)(p_info_ch->multi_ch)           << SSIF_CR_SHIFT_CHNL) |
+             ((uint32_t)(p_info_ch->data_word)          << SSIF_CR_SHIFT_DWL) |
+             ((uint32_t)(p_info_ch->system_word)        << SSIF_CR_SHIFT_SWL) |
+             ((uint32_t)(p_info_ch->bclk_pol)           << SSIF_CR_SHIFT_SCKP) |
+             ((uint32_t)(p_info_ch->ws_pol)             << SSIF_CR_SHIFT_SWSP) |
+             ((uint32_t)(p_info_ch->padding_pol)        << SSIF_CR_SHIFT_SPDP) |
+             ((uint32_t)(p_info_ch->serial_alignment)   << SSIF_CR_SHIFT_SDTA) |
+             ((uint32_t)(p_info_ch->parallel_alignment) << SSIF_CR_SHIFT_PDTA) |
+             ((uint32_t)(p_info_ch->ws_delay)           << SSIF_CR_SHIFT_DEL) |
+             ((uint32_t)(p_info_ch->master_enable)      << SSIF_CR_SHIFT_MST) |
+             ((uint32_t)(p_info_ch->clk_div)            << SSIF_CR_SHIFT_CKDV)
+             );
+
+        if (p_info_ch->tdm_mode == 0) {
+            g_ssireg[ssif_ch]->SSIOFR.BIT.OMOD = 0x0;
+        } else {
+            g_ssireg[ssif_ch]->SSIOFR.BIT.OMOD = 0x1;
+        }
+
+        /* change SNCR register: enter exclusive */
+        core_util_critical_section_enter();
+
+        /* change SNCR register: exit exclusive */
+        core_util_critical_section_exit();
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckChannelCfg
+* @brief         Check channel configuration parameters are valid or not.
+*
+*                Description:<br>
+*
+* @param[in]     p_ch_cfg     :channel configuration
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_ch_cfg)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        switch (p_ch_cfg->clk_select)
+        {
+        case SSIF_CFG_CKS_AUDIO_X1:
+            /* fall through */
+        case SSIF_CFG_CKS_AUDIO_CLK:
+            /* do nothing */
+            break;
+        default:
+            ret = EINVAL_RBSP;
+            break;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->multi_ch)
+            {
+            case SSIF_CFG_MULTI_CH_1:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_2:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_3:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_4:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->data_word)
+            {
+            case SSIF_CFG_DATA_WORD_8:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_16:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_18:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_20:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_22:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_24:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_32:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->system_word)
+            {
+            case SSIF_CFG_SYSTEM_WORD_8:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_16:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_24:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_32:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_48:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_64:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_128:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_256:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->bclk_pol)
+            {
+            case SSIF_CFG_FALLING:
+                /* fall through */
+            case SSIF_CFG_RISING:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_pol)
+            {
+            case SSIF_CFG_WS_LOW:
+                /* fall through */
+            case SSIF_CFG_WS_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->padding_pol)
+            {
+            case SSIF_CFG_PADDING_LOW:
+                /* fall through */
+            case SSIF_CFG_PADDING_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->serial_alignment)
+            {
+            case SSIF_CFG_DATA_FIRST:
+                /* fall through */
+            case SSIF_CFG_PADDING_FIRST:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->parallel_alignment)
+            {
+            case SSIF_CFG_LEFT:
+                /* fall through */
+            case SSIF_CFG_RIGHT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_delay)
+            {
+            case SSIF_CFG_DELAY:
+                /* fall through */
+            case SSIF_CFG_NO_DELAY:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->noise_cancel)
+            {
+            case SSIF_CFG_DISABLE_NOISE_CANCEL:
+                /* fall through */
+            case SSIF_CFG_ENABLE_NOISE_CANCEL:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->tdm_mode)
+            {
+            case SSIF_CFG_DISABLE_TDM:
+                /* fall through */
+            case SSIF_CFG_ENABLE_TDM:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+#if defined(TARGET_RZA1H) /* mbed */
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->romdec_direct.mode)
+            {
+            case SSIF_CFG_DISABLE_ROMDEC_DIRECT:
+                /* fall through */
+            case SSIF_CFG_ENABLE_ROMDEC_DIRECT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL_RBSP;
+                break;
+            }
+        }
+#endif /* mbed */
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckWordSize
+* @brief         Check system word size whether that is valid or not.
+*
+*                Description:<br>
+*                if system_words couldn't involve specified number of<br>
+*                data_words then error.
+* @param[in]     p_info_ch    :channel object
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t ssicr_chnl;
+    uint32_t dw_per_sw;
+    uint32_t datawd_len;
+    uint32_t syswd_len;
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        ssicr_chnl = p_info_ch->multi_ch;
+        /* ->MISRA 13.7 : This is verbose error check by way of precaution */
+        if (SSIF_CFG_MULTI_CH_4 < ssicr_chnl)
+        /* <-MISRA 13.7 */
+        {
+            ret = EINVAL_RBSP;
+        }
+        else
+        {
+            /* data_words number per system_words */
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* When TDM Mode data_word number per system_words fixed to 1 */
+                dw_per_sw = 1u;
+            }
+            else
+            {
+                /* When not TDM data_word number per system_words depends CHNL */
+                dw_per_sw = ssicr_chnl + 1u;
+            }
+
+            /* size of data_words */
+            datawd_len = (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+            if (0u == datawd_len)
+            {
+                ret = EINVAL_RBSP;
+            }
+            else
+            {
+                /* size of system_words */
+                syswd_len = (uint32_t)SSIF_SWLtoLen(p_info_ch->system_word);
+
+                if (syswd_len < (datawd_len * dw_per_sw))
+                {
+                    ret = EINVAL_RBSP;
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Reset
+* @brief         SSIF software reset
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch       :SSIF channel
+* @retval        none
+******************************************************************************/
+static void SSIF_Reset(const uint32_t ssif_ch)
+{
+    g_ssireg[ssif_ch]->SSIFCR.BIT.SSIRST = 1;
+    while (g_ssireg[ssif_ch]->SSIFCR.BIT.SSIRST != 1) {
+        ;
+    }
+    g_ssireg[ssif_ch]->SSIFCR.BIT.SSIRST = 0;
+    while (g_ssireg[ssif_ch]->SSIFCR.BIT.SSIRST != 0) {
+        ;
+    }
+
+    return;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,267 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif.h
+* $Rev: $
+* $Date::                           $
+* Description  : SSIF driver functions header
+******************************************************************************/
+
+#ifndef SSIF_H
+#define SSIF_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "aioif.h"
+#include "iodefine.h"
+#include "ssif_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIF_CHNUM_4    (4u)
+#define SSIF_CHNUM_5    (5u)
+#endif /* mbed */
+
+#define SSIF_CHSTR_0 "\\0"
+#define SSIF_CHSTR_1 "\\1"
+#define SSIF_CHSTR_2 "\\2"
+#define SSIF_CHSTR_3 "\\3"
+#if defined(TARGET_RZA1H) /* mbed */
+#define SSIF_CHSTR_4 "\\4"
+#define SSIF_CHSTR_5 "\\5"
+#endif /* mbed */
+
+#define SSIF_MAX_PATH_LEN           (32u)
+
+#define SSIF_CR_SHIFT_CKS   (30u)
+#define SSIF_CR_SHIFT_TUIEN (29u)
+#define SSIF_CR_SHIFT_TOIEN (28u)
+#define SSIF_CR_SHIFT_RUIEN (27u)
+#define SSIF_CR_SHIFT_ROIEN (26u)
+#define SSIF_CR_SHIFT_IIEN  (25u)
+#define SSIF_CR_SHIFT_CHNL  (22u)
+#define SSIF_CR_SHIFT_DWL   (19u)
+#define SSIF_CR_SHIFT_SWL   (16u)
+#define SSIF_CR_SHIFT_MST   (14u)
+#define SSIF_CR_SHIFT_SCKP  (13u)
+#define SSIF_CR_SHIFT_SWSP  (12u)
+#define SSIF_CR_SHIFT_SPDP  (11u)
+#define SSIF_CR_SHIFT_SDTA  (10u)
+#define SSIF_CR_SHIFT_PDTA  ( 9u)
+#define SSIF_CR_SHIFT_DEL   ( 8u)
+#define SSIF_CR_SHIFT_CKDV  ( 4u)
+#define SSIF_CR_SHIFT_MUEN  ( 3u)
+#define SSIF_CR_SHIFT_TEN   ( 1u)
+#define SSIF_CR_SHIFT_REN   ( 0u)
+
+#define SSIF_CR_BIT_CKS     (1u << SSIF_CR_SHIFT_CKS)
+#define SSIF_CR_BIT_TUIEN   (1u << SSIF_CR_SHIFT_TUIEN)
+#define SSIF_CR_BIT_TOIEN   (1u << SSIF_CR_SHIFT_TOIEN)
+#define SSIF_CR_BIT_RUIEN   (1u << SSIF_CR_SHIFT_RUIEN)
+#define SSIF_CR_BIT_ROIEN   (1u << SSIF_CR_SHIFT_ROIEN)
+#define SSIF_CR_BIT_IIEN    (1u << SSIF_CR_SHIFT_IIEN)
+#define SSIF_CR_BITS_CHNL   (3u << SSIF_CR_SHIFT_CHNL)
+#define SSIF_CR_BITS_DWL    (7u << SSIF_CR_SHIFT_DWL)
+#define SSIF_CR_BITS_SWL    (7u << SSIF_CR_SHIFT_SWL)
+#define SSIF_CR_BIT_MST     (1u << SSIF_CR_SHIFT_MST)
+#define SSIF_CR_BIT_SCKP    (1u << SSIF_CR_SHIFT_SCKP)
+#define SSIF_CR_BIT_SWSP    (1u << SSIF_CR_SHIFT_SWSP)
+#define SSIF_CR_BIT_SPDP    (1u << SSIF_CR_SHIFT_SPDP)
+#define SSIF_CR_BIT_SDTA    (1u << SSIF_CR_SHIFT_SDTA)
+#define SSIF_CR_BIT_PDTA    (1u << SSIF_CR_SHIFT_PDTA)
+#define SSIF_CR_BIT_DEL     (1u << SSIF_CR_SHIFT_DEL)
+#define SSIF_CR_BITS_CKDV   (0xfu << SSIF_CR_SHIFT_CKDV)
+#define SSIF_CR_BIT_MUEN    (1u << SSIF_CR_SHIFT_MUEN)
+#define SSIF_CR_BIT_TEN     (1u << SSIF_CR_SHIFT_TEN)
+#define SSIF_CR_BIT_REN     (1u << SSIF_CR_SHIFT_REN)
+#define SSIF_CR_INT_ERR_MASK    (SSIF_CR_BIT_TUIEN | SSIF_CR_BIT_TOIEN | SSIF_CR_BIT_RUIEN | SSIF_CR_BIT_ROIEN)
+
+#define SSIF_SR_SHIFT_TUIRQ (29u)
+#define SSIF_SR_SHIFT_TOIRQ (28u)
+#define SSIF_SR_SHIFT_RUIRQ (27u)
+#define SSIF_SR_SHIFT_ROIRQ (26u)
+#define SSIF_SR_SHIFT_IIRQ  (25u)
+#define SSIF_SR_SHIFT_IDST  ( 0u)
+
+#define SSIF_SR_BIT_TUIRQ   (1u << SSIF_SR_SHIFT_TUIRQ)
+#define SSIF_SR_BIT_TOIRQ   (1u << SSIF_SR_SHIFT_TOIRQ)
+#define SSIF_SR_BIT_RUIRQ   (1u << SSIF_SR_SHIFT_RUIRQ)
+#define SSIF_SR_BIT_ROIRQ   (1u << SSIF_SR_SHIFT_ROIRQ)
+#define SSIF_SR_BIT_IIRQ    (1u << SSIF_SR_SHIFT_IIRQ)
+#define SSIF_SR_BIT_IDST    (1u << SSIF_SR_SHIFT_IDST)
+#define SSIF_SR_INT_ERR_MASK    (SSIF_SR_BIT_TUIRQ | SSIF_SR_BIT_TOIRQ | SSIF_SR_BIT_RUIRQ | SSIF_SR_BIT_ROIRQ)
+
+#define SSIF_FCR_SHIFT_TIE      (3u)
+#define SSIF_FCR_SHIFT_RIE      (2u)
+#define SSIF_FCR_SHIFT_TFRST    (1u)
+#define SSIF_FCR_SHIFT_RFRST    (0u)
+
+#define SSIF_FCR_BIT_TIE   (1u << SSIF_FCR_SHIFT_TIE)
+#define SSIF_FCR_BIT_RIE   (1u << SSIF_FCR_SHIFT_RIE)
+#define SSIF_FCR_BIT_TFRST (1u << SSIF_FCR_SHIFT_TFRST)
+#define SSIF_FCR_BIT_RFRST (1u << SSIF_FCR_SHIFT_RFRST)
+
+#define SSIF_TDMR_SHIFT_CONT    (8u)
+#define SSIF_TDMR_SHIFT_TDM     (0u)
+
+#define SSIF_TDMR_BIT_CONT (1u << SSIF_TDMR_SHIFT_CONT)
+#define SSIF_TDMR_BIT_TDM  (1u << SSIF_TDMR_SHIFT_TDM)
+
+/* noise canceled bit */
+#define GPIO_SNCR_BIT_SSI5NCE  (1u << 5)
+#define GPIO_SNCR_BIT_SSI4NCE  (1u << 4)
+#define GPIO_SNCR_BIT_SSI3NCE  (1u << 3)
+#define GPIO_SNCR_BIT_SSI2NCE  (1u << 2)
+#define GPIO_SNCR_BIT_SSI1NCE  (1u << 1)
+#define GPIO_SNCR_BIT_SSI0NCE  (1u << 0)
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+typedef enum {
+    SSIF_DRVSTS_UNINIT = 0,
+    SSIF_DRVSTS_INIT
+} ssif_drv_stat_t;
+
+typedef enum
+{
+    SSIF_CHSTS_UNINIT = 0,
+    SSIF_CHSTS_INIT,
+    SSIF_CHSTS_OPEN
+} ssif_ch_stat_t;
+
+typedef enum
+{
+    SSIF_ASYNC_W = 0,
+    SSIF_ASYNC_R
+} ssif_rw_mode_t;
+
+/** Serial word select direction */
+typedef enum
+{
+    SSIF_CFG_SLAVE_MODE  = 0,     /**< Slave mode */
+    SSIF_CFG_MASTER_MODE = 1      /**< Master mode */
+} ssif_chcfg_mst_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+typedef struct ssif_info_ch
+{
+    uint32_t    channel;
+    bool_t      enabled;
+    bool_t      slave_mode;
+    uint32_t    sample_freq;
+    ssif_ch_stat_t ch_stat;
+    osSemaphoreId_t sem_access;
+    AHF_S       tx_que;
+    AHF_S       rx_que;
+    int_t       dma_rx_ch;
+    int_t       dma_tx_ch;
+    bool_t      is_full_duplex;         /* full/half duplex */
+    int_t       openflag;
+    AIOCB*      p_aio_tx_curr;
+    AIOCB*      p_aio_tx_next;
+    AIOCB*      p_aio_rx_curr;
+    AIOCB*      p_aio_rx_next;
+    ssif_chcfg_cks_t                clk_select;
+    ssif_chcfg_multi_ch_t           multi_ch;
+    ssif_chcfg_data_word_t          data_word;
+    ssif_chcfg_system_word_t        system_word;
+    ssif_chcfg_mst_t                master_enable;
+    ssif_chcfg_clock_pol_t          bclk_pol;
+    ssif_chcfg_ws_pol_t             ws_pol;
+    ssif_chcfg_padding_pol_t        padding_pol;
+    ssif_chcfg_serial_alignment_t   serial_alignment;
+    ssif_chcfg_parallel_alignment_t parallel_alignment;
+    ssif_chcfg_ws_delay_t           ws_delay;
+    ssif_chcfg_noise_cancel_t       noise_cancel;
+    ssif_chcfg_tdm_t                tdm_mode;
+    ssif_chcfg_ckdv_t               clk_div;
+#if defined(TARGET_RZA1H) /* mbed */
+    ssif_chcfg_romdec_t             romdec_direct;
+#endif /* mbed */
+#if(1) /* mbed */
+    uint8_t     int_level;
+#endif
+} ssif_info_ch_t;
+
+
+typedef struct ssif_info_drv
+{
+    ssif_drv_stat_t drv_stat;
+    ssif_info_ch_t  info_ch[SSIF_NUM_CHANS];
+} ssif_info_drv_t;
+
+extern volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS];
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialiseOne(const int_t channel);
+#endif /* end mbed */
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialise(void);
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch);
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch);
+void  SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch);
+
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                const ssif_channel_cfg_t* const p_ch_cfg);
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status);
+
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch);
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch);
+
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl);
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl);
+
+#if(1) /* mbed */
+extern ssif_info_drv_t * SSIF_GetDrvInstanc(void);
+#else
+extern ssif_info_drv_t g_ssif_info_drv;
+#endif /* end mbed */
+
+#endif /* SSIF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif_cfg.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,330 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_cfg.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver userown functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "dma_if.h"
+#include "ssif_if.h"
+#include "iodefine.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/***** Audio Clock Source Configurations *****/
+/* AUDIO_X1 :  */
+#define SSIF_AUDIO_X1  (0u)
+
+/* AUDIO_CLK: */
+#define SSIF_AUDIO_CLK (11289600u)
+
+/* SSICR CKDV divieded value */
+#define SSIF_AUDIO_CLK_DIV_1    (1u)
+#define SSIF_AUDIO_CLK_DIV_2    (2u)
+#define SSIF_AUDIO_CLK_DIV_4    (4u)
+#define SSIF_AUDIO_CLK_DIV_8    (8u)
+#define SSIF_AUDIO_CLK_DIV_16   (16u)
+#define SSIF_AUDIO_CLK_DIV_32   (32u)
+#define SSIF_AUDIO_CLK_DIV_64   (64u)
+#define SSIF_AUDIO_CLK_DIV_128  (128u)
+#define SSIF_AUDIO_CLK_DIV_6    (6u)
+#define SSIF_AUDIO_CLK_DIV_12   (12u)
+#define SSIF_AUDIO_CLK_DIV_24   (24u)
+#define SSIF_AUDIO_CLK_DIV_48   (48u)
+#define SSIF_AUDIO_CLK_DIV_96   (96u)
+
+/* SSIF channel number */
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+
+/* misc constant value */
+#define SSIF_I2S_LR_CH  (2u)
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+#if(1) /* mbed */
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+    UNUSED_ARG(ssif_ch);
+
+    return ESUCCESS;
+}
+#else  /* not mbed */
+#include  "mbed_critical.h"
+
+#if defined(TARGET_RZA1H) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_InitPinMux
+* @brief         This function initialise pin multiplex settings.
+*
+*                Description:<br>
+*                R7S72100 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: Working with SSIF5<br>
+*                Channel settings<br>
+*                  SSIF0    : Fully connected to WM8978<br>
+*                  SSIF1    : Read only (NC:SSITxD1) connected to CD Deck<br>
+*                  SSIF2    : No connection<br>
+*                  SSIF3    : Write only (NC:SSIRxD3) connected to AK4353<br>
+*                  SSIF4    : Fully connected to AK4353<br>
+*                  SSIF5    : Fully connected to HCI
+* @param[in]     ssif_ch      :channel number.
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+    int_t ercd = ESUCCESS;
+
+    core_util_critical_section_enter();
+
+    /* -> IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 16bit register. */
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            break;
+
+        case SSIF_CHNUM_1:
+            break;
+
+        case SSIF_CHNUM_2:
+            break;
+
+        case SSIF_CHNUM_3:
+            break;
+
+        default:
+            ercd = EINVAL;
+            break;
+    }
+    /* <- IPA R2.4.2 */
+
+    core_util_critical_section_exit();
+
+    return ercd;
+}
+#else /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_InitPinMux
+* @brief         This function initialise pin multiplex settings.
+*
+*                Description:<br>
+*                R7S72103 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: This port is not set.
+*                             (If you don't use EtherAVB, don't need to set.)
+*                Channel settings<br>
+*                  SSIF0    : No connection<br>
+*                  SSIF1    : Fully connected to AK4353<br>
+*                  SSIF2    : Fully connected to WM8978<br>
+*                  SSIF3    : No connection<br>
+* @param[in]     ssif_ch      :channel number.
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+    int_t ercd = ESUCCESS;
+
+    core_util_critical_section_enter();
+
+    /* -> IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 16bit register. */
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            break;
+
+        case SSIF_CHNUM_1:
+            break;
+
+        case SSIF_CHNUM_2:
+            break;
+
+        case SSIF_CHNUM_3:
+            break;
+
+        default:
+            ercd = EINVAL;
+            break;
+    }
+    /* <- IPA R2.4.2 */
+
+    core_util_critical_section_exit();
+
+    return ercd;
+}
+#endif /* end mbed */
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_SetClockDiv
+* @brief         This function make a value of divieded audio clock.
+*
+*                Description:<br>
+*
+* @param[in]     p_ch_cfg     :pointer of channel configuration parameter.
+* @param[in,out] p_clk_div    :pointer of SSICR register CKDV value
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div)
+{
+    uint32_t input_clk;
+    uint32_t dot_clk;
+    uint32_t n_syswd_per_smp;
+    uint32_t syswd_len;
+    uint32_t smp_freq;
+    uint32_t result;
+    uint32_t division;
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_ch_cfg) || (NULL == p_clk_div))
+    {
+        ret = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SSIF_CFG_CKS_AUDIO_X1 == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_X1;
+        }
+        else if (SSIF_CFG_CKS_AUDIO_CLK == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_CLK;
+        }
+        else
+        {
+            input_clk = 0u;
+        }
+
+        if (0u == input_clk)
+        {
+            ret = EINVAL_RBSP;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            syswd_len = (uint32_t)R_SSIF_SWLtoLen(p_ch_cfg->system_word);
+            smp_freq = p_ch_cfg->sample_freq;
+
+            if (SSIF_CFG_DISABLE_TDM == p_ch_cfg->tdm_mode)
+            {
+                /* I2S format has 2 system_words */
+                n_syswd_per_smp = SSIF_I2S_LR_CH;
+            }
+            else
+            {
+                /* TDM frame has [(CHNL+1) * 2] system_words */
+                n_syswd_per_smp = (((uint32_t)p_ch_cfg->multi_ch) + 1) * SSIF_I2S_LR_CH;
+            }
+
+            dot_clk = syswd_len * n_syswd_per_smp * smp_freq / 2;
+
+            if (0u == dot_clk)
+            {
+                ret = EINVAL_RBSP;
+            }
+            else
+            {
+                /* check if input audio clock can be divided by dotclock */
+                result = input_clk % dot_clk;
+
+                if (0u != result)
+                {
+                    /* cannot create dotclock from input audio clock */
+                    ret = EINVAL_RBSP;
+                }
+                else
+                {
+                    division = input_clk / dot_clk;
+
+                    switch (division)
+                    {
+                    case SSIF_AUDIO_CLK_DIV_1:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_1;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_2:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_2;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_4:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_4;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_8:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_8;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_16:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_16;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_32:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_32;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_64:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_64;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_128:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_128;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_6:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_6;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_12:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_12;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_24:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_24;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_48:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_48;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_96:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_96;
+                        break;
+                    default:
+                        ret = EINVAL_RBSP;
+                        break;
+                    }
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif_dma.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,787 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_dma.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver DMA functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "dma_if.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_DUMMY_DMA_BUF_SIZE (4096u)
+
+/*
+ * The common multiple of 2, 4, 6, 8, 12, 24 and 32
+ * which are all sampling sizes
+ */
+#define SSIF_DUMMY_DMA_TRN_SIZE (4032u)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+static void SSIF_DMA_TxCallback(union sigval param);
+static void SSIF_DMA_RxCallback(union sigval param);
+
+static const dma_res_select_t gb_ssif_dma_tx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSITXI0,
+    DMA_RS_SSITXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSITXI3
+};
+
+static const dma_res_select_t gb_ssif_dma_rx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSIRXI0,
+    DMA_RS_SSIRXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSIRXI3
+};
+
+static AIOCB gb_ssif_dma_tx_end_aiocb[SSIF_NUM_CHANS];
+static AIOCB gb_ssif_dma_rx_end_aiocb[SSIF_NUM_CHANS];
+
+static dma_trans_data_t gb_ssif_txdma_dummy_trparam[SSIF_NUM_CHANS];
+static dma_trans_data_t gb_ssif_rxdma_dummy_trparam[SSIF_NUM_CHANS];
+
+static uint32_t ssif_tx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE / sizeof(uint32_t)];
+static uint32_t ssif_rx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE / sizeof(uint32_t)];
+
+/******************************************************************************
+* Function Name: SSIF_InitDMA
+* @brief         Allocate and Setup DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* allocate DMA Channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                p_info_ch->dma_tx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_tx_ch = -1;
+                    ercd = ENOMEM_RBSP;
+                }
+                else
+                {
+                    p_info_ch->dma_tx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* allocate DMA Channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                p_info_ch->dma_rx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_rx_ch = -1;
+                    ercd = ENOMEM_RBSP;
+                }
+                else
+                {
+                    p_info_ch->dma_rx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR.LONG;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR.LONG;
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR.LONG |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR_RBSP == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR.LONG  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR.LONG  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR.LONG  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL_RBSP;
+            }
+        }
+
+        /* cleanup dma resources when error occured */
+        if (ESUCCESS != ercd)
+        {
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_tx_ch = -1;
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_rx_ch = -1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitDMA
+* @brief         Free DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_tx_ch = -1;
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_rx_ch = -1;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_RestartDMA
+* @brief         Setup DMA_CH for specified SSIF channel(without allocate)
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+#if(1) /* mbed */
+                dma_ch_setup.int_level = p_info_ch->int_level;
+#endif
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR.LONG;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY_RBSP != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR.LONG;
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].count = SSIF_DUMMY_DMA_TRN_SIZE;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT_RBSP;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT_RBSP;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR.LONG |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR_RBSP == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR.LONG  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR.LONG  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY_RBSP == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR.LONG  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL_RBSP;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CancelDMA
+* @brief         Pause DMA transfer for specified SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_DMA_TxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_TxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+#if(1) /* mbed */
+    int32_t ercd = ESUCCESS;
+#else
+    int_t ercd = ESUCCESS;
+#endif
+    int_t ret;
+
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_tx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_tx_curr->aio_return = (ssize_t)p_info_ch->p_aio_tx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_tx_curr = p_info_ch->p_aio_tx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_tx_next = ahf_removehead(&p_info_ch->tx_que);
+
+        if (NULL != p_info_ch->p_aio_tx_next)
+        {
+            /* add user request */
+            dma_data_next.dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR.LONG;
+            dma_data_next.src_addr = (void*)p_info_ch->p_aio_tx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_tx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DMA_RxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_RxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+#if(1) /* mbed */
+    int32_t ercd = ESUCCESS;
+#else
+    int_t ercd = ESUCCESS;
+#endif
+    int_t ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_rx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_rx_curr->aio_return = (ssize_t)p_info_ch->p_aio_rx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_rx_curr = p_info_ch->p_aio_rx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_rx_next = ahf_removehead(&p_info_ch->rx_que);
+
+        if (NULL != p_info_ch->p_aio_rx_next)
+        {
+            /* add user request */
+            dma_data_next.src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR.LONG;
+            dma_data_next.dst_addr = (void*)p_info_ch->p_aio_rx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_rx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif_if.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,944 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_if.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver interface functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "cmsis_os.h"
+#if(1) /* mbed */
+#include "r_bsp_cmn.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+#include "ssif.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+#if(1) /* mbed */
+static ssif_drv_stat_t ch_drv_stat[SSIF_NUM_CHANS] = {SSIF_DRVSTS_UNINIT};
+
+static void* R_SSIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno);
+static int_t R_SSIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno);
+#else  /* not mbed */
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno);
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno);
+#endif /* end mbed */
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno);
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno);
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno);
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* p_aio, int32_t* const p_errno);
+
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen);
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen);
+static void   SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_MakeCbTbl_mbed
+* @brief         Make the SSIF driver function callback table
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of SSIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+RBSP_MBED_FNS* R_SSIF_MakeCbTbl_mbed(void)
+/* <-IPA M1.1.1 */
+{
+    static RBSP_MBED_FNS ssif_apitbl_mbed;
+
+    ssif_apitbl_mbed.initialise_one   = &R_SSIF_InitOne;
+    ssif_apitbl_mbed.uninitialise_one = &R_SSIF_UnInitOne;
+    ssif_apitbl_mbed.open             = &R_SSIF_Open;
+    ssif_apitbl_mbed.close            = &R_SSIF_Close;
+    ssif_apitbl_mbed.ioctl            = &R_SSIF_Ioctl;
+    ssif_apitbl_mbed.read_a           = &R_SSIF_ReadAsync;
+    ssif_apitbl_mbed.write_a          = &R_SSIF_WriteAsync;
+    ssif_apitbl_mbed.cancel           = &R_SSIF_Cancel;
+
+    return &ssif_apitbl_mbed;
+}
+#else  /* not mbed */
+/******************************************************************************
+* Function Name: R_SSIF_MakeCbTbl
+* @brief         Make the SSIF driver function callback table
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        pointer of SSIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+IOIF_DRV_API* R_SSIF_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    static IOIF_DRV_API ssif_apitbl;
+
+    /* ->MISRA 16.4, IPA M4.5.1 : This is IOIF library API type definitnon that can't be modified. */
+    ssif_apitbl.family = IOIF_SERIAL_FAMILY;
+    ssif_apitbl.fns.serial.initialise   = &R_SSIF_Init;
+    ssif_apitbl.fns.serial.uninitialise = &R_SSIF_UnInit;
+    ssif_apitbl.fns.serial.open         = &R_SSIF_Open;
+    ssif_apitbl.fns.serial.close        = &R_SSIF_Close;
+    ssif_apitbl.fns.serial.ioctl        = &R_SSIF_Ioctl;
+    ssif_apitbl.fns.serial.read_a       = &R_SSIF_ReadAsync;
+    ssif_apitbl.fns.serial.write_a      = &R_SSIF_WriteAsync;
+    ssif_apitbl.fns.serial.cancel       = &R_SSIF_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+
+    return &ssif_apitbl;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(byte)
+******************************************************************************/
+int_t R_SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    return SSIF_SWLtoLen(ssicr_swl);
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_InitOne
+* @brief         Initialise the SSIF driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel     :channel number
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SSIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT_RBSP;
+    }
+#if(1) /* mbed */
+    else if ((uint32_t)channel >= SSIF_NUM_CHANS)
+#else
+    else if (channel >= SSIF_NUM_CHANS)
+#endif
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+#if(1) /* mbed */
+        ssif_info_drv_t* const p_info_drv = SSIF_GetDrvInstanc();
+        p_info_drv->drv_stat = SSIF_DRVSTS_INIT;
+#else
+        g_ssif_info_drv.drv_stat = SSIF_DRVSTS_INIT;
+#endif /* end mbed */
+        ch_drv_stat[channel] = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_InitialiseOne(channel, (const ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+#if(1) /* mbed */
+            p_ret = (void*)p_info_drv;
+#else
+            p_ret = (void*)&g_ssif_info_drv;
+#endif /* end mbed */
+        }
+        else
+        {
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_UnInitOne
+* @brief         Uninitialise the SSIF deiver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel         :channel number
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SSIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SSIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+
+    if (NULL == driver_instance)
+    {
+        ercd = EFAULT_RBSP;
+    }
+#if(1) /* mbed */
+    else if ((uint32_t)channel >= SSIF_NUM_CHANS)
+#else
+    else if (channel >= SSIF_NUM_CHANS)
+#endif
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != ch_drv_stat[channel])
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialiseOne(channel);
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+#else  /* not mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Init
+* @brief         Initialise the SSIF driver.
+*
+*                Description:<br>
+*
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (SSIF_DRVSTS_UNINIT != g_ssif_info_drv.drv_stat)
+    {
+        ercd = EBUSY;
+    }
+    else
+    {
+        g_ssif_info_drv.drv_stat = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_Initialise((ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+            p_ret = (void*)&g_ssif_info_drv;
+        }
+        else
+        {
+            g_ssif_info_drv.drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_UnInit
+* @brief         Uninitialise the SSIF deiver.
+*
+*                Description:<br>
+*
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SSIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+    ssif_info_drv_t* const p_info_drv   = driver_instance;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialise();
+            p_info_drv->drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Open
+* @brief         Open an SSIF channel
+*
+*                Description:<br>
+*
+* @param[in,out] p_drv_instance :driver instance which was returned by<br>
+                                 R_SSIF_Init
+* @param[in]     p_path_name    :string of channel
+* @param[in]     flags          :access mode whether the channel is opened<br>
+                                 for a read or a write
+* @param[in]     mode           :not used
+* @param[in,out] p_errno        :pointer of error code
+* @retval        not EERROR     :channel handle
+* @retval        EERROR         :Failure.
+******************************************************************************/
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno)
+{
+    uint32_t ssif_ch;
+    void* p_channelHandle;
+    size_t len;
+    size_t req_path_len;
+    ssif_info_drv_t* const p_info_drv = p_driver_instance;
+    ssif_info_ch_t* p_info_ch = NULL;
+    int_t ret;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+    static const char_t* const ch_name_string[SSIF_NUM_CHANS] =
+    {
+        SSIF_CHSTR_0,
+        SSIF_CHSTR_1,
+        SSIF_CHSTR_2,
+        SSIF_CHSTR_3
+    };
+
+    UNUSED_ARG(mode);
+
+    if ((NULL == p_info_drv) || (NULL == p_path_name))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        req_path_len = strlen(p_path_name);
+        if (0u == req_path_len)
+        {
+            ercd = ENOENT_RBSP;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* Serch the same pathname */
+            for (ssif_ch = 0u; (ssif_ch < SSIF_NUM_CHANS) && (p_info_ch == NULL); ssif_ch++)
+            {
+                len = SSIF_StrnLen(ch_name_string[ssif_ch], SSIF_MAX_PATH_LEN);
+
+                if (req_path_len < len)
+                {
+                    len = req_path_len;
+                }
+
+                if (0 == SSIF_Strncmp(p_path_name, ch_name_string[ssif_ch], len))
+                {
+                    /* found a match */
+                    p_info_ch = &p_info_drv->info_ch[ssif_ch];
+                }
+            }
+        }
+    }
+
+    if (NULL == p_info_ch)
+    {
+        ercd = ENOENT_RBSP;
+    }
+    else
+    {
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->enabled)
+            {
+                ercd = ENOTSUP_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+            {
+                ercd = EBADF_RBSP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                p_info_ch->openflag = flags;
+                p_info_ch->p_aio_tx_curr = NULL;
+                p_info_ch->p_aio_rx_curr = NULL;
+
+                ercd = SSIF_EnableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_OPEN;
+                }
+            }
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    else
+    {
+        p_channelHandle = (void*)p_info_ch;
+        ret = (int_t)p_channelHandle;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Close
+* @brief         Close an SSIF channel.
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, NULL);
+
+                ercd = SSIF_DisableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+                }
+            }
+
+            /* Relese semaphore */
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Ioctl
+* @brief         IOCTL function of the SSIF deiver
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     request    :IOCTL request code
+* @param[in,out] p_buf      :Meaning depends upon request.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT_RBSP;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SSIF_CONFIG_CHANNEL:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ssif_channel_cfg_t* const ch_info = (ssif_channel_cfg_t*)p_buf;
+                            ercd = SSIF_IOCTL_ConfigChannel(p_info_ch, ch_info);
+                        }
+                        break;
+                    }
+
+                    case SSIF_GET_STATUS:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT_RBSP;
+                        }
+                        else
+                        {
+                            ercd = SSIF_IOCTL_GetStatus(p_info_ch, (uint32_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    default:
+                    {
+                        ercd = EINVAL_RBSP;
+                        break;
+                    }
+                } /* switch */
+            }
+        }
+
+        os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+        if (osOK != os_ercd)
+        {
+            ercd = EFAULT_RBSP;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_WriteAsync
+* @brief         Enqueue asynchronous write request
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of write request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        if (((uint32_t)O_RDONLY_RBSP) == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP))
+        {
+            ercd = EACCES_RBSP;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL_RBSP;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_W;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_ReadAsync
+* @brief         Enqueue asynchronous read request
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of read request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+#if defined(TARGET_RZA1H) /* mbed */
+        if ((O_WRONLY_RBSP == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP))
+            || (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                == p_info_ch->romdec_direct.mode))
+#else /* mbed */
+        if ((O_WRONLY_RBSP == ((uint32_t)p_info_ch->openflag & O_ACCMODE_RBSP)))
+#endif /* mbed */
+        {
+            ercd = EACCES_RBSP;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL_RBSP;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_R;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Cancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block to cancel or NULL to cancel all.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT_RBSP;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreAcquire(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT_RBSP;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT_RBSP;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, p_aio);
+            }
+
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT_RBSP;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_StrnLen
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*
+* @param[in]     p_str      :pointer of string.
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        < maxlen   :number of characters in the string
+* @retval        maxlen     :string is longer than maxlen
+******************************************************************************/
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen)
+{
+    size_t len;
+
+    if (NULL == p_str)
+    {
+        len = 0;
+    }
+    else
+    {
+        for (len = 0; len < maxlen; len++)
+        {
+            if ((int_t)p_str[len] == '\0')
+            {
+                break;
+            }
+        }
+    }
+
+    return len;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Strncmp
+* @brief         Compare two strings
+*
+*                Description:<br>
+*
+* @param[in]     p_str1     :pointer of string1
+* @param[in]     p_str2     :pointer of string2
+* @param[in]     maxlen     :maximum length of comparison
+* @retval        zero       :strings are same.
+* @retval        non zero   :strings are different.
+******************************************************************************/
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen)
+{
+    int32_t result = 0;
+    uint32_t index;
+
+    if ((NULL == p_str1) || (NULL == p_str2))
+    {
+        result = -1;
+    }
+    else
+    {
+        for (index = 0; index < maxlen; index++)
+        {
+            /* compare charctor */
+            result = ((int_t)p_str1[index]) - ((int_t)p_str2[index]);
+            if ((result != 0)
+                || ((int_t)p_str1[index] == '\0')
+                || ((int_t)p_str2[index] == '\0'))
+            {
+                /* "charactor mismatch" or "end of string" */
+                break;
+            }
+        }
+    }
+
+    return result;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, do nothing.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif_int.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,307 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_int.c
+* $Rev: $
+* $Date::                           $
+* Description : SSIF driver interrupt functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "ssif_int.h"
+#include "cmsis.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_INT_PER_CH     (4u)
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+
+static void SSIF_ERI0_Handler(void);
+static void SSIF_ERI1_Handler(void);
+static void SSIF_ERI2_Handler(void);
+static void SSIF_ERI3_Handler(void);
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch);
+
+/******************************************************************************
+* Function Name: SSIF_InterruptInit
+* @brief         Initialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Enable interrupt and register interrupt handler.
+* @param[in]     ssif_ch    :SSIF channel
+* @param[in]     int_level  :GIC priority level of interrupt
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            ret = InterruptHandlerRegister(INT_SSIF_INT_REQ_0_IRQn, &SSIF_ERI0_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(INT_SSIF_INT_REQ_0_IRQn, int_level);
+            GIC_SetConfiguration(INT_SSIF_DMA_RX_0_IRQn, 3);
+            GIC_SetPriority(INT_SSIF_DMA_RX_0_IRQn, int_level);
+            GIC_SetConfiguration(INT_SSIF_DMA_TX_0_IRQn, 3);
+            GIC_SetPriority(INT_SSIF_DMA_TX_0_IRQn, int_level);
+            GIC_EnableIRQ(INT_SSIF_INT_REQ_0_IRQn);
+            GIC_EnableIRQ(INT_SSIF_DMA_RX_0_IRQn);
+            GIC_EnableIRQ(INT_SSIF_DMA_TX_0_IRQn);
+            break;
+        case SSIF_CHNUM_1:
+            ret = InterruptHandlerRegister(INT_SSIF_INT_REQ_1_IRQn, &SSIF_ERI1_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(INT_SSIF_INT_REQ_1_IRQn, int_level);
+            GIC_SetConfiguration(INT_SSIF_DMA_RX_1_IRQn, 3);
+            GIC_SetPriority(INT_SSIF_DMA_RX_1_IRQn, int_level);
+            GIC_SetConfiguration(INT_SSIF_DMA_TX_1_IRQn, 3);
+            GIC_SetPriority(INT_SSIF_DMA_TX_1_IRQn, int_level);
+            GIC_EnableIRQ(INT_SSIF_INT_REQ_1_IRQn);
+            GIC_EnableIRQ(INT_SSIF_DMA_RX_1_IRQn);
+            GIC_EnableIRQ(INT_SSIF_DMA_TX_1_IRQn);
+            break;
+        case SSIF_CHNUM_2:
+            ret = InterruptHandlerRegister(INT_SSIF_INT_REQ_2_IRQn, &SSIF_ERI2_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(INT_SSIF_INT_REQ_2_IRQn, int_level);
+            GIC_SetConfiguration(INT_SSIF_DMA_RT_2_IRQn, 3);
+            GIC_SetPriority(INT_SSIF_DMA_RT_2_IRQn, int_level);
+            GIC_EnableIRQ(INT_SSIF_INT_REQ_2_IRQn);
+            GIC_EnableIRQ(INT_SSIF_DMA_RT_2_IRQn);
+            break;
+        case SSIF_CHNUM_3:
+            ret = InterruptHandlerRegister(INT_SSIF_INT_REQ_3_IRQn, &SSIF_ERI3_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(INT_SSIF_INT_REQ_3_IRQn, int_level);
+            GIC_SetConfiguration(INT_SSIF_DMA_RX_3_IRQn, 3);
+            GIC_SetPriority(INT_SSIF_DMA_RX_3_IRQn, int_level);
+            GIC_SetConfiguration(INT_SSIF_DMA_TX_3_IRQn, 3);
+            GIC_SetPriority(INT_SSIF_DMA_TX_3_IRQn, int_level);
+            GIC_EnableIRQ(INT_SSIF_INT_REQ_3_IRQn);
+            GIC_EnableIRQ(INT_SSIF_DMA_RX_3_IRQn);
+            GIC_EnableIRQ(INT_SSIF_DMA_TX_3_IRQn);
+            break;
+        /* ->IPA R3.5.2 : There is nothing to do when unusual conditons. */
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_InterruptShutdown
+* @brief         Uninitialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Disable interrupt and unregister interrupt handler
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptShutdown(const uint32_t ssif_ch)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            GIC_DisableIRQ(INT_SSIF_INT_REQ_0_IRQn);
+            GIC_DisableIRQ(INT_SSIF_DMA_RX_0_IRQn);
+            GIC_DisableIRQ(INT_SSIF_DMA_TX_0_IRQn);
+            ret = InterruptHandlerUnregister(INT_SSIF_INT_REQ_0_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_1:
+            GIC_DisableIRQ(INT_SSIF_INT_REQ_1_IRQn);
+            GIC_DisableIRQ(INT_SSIF_DMA_RX_1_IRQn);
+            GIC_DisableIRQ(INT_SSIF_DMA_TX_1_IRQn);
+            ret = InterruptHandlerUnregister(INT_SSIF_INT_REQ_1_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_2:
+            GIC_DisableIRQ(INT_SSIF_INT_REQ_2_IRQn);
+            GIC_DisableIRQ(INT_SSIF_DMA_RT_2_IRQn);
+            ret = InterruptHandlerUnregister(INT_SSIF_INT_REQ_2_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_3:
+            GIC_DisableIRQ(INT_SSIF_INT_REQ_3_IRQn);
+            GIC_DisableIRQ(INT_SSIF_DMA_RX_3_IRQn);
+            GIC_DisableIRQ(INT_SSIF_DMA_TX_3_IRQn);
+            ret = InterruptHandlerUnregister(INT_SSIF_INT_REQ_3_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_EnableErrorInterrupt
+* @brief         Enable the SSIF channel error interrupt
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* clear error status */
+    g_ssireg[ssif_ch]->SSISR.LONG = 0u;
+
+    /* enable error interrupt */
+    g_ssireg[ssif_ch]->SSICR.LONG |= SSIF_CR_INT_ERR_MASK;
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableErrorInterrupt
+* @brief         Disable the SSIF channel error interrupt
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* disable error interrupt */
+    g_ssireg[ssif_ch]->SSICR.LONG &= ~(SSIF_CR_INT_ERR_MASK);
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ERI<n>_Handler
+* @brief         SSIF error interrupt handler per channel
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI0_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_0);
+    return;
+}
+
+static void SSIF_ERI1_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_1);
+    return;
+}
+
+static void SSIF_ERI2_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_2);
+    return;
+}
+
+static void SSIF_ERI3_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_3);
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ERI_Handler
+* @brief         SSIF error interrupt handler common function
+*
+*                Description:<br>
+*
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch)
+{
+#if(1) /* mbed */
+    ssif_info_drv_t* const p_info_drv = SSIF_GetDrvInstanc();
+    ssif_info_ch_t* const p_info_ch = &p_info_drv->info_ch[ssif_ch];
+#else
+    ssif_info_ch_t* const p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+#endif /* end mbed */
+
+    if (0u != (g_ssireg[ssif_ch]->SSISR.LONG & SSIF_SR_INT_ERR_MASK))
+    {
+        /* Restart or Callback */
+        SSIF_ErrorRecovery(p_info_ch);
+    }
+
+    return;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif_int.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif_int.h
+* $Rev: $
+* $Date::                           $
+* Description  : SSIF driver interrupt functions header
+******************************************************************************/
+
+#ifndef SSIF_INT_H
+#define SSIF_INT_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level);
+void SSIF_InterruptShutdown(const uint32_t ssif_ch);
+
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch);
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch);
+
+#endif /* SSIF_INT_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/TARGET_RZ_A2XX/ssif/ssif_ver.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014-2016 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         ssif_ver.c
+* $Rev: $
+* $Date::                           $
+* @brief        SSIF Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "ssif_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V0.01 -> MAJOR=0, MINOR=01 */
+#define SSIF_DRV_VER_MAJOR  (0u)
+#define SSIF_DRV_VER_MINOR  (1u)
+
+#define SSIF_DRV_VER_MASK   (0xFFu)
+#define SSIF_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SSIF_GetVersion
+* @brief         Get SSIF driver version.
+*
+*                Description:<br>
+*
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SSIF_GetVersion(void)
+{
+    const uint16_t version =
+        ((SSIF_DRV_VER_MAJOR & SSIF_DRV_VER_MASK) << SSIF_DRV_VER_SHIFT)
+        | (SSIF_DRV_VER_MINOR & SSIF_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SSIF_GetVersion
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/drv_src/ioif/aioif.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,459 @@
+/******************************************************************************
+ *
+ * $Rev: $
+ * $Date::                           $
+ *
+ * Description : ITRON support functions for IOIF Asynchronous I/O header file
+ *
+ * (C) Copyright RENESAS ELECTRONICS EUROPE Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+/*************************************************************************
+ System Includes
+*************************************************************************/
+
+#include <r_errno.h>
+#include <cmsis_os.h>
+#include <aioif.h>
+#if(1) /* mbed */
+#include "cmsis.h"
+#include "mbed_critical.h"
+#else  /* not mbed */
+#include <ipcb.h>
+#include <ioif_aio_helper.h>
+#endif /* end mbed */
+#include <misratypes.h>
+#include "bsp_drv_cmn.h"
+#if defined (__ICCARM__)
+#include <intrinsics.h>
+#endif
+
+/*************************************************************************
+ OS Resources
+*************************************************************************/
+
+
+/*************************************************************************
+ Functions
+*************************************************************************/
+static void ahf_lock(AHF_S * const ahf);
+static void ahf_unlock(AHF_S * const ahf);
+
+static void ahf_lock(AHF_S * const ahf)
+{
+    if(ahf->flags & AHF_LOCKSEM)
+    {
+        osMutexAcquire(ahf->semid, 0);
+    }
+    else if (ahf->flags & AHF_LOCKINT)
+    {
+        core_util_critical_section_enter();
+    }
+    else
+    {
+        ;   /* MISRA compliance. */
+    }
+}
+
+static void ahf_unlock(AHF_S * const ahf)
+{
+    if(ahf->flags & AHF_LOCKSEM)
+    {
+        osMutexRelease(ahf->semid);
+    }
+    else if (ahf->flags & AHF_LOCKINT)
+    {
+        core_util_critical_section_exit();
+    }
+    else
+    {
+        ;   /* MISRA compliance. */
+    }
+}
+
+/***********************************************************************************
+Function Name:         ahf_create
+
+Description:    Creates an empty aio control queue pointer.
+                Creates a mutex if AHF_CREATESEM bit flag is set.
+
+Parameters:     ahf  - aio queue structure pointer.
+                f    - flag indicating that at semaphore is to be created.
+
+Return value:   0 on success.   negative error code on error.
+***********************************************************************************/
+int32_t ahf_create (AHF_S * const ahf, const uint32_t f)
+{
+    osMutexAttr_t* p_mutex_def;
+    uint32_t*     p_mutex_data;
+
+    if (ahf == NULL)
+    {
+        return EFAULT_RBSP;
+    }
+
+    ahf->head = NULL;
+    ahf->tail = NULL;
+    ahf->flags = f;
+
+    /* create the mutex if required */
+    if (f & AHF_CREATESEM)
+    {
+#if defined (__GNUC__)
+        /* disable all irq */
+        core_util_critical_section_enter();
+#endif/*__GNUC__*/
+        p_mutex_def = calloc(1, sizeof(osMutexAttr_t));
+#if defined (__GNUC__)
+        /* enable all irq */
+        core_util_critical_section_exit();
+#endif/*__GNUC__*/
+        if ( NULL == p_mutex_def )
+        {
+            return ENOMEM_RBSP;
+        }
+#if defined (__GNUC__)
+        /* disable all irq */
+        core_util_critical_section_enter();
+#endif/*__GNUC__*/
+        p_mutex_data = calloc(7, sizeof(uint32_t));
+#if defined (__GNUC__)
+        /* enable all irq */
+        core_util_critical_section_exit();
+#endif/*__GNUC__*/
+        if ( NULL == p_mutex_data )
+        {
+#if defined (__GNUC__)
+            /* disable all irq */
+            core_util_critical_section_enter();
+#endif/*__GNUC__*/
+            free(p_mutex_def);
+#if defined (__GNUC__)
+            /* enable all irq */
+            core_util_critical_section_exit();
+#endif/*__GNUC__*/
+            return ENOMEM_RBSP;
+        }
+        p_mutex_def->cb_mem = p_mutex_data;
+        ahf->p_cmtx = p_mutex_def;
+        ahf->semid = osMutexNew (p_mutex_def);
+        if ( NULL == ahf->semid )
+        {
+#if defined (__GNUC__)
+            /* disable all irq */
+            core_util_critical_section_enter();
+#endif/*__GNUC__*/
+            free(p_mutex_data);
+            free(p_mutex_def);
+#if defined (__GNUC__)
+            /* enable all irq */
+            core_util_critical_section_exit();
+#endif/*__GNUC__*/
+            return ENOMEM_RBSP;
+        }
+    }
+
+    return 0;
+}
+
+/***********************************************************************************
+Function Name:         ahf_destroy
+
+Description:    Delete aio control block mutex (if it exists).
+                Note: This function does not delete the aio control block queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_destroy (AHF_S const * const ahf)
+{
+    if (ahf == NULL)
+    {
+        return;
+    }
+
+    if (ahf->flags & AHF_CREATESEM)
+    {
+        osMutexDelete (ahf->semid);
+#if defined (__GNUC__)
+        /* disable all irq */
+        core_util_critical_section_enter();
+#endif/*__GNUC__*/
+        free(ahf->p_cmtx->cb_mem);
+        free(ahf->p_cmtx);
+#if defined (__GNUC__)
+        /* enable all irq */
+        core_util_critical_section_exit();
+#endif/*__GNUC__*/
+    }
+}
+
+/***********************************************************************************
+Function Name:         ahf_addtail
+
+Description:    Add an aio control block to the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_addtail (AHF_S * const ahf, struct aiocb * const aio)
+{
+    if (ahf == NULL)
+    {
+        return;
+    }
+
+    ahf_lock (ahf);
+    if (ahf->tail != NULL)
+    {
+        ahf->tail->pNext = aio;
+    }
+    aio->pPrev = ahf->tail;
+    aio->pNext = NULL;
+    ahf->tail = aio;
+    if (ahf->head == NULL)
+    {
+        /* list was empty */
+        ahf->head = aio;
+    }
+
+    ahf_unlock (ahf);
+}
+
+/***********************************************************************************
+Function Name:         ahf_removehead
+
+Description:    Remove an aio control block from the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   aio control block, or NULL if queue is empty.
+
+***********************************************************************************/
+struct aiocb *ahf_removehead (AHF_S * const ahf)
+{
+    struct aiocb *aio;
+
+    if (ahf == NULL)
+    {
+        return(NULL);
+    }
+
+    ahf_lock (ahf);
+
+    aio = ahf->head;
+    if (aio != NULL)
+    {
+        ahf->head = aio->pNext;
+        if (aio->pNext != NULL)
+        {
+            aio->pNext->pPrev = NULL;
+        }
+        if (ahf->tail == aio)
+        {
+            /* the list is now empty */
+            ahf->tail = NULL;
+        }
+    }
+
+    ahf_unlock (ahf);
+    return aio;
+}
+
+/***********************************************************************************
+Function Name:         ahf_peekhead
+
+Description:    Get an aio control block from the queue, but do not remove from the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   aio control block, or NULL if queue is empty.
+
+***********************************************************************************/
+struct aiocb *ahf_peekhead (AHF_S * const ahf)
+{
+    struct aiocb *aio;
+
+    ahf_lock (ahf);
+
+    aio = ahf->head;
+
+    ahf_unlock (ahf);
+    return aio;
+}
+
+/***********************************************************************************
+Function Name:         ahf_cancelall
+
+Description:    Empty an aio control block queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_cancelall (AHF_S * const ahf)
+{
+    struct aiocb *cur, *next;
+
+    ahf_lock (ahf);
+
+    /* cancel all pending requests */
+    cur = ahf->head;
+    while (cur != NULL)
+    {
+        next = cur->pNext;
+        cur->aio_return = ECANCELED_RBSP;
+        ahf_complete (ahf, cur);
+        cur = next;
+    }
+    /* mark the list as empty */
+    ahf->head = NULL;
+    ahf->tail = NULL;
+
+    ahf_unlock (ahf);
+}
+
+/***********************************************************************************
+Function Name:         ahf_complete
+
+Description:    Flag that the operation is complete.
+                If required by the sigev_notify variable contents, the calling task is
+                notified.
+                If a notify was setup, it is signalled.
+
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   0 on success.   negative error code on error.
+
+***********************************************************************************/
+void ahf_complete (AHF_S *ahf, struct aiocb * const aio)
+{
+#if(1) /* mbed */
+#else  /* not mbed */
+    int rv;
+#endif /* end mbed */
+    UNUSED_ARG(ahf);
+
+    if (NULL == aio)
+    {
+        return;
+    }
+
+    /* Flag that the operation is complete */
+    /*  This function must be here
+        because another task may release AIOCB block
+        after the task changed by an iTRON function in the switch statement */
+    aio->aio_complete = 1;
+    switch (aio->aio_sigevent.sigev_notify)
+    {
+    case SIGEV_EVENT:
+         osSignalSet ((osThreadId_t)aio->aio_sigevent.sigev_value.sival_int,
+             (int32_t)aio->aio_sigevent.sigev_signo);
+        break;
+
+    case SIGEV_THREAD:
+        if (aio->aio_sigevent.sigev_notify_function)
+        {
+            (aio->aio_sigevent.sigev_notify_function)
+                (aio->aio_sigevent.sigev_value);
+        }
+        break;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+    case SIGEV_CALLBACK:
+        rv = ipcb_callback ((ipcb_id_t*)aio->aio_sigevent.sigev_signo, &aio->aio_sigevent);
+        break;
+#endif /* end mbed */
+
+    default:
+        /* No notify function */
+        break;
+
+    }
+
+    /* Wakeup any suspended tasks */
+#if(1) /* mbed */
+#else  /* not mbed */
+    aio_complete_suspended(aio);
+#endif /* end mbed */
+}
+
+/***********************************************************************************
+Function Name:         ahf_cancel
+
+Description:    Remove an aio control block from the queue.
+                Signal completion to the calling task and wake it up.
+                If aio is NULL, cancel all.
+
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   0 on success.   negative error code on error.
+
+***********************************************************************************/
+int32_t ahf_cancel (AHF_S * const ahf, struct aiocb * const aio)
+{
+    struct aiocb *cur;
+    int32_t rv = EINVAL_RBSP;
+
+    if (ahf == NULL)
+    {
+        return EFAULT_RBSP;
+    }
+
+    /* If aio is NULL, must cancel all. */
+    if(NULL == aio)
+    {
+        ahf_cancelall(ahf);
+        rv = 0;
+    }
+
+    else
+    {
+        ahf_lock (ahf);
+
+        cur = ahf->head;
+        while ((cur != NULL) && (cur != aio))
+        {
+            cur = cur->pNext;
+        }
+
+        if (cur == aio)
+        {
+            if (aio->pPrev != NULL)
+            {
+                aio->pPrev->pNext = aio->pNext;
+            }
+
+            if (aio->pNext != NULL)
+            {
+                aio->pNext->pPrev = aio->pPrev;
+            }
+
+            if (ahf->head == cur)
+            {
+                ahf->head = cur->pNext;
+            }
+
+            if (ahf->tail == cur)
+            {
+                ahf->tail = cur->pPrev;
+            }
+
+            cur->aio_return = ECANCELED_RBSP;
+            ahf_complete (ahf, aio);
+            rv = 0;
+        }
+
+        ahf_unlock (ahf);
+    }
+    return rv;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/RenesasBSP/version.txt	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1 @@
+V2.03
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_Aio.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Aio.h
+* @brief         R_BSP_Aio API
+******************************************************************************/
+
+#ifndef R_BSP_AIO_H
+#define R_BSP_AIO_H
+
+#include <stdint.h>
+#include "rtos.h"
+
+/** Callback function type 
+  *
+  * @param p_data Location of the data.
+  * @param result Number of bytes transmit on success. negative number on error.
+  * @param p_app_data User definition data.
+  */
+typedef void (*rbsp_notify_func_t)(void * p_data, int32_t result, void * p_app_data);
+
+/** Asynchronous control block structure */
+typedef struct {
+    rbsp_notify_func_t  p_notify_func;  /**< Callback function type. */
+    void *              p_app_data;     /**< User definition data. */
+} rbsp_data_conf_t;
+
+/**
+ * A class to communicate a R_BSP_Aio
+ */
+class R_BSP_Aio {
+
+public:
+
+    /** Write count bytes to the file associated
+     *
+     * @param p_data Location of the data.
+     * @param data_size Number of bytes to write.
+     * @param p_data_conf Asynchronous control block structure.
+     * @return Number of bytes written on success. negative number on error.
+     */
+    int32_t write(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL);
+
+    /** Read count bytes to the file associated
+     *
+     * @param p_data Location of the data.
+     * @param data_size Number of bytes to read.
+     * @param p_data_conf Asynchronous control block structure.
+     * @return Number of bytes read on success. negative number on error.
+     */
+    int32_t read(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL);
+
+protected:
+
+    /** Constructor
+     *
+     */
+    R_BSP_Aio();
+
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_Aio();
+
+    /** Write init
+     *
+     * @param handle channel handle.
+     * @param p_func_a Pointer of write function.
+     * @param max_buff_num The upper limit of write buffer.
+     */
+    void write_init(void * handle, void * p_func_a, int32_t max_buff_num = 16) {
+        init(&write_ctl, handle, p_func_a, max_buff_num);
+    };
+
+    /** Read init
+     *
+     * @param handle channel handle.
+     * @param p_func_a Pointer of read function.
+     * @param max_buff_num The upper limit of read buffer.
+     */
+    void read_init(void * handle, void * p_func_a, int32_t max_buff_num = 16) {
+        init(&read_ctl, handle, p_func_a, max_buff_num);
+    };
+private:
+    typedef struct {
+        rbsp_notify_func_t  p_cb_func;
+        void *              p_cb_data;
+        Semaphore *         p_sem;
+        void *              p_aio;
+    } rbsp_sival_t;
+
+    typedef struct {
+        void *              ch_handle;
+        void *              p_async_func;
+        void *              p_aio_top;
+        int32_t             index;
+        rbsp_sival_t *      p_sival_top;
+        Semaphore *         p_sem_ctl;
+        int32_t             MaxNum;
+    } rbsp_serial_ctl_t;
+
+    typedef struct {
+        Semaphore *         p_sem;
+        int32_t             result;
+    } rbsp_sync_t;
+
+    void init(rbsp_serial_ctl_t * p_ctl, void * handle, void * p_func_a, int32_t max_buff_num);
+    static int32_t sync_trans(rbsp_serial_ctl_t * p_ctl, void * const p_data, uint32_t data_size);
+    static void callback_sync_trans(void * p_data, int32_t result, void * p_app_data);
+    static int32_t aio_trans(rbsp_serial_ctl_t * const p_ctl, void * const p_data, uint32_t data_size,
+                             const rbsp_data_conf_t * const p_data_conf);
+    static void callback_aio_trans(union sigval signo);
+
+    rbsp_serial_ctl_t write_ctl;
+    rbsp_serial_ctl_t read_ctl;
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_Scux.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,152 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Scux.h
+* @brief         SCUX API
+******************************************************************************/
+
+#ifndef R_BSP_SCUX_H
+#define R_BSP_SCUX_H
+
+#if defined(TARGET_RZ_A1XX)
+#define R_BSP_SCUX_ENABLE    1
+
+#include "R_BSP_SerialFamily.h"
+#include "R_BSP_ScuxDef.h"
+
+#define SAMPLING_RATE_8000HZ  (8000U)  /* Selects a sampling rate of 8 kHz. */
+#define SAMPLING_RATE_11025HZ (11025U) /* Selects a sampling rate of 11.025 kHz. */
+#define SAMPLING_RATE_12000HZ (12000U) /* Selects a sampling rate of 12 kHz. */
+#define SAMPLING_RATE_16000HZ (16000U) /* Selects a sampling rate of 16 kHz. */
+#define SAMPLING_RATE_22050HZ (22050U) /* Selects a sampling rate of 22.05 kHz. */
+#define SAMPLING_RATE_24000HZ (24000U) /* Selects a sampling rate of 24 kHz. */
+#define SAMPLING_RATE_32000HZ (32000U) /* Selects a sampling rate of 32 kHz. */
+#define SAMPLING_RATE_44100HZ (44100U) /* Selects a sampling rate of 44.1 kHz. */
+#define SAMPLING_RATE_48000HZ (48000U) /* Selects a sampling rate of 48 kHz. */
+#define SAMPLING_RATE_64000HZ (64000U) /* Selects a sampling rate of 64 kHz. */
+#define SAMPLING_RATE_88200HZ (88200U) /* Selects a sampling rate of 88.2 kHz. */
+#define SAMPLING_RATE_96000HZ (96000U) /* Selects a sampling rate of 96 kHz. */
+#define SELECT_IN_DATA_CH_0   (0U)     /* Specifies audio channel 0ch. */
+#define SELECT_IN_DATA_CH_1   (1U)     /* Specifies audio channel 1ch. */
+
+/** SRC parameter information */
+typedef struct
+{
+    bool                  src_enable;                       /**< SRC function enable setting */
+    scux_data_word_len_t  word_len;                         /**< Word length of the audio data to be used
+                                                                 by the SRC. */
+    bool                  mode_sync;                        /**< Synchronization mode */
+    uint32_t              input_rate;                       /**< Input sampling rate */
+    uint32_t              output_rate;                      /**< Output sampling rate */
+    uint32_t              select_in_data_ch[SCUX_USE_CH_2]; /**< For SRC's input data position swapping */
+} scux_src_usr_cfg_t;
+
+/** The SCUX module is made up of a sampling rate converter, a digital volume unit, and a mixer.
+ *  The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate
+ *  converter. 
+ *  The SCUX driver uses the DMA transfer mode to input and output audio data.
+ */
+class R_BSP_Scux : public R_BSP_SerialFamily {
+
+public:
+    /** Constructor: Initializes and opens the channel designated by the SCUX driver.
+     *
+     * @param channel SCUX channel number
+     * @param int_level Transfer interrupt priority level (0x00-0xF7; default = 0x80)
+     * @param max_write_num Maximum number of writes (1 to 128; default = 16)
+     * @param max_read_num Maximum number of reads (1 to 128; default = 16)
+     */
+    R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level = 0x80, int32_t max_write_num = 16, int32_t max_read_num = 16);
+
+    /** Destructor: Closes the channel designated by the SCUX driver and exits.
+     *
+     */
+    virtual ~R_BSP_Scux(void);
+
+    /** Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
+     * Allocates a DMA channel for read requests.
+     * The function also initializes the SCUX HW error state.
+     *
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool TransStart(void);
+
+    /** Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer,
+     *  then stops the HW operation.
+     *   If a transfer request is being processed, the function stops accepting write/read requests,
+     *   then performs preprocessing to stop the HW operation after flushing out all data in the SCUX
+     *   that is requested for transfer. 
+     *   If no transfer request is being processed, the function stops accepting write/read requests 
+     *   before stopping the HW operation.
+     * The function releases the DMA channel for read requests when the HW operation is stopped.
+     * It also calls the user-own callback function at the end of the transfer.
+     *
+     * @param callback Pointer to the callback function
+     *                 The SCUX driver places an error code indicating the execution result of FlushStop 
+     *                 in the argument of the callback function before calling the callback function. 
+     *                 The error code is set to 0 if FlushStop is successful. A negative number is set 
+     *                 if FlushStop fails.
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool FlushStop(void (* const callback)(int32_t));
+
+    /** Discards all data in the SCUX that is requested for transfer before stopping the hardware operation
+     *  and stops accepting write/read requests. 
+     *  The function releases the DMA channel for read requests when the HW operation is stopped.
+     *
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool ClearStop(void);
+
+    /** Sets up SRC parameters.
+     *
+     * @param p_src_param SRC parameter information
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param);
+
+    /** Obtains the state information of the write request.
+     *
+     * @param p_write_stat Status of the write request
+     *        SCUX_STAT_STOP (0)  Acceptance of requests is stopped.
+     *        SCUX_STAT_IDLE (1)  Processing of all requests is completed and waiting for a request.
+     *        SCUX_STAT_TRANS(2)  Transfer in progress
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool GetWriteStat(uint32_t * const p_write_stat);
+
+    /** Obtains the state information of the read request.
+     *
+     * @param p_read_stat ead request state
+     *        SCUX_STAT_STOP (0)  Acceptance of requests is stopped
+     *        SCUX_STAT_IDLE (1)  Processing of all requests is completed and waiting for a request.
+     *        SCUX_STAT_TRANS(2)  Transfer in progress
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool GetReadStat(uint32_t * const p_read_stat);
+
+private:
+    int32_t scux_ch;
+};
+#endif /* TARGET_RZ_A1XX */
+#endif /* R_BSP_SCUX_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_ScuxDef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,87 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_ScuxDef.h
+* @brief         SCUX defines
+******************************************************************************/
+
+#ifndef R_BSP_SCUXDEF_H
+#define R_BSP_SCUXDEF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/** SCUX channel number */
+typedef enum
+{
+    SCUX_CH_0 = 0,   /**< Specifies SCUX0. */
+    SCUX_CH_1 = 1,   /**< Specifies SCUX1. */
+    SCUX_CH_2 = 2,   /**< Specifies SCUX2. */
+    SCUX_CH_3 = 3,   /**< Specifies SCUX3. */
+    SCUX_CH_NUM = 4  /**< Number of SCUX channels. */
+} scux_ch_num_t;
+
+/** used audio channel number setting */
+typedef enum
+{
+    SCUX_USE_CH_1 = 1,   /**< used audio channel number is 1 */
+    SCUX_USE_CH_2 = 2,   /**< used audio channel number is 2 */
+    SCUX_USE_CH_4 = 4,   /**< used audio channel number is 4 */
+    SCUX_USE_CH_6 = 6,   /**< used audio channel number is 6 */
+    SCUX_USE_CH_8 = 8    /**< used audio channel number is 8 */
+} scux_use_channel_t;
+
+/** SCUX data word length */
+typedef enum
+{
+    SCUX_DATA_LEN_MIN      =(-1), /**< For data word length identification [unsettable] */
+    SCUX_DATA_LEN_24       = 0,   /**< Runs with a data word length of 24 bits. */
+    SCUX_DATA_LEN_16       = 1,   /**< Runs with a data word length of 16 bits. */
+    SCUX_DATA_LEN_16_TO_24 = 2,   /**< Outputs 16-bit data in 24-bit mode. */
+    SCUX_DATA_LEN_MAX      = 3    /**< For data word length identification [unsettable] */
+} scux_data_word_len_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/** Status of the request */
+#define SCUX_STAT_STOP    0  /**< Acceptance of requests is stopped */
+#define SCUX_STAT_IDLE    1  /**< Processing of all requests is completed and waiting for a request. */
+#define SCUX_STAT_TRANS   2  /**< Transfer in progress */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_SCUXDEF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_SerialFamily.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_SerialFamily.h
+* @brief         R_BSP_SerialFamily API
+******************************************************************************/
+
+#ifndef R_BSP_IOIF_H
+#define R_BSP_IOIF_H
+
+#include <stdint.h>
+#include <stdarg.h>
+#include "R_BSP_Aio.h"
+#include "R_BSP_mbed_fns.h"
+#include "rtos.h"
+
+/** A class to communicate a R_BSP_SerialFamily
+ *
+ */
+class R_BSP_SerialFamily : public R_BSP_Aio {
+
+public:
+    /** Manipulates the underlying device parameters of special files
+     *
+     * @param request has encoded in it whether the argument is an "in" parameter or "out" parameter,
+     * and the size of the argument argp in bytes.
+     * @return true = success, false = failure
+     */
+     bool ioctl(int request, ...);
+
+protected:
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_SerialFamily();
+
+    /** Channel init
+     *
+     * @param function_list pointer of driver function callback table
+     * @param channel       channel number
+     * @param config_data   pointer of several parameters for a channel
+     * @param max_write_num The upper limit of write buffer
+     * @param max_read_num  The upper limit of read buffer
+     */
+    bool init_channel(RBSP_MBED_FNS * function_list, int channel, void * const config_data, int32_t max_write_num = 16, int32_t max_read_num = 16);
+
+private:
+    void * instance;
+    void * ch_handle;
+    int32_t ch_no;
+    RBSP_MBED_FNS * functions;
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_Spdif.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,96 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Spdif.h
+* @brief         SPDIF API
+******************************************************************************/
+
+
+#ifndef R_BSP_SPDIF_H
+#define R_BSP_SPDIF_H
+
+#if defined(TARGET_RZ_A2XX)
+#define R_BSP_SPDIF_ENABLE    1
+
+#include <stdint.h>
+#include "R_BSP_SerialFamily.h"
+#include "R_BSP_SpdifDef.h"
+#include "rtos.h"
+#include "pinmap.h"
+
+
+/** A class to communicate a R_BSP_Spdif
+ *
+ */
+class R_BSP_Spdif : public R_BSP_SerialFamily {
+
+public:
+
+    /** Constructor
+     *
+     * @param audio_clk  audio clock
+     * @param tx  SPDIF serial data output
+     * @param rx  SPDIF serial data input
+     */
+    R_BSP_Spdif(PinName audio_clk, PinName tx, PinName rx);
+
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_Spdif();
+
+    /** Initialization
+     *
+     * @param p_ch_cfg SPDIF channel configuration parameter
+     * @param max_write_num The upper limit of write buffer (SPDIF)
+     * @param max_read_num  The upper limit of read buffer (SPDIF)
+     * @return true = success, false = failure
+     */
+    void init(const spdif_channel_cfg_t* const p_ch_cfg, int32_t max_write_num, int32_t max_read_num);
+
+    /** Get a value of SPDIF channel number
+     *
+     * @return SPDIF channel number
+     */
+    int32_t GetSsifChNo(void) {
+        return spdif_ch;
+    };
+
+    /** Save configuration to the SPDIF driver
+     *
+     * @param p_ch_cfg SPDIF channel configuration parameter
+     * @return true = success, false = failure
+     */
+    bool ConfigChannel(const spdif_channel_cfg_t* const p_ch_cfg);
+
+    bool SetChannelStatus(uint32_t status_Lch, uint32_t status_Rch);
+    bool GetChannelStatus(uint32_t * p_status_Lch, uint32_t * p_status_Rch);
+    bool SetTransAudioBit(int direction, char length);
+
+private:
+    int32_t spdif_ch;
+};
+#endif /* TARGET_RZ_A2XX */
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_SpdifDef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,119 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_SpdifDef.h
+* @brief         SPDIF defines
+******************************************************************************/
+
+#ifndef R_BSP_SPDIF_DEF_H
+#define R_BSP_SPDIF_DEF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#define SPDIF_NUM_CHANS       (1u)    /**< Number of SPDIF channels */
+
+/* ==== SPDIF Buffer ==== */
+#define SPDIF_NUMOF_FRM   (192)
+#define SPDIF_NUMOF_CH    (2)
+#define SPDIF_AUDIO_BUFFSIZE (SPDIF_NUMOF_FRM * SPDIF_NUMOF_CH)
+#define SPDIF_USER_BUFFSIZE  ((SPDIF_NUMOF_FRM * SPDIF_NUMOF_CH) / 32)
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+/** CTRL:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SPDIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SPDIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} spdif_chcfg_cks_t; 
+
+/** CTRL:RASS,TASS(Audio bit length) */
+typedef enum
+{
+    SPDIF_CFG_AUDIO_BIT_16 = 0,   /**< Audio bit length 16 */
+    SPDIF_CFG_AUDIO_BIT_20 = 1,   /**< Audio bit length 20 */
+    SPDIF_CFG_AUDIO_BIT_24 = 2    /**< Audio bit length 24 */
+} spdif_chcfg_audio_bit_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+/** This structure contains the configuration settings */
+typedef struct
+{
+    bool                            enabled;             /**< The enable flag for the channel       */
+    uint8_t                         int_level;           /**< Interrupt priority for the channel    */
+    spdif_chcfg_cks_t               clk_select;          /**< CTRL-CKS : Audio clock select         */
+    spdif_chcfg_audio_bit_t         audio_bit_tx;        /**< CTRL-TASS : Audio bit length          */
+    spdif_chcfg_audio_bit_t         audio_bit_rx;        /**< CTRL-RASS : Audio bit length          */
+    bool                            tx_u_data_enabled;   /**< CTRL-RASS : Audio bit length          */
+} spdif_channel_cfg_t;
+
+typedef struct
+{
+    uint32_t                        Lch;                 /**< Channel Status bit Lch    */
+    uint32_t                        Rch;                 /**< Channel Status bit Rch    */
+} spdif_channel_status_t;
+
+typedef struct
+{
+    uint32_t a_buff[SPDIF_AUDIO_BUFFSIZE];               /**< Audio Buffer */
+    uint32_t u_buff[SPDIF_USER_BUFFSIZE];                /**< User Buffer */
+    uint32_t s_buff[SPDIF_NUMOF_CH];                     /**< Channel Status Buffer */
+} spdif_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SPDIF_CONFIG_CHANNEL        (0)
+#define SPDIF_SET_CHANNEL_STATUS    (1)
+#define SPDIF_GET_CHANNEL_STATUS    (2)
+#define SPDIF_SET_TRANS_AUDIO_BIT   (3)
+#define SPDIF_SET_RECV_AUDIO_BIT    (4)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_SPDIF_DEF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_Ssif.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Ssif.h
+* @brief         SSIF API
+******************************************************************************/
+
+#ifndef R_BSP_SSIF_H
+#define R_BSP_SSIF_H
+
+#include <stdint.h>
+#include "R_BSP_SerialFamily.h"
+#include "R_BSP_SsifDef.h"
+#include "rtos.h"
+#include "pinmap.h"
+
+/** A class to communicate a R_BSP_Ssif
+ *
+ */
+class R_BSP_Ssif : public R_BSP_SerialFamily {
+
+public:
+
+    /** Constructor
+     *
+     * @param sck SSIF serial bit clock
+     * @param ws  SSIF word selection
+     * @param tx  SSIF serial data output
+     * @param rx  SSIF serial data input
+     */
+    R_BSP_Ssif(PinName sck, PinName ws, PinName tx, PinName rx, PinName audio_clk = NC);
+
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_Ssif();
+
+
+    /** Initialization
+     *
+     * @param p_ch_cfg SSIF channel configuration parameter
+     * @param max_write_num The upper limit of write buffer (SSIF)
+     * @param max_read_num  The upper limit of read buffer (SSIF)
+     * @return true = success, false = failure
+     */
+    void init(const ssif_channel_cfg_t* const p_ch_cfg, int32_t max_write_num, int32_t max_read_num);
+
+    /** Get a value of SSIF channel number
+     *
+     * @return SSIF channel number
+     */
+    int32_t GetSsifChNo(void) {
+        return ssif_ch;
+    };
+
+    /** Save configuration to the SSIF driver
+     *
+     * @param p_ch_cfg SSIF channel configuration parameter
+     * @return true = success, false = failure
+     */
+    bool ConfigChannel(const ssif_channel_cfg_t* const p_ch_cfg);
+
+    /** Get a value of SSISR register
+     *
+     * @param p_status Pointer of status value
+     * @return true = success, false = failure
+     */
+    bool GetStatus(uint32_t* const p_status);
+
+private:
+    int32_t ssif_ch;
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/api/R_BSP_SsifDef.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,225 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_SsifDef.h
+* @brief         SSIF defines
+******************************************************************************/
+
+#ifndef R_BSP_SSIF_DEF_H
+#define R_BSP_SSIF_DEF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#if defined(TARGET_RZA1H)
+#define SSIF_NUM_CHANS       (6u)    /**< Number of SSIF channels */
+#else
+#define SSIF_NUM_CHANS       (4u)    /**< Number of SSIF channels */
+#endif
+
+#define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u)        /* Disable SSIRDR->STRMDIN0 route */
+#define SSIF_CFG_ENABLE_ROMDEC_DIRECT  (0xDEC0DEC1u) /* Enable  SSIRDR->STRMDIN0 route */
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+
+/** SSICR:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SSIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SSIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} ssif_chcfg_cks_t; 
+
+/** SSICR:CHNL(Audio channels per system word) */
+typedef enum
+{
+    SSIF_CFG_MULTI_CH_1 = 0,     /**< 1ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_2 = 1,     /**< 2ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_3 = 2,     /**< 3ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_4 = 3      /**< 4ch within systemword (on tdm=0) */
+} ssif_chcfg_multi_ch_t;
+
+/** SSICR:DWL(Data word length) */
+typedef enum
+{
+    SSIF_CFG_DATA_WORD_8  = 0,   /**< Data word length 8  */
+    SSIF_CFG_DATA_WORD_16 = 1,   /**< Data word length 16 */
+    SSIF_CFG_DATA_WORD_18 = 2,   /**< Data word length 18 */
+    SSIF_CFG_DATA_WORD_20 = 3,   /**< Data word length 20 */
+    SSIF_CFG_DATA_WORD_22 = 4,   /**< Data word length 22 */
+    SSIF_CFG_DATA_WORD_24 = 5,   /**< Data word length 24 */
+    SSIF_CFG_DATA_WORD_32 = 6    /**< Data word length 32 */
+} ssif_chcfg_data_word_t;
+
+/** SSICR:SWL(System word length) */
+typedef enum
+{
+    SSIF_CFG_SYSTEM_WORD_8   = 0,    /**< System word length 8   */
+    SSIF_CFG_SYSTEM_WORD_16  = 1,    /**< System word length 16  */
+    SSIF_CFG_SYSTEM_WORD_24  = 2,    /**< System word length 24  */
+    SSIF_CFG_SYSTEM_WORD_32  = 3,    /**< System word length 32  */
+    SSIF_CFG_SYSTEM_WORD_48  = 4,    /**< System word length 48  */
+    SSIF_CFG_SYSTEM_WORD_64  = 5,    /**< System word length 64  */
+    SSIF_CFG_SYSTEM_WORD_128 = 6,    /**< System word length 128 */
+    SSIF_CFG_SYSTEM_WORD_256 = 7     /**< System word length 256 */
+} ssif_chcfg_system_word_t;
+
+/** SSICR:SCKP(Clock polarity) */
+typedef enum
+{
+    SSIF_CFG_FALLING = 0,    /**< Falling edge */
+    SSIF_CFG_RISING  = 1     /**< Rising edge  */
+} ssif_chcfg_clock_pol_t;
+
+/** SSICR:SWSP(Word select polarity) */
+typedef enum
+{
+    SSIF_CFG_WS_LOW  = 0,    /**< Low for ther 1st channel(not TDM) */
+    SSIF_CFG_WS_HIGH = 1     /**< High for the 1st channel(not TDM) */
+} ssif_chcfg_ws_pol_t;
+
+/** SSICR:SPDP(Serial padding polarity) */
+typedef enum
+{
+    SSIF_CFG_PADDING_LOW  = 0,   /**< Padding bits are low  */
+    SSIF_CFG_PADDING_HIGH = 1    /**< Padding bits are high */
+} ssif_chcfg_padding_pol_t;
+
+/** SSICR:SDTA(Serial data alignment) */
+typedef enum
+{
+    SSIF_CFG_DATA_FIRST    = 0,  /**< Data first         */
+    SSIF_CFG_PADDING_FIRST = 1   /**< Padding bits first */
+} ssif_chcfg_serial_alignment_t;
+
+/** SSICR:PDTA(Parallel data alignment) */
+typedef enum
+{
+    SSIF_CFG_LEFT  = 0,  /**< Left aligned  */
+    SSIF_CFG_RIGHT = 1   /**< Right aligned */
+} ssif_chcfg_parallel_alignment_t;
+
+/** SSICR:DEL(Serial data delay) */
+typedef enum
+{
+    SSIF_CFG_DELAY    = 0,   /**< 1 clock delay */
+    SSIF_CFG_NO_DELAY = 1    /**< No delay      */
+} ssif_chcfg_ws_delay_t;
+
+/** SSICR:CKDV(Serial oversampling clock division ratio) */
+typedef enum
+{
+    SSIF_CFG_CKDV_BITS_1   = 0,
+    SSIF_CFG_CKDV_BITS_2   = 1,
+    SSIF_CFG_CKDV_BITS_4   = 2,
+    SSIF_CFG_CKDV_BITS_8   = 3,
+    SSIF_CFG_CKDV_BITS_16  = 4,
+    SSIF_CFG_CKDV_BITS_32  = 5,
+    SSIF_CFG_CKDV_BITS_64  = 6,
+    SSIF_CFG_CKDV_BITS_128 = 7,
+    SSIF_CFG_CKDV_BITS_6   = 8,
+    SSIF_CFG_CKDV_BITS_12  = 9,
+    SSIF_CFG_CKDV_BITS_24  = 10,
+    SSIF_CFG_CKDV_BITS_48  = 11,
+    SSIF_CFG_CKDV_BITS_96  = 12
+} ssif_chcfg_ckdv_t;
+
+
+/** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
+    SSIF_CFG_ENABLE_NOISE_CANCEL  = 1  /**< Use noise cancel function     */
+} ssif_chcfg_noise_cancel_t;
+
+
+/** SSITDMR:TDM(TDM mode) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_TDM = 0,   /**< not TDM mode */
+    SSIF_CFG_ENABLE_TDM  = 1    /**< set TDM mode */
+} ssif_chcfg_tdm_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+/** It's used for ROMDEC direct transfer mode and the call back function registration. */
+typedef struct
+{
+    uint32_t    mode;               /**< Enable/Disable SSIRDR->STRMDIN0 route (Invalid in GR_LYCHEE) */
+    void        (*p_cbfunc)(void);  /**< SSIF error callback function          (Invalid in GR_LYCHEE) */
+} ssif_chcfg_romdec_t;
+
+/** This structure contains the configuration settings */
+typedef struct
+{
+    bool                            enabled;             /**< The enable flag for the channel       */
+    uint8_t                         int_level;           /**< Interrupt priority for the channel    */
+    bool                            slave_mode;          /**< Mode of operation                     */
+    uint32_t                        sample_freq;         /**< Audio Sampling frequency(Hz)          */
+    ssif_chcfg_cks_t                clk_select;          /**< SSICR-CKS : Audio clock select        */
+    ssif_chcfg_multi_ch_t           multi_ch;            /**< SSICR-CHNL: Audio channels per system word */
+    ssif_chcfg_data_word_t          data_word;           /**< SSICR-DWL : Data word length          */
+    ssif_chcfg_system_word_t        system_word;         /**< SSICR-SWL : System word length        */
+    ssif_chcfg_clock_pol_t          bclk_pol;            /**< SSICR-SCKP: Bit Clock polarity        */
+    ssif_chcfg_ws_pol_t             ws_pol;              /**< SSICR-SWSP: Word Clock polarity       */
+    ssif_chcfg_padding_pol_t        padding_pol;         /**< SSICR-SPDP: Padding polarity          */
+    ssif_chcfg_serial_alignment_t   serial_alignment;    /**< SSICR-SDTA: Serial data alignment     */
+    ssif_chcfg_parallel_alignment_t parallel_alignment;  /**< SSICR-PDTA: Parallel data alignment   */
+    ssif_chcfg_ws_delay_t           ws_delay;            /**< SSICR-DEL : Serial clock delay        */
+    ssif_chcfg_noise_cancel_t       noise_cancel;        /**< GPIO-SNCR : Noise cancel              */
+    ssif_chcfg_tdm_t                tdm_mode;            /**< SSITDMR-TDM: TDM mode                 */
+    ssif_chcfg_romdec_t             romdec_direct;       /**< DMA : SSIRDR->STRMDIN0 route settings (Invalid in GR_LYCHEE) */
+} ssif_channel_cfg_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SSIF_CONFIG_CHANNEL        (7)
+#define SSIF_GET_STATUS           (13)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_SSIF_DEF_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/common/R_BSP_Aio.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,158 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "r_errno.h"
+#include "aioif.h"
+#include "R_BSP_Aio.h"
+
+typedef int32_t (*rbsp_read_write_a_func_t)(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+
+R_BSP_Aio::R_BSP_Aio() {
+}
+
+R_BSP_Aio::~R_BSP_Aio() {
+    if (write_ctl.MaxNum != 0) {
+        delete [] (rbsp_sival_t *)write_ctl.p_sival_top;
+        delete [] (AIOCB *)write_ctl.p_aio_top;
+        delete write_ctl.p_sem_ctl;
+    }
+    if (read_ctl.MaxNum != 0) {
+        delete [] (rbsp_sival_t *)read_ctl.p_sival_top;
+        delete [] (AIOCB *)read_ctl.p_aio_top;
+        delete read_ctl.p_sem_ctl;
+    }
+}
+
+void R_BSP_Aio::init(rbsp_serial_ctl_t * p_ctl, void * handle, void * p_func_a, int32_t max_buff_num) {
+    if (handle != NULL) {
+        p_ctl->ch_handle    = handle;
+        p_ctl->MaxNum       = max_buff_num;
+        p_ctl->p_aio_top    = NULL;
+        p_ctl->index        = 0;
+        p_ctl->p_async_func = p_func_a;
+        if (p_ctl->MaxNum != 0) {
+            p_ctl->p_sem_ctl    = new Semaphore(p_ctl->MaxNum);
+            p_ctl->p_aio_top    = new AIOCB[p_ctl->MaxNum];
+            p_ctl->p_sival_top  = new rbsp_sival_t[p_ctl->MaxNum];
+        }
+    }
+}
+
+int32_t R_BSP_Aio::write(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    if (p_data_conf == NULL) {
+        return sync_trans(&write_ctl, p_data, data_size);
+    } else {
+        return aio_trans(&write_ctl, p_data, data_size, p_data_conf);
+    }
+}
+
+int32_t R_BSP_Aio::read(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    if (p_data_conf == NULL) {
+        return sync_trans(&read_ctl, p_data, data_size);
+    } else {
+        return aio_trans(&read_ctl, p_data, data_size, p_data_conf);
+    }
+}
+
+/* static */ int32_t R_BSP_Aio::sync_trans(rbsp_serial_ctl_t * p_ctl, void * const p_data, uint32_t data_size) {
+    rbsp_sync_t sync_info;
+    rbsp_data_conf_t data_conf;
+    Semaphore * p_sem_wait = new Semaphore(0);
+
+    sync_info.result = -1;
+    if (p_sem_wait != NULL) {
+        sync_info.p_sem  = p_sem_wait;
+
+        data_conf.p_notify_func = &callback_sync_trans;
+        data_conf.p_app_data    = &sync_info;
+
+        if (aio_trans(p_ctl, p_data, data_size, &data_conf) == ESUCCESS) {
+            p_sem_wait->wait(osWaitForever);
+        }
+        delete p_sem_wait;
+    }
+
+    return sync_info.result;
+}
+
+/* static */ void R_BSP_Aio::callback_sync_trans(void * p_data, int32_t result, void * p_app_data) {
+    rbsp_sync_t * p_sync_info = (rbsp_sync_t *)p_app_data;
+
+    p_sync_info->result = result;
+    p_sync_info->p_sem->release();
+}
+
+/* static */ int32_t R_BSP_Aio::aio_trans(rbsp_serial_ctl_t * const p_ctl,
+               void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    int32_t wk_errno;
+    AIOCB * p_rbsp_aio;
+    rbsp_sival_t * p_sival;
+    rbsp_read_write_a_func_t p_func = (rbsp_read_write_a_func_t)p_ctl->p_async_func;
+
+    if ((p_data_conf == NULL) || (p_data == NULL)) {
+        wk_errno = ENOSPC_RBSP;
+    } else if (p_ctl->p_sem_ctl->wait(osWaitForever) == -1) {
+        wk_errno = EIO_RBSP;
+    } else {
+        p_rbsp_aio = (AIOCB *)p_ctl->p_aio_top + p_ctl->index;
+        p_sival    = p_ctl->p_sival_top + p_ctl->index;
+
+        p_sival->p_cb_func     = p_data_conf->p_notify_func;
+        p_sival->p_cb_data     = p_data_conf->p_app_data;
+        p_sival->p_sem         = p_ctl->p_sem_ctl;
+        p_sival->p_aio         = p_rbsp_aio;
+
+        p_rbsp_aio->aio_fildes = 0;
+        p_rbsp_aio->aio_buf    = p_data;
+        p_rbsp_aio->aio_nbytes = data_size;
+        p_rbsp_aio->aio_offset = 0;
+        p_rbsp_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+        p_rbsp_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_sival;
+        p_rbsp_aio->aio_sigevent.sigev_notify_function = &callback_aio_trans;
+        p_func(p_ctl->ch_handle, p_rbsp_aio, &wk_errno);
+
+        if (wk_errno == ESUCCESS) {
+            if ((p_ctl->index + 1) >= p_ctl->MaxNum) {
+                p_ctl->index = 0;
+            } else {
+                p_ctl->index++;
+            }
+        } else {
+            p_ctl->p_sem_ctl->release();
+        }
+    }
+
+    return wk_errno;
+}
+
+/* static */ void R_BSP_Aio::callback_aio_trans(union sigval signo) {
+    rbsp_sival_t * p_sival = (rbsp_sival_t *)signo.sival_ptr;
+    AIOCB * p_aio_result = (AIOCB *)p_sival->p_aio;
+
+    if ((p_sival->p_cb_func != NULL) && (p_aio_result != NULL)) {
+        p_sival->p_cb_func((void *)p_aio_result->aio_buf, p_aio_result->aio_return, p_sival->p_cb_data);
+    }
+    p_sival->p_sem->release();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/common/R_BSP_Scux.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,357 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "R_BSP_Scux.h"
+#if (R_BSP_SCUX_ENABLE == 1)
+#include "r_bsp_cmn.h"
+#include "scux_if.h"
+
+#define CH_ERR_NUM                  (-1)     /* Channel error number */
+#define INT_LEVEL_MAX               (0xF7)   /* The maximum value of the interrupt level */
+#define REQ_BUFF_NUM_MIN            (1)      /* The minimum value of the request buffer */
+#define REQ_BUFF_NUM_MAX            (128)    /* The maximum value of the request buffer */
+#define INPUT_DIV_INIT_VALUE        (1000U)  /* The initial value of input divide ratio */
+#define OUTPUT_DIV_INIT_VALUE       (0U)     /* The initial value of output divide ratio  */
+#define INPUT_WS_INIT_VALUE         (1U)     /* The initial value of input WS frequency */
+#define OUTPUT_WS_INIT_VALUE        (96000U) /* The initial value of output WS frequency */
+#define FREQ_TIOC3A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC3 */
+#define FREQ_TIOC4A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC4 */
+#define WAIT_SAMPLE_INIT_VALUE      (0U)     /* The initial value of wait time */
+#define MIN_RATE_PER_INIT_VALUE     (98U)    /* The initial value of minimum rate */
+#define DIV_RATIO_CLK_AUDIO_22050HZ (1024U)  /* Divide ratio when the frequency is 22050Hz */
+#define DIV_RATIO_CLK_AUDIO_44100HZ (512U)   /* Divide ratio when the frequency is 44100Hz */
+#define DIV_RATIO_CLK_AUDIO_88200HZ (256U)   /* Divide ratio when the frequency is 88200Hz */
+#define DIV_RATIO_CLK_USB_24000HZ   (2000U)  /* Divide ratio when the frequency is 24000Hz */
+#define DIV_RATIO_CLK_USB_32000HZ   (1500U)  /* Divide ratio when the frequency is 36000Hz */
+#define DIV_RATIO_CLK_USB_48000HZ   (1000U)  /* Divide ratio when the frequency is 48000Hz */
+#define DIV_RATIO_CLK_USB_64000HZ   (750U)   /* Divide ratio when the frequency is 64000Hz */
+#define DIV_RATIO_CLK_USB_96000HZ   (500U)   /* Divide ratio when the frequency is 96000Hz */
+
+static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg);
+
+R_BSP_Scux::R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
+    scux_channel_cfg_t scux_cfg;
+    int32_t result;
+    bool    init_result;
+
+    if (channel >= SCUX_CH_NUM) {
+        result = EERROR;
+    } else if (int_level > INT_LEVEL_MAX) {
+        result = EERROR;
+    } else if ((max_write_num < REQ_BUFF_NUM_MIN) || (max_write_num > REQ_BUFF_NUM_MAX)) {
+        result = EERROR;
+    } else if ((max_read_num < REQ_BUFF_NUM_MIN) || (max_read_num > REQ_BUFF_NUM_MAX)) {
+        result = EERROR;
+    } else {
+        result = R_BSP_CMN_Init();
+        if (result == ESUCCESS) {
+            scux_ch = (int32_t)channel;
+
+            scux_cfg.enabled       = true;
+            scux_cfg.int_level     = int_level;
+
+            switch (channel) {
+                case SCUX_CH_0:
+                    scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
+                    break;
+                case SCUX_CH_1:
+                    scux_cfg.route = SCUX_ROUTE_SRC1_MEM;
+                    break;
+                case SCUX_CH_2:
+                    scux_cfg.route = SCUX_ROUTE_SRC2_MEM;
+                    break;
+                case SCUX_CH_3:
+                    scux_cfg.route = SCUX_ROUTE_SRC3_MEM;
+                    break;
+                default:
+                    /* NOTREACHED on At the time of a normal performance */
+                    scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
+                    break;
+            }
+
+            init_result = set_src_init_cfg(&scux_cfg.src_cfg);
+            if (init_result != false) {
+                init_result = init_channel(R_SCUX_MakeCbTbl_mbed(), (int32_t)channel, &scux_cfg, max_write_num, max_read_num);
+                if (init_result == false) {
+                    result = EERROR;
+                }
+            } else {
+                result = EERROR;
+            }
+        }
+    }
+
+    if (result != ESUCCESS) {
+        scux_ch   = CH_ERR_NUM;
+    }
+}
+
+R_BSP_Scux::~R_BSP_Scux(void) {
+}
+
+bool R_BSP_Scux::TransStart(void) {
+    return ioctl(SCUX_IOCTL_SET_START, NULL);
+}
+
+bool R_BSP_Scux::FlushStop(void (* const callback)(int32_t)) {
+    return ioctl(SCUX_IOCTL_SET_FLUSH_STOP, (void *)callback);
+}
+
+bool R_BSP_Scux::ClearStop(void) {
+    return ioctl(SCUX_IOCTL_SET_CLEAR_STOP, NULL);
+}
+
+bool R_BSP_Scux::SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param) {
+    scux_src_cfg_t src_cfg;
+    bool    init_result;
+    bool    ret = true;
+    int32_t i;
+
+    if (scux_ch == CH_ERR_NUM) {
+        ret = false;
+    } else if (p_src_param == NULL) {
+        ret = false;
+    } else if ((p_src_param->mode_sync != false) && (p_src_param->src_enable == false)) {
+        ret = false;
+    } else {
+        init_result = set_src_init_cfg(&src_cfg);
+        if (init_result != true) {
+            ret = false;
+        } else {
+            src_cfg.src_enable = p_src_param->src_enable;
+            src_cfg.mode_sync  = p_src_param->mode_sync;
+
+            switch (p_src_param->word_len) {
+                case SCUX_DATA_LEN_24:
+                    /* fall through */
+                case SCUX_DATA_LEN_16:
+                    /* fall through */
+                case SCUX_DATA_LEN_16_TO_24:
+                    src_cfg.word_len = p_src_param->word_len;
+                    break;
+                default:
+                    ret = false;
+                    break;
+            }
+
+            if (ret == true) {
+                if (p_src_param->mode_sync != false) {
+                    switch (p_src_param->input_rate) {
+                        case SAMPLING_RATE_8000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_8;
+                            break;
+                        case SAMPLING_RATE_11025HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_11_025;
+                            break;
+                        case SAMPLING_RATE_12000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_12;
+                            break;
+                        case SAMPLING_RATE_16000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_16;
+                            break;
+                        case SAMPLING_RATE_22050HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_22_05;
+                            break;
+                        case SAMPLING_RATE_24000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_24;
+                            break;
+                        case SAMPLING_RATE_32000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_32;
+                            break;
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_44_1;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_48;
+                            break;
+                        case SAMPLING_RATE_64000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_64;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_88_2;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_96;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                } else {
+                    switch (p_src_param->input_rate) {
+                        case SAMPLING_RATE_22050HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_22050HZ;
+                            break;
+                        case SAMPLING_RATE_24000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_24000HZ;
+                            break;
+                        case SAMPLING_RATE_32000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_32000HZ;
+                            break;
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_44100HZ;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_48000HZ;
+                            break;
+                        case SAMPLING_RATE_64000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_64000HZ;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_88200HZ;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_96000HZ;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                if (p_src_param->mode_sync != false) {
+                    switch (p_src_param->output_rate) {
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_44_1;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_48;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_96;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                } else {
+                    switch (p_src_param->output_rate) {
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_44100HZ;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_48000HZ;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_88200HZ;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_96000HZ;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                for (i = 0; i < SCUX_USE_CH_2; i++) {
+                    switch (p_src_param->select_in_data_ch[i]) {
+                        case SELECT_IN_DATA_CH_0:
+                            src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_0;
+                            break;
+                        case SELECT_IN_DATA_CH_1:
+                            src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_1;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                ret = ioctl(SCUX_IOCTL_SET_SRC_CFG, (void *)&src_cfg);
+            }
+        }
+    }
+
+    return ret;
+}
+
+bool R_BSP_Scux::GetWriteStat(uint32_t * const p_write_stat) {
+    return ioctl(SCUX_IOCTL_GET_WRITE_STAT, (void *)p_write_stat);
+}
+
+bool R_BSP_Scux::GetReadStat(uint32_t * const p_read_stat) {
+    return ioctl(SCUX_IOCTL_GET_READ_STAT, (void *)p_read_stat);
+}
+
+/**************************************************************************//**
+* Function Name: set_src_init_cfg
+* @brief         SRC configuration initialization.
+*
+*                Description:<br>
+*                
+* @param[in]     src_cfg SRC configuration. 
+* @retval        true  Setting success.
+*                false Setting fails.
+******************************************************************************/
+static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg) {
+    bool ret = true;
+
+    if (src_cfg == NULL) {
+        ret = false;
+    } else {
+        src_cfg->src_enable                         = true;
+        src_cfg->use_ch                             = SCUX_USE_CH_2;
+        src_cfg->word_len                           = SCUX_DATA_LEN_16;
+        src_cfg->mode_sync                          = true;
+        src_cfg->input_rate_sync                    = SCUX_SYNC_RATE_48;
+        src_cfg->input_clk_async                    = SCUX_CLK_USB_X1;
+        src_cfg->input_div_async                    = INPUT_DIV_INIT_VALUE;
+        src_cfg->output_rate_sync                   = SCUX_SYNC_RATE_96;
+        src_cfg->output_clk_async                   = SCUX_CLK_SSIF0_WS;
+        src_cfg->output_div_async                   = OUTPUT_DIV_INIT_VALUE;
+        src_cfg->input_ws                           = INPUT_WS_INIT_VALUE;
+        src_cfg->output_ws                          = OUTPUT_WS_INIT_VALUE;
+        src_cfg->freq_tioc3a                        = FREQ_TIOC3A_INIT_VALUE;
+        src_cfg->freq_tioc4a                        = FREQ_TIOC4A_INIT_VALUE;
+        src_cfg->delay_mode                         = SCUX_DELAY_NORMAL;
+        src_cfg->wait_sample                        = WAIT_SAMPLE_INIT_VALUE;
+        src_cfg->min_rate_percentage                = MIN_RATE_PER_INIT_VALUE;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_0] = SCUX_AUDIO_CH_0;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_1] = SCUX_AUDIO_CH_1;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_2] = SCUX_AUDIO_CH_2;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_3] = SCUX_AUDIO_CH_3;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_4] = SCUX_AUDIO_CH_4;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_5] = SCUX_AUDIO_CH_5;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_6] = SCUX_AUDIO_CH_6;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_7] = SCUX_AUDIO_CH_7;
+    }
+
+    return ret;
+}
+
+#endif /* R_BSP_SCUX_ENABLE */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/common/R_BSP_SerialFamily.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,122 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "r_bsp_cmn.h"
+#include "R_BSP_SerialFamily.h"
+#include "posix_types.h"
+#include "r_errno.h"
+
+#define PATH_NAME_LENGTH            (3)      /* Path name length */
+#define PATH_TOP_PART               (0)      /* Path top part */
+#define CH_ID_PART                  (1)      /* Channel identifier part */
+#define TERM_CHAR_PART              (2)      /* Termination character part */
+#define PATH_SEPARATOR              ('\\')   /* Path separator */
+#define CHARACTER_0                 (0x30)   /* character 0 */
+
+R_BSP_SerialFamily::~R_BSP_SerialFamily() {
+    if (functions != NULL) {
+        if ((ch_handle != NULL) && (functions->close != NULL)) {
+            (void)functions->close(ch_handle, NULL);
+        }
+        if ((ch_no != -1) && (instance != NULL) && (functions->uninitialise_one != NULL)) {
+            (void)functions->uninitialise_one(ch_no, instance, NULL);
+        }
+    }
+}
+
+bool R_BSP_SerialFamily::init_channel(RBSP_MBED_FNS * function_list, int channel, void * const config_data,
+                                      int32_t max_write_num, int32_t max_read_num) {
+    bool    ret = false;
+    int32_t wk_errno;
+    char_t  path_name[PATH_NAME_LENGTH];
+    int_t   flags;
+
+    if ((max_write_num > 0) && (max_read_num > 0)) {
+        flags = O_RDWR_RBSP;
+    } else if (max_write_num > 0) {
+        flags = O_WRONLY_RBSP;
+    } else if (max_read_num > 0) {
+        flags = O_RDONLY_RBSP;
+    } else {
+        flags = 0;
+    }
+
+    if ((channel >= 0) && (channel <= 9) && (function_list != NULL) && (flags != 0)) {
+        ch_no     = channel;
+        functions = function_list;
+
+        if ((functions->initialise_one != NULL) && (functions->open != NULL)) {
+            R_BSP_CMN_Init();
+            instance = functions->initialise_one(ch_no, config_data, &wk_errno);
+            if ((int32_t)instance != EERROR) {
+                path_name[PATH_TOP_PART]  = PATH_SEPARATOR;
+                path_name[CH_ID_PART]     = CHARACTER_0 + ch_no;
+                path_name[TERM_CHAR_PART] = '\0';
+                ch_handle = (void *)functions->open(instance, path_name, flags, 0, &wk_errno);
+                if ((int32_t)ch_handle != EERROR) {
+                    if (functions->write_a != NULL) {
+                        write_init(ch_handle, (void *)functions->write_a, max_write_num);
+                    }
+                    if (functions->read_a != NULL) {
+                        read_init(ch_handle, (void *)functions->read_a, max_read_num);
+                    }
+                    ret = true;
+                } else {
+                    (void)((RBSP_MBED_FNS *)functions)->uninitialise_one(ch_no, instance, NULL);
+                }
+            }
+        }
+    }
+
+    if (ret == false) {
+        functions = NULL;
+        instance  = NULL;
+        ch_handle = NULL;
+        ch_no     = -1;
+    }
+
+    return ret;
+}
+
+bool R_BSP_SerialFamily::ioctl(int request, ...) {
+    bool    ret = true;
+    int32_t wk_errno;
+    void *buf;
+    va_list ap;
+
+    if (functions == NULL) {
+        ret = false;
+    } else if (functions->ioctl == NULL) {
+        ret = false;
+    } else {
+        va_start(ap, request);
+        buf = (void *)va_arg(ap, void*);
+        functions->ioctl(ch_handle, request, buf, &wk_errno);
+        va_end(ap);
+        if (wk_errno != ESUCCESS) {
+            ret = false;
+        }
+    }
+
+    return ret;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/common/R_BSP_Spdif.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "R_BSP_Spdif.h"
+#if (R_BSP_SPDIF_ENABLE == 1)
+#include "r_bsp_cmn.h"
+#include "spdif_if.h"
+#include "spdif_api.h"
+
+R_BSP_Spdif::R_BSP_Spdif(PinName audio_clk, PinName tx, PinName rx) : spdif_ch(-1) {
+    int32_t wk_channel;
+
+    wk_channel = spdif_init(audio_clk, tx, rx);
+    if (wk_channel != NC) {
+        spdif_ch = wk_channel;
+    }
+}
+
+R_BSP_Spdif::~R_BSP_Spdif() {
+    // do nothing
+}
+
+void R_BSP_Spdif::init(const spdif_channel_cfg_t* const p_ch_cfg, int32_t max_write_num, int32_t max_read_num) {
+    if (spdif_ch >= 0) {
+        init_channel(R_SPDIF_MakeCbTbl_mbed(), spdif_ch, (void *)p_ch_cfg, max_write_num, max_read_num);
+    }
+}
+
+bool R_BSP_Spdif::ConfigChannel(const spdif_channel_cfg_t* const p_ch_cfg) {
+    return ioctl(SPDIF_CONFIG_CHANNEL, (void *)p_ch_cfg);
+}
+
+bool R_BSP_Spdif::SetChannelStatus(uint32_t status_Lch, uint32_t status_Rch) {
+    spdif_channel_status_t channel_status;
+
+    channel_status.Lch = status_Lch;
+    channel_status.Rch = status_Rch;
+
+    return ioctl(SPDIF_SET_CHANNEL_STATUS, (void *)&channel_status);
+}
+
+bool R_BSP_Spdif::GetChannelStatus(uint32_t * p_status_Lch, uint32_t * p_status_Rch) {
+    spdif_channel_status_t channel_status;
+
+    if (ioctl(SPDIF_GET_CHANNEL_STATUS, (void *)&channel_status) != false) {
+        if (p_status_Lch != NULL) {
+            *p_status_Lch = channel_status.Lch;
+        }
+        if (p_status_Rch != NULL) {
+            *p_status_Rch = channel_status.Rch;
+        }
+    }
+
+    return true;
+}
+
+bool R_BSP_Spdif::SetTransAudioBit(int direction, char length) {
+    spdif_chcfg_audio_bit_t audio_bit;
+    int control_type;
+
+    if (direction == 0) {
+        control_type = SPDIF_SET_TRANS_AUDIO_BIT;
+    } else {
+        control_type = SPDIF_SET_RECV_AUDIO_BIT;
+    }
+
+    switch (length) {
+        case 16:
+            audio_bit = SPDIF_CFG_AUDIO_BIT_16;
+            break;
+        case 20:
+            audio_bit = SPDIF_CFG_AUDIO_BIT_20;
+            break;
+        case 24:
+            audio_bit = SPDIF_CFG_AUDIO_BIT_24;
+            break;
+        default:
+            return false;
+    }
+
+    return ioctl(control_type, (void *)&audio_bit);
+}
+
+#endif /* R_BSP_SPDIF_ENABLE */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/common/R_BSP_Ssif.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "r_bsp_cmn.h"
+#include "R_BSP_Ssif.h"
+#include "ssif_if.h"
+#include "ssif_api.h"
+
+R_BSP_Ssif::R_BSP_Ssif(PinName sck, PinName ws, PinName tx, PinName rx, PinName audio_clk) : ssif_ch(-1) {
+    int32_t wk_channel;
+
+    wk_channel = ssif_init(sck, ws, tx, rx, audio_clk);
+    if (wk_channel != NC) {
+        ssif_ch      = wk_channel;
+    }
+}
+
+R_BSP_Ssif::~R_BSP_Ssif() {
+    // do nothing
+}
+
+void R_BSP_Ssif::init(const ssif_channel_cfg_t* const p_ch_cfg, int32_t max_write_num, int32_t max_read_num) {
+    if (ssif_ch >= 0) {
+        init_channel(R_SSIF_MakeCbTbl_mbed(), ssif_ch, (void *)p_ch_cfg, max_write_num, max_read_num);
+    }
+}
+
+
+bool R_BSP_Ssif::ConfigChannel(const ssif_channel_cfg_t* const p_ch_cfg) {
+    return ioctl(SSIF_CONFIG_CHANNEL, (void *)p_ch_cfg);
+}
+
+bool R_BSP_Ssif::GetStatus(uint32_t* const p_status) {
+    return ioctl(SSIF_CONFIG_CHANNEL, (void *)p_status);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/R_BSP_mbed_fns.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,54 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+
+#ifndef R_BSP_MBED_FNS_H
+#define R_BSP_MBED_FNS_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "ioif_aio.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+typedef struct {
+    void *(*initialise_one)(const int_t channel, const void* const config_data, int32_t* const p_errno);
+    int_t (*uninitialise_one)(const int_t channel, const void* const driver_instance, int32_t* const p_errno);
+    int_t (*open)(void *driver_instance, const char_t *pathname, int_t flags, int_t mode, int32_t* p_errno);
+    int_t (*close)(void *fd, int32_t* p_errno);
+    int_t (*ioctl)(void *fd, int_t request, void *buf, int32_t* p_errno);
+    int_t (*read_a)(void *fd, struct aiocb *p_aio, int32_t* p_errno);
+    int_t (*write_a)(void *fd, struct aiocb *p_aio, int32_t* p_errno);
+    int_t (*cancel)(void *fd, struct aiocb *p_aio, int32_t* p_errno);
+} RBSP_MBED_FNS;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_MBED_FNS_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/bsp_util.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         bsp_util.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief        BSP Utilities
+******************************************************************************/
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    rt_CMSIS.c
+ *      Purpose: CMSIS RTOS API
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis.h"
+#include "mbed_critical.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_ExceptionalMode
+* @brief         Get current context
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval 0      Current context is non-task
+* @retval 1      Current context is task
+******************************************************************************/
+int32_t R_ExceptionalMode(void)
+{
+    if (core_util_is_isr_active() == false) {
+        return 0;
+    } else {
+        return 1;
+    }
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/r_bsp_cmn.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include <stdio.h>
+#include "dma_if.h"
+
+
+static bool_t dma_init_end = false;
+static dma_drv_init_t dma_init_param;
+void userdef_dma_error_callback(union sigval signo);
+static AIOCB dma_err_aio;
+
+int32_t R_BSP_CMN_Init(void) {
+    int32_t retval = ESUCCESS;
+
+    if (dma_init_end == false) {
+        dma_init_end = true;
+        /***********************************************************************/
+        /* Initialise DMA */
+        /***********************************************************************/
+
+        dma_init_param.channel[DMA_CH_0] = true;
+        dma_init_param.channel[DMA_CH_1] = true;
+        dma_init_param.channel[DMA_CH_2] = true;
+        dma_init_param.channel[DMA_CH_3] = true;
+        dma_init_param.channel[DMA_CH_4] = true;
+        dma_init_param.channel[DMA_CH_5] = true;
+        dma_init_param.channel[DMA_CH_6] = true;
+        dma_init_param.channel[DMA_CH_7] = true;
+        dma_init_param.channel[DMA_CH_8] = true;
+        dma_init_param.channel[DMA_CH_9] = true;
+        dma_init_param.channel[DMA_CH_10] = true;
+        dma_init_param.channel[DMA_CH_11] = true;
+        dma_init_param.channel[DMA_CH_12] = true;
+        dma_init_param.channel[DMA_CH_13] = true;
+        dma_init_param.channel[DMA_CH_14] = true;
+        dma_init_param.channel[DMA_CH_15] = true;
+
+        dma_err_aio.aio_sigevent.sigev_notify = SIGEV_THREAD;
+        dma_err_aio.aio_sigevent.sigev_notify_function = &userdef_dma_error_callback;
+        dma_init_param.p_aio = &dma_err_aio;
+
+        retval = R_DMA_Init(&dma_init_param, NULL);
+        if (retval != ESUCCESS) {
+            dma_init_end = false;
+        }
+    }
+
+    return retval;
+}
+
+/**************************************************************************//**
+* Function Name: userdef_dma_error_callback
+* @brief         DMA driver : error callback function
+*
+*                Description:<br>
+*                DMA error interrupt callback function
+* @param[in]     signo.sival_int : bitmap of error channel(bit0=ch0)
+* @retval        none
+******************************************************************************/
+void userdef_dma_error_callback(union sigval signo) {
+    printf("DMAERR MAP:0x%02x\n", signo.sival_int);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/r_bsp_cmn.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,48 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+
+#ifndef R_BSP_CMN_H
+#define R_BSP_CMN_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+extern int32_t R_BSP_CMN_Init(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_CMN_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/spdif_api.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,68 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#if defined(TARGET_RZ_A2XX)
+
+#include "spdif_api.h"
+
+static const PinMap PinMap_SPDIF_AUDIO_CLK[] = {
+    {P6_4,  0,      4},
+    {PH_0,  0,      1},
+    {NC,    NC,     0}
+};
+
+static const PinMap PinMap_SPDIF_TX[] = {
+    {PJ_0,  0,      2},
+    {PC_5,  0,      4},
+    {NC,    NC,     0}
+};
+
+static const PinMap PinMap_SPDIF_RX[] = {
+    {PJ_1,  0,      2},
+    {PC_4,  0,      4},
+    {NC,    NC,     0}
+};
+
+int32_t spdif_init(PinName audio_clk, PinName tx, PinName rx) {
+    /* determine the ssif to use */
+    uint32_t spdif_clk = pinmap_peripheral(audio_clk, PinMap_SPDIF_AUDIO_CLK);
+    uint32_t spdif_tx  = pinmap_peripheral(tx, PinMap_SPDIF_TX);
+    uint32_t spdif_rx  = pinmap_peripheral(rx, PinMap_SPDIF_RX);
+    uint32_t spdif_ch  = pinmap_merge(spdif_tx, spdif_rx);
+
+    if ((int32_t)spdif_clk != NC) {
+        pinmap_pinout(audio_clk, PinMap_SPDIF_AUDIO_CLK);
+    }
+
+    if ((int32_t)spdif_tx != NC) {
+        pinmap_pinout(tx, PinMap_SPDIF_TX);
+    }
+
+    if ((int32_t)spdif_rx != NC) {
+        pinmap_pinout(rx, PinMap_SPDIF_RX);
+    }
+
+    return (int32_t)spdif_ch;
+}
+
+#endif /* TARGET_RZ_A2XX */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/spdif_api.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,43 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#if defined(TARGET_RZ_A2XX)
+
+#ifndef MBED_SPDIF_API_H
+#define MBED_SPDIF_API_H
+
+#include "pinmap.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32_t spdif_init(PinName audio_clk, PinName tx, PinName rx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif /* TARGET_RZ_A2XX */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/ssif_api.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,250 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "ssif_api.h"
+
+#if defined(TARGET_RZ_A1XX)
+#if defined(TARGET_RZA1H) /* mbed */
+static const PinMap PinMap_SSIF_SCK[] = {
+//   pin      ch     func
+    {P2_8   , 0    , 4},
+    {P4_4   , 0    , 5},
+    {P3_4   , 1    , 3},
+    {P7_1   , 1    , 6},
+    {P10_12 , 1    , 2},
+    {P7_5   , 2    , 6},
+    {P9_5   , 2    , 3},
+    {P4_12  , 3    , 6},
+    {P7_8   , 3    , 2},
+    {P7_12  , 4    , 2},
+    {P8_12  , 4    , 8},
+    {P11_4  , 4    , 3},
+    {P2_4   , 5    , 4},
+    {P4_8   , 5    , 5},
+    {P8_8   , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_WS[] = {
+//   pin      ch     func
+    {P2_9   , 0    , 4},
+    {P4_5   , 0    , 5},
+    {P3_5   , 1    , 3},
+    {P7_2   , 1    , 6},
+    {P10_13 , 1    , 2},
+    {P7_6   , 2    , 6},
+    {P9_6   , 2    , 3},
+    {P4_13  , 3    , 6},
+    {P7_9   , 3    , 2},
+    {P7_13  , 4    , 2},
+    {P8_13  , 4    , 8},
+    {P11_5  , 4    , 3},
+    {P2_5   , 5    , 4},
+    {P4_9   , 5    , 5},
+    {P8_9   , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_TxD[] = {
+//   pin      ch     func
+    {P2_11  , 0    , 4},
+    {P4_7   , 0    , 5},
+    {P7_4   , 1    , 6},
+    {P10_15 , 1    , 2},
+    {P7_7   , 2    , 6},  /* SSIDATA2 */
+    {P9_7   , 2    , 3},  /* SSIDATA2 */
+    {P4_15  , 3    , 6},
+    {P7_11  , 3    , 2},
+    {P6_1   , 4    , 6},  /* SSIDATA4 */
+    {P7_14  , 4    , 2},  /* SSIDATA4 */
+    {P8_14  , 4    , 8},  /* SSIDATA4 */
+    {P11_6  , 4    , 3},  /* SSIDATA4 */
+    {P2_7   , 5    , 4},
+    {P4_11  , 5    , 5},
+    {P8_10  , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_RxD[] = {
+//   pin      ch     func
+    {P2_10  , 0    , 4},
+    {P4_6   , 0    , 5},
+    {P3_7   , 1    , 3},
+    {P7_3   , 1    , 6},
+    {P10_14 , 1    , 2},
+    {P7_7   , 2    , 6},  /* SSIDATA2 */
+    {P9_7   , 2    , 3},  /* SSIDATA2 */
+    {P4_14  , 3    , 6},
+    {P7_10  , 3    , 2},
+    {P6_1   , 4    , 6},  /* SSIDATA4 */
+    {P7_14  , 4    , 2},  /* SSIDATA4 */
+    {P8_14  , 4    , 8},  /* SSIDATA4 */
+    {P11_6  , 4    , 3},  /* SSIDATA4 */
+    {P2_6   , 5    , 4},
+    {P4_10  , 5    , 5},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SPDIF_AUDIO_CLK[] = {
+    {NC,    NC,     0}
+};
+
+#else
+static const PinMap PinMap_SSIF_SCK[] = {
+//   pin      ch     func
+    {P2_7   , 3    , 2},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_WS[] = {
+//   pin      ch     func
+    {P2_9   , 3    , 2},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_TxD[] = {
+//   pin      ch     func
+    {P2_8   , 3    , 2},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_RxD[] = {
+//   pin      ch     func
+    {P2_6   , 3    , 2},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SPDIF_AUDIO_CLK[] = {
+    {NC,    NC,     0}
+};
+
+#endif
+
+static void ssif_power_enable(uint32_t ssif_ch) {
+    volatile uint8_t dummy;
+
+    switch (ssif_ch) {
+        case 0:
+            CPGSTBCR11 &= ~(0x20);
+            break;
+        case 1:
+            CPGSTBCR11 &= ~(0x10);
+            break;
+        case 2:
+            CPGSTBCR11 &= ~(0x08);
+            break;
+        case 3:
+            CPGSTBCR11 &= ~(0x04);
+            break;
+#if defined(TARGET_RZA1H) /* mbed */
+        case 4:
+            CPGSTBCR11 &= ~(0x02);
+            break;
+        case 5:
+            CPGSTBCR11 &= ~(0x01);
+            break;
+#endif
+    }
+    dummy = CPGSTBCR11;
+    (void)dummy;
+}
+
+#elif defined(TARGET_RZ_A2XX)
+
+static const PinMap PinMap_SSIF_SCK[] = {
+//   pin      ch     func
+    {P9_6   , 0    , 5},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_WS[] = {
+//   pin      ch     func
+    {P9_5   , 0    , 5},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_TxD[] = {
+//   pin      ch     func
+    {P9_4   , 0    , 5},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_RxD[] = {
+//   pin      ch     func
+    {P9_3   , 0    , 5},
+    {NC     , NC   , 0}
+};
+
+static void ssif_power_enable(uint32_t ssif_ch) {
+    volatile uint8_t dummy;
+
+    switch (ssif_ch) {
+        case 0:
+            CPG.STBCR7.BYTE &= ~(0x08);
+            break;
+        case 1:
+            CPG.STBCR7.BYTE &= ~(0x04);
+            break;
+        case 2:
+            CPG.STBCR7.BYTE &= ~(0x02);
+            break;
+        case 3:
+            CPG.STBCR7.BYTE &= ~(0x01);
+            break;
+    }
+    dummy = CPG.STBCR7.BYTE;
+    (void)dummy;
+}
+
+static const PinMap PinMap_SPDIF_AUDIO_CLK[] = {
+    {P6_4,  0,      4},
+    {PH_0,  0,      1},
+    {NC,    NC,     0}
+};
+
+#endif
+
+int32_t ssif_init(PinName sck, PinName ws, PinName tx, PinName rx, PinName audio_clk) {
+    /* determine the ssif to use */
+    uint32_t ssif_sck = pinmap_peripheral(sck, PinMap_SSIF_SCK);
+    uint32_t ssif_ws  = pinmap_peripheral(ws,  PinMap_SSIF_WS);
+    uint32_t ssif_tx  = pinmap_peripheral(tx,  PinMap_SSIF_TxD);
+    uint32_t ssif_rx  = pinmap_peripheral(rx,  PinMap_SSIF_RxD);
+    uint32_t ssif_ch  = pinmap_merge(ssif_tx, ssif_rx);
+
+    if ((ssif_ch == ssif_sck) && (ssif_ch == ssif_ws)) {
+        ssif_power_enable(ssif_ch);
+        pinmap_pinout(sck, PinMap_SSIF_SCK);
+        pinmap_pinout(ws,  PinMap_SSIF_WS);
+        pinmap_pinout(tx,  PinMap_SSIF_TxD);
+        pinmap_pinout(rx,  PinMap_SSIF_RxD);
+        if ((int32_t)audio_clk != NC) {
+            pinmap_pinout(audio_clk, PinMap_SPDIF_AUDIO_CLK);
+        }
+    } else {
+        ssif_ch = (uint32_t)NC;
+    }
+
+    return (int32_t)ssif_ch;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/R_BSP/tools/ssif_api.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,39 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef MBED_SSIF_API_H
+#define MBED_SSIF_API_H
+
+#include "pinmap.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32_t ssif_init(PinName sck, PinName ws, PinName tx, PinName rx, PinName audio_clk);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A1XX/SDBlockDevice_GRBoard.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,72 @@
+/* Copyright (c) 2017 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SDFILESYSTEM_GRBOARD_H
+#define MBED_SDFILESYSTEM_GRBOARD_H
+
+#include "SDBlockDevice.h"
+
+/**
+ * A class to communicate a SD
+ */
+class SDBlockDevice_GRBoard : public SDBlockDevice {
+public:
+
+    /**
+    * Constructor
+    *
+    */
+    SDBlockDevice_GRBoard() :
+#if defined(TARGET_RZ_A1H)
+      SDBlockDevice(P8_5, P8_6, P8_3, P8_4, 15000000), _sd_cd(P7_8),
+#elif defined(TARGET_GR_LYCHEE)
+      SDBlockDevice(P5_6, P5_7, P5_4, P5_5, 15000000), _sd_cd(P3_8),
+#endif
+      _connect(false) {
+    }
+
+    /**
+    * Check if a SD is connected
+    *
+    * @return true if a SD is connected
+    */
+    bool connected() {
+        if (_sd_cd.read() != 0) {
+            _connect = false;
+        }
+        return _connect;
+    }
+
+    /**
+     * Try to connect to a SD
+     *
+     * @return true if connection was successful
+     */
+    bool connect() {
+        if (_sd_cd.read() == 0) {
+            _connect = true;
+        } else {
+            _connect = false;
+        }
+        return _connect;
+    }
+
+
+private:
+    DigitalIn   _sd_cd;
+    bool        _connect;
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/SDBlockDevice_GRBoard.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,68 @@
+/* Copyright (c) 2018 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SDFILESYSTEM_GRBOARD_H
+#define MBED_SDFILESYSTEM_GRBOARD_H
+
+#include "SDHSBlockDevice.h"
+
+/**
+ * A class to communicate a SD
+ */
+class SDBlockDevice_GRBoard : public SDHSBlockDevice {
+public:
+
+    /**
+    * Constructor
+    *
+    */
+    SDBlockDevice_GRBoard() :
+#if defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF)
+      SDHSBlockDevice(P5_4, P5_5),
+#elif defined(TARGET_RZ_A2M_SBEV)
+      SDHSBlockDevice(P5_4, NC),
+#else
+      SDHSBlockDevice(NC, NC),
+#endif
+      _connect(false) {
+    }
+
+    /**
+    * Check if a SD is connected
+    *
+    * @return true if a SD is connected
+    */
+    bool connected() {
+        if (is_connect() == false) {
+            _connect = false;
+        }
+        return _connect;
+    }
+
+    /**
+     * Try to connect to a SD
+     *
+     * @return true if connection was successful
+     */
+    bool connect() {
+        _connect = is_connect();
+        return _connect;
+    }
+
+private:
+   bool        _connect;
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/SDHSBlockDevice.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,377 @@
+/******************************************************************************
+* DISCLAIMER
+
+* This software is supplied by Renesas Electronics Corporation and is only 
+* intended for use with Renesas products. No other uses are authorized.
+
+* This software is owned by Renesas Electronics Corporation and is protected under 
+* all applicable laws, including copyright laws.
+
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES 
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, 
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY 
+* DISCLAIMED.
+
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES 
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS 
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+* Renesas reserves the right, without notice, to make changes to this 
+* software and to discontinue the availability of this software.  
+* By using this software, you agree to the additional terms and 
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+******************************************************************************/
+/* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.  */
+
+#include <string.h>
+#include "SDHSBlockDevice.h"
+#include "r_typedefs.h"
+#include "r_sd_cfg.h"
+#include "r_sdif.h"
+#include "pinmap.h"
+
+#include "dcache-control.h"
+
+#define SD_SECTOR_SIZE      (512)
+#define SD_RW_BUFF_SIZE     (1 * 1024)
+
+#if defined(__ICCARM__)
+#pragma data_alignment=32
+static uint8_t sd_work_hndl_buff[SD_SIZE_OF_INIT]@ ".mirrorram";
+#pragma data_alignment=32
+static uint8_t sd_work_rw_buff[SD_RW_BUFF_SIZE]@ ".mirrorram";
+#pragma data_alignment=32
+static uint8_t sd_work_buff[SD_SECTOR_SIZE];
+#else
+static uint8_t sd_work_hndl_buff[SD_SIZE_OF_INIT]__attribute((section("NC_BSS"),aligned(32)));
+static uint8_t sd_work_rw_buff[SD_RW_BUFF_SIZE]__attribute((section("NC_BSS"),aligned(32)));
+static uint8_t sd_work_buff[SD_SECTOR_SIZE]__attribute((aligned(32)));
+#endif
+
+static const uint32_t sd_base_addr[2] = {
+     SD_CFG_IP0_BASE
+    ,SD_CFG_IP1_BASE
+};
+
+SDHSBlockDevice::SDHSBlockDevice(PinName cd, PinName wp) : sd_ch(-1)
+{
+    /* Initialize SD driver. */
+    static const PinMap PinMap_SD_CD[] = {
+    //   pin      ch     func
+        {P6_4   , 1    , 5},
+        {P5_4   , 1    , 3},
+        {PC_6   , 1    , 4},
+        {P5_0   , 1    , 4},
+        {NC     , NC   , 0}
+    };
+
+    static const PinMap PinMap_SD_WP[] = {
+    //   pin      ch     func
+        {P9_7   , 1    , 5},
+        {PC_7   , 1    , 4},
+        {P5_1   , 1    , 4},
+        {P5_5   , 1    , 3},
+        {NC     , NC   , 0}
+    };
+
+    int32_t sd_cd = pinmap_peripheral(cd, PinMap_SD_CD);
+    int32_t sd_wp = pinmap_peripheral(wp, PinMap_SD_WP);
+    int32_t chk;
+
+    sd_info.type = SD_MEDIA_UNKNOWN;
+    sd_info.iswp = SD_WP_OFF;
+
+    if (sd_cd == NC) {
+        sd_ch = -1;
+        return;
+    }
+
+    if (sd_wp != NC) {
+        pinmap_pinout(wp, PinMap_SD_WP);
+    }
+
+    sd_ch = sd_cd;
+    pinmap_pinout(cd, PinMap_SD_CD);
+    chk = sd_init((int32_t)sd_ch, sd_base_addr[sd_ch], sd_work_hndl_buff, SD_CD_SOCKET);
+    if (chk != SD_OK) {
+        sd_ch = -1;
+        return;
+    }
+    /* Set the card detect interrupt. */
+    chk = sd_cd_int(sd_ch, SD_CD_INT_ENABLE, NULL);
+    if (chk != SD_OK) {
+        sd_ch = -1;
+        return;
+    }
+    /* Register callback function. */
+    chk = sd_set_intcallback(sd_ch, &SD_status_callback_function);
+    if (chk != SD_OK){
+        sd_ch = -1;
+        return;
+    }
+    chk = sd_set_dma_intcallback(sd_ch, &SD_dma_end_callback_function);
+    if (chk != SD_OK){
+        sd_ch = -1;
+        return;
+    }
+    /* Initialize SD driver work buffer. */
+    chk = sd_set_buffer(sd_ch, sd_work_rw_buff, SD_RW_BUFF_SIZE);
+    if (chk != SD_OK) {
+        sd_ch = -1;
+        return;
+    }
+}
+
+SDHSBlockDevice::~SDHSBlockDevice()
+{
+    deinit();
+}
+
+bool SDHSBlockDevice::is_connect() {
+    if (sd_check_media(sd_ch) == SD_OK) {
+        return true;
+    }
+    return false;
+}
+
+int SDHSBlockDevice::init()
+{
+    int32_t     chk;
+    uint16_t    type;
+
+    lock();
+
+    if (sd_ch < 0){
+        unlock();
+        return BD_ERROR_DEVICE_ERROR;
+    }
+
+    /* Initialize card information. */
+    sd_info.type = SD_MEDIA_UNKNOWN;
+    sd_info.iswp = SD_WP_OFF;
+
+    /* Check if the card is inserted. */
+    chk = sd_check_media(sd_ch);
+    if (chk != SD_OK) {
+        unlock();
+        return BD_ERROR_DEVICE_ERROR;
+    } else {
+        /* Mount SD card. */
+        chk = sd_mount(sd_ch, SD_CFG_DRIVER_MODE, SD_VOLT_3_3);
+        if (chk != SD_OK) {
+            unlock();
+            return BD_ERROR_DEVICE_ERROR;
+        }
+        /* Get the card type. */
+        chk = sd_get_type(sd_ch, &type, NULL, NULL);
+        if (chk != SD_OK) {
+            unlock();
+            return BD_ERROR_DEVICE_ERROR;
+        }
+        sd_info.type = type;
+        /* Get write protected information. */
+        chk = sd_iswp(sd_ch);
+        if (chk == SD_ERR) {
+            unlock();
+            return BD_ERROR_DEVICE_ERROR;
+        }
+        sd_info.iswp = chk;
+    }
+
+    unlock();
+    return BD_ERROR_OK;
+}
+
+int SDHSBlockDevice::deinit()
+{
+    if (sd_ch < 0){
+        return BD_ERROR_DEVICE_ERROR;
+    }
+
+    sd_unmount(sd_ch);
+    sd_finalize(sd_ch);
+    sd_info.type = SD_MEDIA_UNKNOWN;
+    sd_info.iswp = SD_WP_OFF;
+
+    return BD_ERROR_OK;
+}
+
+bd_size_t SDHSBlockDevice::get_read_size() const
+{
+    return SD_SECTOR_SIZE;
+}
+
+bd_size_t SDHSBlockDevice::get_program_size() const
+{
+    return SD_SECTOR_SIZE;
+}
+
+bd_size_t SDHSBlockDevice::size() const
+{
+    uint32_t size = 0;
+
+    if (sd_ch < 0){
+        return 0;
+    }
+    sd_get_size(sd_ch, &size, NULL);
+
+    return (bd_size_t)(size * SD_SECTOR_SIZE);
+}
+
+const char *SDHSBlockDevice::get_type() const
+{
+    if (sd_info.type == SD_MEDIA_MMC) {
+        return "MMC";
+    } else {
+        return "SD";
+    }
+}
+
+int SDHSBlockDevice::read(void *b, bd_addr_t addr, bd_size_t size)
+{
+    MBED_ASSERT(is_valid_read(addr, size));
+
+    int32_t  chk;
+    uint32_t psn = (addr / SD_SECTOR_SIZE);
+    int32_t  sec_cnt = (size / SD_SECTOR_SIZE);
+
+    if (sd_ch < 0){
+        return BD_ERROR_DEVICE_ERROR;
+    }
+
+    if (sec_cnt == 0) {
+        return BD_ERROR_OK;
+    }
+
+    if (((uint32_t)b & 0x0000001F) == 0) {
+        // aligned 32
+        dcache_invalid((uint8_t *)b, size);
+        lock();
+        chk = sd_read_sect(sd_ch, (uint8_t *)b, psn, sec_cnt);
+        if (chk != SD_OK) {
+            unlock();
+            return BD_ERROR_DEVICE_ERROR;
+        }
+        unlock();
+    } else {
+        // not aligned 32
+        if (sec_cnt >= 3) {
+            dcache_invalid((uint8_t *)((uint32_t)b + SD_SECTOR_SIZE), (sec_cnt - 2) * SD_SECTOR_SIZE);
+        }
+
+        lock();
+        dcache_invalid(sd_work_buff, SD_SECTOR_SIZE);
+        chk = sd_read_sect(sd_ch, sd_work_buff, psn, 1);
+        if (chk != SD_OK) {
+            unlock();
+            return BD_ERROR_DEVICE_ERROR;
+        }
+        memcpy((uint8_t *)b, sd_work_buff, SD_SECTOR_SIZE);
+        b = (void *)((uint32_t)b + SD_SECTOR_SIZE);
+        psn++;
+        sec_cnt--;
+
+        if (sec_cnt >= 2) {
+            chk = sd_read_sect(sd_ch, (uint8_t *)b, psn, sec_cnt - 1);
+            if (chk != SD_OK) {
+                unlock();
+                return BD_ERROR_DEVICE_ERROR;
+            }
+            b = (void *)((uint32_t)b + (SD_SECTOR_SIZE * (sec_cnt - 1)));
+            psn += (sec_cnt - 1);
+            sec_cnt = 1;
+        }
+
+        if (sec_cnt >= 1) {
+            dcache_invalid(sd_work_buff, SD_SECTOR_SIZE);
+            chk = sd_read_sect(sd_ch, sd_work_buff, psn, 1);
+            if (chk != SD_OK) {
+                unlock();
+                return BD_ERROR_DEVICE_ERROR;
+            }
+            memcpy((uint8_t *)b, sd_work_buff, SD_SECTOR_SIZE);
+        }
+        unlock();
+    }
+
+    return BD_ERROR_OK;
+}
+
+int SDHSBlockDevice::program(const void *b, bd_addr_t addr, bd_size_t size)
+{
+    MBED_ASSERT(is_valid_program(addr, size));
+
+    int32_t  chk;
+    uint32_t psn = (addr / SD_SECTOR_SIZE);
+    int32_t  sec_cnt = (size / SD_SECTOR_SIZE);
+
+    if (sd_ch < 0){
+        return BD_ERROR_DEVICE_ERROR;
+    }
+
+    if (sd_info.iswp != SD_WP_OFF) {
+        return BD_ERROR_DEVICE_ERROR;
+    }
+
+    if (sec_cnt == 0) {
+        return BD_ERROR_OK;
+    }
+
+    if (((uint32_t)b & 0x0000001F) == 0) {
+        // aligned 32
+        dcache_clean((uint8_t *)b, size);
+        lock();
+        chk = sd_write_sect(sd_ch, (uint8_t *)b, psn, sec_cnt, SD_WRITE_OVERWRITE);
+        if (chk != SD_OK) {
+            unlock();
+            return BD_ERROR_DEVICE_ERROR;
+        }
+        unlock();
+    } else {
+        // not aligned 32
+        if (sec_cnt >= 3) {
+            dcache_clean((uint8_t *)((uint32_t)b + SD_SECTOR_SIZE), (sec_cnt - 2) * SD_SECTOR_SIZE);
+        }
+
+        lock();
+        memcpy(sd_work_buff, (uint8_t *)b, SD_SECTOR_SIZE);
+        dcache_clean(sd_work_buff, SD_SECTOR_SIZE);
+        chk = sd_write_sect(sd_ch, sd_work_buff, psn, 1, SD_WRITE_OVERWRITE);
+        if (chk != SD_OK) {
+            unlock();
+            return BD_ERROR_DEVICE_ERROR;
+        }
+        b = (void *)((uint32_t)b + SD_SECTOR_SIZE);
+        psn++;
+        sec_cnt--;
+
+        if (sec_cnt >= 2) {
+            chk = sd_write_sect(sd_ch, (uint8_t *)b, psn, sec_cnt - 1, SD_WRITE_OVERWRITE);
+            if (chk != SD_OK) {
+                unlock();
+                return BD_ERROR_DEVICE_ERROR;
+            }
+            b = (void *)((uint32_t)b + (SD_SECTOR_SIZE * (sec_cnt - 1)));
+            psn += (sec_cnt - 1);
+            sec_cnt = 1;
+        }
+
+        if (sec_cnt >= 1) {
+            memcpy(sd_work_buff, (uint8_t *)b, SD_SECTOR_SIZE);
+            dcache_clean(sd_work_buff, SD_SECTOR_SIZE);
+            chk = sd_write_sect(sd_ch, sd_work_buff, psn, 1, SD_WRITE_OVERWRITE);
+            if (chk != SD_OK) {
+                unlock();
+                return BD_ERROR_DEVICE_ERROR;
+            }
+        }
+        unlock();
+    }
+
+    return BD_ERROR_OK;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/SDHSBlockDevice.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,132 @@
+/******************************************************************************
+* DISCLAIMER
+
+* This software is supplied by Renesas Electronics Corporation and is only 
+* intended for use with Renesas products. No other uses are authorized.
+
+* This software is owned by Renesas Electronics Corporation and is protected under 
+* all applicable laws, including copyright laws.
+
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES 
+* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, 
+* INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
+* PARTICULAR PURPOSE AND NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY 
+* DISCLAIMED.
+
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS 
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE 
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES 
+* FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS 
+* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+* Renesas reserves the right, without notice, to make changes to this 
+* software and to discontinue the availability of this software.  
+* By using this software, you agree to the additional terms and 
+* conditions found by accessing the following link:
+* http://www.renesas.com/disclaimer
+******************************************************************************/
+/* Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.  */
+
+#ifndef SDHS_BLOCK_DEVICE_H
+#define SDHS_BLOCK_DEVICE_H
+
+#include "BlockDevice.h"
+#include "platform/platform.h"
+#include "platform/PlatformMutex.h"
+
+
+/** SDHSBlockDevice class
+ *
+ * Access an SD Card using SD bus
+ */
+class SDHSBlockDevice : public BlockDevice
+{
+public:
+
+    /** Constructor
+     *
+     *  @param cd       SD card detection pin
+     *  @param wp       Write protection signal pin
+     */
+    SDHSBlockDevice(PinName cd, PinName wp);
+    virtual ~SDHSBlockDevice();
+
+    bool is_connect();
+
+    /** Initialize a block device
+     *
+     *  @return         0 on success or a negative error code on failure
+     */
+    virtual int init();
+
+    /** Deinitialize a block device
+     *
+     *  @return         0 on success or a negative error code on failure
+     */
+    virtual int deinit();
+
+    /** Read blocks from a block device
+     *
+     *  @param buffer   Buffer to read blocks into
+     *  @param addr     Address of block to begin reading from
+     *  @param size     Size to read in bytes, must be a multiple of read block size
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int read(void *buffer, bd_addr_t addr, bd_size_t size);
+
+    /** Program blocks to a block device
+     *
+     *  The blocks must have been erased prior to being programmed
+     *
+     *  @param buffer   Buffer of data to write to blocks
+     *  @param addr     Address of block to begin writing to
+     *  @param size     Size to write in bytes, must be a multiple of program block size
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int program(const void *buffer, bd_addr_t addr, bd_size_t size);
+
+    /** Get the size of a readable block
+     *
+     *  @return         Size of a readable block in bytes
+     */
+    virtual bd_size_t get_read_size() const;
+
+    /** Get the size of a programable block
+     *
+     *  @return         Size of a programable block in bytes
+     */
+    virtual bd_size_t get_program_size() const;
+
+    /** Get the total size of the underlying device
+     *
+     *  @return         Size of the underlying device in bytes
+     */
+    virtual bd_size_t size() const;
+
+    /** Get the BlockDevice class type.
+     *
+     *  @return         A string representation of the BlockDevice class type.
+     */
+    virtual const char *get_type() const;
+
+private:
+    typedef struct {
+        uint16_t type;
+        int32_t  iswp;
+    } SD_INFO;
+
+    int32_t sd_ch;
+    SD_INFO sd_info;
+    PlatformMutex _mutex;
+
+    virtual void lock()
+    {
+        _mutex.lock();
+    }
+
+    virtual void unlock()
+    {
+        _mutex.unlock();
+    }
+};
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/inc/r_sd_cfg.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,151 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver Sample Program
+* File Name    : r_sd_cfg.h
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : SD Memory card driver configuration
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+#ifndef R_SD_CFG_H
+#define R_SD_CFG_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ------------------------------------------------------
+  Set SDHI Base Address
+--------------------------------------------------------*/
+#define SD_CFG_IP0_BASE      (SD_SCC_IP0_BASE_ADDR)      /* Set the base address of SCC ch0. */
+#define SD_CFG_IP1_BASE      (SD_SCC_IP1_BASE_ADDR)      /* Set the base address of SCC ch1. */
+
+/* ------------------------------------------------------
+  Set the method of check SD Status
+--------------------------------------------------------*/
+#define SD_CFG_HWINT
+/* #define SD_CFG_POLL */
+
+/* ------------------------------------------------------
+  Set the method of data transfer
+--------------------------------------------------------*/
+#define SD_CFG_TRNS_DMA
+/* #define SD_CFG_TRNS_SW */
+
+/* ------------------------------------------------------
+  Set the card type to support
+--------------------------------------------------------*/
+#define SD_CFG_MEM
+
+/* ------------------------------------------------------
+  Set the version to support
+--------------------------------------------------------*/
+/* #define SD_CFG_VER1X */            /* Version 1.1 */
+#define SD_CFG_VER2X            /* Version 2.x */
+
+/* ------------------------------------------------------
+  Set the method to detect card
+--------------------------------------------------------*/
+#define SD_CFG_CD_INT
+
+#ifdef SD_CFG_CD_INT
+    #ifndef SD_CFG_HWINT
+        #error    please define SD_CFG_HWINT
+    #endif
+#endif
+
+/* ==== end of the setting ==== */
+#if    defined(SD_CFG_HWINT)
+    #if    defined(SD_CFG_TRNS_DMA)
+            #if    defined(SD_CFG_VER2X)
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X)
+            #else
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_HWINT|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X)
+            #endif
+    #else
+            #if    defined(SD_CFG_VER2X)
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X)
+            #else
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_HWINT|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X)
+            #endif
+    #endif
+#else
+    #if    defined(SD_CFG_TRNS_DMA)
+            #if    defined(SD_CFG_VER2X)
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X)
+            #else
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_POLL|SD_MODE_DMA|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X)
+            #endif
+    #else
+            #if    defined(SD_CFG_VER2X)
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER2X)
+            #else
+
+                /* configuration driver mode */
+                #define SD_CFG_DRIVER_MODE     (SD_MODE_POLL|SD_MODE_SW|SD_MODE_MEM|SD_MODE_DS|SD_MODE_VER1X)
+            #endif
+    #endif
+#endif    
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+#endif /* R_SD_CFG_H    */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/inc/r_sdhi_simplified_drv_sc_cfg.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,157 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/**********************************************************************************************************************
+* File Name    : r_sdhi_simplified_drv_sc_cfg.h
+* Version      : 1.20
+* Device(s)    : R7S921053
+* Description  : SDHI Configuration.
+* Creation Date: 2019-05-29
+ *********************************************************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#if(1) /* mbed */
+#else
+#include "r_gpio_drv_api.h"
+#include "r_gpio_drv_sc_cfg.h"
+#endif
+#include "r_sdif.h"
+
+#ifndef SRC_RENESAS_CONFIG_R_SDHI_SIMPLIFIED_DRV_SC_CFG_H_
+#define SRC_RENESAS_CONFIG_R_SDHI_SIMPLIFIED_DRV_SC_CFG_H_
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef enum
+{
+    SD_CB_UNUSED,               /*!< SD card detection callback function setting is unused */
+    SD_CB_USED,                 /*!< SD card detection callback function setting is used */
+} e_sd_cb_layout_t;
+
+typedef struct
+{
+    e_sd_cd_layout_t  cd;       /*!< SD card detection option */
+    e_sd_wp_layout_t  wp;       /*!< SD write protection signal detection option */
+    e_sd_cb_layout_t  cb;       /*!< SD card detection callback function setting */
+    p_intCallbackFunc cb_func;  /*!< SD card detection callback function */
+} st_sdhi_config_t;
+
+/**
+ * @typedef st_r_drv_sdhi_sc_config_t Smart Configurator Interface
+ */
+typedef struct
+{
+    int_t                           channel;
+    st_sdhi_config_t                config;
+#if(1) /* mbed */
+#else
+    st_r_drv_gpio_pin_init_table_t  pin;
+#endif
+} st_r_drv_sdhi_sc_config_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+#if(1) /* mbed */
+#else
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/* This code is auto-generated. Do not edit manually */
+extern int32_t fat_sample_cd_int_cb_function(int32_t sd_port, int32_t cd);
+/* End of modification */
+#if defined(__cplusplus)
+}
+#endif
+#endif
+
+/**
+ * @section SDHI_SC_TABLE Smart Configurator settings table.
+ */
+#if(1) /* mbed */
+static const st_r_drv_sdhi_sc_config_t SDHI_SC_TABLE[] =
+{
+    /* This code is auto-generated. Do not edit manually */
+    { 0, 
+        {
+            SD_CD_ENABLED, 
+            SD_WP_ENABLED, 
+            SD_CB_UNUSED, 
+            NULL, 
+        }
+    },
+    { 1, 
+        {
+            SD_CD_ENABLED, 
+#if defined(TARGET_RZ_A2M_SBEV)
+            SD_WP_DISABLED, 
+#else
+            SD_WP_ENABLED, 
+#endif
+            SD_CB_UNUSED, 
+            NULL, 
+        }
+    },
+    /* End of modification */
+};
+#else
+static const st_r_drv_sdhi_sc_config_t SDHI_SC_TABLE[] =
+{
+    /* This code is auto-generated. Do not edit manually */
+    { 0, 
+        {
+            SD_CD_ENABLED, 
+            SD_WP_ENABLED, 
+            SD_CB_USED, 
+            fat_sample_cd_int_cb_function, 
+        }, 
+        {
+            &GPIO_SC_TABLE_sdhi_simplified0[0], 
+            sizeof(GPIO_SC_TABLE_sdhi_simplified0)/sizeof(st_r_drv_gpio_sc_config_t), 
+        }
+    },
+    { 1, 
+        {
+            SD_CD_ENABLED, 
+            SD_WP_ENABLED, 
+            SD_CB_UNUSED, 
+            NULL, 
+        }, 
+        {
+            &GPIO_SC_TABLE_sdhi_simplified1[0], 
+            sizeof(GPIO_SC_TABLE_sdhi_simplified1)/sizeof(st_r_drv_gpio_sc_config_t), 
+        }
+    },
+    /* End of modification */
+};
+#endif
+
+
+#endif /* SRC_RENESAS_CONFIG_R_SDHI_SIMPLIFIED_DRV_SC_CFG_H_ */
+
+/**********************************************************************************************************************
+End  Of File
+**********************************************************************************************************************/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/inc/r_sdif.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1046 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : r_sdif.h
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : SD Memory card driver I/F
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02     Support for OS
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+#ifndef R_SDIF_H
+#define R_SDIF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef    __cplusplus
+extern "C" {
+#endif    /* __cplusplus    */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ==== define  ==== */
+#define SD_SCC_IP0_BASE_ADDR      (0xE8227000uL)        /* Set the base address of SCC ch0. */
+#define SD_SCC_IP1_BASE_ADDR      (0xE8229000uL)        /* Set the base address of SCC ch1. */
+
+/* ---- SD Driver work buffer ---- */
+#define SD_SIZE_OF_INIT           (240)
+
+/* ---- error code ---- */
+#define SD_OK_LOCKED_CARD         (1)                   /* OK but card is locked status */
+#define SD_OK                     (0)                   /* OK */
+#define SD_ERR                    (-1)                  /* general error */
+#define SD_ERR_WP                 (-2)                  /* write protect error */
+/* 3 */
+#define SD_ERR_RES_TOE            (-4)                  /* response time out error */
+#define SD_ERR_CARD_TOE           (-5)                  /* card time out error */
+#define SD_ERR_END_BIT            (-6)                  /* end bit error */
+#define SD_ERR_CRC                (-7)                  /* CRC error */
+#define SD_ERR_ILL_ACCESS         (-8)                  /* illegal access error */
+#define SD_ERR_HOST_TOE           (-9)                  /* host time out error */
+#define SD_ERR_CARD_ERASE         (-10)                 /* card erase error */
+#define SD_ERR_CARD_LOCK          (-11)                 /* card lock error */
+#define SD_ERR_CARD_UNLOCK        (-12)                 /* card unlock error */
+#define SD_ERR_HOST_CRC           (-13)                 /* host CRC error */
+#define SD_ERR_CARD_ECC           (-14)                 /* card internal ECC error */
+#define SD_ERR_CARD_CC            (-15)                 /* card internal error */
+#define SD_ERR_CARD_ERROR         (-16)                 /* unknown card error */
+#define SD_ERR_CARD_TYPE          (-17)                 /* non support card type */
+#define SD_ERR_NO_CARD            (-18)                 /* no card */
+#define SD_ERR_ILL_READ           (-19)                 /* illegal buffer read */
+#define SD_ERR_ILL_WRITE          (-20)                 /* illegal buffer write */
+#define SD_ERR_AKE_SEQ            (-21)                 /* the sequence of authentication process */
+#define SD_ERR_OVERWRITE          (-22)                 /* CID/CSD overwrite error */
+/* 23-29 */
+#define SD_ERR_CPU_IF             (-30)                 /* target CPU interface function error  */
+#define SD_ERR_STOP               (-31)                 /* user stop */
+/* 32-49 */
+#define SD_ERR_CSD_VER            (-50)                 /* CSD register version error */
+/* 51 */
+#define SD_ERR_FILE_FORMAT        (-52)                 /* CSD register file format error  */
+#define SD_ERR_NOTSUP_CMD         (-53)                 /* not supported command  */
+/* 54-69 */
+#define SD_ERR_IFCOND_VER         (-70)                 /* Interface condition version error */
+/* 71 */
+#define SD_ERR_IFCOND_ECHO        (-72)                 /* Interface condition echo back pattern error */
+/* 73-79 */
+#define SD_ERR_OUT_OF_RANGE       (-80)                 /* the argument was out of range */
+#define SD_ERR_ADDRESS_ERROR      (-81)                 /* misassigned address */
+#define SD_ERR_BLOCK_LEN_ERROR    (-82)                 /* transfered block length is not allowed */
+#define SD_ERR_ILLEGAL_COMMAND    (-83)                 /* Command not legal  */
+#define SD_ERR_RESERVED_ERROR18   (-84)                 /* Reserved bit 18 Error */
+#define SD_ERR_RESERVED_ERROR17   (-85)                 /* Reserved bit 17 Error */
+#define SD_ERR_CMD_ERROR          (-86)                 /* SD_INFO2 bit  0 CMD error */
+#define SD_ERR_CBSY_ERROR         (-87)                 /* SD_INFO2 bit 14 CMD Type Reg Busy error */
+#define SD_ERR_NO_RESP_ERROR      (-88)                 /* SD_INFO1 bit  0 No Response error */
+/* 89-98 */
+#define SD_ERR_INTERNAL           (-99)                 /* driver software internal error */
+
+/* ---- driver mode ---- */
+#define SD_MODE_POLL              (0x0000ul)            /* status check mode is software polling */
+#define SD_MODE_HWINT             (0x0001ul)            /* status check mode is hardware interrupt */
+#define SD_MODE_SW                (0x0000ul)            /* data transfer mode is software */
+#define SD_MODE_DMA               (0x0002ul)            /* data transfer mode is DMA */
+
+/* ---- support mode ---- */
+#define SD_MODE_MEM               (0x0000ul)            /* memory cards only are supported */
+#define SD_MODE_DS                (0x0000ul)            /* only default speed mode is supported */
+#define SD_MODE_VER1X             (0x0000ul)            /* ver1.1 host */
+#define SD_MODE_VER2X             (0x0080ul)            /* ver2.x host (high capacity and dual voltage) */
+#define SD_MODE_1BIT              (0x0100ul)            /* SD Mode 1bit only is supported */
+#define SD_MODE_4BIT              (0x0000ul)            /* SD Mode 1bit and 4bit is supported */
+
+/* ---- media voltage ---- */
+#define SD_VOLT_1_7               (0x00000010ul)        /* low voltage card minimum */
+#define SD_VOLT_1_8               (0x00000020ul)
+#define SD_VOLT_1_9               (0x00000040ul)
+#define SD_VOLT_2_0               (0x00000080ul)
+#define SD_VOLT_2_1               (0x00000100ul)        /* basic communication minimum */
+#define SD_VOLT_2_2               (0x00000200ul)
+#define SD_VOLT_2_3               (0x00000400ul)
+#define SD_VOLT_2_4               (0x00000800ul)
+#define SD_VOLT_2_5               (0x00001000ul)
+#define SD_VOLT_2_6               (0x00002000ul)
+#define SD_VOLT_2_7               (0x00004000ul)
+#define SD_VOLT_2_8               (0x00008000ul)        /* memory access minimum */
+#define SD_VOLT_2_9               (0x00010000ul)
+#define SD_VOLT_3_0               (0x00020000ul)
+#define SD_VOLT_3_1               (0x00040000ul)
+#define SD_VOLT_3_2               (0x00080000ul)
+#define SD_VOLT_3_3               (0x00100000ul)
+#define SD_VOLT_3_4               (0x00200000ul)
+#define SD_VOLT_3_5               (0x00400000ul)
+#define SD_VOLT_3_6               (0x00800000ul)
+
+/* ---- memory card write mode ---- */
+#define SD_WRITE_WITH_PREERASE    (0x0000u)             /* pre-erease write */
+#define SD_WRITE_OVERWRITE        (0x0001u)             /* overwrite  */
+
+/* ---- media type ---- */
+#define SD_MEDIA_UNKNOWN          (0x0000u)             /* unknown media */
+#define SD_MEDIA_MMC              (0x0010u)             /* MMC card */
+#define SD_MEDIA_SD               (0x0020u)             /* SD Memory card */
+#define SD_MEDIA_MEM              (0x0030u)             /* Memory card */
+
+/* ---- write protect info --- */
+#define SD_WP_OFF                 (0x0000u)             /* card is not write protect */
+#define SD_WP_HW                  (0x0001u)             /* card is H/W write protect */
+#define SD_WP_TEMP                (0x0002u)             /* card is TEMP_WRITE_PROTECT */
+#define SD_WP_PERM                (0x0004u)             /* card is PERM_WRITE_PROTECT */
+#define SD_WP_ROM                 (0x0010u)             /* card is SD-ROM */
+
+/* ---- SD clock div ---- */    /* IMCLK is host controller clock */
+#define SD_DIV_512                (0x0080u)             /* SDCLOCK = IMCLK/512 */
+#define SD_DIV_256                (0x0040u)             /* SDCLOCK = IMCLK/256 */
+#define SD_DIV_128                (0x0020u)             /* SDCLOCK = IMCLK/128 */
+#define SD_DIV_64                 (0x0010u)             /* SDCLOCK = IMCLK/64 */
+#define SD_DIV_32                 (0x0008u)             /* SDCLOCK = IMCLK/32 */
+#define SD_DIV_16                 (0x0004u)             /* SDCLOCK = IMCLK/16 */
+#define SD_DIV_8                  (0x0002u)             /* SDCLOCK = IMCLK/8 */
+#define SD_DIV_4                  (0x0001u)             /* SDCLOCK = IMCLK/4 */
+#define SD_DIV_2                  (0x0000u)             /* SDCLOCK = IMCLK/2 */
+#define SD_DIV_1                  (0x00FFu)             /* SDCLOCK = IMCLK (option) */
+
+/* ---- SD clock define ---- */    /* max frequency */
+#define SD_CLK_400KHZ             (0x0000u)             /* 400kHz */
+#define SD_CLK_1MHZ               (0x0001u)             /* 1MHz */
+#define SD_CLK_5MHZ               (0x0002u)             /* 5MHz */
+#define SD_CLK_10MHZ              (0x0003u)             /* 10MHz */
+#define SD_CLK_20MHZ              (0x0004u)             /* 20MHz */
+#define SD_CLK_25MHZ              (0x0005u)             /* 25MHz */
+#define SD_CLK_50MHZ              (0x0006u)             /* 50MHz (phys spec ver1.10) */
+
+/* ---- speed class ---- */
+#define SD_SPEED_CLASS_0          (0x00u)               /* not defined, or less than ver2.0 */
+#define SD_SPEED_CLASS_2          (0x01u)               /* 2MB/sec */
+#define SD_SPEED_CLASS_4          (0x02u)               /* 4MB/sec */
+#define SD_SPEED_CLASS_6          (0x03u)               /* 6MB/sec */
+
+/* ---- SD port mode ---- */
+#define SD_PORT_SERIAL            (0x0000u)             /* 1bit mode */
+#define SD_PORT_PARALLEL          (0x0001u)             /* 4bits mode */
+
+/* ---- SD Card detect port ---- */
+#define SD_CD_SOCKET              (0x0000u)             /* CD pin */
+#define SD_CD_DAT3                (0x0001u)             /* DAT3 pin */
+
+/* ---- SD Card detect interrupt ---- */
+#define SD_CD_INT_DISABLE         (0x0000u)             /* card detect interrupt disable */
+#define SD_CD_INT_ENABLE          (0x0001u)             /* card detect interrupt enable */
+
+/* ---- lock/unlock mode ---- */
+#define SD_FORCE_ERASE            (0x08)
+#define SD_LOCK_CARD              (0x04)
+#define SD_UNLOCK_CARD            (0x00)
+#define SD_CLR_PWD                (0x02)
+#define SD_SET_PWD                (0x01)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* ---- User Configuration ---- */
+/* SD card detection option */
+typedef enum
+{
+    SD_CD_ENABLED,      /* SD card detection is enabled. */
+    SD_CD_DISABLED      /* When SD card detection is disabled,
+                           the status is always loading. */
+} e_sd_cd_layout_t;
+
+/* SD write protection signal detection option */
+typedef enum
+{
+    SD_WP_ENABLED,      /* Write protection signal detection is enabled. */
+    SD_WP_DISABLED      /* When write protection signal detection is disabled,
+                           the status is always write protection signal off. */
+} e_sd_wp_layout_t;
+
+typedef int32_t (*p_intCallbackFunc)(int32_t sd_port, int32_t cd);
+typedef int32_t (*p_fmtCallbackFunc)(uint32_t secno, uint32_t size);
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+/* ==== API prototype ===== */
+/* ---- access library I/F ---- */
+/* Function Name: sd_init */
+/**************************************************************************//**
+ * @fn            int32_t sd_init(int32_t sd_port, uint32_t base, void *workarea, int32_t cd_port)
+ * @brief         initialize SD Driver (more than 2ports). <br>
+ *                initialize SD Driver work memory started from SDHI register
+ *                base <br>
+ *                address specified by argument (base) <br>
+ *                initialize port specified by argument (cd_port) <br>
+ *                work memory is allocated octlet boundary
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    uint32_t base   : SDHI register base address
+ * @param [in]    void *workarea  : SD Driver work memory
+ * @param [in]    int32_t cd_port : card detect port <br>
+ *                  SD_CD_SOCKET  : card detect by CD pin <br>
+ *                  SD_CD_DAT3    : card detect by DAT3 pin
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ * @retval        SD_ERR_CPU_IF : CPU-IF function error
+ *****************************************************************************/
+int32_t sd_init(int32_t sd_port, uint32_t base, void *workarea, int32_t cd_port);
+
+/* Function Name: sd_cd_int */
+/**************************************************************************//**
+ * @fn            int32_t sd_cd_int(int32_t sd_port, int32_t enable, int32_t (*callback)(int32_t, int32_t))
+ * @brief         set card detect interrupt <br>
+ *                if select SD_CD_INT_ENABLE, detect interrupt is enbled and
+ *                it is possible register callback function <br>
+ *                if select SD_CD_INT_DISABLE, detect interrupt is disabled
+ * @warning       .
+ * @param [in]    int32_t sd_port               : channel no (0 or 1)
+ * @param [in]    int32_t enable                : is enable or disable card detect interrupt?
+ * @param [in]    int32_t (*callback)(int32_t, int32_t)
+ *                                              : interrupt callback function
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_cd_int(int32_t sd_port, int32_t enable, int32_t (*callback)(int32_t, int32_t));
+
+/* Function Name: sd_check_media */
+/**************************************************************************//**
+ * @fn            int32_t sd_check_media(int32_t sd_port)
+ * @brief         check card insertion <br>
+ *                if card is inserted, return SD_OK <br>
+ *                if card is not inserted, return SD_ERR <br>
+ *                if SD handle is not initialized, return SD_ERR
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK  : card is inserted
+ * @retval        SD_ERR : card is not inserted
+ *****************************************************************************/
+int32_t sd_check_media(int32_t sd_port);
+
+/* Function Name: sd_mount */
+/**************************************************************************//**
+ * @fn            int32_t sd_mount(int32_t sd_port, uint32_t mode, uint32_t voltage)
+ * @brief         mount SD card. <br>
+ *                mount SD memory card user area
+ *                can be access user area after this function is finished
+ *                without errors <br>
+ *                turn on power <br>
+ * <br>
+ *                following is available SD Driver mode <br>
+ *                SD_MODE_POLL     : software polling <br>
+ *                SD_MODE_HWINT    : hardware interrupt <br>
+ *                SD_MODE_SW       : software data transfer (SD_BUF) <br>
+ *                SD_MODE_DMA      : DMA data transfer (SD_BUF) <br>
+ *                SD_MODE_MEM      : only memory cards <br>
+ *                SD_MODE_DS       : only default speed <br>
+ *                SD_MODE_VER1X    : ver1.1 host <br>
+ *                SD_MODE_VER2X    : ver2.x host
+ * @warning       user area should be mounted
+ * @param [in]    int32_t sd_port  : channel no (0 or 1)
+ * @param [in]    uint32_t mode    : SD Driver operation mode
+ * @param [in]    uint32_t voltage : operation voltage
+ * @retval        p_hndl->error    : SD handle error value
+ * @retval        SD_OK : end of succeed
+ * @retval        other : end of error
+ *****************************************************************************/
+int32_t sd_mount(int32_t sd_port, uint32_t mode, uint32_t voltage);
+
+/* Function Name: sd_read_sect */
+/**************************************************************************//**
+ * @fn            int32_t sd_read_sect(int32_t sd_port, uint8_t *buff, uint32_t psn, int32_t cnt)
+ * @brief         read sector data from card. <br>
+ *                read sector data from physical sector number (=psn) by the
+ *                number of sectors (=cnt) <br>
+ *                if SD Driver mode is SD_MODE_SW, data transfer by
+ *                sddev_read_data function <br>
+ *                if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [out]   uint8_t *buff   : read data buffer
+ * @param [in]    uint32_t psn    : read physical sector number
+ * @param [in]    int32_t cnt     : number of read sectors
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_read_sect(int32_t sd_port, uint8_t *buff, uint32_t psn, int32_t cnt);
+
+/* Function Name: sd_write_sect */
+/**************************************************************************//**
+ * @fn            int32_t sd_write_sect(int32_t sd_port, uint8_t *buff, uint32_t psn, int32_t cnt, int32_t writemode)
+ * @brief         write sector data to card. <br>
+ *                write sector data from physical sector number (=psn) by the
+ *                number of sectors (=cnt) <br>
+ *                if SD Driver mode is SD_MODE_SW, data transfer by
+ *                sddev_read_data function <br>
+ *                if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * @warning       .
+ * @param [in]    int32_t sd_port   : channel no (0 or 1).
+ * @param [out]   uint8_t *buff     : write data buffer
+ * @param [in]    uint32_t psn      : write physical sector number
+ * @param [in]    int32_t cnt       : number of write sectors
+ * @param [in]    int32_t writemode : memory card write mode <br>
+ *                  SD_WRITE_WITH_PREERASE : pre-erease write <br>
+ *                  SD_WRITE_OVERWRITE     : overwrite
+ * @retval        SD_OK  : end of succeed.
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_write_sect(int32_t sd_port, uint8_t *buff, uint32_t psn, int32_t cnt, int32_t writemode);
+
+/* Function Name: sd_get_type */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_type(int32_t sd_port, uint16_t *type, uint16_t *speed, uint8_t *capa)
+ * @brief         get card type. <br>
+ *                get mounting card type, current and supported speed mode
+ *                and capacity type <br>
+ *                (if SD memory card) <br>
+ *                following card types are defined <br>
+ *                SD_MEDIA_UNKNOWN : unknown media <br>
+ *                SD_MEDIA_MMC     : MMC card <br>
+ *                SD_MEDIA_SD      : SD Memory card
+ * @warning       if pointer has NULL ,the value isn't returned <br>
+ *                only SD memory card, speed mode has meaning
+ * @param [in]    int32_t  sd_port : channel no (0 or 1)
+ * @param [out]   uint16_t *type   : mounting card type
+ * @param [out]   uint16_t *speed  : speed mode
+ * @param [out]   uint8_t  *capa   : card capacity <br>
+ *                  Standard capacity : 0, High capacity : 1
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_type(int32_t sd_port, uint16_t *type, uint16_t *speed, uint8_t *capa);
+
+/* Function Name: sd_get_size */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_size(int32_t sd_port, uint32_t *user, uint32_t *protect)
+ * @brief         get card size. <br>
+ *                get total sectors of user area calculated from CSD <br>
+ *                get total sectors of protect area calculated from CSD and
+ *                SD STAUS
+ * @warning       if pointer has NULL ,the value isn't returned <br>
+ *                return just the number of all sectors <br>
+ *                only SD memory card, protect area size has meaning
+ * @param [in]    int32_t sd_port   : channel no (0 or 1)
+ * @param [out]   uint32_t *user    : user area size
+ * @param [out]   uint32_t *protect : protect area size
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_size(int32_t sd_port, uint32_t *user, uint32_t *protect);
+
+/* Function Name: sd_iswp */
+/**************************************************************************//**
+ * @fn            int32_t sd_iswp(int32_t sd_port)
+ * @brief         check hardware write protect. <br>
+ *                check hardware write protect refer to SDHI register <br>
+ *                if WP pin is disconnected to SDHI, return value has no
+ *                meaning
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        p_hndl->write_protect : write protected state
+ *****************************************************************************/
+int32_t sd_iswp(int32_t sd_port);
+
+/* Function Name: sd_unmount */
+/**************************************************************************//**
+ * @fn            int32_t sd_unmount(int32_t sd_port)
+ * @brief         unmount card. <br>
+ *                turn off power
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t sd_unmount(int32_t sd_port);
+
+/* Function Name: sd_stop */
+/**************************************************************************//**
+ * @fn            void    sd_stop(int32_t sd_port);
+ * @brief         stop operations compulsory. <br>
+ *                set flag (=SD handle member stop) stop operations compulsory <br>
+ *                if this flag is set, read, write operations is stopped <br>
+ *                this flag is used for card detect/removal interrupt detection
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        none
+ *****************************************************************************/
+void    sd_stop(int32_t sd_port);
+
+/* Function Name: sd_set_intcallback */
+/**************************************************************************//**
+ * @fn            int32_t sd_set_intcallback(int32_t sd_port, int32_t (*callback)(int32_t, int32_t))
+ * @brief         register SD_INFO1 or SD_INFO2 interrupt callback function. <br>
+ *                register callback function <br>
+ *                if SD_INFO1 or SD_INFO2 interrupt are occured, call callback
+ *                function
+ * @warning       .
+ * @param [in]    int32_t sd_port                       : channel no (0 or 1)
+ * @param [in]    int32_t (*callback)(int32_t, int32_t) : callback function
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_set_intcallback(int32_t sd_port, int32_t (*callback)(int32_t, int32_t));
+
+/* Function Name: sd_set_dma_intcallback */
+/**************************************************************************//**
+ * @fn            int32_t sd_set_dma_intcallback(int32_t sd_port, int32_t (*callback)(int32_t, int32_t))
+ * @brief         register DM_CM_INFO1 or DM_CM_INFO2 interrupt callback function. <br>
+ *                register callback function <br>
+ *                if DM_CM_INFO1 or DM_CM_INFO2 interrupt are occured, call callback
+ *                function
+ * @warning       .
+ * @param [in]    int32_t sd_port                       : channel no (0 or 1)
+ * @param [in]    int32_t (*callback)(int32_t, int32_t) : callback function
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_set_dma_intcallback(int32_t sd_port, int32_t (*callback)(int32_t, int32_t));
+
+/* Function Name: sd_int_handler */
+/**************************************************************************//**
+ * @fn            void    sd_int_handler(int32_t sd_port)
+ * @brief         SD_INFO1 and SD_INFO2 interrupt handler <br>
+ *                examine the relevant elements (without masked) <br>
+ *                save those elements to int_info1 or int_info2 <br>
+ *                if a callback function is registered, call it
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        none
+ *****************************************************************************/
+void    sd_int_handler(int32_t sd_port);
+
+/* Function Name: sd_get_error */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_error(int32_t sd_port)
+ * @brief         get SD Driver errors (=p_hndl->error) and return it
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        p_hndl->error
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_error(int32_t sd_port);
+
+/* Function Name: sd_check_int */
+/**************************************************************************//**
+ * @fn            int32_t sd_check_int(int32_t sd_port)
+ * @brief         check SD_INFO1 and SD_INFO2 interrupt elements <br>
+ *                if any interrupt is detected, return SD_OK <br>
+ *                if no interrupt is detected, return SD_ERR
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_check_int(int32_t sd_port);
+
+/* Function Name: sd_int_dm_handler */
+/**************************************************************************//**
+ * @fn            void    sd_int_dm_handler(int32_t sd_port)
+ * @brief         DM_CM_INFO1 and DM_CM_INFO2 interrupt handler <br>
+ *                examine the relevant elements (without masked) <br>
+ *                save those elements to int_dm_info1 or int_dm_info2 <br>
+ *                if a callback function is registered, call it
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        none
+ *****************************************************************************/
+void    sd_int_dm_handler(int32_t sd_port);
+
+/* Function Name: sd_check_int_dm */
+/**************************************************************************//**
+ * @fn            int32_t sd_check_int_dm(int32_t sd_port)
+ * @brief         check DM_CM_INFO1 and DM_CM_INFO2 interrupt elements <br>
+ *                if any interrupt is detected, return SD_OK <br>
+ *                if no interrupt is detected, return SD_ERR
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK  : any interrupt occured
+ * @retval        SD_ERR : no interrupt occured
+ *****************************************************************************/
+int32_t sd_check_int_dm(int32_t sd_port);
+
+/* Function Name: sd_get_reg */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_reg(int32_t sd_port, uint8_t *ocr, uint8_t *cid,
+ *                      uint8_t *csd, uint8_t *dsr, uint8_t *scr)
+ * @brief         get card register. <br>
+ *                get card register value
+ * @warning       if pointer has NULL ,the register value isn't returned
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [out]   uint8_t *ocr    : OCR register address
+ * @param [out]   uint8_t *cid    : CID register address
+ * @param [out]   uint8_t *csd    : CSD register address
+ * @param [out]   uint8_t *dsr    : DSR register address
+ * @param [out]   uint8_t *scr    : SCR register address
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_reg(int32_t sd_port, uint8_t *ocr, uint8_t *cid, uint8_t *csd, uint8_t *dsr, uint8_t *scr);
+
+/* Function Name: sd_get_rca */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_rca(int32_t sd_port, uint8_t *rca)
+ * @brief         get rca register. <br>
+ *                get card register value
+ * @warning       if pointer has NULL ,the register value isn't returned
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [out]   uint8_t *rca    : RCA register address
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_rca(int32_t sd_port, uint8_t *rca);
+
+/* Function Name: sd_get_sdstatus */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_sdstatus(int32_t sd_port, uint8_t *sdstatus)
+ * @brief         get SD Status register value
+ * @warning       if pointer has NULL ,the register value isn't returned
+ * @param [in]    int32_t sd_port   : channel no (0 or 1)
+ * @param [out]   uint8_t *sdstatus : SD STATUS address
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_sdstatus(int32_t sd_port, uint8_t *sdstatus);
+
+/* Function Name: sd_get_speed */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_speed(int32_t sd_port, uint8_t *clss, uint8_t *move)
+ * @brief         get card speed. <br>
+ *                get card speed class and performance move
+ * @warning       if pointer has NULL ,the register value isn't returned
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [out]   uint8_t *clss   : speed class
+ * @param [out]   uint8_t *move   : performance move
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_speed(int32_t sd_port, uint8_t *clss, uint8_t *move);
+
+/* Function Name: sd_finalize */
+/**************************************************************************//**
+ * @fn            int32_t sd_finalize(int32_t sd_port)
+ * @brief         do finish operation of SD Driver (2ports). <br>
+ *                finish SD Driver <br>
+ *                reset SDHI include card detection/removal
+ * @warning       after this function finished, SD handle is unavailable
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_finalize(int32_t sd_port);
+
+/* Function Name: sd_set_seccnt */
+/**************************************************************************//**
+ * @fn            int32_t sd_set_seccnt(int32_t sd_port, int16_t sectors)
+ * @brief         set maximum block count per multiple command
+ * @warning       maximam block count is constrained from 3 to 32767(0x7fff)
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int16_t sectors : block count
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_set_seccnt(int32_t sd_port, int16_t sectors);
+
+/* Function Name: sd_get_seccnt */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_seccnt(int32_t sd_port)
+ * @brief         get block count. <br>
+ *                get maximum block count per multiple command
+ * @warning       maximam block count are constrained from 1 to 65535
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        not less than 0 : block count
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_seccnt(int32_t sd_port);
+
+/* Function Name: sd_get_ver */
+/**************************************************************************//**
+ * @fn            int32_t sd_get_ver(int32_t sd_port, uint16_t *sdhi_ver, char_t *sddrv_ver)
+ * @brief         get SDHI and SD Driver versions. <br>
+ *                get SDHI version from VERSION register <br>
+ *                get SD Driver version from constant DRIVER NAME
+ * @warning       if pointer has NULL ,the value isn't returned
+ * @param [in]    int32_t sd_port    : channel no (0 or 1)
+ * @param [out]   uint16_t *sdhi_ver : SDHI version
+ * @param [out]   char_t *sddrv_ver  : SD Driver version
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_get_ver(int32_t sd_port, uint16_t *sdhi_ver, char_t *sddrv_ver);
+
+/* Function Name: sd_set_cdtime */
+/**************************************************************************//**
+ * @fn            int32_t sd_set_cdtime(int32_t sd_port, uint16_t cdtime)
+ * @brief         set card detect time. <br>
+ *                set card detect time equal to IMCLK*2^(10+cdtime)
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    uint16_t cdtime : card detect time interval
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_set_cdtime(int32_t sd_port, uint16_t cdtime);
+
+/* Function Name: sd_set_responsetime */
+/**************************************************************************//**
+ * @fn            int32_t sd_set_responsetime(int32_t sd_port, uint16_t responsetime)
+ * @brief         set response timeout. <br>
+ *                set response timeout equal to IMCLK*2^(13+cdtime)
+ * @warning       .
+ * @param [in]    int32_t sd_port       : channel no (0 or 1)
+ * @param [in]    uint16_t responsetime : response timeout interval
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_set_responsetime(int32_t sd_port, uint16_t responsetime);
+
+/* Function Name: sd_set_buffer */
+/**************************************************************************//**
+ * @fn            int32_t sd_set_buffer(int32_t sd_port, void *buff, uint32_t size)
+ * @brief         initialize SD driver work buffer. <br>
+ *                this buffer is used for mainly MKB process
+ * @warning       if applied to CPRM, allocating more than 8K bytes
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    void *buff      : work buffer address
+ * @param [in]    uint32_t size   : work buffer size
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_set_buffer(int32_t sd_port, void *buff, uint32_t size);
+
+/* Function Name: sd_standby */
+/**************************************************************************//**
+ * @fn            int32_t sd_standby(int32_t sd_port)
+ * @brief         transfer card to stand-by state. <br>
+ *                transfer card from transfer state to stand-by state
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_standby(int32_t sd_port);
+
+/* Function Name: sd_active */
+/**************************************************************************//**
+ * @fn            int32_t sd_active(int32_t sd_port)
+ * @brief         transfer card to transfer state. <br>
+ *                transfer card from stand-by state to transfer state
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_active(int32_t sd_port);
+
+/* Function Name: sd_inactive */
+/**************************************************************************//**
+ * @fn            int32_t sd_inactive(int32_t sd_port)
+ * @brief         transfer card to inactive state. <br>
+ *                transfer card from any state to inactive state
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_inactive(int32_t sd_port);
+
+/* Function Name: sd_reget_reg */
+/**************************************************************************//**
+ * @fn            int32_t sd_reget_reg(int32_t sd_port, uint8_t *reg, int32_t is_csd)
+ * @brief         reget register. <br>
+ *                reget CID or CSD
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [out]   uint8_t *reg    : reget CID or CSD register address
+ * @param [in]    int32_t is_csd  : CID(=0) or CSD(=1)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_reget_reg(int32_t sd_port, uint8_t *reg, int32_t is_csd);
+
+/* Function Name: sd_set_tmpwp */
+/**************************************************************************//**
+ * @fn            int32_t sd_set_tmpwp(int32_t sd_port, int32_t is_set)
+ * @brief         set tempolary write protect. <br>
+ *                set temporary write protect programing csd
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int32_t is_set  : set or clear
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_set_tmpwp(int32_t sd_port, int32_t is_set);
+
+/* Function Name: sd_lock_unlock */
+/**************************************************************************//**
+ * @fn            int32_t sd_lock_unlock(int32_t sd_port, uint8_t code, uint8_t *pwd, uint8_t len)
+ * @brief         lock/unlock. <br>
+ *                lock/unlock operation <br>
+ *                passward length is up to 16 bytes <br>
+ *                case of cahnge passward, total length is 32 bytes,that is
+ *                old and new passward maximum length
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    uint8_t code    : operation code
+ * @param [in]    uint8_t *pwd    : passward
+ * @param [in]    uint8_t len     : passward length
+ * @retval        SD_OK  : end of succeed.
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t sd_lock_unlock(int32_t sd_port, uint8_t code, uint8_t *pwd, uint8_t len);
+
+/* ---- target CPU I/F ---- */
+/* Function Name: sddev_init */
+/**************************************************************************//**
+ * @fn            int32_t sddev_init(int32_t sd_port)
+ * @brief         Initialize H/W to use SDHI
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_init(int32_t sd_port);
+
+/* Function Name: sddev_power_on */
+/**************************************************************************//**
+ * @fn            int32_t sddev_power_on(int32_t sd_port)
+ * @brief         Power-on H/W to use SDHI
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_power_on(int32_t sd_port);
+
+/* Function Name: sddev_power_off */
+/**************************************************************************//**
+ * @fn            int32_t sddev_power_off(int32_t sd_port)
+ * @brief         Power-off H/W to use SDHI
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_power_off(int32_t sd_port);
+
+/* Function Name: sddev_read_data */
+/**************************************************************************//**
+ * @fn            int32_t sddev_read_data(int32_t sd_port, uint8_t *buff, uint32_t reg_addr, int32_t num)
+ * @brief         read from SDHI buffer FIFO
+ * @warning       .
+ * @param [in]    int32_t sd_port   : channel no (0 or 1)
+ * @param [out]   uint8_t *buff     : buffer addrees to store reading datas
+ * @param [in]    uint32_t reg_addr : SDIP FIFO address
+ * @param [in]    int32_t num       : counts to read(unit : byte)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_read_data(int32_t sd_port, uint8_t *buff, uint32_t reg_addr, int32_t num);
+
+/* Function Name: sddev_write_data */
+/**************************************************************************//**
+ * @fn            int32_t sddev_write_data(int32_t sd_port, uint8_t *buff, uint32_t reg_addr, int32_t num)
+ * @brief         write to SDHI buffer FIFO
+ * @warning       .
+ * @param [in]    int32_t sd_port   : channel no (0 or 1)
+ * @param [in]    uint8_t *buff     : buffer addrees to store writting datas
+ * @param [in]    uint32_t reg_addr : SDIP FIFO address
+ * @param [in]    int32_t num       : counts to write(unit : byte)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_write_data(int32_t sd_port, uint8_t *buff, uint32_t reg_addr, int32_t num);
+
+/* Function Name: sddev_get_clockdiv */
+/**************************************************************************//**
+ * @fn            uint32_t sddev_get_clockdiv(int32_t sd_port, int32_t clock)
+ * @brief         Get clock div value.
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int32_t clock   : request clock frequency <br>
+ *                  SD_CLK_50MHZ <br>
+ *                  SD_CLK_25MHZ <br>
+ *                  SD_CLK_20MHZ <br>
+ *                  SD_CLK_10MHZ <br>
+ *                  SD_CLK_5MHZ <br>
+ *                  SD_CLK_1MHZ <br>
+ *                  SD_CLK_400KHZ
+ * @retval        clock div value <br>
+ *                  SD_DIV_4   : 1/4   clock <br>
+ *                  SD_DIV_8   : 1/8   clock <br>
+ *                  SD_DIV_16  : 1/16  clock <br>
+ *                  SD_DIV_32  : 1/32  clock <br>
+ *                  SD_DIV_256 : 1/256 clock <br>
+ *                  SD_DIV_512 : 1/512 clock
+ *****************************************************************************/
+uint32_t sddev_get_clockdiv(int32_t sd_port, int32_t clock);
+
+/* Function Name: sddev_set_port */
+/**************************************************************************//**
+ * @fn            int32_t sddev_set_port(int32_t sd_port, int32_t mode)
+ * @brief         setting ports to use SDHI
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int32_t mode    : SD_PORT_PARALLEL : 4bit mode <br>
+ *                                : SD_PORT_SERIAL   : 1bit mode
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_set_port(int32_t sd_port, int32_t mode);
+
+/* Function Name: sddev_int_wait */
+/**************************************************************************//**
+ * @fn            int32_t sddev_int_wait(int32_t sd_port, int32_t time)
+ * @brief         Waitting for SDHI Interrupt
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int32_t time    : time out value to wait interrupt
+ * @retval        get interrupt : SD_OK
+ * @retval        time out      : SD_ERR
+ *****************************************************************************/
+int32_t sddev_int_wait(int32_t sd_port, int32_t time);
+
+/* Function Name: sddev_init_dma */
+/**************************************************************************//**
+ * @fn            int32_t sddev_init_dma(int32_t sd_port, uint32_t buff, int32_t dir)
+ * @brief         Initialize DMAC to transfer data from SDHI FIFO
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    uint32_t buff   : buffer addrees to transfer datas
+ * @param [in]    int32_t dir     : direction to transfer <br>
+ *                                :   0 : FIFO -> buffer <br>
+ *                                :   1 : buffer -> FIFO
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_init_dma(int32_t sd_port, uint32_t buff, int32_t dir);
+
+/* Function Name: sddev_wait_dma_end */
+/**************************************************************************//**
+ * @fn            int32_t sddev_wait_dma_end(int32_t sd_port, int32_t cnt)
+ * @brief         Wait to complete DMAC transfer
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int32_t cnt     : counts to transfer(unit : byte)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_wait_dma_end(int32_t sd_port, int32_t cnt);
+
+/* Function Name: sddev_disable_dma */
+/**************************************************************************//**
+ * @fn            int32_t sddev_disable_dma(int32_t sd_port)
+ * @brief         Disable DMAC transfer
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_disable_dma(int32_t sd_port);
+
+/* Function Name: sddev_reset_dma */
+/**************************************************************************//**
+ * @fn            int32_t sddev_reset_dma(int32_t sd_port)
+ * @brief         Reset of the SDHI module built-in DMAC.
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_reset_dma(int32_t sd_port);
+
+/* Function Name: sddev_finalize_dma */
+/**************************************************************************//**
+ * @fn            int32_t sddev_finalize_dma(int32_t sd_port)
+ * @brief         Finalize of the SDHI module built-in DMAC.
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_finalize_dma(int32_t sd_port);
+
+/* Function Name: sddev_finalize */
+/**************************************************************************//**
+ * @fn            int32_t sddev_finalize(int32_t sd_port)
+ * @brief         finalize SDHI
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_finalize(int32_t sd_port);
+
+/* Function Name: sddev_loc_cpu */
+/**************************************************************************//**
+ * @fn            int32_t sddev_loc_cpu(int32_t sd_port)
+ * @brief         lock cpu to disable interrupt
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_loc_cpu(int32_t sd_port);
+
+/* Function Name: sddev_unl_cpu */
+/**************************************************************************//**
+ * @fn            int32_t sddev_unl_cpu(int32_t sd_port)
+ * @brief         unlock cpu to enable interrupt
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_unl_cpu(int32_t sd_port);
+
+/* Function Name: sddev_cd_layout */
+/**************************************************************************//**
+ * @fn            int32_t sddev_cd_layout(int32_t sd_port)
+ * @brief         CD Terminal Support Confirmation
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        Support     : SD_OK
+ * @retval        Not Support : SD_ERR
+ *****************************************************************************/
+int32_t sddev_cd_layout(int32_t sd_port);
+
+/* Function Name: sddev_wp_layout */
+/**************************************************************************//**
+ * @fn            int32_t sddev_wp_layout(int32_t sd_port)
+ * @brief         WP Terminal Support Confirmation
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        Support     : SD_OK
+ * @retval        Not Support : SD_ERR
+ *****************************************************************************/
+int32_t sddev_wp_layout(int32_t sd_port);
+
+/* Function Name: sddev_get_sc_table_config_ch */
+/******************************************************************************
+ * @fn            int32_t sddev_get_sc_table_config_ch(int32_t sd_port, int32_t *p_sc_port)
+ * @brief         Get the channel number of the table generated by the smart
+ *                configurator.
+ * @warning       .
+ * @param [in]    int32_t sd_port    : channel no (0 or 1)
+ * @param [out]   int32_t *p_sc_port : pointer to sc channel no
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t sddev_get_sc_table_config_ch(int32_t sd_port, int32_t *p_sc_port);
+
+/* Function Name: SD_status_callback_function */
+/**************************************************************************//**
+ * @fn            int32_t SD_status_callback_function(int32_t sd_port, int32_t cd)
+ * @brief         Callback interrupt function for SDHI protocol status control
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int32_t cd      : no used
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t SD_status_callback_function(int32_t sd_port, int32_t cd);
+
+/* Function Name: SD_dma_end_callback_function */
+/**************************************************************************//**
+ * @fn            int32_t SD_dma_end_callback_function(int32_t sd_port, int32_t cd)
+ * @brief         Callback interrupt function for complete DMA transfer control
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @param [in]    int32_t cd      : no used
+ * @retval        success : SD_OK
+ * @retval        fail    : SD_ERR
+ *****************************************************************************/
+int32_t SD_dma_end_callback_function(int32_t sd_port, int32_t cd);
+
+/* Function Name: SD_confirm_semaphore */
+/**************************************************************************//**
+ * @fn            void    SD_confirm_semaphore(int32_t sd_port)
+ * @brief         Confirm semaphore status
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1)
+ * @retval        none
+ *****************************************************************************/
+void    SD_confirm_semaphore(int32_t sd_port);
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+#ifdef    __cplusplus
+}
+#endif    /* __cplusplus    */
+
+#endif    /* R_SDIF_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_cd.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,250 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_cd.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  :
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+ * Function Name: sd_cd_int
+ * Description  : set card detect interrupt
+ *              : if select SD_CD_INT_ENABLE, detect interrupt is enbled and
+ *              : it is possible register callback function
+ *              : if select SD_CD_INT_DISABLE, detect interrupt is disabled
+ * Arguments    : int32_t sd_port               : channel no (0 or 1)
+ *              : int32_t enable                : is enable or disable card detect interrupt?
+ *              : int32_t (*callback)(int32_t, int32_t)
+ *                                              : interrupt callback function
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_cd_int(int32_t sd_port, int32_t enable, int32_t (*callback)(int32_t, int32_t))
+{
+    uint64_t    info1;
+    st_sdhndl_t *p_hndl;
+    int32_t     layout;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+    if ((SD_CD_INT_ENABLE != enable) && (SD_CD_INT_DISABLE != enable))
+    {
+        return SD_ERR;  /* parameter error */
+    }
+
+    /* is change interrupt disable to enable? */
+    if ((p_hndl->int_info1_mask & (SD_INFO1_MASK_DET_DAT3 | SD_INFO1_MASK_DET_CD)) == 0)
+    {
+        sddev_loc_cpu(sd_port);
+
+        /* Cast to an appropriate type */
+        info1 = SD_INP(p_hndl, SD_INFO1) ;
+
+        /* Cast to an appropriate type */
+        info1 &= (uint64_t)~SD_INFO1_MASK_DET_DAT3_CD;
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_INFO1, info1); /* clear insert and remove bits */
+        sddev_unl_cpu(sd_port);
+    }
+
+    layout = sddev_cd_layout(sd_port);
+    if (SD_OK == layout)
+    {
+        if (SD_CD_INT_ENABLE == enable)
+        {
+            /* enable insert and remove interrupts */
+            if (SD_CD_SOCKET == p_hndl->cd_port)  /* CD */
+            {
+                /* Cast to an appropriate type */
+                _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DET_CD, 0);
+            }
+            else    /* DAT3 */
+            {
+                /* Cast to an appropriate type */
+                _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DET_DAT3, 0);
+            }
+        }
+        else    /* case SD_CD_INT_DISABLE */
+        {
+            /* disable insert and remove interrupts */
+            if (SD_CD_SOCKET == p_hndl->cd_port)  /* CD */
+            {
+                /* Cast to an appropriate type */
+                _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DET_CD, 0);
+            }
+            else    /* DAT3 */
+            {
+                /* Cast to an appropriate type */
+                _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DET_DAT3, 0);
+            }
+        }
+    }
+
+    /* ---- register callback function ---- */
+    p_hndl->int_cd_callback = callback;
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_cd_int
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_check_media
+ * Description  : check card insertion
+ *              : if card is inserted, return SD_OK
+ *              : if card is not inserted, return SD_ERR
+ *              : if SD handle is not initialized, return SD_ERR
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : card is inserted
+ *              : SD_ERR: card is not inserted
+ *****************************************************************************/
+int32_t sd_check_media(int32_t sd_port)
+{
+    st_sdhndl_t  *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    return _sd_check_media(p_hndl);
+}
+/******************************************************************************
+ End of function sd_check_media
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_check_media
+ * Description  : check card insertion
+ *              : if card is inserted, return SD_OK
+ *              : if card is not inserted, return SD_ERR
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : card is inserted
+ *              : SD_ERR: card is not inserted
+ *****************************************************************************/
+int32_t _sd_check_media(st_sdhndl_t *p_hndl)
+{
+    uint16_t reg;
+    int32_t  layout;
+
+    /* Cast to an appropriate type */
+    layout = sddev_cd_layout((int32_t)(p_hndl->sd_port));
+    if (SD_OK == layout)
+    {
+        /* Cast to an appropriate type */
+        reg = SD_INPLL(p_hndl, SD_INFO1);
+        if (SD_CD_SOCKET == p_hndl->cd_port)
+        {
+            /* Cast to an appropriate type */
+            reg &= (uint16_t)SD_INFO1_MASK_STATE_CD;    /* check CD level   */
+#if defined(TARGET_RZ_A2M_SBEV) /* mbed */
+            if ((reg & SD_INFO1_MASK_STATE_CD) == 0) {
+                reg |= SD_INFO1_MASK_STATE_CD;
+            } else {
+                reg &= ~SD_INFO1_MASK_STATE_CD;
+            }
+#endif
+        }
+        else
+        {
+            /* Cast to an appropriate type */
+            reg &= (uint16_t)SD_INFO1_MASK_STATE_DAT3;  /* check DAT3 level */
+        }
+    }
+    else
+    {
+        reg = SD_CD_DETECT;                             /* Always inserted */
+    }
+
+    if (reg)
+    {
+        return SD_OK;   /* inserted */
+    }
+
+    return SD_ERR;  /* no card */
+}
+/******************************************************************************
+ End of function _sd_check_media
+ *****************************************************************************/
+
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_cmd.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,855 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_cmd.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : command issue, response receive and register check
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+/* ==== response errors ==== */
+/* for internal error detail    */
+static const int32_t s_resp_err_tbl[] =
+{
+    SD_ERR_OUT_OF_RANGE,                /* b31 : OUT_OF_RANGE                   */
+    SD_ERR_ADDRESS_ERROR,               /* b30 : ADDRESS_ERROR                  */
+    SD_ERR_BLOCK_LEN_ERROR,             /* b29 : BLOCK_LEN_ERROR                */
+    SD_ERR_CARD_ERASE,                  /* b28 : ERASE_SEQ_ERROR                */
+    SD_ERR_CARD_ERASE,                  /* b27 : ERASE_PARAM                    */
+    SD_ERR_WP,                          /* b26 : WP_VIOLATION                   */
+    SD_ERR_CARD_LOCK,                   /* b25 : CARD_IS_LOCKED                 */
+    SD_ERR_CARD_UNLOCK,                 /* b24 : LOCK_UNLOCK_FAILED             */
+    SD_ERR_HOST_CRC,                    /* b23 : COM_CRC_ERROR                  */
+    SD_ERR_ILLEGAL_COMMAND,             /* b22 : ILLEGAL_COMMAND                */
+    SD_ERR_CARD_ECC,                    /* b21 : CARD_ECC_FAILED                */
+    SD_ERR_CARD_CC,                     /* b20 : CC_ERROR                       */
+    SD_ERR_CARD_ERROR,                  /* b19 : ERROR                          */
+    SD_ERR_RESERVED_ERROR18,            /* b18 : (reserved)                     */
+    SD_ERR_RESERVED_ERROR17,            /* b17 : (reserved)                     */
+    SD_ERR_OVERWRITE,                   /* b16 : CSD_OVERWRITE                  */
+};
+
+/* ==== SD_INFO2 errors table ==== */
+static const int32_t s_info2_err_tbl[] =
+{
+    SD_ERR_ILL_ACCESS,                  /* b15 : Illegal Access Error           */
+    SD_OK,                              /* b14 :                                */
+    SD_OK,                              /* b13 :                                */
+    SD_OK,                              /* b12 :                                */
+    SD_OK,                              /* b11 :                                */
+    SD_OK,                              /* b10 :                                */
+    SD_OK,                              /* b9  :                                */
+    SD_OK,                              /* b8  :                                */
+    SD_OK,                              /* b7  :                                */
+    SD_ERR_RES_TOE,                     /* b6  : Response Timeout               */
+    SD_ERR_ILL_READ,                    /* b5  : SD_BUF Illegal Read Access     */
+    SD_ERR_ILL_WRITE,                   /* b4  : SD_BUF Illegal Write Access    */
+    SD_ERR_CARD_TOE,                    /* b3  : Data Timeout                   */
+    SD_ERR_END_BIT,                     /* b2  : END Error                      */
+    SD_ERR_CRC,                         /* b1  : CRC Error                      */
+    SD_ERR_CMD_ERROR,                   /* b0  : CMD Error                      */
+};
+
+/* ==== transfer speed table ==== */
+static const uint16_t s_tran_speed[8] =
+{
+    1,      // 100kbit/s
+    10,     // 1Mbit/s
+    100,    // 10Mbit/s
+    1000,   // 100Mbit/s
+    1000,   // reserved
+    1000,   // reserved
+    1000,   // reserved
+    1000,   // reserved
+};
+static const uint8_t s_time_value[16] =
+{
+    0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80
+};
+
+static void _sd_get_info2(st_sdhndl_t *p_hndl);
+
+/******************************************************************************
+ * Function Name: _sd_send_cmd
+ * Description  : issue SD command, hearafter wait recive response
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint16_t cmd        : command code
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : not get response and check response errors
+ *****************************************************************************/
+int32_t _sd_send_cmd(st_sdhndl_t *p_hndl, uint16_t cmd)
+{
+    int32_t time;
+    int32_t i;
+
+    p_hndl->error = SD_OK;
+
+    if (CMD38 == cmd)   /* erase command */
+    {
+        time = SD_TIMEOUT_ERASE_CMD;    /* extend timeout 1 sec */
+    }
+    else if (ACMD46 == cmd) /* ACMD46 */
+    {
+        time = SD_TIMEOUT_MULTIPLE; /* same as write timeout */
+    }
+    else if (CMD7 == cmd)
+    {
+        time = SD_TIMEOUT_RESP; /* same as write timeout */
+    }
+    else if (CMD12 == cmd)
+    {
+        time = SD_TIMEOUT_RESP; /* same as write timeout */
+    }
+    else if (CMD43 == cmd)
+    {
+        time = SD_TIMEOUT_RESP;
+    }
+    else if (CMD44 == cmd)
+    {
+        time = SD_TIMEOUT_RESP;
+    }
+    else if (CMD45 == cmd)
+    {
+        time = SD_TIMEOUT_RESP;
+    }
+    else
+    {
+        time = SD_TIMEOUT_CMD;
+    }
+
+    /* enable resp end and illegal access interrupts *//* Cast to an appropriate type */
+    _sd_set_int_mask(p_hndl, SD_INFO1_MASK_RESP, 0);
+
+    for (i = 0; i < SCLKDIVEN_LOOP_COUNT; i++)
+    {
+
+        /* Cast to an appropriate type */
+        if (SD_INP(p_hndl, SD_INFO2) & SD_INFO2_MASK_SCLKDIVEN)
+        {
+            break;
+        }
+    }
+    if (SCLKDIVEN_LOOP_COUNT == i)
+    {
+        _sd_set_err(p_hndl, SD_ERR_CBSY_ERROR);       /* treate as CBSY ERROR */
+        return p_hndl->error;
+    }
+
+    /* ---- issue command ---- */
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_CMD, (uint64_t)cmd);
+
+    /* ---- wait resp end ---- */
+    if (sddev_int_wait(p_hndl->sd_port, time) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+
+        /* Cast to an appropriate type */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+        return p_hndl->error;
+    }
+
+    /* disable resp end and illegal access interrupts *//* Cast to an appropriate type */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+
+    _sd_get_info2(p_hndl);    /* get SD_INFO2 register */
+
+    _sd_check_info2_err(p_hndl);  /* check SD_INFO2 error bits */
+
+    /* Cast to an appropriate type */
+    if (!(p_hndl->int_info1 & SD_INFO1_MASK_RESP))
+    {
+        _sd_set_err(p_hndl, SD_ERR_NO_RESP_ERROR);    /* no response */
+    }
+
+    /* ---- clear previous errors ---- *//* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ERR);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_send_cmd
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_send_acmd
+ * Description  : issue application specific command, hearafter wait recive
+ *              : response
+ *              : issue CMD55 preceide application specific command
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint16_t cmd        : command code
+ *              : uint16_t h_arg      : command argument high [31:16]
+ *              : uint16_t l_arg      : command argument low [15:0]
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_send_acmd(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg,
+                        uint16_t l_arg)
+{
+    /* ---- issue CMD 55 ---- */
+    _sd_set_arg(p_hndl, p_hndl->rca[0], 0);
+    if (_sd_send_cmd(p_hndl, CMD55) != SD_OK)
+    {
+        return SD_ERR;
+    }
+
+    if (_sd_get_resp(p_hndl, SD_RSP_R1) != SD_OK)
+    {
+        return SD_ERR;
+    }
+
+    /* ---- issue ACMD ---- */
+    _sd_set_arg(p_hndl, h_arg, l_arg);
+    if (_sd_send_cmd(p_hndl, cmd) != SD_OK)
+    {
+        return SD_ERR;
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_send_acmd
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_send_mcmd
+ * Description  : issue multiple command (CMD18 or CMD25)
+ *              : wait response
+ *              : set read start address to startaddr
+ *              : after this function finished, start data transfer
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint16_t cmd        : command code (CMD18 or CMD25)
+ *              : uint32_t startaddr  : data address (command argument)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_send_mcmd(st_sdhndl_t *p_hndl, uint16_t cmd, uint32_t startaddr)
+{
+    int32_t i;
+
+    /* Cast to an appropriate type */
+    _sd_set_arg(p_hndl, (uint16_t)(startaddr >> 16), (uint16_t)startaddr);
+
+    for (i = 0; i < SCLKDIVEN_LOOP_COUNT; i++)
+    {
+
+        /* Cast to an appropriate type */
+        if (SD_INP(p_hndl, SD_INFO2) & SD_INFO2_MASK_SCLKDIVEN)
+        {
+            break;
+        }
+    }
+    if (SCLKDIVEN_LOOP_COUNT == i)
+    {
+        _sd_set_err(p_hndl, SD_ERR_CBSY_ERROR);       /* treate as CBSY ERROR */
+        return p_hndl->error;
+    }
+
+    /* ---- issue command ---- */
+    SD_OUTP(p_hndl, SD_CMD, (uint64_t)cmd);
+
+    /* ---- wait resp end ---- */
+    if (sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_CMD) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+        return p_hndl->error;
+    }
+
+    _sd_get_info2(p_hndl);    /* get SD_INFO2 register */
+
+    _sd_check_info2_err(p_hndl);  /* check SD_INFO2 error bits */
+
+    /* Cast to an appropriate type */
+    if (p_hndl->int_info1 & SD_INFO1_MASK_RESP)
+    {
+        if (!p_hndl->error)
+        {
+            _sd_get_resp(p_hndl, SD_RSP_R1); /* check R1 resp */
+        }
+    }
+    else
+    {
+        _sd_set_err(p_hndl, SD_ERR_NO_RESP_ERROR);    /* no response */
+    }
+
+    /* ---- clear previous errors ---- *//* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ERR);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_send_mcmd
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_card_send_cmd_arg
+ * Description  : issue general SD command.
+ *              : issue command specified cmd code
+ *              : get and check response
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint16_t cmd        : command code (CMD18 or CMD25)
+ *              : int32_t  resp       : command response
+ *              : uint16_t h_arg      : command argument high [31:16]
+ *              : uint16_t l_arg      : command argument low [15:0]
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_card_send_cmd_arg(st_sdhndl_t *p_hndl, uint16_t cmd, int32_t resp,
+                                uint16_t h_arg, uint16_t l_arg)
+{
+    int32_t ret;
+
+    _sd_set_arg(p_hndl, h_arg, l_arg);
+
+    /* ---- issue command ---- */
+    if (SD_OK == (ret = _sd_send_cmd(p_hndl, cmd)))
+    {
+        ret = _sd_get_resp(p_hndl, resp); /* get and check response */
+    }
+    return ret;
+}
+/******************************************************************************
+ End of function _sd_card_send_cmd_arg
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_set_arg
+ * Description  : set command argument to SDHI
+ *              : h_arg means higher 16bits [31:16] and  set SD_ARG0
+ *              : l_arg means lower 16bits [15:0] and set SD_ARG1
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint16_t h_arg      : command argument high [31:16]
+ *              : uint16_t l_arg      : command argument low [15:0]
+ * Return Value : none
+ * Remark       : SD_ARG0 and SD_ARG1 are like little endian order
+ *****************************************************************************/
+void _sd_set_arg(st_sdhndl_t *p_hndl, uint16_t h_arg, uint16_t l_arg)
+{
+    /* Cast to an appropriate type */
+    SD_OUTPLL(p_hndl, SD_ARG, l_arg);
+
+    /* Cast to an appropriate type */
+    SD_OUTPLL(p_hndl, SD_ARG1, h_arg);
+}
+/******************************************************************************
+ End of function _sd_set_arg
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_card_send_ocr
+ * Description  : get OCR register and check card operation voltage
+ *              : if type is SD_MEDIA_SD, issue ACMD41
+ *              : if type is SD_MEDIA_MMC, issue CMD1
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t type        : card type
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_card_send_ocr(st_sdhndl_t *p_hndl, int32_t type)
+{
+    int32_t ret;
+    int32_t i;
+    int32_t j = 0;
+
+    /* ===== distinguish card type issuing ACMD41 or CMD1 ==== */
+    for (i = 0; i < 200; i++)
+    {
+        switch (type)
+        {
+            case SD_MEDIA_SD:
+                if (SD_MODE_VER2X == p_hndl->sup_ver)
+                {
+                    if ( p_hndl->sd_spec & SD_SPEC_20 )
+                    {
+                        /* cmd8 have response   *//* set HCS bit */
+                        p_hndl->voltage |= 0x40000000;
+                    }
+                }
+
+                /* ---- issue ACMD41 ---- *//* Cast to an appropriate type */
+                ret = _sd_send_acmd(p_hndl, ACMD41, (uint16_t)(p_hndl->voltage >> 16), (uint16_t)p_hndl->voltage);
+                break;
+
+            case SD_MEDIA_MMC:  /* MMC */
+
+                /* ---- issue CMD1 ---- *//* Cast to an appropriate type */
+                _sd_set_arg(p_hndl, (uint16_t)(p_hndl->voltage >> 16), (uint16_t)p_hndl->voltage);
+                ret = _sd_send_cmd(p_hndl, CMD1);
+                break;
+
+            default:
+                p_hndl->resp_status = 0;
+
+                /* for internal error detail    */
+                /* but not need to change       */
+                p_hndl->error = SD_ERR_INTERNAL;
+                return SD_ERR;
+        }
+
+        if (SD_OK == ret)
+        {
+            _sd_get_resp(p_hndl, SD_RSP_R3); /* check R3 resp */
+
+            /* ---- polling busy bit ---- */
+            if (p_hndl->ocr[0] & 0x8000)  /* busy cleared */
+            {
+                break;
+            }
+            else
+            {
+                ret = SD_ERR;   /* busy */
+                sddev_int_wait(p_hndl->sd_port, 5);   /* add wait function because retry interval is too short */
+            }
+        }
+
+        /* if more than 3 times response timeout occured, retry stop quick distinction to MMC */
+        if (SD_ERR_RES_TOE == p_hndl->error)
+        {
+            ++j;
+            if (3 == j)
+            {
+                break;
+            }
+        }
+        else
+        {
+            j = 0;
+        }
+    }
+    return ret;
+}
+/******************************************************************************
+ End of function _sd_card_send_ocr
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_check_resp_error
+ * Description  : distinguish error bit from R1 response
+ *              : set the error bit to p_hndl->error
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : no error detected
+ *              : SD_ERR: any errors detected
+ *****************************************************************************/
+int32_t _sd_check_resp_error(st_sdhndl_t *p_hndl)
+{
+    uint16_t status;
+    int32_t  bit;
+
+
+    /* SD or MMC card */
+    status = (uint16_t)((p_hndl->resp_status >> 16 ) & 0xfdffu);
+
+    /* ---- search R1 error bit ---- */
+    bit = _sd_bit_search(status);
+
+    if ((-1) != bit)
+    {
+        /* R1 resp errors bits but for AKE_SEQ_ERROR */
+        _sd_set_err(p_hndl, s_resp_err_tbl[bit]);
+        return SD_ERR;
+    }
+    else if (p_hndl->resp_status & RES_AKE_SEQ_ERROR)
+    {
+        /* authentication process sequence error */
+        _sd_set_err(p_hndl, SD_ERR_AKE_SEQ);
+        return SD_ERR;
+    }
+    else
+    {
+        /* DO NOTHING */
+        ;
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_check_resp_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_get_resp
+ * Description  : get response and check response errors.
+ *              : get response value from RESP register
+ *              : R1, R2, R3,(R4, R5) and R6 types are available
+ *              : specify response type by the argument resp
+ *              : set response value to SD handle member
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t resp        : response type
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_get_resp(st_sdhndl_t *p_hndl, int32_t resp)
+{
+    uint32_t status;
+    uint16_t *p_ptr;
+
+    /* select RESP register depend on the response type */
+    switch (resp)
+    {
+        case SD_RSP_NON:   /* no response */
+
+            /* DO NOTHING */
+            ;
+            break;
+        case SD_RSP_R1:    /* nomal response (32bits length) */
+        case SD_RSP_R1B:   /* nomal response with an optional busy signal */
+
+            /* Cast to an appropriate type */
+            status = SD_INPLL(p_hndl, SD_RSP1);
+            status <<= 16;
+
+            /* Cast to an appropriate type */
+            status |= SD_INPLL(p_hndl, SD_RSP10);
+            p_hndl->resp_status = status;
+
+            if (status & 0xfdffe008)        /* ignore card locked status    */
+            {
+                /* any status error */
+                return _sd_check_resp_error(p_hndl);
+            }
+
+            break;
+
+        case SD_RSP_R1_SCR:    /* nomal response with an optional busy signal */
+
+            /* Cast to an appropriate type */
+            p_hndl->scr[0] = SD_INPLL(p_hndl, SD_RSP1);
+
+            /* Cast to an appropriate type */
+            p_hndl->scr[1] = SD_INPLL(p_hndl, SD_RSP10);
+            break;
+
+        case SD_RSP_R2_CID:    /* CID register (128bits length) */
+            p_ptr = p_hndl->cid;
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP7);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP76);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP5);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP54);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP3);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP32);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP1);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP10);
+            break;
+
+        case SD_RSP_R2_CSD:    /* CSD register (128bits length) */
+            p_ptr = p_hndl->csd;
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP7);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP76);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP5);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP54);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP3);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP32);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP1);
+
+            /* Cast to an appropriate type */
+            *p_ptr++ = SD_INPLL(p_hndl, SD_RSP10);
+            break;
+
+        case SD_RSP_R3:    /* OCR register (32bits length) */
+
+            /* Cast to an appropriate type */
+            p_hndl->ocr[0] = SD_INPLL(p_hndl, SD_RSP1);
+
+            /* Cast to an appropriate type */
+            p_hndl->ocr[1] = SD_INPLL(p_hndl, SD_RSP10);
+            break;
+
+        case SD_RSP_R6:        /* Published RCA response (32bits length) */
+
+            /* Cast to an appropriate type */
+            p_hndl->rca[0] = SD_INPLL(p_hndl, SD_RSP1);
+
+            /* Cast to an appropriate type */
+            p_hndl->rca[1] = SD_INPLL(p_hndl, SD_RSP10);
+            break;
+
+        case SD_RSP_R7:       /* IF_COND response */
+
+            /* Cast to an appropriate type */
+            p_hndl->if_cond[0] = SD_INPLL(p_hndl, SD_RSP1);
+
+            /* Cast to an appropriate type */
+            p_hndl->if_cond[1] = SD_INPLL(p_hndl, SD_RSP10);
+            break;
+
+        default:
+
+            /* unknown type */
+            p_hndl->resp_status = 0;
+            p_hndl->error = SD_ERR_INTERNAL;
+            return SD_ERR;
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_get_resp
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_check_csd
+ * Description  : check CSD register and get following information
+ *              : Transfer Speed
+ *              : Command Class
+ *              : Read Block Length
+ *              : Copy Bit
+ *              : Write Protect Bit
+ *              : File Format Group
+ *              : Number of Erase Sector
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_check_csd(st_sdhndl_t *p_hndl)
+{
+    uint32_t transpeed;
+    uint32_t timevalue;
+    uint32_t erase_sector_size;
+    uint32_t erase_group_size;
+
+    /* ---- CSD Structure ---- */
+    if (SD_MEDIA_MMC == p_hndl->media_type)
+    {
+        p_hndl->csd_structure = 0;
+    }
+    else
+    {
+        /* Cast to an appropriate type */
+        p_hndl->csd_structure = (uint8_t)((p_hndl->csd[0] & 0x00c0u) >> 6u);
+        if ( 1 == p_hndl->csd_structure )
+        {
+            if ((SD_SPEC_10 == p_hndl->sd_spec) || (SD_SPEC_11 == p_hndl->sd_spec))
+            {
+                /* if csd_structure is ver1.00 or 1.10, sd_spec has to be phys spec ver1.00 or 1.10 */
+                _sd_set_err(p_hndl, SD_ERR_CSD_VER);
+                return SD_ERR;
+            }
+        }
+    }
+
+    /* ---- TAAC/NSAC ---- */
+    /* no check, to be obsolete */
+
+    /* ---- TRAN_SPEED  ---- */
+    transpeed = (p_hndl->csd[2] & 0x0700u) >> 8u;
+    timevalue = (p_hndl->csd[2] & 0x7800u) >> 11u;
+
+    /* Cast to an appropriate type */
+    transpeed = (uint32_t)(s_tran_speed[transpeed] * s_time_value[timevalue]);
+
+    /* ---- set transfer speed (memory access) ---- */
+    if (transpeed >= 5000)
+    {
+        p_hndl->csd_tran_speed = SD_CLK_50MHZ;
+    }
+    else if (transpeed >= 2500)
+    {
+        p_hndl->csd_tran_speed = SD_CLK_25MHZ;
+    }
+    else if (transpeed >= 2000)
+    {
+        p_hndl->csd_tran_speed = SD_CLK_20MHZ;
+    }
+    else if (transpeed >= 1000)
+    {
+        p_hndl->csd_tran_speed = SD_CLK_10MHZ;
+    }
+    else if (transpeed >= 500)
+    {
+        p_hndl->csd_tran_speed = SD_CLK_5MHZ;
+    }
+    else if (transpeed >= 100)
+    {
+        p_hndl->csd_tran_speed = SD_CLK_1MHZ;
+    }
+    else
+    {
+        p_hndl->csd_tran_speed = SD_CLK_400KHZ;
+    }
+
+    /* ---- CCC  ---- */
+    p_hndl->csd_ccc = (uint16_t)(((p_hndl->csd[2] & 0x00ffu) << 4u) |
+                                ((p_hndl->csd[3] & 0xf000u) >> 12u));
+
+
+    /* ---- COPY ---- */
+    p_hndl->csd_copy = (uint8_t)(p_hndl->csd[7] & 0x0040u);
+
+    /* ---- PERM/TMP_WRITE_PROTECT ---- */
+    p_hndl->write_protect |= (uint8_t)((p_hndl->csd[7] & 0x0030u) >> 3u);
+
+    /* ---- FILE_FORMAT ---- */
+    p_hndl->csd_file_format = (uint8_t)(p_hndl->csd[7] & 0x008cu);
+    if (p_hndl->csd_file_format & 0x80u)
+    {
+        _sd_set_err(p_hndl, SD_ERR_FILE_FORMAT);
+        return SD_ERR;
+    }
+
+    /* ---- calculate the number of erase sectors ---- */
+    if (p_hndl->media_type & SD_MEDIA_SD)
+    {
+        erase_sector_size = ((p_hndl->csd[5] & 0x003fu) << 1u) |
+                            ((p_hndl->csd[6] & 0x8000) >> 15);
+        erase_group_size = (p_hndl->csd[6] & 0x7f00u) >> 8u;
+    }
+    else
+    {
+        erase_sector_size = (p_hndl->csd[5] & 0x007cu) >> 2u;
+        erase_group_size = ((p_hndl->csd[5] & 0x0003u) << 3u) |
+                            ((p_hndl->csd[6] & 0xe000u) >> 13u);
+    }
+    p_hndl->erase_sect = (erase_sector_size + 1) * (erase_group_size + 1);
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_check_csd
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_check_info2_err
+ * Description  : check SD_INFO2 register errors.
+ *              : check error bit of SD_INFO2 register
+ *              : set the error bit to p_hndl->error
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_check_info2_err(st_sdhndl_t *p_hndl)
+{
+    uint16_t info2;
+    int32_t  bit;
+
+    /* Cast to an appropriate type */
+    info2 = (uint16_t)(p_hndl->int_info2 & SD_INFO2_MASK_ERR);
+
+    /* ---- search error bit ---- */
+    bit = _sd_bit_search(info2);
+
+    if ((-1) != bit)
+    {
+        _sd_set_err(p_hndl, s_info2_err_tbl[bit]);
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_check_info2_err
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_get_info2
+ * Description  : get SD_INFO2 register
+ *              : set the register value to p_hndl->int_info2
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : none
+ *****************************************************************************/
+static void _sd_get_info2(st_sdhndl_t *p_hndl)
+{
+    uint64_t info2_reg;
+
+    /* Cast to an appropriate type */
+    info2_reg = (uint64_t)((SD_INP(p_hndl, SD_INFO2) & SD_INFO2_MASK_ERR));
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2, (uint64_t)~info2_reg);
+
+    /* Cast to an appropriate type */
+    p_hndl->int_info2 = (uint64_t)(p_hndl->int_info2 | info2_reg);
+}
+/******************************************************************************
+ End of function _sd_get_info2
+ *****************************************************************************/
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_init.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,444 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_init.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : SD Driver initialize
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02     Support for OS
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+st_sdhndl_t *gp_sdhandle[NUM_PORT];
+
+static int32_t _sd_init_error(int32_t sd_port, int32_t ret);
+
+/******************************************************************************
+ * Function Name: sd_init
+ * Description  : initialize SD Driver (more than 2ports).
+ *              : initialize SD Driver work memory started from SDHI register
+ *              : base
+ *              : address specified by argument (base)
+ *              : initialize port specified by argument (cd_port)
+ *              : work memory is allocated octlet boundary
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint32_t base   : SDHI register base address
+ *              : void *workarea  : SD Driver work memory
+ *              : int32_t cd_port : card detect port
+ *              :   SD_CD_SOCKET  : card detect by CD pin
+ *              :   SD_CD_DAT3    : card detect by DAT3 pin
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *              : SD_ERR_CPU_IF : CPU-IF function error
+ *****************************************************************************/
+int32_t sd_init(int32_t sd_port, uint32_t base, void *workarea, int32_t cd_port)
+{
+    int32_t     i;
+    uint64_t    info1;
+    uint8_t     *p_ptr;
+    st_sdhndl_t *p_hndl;
+    int32_t     ret;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    if ((SD_SCC_IP0_BASE_ADDR != base) && (SD_SCC_IP1_BASE_ADDR != base))
+    {
+        return SD_ERR;
+    }
+
+    /* ==== initialize work memory  ==== */
+    if ((uint32_t)workarea == 0)
+    {
+        ret = SD_ERR;
+        return _sd_init_error(sd_port, ret);
+    }
+
+    /* ==== work memory boundary check (octlet unit) ==== */
+    if ((uint32_t)workarea & 0x7u)
+    {
+        ret = SD_ERR;
+        return _sd_init_error(sd_port, ret);
+    }
+
+    /* ==== check card detect port ==== */
+    if ((SD_CD_SOCKET != cd_port) && (SD_CD_DAT3 != cd_port))
+    {
+        ret = SD_ERR;
+        return _sd_init_error(sd_port, ret);
+    }
+
+    /* card detect port is fixed at CD pin */
+    cd_port = SD_CD_SOCKET;
+
+    /* ==== initialize peripheral module ==== */
+    if (sddev_init(sd_port) != SD_OK)
+    {
+        ret = SD_ERR_CPU_IF;
+        return _sd_init_error(sd_port, ret);
+    }
+
+    /* disable all interrupts */
+    sddev_loc_cpu(sd_port);
+
+    /* Cast to an appropriate type */
+    p_hndl = (st_sdhndl_t *)workarea;
+
+    gp_sdhandle[sd_port] = p_hndl;
+
+    /* ---- clear work memory zero value --- */
+    p_ptr = (uint8_t *)p_hndl;
+    for (i = sizeof(st_sdhndl_t); i > 0 ; i--)
+    {
+        *p_ptr++ = 0;
+    }
+
+    /* ---- set SDHI register address ---- */
+    p_hndl->reg_base = base;
+
+    /* Cast to an appropriate type */
+    p_hndl->cd_port = (uint8_t)cd_port;
+
+    /* ---- initialize maximum block count ---- */
+    p_hndl->trans_sectors = 256;
+    p_hndl->trans_blocks  = 32;
+
+    p_hndl->sd_port = sd_port;
+
+    /* return to select port0 */
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* ==== initialize SDHI ==== */
+    SD_OUTP(p_hndl, SD_INFO1_MASK, SD_INFO1_MASK_ALL);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2_MASK, SD_INFO2_MASK_ALLP);
+
+    /* Cast to an appropriate type */
+    info1 = SD_INP(p_hndl, SD_INFO1);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO1, (uint64_t)(info1 & ~SD_INFO1_MASK_TRNS_RESP));
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2, 0x0000);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RESET);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RELEASED);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO1_MASK, DM_CM_INFO1_MASK_ALLP);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO2_MASK, DM_CM_INFO2_MASK_ALLP);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO1, (uint64_t)0);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO2, (uint64_t)0);
+
+    /* initialize DMAC */
+    ret = sddev_reset_dma(sd_port);
+    if (SD_OK != ret)
+    {
+        return ret;
+    }
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, HOST_MODE, HOST_MODE_64BIT_ACCESS);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_OPTION, SD_OPTION_INIT);
+
+    /* enable all interrupts */
+    sddev_unl_cpu(sd_port);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_init
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_init_error
+ * Description  : initialize SD Driver error.
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : int32_t ret     : return value
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *              : SD_ERR_CPU_IF : CPU-IF function error
+ *****************************************************************************/
+static int32_t _sd_init_error(int32_t sd_port, int32_t ret)
+{
+    gp_sdhandle[sd_port] = 0;  /* relese SD handle */
+    return ret;
+}
+/******************************************************************************
+ End of function _sd_init_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_finalize
+ * Description  : do finish operation of SD Driver (2ports).
+ *              : finish SD Driver
+ *              : reset SDHI include card detection/removal
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : after this function finished, SD handle is unavailable
+ *****************************************************************************/
+int32_t sd_finalize(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+    uint64_t    info1;
+    int32_t     ret;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    if (0 == gp_sdhandle[sd_port])
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* reset SDHI */
+    SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RESET);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO1_MASK, SD_INFO1_MASK_ALL);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2_MASK, SD_INFO2_MASK_ALLP);
+
+    /* Cast to an appropriate type */
+    info1 = SD_INP(p_hndl, SD_INFO1);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO1, (uint64_t)(info1 & ~SD_INFO1_MASK_TRNS_RESP));
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2, 0x0000);
+
+    /* reset DMAC */
+    ret = sddev_finalize_dma(sd_port);
+    if (SD_OK != ret)
+    {
+        return ret;
+    }
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO1_MASK, DM_CM_INFO1_MASK_ALLP);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO2_MASK, DM_CM_INFO2_MASK_ALLP);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO1, (uint64_t)0);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO2, (uint64_t)0);
+
+    /* ==== finish peripheral module ==== */
+    ret = sddev_finalize(sd_port);
+
+    gp_sdhandle[sd_port] = 0;  /* destruct SD Handle */
+
+    return ret;
+}
+/******************************************************************************
+ End of function sd_finalize
+ *****************************************************************************/
+
+
+/******************************************************************************
+ * Function Name: _sd_init_hndl
+ * Description  : initialize SD handle.
+ *              : initialize following SD handle members
+ *              : media_type       : card type
+ *              : write_protect    : write protect
+ *              : resp_status      : R1/R1b response status
+ *              : error            : error detail information
+ *              : stop             : compulsory stop flag
+ *              : prot_sector_size : sector size (protect area)
+ *              : card registers   : ocr, cid, csd, dsr, rca, scr, sdstatus and
+ *              : status_data
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint32_t mode       : driver mode
+ *              : uint32_t voltage    : working voltage
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_init_hndl(st_sdhndl_t *p_hndl, uint32_t mode, uint32_t voltage)
+{
+    int32_t i;
+
+    p_hndl->media_type = SD_MEDIA_UNKNOWN;
+    p_hndl->write_protect = 0;
+    p_hndl->resp_status = STATE_IDEL;
+    p_hndl->error = SD_OK;
+    p_hndl->stop = 0;
+    p_hndl->prot_sector_size = 0;
+    p_hndl->voltage = voltage;
+    p_hndl->speed_mode = 0;
+
+    /* Cast to an appropriate type */
+    p_hndl->int_mode = (uint8_t)(mode & 0x1u);
+
+    /* Cast to an appropriate type */
+    p_hndl->trans_mode = (uint8_t)(mode & SD_MODE_DMA);
+
+    /* Cast to an appropriate type */
+    p_hndl->sup_card = (uint8_t)(mode & 0x30u);
+
+    /* Cast to an appropriate type */
+    p_hndl->sup_speed = (uint16_t)(mode & 0xF040u);
+
+    /* Cast to an appropriate type */
+    p_hndl->sup_ver = (uint8_t)(mode & 0x80u);
+    if (mode & SD_MODE_1BIT)
+    {
+        p_hndl->sup_if_mode = SD_PORT_SERIAL;
+    }
+    else
+    {
+        p_hndl->sup_if_mode = SD_PORT_PARALLEL;
+    }
+
+    /* initialize card registers */
+    for (i = 0; i < (4 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->ocr[i] = 0;
+    }
+    for (i = 0; i < (16 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->cid[i] = 0;
+    }
+    for (i = 0; i < (16 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->csd[i] = 0;
+    }
+    for (i = 0; i < (2 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->dsr[i] = 0;
+    }
+    for (i = 0; i < (4 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->rca[i] = 0;
+    }
+    for (i = 0; i < (8 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->scr[i] = 0;
+    }
+    for (i = 0; i < (14 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->sdstatus[i] = 0;
+    }
+    for (i = 0; i < (18 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->status_data[i] = 0;
+    }
+    for (i = 0; i < (4 / sizeof(uint16_t)); ++i)
+    {
+        p_hndl->if_cond[i] = 0;
+    }
+
+    if (SD_MODE_VER2X == p_hndl->sup_ver)
+    {
+        p_hndl->if_cond[0] = 0;
+        p_hndl->if_cond[1] = 0x00aa;
+        if (p_hndl->voltage & 0x00FF8000)
+        {
+            p_hndl->if_cond[1] |= 0x0100; /* high volatege : 2.7V-3.6V */
+        }
+        if (p_hndl->voltage & 0x00000F00)
+        {
+            p_hndl->if_cond[1] |= 0x0200; /* low volatege : 1.65V-1.95V */
+        }
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_init_hndl
+ *****************************************************************************/
+
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_int.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,604 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_int.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : SD_INFO1 and SD_INFO2 interrupt
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+ * Function Name: _sd_set_int_mask
+ * Description  : set SD_INFO1 and SD_INFO2 interrupt mask.
+ *              : set int_info1_mask and int_info2_mask depend on the mask bits
+ *              : value
+ *              : if mask bit is one, it is enabled
+ *              : if mask bit is zero, it is disabled
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint64_t mask1      : SD_INFO1_MASK1 bits value
+ *              : uint64_t mask2      : SD_INFO1_MASK2 bits value
+ * Return Value : SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_set_int_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+{
+    sddev_loc_cpu(p_hndl->sd_port);
+
+    /* ---- set int_info1_mask and int_info2_mask ---- */
+    p_hndl->int_info1_mask |= mask1;
+    p_hndl->int_info2_mask |= mask2;
+
+    /* ---- set hardware mask ---- */
+    SD_OUTP(p_hndl, SD_INFO1_MASK, (uint64_t)~(p_hndl->int_info1_mask));
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2_MASK, (uint64_t)~(p_hndl->int_info2_mask));
+
+    sddev_unl_cpu(p_hndl->sd_port);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_set_int_mask
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_clear_int_mask
+ * Description  : clear SD_INFO1 and SD_INFO2 interrupt mask.
+ *              : clear int_cc_status_mask depend on the mask bits value
+ *              : if mask bit is one, it is disabled
+ *              : if mask bit is zero, it is enabled
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint64_t mask1      : SD_INFO1_MASK1 bits value
+ *              : uint64_t mask2      : SD_INFO1_MASK2 bits value
+ * Return Value : SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_clear_int_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+{
+    sddev_loc_cpu(p_hndl->sd_port);
+
+    /* ---- clear int_info1_mask and int_info2_mask ---- */
+    p_hndl->int_info1_mask &= (uint64_t)~mask1;
+
+    /* Cast to an appropriate type */
+    p_hndl->int_info2_mask &= (uint64_t)~mask2;
+
+    /* ---- clear hardware mask ---- */
+    SD_OUTP(p_hndl, SD_INFO1_MASK, (uint64_t)~(p_hndl->int_info1_mask));
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2_MASK, (uint64_t)~(p_hndl->int_info2_mask));
+
+    sddev_unl_cpu(p_hndl->sd_port);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_clear_int_mask
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_clear_info
+ * Description  : clear int_info bits.
+ *              : clear int_info1 and int_info2 depend on the clear value
+ * Arguments    : st_sdhndl_t *p_hndl  : SD handle
+ *              : uint64_t clear_info1 : int_info1 clear bits value
+ *              : uint64_t clear_info2 : int_info2 clear bits value
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : SD_INFO1 and SD_INFO2 bits are not cleared
+ *****************************************************************************/
+int32_t _sd_clear_info(st_sdhndl_t *p_hndl, uint64_t clear_info1, uint64_t clear_info2)
+{
+    sddev_loc_cpu(p_hndl->sd_port);
+
+    /* ---- clear int_info1 and int_info2 ---- */
+    p_hndl->int_info1 &= (uint64_t)~clear_info1;
+
+    /* Cast to an appropriate type */
+    p_hndl->int_info2 &= (uint64_t)~clear_info2;
+
+    sddev_unl_cpu(p_hndl->sd_port);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_clear_info
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_get_int
+ * Description  : get SD_INFO1 and SD_INFO2 interrupt elements.
+ *              : get SD_INFO1 and SD_INFO2 bits
+ *              : examine enabled elements
+ *              : hearafter, clear SD_INFO1 and SD_INFO2 bits
+ *              : save those bits to int_info1 or int_info2
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_get_int(st_sdhndl_t *p_hndl)
+{
+    uint64_t info1;
+    uint64_t info2;
+
+    /* get SD_INFO1 and SD_INFO2 bits */
+    info1 = (uint64_t)(SD_INP(p_hndl, SD_INFO1) & p_hndl->int_info1_mask);
+
+    /* Cast to an appropriate type */
+    info2 = (uint64_t)(SD_INP(p_hndl, SD_INFO2) & p_hndl->int_info2_mask);
+
+    /* clear SD_INFO1 and SD_INFO2 bits */
+    SD_OUTP(p_hndl, SD_INFO1, (uint64_t)~info1);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2, (uint64_t)~info2);
+
+    /* save enabled elements */
+    p_hndl->int_info1 |= info1;
+    p_hndl->int_info2 |= info2;
+    if (info1 || info2)
+    {
+        return SD_OK;   /* any interrupt occured */
+    }
+
+    return SD_ERR;  /* no interrupt occured */
+}
+/******************************************************************************
+ End of function _sd_get_int
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_check_int
+ * Description  : check SD_INFO1 and SD_INFO2 interrupt elements
+ *              : if any interrupt is detected, return SD_OK
+ *              : if no interrupt is detected, return SD_ERR
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_check_int(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (p_hndl->int_mode)
+    {
+        /* ---- hardware interrupt mode ---- */
+        if (p_hndl->int_info1 || p_hndl->int_info2)
+        {
+            return SD_OK;
+        }
+        else
+        {
+            return SD_ERR;
+        }
+    }
+
+    /* ---- polling mode ---- */
+    return _sd_get_int(p_hndl);
+}
+/******************************************************************************
+ End of function sd_check_int
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_int_handler
+ * Description  : SD_INFO1 and SD_INFO2 interrupt handler
+ *              : examine the relevant elements (without masked)
+ *              : save those elements to int_info1 or int_info2
+ *              : if a callback function is registered, call it
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : none
+ *****************************************************************************/
+void sd_int_handler(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+    int32_t     cd;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return;
+    }
+
+    if (_sd_get_int(p_hndl) == SD_OK)
+    {
+        /* is card detect interrupt? */
+        if (p_hndl->int_info1 & (SD_INFO1_MASK_DET_DAT3 | SD_INFO1_MASK_DET_CD))
+        {
+            if (p_hndl->int_cd_callback)
+            {
+                /* Cast to an appropriate type */
+                if (p_hndl->int_info1 & (SD_INFO1_MASK_INS_DAT3 | SD_INFO1_MASK_INS_CD))
+                {
+                    cd = 1; /* insert */
+                }
+                else
+                {
+                    cd = 0; /* remove */
+                }
+                (*p_hndl->int_cd_callback)(sd_port, cd);
+            }
+
+            /* Cast to an appropriate type */
+            p_hndl->int_info1 &= (uint64_t)~(SD_INFO1_MASK_DET_DAT3 | SD_INFO1_MASK_DET_CD);
+        }
+        else
+        {
+            if (p_hndl->int_callback)
+            {
+                (*p_hndl->int_callback)(sd_port, 0);  /* arguments to be defined */
+            }
+        }
+    }
+}
+/******************************************************************************
+ End of function sd_int_handler
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_set_intcallback
+ * Description  : register SD_INFO1 or SD_INFO2 interrupt callback function.
+ *              : register callback function
+ *              : if SD_INFO1 or SD_INFO2 interrupt are occured, call callback
+ *              : function
+ * Arguments    : int32_t sd_port                       : channel no (0 or 1)
+ *              : int32_t (*callback)(int32_t, int32_t) : callback function
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_set_intcallback(int32_t sd_port, int32_t (*callback)(int32_t, int32_t))
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    p_hndl->int_callback = callback;
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_set_intcallback
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_set_int_dm_mask
+ * Description  : set DM_CM_INFO1_MASK and DM_CM_INFO2_MASK interrupt mask.
+ *              : set int_dm_info1_mask and int_dm_info2_mask depend on the mask bits
+ *              : value
+ *              : if mask bit is one, it is enabled
+ *              : if mask bit is zero, it is disabled
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint64_t mask1      : DM_CM_INFO1_MASK bits value
+ *              : uint64_t mask2      : DM_CM_INFO2_MASK bits value
+ * Return Value : SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_set_int_dm_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+{
+    sddev_loc_cpu(p_hndl->sd_port);
+
+    /* ---- set int_dm_info1_mask and int_dm_info2_mask ---- */
+    p_hndl->int_dm_info1_mask |= mask1;
+    p_hndl->int_dm_info2_mask |= mask2;
+
+    /* ---- set hardware mask ---- */
+    SD_OUTP(p_hndl, DM_CM_INFO1_MASK, (uint64_t)~(p_hndl->int_dm_info1_mask));
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO2_MASK, (uint64_t)~(p_hndl->int_dm_info2_mask));
+
+    sddev_unl_cpu(p_hndl->sd_port);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_set_int_dm_mask
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_clear_int_dm_mask
+ * Description  : clear DM_CM_INFO1_MASK and DM_CM_INFO2_MASK interrupt mask.
+ *              : clear int_dm_info1_mask and int_dm_info2_mask depend on the mask bits value
+ *              : if mask bit is one, it is disabled
+ *              : if mask bit is zero, it is enabled
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint64_t mask1      : DM_CM_INFO1_MASK bits value
+ *              : uint64_t mask2      : DM_CM_INFO2_MASK bits value
+ * Return Value : SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_clear_int_dm_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+{
+    sddev_loc_cpu(p_hndl->sd_port);
+
+    /* ---- clear int_dm_info1_mask and int_dm_info2_mask ---- */
+    p_hndl->int_dm_info1_mask &= (uint64_t)~mask1;
+
+    /* Cast to an appropriate type */
+    p_hndl->int_dm_info2_mask &= (uint64_t)~mask2;
+
+    /* ---- clear hardware mask ---- */
+    SD_OUTP(p_hndl, DM_CM_INFO1_MASK, (uint64_t)~(p_hndl->int_dm_info1_mask));
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO2_MASK, (uint64_t)~(p_hndl->int_dm_info2_mask));
+
+    sddev_unl_cpu(p_hndl->sd_port);
+
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_clear_int_dm_mask
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_clear_dm_info
+ * Description  : clear int_dm_info bits.
+ *              : clear int_dm_info1 and int_dm_info2 depend on the clear value
+ * Arguments    : st_sdhndl_t *p_hndl  : SD handle
+ *              : uint64_t clear_info1 : int_dm_info1 clear bits value
+ *              : uint64_t clear_info2 : int_dm_info2 clear bits value
+ * Return Value : SD_OK : end of succeed
+ * Remark       : DM_CM_INFO1 and DM_CM_INFO2 bits are not cleared
+ *****************************************************************************/
+int32_t _sd_clear_dm_info(st_sdhndl_t *p_hndl, uint64_t clear_info1, uint64_t clear_info2)
+{
+    sddev_loc_cpu(p_hndl->sd_port);
+
+    /* ---- clear int_dm_info1 and int_dm_info2 ---- */
+    p_hndl->int_dm_info1 &= (uint64_t)~clear_info1;
+
+    /* Cast to an appropriate type */
+    p_hndl->int_dm_info2 &= (uint64_t)~clear_info2;
+
+    sddev_unl_cpu(p_hndl->sd_port);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_clear_dm_info
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_get_int_dm
+ * Description  : get DM_CM_INFO1 and DM_CM_INFO2 interrupt elements.
+ *              : get DM_CM_INFO1 and DM_CM_INFO2 bits
+ *              : examine enabled elements
+ *              : hearafter, clear DM_CM_INFO1 and DM_CM_INFO2 bits
+ *              : save those bits to int_dm_info1 or int_dm_info2
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : any interrupt occured
+ *              : SD_ERR: no interrupt occured
+ *****************************************************************************/
+int32_t _sd_get_int_dm(st_sdhndl_t *p_hndl)
+{
+    uint64_t info1;
+    uint64_t info2;
+
+    /* get DM_CM_INFO1 and DM_CM_INFO2 bits */
+    info1 = (uint64_t)(SD_INP(p_hndl, DM_CM_INFO1) & p_hndl->int_dm_info1_mask);
+
+    /* Cast to an appropriate type */
+    info2 = (uint64_t)(SD_INP(p_hndl, DM_CM_INFO2) & p_hndl->int_dm_info2_mask);
+
+    /* clear DM_CM_INFO1 and DM_CM_INFO2 bits */
+    SD_OUTP(p_hndl, DM_CM_INFO1, (uint64_t)~info1);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, DM_CM_INFO2, (uint64_t)~info2);
+
+    /* save enabled elements */
+    p_hndl->int_dm_info1 |= info1;
+    p_hndl->int_dm_info2 |= info2;
+    if (info1 || info2)
+    {
+        return SD_OK;   /* any interrupt occured */
+    }
+
+    return SD_ERR;  /* no interrupt occured */
+}
+/******************************************************************************
+ End of function _sd_get_int_dm
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_check_int_dm
+ * Description  : check DM_CM_INFO1 and DM_CM_INFO2 interrupt elements
+ *              : if any interrupt is detected, return SD_OK
+ *              : if no interrupt is detected, return SD_ERR
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : any interrupt occured
+ *              : SD_ERR: no interrupt occured
+ *****************************************************************************/
+int32_t sd_check_int_dm(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (p_hndl->int_mode)
+    {
+        /* ---- hardware interrupt mode ---- */
+        if (p_hndl->int_dm_info1 || p_hndl->int_dm_info2)
+        {
+            return SD_OK;
+        }
+        else
+        {
+            return SD_ERR;
+        }
+    }
+
+    /* ---- polling mode ---- */
+    return _sd_get_int_dm(p_hndl);
+}
+/******************************************************************************
+ End of function sd_check_int_dm
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_int_dm_handler
+ * Description  : DM_CM_INFO1 and DM_CM_INFO2 interrupt handler
+ *              : examine the relevant elements (without masked)
+ *              : save those elements to int_dm_info1 or int_dm_info2
+ *              : if a callback function is registered, call it
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : none
+ *****************************************************************************/
+void sd_int_dm_handler(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return;
+    }
+
+    if (_sd_get_int_dm(p_hndl) == SD_OK)
+    {
+        if (p_hndl->int_dma_callback)
+        {
+            (*p_hndl->int_dma_callback)(sd_port, 0);  /* arguments to be defined */
+        }
+    }
+}
+/******************************************************************************
+ End of function sd_int_dm_handler
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_set_dma_intcallback
+ * Description  : register DM_CM_INFO1 or DM_CM_INFO2 interrupt callback function.
+ *              : register callback function
+ *              : if DM_CM_INFO1 or DM_CM_INFO2 interrupt are occured, call callback
+ *              : function
+ * Arguments    : int32_t sd_port                       : channel no (0 or 1)
+ *              : int32_t (*callback)(int32_t, int32_t) : callback function
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_set_dma_intcallback(int32_t sd_port, int32_t (*callback)(int32_t, int32_t))
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    p_hndl->int_dma_callback = callback;
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_set_dma_intcallback
+ *****************************************************************************/
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_mount.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1053 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_mount.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : Card mount
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02     Support for OS
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static uint16_t s_stat_buff[NUM_PORT][64 / sizeof(uint16_t)];
+
+static int32_t _sd_mount_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_card_init_get_rca(st_sdhndl_t *p_hndl);
+static int32_t _sd_mem_mount_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_read_byte_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_write_byte_error(st_sdhndl_t *p_hndl);
+
+/******************************************************************************
+ * Function Name: sd_mount
+ * Description  : mount SD card.
+ *              : mount SD memory card user area
+ *              : can be access user area after this function is finished
+ *              : without errors
+ *              : turn on power
+ *              :
+ *              : following is available SD Driver mode
+ *              : SD_MODE_POLL     : software polling
+ *              : SD_MODE_HWINT    : hardware interrupt
+ *              : SD_MODE_SW       : software data transfer (SD_BUF)
+ *              : SD_MODE_DMA      : DMA data transfer (SD_BUF)
+ *              : SD_MODE_MEM      : only memory cards
+ *              : SD_MODE_DS       : only default speed
+ *              : SD_MODE_VER1X    : ver1.1 host
+ *              : SD_MODE_VER2X    : ver2.x host
+ * Arguments    : int32_t sd_port  : channel no (0 or 1)
+ *              : uint32_t mode    : SD Driver operation mode
+ *              : uint32_t voltage : operation voltage
+ * Return Value : p_hndl->error    : SD handle error value
+ *              : SD_OK : end of succeed
+ *              : other : end of error
+ * Remark       : user area should be mounted
+ *****************************************************************************/
+int32_t sd_mount(int32_t sd_port, uint32_t mode, uint32_t voltage)
+{
+    st_sdhndl_t *p_hndl;
+    uint64_t    info1_back;
+    uint16_t    sd_spec;
+    uint16_t    sd_spec3;
+
+    if ((0 != sd_port) && (1 != sd_port))
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* ==== check work buffer is allocated ==== */
+    if (0 == p_hndl->p_rw_buff)
+    {
+        return SD_ERR;  /* not allocated yet */
+    }
+
+    /* ==== initialize parameter ==== */
+    _sd_init_hndl(p_hndl, mode, voltage);
+    p_hndl->error = SD_OK;
+
+    /* ==== is card inserted? ==== */
+    if (_sd_check_media(p_hndl) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_NO_CARD);
+        return p_hndl->error;     /* not inserted */
+    }
+
+    /* ==== power on sequence ==== */
+    /* ---- turn on voltage ---- */
+    if (sddev_power_on(sd_port) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+        return _sd_mount_error(p_hndl);
+    }
+
+    /* ---- set single port ---- */
+    _sd_set_port(p_hndl, SD_PORT_SERIAL);
+
+    /* ---- supply clock (card-identification ratio) ---- */
+    if (_sd_set_clock(p_hndl, SD_CLK_400KHZ, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return p_hndl->error;     /* not inserted */
+    }
+
+    sddev_int_wait(sd_port, 2); /* add wait function  */
+
+    sddev_loc_cpu(sd_port);
+
+    /* Cast to an appropriate type */
+    info1_back = SD_INP(p_hndl, SD_INFO1);
+
+    /* Cast to an appropriate type */
+    info1_back &= (uint64_t)0xfff8;
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO1, (uint64_t)info1_back);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_INFO2, (uint64_t)0);
+
+    /* Clear DMA Enable because of CPU Transfer */
+    SD_OUTP(p_hndl, CC_EXT_MODE, (uint64_t)(SD_INP(p_hndl, CC_EXT_MODE) & ~CC_EXT_MODE_DMASDRW)); /* disable DMA  */
+
+    sddev_unl_cpu(sd_port);
+
+    /* ==== initialize card and distinguish card type ==== */
+    if (_sd_card_init(p_hndl) != SD_OK)
+    {
+        return _sd_mount_error(p_hndl);  /* failed card initialize */
+    }
+
+    if (p_hndl->media_type & SD_MEDIA_MEM)    /* with memory part */
+    {
+        /* ==== check card registers ==== */
+        /* ---- check CSD register ---- */
+        if (_sd_check_csd(p_hndl) != SD_OK)
+        {
+            return _sd_mount_error(p_hndl);
+        }
+
+        /* ---- no check other registers (to be create) ---- */
+
+        /* get user area size */
+        if (_sd_get_size(p_hndl, SD_USER_AREA) != SD_OK)
+        {
+            return _sd_mount_error(p_hndl);
+        }
+
+        /* check write protect */
+        p_hndl->write_protect |= (uint8_t)_sd_iswp(p_hndl);
+    }
+
+    if (p_hndl->media_type & SD_MEDIA_MEM)    /* with memory part */
+    {
+        if (_sd_mem_mount(p_hndl) != SD_OK)
+        {
+            return _sd_mount_error(p_hndl);
+        }
+        if (SD_ERR_CARD_LOCK == p_hndl->error)
+        {
+            p_hndl->mount = (SD_CARD_LOCKED | SD_MOUNT_LOCKED_CARD);
+
+            /* ---- halt clock ---- */
+            _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+            return SD_OK_LOCKED_CARD;
+        }
+    }
+
+    /* if SD memory card, get SCR register */
+    if (p_hndl->media_type & SD_MEDIA_SD)
+    {
+        if (_sd_card_get_scr(p_hndl) != SD_OK)
+        {
+            return _sd_mount_error(p_hndl);
+        }
+
+        if (SD_SPEC_20 == p_hndl->sd_spec)
+        {
+            /* Cast to an appropriate type */
+            sd_spec = (uint16_t)(p_hndl->scr[0] & SD_SPEC_REGISTER_MASK);
+
+            /* Cast to an appropriate type */
+            sd_spec3 = (uint16_t)(p_hndl->scr[1] & SD_SPEC_30_REGISTER);
+            if ((SD_SPEC_20_REGISTER == sd_spec) && (SD_SPEC_30_REGISTER == sd_spec3))
+            {
+                /* ---- more than phys spec ver3.00 ---- */
+                p_hndl->sd_spec = SD_SPEC_30;
+            }
+            else     /* ---- phys spec ver2.00 ---- */
+            {
+                p_hndl->sd_spec = SD_SPEC_20;
+            }
+        }
+        else
+        {
+            /* Cast to an appropriate type */
+            sd_spec = (uint16_t)(p_hndl->scr[0] & SD_SPEC_REGISTER_MASK);
+            if (SD_SPEC_11_REGISTER == sd_spec)   /* ---- phys spec ver1.10 ---- */
+            {
+                p_hndl->sd_spec = SD_SPEC_11;
+            }
+            else    /* ---- phys spec ver1.00 or ver1.01 ---- */
+            {
+                p_hndl->sd_spec = SD_SPEC_10;
+            }
+        }
+
+        /* Cast to an appropriate type */
+        (void)_sd_calc_erase_sector(p_hndl);
+    }
+
+    /* ---- set mount flag ---- */
+    p_hndl->mount = SD_MOUNT_UNLOCKED_CARD;
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function sd_mount
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_mount_error
+ * Description  : mount SD card error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : p_hndl->error  : SD handle error value
+ *              : SD_OK : end of succeed
+ *              : other : end of error
+ *****************************************************************************/
+static int32_t _sd_mount_error(st_sdhndl_t *p_hndl)
+{
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_mount_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_card_init
+ * Description  : initialize card.
+ *              : initialize card from idle state to stand-by
+ *              : distinguish card type (SD, MMC, IO or COMBO)
+ *              : get CID, RCA, CSD from the card
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_card_init(st_sdhndl_t *p_hndl)
+{
+    int32_t  ret;
+    int32_t  i;
+    uint16_t if_cond_0;
+    uint16_t if_cond_1;
+
+    p_hndl->media_type = SD_MEDIA_UNKNOWN;
+    if_cond_0 = p_hndl->if_cond[0];
+    if_cond_1 = p_hndl->if_cond[1];
+
+    /* ==== transfer idle state (issue CMD0) ==== */
+    for (i = 0; i < 3; i++)
+    {
+        ret = _sd_send_cmd(p_hndl, CMD0);
+        if (SD_OK == ret)
+        {
+            break;
+        }
+    }
+
+    if (SD_OK != ret)
+    {
+        return SD_ERR;  /* error for CMD0 */
+    }
+
+    /* clear error by reissuing CMD0 */
+    p_hndl->error = SD_OK;
+
+    p_hndl->media_type |= SD_MEDIA_SD;
+
+    if (SD_MODE_VER2X == p_hndl->sup_ver)
+    {
+        ret = _sd_card_send_cmd_arg(p_hndl, CMD8, SD_RSP_R7, if_cond_0, if_cond_1);
+        if (SD_OK == ret)
+        {
+            /* check R7 response */
+            if (p_hndl->if_cond[0] & 0xf000)
+            {
+                p_hndl->error = SD_ERR_IFCOND_VER;
+                return SD_ERR;
+            }
+            if ((p_hndl->if_cond[1] & 0x00ff) != 0x00aa)
+            {
+                p_hndl->error = SD_ERR_IFCOND_ECHO;
+                return SD_ERR;
+            }
+            p_hndl->sd_spec = SD_SPEC_20;         /* cmd8 have response.              */
+
+            /* because of (phys spec ver2.00)   */
+        }
+        else
+        {
+            /* ==== clear illegal command error for CMD8 ==== */
+            for (i = 0; i < 3; i++)
+            {
+                ret = _sd_send_cmd(p_hndl, CMD0);
+                if (SD_OK == ret)
+                {
+                    break;
+                }
+            }
+            p_hndl->error = SD_OK;
+            p_hndl->sd_spec = SD_SPEC_10;         /* cmd8 have no response.                   */
+
+            /* because of (phys spec ver1.01 or 1.10)   */
+        }
+    }
+    else
+    {
+        p_hndl->sd_spec = SD_SPEC_10;             /* cmd8 have response.                      */
+
+        /* because of (phys spec ver1.01 or 1.10)   */
+    }
+
+    /* set OCR (issue ACMD41) */
+    ret = _sd_card_send_ocr(p_hndl, (int32_t)p_hndl->media_type);
+
+    /* clear error due to card distinction */
+    p_hndl->error = SD_OK;
+
+    if (SD_OK != ret)
+    {
+        /* softreset for error clear (issue CMD0) */
+        for (i = 0; i < 3; i++)
+        {
+            ret = _sd_send_cmd(p_hndl, CMD0);
+            if (SD_OK == ret)
+            {
+                break;
+            }
+        }
+        if (SD_OK != ret)
+        {
+            return SD_ERR;  /* error for CMD0 */
+        }
+
+        /* clear error by reissuing CMD0 */
+        p_hndl->error = SD_OK;
+
+        /* ---- get OCR (issue CMD1) ---- */
+        if (SD_OK == (ret = _sd_card_send_ocr(p_hndl, SD_MEDIA_MMC)))
+        {
+            /* MMC */
+            p_hndl->media_type = SD_MEDIA_MMC;
+            p_hndl->error = SD_OK;
+        }
+        else
+        {
+            /* unknown card */
+            p_hndl->media_type = SD_MEDIA_UNKNOWN;
+            _sd_set_err(p_hndl, SD_ERR_CARD_TYPE);
+            return SD_ERR;
+        }
+    }
+
+    /* ---- get CID (issue CMD2) ---- */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD2, SD_RSP_R2_CID, 0, 0) != SD_OK)
+    {
+        return SD_ERR;
+    }
+    return _sd_card_init_get_rca(p_hndl);
+}
+/******************************************************************************
+ End of function _sd_card_init
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_card_init_get_rca
+ * Description  : initialize card.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_card_init_get_rca(st_sdhndl_t *p_hndl)
+{
+    int32_t  i;
+
+    /* ---- get RCA (issue CMD3) ---- */
+    if (p_hndl->media_type & SD_MEDIA_SD)  /* SD */
+    {
+        for (i = 0; i < 3; i++)
+        {
+            if (_sd_card_send_cmd_arg(p_hndl, CMD3, SD_RSP_R6, 0, 0) != SD_OK)
+            {
+                return SD_ERR;
+            }
+            if (0x00 != p_hndl->rca[0])
+            {
+                break;
+            }
+        }
+
+        /* illegal RCA */
+        if (3 == i)
+        {
+            _sd_set_err(p_hndl, SD_ERR_CARD_CC);
+            return SD_ERR;
+        }
+    }
+    else
+    {
+        p_hndl->rca[0] = 1;   /* fixed 1 */
+        if (_sd_card_send_cmd_arg(p_hndl, CMD3, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+                != SD_OK)
+        {
+            return SD_ERR;
+        }
+    }
+
+    /* ---- get CSD (issue CMD9) ---- */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD9, SD_RSP_R2_CSD, p_hndl->rca[0], 0x0000)
+            != SD_OK)
+    {
+        return SD_ERR;
+    }
+
+    p_hndl->dsr[0] = 0x0000;
+
+    if (p_hndl->media_type & SD_MEDIA_MEM)
+    {
+        /* is DSR implimented? */
+        if (p_hndl->csd[3] & 0x0010u) /* implimented */
+        {
+            /* set DSR (issue CMD4) */
+            p_hndl->dsr[0] = 0x0404;
+            if (_sd_card_send_cmd_arg(p_hndl, CMD4, SD_RSP_NON, p_hndl->dsr[0], 0x0000)
+                    != SD_OK)
+            {
+                return SD_ERR;
+            }
+        }
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_card_init_get_rca
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_mem_mount
+ * Description  : mount memory card.
+ *              : mount memory part from stand-by to transfer state
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_mem_mount(st_sdhndl_t *p_hndl)
+{
+    /* ==== data-transfer mode(Transfer State) ==== */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD7, SD_RSP_R1B, p_hndl->rca[0], 0x0000)
+            != SD_OK)
+    {
+        return _sd_mem_mount_error(p_hndl);
+    }
+
+    if ((p_hndl->resp_status & 0x02000000))
+    {
+        _sd_set_err(p_hndl, SD_ERR_CARD_LOCK);
+        return SD_OK;
+    }
+
+    /* ---- set block length (issue CMD16) ---- */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD16, SD_RSP_R1, 0x0000, 0x0200) != SD_OK)
+    {
+        return _sd_mem_mount_error(p_hndl);
+    }
+
+    /* if 4bits transfer supported (SD memory card mandatory), change bus width 4bits */
+    if (p_hndl->media_type & SD_MEDIA_SD)
+    {
+        _sd_set_port(p_hndl, p_hndl->sup_if_mode);
+    }
+
+    /* clear pull-up DAT3 */
+    if (p_hndl->media_type & SD_MEDIA_SD)
+    {
+        if (_sd_send_acmd(p_hndl, ACMD42, 0, 0) != SD_OK)
+        {
+            return _sd_mem_mount_error(p_hndl);
+        }
+
+        /* check R1 resp */
+        if (_sd_get_resp(p_hndl, SD_RSP_R1) != SD_OK)
+        {
+            return _sd_mem_mount_error(p_hndl);
+        }
+    }
+
+    /* if SD memory card, get SD Status */
+    if (p_hndl->media_type & SD_MEDIA_SD)
+    {
+        if (_sd_card_get_status(p_hndl) != SD_OK)
+        {
+            return _sd_mem_mount_error(p_hndl);
+        }
+
+        /* get protect area size */
+        if (_sd_get_size(p_hndl, SD_PROT_AREA) != SD_OK)
+        {
+            return _sd_mem_mount_error(p_hndl);
+        }
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_mem_mount
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_mem_mount_error
+ * Description  : mount memory card error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_mem_mount_error(st_sdhndl_t *p_hndl)
+{
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_mem_mount_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_unmount
+ * Description  : unmount card.
+ *              : turn off power
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : end of succeed
+ *****************************************************************************/
+int32_t sd_unmount(int32_t sd_port)
+{
+    st_sdhndl_t  *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initialized */
+    }
+
+    /* ---- clear mount flag ---- */
+    p_hndl->mount = SD_UNMOUNT_CARD;
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    /* ---- set single port ---- */
+    sddev_set_port(sd_port, SD_PORT_SERIAL);
+
+    /* ---- turn off power ---- */
+    if (sddev_power_off(sd_port) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+        return p_hndl->error;
+    }
+
+    /* ---- initilaize SD handle ---- */
+    _sd_init_hndl(p_hndl, 0, p_hndl->voltage);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_unmount
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_card_get_status
+ * Description  : get SD Status (issue ACMD13)
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_card_get_status(st_sdhndl_t *p_hndl)
+{
+    int32_t  ret;
+    int32_t  i;
+    uint8_t  *p_rw_buff;
+
+    /* Cast to an appropriate type */
+    p_rw_buff = (uint8_t *)&s_stat_buff[p_hndl->sd_port][0];
+
+    /* ---- get SD Status (issue ACMD13) ---- */
+    if (_sd_read_byte(p_hndl, ACMD13, 0, 0, p_rw_buff, SD_STATUS_BYTE) != SD_OK)
+    {
+        return SD_ERR;
+    }
+
+    /* ---- distinguish SD ROM card ---- */
+    if ((p_rw_buff[2] & 0xffu) == 0x00) /* [495:488] = 0x00 */
+    {
+        ret = SD_OK;
+        if ((p_rw_buff[3] & 0xffu) == 0x01)
+        {
+            p_hndl->write_protect |= SD_WP_ROM;
+        }
+    }
+    else
+    {
+        ret = SD_ERR;
+        _sd_set_err(p_hndl, SD_ERR_CARD_ERROR);
+    }
+
+    p_hndl->speed_class = p_rw_buff[8];
+    p_hndl->perform_move = p_rw_buff[9];
+
+    /* ---- save SD STATUS ---- */
+    for (i = 0; i < (16 / sizeof(uint16_t)); i++)
+    {
+        p_hndl->sdstatus[i] = (s_stat_buff[p_hndl->sd_port][i] << 8) | (s_stat_buff[p_hndl->sd_port][i] >> 8);
+    }
+
+    return ret;
+}
+/******************************************************************************
+ End of function _sd_card_get_status
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_card_get_scr
+ * Description  : get SCR register (issue ACMD51).
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_card_get_scr(st_sdhndl_t *p_hndl)
+{
+    uint8_t  *p_rw_buff;
+
+    /* Cast to an appropriate type */
+    p_rw_buff = (uint8_t *)&s_stat_buff[p_hndl->sd_port][0];
+
+    /* ---- get SCR register (issue ACMD51) ---- */
+    if (_sd_read_byte(p_hndl, ACMD51, 0, 0, p_rw_buff, SD_SCR_REGISTER_BYTE) != SD_OK)
+    {
+        return SD_ERR;
+    }
+
+    /* ---- save SCR register ---- */
+    p_hndl->scr[0] = (s_stat_buff[p_hndl->sd_port][0] << 8) | (s_stat_buff[p_hndl->sd_port][0] >> 8);
+    p_hndl->scr[1] = (s_stat_buff[p_hndl->sd_port][1] << 8) | (s_stat_buff[p_hndl->sd_port][1] >> 8);
+    p_hndl->scr[2] = (s_stat_buff[p_hndl->sd_port][2] << 8) | (s_stat_buff[p_hndl->sd_port][2] >> 8);
+    p_hndl->scr[3] = (s_stat_buff[p_hndl->sd_port][3] << 8) | (s_stat_buff[p_hndl->sd_port][3] >> 8);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_card_get_scr
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_read_byte
+ * Description  : read byte data from card
+ *              : issue byte data read command and read data from SD_BUF
+ *              : using following commands
+ *              : SD STATUS(ACMD13),SCR(ACMD51),NUM_WRITE_BLOCK(ACMD22),
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint16_t cmd        : command code
+ *              : uint16_t h_arg      : command argument high [31:16]
+ *              : uint16_t l_arg      : command argument low [15:0]
+ *              : uint8_t *readbuff   : read data buffer
+ *              : uint16_t byte       : the number of read bytes
+ * Return Value : SD_OK : end of succeed
+ * Remark       : transfer type is PIO
+ *****************************************************************************/
+int32_t _sd_read_byte(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg,
+                        uint16_t l_arg, uint8_t *readbuff, uint16_t byte)
+{
+    /* ---- disable SD_SECCNT ---- */
+    SD_OUTP(p_hndl, SD_STOP, 0x0000);
+
+    /* ---- set transfer bytes ---- */
+    SD_OUTP(p_hndl, SD_SIZE, (uint64_t)byte);
+
+    /* ---- issue command ---- */
+    if (cmd & 0x0040u)  /* ACMD13, ACMD22 and ACMD51 */
+    {
+        if (_sd_send_acmd(p_hndl, cmd, h_arg, l_arg) != SD_OK)
+        {
+            if ((SD_ERR_END_BIT == p_hndl->error) ||
+                    (SD_ERR_CRC == p_hndl->error))
+            {
+                /* continue */
+                ;
+            }
+            else
+            {
+                return _sd_read_byte_error(p_hndl);
+            }
+        }
+    }
+    else
+    {
+        _sd_set_arg(p_hndl, h_arg, l_arg);
+        if (_sd_send_cmd(p_hndl, cmd) != SD_OK)
+        {
+            return SD_ERR;
+        }
+    }
+
+    /* ---- check R1 response ---- */
+    if (_sd_get_resp(p_hndl, SD_RSP_R1) != SD_OK)
+    {
+        return _sd_read_byte_error(p_hndl);
+    }
+
+    /* enable All end, BRE and errors */
+    _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BRE);
+
+    /* ---- wait BRE interrupt ---- */
+    if (sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_MULTIPLE) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+        return _sd_read_byte_error(p_hndl);
+    }
+
+    /* ---- check errors ---- */
+    if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+    {
+        _sd_check_info2_err(p_hndl);
+        return _sd_read_byte_error(p_hndl);
+    }
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, 0x0000, SD_INFO2_MASK_RE); /* clear BRE bit */
+
+    /* transfer data */
+    if (sddev_read_data(p_hndl->sd_port, readbuff, (uint32_t)(p_hndl->reg_base + SD_BUF0), (int32_t)byte) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+        return _sd_read_byte_error(p_hndl);
+    }
+
+    /* wait All end interrupt */
+    if (sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_RESP) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+        return _sd_read_byte_error(p_hndl);
+    }
+
+    /* ---- check errors ---- */
+    if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+    {
+        _sd_check_info2_err(p_hndl);
+        return _sd_read_byte_error(p_hndl);
+    }
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_ERR); /* clear All end bit */
+
+    /* disable all interrupts */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BRE);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_read_byte
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_read_byte_error
+ * Description  : read byte data error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle.
+ * Return Value : SD_ERR: end of error.
+ *****************************************************************************/
+static int32_t _sd_read_byte_error(st_sdhndl_t *p_hndl)
+{
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);                       /* stop data transfer   */
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_ERR); /* clear All end bit    */
+
+    /* disable all interrupts */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BRE);
+
+    return SD_ERR;
+}
+/******************************************************************************
+ End of function _sd_read_byte_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_write_byte
+ * Description  : write byte data to card
+ *              : issue byte data write command and write data to SD_BUF
+ *              : using following commands
+ *              : (CMD27 and CMD42)
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint16_t cmd        : command code
+ *              : uint16_t h_arg      : command argument high [31:16]
+ *              : uint16_t l_arg      : command argument low [15:0]
+ *              : uint8_t *writebuff  : write data buffer
+ *              : uint16_t byte       : the number of write bytes
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : transfer type is PIO
+ *****************************************************************************/
+int32_t _sd_write_byte(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg,
+                        uint16_t l_arg, uint8_t *writebuff, uint16_t byte)
+{
+    int32_t time_out;
+
+    /* ---- disable SD_SECCNT ---- */
+    SD_OUTP(p_hndl, SD_STOP, 0x0000);
+
+    /* ---- set transfer bytes ---- */
+    SD_OUTP(p_hndl, SD_SIZE, (uint64_t)byte);
+
+    /* ---- issue command ---- */
+    _sd_set_arg(p_hndl, h_arg, l_arg);
+    if (_sd_send_cmd(p_hndl, cmd) != SD_OK)
+    {
+        return SD_ERR;
+    }
+
+    /* ---- check R1 response ---- */
+    if (_sd_get_resp(p_hndl, SD_RSP_R1) != SD_OK)
+    {
+        if (SD_ERR_CARD_LOCK == p_hndl->error)
+        {
+            p_hndl->error = SD_OK;
+        }
+        else
+        {
+            return _sd_write_byte_error(p_hndl);
+        }
+    }
+
+    /* enable All end, BWE and errors */
+    _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BWE);
+
+    /* ---- wait BWE interrupt ---- */
+    if (sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_MULTIPLE) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+        return _sd_write_byte_error(p_hndl);
+    }
+
+    /* ---- check errors ---- */
+    if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+    {
+        _sd_check_info2_err(p_hndl);
+        return _sd_write_byte_error(p_hndl);
+    }
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, 0x0000, SD_INFO2_MASK_WE); /* clear BWE bit */
+
+    /* transfer data */
+    if (sddev_write_data(p_hndl->sd_port, writebuff, (uint32_t)(p_hndl->reg_base + SD_BUF0), (int32_t)byte) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+        return _sd_write_byte_error(p_hndl);
+    }
+
+    /* wait All end interrupt */
+    if ( (CMD42 == cmd) && (1 == byte) )
+    {
+        /* force erase timeout  */
+        time_out = SD_TIMEOUT_ERASE_CMD;
+    }
+    else
+    {
+        time_out = SD_TIMEOUT_RESP;
+    }
+
+    if (sddev_int_wait(p_hndl->sd_port, time_out) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+        return _sd_write_byte_error(p_hndl);
+    }
+
+    /* ---- check errors but for timeout ---- */
+    if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+    {
+        _sd_check_info2_err(p_hndl);
+        if ( SD_TIMEOUT_ERASE_CMD == time_out )
+        {
+            /* force erase  */
+            if (SD_ERR_CARD_TOE == p_hndl->error)
+            {
+                /* force erase timeout  */
+                _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ERR);
+                if (_sd_wait_rbusy(p_hndl, 10000000) != SD_OK)
+                {
+                    return _sd_write_byte_error(p_hndl);
+                }
+            }
+            else
+            {
+                return _sd_write_byte_error(p_hndl);
+            }
+        }
+        else
+        {
+            return _sd_write_byte_error(p_hndl);
+        }
+    }
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0x0000);  /* clear All end bit */
+
+    /* disable all interrupts */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BWE);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_write_byte
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_write_byte_error
+ * Description  : write byte data error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_write_byte_error(st_sdhndl_t *p_hndl)
+{
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);               /* stop data transfer   */
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0x0000);  /* clear All end bit    */
+
+    /* disable all interrupts */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BWE);
+
+    return SD_ERR;
+}
+/******************************************************************************
+ End of function _sd_write_byte_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_calc_erase_sector
+ * Description  : calculate erase sector.
+ *              : This function calculate erase sector for SD Phy Ver2.0.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : transfer type is PIO
+ *****************************************************************************/
+int32_t _sd_calc_erase_sector(st_sdhndl_t *p_hndl)
+{
+    uint16_t au;
+    uint16_t erase_size;
+
+    if ((p_hndl->scr[0] & 0x0f00) == 0x0200)
+    {
+        /* AU is not defined,set to fixed value */
+        p_hndl->erase_sect = SD_ERASE_SECTOR;
+
+        /* get AU size */
+        au = p_hndl->sdstatus[5] >> 12;
+
+        if ( (au > 0) && (au < 0x0a) )
+        {
+            /* get AU_SIZE(sectors) */
+            p_hndl->erase_sect = ((8 * 1024) / 512) << au;
+
+            /* get ERASE_SIZE */
+            erase_size = (p_hndl->sdstatus[5] << 8) | (p_hndl->sdstatus[6] >> 8);
+            if (0 != erase_size)
+            {
+                p_hndl->erase_sect *= erase_size;
+            }
+        }
+
+    }
+    else
+    {
+        /* If card is not Ver2.0,it use ERASE_BLK_LEN in CSD *//* DO NOTHING */
+        ;
+    }
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_calc_erase_sector
+ *****************************************************************************/
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_read.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,699 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_read.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : Card read
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02     Support for OS
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static int32_t _sd_read_sect_error(st_sdhndl_t *p_hndl, int32_t mode);
+static int32_t _sd_single_read(st_sdhndl_t *p_hndl, uint8_t *buff, uint32_t psn, int32_t mode);
+static int32_t _sd_single_read_error(st_sdhndl_t *p_hndl, int32_t mode);
+
+/******************************************************************************
+ * Function Name: sd_read_sect
+ * Description  : read sector data from card.
+ *              : read sector data from physical sector number (=psn) by the
+ *              : number of sectors (=cnt)
+ *              : if SD Driver mode is SD_MODE_SW, data transfer by
+ *              : sddev_read_data function
+ *              : if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint8_t *buff   : read data buffer
+ *              : uint32_t psn    : read physical sector number
+ *              : int32_t cnt     : number of read sectors
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_read_sect(int32_t sd_port, uint8_t *buff, uint32_t psn, int32_t cnt)
+{
+
+    st_sdhndl_t *p_hndl;
+    int32_t     i;
+    int32_t     j;
+    int32_t     ret;
+    int32_t     mode = SD_MODE_SW;
+    int32_t     mmc_lastsect = 0;
+    uint64_t    info1_back;
+    uint64_t    opt_back;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* Cast to an appropriate type */
+    if (NULL == buff)
+    {
+        return SD_ERR;
+    }
+
+    p_hndl->error = SD_OK;
+
+    /* ---- check card is mounted ---- */
+    if (SD_MOUNT_UNLOCKED_CARD != p_hndl->mount)
+    {
+        _sd_set_err(p_hndl, SD_ERR);
+        return p_hndl->error; /* not mounted yet */
+    }
+
+    /* ---- is stop compulsory? ---- */
+    if (p_hndl->stop)
+    {
+        p_hndl->stop = 0;
+        _sd_set_err(p_hndl, SD_ERR_STOP);
+        return SD_ERR_STOP;
+    }
+
+    /* ---- is card existed? ---- */
+    if (_sd_check_media(p_hndl) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_NO_CARD);  /* no card */
+        return SD_ERR_NO_CARD;
+    }
+
+    /* access area check */
+    if ((psn >= p_hndl->card_sector_size) || ((psn + cnt) > p_hndl->card_sector_size))
+    {
+        _sd_set_err(p_hndl, SD_ERR);
+        return p_hndl->error; /* out of area */
+    }
+
+    /* if DMA transfer, buffer boundary is octlet unit */
+    if ((p_hndl->trans_mode & SD_MODE_DMA) && (((uint32_t)buff & 0x07u) == 0))
+    {
+        mode = SD_MODE_DMA; /* set DMA mode */
+    }
+
+    /* transfer size is fixed (512 bytes) */
+    SD_OUTP(p_hndl, SD_SIZE, (uint64_t)512);
+
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return p_hndl->error;
+    }
+
+    /* ==== check status precede read operation ==== */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+            == SD_OK)
+    {
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)  /* not transfer state */
+        {
+            p_hndl->error = SD_ERR;
+            return _sd_read_sect_error(p_hndl, mode);
+        }
+    }
+    else    /* SDHI error */
+    {
+        return _sd_read_sect_error(p_hndl, mode);
+    }
+
+    /* ==== execute multiple transfer by 256 sectors ==== */
+    for (i = cnt; i > 0 ;
+            i -= TRANS_SECTORS, psn += TRANS_SECTORS, buff += (TRANS_SECTORS * 512))
+    {
+
+        /* ---- is card existed? ---- */
+        if (_sd_check_media(p_hndl) != SD_OK)
+        {
+            _sd_set_err(p_hndl, SD_ERR_NO_CARD);  /* no card */
+            return _sd_read_sect_error(p_hndl, mode);
+        }
+
+        /* set transfer sector numbers to SD_SECCNT */
+        cnt = i - TRANS_SECTORS;
+        if (cnt < 0)    /* remaining sectors are less than TRANS_SECTORS */
+        {
+            cnt = i;
+        }
+        else
+        {
+            cnt = TRANS_SECTORS;
+        }
+
+        if (cnt <= 2)
+        {
+            /* disable SD_SECCNT */
+            SD_OUTP(p_hndl, SD_STOP, 0x0000);
+            for (j = cnt; j > 0; j--, psn++, buff += 512)
+            {
+                ret = _sd_single_read(p_hndl, buff, psn, mode);
+                if (SD_OK != ret)
+                {
+                    /* Cast to an appropriate type */
+                    opt_back = SD_INP(p_hndl, SD_OPTION);
+
+                    /* Cast to an appropriate type */
+                    SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RESET);
+
+                    /* Cast to an appropriate type */
+                    SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RELEASED);
+
+                    /* Cast to an appropriate type */
+                    SD_OUTP(p_hndl, SD_OPTION, opt_back);
+                    break;
+                }
+            }
+
+            /* ---- halt clock ---- */
+            _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+            return p_hndl->error;
+        }
+
+        /* enable SD_SECCNT */
+        SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0100);
+
+        /* issue CMD12 not automatically, if MMC last sector access */
+        mmc_lastsect = 0;
+        if ((SD_MEDIA_MMC == (p_hndl->media_type)) && ((psn + cnt) == (p_hndl->card_sector_size)))
+        {
+            mmc_lastsect = 1;
+        }
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_SECCNT, (uint64_t)cnt);
+
+        /* ---- enable RespEnd and ILA ---- */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_RESP, 0);
+
+        /* issue CMD18 (READ_MULTIPLE_BLOCK) */
+        if (0 != mmc_lastsect)   /* MMC last sector access */
+        {
+            if (_sd_send_mcmd(p_hndl, CMD18 | SDR104_READ_CMD, SET_ACC_ADDR) != SD_OK)
+            {
+                return _sd_read_sect_error(p_hndl, mode);
+            }
+        }
+        else
+        {
+            if (_sd_send_mcmd(p_hndl, CMD18, SET_ACC_ADDR) != SD_OK)
+            {
+                return _sd_read_sect_error(p_hndl, mode);
+            }
+        }
+
+        /* ---- disable RespEnd and ILA ---- */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+
+        if (SD_MODE_SW == mode) /* ==== PIO ==== */
+        {
+            /* enable All end, BRE and errors */
+            _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BRE);
+
+            /* software data transfer */
+            ret = _sd_software_trans(p_hndl, buff, cnt, SD_TRANS_READ);
+        }
+        else    /* ==== DMA ==== */
+        {
+            /* disable card ins&rem interrupt for FIFO */
+            info1_back = (uint64_t)(p_hndl->int_info1_mask & SD_INFO1_MASK_DET_CD);
+
+            /* Cast to an appropriate type */
+            _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DET_CD, 0);
+
+            /* enable All end and errors */
+            _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_ERR);
+
+            /* ---- initialize DMAC ---- */
+            if (sddev_init_dma(sd_port, (uint32_t)buff, SD_TRANS_READ) != SD_OK)
+            {
+                _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+                return _sd_read_sect_error(p_hndl, mode);
+            }
+
+            /* DMA data transfer */
+            ret = _sd_dma_trans(p_hndl, cnt);
+
+            _sd_set_int_mask(p_hndl, info1_back, 0);
+        }
+
+        if (SD_OK != ret)
+        {
+            return _sd_read_sect_error(p_hndl, mode);
+        }
+
+        /* ---- wait All end interrupt ---- */
+        if (sddev_int_wait(sd_port, SD_TIMEOUT_RESP) != SD_OK)
+        {
+            _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+            return _sd_read_sect_error(p_hndl, mode);
+        }
+
+        /* ---- check errors ---- */
+        if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+        {
+            _sd_check_info2_err(p_hndl);
+            return _sd_read_sect_error(p_hndl, mode);
+        }
+
+        /* clear All end bit */
+        _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0x0000);
+
+        /* disable All end, BRE and errors */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BRE);
+
+        if (mmc_lastsect)
+        {
+            if (_sd_card_send_cmd_arg(p_hndl, 12, SD_RSP_R1B, 0, 0) != SD_OK)
+            {
+                /* check OUT_OF_RANGE error */
+                /* ignore errors during last block access */
+                if (p_hndl->resp_status & 0xffffe008ul)
+                {
+                    if ((psn + cnt) != p_hndl->card_sector_size)
+                    {
+                        return _sd_read_sect_error(p_hndl, mode);  /* but for last block */
+                    }
+                    if (p_hndl->resp_status & 0x7fffe008ul)
+                    {
+                        return _sd_read_sect_error(p_hndl, mode);  /* not OUT_OF_RANGE error */
+                    }
+
+                    /* clear OUT_OF_RANGE error */
+                    p_hndl->resp_status &= 0x1f00u;
+                    p_hndl->error = SD_OK;
+                }
+                else    /* SDHI error, ex)timeout error so on */
+                {
+                    return _sd_read_sect_error(p_hndl, mode);
+                }
+            }
+        }
+
+        /* ==== check status after read operation ==== */
+        if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+                != SD_OK)
+        {
+            /* check OUT_OF_RANGE error */
+            /* ignore errors during last block access */
+            if (p_hndl->resp_status & 0xffffe008ul)
+            {
+                if ((psn + cnt) != p_hndl->card_sector_size)
+                {
+                    return _sd_read_sect_error(p_hndl, mode);  /* but for last block */
+                }
+                if (p_hndl->resp_status & 0x7fffe008ul)
+                {
+                    return _sd_read_sect_error(p_hndl, mode);  /* not OUT_OF_RANGE error */
+                }
+
+                /* clear OUT_OF_RANGE error */
+                p_hndl->resp_status &= 0x1f00u;
+                p_hndl->error = SD_OK;
+            }
+            else    /* SDHI error, ex)timeout error so on */
+            {
+                return _sd_read_sect_error(p_hndl, mode);
+            }
+        }
+
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)
+        {
+            p_hndl->error = SD_ERR;
+            return _sd_read_sect_error(p_hndl, mode);
+        }
+
+        /* ---- is stop compulsory? ---- */
+        if (p_hndl->stop)
+        {
+            p_hndl->stop = 0;
+
+            /* data transfer stop (issue CMD12) */
+            SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);
+            i = 0;  /* set zero to break loop */
+            _sd_set_err(p_hndl, SD_ERR_STOP);
+        }
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function sd_read_sect
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_read_sect_error
+ * Description  : read sector data error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t mode        : data transfer mode
+ *              :   SD_MODE_SW  : software
+ *              :   SD_MODE_DMA : DMA
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_read_sect_error(st_sdhndl_t *p_hndl, int32_t mode)
+{
+    int32_t  error;
+    uint64_t sd_option;
+    uint64_t sd_clk_ctrl;
+
+    if (SD_MODE_DMA == mode)
+    {
+        /* Cast to an appropriate type */
+        (void)sddev_disable_dma((int32_t)(p_hndl->sd_port)); /* disable DMA */
+
+        /* reset DMAC */
+        error = sddev_reset_dma((int32_t)(p_hndl->sd_port));
+        if (SD_OK != error)
+        {
+            /* DO NOTHING */
+            ;
+        }
+    }
+    mode = p_hndl->error;
+
+    /* ---- clear error bits ---- */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* ---- disable all interrupts ---- */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* Cast to an appropriate type */
+    if ((SD_INP(p_hndl, SD_INFO2) & SD_INFO2_MASK_CBSY) == SD_INFO2_MASK_CBSY)
+    {
+        /* ---- enable All end ---- */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0);
+
+        /* ---- data transfer stop (issue CMD12) ---- */
+        SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);
+
+        /* ---- wait All end ---- */
+        sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_RESP);
+
+        /* Cast to an appropriate type */
+        _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+        /* Cast to an appropriate type */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0);
+
+        sddev_loc_cpu(p_hndl->sd_port);
+
+        /* Cast to an appropriate type */
+        sd_option   = SD_INP(p_hndl, SD_OPTION);
+
+        /* Cast to an appropriate type */
+        sd_clk_ctrl = SD_INP(p_hndl, SD_CLK_CTRL);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RESET);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RELEASED);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_STOP, 0x0000);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_OPTION, sd_option);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_CLK_CTRL, sd_clk_ctrl);
+        sddev_unl_cpu(p_hndl->sd_port);
+    }
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_STOP, 0x0000);
+
+    /* Check Current State */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000) == SD_OK)
+    {
+        /* not transfer state? */
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)
+        {
+            /* if not tran state, issue CMD12 to transit the SD card to tran state */
+            _sd_card_send_cmd_arg(p_hndl, CMD12, SD_RSP_R1B, p_hndl->rca[0], 0x0000);
+
+            /* not check error because already checked */
+        }
+    }
+
+    p_hndl->error = mode;
+
+    /* Cast to an appropriate type */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_read_sect_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_single_read
+ * Description  : read sector data from card by single block transfer.
+ *              : read sector data from physical sector number (=psn) by the
+ *              : single block transfer
+ *              : if SD Driver mode is SD_MODE_SW, data transfer by
+ *              : sddev_read_data function
+ *              : if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint8_t *buff       : read data buffer
+ *              : uint32_t psn        : read physical sector number
+ *              : int32_t mode        : data transfer mode
+ *              :   SD_MODE_SW  : software
+ *              :   SD_MODE_DMA : DMA
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_single_read(st_sdhndl_t *p_hndl, uint8_t *buff, uint32_t psn,
+                                int32_t mode)
+{
+    int32_t  ret;
+    uint64_t info1_back;
+
+    /* ---- enable RespEnd and ILA ---- */
+    _sd_set_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+
+    /* issue CMD17 (READ_SINGLE_BLOCK) */
+    if (_sd_send_mcmd(p_hndl, CMD17, SET_ACC_ADDR) != SD_OK)
+    {
+        return _sd_single_read_error(p_hndl, mode);
+    }
+
+    /* ---- disable RespEnd and ILA ---- */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+
+    if (SD_MODE_SW == mode) /* ==== PIO ==== */
+    {
+        /* enable All end, BRE and errors */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BRE);
+
+        /* software data transfer */
+        ret = _sd_software_trans(p_hndl, buff, 1, SD_TRANS_READ);
+    }
+    else    /* ==== DMA ==== */
+    {
+        /* disable card ins&rem interrupt for FIFO */
+        info1_back = (uint64_t)(p_hndl->int_info1_mask & SD_INFO1_MASK_DET_CD);
+
+        /* Cast to an appropriate type */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DET_CD, 0);
+
+        /* enable All end and errors */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_ERR);
+
+        /* ---- initialize DMAC ---- */
+        if (sddev_init_dma(p_hndl->sd_port, (uint32_t)buff, SD_TRANS_READ) != SD_OK)
+        {
+            _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+            return _sd_single_read_error(p_hndl, mode);
+        }
+
+        /* DMA data transfer */
+        ret = _sd_dma_trans(p_hndl, 1);
+
+        _sd_set_int_mask(p_hndl, info1_back, 0);
+    }
+
+    if (SD_OK != ret)
+    {
+        return _sd_single_read_error(p_hndl, mode);
+    }
+
+    /* ---- wait All end interrupt ---- */
+    if (sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_RESP) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+        return _sd_single_read_error(p_hndl, mode);
+    }
+
+    /* ---- check errors ---- */
+    if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+    {
+        _sd_check_info2_err(p_hndl);
+        return _sd_single_read_error(p_hndl, mode);
+    }
+
+    /* clear All end bit */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0x0000);
+
+    /* disable All end, BRE and errors */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BRE);
+
+
+    /* ==== check status after read operation ==== */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000) != SD_OK)
+    {
+        /* check OUT_OF_RANGE error */
+        /* ignore errors during last block access */
+        if (p_hndl->resp_status & 0xffffe008ul)
+        {
+            if ((psn + 1) != p_hndl->card_sector_size)
+            {
+                return _sd_single_read_error(p_hndl, mode);  /* but for last block */
+            }
+            if (p_hndl->resp_status & 0x7fffe008ul)
+            {
+                return _sd_single_read_error(p_hndl, mode);  /* not OUT_OF_RANGE error */
+            }
+
+            /* clear OUT_OF_RANGE error */
+            p_hndl->resp_status &= 0x1f00u;
+            p_hndl->error = SD_OK;
+        }
+        else    /* SDHI error, ex)timeout error so on */
+        {
+            return _sd_single_read_error(p_hndl, mode);
+        }
+    }
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_single_read
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_single_read_error
+ * Description  : read sector data error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t mode        : data transfer mode
+ *              :   SD_MODE_SW  : software
+ *              :   SD_MODE_DMA : DMA
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_single_read_error(st_sdhndl_t *p_hndl, int32_t mode)
+{
+    int32_t error;
+
+    if (SD_MODE_DMA == mode)
+    {
+        /* Cast to an appropriate type */
+        (void)sddev_disable_dma((int32_t)(p_hndl->sd_port));   /* disable DMA */
+
+        /* reset DMAC */
+        error = sddev_reset_dma((int32_t)(p_hndl->sd_port));
+        if (SD_OK != error)
+        {
+            /* DO NOTHING */
+            ;
+        }
+    }
+
+    error = p_hndl->error;
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* Cast to an appropriate type */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* Cast to an appropriate type */
+    _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0);
+
+    /* Cast to an appropriate type */
+    _sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000);
+
+    /* Cast to an appropriate type */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    p_hndl->error = error;
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_single_read_error
+ *****************************************************************************/
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_trns.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,183 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_trns.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : Data transfer
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_software_trans
+ * Description  : transfer data by software.
+ *              : transfer data to/from card by software
+ *              : this operations are used multiple command data phase
+ *              : if dir is SD_TRANS_READ, data is from card to host
+ *              : if dir is SD_TRANS_WRITE, data is from host to card
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint8_t *buff       : destination/source data buffer
+ *              : int32_t cnt         : number of transfer bytes
+ *              : int32_t dir         : transfer direction
+ * Return Value : p_hndl->error  : SD handle error value
+ *              : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : transfer finished, check CMD12 sequence refer to All end
+ *****************************************************************************/
+int32_t _sd_software_trans(st_sdhndl_t *p_hndl, uint8_t *buff, int32_t cnt, int32_t dir)
+{
+    int32_t j;
+    int32_t (*func)(int32_t sd_port, uint8_t *buff, uint32_t reg_addr, int32_t num);
+
+    if (SD_TRANS_READ == dir)
+    {
+        func = sddev_read_data;
+    }
+    else
+    {
+        func = sddev_write_data;
+    }
+
+    for (j = cnt; j > 0 ; j--)
+    {
+        /* ---- wait BWE/BRE interrupt ---- */
+        if (sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_MULTIPLE) != SD_OK)
+        {
+            _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+            break;
+        }
+
+        /* Cast to an appropriate type */
+        if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+        {
+            _sd_check_info2_err(p_hndl);
+            break;
+        }
+
+        if (SD_TRANS_READ == dir)
+        {
+            /* Cast to an appropriate type */
+            _sd_clear_info(p_hndl, 0x0000, SD_INFO2_MASK_RE); /* clear BRE and errors bit */
+        }
+        else
+        {
+            /* Cast to an appropriate type */
+            _sd_clear_info(p_hndl, 0x0000, SD_INFO2_MASK_WE); /* clear BWE and errors bit */
+        }
+
+        /* write/read to/from SD_BUF by 1 sector */
+        if ((*func)(p_hndl->sd_port, buff, (uint32_t)p_hndl->reg_base + SD_BUF0, 512) != SD_OK)
+        {
+            _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+            break;
+        }
+
+        /* update buffer */
+        buff += 512;
+
+    }
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_software_trans
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_dma_trans
+ * Description  : transfer data by DMA.
+ *              : transfer data to/from card by DMA
+ *              : this operations are multiple command data phase
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t cnt         : number of transfer bytes
+ * Return Value : p_hndl->error  : SD handle error value
+ *              : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : transfer finished, check CMD12 sequence refer to All end
+ *****************************************************************************/
+int32_t _sd_dma_trans(st_sdhndl_t *p_hndl, int32_t cnt)
+{
+    /* ---- check DMA transfer end  --- */
+    /* timeout value is depend on transfer size */
+    if (sddev_wait_dma_end((int32_t)(p_hndl->sd_port), cnt * 512) != SD_OK)
+    {
+        /* Cast to an appropriate type */
+        (void)sddev_disable_dma((int32_t)(p_hndl->sd_port));   /* disable DMAC */
+        (void)_sd_set_err(p_hndl, SD_ERR_CPU_IF);
+        return p_hndl->error;
+    }
+
+    /* ---- disable DMAC ---- */
+    if (sddev_disable_dma((int32_t)(p_hndl->sd_port)) != SD_OK)
+    {
+        /* Cast to an appropriate type */
+        (void)_sd_set_err(p_hndl, SD_ERR_CPU_IF);
+        return p_hndl->error;
+    }
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_dma_trans
+ *****************************************************************************/
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_util.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1974 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_util.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : Function setting
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static uint32_t s_next;       /* Volume ID Number */
+
+static int32_t _sd_standby_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_active_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_inactive_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_reget_reg_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_lock_unlock_error(st_sdhndl_t *p_hndl);
+static int32_t _sd_set_tmpwp_error(st_sdhndl_t *p_hndl);
+static uint8_t _sd_calc_crc(uint8_t *data, int32_t len);
+
+/******************************************************************************
+ * Function Name: _sd_set_clock
+ * Description  : control SD clock.
+ *              : supply or halt SD clock
+ *              : if enable is SD_CLOCK_ENABLE, supply SD clock
+ *              : if enable is SD_CLOCK_DISKABLE, halt SD clock
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t clock       : SD clock frequency
+ *              : int32_t enable      : supply or halt SD clock
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_set_clock(st_sdhndl_t *p_hndl, int32_t clock, int32_t enable)
+{
+    uint32_t div;
+    int32_t  i;
+
+    if (SD_CLOCK_ENABLE == enable)
+    {
+        /* convert clock frequency to clock divide ratio */
+        div = sddev_get_clockdiv(p_hndl->sd_port, clock);
+
+        if ((div > SD_DIV_512) && (SD_DIV_1 != div))
+        {
+            _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+            return SD_ERR;
+        }
+
+        /* SCLKEN = 0 */
+        SD_OUTP(p_hndl, SD_CLK_CTRL, (SD_INP(p_hndl, SD_CLK_CTRL) & (~SD_CLK_CTRL_SCLKEN)));
+
+        /* write DIV[7:0] */
+        SD_OUTP(p_hndl, SD_CLK_CTRL, ((SD_INP(p_hndl, SD_CLK_CTRL) & (~0x00FFuL)) | div));
+
+        /* SCLKEN = 1 */
+        SD_OUTP(p_hndl, SD_CLK_CTRL, (SD_INP(p_hndl, SD_CLK_CTRL) | SD_CLK_CTRL_SCLKEN));
+
+    }
+    else
+    {
+        for (i = 0; i < SCLKDIVEN_LOOP_COUNT; i++)
+        {
+#ifdef USE_INFO2_CBSY
+            /* Cast to an appropriate type */
+            if ( (SD_INP(p_hndl, SD_INFO2) & SD_INFO2_MASK_CBSY) == 0 )
+            {
+                break;
+            }
+#else
+            /* Cast to an appropriate type */
+            if (SD_INP(p_hndl, SD_INFO2) & SD_INFO2_MASK_SCLKDIVEN)
+            {
+                break;
+            }
+#endif
+        }
+        if (SCLKDIVEN_LOOP_COUNT == i)
+        {
+            p_hndl->error = SD_ERR_CBSY_ERROR;
+        }
+
+        /* SCLKEN = 0  halt */
+        SD_OUTP(p_hndl, SD_CLK_CTRL, (SD_INP(p_hndl, SD_CLK_CTRL) & (~SD_CLK_CTRL_SCLKEN)));
+
+    }
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_set_clock
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_set_port
+ * Description  : control data bus width.
+ *              : change data bus width
+ *              : if port is SD_PORT_SERIAL, set data bus width 1bit
+ *              : if port is SD_PORT_PARALEL, set data bus width 4bits
+ *              : change between 1bit and 4bits by ACMD6
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t port        : setting bus with
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : before execute this function, check card supporting bus
+ *              : width
+ *              : SD memory card is 4bits support mandatory
+ *****************************************************************************/
+int32_t _sd_set_port(st_sdhndl_t *p_hndl, int32_t port)
+{
+    uint64_t reg;
+    uint16_t arg;
+
+    if (p_hndl->media_type & SD_MEDIA_SD)    /* SD */
+    {
+        /* ---- check card state ---- */
+        if ((p_hndl->resp_status & RES_STATE) == STATE_TRAN)  /* transfer state */
+        {
+            if (SD_PORT_SERIAL == port)
+            {
+                arg = ARG_ACMD6_1BIT;
+            }
+            else
+            {
+                arg = ARG_ACMD6_4BIT;
+            }
+
+            /* ==== change card bus width (issue ACMD6) ==== */
+            if (_sd_send_acmd(p_hndl, ACMD6, 0, arg) != SD_OK)
+            {
+                return SD_ERR;
+            }
+            if (_sd_get_resp(p_hndl, SD_RSP_R1) != SD_OK)
+            {
+                return SD_ERR;
+            }
+        }
+    }
+
+    /* ==== change SDHI bus width ==== */
+    if (SD_PORT_SERIAL == port) /* 1bit */
+    {
+        sddev_set_port(p_hndl->sd_port, port);
+
+        /* Cast to an appropriate type */
+        reg = SD_INP(p_hndl, SD_OPTION);
+
+        /* Cast to an appropriate type */
+        reg |= SD_OPTION_WIDTH;
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_OPTION, reg);
+    }
+    else    /* 4bits */
+    {
+        /* Cast to an appropriate type */
+        reg = SD_INP(p_hndl, SD_OPTION);
+
+        /* Cast to an appropriate type */
+        reg &= (~SD_OPTION_WIDTH_MASK);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_OPTION, reg);
+        sddev_set_port(p_hndl->sd_port, port);
+    }
+
+    /* Cast to an appropriate type */
+    p_hndl->if_mode = (uint8_t)port;
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_set_port
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_iswp
+ * Description  : check hardware write protect.
+ *              : check hardware write protect refer to SDHI register
+ *              : if WP pin is disconnected to SDHI, return value has no
+ *              : meaning
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : p_hndl->write_protect : write protected state
+ *****************************************************************************/
+int32_t sd_iswp(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* Cast to an appropriate type */
+    return (int32_t)p_hndl->write_protect;
+}
+/******************************************************************************
+ End of function sd_iswp
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_iswp
+ * Description  : check hardware write protect refer to SDHI register
+ *              : if WP pin is disconnected to SDHI, return value has no
+ *              : meaning
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_WP_OFF (0): not write protected
+ *              : SD_WP_HW  (1): write protected
+ * Remark       : don't check CSD write protect bits and ROM card
+ *****************************************************************************/
+int32_t _sd_iswp(st_sdhndl_t *p_hndl)
+{
+    int32_t wp;
+    int32_t layout;
+
+    /* Cast to an appropriate type */
+    layout = sddev_wp_layout((int32_t)(p_hndl->sd_port));
+
+    if (SD_OK == layout)
+    {
+        /* ===== check SD_INFO1 WP bit ==== */
+        wp = (int32_t)(((~SD_INPLL(p_hndl, SD_INFO1)) & SD_INFO1_MASK_WP) >> 7);
+    }
+    else
+    {
+        /* Cast to an appropriate type */
+        wp = (int32_t)SD_WP_OFF;
+    }
+    return wp;
+}
+/******************************************************************************
+ End of function _sd_iswp
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_bit_search
+ * Description  : get bit information.
+ *              : check every bits of argument (data) from LSB
+ *              : return first bit whose value is 1'b
+ *              : bit number is big endian (MSB is 0)
+ * Arguments    : uint16_t data : checked data
+ * Return Value : not less than 0 : bit number has 1'b
+ *              : -1 : no bit has 1'b
+ * Remark       : just 16bits value can be applied
+ *****************************************************************************/
+int32_t _sd_bit_search(uint16_t data)
+{
+    int32_t i;
+
+    for (i = 15; i >= 0 ; i--)
+    {
+        if (data & 1u)
+        {
+            return i;
+        }
+        data >>= 1;
+    }
+
+    return -1;
+}
+/******************************************************************************
+ End of function _sd_bit_search
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_set_err
+ * Description  : set errors information.
+ *              : set error information (=error) to SD Handle member
+ *              : (=p_hndl->error)
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t error       : setting error information
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if p_hndl->error was already set, no overwrite it
+ *****************************************************************************/
+int32_t _sd_set_err(st_sdhndl_t *p_hndl, int32_t error)
+{
+    if (SD_OK == p_hndl->error)
+    {
+        p_hndl->error = error;
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_set_err
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_stop
+ * Description  : stop operations compulsory.
+ *              : set flag (=SD handle member stop) stop operations compulsory
+ *              : if this flag is set, read, write operations is stopped
+ *              : this flag is used for card detect/removal interrupt detection
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : none
+ *****************************************************************************/
+void sd_stop(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return; /* not initilized */
+    }
+
+    p_hndl->stop = 1;
+}
+/******************************************************************************
+ End of function sd_stop
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_type
+ * Description  : get card type.
+ *              : get mounting card type, current and supported speed mode
+ *              : and capacity type
+ *              : (if SD memory card)
+ *              : following card types are defined
+ *              : SD_MEDIA_UNKNOWN : unknown media
+ *              : SD_MEDIA_MMC     : MMC card
+ *              : SD_MEDIA_SD      : SD Memory card
+ * Arguments    : int32_t  sd_port : channel no (0 or 1)
+ *              : uint16_t *type   : mounting card type
+ *              : uint16_t *speed  : speed mode
+ *              : uint8_t  *capa   : card capacity
+ *              :   Standard capacity:0, High capacity:1
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if pointer has NULL ,the value isn't returned
+ *              : only SD memory card, speed mode has meaning
+ *****************************************************************************/
+int32_t sd_get_type(int32_t sd_port, uint16_t *type, uint16_t *speed, uint8_t *capa)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (type)
+    {
+        *type = p_hndl->media_type;
+    }
+    if (speed)
+    {
+        *speed = p_hndl->speed_mode;
+    }
+    if (capa)
+    {
+        *capa = p_hndl->csd_structure;
+    }
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_get_type
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_size
+ * Description  : get card size.
+ *              : get total sectors of user area calculated from CSD
+ *              : get total sectors of protect area calculated from CSD and
+ *              : SD STAUS
+ * Arguments    : int32_t sd_port   : channel no (0 or 1)
+ *              : uint32_t *user    : user area size
+ *              : uint32_t *protect : protect area size
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if pointer has NULL ,the value isn't returned
+ *              : return just the number of all sectors
+ *              : only SD memory card, protect area size has meaning
+ *****************************************************************************/
+int32_t sd_get_size(int32_t sd_port, uint32_t *user, uint32_t *protect)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (user)
+    {
+        *user = p_hndl->card_sector_size;
+    }
+    if (protect)
+    {
+        *protect = p_hndl->prot_sector_size;
+    }
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_get_size
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_get_size
+ * Description  : get card size.
+ *              : get memory card size
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t area   : memory area (bit0:user area, bit1:protect area)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : protect area is just the number of all sectors
+ *****************************************************************************/
+int32_t _sd_get_size(st_sdhndl_t *p_hndl, uint32_t area)
+{
+    uint32_t c_mult;
+    uint32_t c_size;
+    uint32_t read_bl_len;
+
+    /* ---- READ BL LEN ---- */
+    read_bl_len = (p_hndl->csd[3] & 0x0f00u) >> 8;
+
+    /* ---- C_SIZE_MULT ---- */
+    c_mult = ((p_hndl->csd[5] & 0x0380u) >> 7);
+
+    if (area & SD_PROT_AREA)
+    {
+        /* calculate the number of all sectors */
+        if ((SD_MODE_VER2X == p_hndl->sup_ver) && (0x01 == p_hndl->csd_structure))
+        {
+            /* Cast to an appropriate type */
+            p_hndl->prot_sector_size = (((uint32_t)p_hndl->sdstatus[2] << 16u) |
+
+                                        /* Cast to an appropriate type */
+                                        ((uint32_t)p_hndl->sdstatus[3])) / 512;
+        }
+        else
+        {
+            /* Cast to an appropriate type */
+            p_hndl->prot_sector_size = (p_hndl->sdstatus[3] *
+
+                                        /* Cast to an appropriate type */
+                                        ((uint32_t)1 << (c_mult + 2)) *
+
+                                        /* Cast to an appropriate type */
+                                        ((uint32_t)1 << read_bl_len)) / 512;
+        }
+    }
+
+    if (area & SD_USER_AREA)
+    {
+        if ((SD_MODE_VER2X == p_hndl->sup_ver) && (0x01 == p_hndl->csd_structure))
+        {
+            /* Cast to an appropriate type */
+            c_size = ((((uint32_t)p_hndl->csd[4] & 0x3fffu) << 8u) |
+
+                    /* Cast to an appropriate type */
+                    (((uint32_t)p_hndl->csd[5] & 0xff00u) >> 8u));
+
+            /* memory capacity = C_SIZE*512K byte */
+            /* sector_size = memory capacity/512 */
+            p_hndl->card_sector_size = ((c_size + 1) << 10u);
+        }
+        else
+        {
+            /* ---- C_SIZE ---- */
+            c_size = ((p_hndl->csd[3] & 0x0003u) << 10) |
+                        ((p_hndl->csd[4] & 0xffc0u) >> 6);
+
+            /* calculate the number of all sectors */
+            p_hndl->card_sector_size = ((uint32_t)(c_size + 1) *
+
+                                    /* Cast to an appropriate type */
+                                    ((uint32_t)1 << (c_mult + 2)) * ((uint32_t)1
+                                        << read_bl_len)) / 512;
+        }
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_get_size
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_error
+ * Description  : get SD Driver errors (=p_hndl->error) and return it
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : p_hndl->error
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_get_error(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function sd_get_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_reg
+ * Description  : get card register.
+ *              : get card register value
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint8_t *ocr    : OCR register address
+ *              : uint8_t *cid    : CID register address
+ *              : uint8_t *csd    : CSD register address
+ *              : uint8_t *dsr    : DSR register address
+ *              : uint8_t *scr    : SCR register address
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if pointer has NULL ,the register value isn't returned
+ *****************************************************************************/
+int32_t sd_get_reg(int32_t sd_port, uint8_t *ocr, uint8_t *cid, uint8_t *csd,
+                    uint8_t *dsr, uint8_t *scr)
+{
+    st_sdhndl_t *p_hndl;
+    uint32_t    i;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (ocr)
+    {
+        for (i = 0; i < 2; ++i)
+        {
+            /* Cast to an appropriate type */
+            *ocr++ = (uint8_t)(p_hndl->ocr[i] >> 8);
+
+            /* Cast to an appropriate type */
+            *ocr++ = (uint8_t)p_hndl->ocr[i];
+        }
+    }
+    if (cid)
+    {
+        for (i = 0; i < 8; ++i)
+        {
+            /* Cast to an appropriate type */
+            *cid++ = (uint8_t)(p_hndl->cid[i] >> 8);
+
+            /* Cast to an appropriate type */
+            *cid++ = (uint8_t)p_hndl->cid[i];
+        }
+    }
+    if (csd)
+    {
+        for (i = 0; i < 8; ++i)
+        {
+            /* Cast to an appropriate type */
+            *csd++ = (uint8_t)(p_hndl->csd[i] >> 8);
+
+            /* Cast to an appropriate type */
+            *csd++ = (uint8_t)p_hndl->csd[i];
+        }
+    }
+    if (dsr)
+    {
+        /* Cast to an appropriate type */
+        *dsr++ = (uint8_t)(p_hndl->dsr[0] >> 8);
+
+        /* Cast to an appropriate type */
+        *dsr++ = (uint8_t)p_hndl->dsr[0];
+    }
+    if (scr)
+    {
+        for (i = 0; i < 4; ++i)
+        {
+            /* Cast to an appropriate type */
+            *scr++ = (uint8_t)(p_hndl->scr[i] >> 8);
+
+            /* Cast to an appropriate type */
+            *scr++ = (uint8_t)p_hndl->scr[i];
+        }
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_get_reg
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_rca
+ * Description  : get rca register.
+ *              : get card register value
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint8_t *rca    : RCA register address
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if pointer has NULL ,the register value isn't returned
+ *****************************************************************************/
+int32_t sd_get_rca(int32_t sd_port, uint8_t *rca)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (rca)    /* return high 16bits */
+    {
+        /* Cast to an appropriate type */
+        *rca++ = (uint8_t)(p_hndl->rca[0] >> 8);
+
+        /* Cast to an appropriate type */
+        *rca++ = (uint8_t)p_hndl->rca[0];
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_get_rca
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_sdstatus
+ * Description  : get SD Status register value
+ * Arguments    : int32_t sd_port   : channel no (0 or 1)
+ *              : uint8_t *sdstatus : SD STATUS address
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if pointer has NULL ,the register value isn't returned
+ *****************************************************************************/
+int32_t sd_get_sdstatus(int32_t sd_port, uint8_t *sdstatus)
+{
+    st_sdhndl_t *p_hndl;
+    uint32_t    i;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (sdstatus)
+    {
+        for (i = 0; i < 8; ++i)
+        {
+            /* Cast to an appropriate type */
+            *sdstatus++ = (uint8_t)(p_hndl->sdstatus[i] >> 8);
+
+            /* Cast to an appropriate type */
+            *sdstatus++ = (uint8_t)p_hndl->sdstatus[i];
+        }
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_get_sdstatus
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_speed
+ * Description  : get card speed.
+ *              : get card speed class and performance move
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint8_t *clss   : speed class
+ *              : uint8_t *move   : performance move
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if pointer has NULL ,the register value isn't returned
+ *****************************************************************************/
+int32_t sd_get_speed(int32_t sd_port, uint8_t *clss, uint8_t *move)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (clss)
+    {
+        *clss = p_hndl->speed_class;
+    }
+
+    if (move)
+    {
+        *move = p_hndl->perform_move;
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_get_speed
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_set_seccnt
+ * Description  : set maximum block count per multiple command
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : int16_t sectors : block count
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : maximam block count is constrained from 3 to 32767(0x7fff)
+ *****************************************************************************/
+int32_t sd_set_seccnt(int32_t sd_port, int16_t sectors)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (sectors <= 2)
+    {
+        /* need more than 3 continuous transfer */
+        return SD_ERR;  /* undefined value */
+    }
+
+    p_hndl->trans_sectors = sectors;
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_set_seccnt
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_seccnt
+ * Description  : get block count.
+ *              : get maximum block count per multiple command
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : not less than 0 : block count
+ *              : SD_ERR: end of error
+ * Remark       : maximam block count are constrained from 1 to 65535
+ *****************************************************************************/
+int32_t sd_get_seccnt(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* Cast to an appropriate type */
+    return (int32_t)p_hndl->trans_sectors;
+}
+/******************************************************************************
+ End of function sd_get_seccnt
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_get_ver
+ * Description  : get SDHI and SD Driver versions.
+ *              : get SDHI version from VERSION register
+ *              : get SD Driver version from constant DRIVER NAME
+ * Arguments    : int32_t sd_port    : channel no (0 or 1)
+ *              : uint16_t *sdhi_ver : SDHI version
+ *              : char_t *sddrv_ver  : SD Driver version
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if pointer has NULL ,the value isn't returned
+ *****************************************************************************/
+int32_t sd_get_ver(int32_t sd_port, uint16_t *sdhi_ver, char_t *sddrv_ver)
+{
+    st_sdhndl_t *p_hndl;
+    int32_t     i;
+
+    /* Cast to an appropriate type */
+    char_t  *p_name = (char_t*)DRIVER_NAME;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (sdhi_ver)
+    {
+        /* Cast to an appropriate type */
+        *sdhi_ver = SD_INPLL(p_hndl, VERSION);
+    }
+
+    if (sddrv_ver)
+    {
+        for (i = 0; i < 32; ++i)
+        {
+            *sddrv_ver++ = *p_name++;
+        }
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_get_ver
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_set_cdtime
+ * Description  : set card detect time.
+ *              : set card detect time equal to IMCLK*2^(10+cdtime)
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint16_t cdtime : card detect time interval
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_set_cdtime(int32_t sd_port, uint16_t cdtime)
+{
+    st_sdhndl_t *p_hndl;
+    uint64_t    reg;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (cdtime >= 0x000f)
+    {
+        return SD_ERR;  /* undefined value */
+    }
+
+    /* Cast to an appropriate type */
+    reg = SD_INP(p_hndl, SD_OPTION);
+
+    /* Cast to an appropriate type */
+    reg &= (~(uint64_t)0x000f);
+
+    /* Cast to an appropriate type */
+    reg |= (uint64_t)(cdtime & 0x000fu);
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_OPTION, reg);
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_set_cdtime
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_set_responsetime
+ * Description  : set response timeout.
+ *              : set response timeout equal to IMCLK*2^(13+cdtime)
+ * Arguments    : int32_t sd_port       : channel no (0 or 1)
+ *              : uint16_t responsetime : response timeout interval
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_set_responsetime(int32_t sd_port, uint16_t responsetime)
+{
+    st_sdhndl_t *p_hndl;
+    uint64_t    reg;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    if (responsetime >= 0x0010u)
+    {
+        return SD_ERR;  /* undefined value */
+    }
+
+    /* Cast to an appropriate type */
+    reg = SD_INP(p_hndl, SD_OPTION);
+
+    /* Cast to an appropriate type */
+    reg &= (~SD_OPTION_TOP_MASK);
+
+    if (0x000fu == responsetime)
+    {
+        /* Cast to an appropriate type */
+        reg |= SD_OPTION_TOP_MAX;
+    }
+    else
+    {
+        /* Cast to an appropriate type */
+        reg |= (uint64_t)(((uint64_t)responsetime & 0x000fu) << 4);
+    }
+
+    /* Cast to an appropriate type */
+    SD_OUTP(p_hndl, SD_OPTION, reg);
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_set_responsetime
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_set_buffer
+ * Description  : initialize SD driver work buffer.
+ *              : this buffer is used for mainly MKB process
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : void *buff      : work buffer address
+ *              : uint32_t size   : work buffer size
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ * Remark       : if applied to CPRM, allocating more than 8K bytes
+ *****************************************************************************/
+int32_t sd_set_buffer(int32_t sd_port, void *buff, uint32_t size)
+{
+    st_sdhndl_t  *p_hndl;
+
+    /* check buffer boundary (octlet unit) */
+    if ( 0 != ((uint32_t)buff & 0x00000007u) )
+    {
+        return SD_ERR;
+    }
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* initialize buffer area */
+    p_hndl->p_rw_buff = (uint8_t*)buff;
+
+    /* initialize buffer size */
+    p_hndl->buff_size = size;
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_set_buffer
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_standby
+ * Description  : transfer card to stand-by state.
+ *              : transfer card from transfer state to stand-by state
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_standby(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+    int32_t     ret;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+    p_hndl->error = SD_OK;
+
+    ret = _sd_standby(p_hndl);
+
+    return ret;
+}
+/******************************************************************************
+ End of function sd_standby
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_standby
+ * Description  : transfer card to stand-by state.
+ *              : transfer card from transfer state to stand-by state
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_standby(st_sdhndl_t *p_hndl)
+{
+    int32_t  ret;
+    uint16_t de_rca;
+
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return _sd_standby_error(p_hndl);
+    }
+
+    /* set deselect RCA */
+    de_rca = 0;
+
+    /* ==== state transfer (transfer to stand-by) ==== */
+    ret = _sd_card_send_cmd_arg(p_hndl, CMD7, SD_RSP_R1B, de_rca, 0x0000);
+
+    /* timeout error occured due to no response or response busy */
+    if ((SD_OK != ret) && (SD_ERR_RES_TOE != p_hndl->error))
+    {
+        return _sd_standby_error(p_hndl);
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_standby
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_standby_error
+ * Description  : transfer card to stand-by state error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_standby_error(st_sdhndl_t *p_hndl)
+{
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_standby_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_active
+ * Description  : transfer card to transfer state.
+ *              : transfer card from stand-by state to transfer state
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_active(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+    int32_t     ret;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+    p_hndl->error = SD_OK;
+
+    ret = _sd_active(p_hndl);
+
+    return ret;
+}
+/******************************************************************************
+ End of function sd_active
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_active
+ * Description  : transfer card to transfer state.
+ *              : transfer card from stand-by state to transfer state
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_active(st_sdhndl_t *p_hndl)
+{
+    uint64_t reg;
+
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return _sd_active_error(p_hndl);
+    }
+
+    if (SD_PORT_SERIAL == p_hndl->if_mode)    /* 1bit */
+    {
+        sddev_set_port(p_hndl->sd_port, SD_PORT_SERIAL);
+
+        /* Cast to an appropriate type */
+        reg = SD_INP(p_hndl, SD_OPTION);
+
+        /* Cast to an appropriate type */
+        reg |= SD_OPTION_WIDTH;
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_OPTION, reg);
+    }
+    else    /* 4bits */
+    {
+
+        /* Cast to an appropriate type */
+        reg = SD_INP(p_hndl, SD_OPTION);
+
+        /* Cast to an appropriate type */
+        reg &= (~SD_OPTION_WIDTH_MASK);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_OPTION, reg);
+        sddev_set_port(p_hndl->sd_port, SD_PORT_PARALLEL);
+    }
+
+    /* ==== state transfer (stand-by to transfer) ==== */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD7, SD_RSP_R1B, p_hndl->rca[0], 0x0000)
+            != SD_OK)
+    {
+        return _sd_active_error(p_hndl);
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_active
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_active_error
+ * Description  : transfer card to transfer state error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_active_error(st_sdhndl_t *p_hndl)
+{
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_active_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_inactive
+ * Description  : transfer card to inactive state.
+ *              : transfer card from any state to inactive state
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_inactive(int32_t sd_port)
+{
+    st_sdhndl_t *p_hndl;
+    int32_t     ret;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+    p_hndl->error = SD_OK;
+
+    ret = _sd_inactive(p_hndl);
+
+    return ret;
+}
+/******************************************************************************
+ End of function sd_inactive
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_inactive
+ * Description  : transfer card to inactive state.
+ *              : transfer card from any state to inactive state
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_inactive(st_sdhndl_t *p_hndl)
+{
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return _sd_inactive_error(p_hndl);
+    }
+
+    /* ==== state transfer (transfer to stand-by) ==== */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD15, SD_RSP_NON, p_hndl->rca[0], 0x0000)
+            != SD_OK)
+    {
+        return _sd_inactive_error(p_hndl);
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function _sd_inactive
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_inactive_error
+ * Description  : transfer card to inactive state error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_inactive_error(st_sdhndl_t *p_hndl)
+{
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_inactive_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_reget_reg
+ * Description  : reget register.
+ *              : reget CID or CSD
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint8_t *reg    : reget CID or CSD register address
+ *              : int32_t is_csd  : CID(=0) or CSD(=1)
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_reget_reg(int32_t sd_port, uint8_t *reg, int32_t is_csd)
+{
+    st_sdhndl_t *p_hndl;
+    int32_t     i;
+    uint16_t    *p_ptr;
+    uint16_t    cmd;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    p_hndl->error = SD_OK;
+
+    /* ---- transfer stand-by state ---- */
+    if (_sd_standby(p_hndl) != SD_OK)
+    {
+        return _sd_reget_reg_error(p_hndl);
+    }
+
+    /* verify CID or CSD */
+    if (0 == is_csd)
+    {
+        p_ptr = p_hndl->cid;
+        cmd = CMD10;
+    }
+    else
+    {
+        p_ptr = p_hndl->csd;
+        cmd = CMD9;
+    }
+
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return _sd_reget_reg_error(p_hndl);
+    }
+
+    /* ---- reget CID or CSD (issue CMD10 or CMD9) ---- */
+    if (_sd_card_send_cmd_arg(p_hndl, cmd, SD_RSP_R2_CID, p_hndl->rca[0], 0x0000) != SD_OK)
+    {
+        return _sd_reget_reg_error(p_hndl);
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    if (_sd_active(p_hndl) != SD_OK)
+    {
+        return _sd_reget_reg_error(p_hndl);
+    }
+
+    for (i = 0; i < 8; ++i)
+    {
+        /* Cast to an appropriate type */
+        *reg++ = (uint8_t)((*p_ptr) >> 8);
+
+        /* Cast to an appropriate type */
+        *reg++ = (uint8_t)(*p_ptr++);
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_reget_reg
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_reget_reg_error
+ * Description  : reget register error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_reget_reg_error(st_sdhndl_t *p_hndl)
+{
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_reget_reg_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_lock_unlock
+ * Description  : lock/unlock.
+ *              : lock/unlock operation
+ *              : passward length is up to 16 bytes
+ *              : case of cahnge passward, total length is 32 bytes,that is
+ *              : old and new passward maximum length
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : uint8_t code    : operation code
+ *              : uint8_t *pwd    : passward
+ *              : uint8_t len     : passward length
+ * Return Value : SD_OK : end of succeed.
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_lock_unlock(int32_t sd_port, uint8_t code, uint8_t *pwd, uint8_t len)
+{
+    st_sdhndl_t *p_hndl;
+    uint16_t    cmd_len;   /* lock/unlock data length */
+    char_t      data[32];
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    p_hndl->error = SD_OK;
+
+    /* ---- check mount ---- */
+    if ( (p_hndl->mount && (SD_MOUNT_LOCKED_CARD | SD_MOUNT_UNLOCKED_CARD)) == 0 )
+    {
+        _sd_set_err(p_hndl, SD_ERR);
+        return p_hndl->error; /* not mounted yet */
+    }
+
+    /* check suppoted command class */
+    if (!(p_hndl->csd_ccc & 0x0080))  /* don't support lock/unlock */
+    {
+        _sd_set_err(p_hndl, SD_ERR_NOTSUP_CMD);
+        return SD_ERR_NOTSUP_CMD;
+    }
+
+    /* Cast to an appropriate type */
+    data[0] = (char_t)code;
+
+    if (code & 0x08)    /* forcing erase */
+    {
+        cmd_len = 1;
+    }
+    else
+    {
+        if (code & 0x01)    /* set passward */
+        {
+            if (len > 16)
+            {
+                /* total passward length is not more than 32 bytes      */
+                /* but the library prohibit change password operation   */
+                return SD_ERR;
+            }
+            if (p_hndl->resp_status & 0x02000000)
+            {
+                /* prohibit set passward to lock card */
+                _sd_set_err(p_hndl, SD_ERR_CARD_LOCK);
+                return SD_ERR;
+            }
+        }
+        else if (len > 16)  /* only lock or unlock */
+        {
+            /* one passward length is not more than 16 bytes */
+            return SD_ERR;
+        }
+        else
+        {
+            /* DO NOTHING */
+            ;
+        }
+
+        /* include code and total data length */
+        cmd_len = (uint16_t)(len + 2);
+
+        /* set lock/unlock command data */
+        data[1] = (char_t)len;
+        while (len)
+        {
+            data[cmd_len - len] = *pwd++;
+            len--;
+        }
+    }
+
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return _sd_lock_unlock_error(p_hndl);
+    }
+
+    /* ---- set block length (issue CMD16) ---- */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD16, SD_RSP_R1, 0x0000, cmd_len) != SD_OK)
+    {
+        if (SD_ERR_CARD_LOCK == p_hndl->error)
+        {
+            p_hndl->error = SD_OK;
+        }
+        else
+        {
+            return _sd_lock_unlock_error(p_hndl);
+        }
+    }
+
+    /* Cast to an appropriate type */
+    if (_sd_write_byte(p_hndl, CMD42, 0x0000, 0x0000, (uint8_t*)data, cmd_len)
+            != SD_OK)
+    {
+        return _sd_lock_unlock_error(p_hndl);
+    }
+
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+            == SD_OK)
+    {
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)  /* not transfer state */
+        {
+            p_hndl->error = SD_ERR;
+            return _sd_lock_unlock_error(p_hndl);
+        }
+    }
+    else    /* SDHI error */
+    {
+        return _sd_lock_unlock_error(p_hndl);
+    }
+
+    if ( (code & SD_LOCK_CARD) == SD_UNLOCK_CARD )
+    {
+        /* ---- clear locked status ---- */
+        p_hndl->mount &= (~SD_CARD_LOCKED);
+
+        if ( SD_MOUNT_UNLOCKED_CARD == p_hndl->mount )
+        {
+            /* the card is already mounted as unlock card   */
+
+            /* ---- set block length (issue CMD16) ---- */
+            if (_sd_card_send_cmd_arg(p_hndl, CMD16, SD_RSP_R1, 0x0000, 0x0200) != SD_OK)
+            {
+                /* ---- set locked status ---- */
+                p_hndl->mount |=  SD_CARD_LOCKED;
+                return _sd_lock_unlock_error(p_hndl);
+            }
+        }
+    }
+    else
+    {
+        /* ---- set locked status ---- */
+        p_hndl->mount |=  SD_CARD_LOCKED;
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_lock_unlock
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_lock_unlock_error
+ * Description  : lock/unlock error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_lock_unlock_error(st_sdhndl_t *p_hndl)
+{
+    int32_t  temp_error;
+    int32_t  loop;
+
+    /* keep error   */
+    temp_error = p_hndl->error;
+
+    for ( loop = 0; loop < 3; loop++ )
+    {
+        /* ---- retrive block length ---- */
+        if (_sd_card_send_cmd_arg(p_hndl, CMD16, SD_RSP_R1, 0x0000, 0x0200) == SD_OK)
+        {
+            break;
+        }
+    }
+
+    _sd_set_err(p_hndl, temp_error);
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_lock_unlock_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: sd_set_tmpwp
+ * Description  : set tempolary write protect.
+ *              : set temporary write protect programing csd
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ *              : int32_t is_set  : set or clear
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_set_tmpwp(int32_t sd_port, int32_t is_set)
+{
+    st_sdhndl_t *p_hndl;
+    int32_t     i;
+    uint16_t    *p_ptr;     /* got csd */
+    uint8_t     w_csd[16];  /* work csd */
+    uint8_t     crc7;       /* calculated crc7 value */
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    p_hndl->error = SD_OK;
+
+    /* check suppoted command class */
+    if (!(p_hndl->csd_ccc & 0x0010))  /* don't support block write */
+    {
+        _sd_set_err(p_hndl, SD_ERR_NOTSUP_CMD);
+        return SD_ERR;
+    }
+
+    /* ---- make programing csd value ---- */
+    /* set unprogramable fields */
+    p_ptr = p_hndl->csd;
+    for (i = 0; i < 14; i += 2)
+    {
+        /* Cast to an appropriate type */
+        w_csd[i] = (uint8_t)(*p_ptr++);
+
+        /* Cast to an appropriate type */
+        w_csd[i + 1] = (uint8_t)(((*p_ptr) >> 8u));
+    }
+
+    /* set programing fields */
+    w_csd[14] = (uint8_t)(*p_ptr);
+    if (1 == is_set)    /* set write protect */
+    {
+        w_csd[14] |= 0x10;
+    }
+    else    /* clear write protect */
+    {
+        w_csd[14] &= (~0x10);
+    }
+
+    /* calculate crc7 for CSD */
+    crc7 = _sd_calc_crc(w_csd, 15);
+
+    /* set crc7 filelds */
+    w_csd[15] = (uint8_t)((crc7 << 1u) | 0x01);
+
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return _sd_set_tmpwp_error(p_hndl);
+    }
+
+    if (_sd_write_byte(p_hndl, CMD27, 0x0000, 0x0000, w_csd, sizeof(w_csd)) != SD_OK)
+    {
+        return _sd_set_tmpwp_error(p_hndl);
+    }
+
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+            == SD_OK)
+    {
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)  /* not transfer state */
+        {
+            p_hndl->error = SD_ERR;
+            return _sd_set_tmpwp_error(p_hndl);
+        }
+    }
+    else    /* SDHI error */
+    {
+        return _sd_set_tmpwp_error(p_hndl);
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    if (1 == is_set)    /* set write protect */
+    {
+        /* Cast to an appropriate type */
+        p_hndl->write_protect |= (uint8_t)SD_WP_TEMP;
+    }
+    else    /* clear write protect */
+    {
+        /* Cast to an appropriate type */
+        p_hndl->write_protect &= (uint8_t)~SD_WP_TEMP;
+    }
+
+    return SD_OK;
+}
+/******************************************************************************
+ End of function sd_set_tmpwp
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_set_tmpwp_error
+ * Description  : set tempolary write protect error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_set_tmpwp_error(st_sdhndl_t *p_hndl)
+{
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_set_tmpwp_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_calc_crc
+ * Description  : calculate crc7.
+ *              : calculate crc7 value
+ * Arguments    : uint8_t *data : input data
+ *              : int32_t len   : input data length (byte unit)
+ * Return Value : calculated crc7 value
+ *****************************************************************************/
+static uint8_t _sd_calc_crc(uint8_t *data, int32_t len)
+{
+    int32_t i;
+    int32_t j;
+    int32_t k;
+    uint8_t p_crc[7];   /* previous crc value */
+    uint8_t t_crc[7];   /* tentative crc value */
+    uint8_t m_data;     /* input bit mask data */
+    uint8_t crc7 = 0;   /* calculated crc7 */
+
+    for (i = 0; i < (sizeof(p_crc)); i++)
+    {
+        p_crc[i] = 0;
+        t_crc[i] = 0;
+    }
+
+    for (i = len; i > 0; i--, data++) /* byte loop */
+    {
+        for (j = 8; j > 0; j--) /* bit loop */
+        {
+            /* Cast to an appropriate type */
+            m_data = (uint8_t)((((*data) >> (j - 1)) & 0x01));
+            t_crc[6] = (p_crc[0] != m_data);
+            t_crc[5] = p_crc[6];
+            t_crc[4] = p_crc[5];
+            t_crc[3] = (p_crc[4] != (p_crc[0] != m_data));
+            t_crc[2] = p_crc[3];
+            t_crc[1] = p_crc[2];
+            t_crc[0] = p_crc[1];
+
+            /* save tentative crc value */
+            for (k = 0; k < (sizeof(p_crc)); k++)
+            {
+                p_crc[k] = t_crc[k];
+            }
+        }
+    }
+
+    /* convert bit to byte form */
+    for (i = 0; i < (sizeof(p_crc)); i++)
+    {
+        /* Cast to an appropriate type */
+        crc7 |= (uint8_t)((p_crc[i] << (6 - i)));
+    }
+
+    return crc7;
+}
+/******************************************************************************
+ End of function _sd_calc_crc
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_memset
+ * Description  : set memory.
+ *              : fill memory filling data(=data) from start address(=p)
+ *              : by filling size(=cnt)
+ * Arguments    : uint8_t *p   : start address of memory
+ *              : uint8_t data : filling data
+ *              : uint32_t cnt : filling size
+ * Return Value : 0 : end of succeed
+ *****************************************************************************/
+int32_t _sd_memset(uint8_t *p, uint8_t data, uint32_t cnt)
+{
+    while (cnt--)
+    {
+        *p++ = data;
+    }
+
+    return 0;
+}
+/******************************************************************************
+ End of function _sd_memset
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_memcpy
+ * Description  : copy memory.
+ *              : copy data from source address(=src) to destination address
+ *              : (=dst) by copy size(=cnt)
+ * Arguments    : uint8_t *dst : destination address
+ *              : uint8_t *src : source address
+ *              : uint32_t cnt : copy size
+ * Return Value : 0 : end of succeed
+ *****************************************************************************/
+int32_t _sd_memcpy(uint8_t *dst, uint8_t *src, uint32_t cnt)
+{
+    while (cnt--)
+    {
+        *dst++ = *src++;
+    }
+
+    return 0;
+}
+/******************************************************************************
+ End of function _sd_memcpy
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_rand
+ * Description  : create Volume ID Number.
+ *              : get Volume ID Number
+ *              : Volume ID Number is created by pseudo random number
+ * Arguments    : none
+ * Return Value : created Volume ID Number
+ *****************************************************************************/
+uint16_t _sd_rand(void)
+{
+
+    s_next = (s_next * 1103515245L) + 12345;
+
+    /* Cast to an appropriate type */
+    return (uint16_t)s_next;
+
+}
+/******************************************************************************
+ End of function _sd_rand
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_srand
+ * Description  : set initial value of Volume ID Number.
+ * Arguments    : uint32_t seed : initial seting value
+ * Return Value : none
+ *****************************************************************************/
+void _sd_srand(uint32_t seed)
+{
+    if (0 == s_next)
+    {
+        s_next = seed;
+    }
+}
+/******************************************************************************
+ End of function _sd_srand
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_wait_rbusy
+ * Description  : wait response busy.
+ *              : wait response busy finished
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t time        : response busy wait interval
+ * Return Value : SD_OK : response busy finished
+ *              : SD_ERR: response busy not finished
+ *****************************************************************************/
+int32_t _sd_wait_rbusy(st_sdhndl_t *p_hndl, int32_t time)
+{
+    int32_t i;
+
+
+    for (i = 0; i < time; ++i)
+    {
+        if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000) == SD_OK)
+        {
+            if ((p_hndl->resp_status & RES_STATE) == STATE_TRAN)  /* transfer state */
+            {
+                return SD_OK;
+            }
+        }
+        else    /* SDHI error */
+        {
+            break;
+        }
+
+        if (_sd_check_media(p_hndl) != SD_OK)
+        {
+            break;
+        }
+
+        sddev_int_wait(p_hndl->sd_port, 1);
+    }
+
+    _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+
+    return SD_ERR;
+
+}
+/******************************************************************************
+ End of function _sd_wait_rbusy
+ *****************************************************************************/
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/access/sd_write.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,778 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_write.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : Card write
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02     Support for OS
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "r_sdif.h"
+#include "sd.h"
+
+#ifdef __CC_ARM
+#pragma arm section code = "CODE_SDHI"
+#pragma arm section rodata = "CONST_SDHI"
+#pragma arm section rwdata = "DATA_SDHI"
+#pragma arm section zidata = "BSS_SDHI"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static int32_t _sd_write_sect_error(st_sdhndl_t *p_hndl, int32_t mode);
+static int32_t _sd_single_write(st_sdhndl_t *p_hndl, uint8_t *buff, uint32_t psn, int32_t mode);
+static int32_t _sd_single_write_error(st_sdhndl_t *p_hndl, int32_t mode);
+
+/******************************************************************************
+ * Function Name: sd_write_sect
+ * Description  : write sector data to card.
+ *              : write sector data from physical sector number (=psn) by the
+ *              : number of sectors (=cnt)
+ *              : if SD Driver mode is SD_MODE_SW, data transfer by
+ *              : sddev_read_data function
+ *              : if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * Arguments    : int32_t sd_port   : channel no (0 or 1).
+ *              : uint8_t *buff     : write data buffer
+ *              : uint32_t psn      : write physical sector number
+ *              : int32_t cnt       : number of write sectors
+ *              : int32_t writemode : memory card write mode
+ *              :   SD_WRITE_WITH_PREERASE : pre-erease write
+ *              :   SD_WRITE_OVERWRITE     : overwrite
+ * Return Value : SD_OK : end of succeed.
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t sd_write_sect(int32_t sd_port, uint8_t *buff, uint32_t psn, int32_t cnt, int32_t writemode)
+{
+    st_sdhndl_t *p_hndl;
+
+    if ( (0 != sd_port) && (1 != sd_port) )
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    if (0 == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* Cast to an appropriate type */
+    if (NULL == buff)
+    {
+        return SD_ERR;
+    }
+
+    p_hndl->error = SD_OK;
+
+    /* ---- check card is mounted ---- */
+    if (SD_MOUNT_UNLOCKED_CARD != p_hndl->mount)
+    {
+        _sd_set_err(p_hndl, SD_ERR);
+        return p_hndl->error; /* not mounted yet */
+    }
+
+    /* ---- check write protect ---- */
+    if (p_hndl->write_protect)
+    {
+        _sd_set_err(p_hndl, SD_ERR_WP);
+        return p_hndl->error; /* write protect error */
+    }
+
+    /* ---- is stop compulsory? ---- */
+    if (p_hndl->stop)
+    {
+        p_hndl->stop = 0;
+        _sd_set_err(p_hndl, SD_ERR_STOP);
+        return p_hndl->error;
+    }
+
+    /* ---- is card existed? ---- */
+    if (_sd_check_media(p_hndl) != SD_OK)
+    {
+        _sd_set_err(p_hndl, SD_ERR_NO_CARD);
+        return p_hndl->error;
+    }
+
+    /* ==== write sector data to card ==== */
+    _sd_write_sect(p_hndl, buff, psn, cnt, writemode);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function sd_write_sect
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_write_sect
+ * Description  : write sector data to card.
+ *              : write sector data from physical sector number (=psn) by the
+ *              : number of sectors (=cnt)
+ *              : if SD Driver mode is SD_MODE_SW, data transfer by
+ *              : sddev_read_data function
+ *              : if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint8_t *buff       : write data buffer
+ *              : uint32_t psn        : write physical sector number
+ *              : int32_t cnt         : number of write sectors
+ *              : int32_t writemode   : memory card write mode
+ *              :   SD_WRITE_WITH_PREERASE : pre-erease write
+ *              :   SD_WRITE_OVERWRITE     : overwrite
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+int32_t _sd_write_sect(st_sdhndl_t *p_hndl, uint8_t *buff, uint32_t psn, int32_t cnt, int32_t writemode)
+{
+    int32_t  i;
+    int32_t  j;
+    int32_t  ret;
+    int32_t  trans_ret;
+    int32_t  mode = SD_MODE_SW;
+    uint8_t  wb[4];
+    uint32_t writeblock;
+    uint64_t info1_back;
+    uint64_t opt_back;
+
+    /* access area check */
+    if ((psn >= p_hndl->card_sector_size) || ((psn + cnt) > p_hndl->card_sector_size))
+    {
+        _sd_set_err(p_hndl, SD_ERR);
+        return p_hndl->error; /* out of area */
+    }
+
+    /* if DMA transfer, buffer boundary is octlet unit */
+    if ((p_hndl->trans_mode & SD_MODE_DMA) && (((uint32_t)buff & 0x07u) == 0))
+    {
+        mode = SD_MODE_DMA; /* set DMA mode */
+    }
+
+    /* ---- supply clock (data-transfer ratio) ---- */
+    if (_sd_set_clock(p_hndl, (int32_t)p_hndl->csd_tran_speed, SD_CLOCK_ENABLE) != SD_OK)
+    {
+        return p_hndl->error;
+    }
+
+    /* ==== check status precede write operation ==== */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+            == SD_OK)
+    {
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)  /* not transfer state */
+        {
+            p_hndl->error = SD_ERR;
+            return _sd_write_sect_error(p_hndl, mode);
+        }
+    }
+    else    /* SDHI error */
+    {
+        return _sd_write_sect_error(p_hndl, mode);
+    }
+
+    /* ==== execute multiple transfer by 256 sectors ==== */
+    for (i = cnt; i > 0 ;
+            i -= TRANS_SECTORS, psn += TRANS_SECTORS, buff += (TRANS_SECTORS * 512))
+    {
+
+        /* ---- is card existed? ---- */
+        if (_sd_check_media(p_hndl) != SD_OK)
+        {
+            _sd_set_err(p_hndl, SD_ERR_NO_CARD);
+            return _sd_write_sect_error(p_hndl, mode);
+        }
+
+        cnt = i - TRANS_SECTORS;
+        if (cnt < 0)    /* remaining sectors is less than TRANS_SECTORS */
+        {
+            cnt = i;
+        }
+        else
+        {
+            cnt = TRANS_SECTORS;
+        }
+
+        /* if card is SD Memory card and pre-erease write, issue ACMD23 */
+        if ((p_hndl->media_type & SD_MEDIA_SD) &&
+                (SD_WRITE_WITH_PREERASE == writemode))
+        {
+            /* Cast to an appropriate type */
+            if (_sd_send_acmd(p_hndl, ACMD23, 0, (uint16_t)cnt) != SD_OK)
+            {
+                return _sd_write_sect_error(p_hndl, mode);
+            }
+            if (_sd_get_resp(p_hndl, SD_RSP_R1) != SD_OK)
+            {
+                return _sd_write_sect_error(p_hndl, mode);
+            }
+        }
+
+        /* transfer size is fixed (512 bytes) */
+        SD_OUTP(p_hndl, SD_SIZE, (uint64_t)512);
+
+        /* 1 or 2 blocks, apply single read */
+        if (cnt <= 2)
+        {
+            /* disable SD_SECCNT */
+            SD_OUTP(p_hndl, SD_STOP, 0x0000);
+            for (j = cnt; j > 0; j--, psn++, buff += 512)
+            {
+                trans_ret = _sd_single_write(p_hndl, buff, psn, mode);
+                if (SD_OK != trans_ret)
+                {
+                    /* Cast to an appropriate type */
+                    opt_back = SD_INP(p_hndl, SD_OPTION);
+
+                    /* Cast to an appropriate type */
+                    SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RESET);
+
+                    /* Cast to an appropriate type */
+                    SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RELEASED);
+
+                    /* Cast to an appropriate type */
+                    SD_OUTP(p_hndl, SD_OPTION, opt_back);
+                    break;
+                }
+            }
+
+            /* ---- halt clock ---- */
+            _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+            return p_hndl->error;
+        }
+
+        /* enable SD_SECCNT */
+        SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0100);
+
+        /* set number of transfer sectors */
+        SD_OUTP(p_hndl, SD_SECCNT, (uint64_t)cnt);
+
+        /* ---- enable RespEnd and ILA ---- */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_RESP, 0);
+
+        /* issue CMD25 (WRITE_MULTIPLE_BLOCK) */
+        ret = _sd_send_mcmd(p_hndl, CMD25, SET_ACC_ADDR);
+        if (SD_OK != ret)
+        {
+            return _sd_write_sect_error(p_hndl, mode);
+        }
+
+        /* ---- disable RespEnd and ILA ---- */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+
+        if (SD_MODE_SW == mode) /* ==== PIO ==== */
+        {
+            /* enable All end, BWE and errors */
+            _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BWE);
+
+            /* software data transfer */
+            trans_ret = _sd_software_trans(p_hndl, buff, cnt, SD_TRANS_WRITE);
+        }
+        else    /* ==== DMA ==== */
+        {
+            /* disable card ins&rem interrupt for FIFO */
+            info1_back = (uint64_t)(p_hndl->int_info1_mask & SD_INFO1_MASK_DET_CD);
+
+            /* Cast to an appropriate type */
+            _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DET_CD, 0);
+
+            /* enable All end and errors */
+            _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_ERR);
+
+            /* ---- initialize DMAC ---- */
+            if (sddev_init_dma(p_hndl->sd_port, (uint32_t)buff, SD_TRANS_WRITE) != SD_OK)
+            {
+                _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+                return _sd_write_sect_error(p_hndl, mode);
+            }
+
+            /* DMA data transfer */
+            trans_ret = _sd_dma_trans(p_hndl, cnt);
+        }
+
+        /* ---- wait All end interrupt ---- */
+        ret = sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_RESP);
+
+        if (SD_MODE_DMA == mode)
+        {
+            _sd_set_int_mask(p_hndl, info1_back, 0);
+        }
+
+        /* ---- check result of transfer ---- */
+        if (SD_OK != trans_ret)
+        {
+            return _sd_write_sect_error(p_hndl, mode);
+        }
+
+        /* ---- check result of wait All end interrupt ---- */
+        if (SD_OK != ret)
+        {
+            _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+            return _sd_write_sect_error(p_hndl, mode);
+        }
+
+        /* ---- check errors ---- */
+        if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+        {
+            _sd_check_info2_err(p_hndl);
+            return _sd_write_sect_error(p_hndl, mode);
+        }
+
+        /* clear All end bit */
+        _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0x0000);
+
+        /* disable All end, BWE and errors */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BWE);
+
+        if (p_hndl->media_type & SD_MEDIA_SD)
+        {
+            if (_sd_get_resp(p_hndl, SD_RSP_R1) != SD_OK)
+            {
+                /* check number of write complete block */
+                if (_sd_read_byte(p_hndl, ACMD22, 0, 0, wb, 4) != SD_OK)
+                {
+                    return _sd_write_sect_error(p_hndl, mode);
+                }
+
+                /* type cast (uint32_t) remove compiler dependence */
+                writeblock = ((uint32_t)wb[0] << 24) | ((uint32_t)wb[1] << 16) |
+
+                            /* Cast to an appropriate type */
+                            ((uint32_t)wb[2] << 8)  | (uint32_t)wb[3];
+
+                if (cnt != writeblock)  /* no write complete block */
+                {
+                    _sd_set_err(p_hndl, SD_ERR);
+                    return _sd_write_sect_error(p_hndl, mode);
+                }
+            }
+        }
+
+        /* ==== check status after write operation ==== */
+        if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+                != SD_OK)
+        {
+            /* check OUT_OF_RANGE error */
+            /* ignore errors during last block access */
+            if (p_hndl->resp_status & 0xffffe008ul)
+            {
+                if ((psn + cnt) != p_hndl->card_sector_size)
+                {
+                    return _sd_write_sect_error(p_hndl, mode);   /* but for last block */
+                }
+                if (p_hndl->resp_status & 0x7fffe008ul)
+                {
+                    return _sd_write_sect_error(p_hndl, mode);   /* not OUT_OF_RANGE error */
+                }
+
+                /* clear OUT_OF_RANGE error */
+                p_hndl->resp_status &= 0x1f00u;
+                p_hndl->error = SD_OK;
+            }
+            else    /* SDHI error, ex)timeout error so on */
+            {
+                return _sd_write_sect_error(p_hndl, mode);
+            }
+        }
+
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)
+        {
+            p_hndl->error = SD_ERR;
+            return _sd_write_sect_error(p_hndl, mode);
+        }
+
+        /* ---- is stop compulsory? ---- */
+        if (p_hndl->stop)
+        {
+            p_hndl->stop = 0;
+
+            /* data transfer stop (issue CMD12) */
+            SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);
+            i = 0;  /* set zero to break loop */
+            _sd_set_err(p_hndl, SD_ERR_STOP);
+        }
+    }
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+
+    /*
+        CMD12 may not be issued when an error occurs.
+        When the SDHI does not execute the command sequence and the SD card is not in the transfer state,
+        CMD12 must be issued.
+
+        Conditions for error processing
+        1.The SD card is not in the transfer state when CMD13 is issued.
+        2.CMD13 issuing process is failed.
+
+        3.DMA transfer processing is failed.
+          The sequence is suspended by the implementation failure of the user-defined function or INFO2 error.
+        4.Interrupt for access end or response end is not generated.
+          Implementation failure of the user-defined function caused timeout during the command sequence execution.
+        5.Error bit of INFO2 is set.
+        6.ACMD22 is in error.
+        7.The sector count for writing obtained by ACMD22 and the transmitted sector count are different.
+        8.Error bit of CMD13 response is set.
+        9.CMD13 issuing process is failed.
+        10.The SD card is not in the transfer state when CMD13 is issued.
+    */
+}
+/******************************************************************************
+ End of function _sd_write_sect
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_write_sect_error
+ * Description  : write sector data error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : int32_t mode        : data transfer mode
+ *              :   SD_MODE_SW  : software
+ *              :   SD_MODE_DMA : DMA
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_write_sect_error(st_sdhndl_t *p_hndl, int32_t mode)
+{
+    volatile int32_t error;
+    uint64_t sd_option;
+    uint64_t sd_clk_ctrl;
+
+    if (SD_MODE_DMA == mode)
+    {
+        /* Cast to an appropriate type */
+        (void)sddev_disable_dma((int32_t)(p_hndl->sd_port));   /* disable DMA */
+
+        /* reset DMAC */
+        error = sddev_reset_dma((int32_t)(p_hndl->sd_port));
+        if (SD_OK != error)
+        {
+            /* DO NOTHING */
+            ;
+        }
+    }
+
+    error = p_hndl->error;
+
+    /* ---- clear error bits ---- */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* ---- disable all interrupts ---- */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* Cast to an appropriate type */
+    if ((SD_INP(p_hndl, SD_INFO2) & SD_INFO2_MASK_CBSY) == SD_INFO2_MASK_CBSY)
+    {
+        /* ---- enable All end ---- */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0);
+
+        /* ---- data transfer stop (issue CMD12) ---- */
+        SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);
+
+        /* ---- wait All end ---- */
+        sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_RESP);
+
+        /* Cast to an appropriate type */
+        _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+        /* Cast to an appropriate type */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0);
+
+        sddev_loc_cpu(p_hndl->sd_port);
+
+        /* Cast to an appropriate type */
+        sd_option   = SD_INP(p_hndl, SD_OPTION);
+
+        /* Cast to an appropriate type */
+        sd_clk_ctrl = SD_INP(p_hndl, SD_CLK_CTRL);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RESET);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SOFT_RST, SOFT_RST_SDRST_RELEASED);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_STOP, 0x0000);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_OPTION, sd_option);
+
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, SD_CLK_CTRL, sd_clk_ctrl);
+        sddev_unl_cpu(p_hndl->sd_port);
+
+    }
+
+    /* Check Current State */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000) == SD_OK)
+    {
+        /* not transfer state? */
+        if ((p_hndl->resp_status & RES_STATE) != STATE_TRAN)
+        {
+            /* if not tran state, issue CMD12 to transit the SD card to tran state */
+            _sd_card_send_cmd_arg(p_hndl, CMD12, SD_RSP_R1B, p_hndl->rca[0], 0x0000);
+
+            /* not check error because already checked */
+        }
+    }
+
+    p_hndl->error = error;
+
+    /* Cast to an appropriate type */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+
+}
+/******************************************************************************
+ End of function _sd_write_sect_error
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_single_write
+ * Description  : write sector data to card by single block transfer.
+ *              : read sector data from physical sector number (=psn) by the
+ *              : single block transfer
+ *              : if SD Driver mode is SD_MODE_SW, data transfer by
+ *              : sddev_read_data function
+ *              : if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle
+ *              : uint8_t *buff       : write data buffer
+ *              : uint32_t psn        : write physical sector number
+ *              : int32_t mode        : data transfer mode
+ *              :   SD_MODE_SW  : software
+ *              :   SD_MODE_DMA : DMA
+ * Return Value : SD_OK : end of succeed
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_single_write(st_sdhndl_t *p_hndl, uint8_t *buff, uint32_t psn,
+                                int32_t mode)
+{
+    int32_t  ret;
+    int32_t  trans_ret;
+    uint64_t info1_back;
+
+    /* ---- enable RespEnd and ILA ---- */
+    _sd_set_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+
+    /* issue CMD24 (WRITE_SIGLE_BLOCK) */
+    if (_sd_send_mcmd(p_hndl, CMD24, SET_ACC_ADDR) != SD_OK)
+    {
+        return _sd_single_write_error(p_hndl, mode);
+    }
+
+    /* ---- disable RespEnd and ILA ---- */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_RESP, SD_INFO2_MASK_ILA);
+
+    if (SD_MODE_SW == mode) /* ==== PIO ==== */
+    {
+        /* enable All end, BWE and errors */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BWE);
+
+        /* software data transfer */
+        trans_ret = _sd_software_trans(p_hndl, buff, 1, SD_TRANS_WRITE);
+    }
+    else    /* ==== DMA ==== */
+    {
+        /* disable card ins&rem interrupt for FIFO */
+        info1_back = (uint64_t)(p_hndl->int_info1_mask & SD_INFO1_MASK_DET_CD);
+
+        /* Cast to an appropriate type */
+        _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DET_CD, 0);
+
+        /* enable All end and errors */
+        _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_ERR);
+
+        /* ---- initialize DMAC ---- */
+        if (sddev_init_dma(p_hndl->sd_port, (uint32_t)buff, SD_TRANS_WRITE) != SD_OK)
+        {
+            _sd_set_err(p_hndl, SD_ERR_CPU_IF);
+            return _sd_single_write_error(p_hndl, mode);
+        }
+
+        /* DMA data transfer */
+        trans_ret = _sd_dma_trans(p_hndl, 1);
+    }
+
+    /* ---- wait All end interrupt ---- */
+    ret = sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_RESP);
+
+    if (SD_MODE_DMA == mode)
+    {
+        _sd_set_int_mask(p_hndl, info1_back, 0);
+    }
+
+    /* ---- check result of transfer ---- */
+    if (SD_OK != trans_ret)
+    {
+        return _sd_single_write_error(p_hndl, mode);
+    }
+
+    /* ---- check result of wait All end interrupt ---- */
+    if (SD_OK != ret)
+    {
+        _sd_set_err(p_hndl, SD_ERR_HOST_TOE);
+        return _sd_single_write_error(p_hndl, mode);
+    }
+
+    /* ---- check errors ---- */
+    if (p_hndl->int_info2 & SD_INFO2_MASK_ERR)
+    {
+        _sd_check_info2_err(p_hndl);
+        return _sd_single_write_error(p_hndl, mode);
+    }
+
+    /* clear All end bit */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0x0000);
+
+    /* disable All end, BWE and errors */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, SD_INFO2_MASK_BWE);
+
+    /* ==== skip write complete block number check ==== */
+
+    /* ==== check status after write operation ==== */
+    if (_sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000)
+            != SD_OK)
+    {
+        /* check OUT_OF_RANGE error */
+        /* ignore errors during last block access */
+        if (p_hndl->resp_status & 0xffffe008ul)
+        {
+            if ((psn + 1) != p_hndl->card_sector_size)
+            {
+                return _sd_single_write_error(p_hndl, mode);  /* but for last block */
+            }
+            if (p_hndl->resp_status & 0x7fffe008ul)
+            {
+                return _sd_single_write_error(p_hndl, mode);  /* not OUT_OF_RANGE error */
+            }
+
+            /* clear OUT_OF_RANGE error */
+            p_hndl->resp_status &= 0x1f00u;
+            p_hndl->error = SD_OK;
+        }
+        else    /* SDHI error, ex)timeout error so on */
+        {
+            return _sd_single_write_error(p_hndl, mode);
+        }
+    }
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_single_write
+ *****************************************************************************/
+
+/******************************************************************************
+ * Function Name: _sd_single_write_error
+ * Description  : write sector data to card error.
+ * Arguments    : st_sdhndl_t *p_hndl : SD handle.
+ *              : int32_t mode        : data transfer mode
+ *              :   SD_MODE_SW  : software
+ *              :   SD_MODE_DMA : DMA
+ * Return Value : SD_OK : end of succeed.
+ *              : SD_ERR: end of error
+ *****************************************************************************/
+static int32_t _sd_single_write_error(st_sdhndl_t *p_hndl, int32_t mode)
+{
+    int32_t temp_error;
+
+    if (SD_MODE_DMA == mode)
+    {
+        /* Cast to an appropriate type */
+        (void)sddev_disable_dma((int32_t)(p_hndl->sd_port));   /* disable DMA */
+
+        /* reset DMAC */
+        temp_error = sddev_reset_dma((int32_t)(p_hndl->sd_port));
+        if (SD_OK != temp_error)
+        {
+            /* DO NOTHING */
+            ;
+        }
+    }
+    temp_error = p_hndl->error;
+
+    /* ---- clear error bits ---- */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* ---- disable all interrupts ---- */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* ---- enable All end ---- */
+    _sd_set_int_mask(p_hndl, SD_INFO1_MASK_DATA_TRNS, 0);
+
+    /* ---- data transfer stop (issue CMD12) ---- */
+    SD_OUTP(p_hndl, SD_STOP, (uint64_t)0x0001);
+
+    /* ---- wait All end ---- */
+    sddev_int_wait(p_hndl->sd_port, SD_TIMEOUT_RESP);
+
+    /* Cast to an appropriate type */
+    _sd_clear_info(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+    _sd_card_send_cmd_arg(p_hndl, CMD13, SD_RSP_R1, p_hndl->rca[0], 0x0000);
+    p_hndl->error = temp_error;
+
+    /* Cast to an appropriate type */
+    _sd_clear_int_mask(p_hndl, SD_INFO1_MASK_TRNS_RESP, SD_INFO2_MASK_ALL);
+
+    /* ---- halt clock ---- */
+    _sd_set_clock(p_hndl, 0, SD_CLOCK_DISABLE);
+
+    return p_hndl->error;
+}
+/******************************************************************************
+ End of function _sd_single_write_error
+ *****************************************************************************/
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/inc/access/sd.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1209 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd.h
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : SD Driver header file
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02     Support for OS
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "sys_sel.h"
+
+#ifndef SD_H
+#define SD_H
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef union
+{
+    uint64_t        longlong;
+    struct
+    {
+        uint32_t    l_;
+        uint32_t    h_;
+    } st_long_t;
+    struct
+    {
+        uint16_t    ll_;
+        uint16_t    lh_;
+        uint16_t    hl_;
+        uint16_t    hh_;
+    } st_word_t;
+} u_sd_reg_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ==== option ==== */
+#define SD_UNMOUNT_CARD             (0x00u)
+#define SD_MOUNT_UNLOCKED_CARD      (0x01u)
+#define SD_MOUNT_LOCKED_CARD        (0x02u)
+#define SD_CARD_LOCKED              (0x04u)
+
+/* ==== SDHI register address ==== */
+#define SD_CMD          ((0x0000u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* Command Type                                 */
+#define SD_ARG          ((0x0010u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Command Argument CF39-CF8(32bit)          */
+#define SD_ARG1         ((0x0018u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Command Argument CF39-CF24(high 16bits)   */
+#define SD_STOP         ((0x0020u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* Data Stop                                    */
+#define SD_SECCNT       ((0x0028u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* Block Count                                  */
+#define SD_RSP10        ((0x0030u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R71-8(64bit)                */
+#define SD_RSP1         ((0x0038u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R39-24                      */
+#define SD_RSP32        ((0x0040u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R71-40(32bit)               */
+#define SD_RSP3         ((0x0048u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R71-56                      */
+#define SD_RSP54        ((0x0050u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R127-72(56bit)              */
+#define SD_RSP5         ((0x0058u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R103-88                     */
+#define SD_RSP76        ((0x0060u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R127-104(24bit)             */
+#define SD_RSP7         ((0x0068u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Response R127-120                    */
+#define SD_INFO1        ((0x0070u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Interrupt Flag(1)                    */
+#define SD_INFO2        ((0x0078u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Interrupt Flag(2)                    */
+#define SD_INFO1_MASK   ((0x0080u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD_INFO1 Interrupt Mask                      */
+#define SD_INFO2_MASK   ((0x0088u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD_INFO2 Interrupt Mask                      */
+#define SD_CLK_CTRL     ((0x0090u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Clock Control                             */
+#define SD_SIZE         ((0x0098u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* Transfer Data Length                         */
+#define SD_OPTION       ((0x00A0u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Card Access Control Option                */
+#define SD_ERR_STS1     ((0x00B0u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Error Status 1                            */
+#define SD_ERR_STS2     ((0x00B8u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Error Status 2                            */
+#define SD_BUF0         ((0x00C0u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* SD Buffer Read/Write                         */
+#define CC_EXT_MODE     ((0x0360u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* DMA Mode Enable                              */
+#define SOFT_RST        ((0x0380u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* Soft Reset                                   */
+#define VERSION         ((0x0388u<<SD_REG_SHIFT)+SD_BYTE_OFFSET) /* Version                                      */
+
+#define HOST_MODE                   ((0x0390u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define SDIF_MODE                   ((0x0398u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define SD_STATUS                   ((0x03C8u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_CM_DTRAN_MODE            ((0x0820u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_CM_DTRAN_CTRL            ((0x0828u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_CM_RST                   ((0x0830u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_CM_INFO1                 ((0x0840u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_CM_INFO1_MASK            ((0x0848u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_CM_INFO2                 ((0x0850u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_CM_INFO2_MASK            ((0x0858u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+#define DM_DTRAN_ADDR               ((0x0880u<<SD_REG_SHIFT)+SD_BYTE_OFFSET)
+
+/* ==== SCC register address ==== */
+#define SCC_DTCNTL                  (0x0000u<<SD_REG_SHIFT)
+#define SCC_TAPSET                  (0x0008u<<SD_REG_SHIFT)
+#define SCC_DT2FF                   (0x0010u<<SD_REG_SHIFT)
+#define SCC_CKSEL                   (0x0018u<<SD_REG_SHIFT)
+#define SCC_RVSCNTL                 (0x0020u<<SD_REG_SHIFT)
+#define SCC_RVSREQ                  (0x0028u<<SD_REG_SHIFT)
+#define SCC_SMPCMP                  (0x0030u<<SD_REG_SHIFT)
+
+/* ==== command type ==== */
+/* ---- SD commands ---- */
+#define CMD0                        (0u)                        /* GO_IDLE_STATE */
+#define CMD1                        (1u)                        /* SD_SEND_OP_COND for MMC */
+#define CMD2                        (2u)                        /* ALL_SEND_CID */
+#define CMD3                        (3u)                        /* SEND_RELATIVE_ADDR */
+#define CMD4                        (4u)                        /* SET_DSR */
+#define CMD7                        (7u)                        /* SELECT/DESELECT_CARD */
+#define CMD9                        (9u)                        /* SEND_CSD */
+#define CMD10                       (10u)                       /* SEND_CID */
+#define CMD12                       (12u)                       /* STOP_TRANSMISSION */
+#define CMD13                       (13u)                       /* SEND_STATUS */
+#define CMD15                       (15u)                       /* GO_INACTIVE_STATE */
+#define CMD16                       (16u)                       /* SET_BLOCK_LEN */
+#define CMD17                       (17u)                       /* READ_SINGLE_BLOCK */
+#define CMD18                       (18u)                       /* READ_MULTIPLE_BLOCK */
+#define CMD24                       (24u)                       /* WRITE_SINGLE_BLOCK */
+#define CMD25                       (25u)                       /* WRITE_MULTIPLE_BLOCK */
+#define CMD27                       (27u)                       /* PROGRAM_CSD */
+#define CMD28                       (28u)                       /* SET_WRITE_PROT */
+#define CMD29                       (29u)                       /* CLR_WRITE_PROT */
+#define CMD30                       (30u)                       /* SEND_WRITE_PROT */
+#define CMD32                       (32u)                       /* ERASE_WR_BLK_START */
+#define CMD33                       (33u)                       /* ERASE_WR_BLK_END */
+#define CMD35                       (35u)                       /* ERASE_GROUP_START */
+#define CMD36                       (36u)                       /* ERASE_GROUP_END */
+#define CMD38                       (38u)                       /* ERASE */
+#define CMD42                       (42u)                       /* LOCK_UNLOCK */
+#define CMD55                       (55u)                       /* APP_CMD */
+
+/* ---- switch function command (phys spec ver1.10) ---- */
+#define CMD6                        (0x1C06u)                   /* SWITCH_FUNC */
+
+/* ---- dual voltage inquiry command (phys spec ver2.0) ---- */
+#define CMD8                        (0x0408u)                   /* SEND_IF_COND */
+
+/* ---- application specific commands ---- */
+#define ACMD6                       (0x40u|6u)                  /* SET_BUS_WIDTH */
+#define ACMD13                      (0x40u|13u)                 /* SD_STATUS */
+#define ACMD22                      (0x40u|22u)                 /* SEND_NUM_WR_BLOCKS */
+#define ACMD23                      (0x40u|23u)                 /* SET_WR_BLK_ERASE_COUNT */
+#define ACMD41                      (0x40u|41u)                 /* SD_SEND_OP_COND */
+#define ACMD42                      (0x40u|42u)                 /* SET_CLR_CARD_DETECT */
+#define ACMD51                      (0x40u|51u)                 /* SEND_SCR */
+
+/* ---- security commands (security spec ver1.01) ---- */
+#define ACMD18                      (0x40u|18u)                 /* SECURE_READ_MULTIPLE_BLOCK */
+#define ACMD25                      (0x40u|25u)                 /* SECURE_WRITE_MULTIPLE_BLOCK */
+#define ACMD26                      (0x40u|26u)                 /* SECURE_WRITE_MKB */
+#define ACMD38                      (0x40u|38u)                 /* SECURE_ERASE */
+#define ACMD43                      (0x40u|43u)                 /* GET_MKB */
+#define ACMD44                      (0x40u|44u)                 /* GET_MID */
+#define ACMD45                      (0x40u|45u)                 /* SET_CER_RN1 */
+#define ACMD46                      (0x40u|46u)                 /* GET_CER_RN2 */
+#define ACMD47                      (0x40u|47u)                 /* SET_CER_RES2 */
+#define ACMD48                      (0x40u|48u)                 /* GET_CER_RES1 */
+#define ACMD49                      (0x40u|49u)                 /* CHANGE_SECURE_AREA */
+
+/* ==== constants ==== */
+/* --- command arg --- */
+#define ARG_ACMD6_1BIT              (0)
+#define ARG_ACMD6_4BIT              (2)
+
+/* ---- response type  ---- */
+#define SD_RSP_NON                  (0)                         /* no response */
+#define SD_RSP_R1                   (1)                         /* nomal response */
+#define SD_RSP_R1B                  (2)                         /* nomal response with an optional busy signal */
+#define SD_RSP_R1_SCR               (3)                         /* nomal response with an optional busy signal */
+#define SD_RSP_R2_CID               (4)                         /* CID register */
+#define SD_RSP_R2_CSD               (5)                         /* CSD register */
+#define SD_RSP_R3                   (6)                         /* OCR register */
+#define SD_RSP_R6                   (7)                         /* Published RCA response */
+#define SD_RSP_R7                   (10)                        /* Card Interface Condition response */
+
+/* --- R1 response error bit ---- */
+#define RES_SW_INTERNAL             (0xe8400000ul)              /* Driver illegal process */
+                                                                /* OUT_OF_RANGE */
+                                                                /* ADDRESS_ERROR */
+                                                                /* BLOCK_LEN_ERROR */
+                                                                /* ERASE_PARAM */
+                                                                /* RES_ILLEGAL_COMMAND */
+#define RES_ERASE_SEQ_ERROR         (0x10008000ul)              /* ERASE_SEQ_ERROR + WP_ERASE_SKIP */
+#define RES_WP_VIOLATION            (0x04000000ul)
+#define RES_CARD_IS_LOCKED          (0x02000000ul)
+#define RES_CARD_UNLOCKED_FAILED    (0x01000000ul)
+#define RES_COM_CRC_ERROR           (0x00800000ul)
+#define RES_CARD_ECC_FAILED         (0x00200000ul)
+#define RES_CC_ERROR                (0x00100000ul)
+#define RES_ERROR                   (0x00080000ul)
+#define RES_AKE_SEQ_ERROR           (0x00000008ul)
+#define RES_STATE                   (0x00001e00ul)
+
+/* --- current_state --- */
+#define STATE_IDEL                  (0)
+#define STATE_READY                 (1u<<9u)
+#define STATE_IDENT                 (2u<<9u)
+#define STATE_STBY                  (3u<<9u)
+#define STATE_TRAN                  (4u<<9u)
+#define STATE_DATA                  (5u<<9u)
+#define STATE_RCV                   (6u<<9u)
+#define STATE_PRG                   (7u<<9u)
+#define STATE_DIS                   (8u<<9u)
+
+/* ---- maximum block count per multiple command ---- */
+#define TRANS_SECTORS               (p_hndl->trans_sectors)     /* max 65535 blocks */
+#define TRANS_BLOCKS                (p_hndl->trans_blocks)      /* max 65535 blocks */
+
+/* ---- set block address, if HC card ---- */
+#define SET_ACC_ADDR                ((p_hndl->csd_structure == 0x01) ? (psn) : (psn*512))
+
+/* ---- SD clock control ---- */
+#define SD_CLOCK_ENABLE             (1)                         /* supply clock */
+#define SD_CLOCK_DISABLE            (0)                         /* halt clock */
+
+/* ---- SD_OPTION register ---- */
+#define SD_OPTION_INIT              ((uint64_t)(0x00ee))        /* SD_OPTION initial value */
+                                                                /* b7-4 : timeout counter = SD_CLK x 2^27           */
+                                                                /* b3-0 : card detect timer counter = SD_CLK x 2^24 */
+#define SD_OPTION_TOP_MAX           ((uint64_t)(0x02e0))        /* SD_OPTION TOP value is max.                      */
+#define SD_OPTION_TOP_MASK          ((uint64_t)(0x02f0))        /* SD_OPTION TOP mask                               */
+#define SD_OPTION_WIDTH_MASK        (SD_OPTION_WIDTH|SD_OPTION_WIDTH8)
+                                                                /* SD_OPTION Bus width mask                         */
+#define SD_OPTION_WIDTH             ((uint64_t)(0x8000))        /* b15 : Bus width(WIDTH)                           */
+#define SD_OPTION_WIDTH8            ((uint64_t)(0x2000))        /* b13 : Bus width(WIDTH8)                          */
+                                                                /* WIDTH,WIDTH8                                     */
+                                                                /*     0,     1 = 8 bits bus width                  */
+                                                                /*     0,     0 = 4 bits bus width                  */
+                                                                /*     1,     0 = 1 bit  bus width                  */
+                                                                /*     1,     1 = 1 bit  bus width                  */
+
+
+/* ---- SD_INFO1 interrupt mask register ---- */
+#define SD_INFO1_MASK_ALL           ((uint64_t)(0x1031d))       /* ALL SD_INFO1 Interrupt                       */
+#define SD_INFO1_MASK_STATE_DAT3    ((uint64_t)(0x0400))        /* b10 : SD_D3 State                            */
+#define SD_INFO1_MASK_DET_DAT3      ((uint64_t)(0x0300))        /* b8,9: SD_D3 Card Insertion and Removal       */
+#define SD_INFO1_MASK_INS_DAT3      ((uint64_t)(0x0200))        /* b9  : SD_D3 Card Insertion                   */
+#define SD_INFO1_MASK_REM_DAT3      ((uint64_t)(0x0100))        /* b8  : SD_D3 Card Removal                     */
+#define SD_INFO1_MASK_WP            ((uint64_t)(0x0080))        /* b7  : Write Protect                          */
+#define SD_INFO1_MASK_STATE_CD      ((uint64_t)(0x0020))        /* b5  : SD_CD State                            */
+#define SD_INFO1_MASK_DET_CD        ((uint64_t)(0x0018))        /* b3,4: SD_CD Card Insertion and Removal       */
+#define SD_INFO1_MASK_INS_CD        ((uint64_t)(0x0010))        /* b4  : SD_CD Card Insertion                   */
+#define SD_INFO1_MASK_REM_CD        ((uint64_t)(0x0008))        /* b3  : SD_CD Card Removal                     */
+#define SD_INFO1_MASK_TRNS_RESP     ((uint64_t)(0x0005))        /* b0,2: Access End and Response End            */
+#define SD_INFO1_MASK_DATA_TRNS     ((uint64_t)(0x0004))        /* b2  : Access End                             */
+#define SD_INFO1_MASK_RESP          ((uint64_t)(0x0001))        /* b0  : Response End                           */
+#define SD_INFO1_MASK_DET_DAT3_CD   (SD_INFO1_MASK_DET_DAT3|SD_INFO1_MASK_DET_CD)
+
+/* ---- SD_INFO2 interrupt mask register ---- */
+#define SD_INFO2_MASK_ALLP          ((uint64_t)(0x8b7f))    /* All SD_INFO2 Interrupt for OUTPUT(b11 is always 1) */
+#define SD_INFO2_MASK_ALL           ((uint64_t)(0x837f))        /* All SD_INFO2 Interrupt                       */
+#define SD_INFO2_MASK_BWE           ((uint64_t)(0x827f))        /* Write enable and All errors                  */
+#define SD_INFO2_MASK_BRE           ((uint64_t)(0x817f))        /* Read enable and All errors                   */
+#define SD_INFO2_MASK_ERR           ((uint64_t)(0x807f))        /* All errors                                   */
+#define SD_INFO2_MASK_ILA           ((uint64_t)(0x8000))        /* b15 : Illegal Access Error                   */
+#define SD_INFO2_MASK_CBSY          ((uint64_t)(0x4000))        /* b14 : Command Type Register Busy             */
+#define SD_INFO2_MASK_SCLKDIVEN     ((uint64_t)(0x2000))        /* b13 : SD Bus Busy                            */
+#define SD_INFO2_MASK_WE            ((uint64_t)(0x0200))        /* b9  : SD_BUF Write Enable                    */
+#define SD_INFO2_MASK_RE            ((uint64_t)(0x0100))        /* b8  : SD_BUF Read Enable                     */
+#define SD_INFO2_MASK_ERR6          ((uint64_t)(0x0040))        /* b6  : Response Timeout                       */
+#define SD_INFO2_MASK_ERR5          ((uint64_t)(0x0020))        /* b5  : SD_BUF Illegal Read Access             */
+#define SD_INFO2_MASK_ERR4          ((uint64_t)(0x0010))        /* b4  : SD_BUF Illegal Write Access            */
+#define SD_INFO2_MASK_ERR3          ((uint64_t)(0x0008))        /* b3  : Data Timeout(except response timeout)  */
+#define SD_INFO2_MASK_ERR2          ((uint64_t)(0x0004))        /* b2  : END Error                              */
+#define SD_INFO2_MASK_ERR1          ((uint64_t)(0x0002))        /* b1  : CRC Error                              */
+#define SD_INFO2_MASK_ERR0          ((uint64_t)(0x0001))        /* b0  : CMD Error                              */
+
+/* ---- DMA mode enable register ---- */
+#define CC_EXT_MODE_DMASDRW         ((uint64_t)(0x0002))        /* SD_BUF Read/Write DMA Transfer           */
+
+/* ---- Software reset register ---- */
+#define SOFT_RST_SDRST_RESET        ((uint64_t)(0x0006))        /* Software Reset                           */
+#define SOFT_RST_SDRST_RELEASED     ((uint64_t)(0x0007))        /* Software Reset Released                  */
+
+/* ---- Host interface mode set register ---- */
+#define HOST_MODE_32BIT_ACCESS      ((uint64_t)(0x0101))        /* SD_BUF access size (32bit)               */
+#define HOST_MODE_64BIT_ACCESS      ((uint64_t)(0x0000))        /* SD_BUF access size (64bit)               */
+
+/* ---- DMAC mode regiter ---- */
+#define DM_CM_DTRAN_MODE_READ       ((uint64_t)(0x10030))       /* SD upstream                              */
+#define DM_CM_DTRAN_MODE_WRITE      ((uint64_t)(0x00030))       /* SD downstream                            */
+                                                                /* b17,b16 : CH_NUM[1:0]                    */
+                                                                /*   0,  0 : SD downstream                  */
+                                                                /*   0,  1 : SD upstream                    */
+                                                                /*  b5, b4 : BUS_WIDTH[1:0]                 */
+                                                                /*   1,  1 : 64bit(fix)                     */
+
+/* ---- DMAC control register ---- */
+#define DM_CM_DTRAN_CTRL_DM_START   ((uint64_t)(0x0001))        /* b0 : DM_START                            */
+
+/* ---- DMAC soft reset register ---- */
+#define DM_CM_RST_RESET             ((uint64_t)(0xFFFFFCFF))    /* b8,9 = 0,0 : ch0/ch1 soft reset          */
+#define DM_CM_RST_RELEASED          ((uint64_t)(0xFFFFFFFF))    /* b8,9 = 1,1 : ch0/ch1 soft reset released */
+
+/* ---- DM_CM_INFO1 interrupt mask register ---- */
+#define DM_CM_INFO1_MASK_DTRANEND1  ((uint64_t)(0x00100000))    /* b20 : DMAC ch1 trans end mask            */
+#define DM_CM_INFO1_MASK_DTRANEND0  ((uint64_t)(0x00010000))    /* b16 : DMAC ch0 trans end mask            */
+#define DM_CM_INFO1_MASK_ALLP       ((uint64_t)(0xFFFFFFFF))    /* All : b1-15, b17-19, b21-31 are always 1 */
+
+/* ---- DM_CM_INFO2 interrupt mask register ---- */
+#define DM_CM_INFO2_MASK_DTRANERR1  ((uint64_t)(0x00020000))    /* b17 : DMAC ch1 error mask                */
+#define DM_CM_INFO2_MASK_DTRANERR0  ((uint64_t)(0x00010000))    /* b16 : DMAC ch0 error mask                */
+#define DM_CM_INFO2_MASK_ALLP       ((uint64_t)(0xFFFFFFFF))    /* All : b1-15, b18-31 are always 1         */
+
+/* ---- time out count ---- */
+#define SD_TIMEOUT_CMD              (100)                       /* commnad timeout */
+#define SD_TIMEOUT_MULTIPLE         (1000)                      /* block transfer timeout */
+#define SD_TIMEOUT_RESP             (1000)                      /* command sequence timeout */
+#define SD_TIMEOUT_DMA_END          (1000)                      /* DMA transfer timeout */
+#define SD_TIMEOUT_ERASE_CMD        (10000)                     /* erase timeout */
+#define SD_TIMEOUT_PROG_CMD         (10000)                     /* programing timeout */
+
+/* ---- data transafer direction ---- */
+#define SD_TRANS_READ               (0)                         /* Host <- SD */
+#define SD_TRANS_WRITE              (1)                         /* Host -> SD */
+
+/* ---- card register size ---- */
+#define STATUS_DATA_BYTE            (64)                        /* STATUS_DATA size */
+#define SD_STATUS_BYTE              (64)                        /* SD STATUS size */
+#define SD_SCR_REGISTER_BYTE        (8)                         /* SCR register size */
+
+/* ---- area distinction ---- */
+#define SD_USER_AREA                (1u)
+#define SD_PROT_AREA                (2u)
+
+/* --- SD specification version ---- */
+#define SD_SPEC_10                  (0)                         /* SD physical spec 1.01 (phys spec ver1.01) */
+#define SD_SPEC_11                  (1)                         /* SD physical spec 1.10 (phys spec ver1.10) */
+#define SD_SPEC_20                  (2)                         /* SD physical spec 2.00 (phys spec ver2.00) */
+#define SD_SPEC_30                  (3)                         /* SD physical spec 3.00 (phys spec ver3.00) */
+
+/* --- SD specification version register mask --- */
+#define SD_SPEC_REGISTER_MASK       (0x0F00u)                   /* SD_SPEC SCR[59:56] mask */
+#define SD_SPEC_30_REGISTER         (0x8000u)                   /* SD_SPEC3 SCR[47] is 1   */
+#define SD_SPEC_20_REGISTER         (0x0200u)                   /* SD_SPEC SCR[57] is 1    */
+#define SD_SPEC_11_REGISTER         (0x0100u)                   /* SD_SPEC SCR[56] is 1    */
+/* ==== format parameter ==== */
+#define SIZE_CARD_256KB             (256*1024/512)              /*  256*1KB/(sector size) */
+#define SIZE_CARD_1MB               (1024*1024/512)             /* 1024*1KB/(sector size) */
+#define SIZE_CARD_2MB               (2*1024*1024/512)           /*    2*1MB/(sector size) */
+#define SIZE_CARD_4MB               (4*1024*1024/512)           /*    4*1MB/(sector size) */
+#define SIZE_CARD_8MB               (8*1024*1024/512)           /*    8*1MB/(sector size) */
+#define SIZE_CARD_16MB              (16*1024*1024/512)          /*   16*1MB/(sector size) */
+#define SIZE_CARD_32MB              (32*1024*1024/512)          /*   32*1MB/(sector size) */
+#define SIZE_CARD_64MB              (64*1024*1024/512)          /*   64*1MB/(sector size) */
+#define SIZE_CARD_128MB             (128*1024*1024/512)         /*  128*1MB/(sector size) */
+#define SIZE_CARD_256MB             (256*1024*1024/512)         /*  256*1MB/(sector size) */
+#define SIZE_CARD_504MB             (504*1024*1024/512)         /*  504*1MB/(sector size) */
+#define SIZE_CARD_1008MB            (1008*1024*1024/512)        /* 1008*1MB/(sector size) */
+#define SIZE_CARD_1024MB            (1024*1024*1024/512)        /* 1024*1MB/(sector size) */
+#define SIZE_CARD_2016MB            (2016*1024*1024/512)        /* 2016*1MB/(sector size) */
+#define SIZE_CARD_2048MB            (2048ul*1024ul*1024ul/512ul)/* 2048*1MB/(sector size) */
+#define SIZE_CARD_4032MB            (4032ul*1024ul*2ul)         /* 4032*(1MB/sector size) */
+#define SIZE_CARD_4096MB            (4096ul*1024ul*2ul)         /* 4096*(1MB/sector size) */
+#define SIZE_CARD_8192MB            (8192ul*1024ul*2ul)         /* 2048*(1MB/sector size) */
+#define SIZE_CARD_16384MB           (16384ul*1024ul*2ul)        /* 2048*(1MB/sector size) */
+#define SIZE_CARD_32768MB           (32768ul*1024ul*2ul)        /* 2048*(1MB/sector size) */
+#define SIZE_CARD_128GB             (128ul*1024ul*1024ul*2ul)   /*  128*(1GB/sector size) */
+#define SIZE_CARD_512GB             (512ul*1024ul*1024ul*2ul)   /*  512*(1GB/sector size) */
+#define SIZE_CARD_2TB               (0xFFFFFFFF)                /*    2*(1TB/sector size) over 32bit max value! */
+
+#define NUM_HEAD_2                  (2)
+#define NUM_HEAD_4                  (4)
+#define NUM_HEAD_8                  (8)
+#define NUM_HEAD_16                 (16)
+#define NUM_HEAD_32                 (32)
+#define NUM_HEAD_64                 (64)
+#define NUM_HEAD_128                (128)
+#define NUM_HEAD_255                (255)
+
+#define SEC_PER_TRACK_16            (16)
+#define SEC_PER_TRACK_32            (32)
+#define SEC_PER_TRACK_63            (63)
+
+#define SEC_PER_CLUSTER_1           (1)
+#define SEC_PER_CLUSTER_2           (2)
+#define SEC_PER_CLUSTER_8           (8)
+#define SEC_PER_CLUSTER_16          (16)
+#define SEC_PER_CLUSTER_32          (32)
+#define SEC_PER_CLUSTER_64          (64)
+#define SEC_PER_CLUSTER_256         (256)
+#define SEC_PER_CLUSTER_512         (512)
+#define SEC_PER_CLUSTER_1024        (1024)
+
+/* Boundary Unit Size(sectors) */
+#define SIZE_OF_BU_1                (1)
+#define SIZE_OF_BU_2                (2)
+#define SIZE_OF_BU_8                (8)
+#define SIZE_OF_BU_16               (16)
+#define SIZE_OF_BU_32               (32)
+#define SIZE_OF_BU_64               (64)
+#define SIZE_OF_BU_128              (128)
+#define SIZE_OF_BU_8192             (8192)
+#define SIZE_OF_BU_32768            (32768)
+#define SIZE_OF_BU_65536            (65536)
+#define SIZE_OF_BU_131072           (131072)
+
+#define SD_SECTOR_SIZE              (512)
+
+/* Maximum AU size */
+#define SD_ERASE_SECTOR             ((4096*1024)/512)
+
+#define SCLKDIVEN_LOOP_COUNT        (10000)                     /* check SCLKDIVEN bit loop count */
+
+/* ==== macro functions ==== */
+#define SD_GET_HNDLS(a)            (gp_sdhandle[(a)])
+
+/* 64bit access */
+#define SD_OUTP(h,offset,data)      (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->longlong = (data))
+#define SD_INP(h,offset)            (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->longlong)
+
+/* 32bit access */
+#define SD_OUTPH(h,offset,data)     (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_long_t.h_ = (data))
+#define SD_OUTPL(h,offset,data)     (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_long_t.l_ = (data))
+#define SD_INPH(h,offset)           (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_long_t.h_)
+#define SD_INPL(h,offset)           (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_long_t.l_)
+
+/* 16bit access */
+#define SD_OUTPHH(h,offset,data)    (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.hh_ = (data))
+#define SD_OUTPHL(h,offset,data)    (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.hl_ = (data))
+#define SD_OUTPLH(h,offset,data)    (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.lh_ = (data))
+#define SD_OUTPLL(h,offset,data)    (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.ll_ = (data))
+#define SD_INPHH(h,offset)          (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.hh_)
+#define SD_INPHL(h,offset)          (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.hl_)
+#define SD_INPLH(h,offset)          (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.lh_)
+#define SD_INPLL(h,offset)          (((volatile u_sd_reg_t *)((h)->reg_base+(offset)))->st_word_t.ll_)
+
+/* ==== command type ==== */
+/* ---- eSD commands ---- */
+#define CMD43                       (0x052B)                    /* SELECT_PARTITIONS */
+#define CMD44                       (0x0C2C)                    /* MANAGE_PARTITIONS */
+#define CMD45                       (0x1C2D)                    /* QUERY_PARTITIONS */
+
+/* ==== SD Card detect ==== */
+#define SD_CD_DETECT                (0x0001u)                   /* card detection */
+
+/* === SDR104 READ/WRITE CMD === */
+#define SDR104_READ_CMD             (0x7c00u)
+
+/* === SD Set Clock === */
+#define SD_CLK_CTRL_SCLKEN          (0x0100uL)
+
+/* ==== SD Driver work buffer (allocated by File system) ==== */
+typedef struct __sdhndl                 /* SD handle */
+{
+    uint32_t    reg_base;               /* SDHI base address */
+    uint32_t    card_sector_size;       /* sector size (user area) */
+    uint32_t    prot_sector_size;       /* sector size (protect area) */
+    uint32_t    erase_sect;             /* erase block size */
+    uint8_t     fat_type;               /* FAT type (FAT12:1 FAT16:2 FAT32:3 unknown:0)  */
+    uint8_t     csd_structure;          /* CSD structure (Standard capacity:0 High capacity:1) */
+    uint8_t     csd_tran_speed;         /* CSD transfer speed */
+    uint16_t    csd_ccc;                /* CSD command class */
+    uint8_t     csd_copy;               /* CSD copy flag (not used) */
+    uint8_t     csd_file_format;        /* CSD file format group */
+    uint8_t     sd_spec;                /* SCR spec version */
+    uint8_t     if_mode;                /* bus width (1bit:0 4bits:1) */
+    uint16_t    speed_mode;             /* card speed mode; */
+    uint8_t     speed_class;            /* card speed class */
+    uint8_t     perform_move;           /* card move performance */
+    uint8_t     media_type;             /* card type */
+    uint8_t     write_protect;          /* write protect:       OFF : 0     */
+
+                                        /*                   H/W WP : 1     */
+                                        /*   CSD  TMP_WRITE_PROTECT : 2     */
+                                        /*   CSD PERM_WRITE_PROTECT : 4     */
+                                        /*   SD ROM                 : 0x10  */
+    uint64_t    int_info1;              /* SD_INFO1 status */
+    uint64_t    int_info2;              /* SD_INFO2 status */
+    uint64_t    int_info1_mask;         /* SD_INFO1_MASK status */
+    uint64_t    int_info2_mask;         /* SD_INFO2_MASK status */
+    uint64_t    int_dm_info1;           /* DM_CM_INFO1 status */
+    uint64_t    int_dm_info2;           /* DM_CM_INFO2 status */
+    uint64_t    int_dm_info1_mask;      /* DM_CM_INFO1_MASK status */
+    uint64_t    int_dm_info2_mask;      /* DM_CM_INFO2_MASK status */
+    uint32_t    voltage;                /* system supplied voltage */
+    int32_t     error;                  /* error detail information */
+    uint16_t    stop;                   /* compulsory stop flag */
+    uint8_t     mount;                  /* mount flag (mount:0 unmount:1) */
+    uint8_t     int_mode;               /* interrupt flag detect method (polling:0 H/W interrupt:1) */
+    uint8_t     trans_mode;             /* data transfer method  PIO : 0    */
+
+                                        /*                SD_BUF DMA : 2    */
+    uint8_t     sup_card;               /* support card;                */
+
+                                        /*  Memory (include MMC) : 0    */
+                                        /*                    IO : 1    */
+    uint16_t    sup_speed;              /* support speed */
+    uint8_t     sup_ver;                /* support version (ver1.1:0 ver2.x:1) */
+    uint8_t     cd_port;                /* card detect method (CD pin:0 DAT3:1) */
+    uint8_t     sd_port;                /* card port number */
+    int16_t     trans_sectors;          /* maximum block counts per multiple command */
+    int16_t     trans_blocks;           /* maximum block counts per multiple command */
+    p_intCallbackFunc int_cd_callback;   /* callback function for card detection */
+    p_fmtCallbackFunc int_format_callback;  /* callback function for card format */
+    p_intCallbackFunc int_callback;         /* callback function for interrupt flags */
+    p_intCallbackFunc int_dma_callback;     /* callback function for interrupt flags */
+    uint32_t    resp_status;                            /* R1/R1b response status */
+    uint16_t    ocr[4 / sizeof(uint16_t)];              /* OCR value */
+    uint16_t    if_cond[4 / sizeof(uint16_t)];          /* IF_COND value */
+    uint16_t    cid[16 / sizeof(uint16_t)];             /* CID value */
+    uint16_t    csd[16 / sizeof(uint16_t)];             /* CSD value */
+    uint16_t    dsr[2 / sizeof(uint16_t)];              /* DSR value */
+    uint16_t    rca[4 / sizeof(uint16_t)];              /* RCA value */
+    uint16_t    scr[8 / sizeof(uint16_t)];              /* SCR value */
+    uint16_t    sdstatus[16 / sizeof(uint16_t)];        /* SD STATUS value */
+    uint16_t    status_data[18 / sizeof(uint16_t)];     /* STATUS DATA value (phys spec ver1.10) */
+    uint8_t     *p_rw_buff;                             /* work buffer pointer */
+    uint32_t    buff_size;                              /* work buffer size */
+    int32_t     sup_if_mode;                            /* supported bus width (1bit:0 4bits:1) */
+} st_sdhndl_t;
+
+extern st_sdhndl_t *gp_sdhandle[NUM_PORT];
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+/* ==== proto type ==== */
+/* ---- sd_init.c ---- */
+/* Function Name: _sd_init_hndl */
+/**************************************************************************//**
+ * @fn            int32_t _sd_init_hndl(st_sdhndl_t *p_hndl, uint32_t mode, uint32_t voltage)
+ * @brief         initialize SD handle. <br>
+ *                initialize following SD handle members <br>
+ *                media_type       : card type <br>
+ *                write_protect    : write protect <br>
+ *                resp_status      : R1/R1b response status <br>
+ *                error            : error detail information <br>
+ *                stop             : compulsory stop flag <br>
+ *                prot_sector_size : sector size (protect area) <br>
+ *                card registers   : ocr, cid, csd, dsr, rca, scr, sdstatus and
+ *                status_data
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint32_t mode       : driver mode
+ * @param [in]    uint32_t voltage    : working voltage
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_init_hndl(st_sdhndl_t *p_hndl, uint32_t mode, uint32_t voltage);
+
+/* ---- sd_mount.c ---- */
+/* Function Name: _sd_card_init */
+/**************************************************************************//**
+ * @fn            int32_t _sd_card_init(st_sdhndl_t *p_hndl)
+ * @brief         initialize card. <br>
+ *                initialize card from idle state to stand-by <br>
+ *                distinguish card type (SD, MMC, IO or COMBO) <br>
+ *                get CID, RCA, CSD from the card
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_card_init(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_mem_mount */
+/**************************************************************************//**
+ * @fn            int32_t _sd_mem_mount(st_sdhndl_t *p_hndl)
+ * @brief         mount memory card. <br>
+ *                mount memory part from stand-by to transfer state
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_mem_mount(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_card_get_status */
+/**************************************************************************//**
+ * @fn            int32_t _sd_card_get_status(st_sdhndl_t *p_hndl)
+ * @brief         get SD Status (issue ACMD13)
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_card_get_status(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_card_get_scr */
+/**************************************************************************//**
+ * @fn            int32_t _sd_card_get_scr(st_sdhndl_t *p_hndl)
+ * @brief         get SCR register (issue ACMD51).
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_card_get_scr(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_read_byte */
+/**************************************************************************//**
+ * @fn            int32_t _sd_read_byte(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg, uint16_t l_arg,
+ *                      uint8_t *readbuff, uint16_t byte)
+ * @brief         read byte data from card <br>
+ *                issue byte data read command and read data from SD_BUF
+ *                using following commands <br>
+ *                SD STATUS(ACMD13),SCR(ACMD51),NUM_WRITE_BLOCK(ACMD22),
+ * @warning       transfer type is PIO
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint16_t cmd        : command code
+ * @param [in]    uint16_t h_arg      : command argument high [31 : 16]
+ * @param [in]    uint16_t l_arg      : command argument low [15 : 0]
+ * @param [out]   uint8_t *readbuff   : read data buffer
+ * @param [in]    uint16_t byte       : the number of read bytes
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_read_byte(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg, uint16_t l_arg,
+                        uint8_t *readbuff, uint16_t byte);
+
+/* Function Name: _sd_write_byte */
+/**************************************************************************//**
+ * @fn            int32_t _sd_write_byte(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg, uint16_t l_arg,
+ *                      uint8_t *writebuff, uint16_t byte)
+ * @brief         write byte data to card <br>
+ *                issue byte data write command and write data to SD_BUF
+ *                using following commands 
+ *                (CMD27 and CMD42)
+ * @warning       transfer type is PIO
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint16_t cmd        : command code
+ * @param [in]    uint16_t h_arg      : command argument high [31 : 16]
+ * @param [in]    uint16_t l_arg      : command argument low [15 : 0]
+ * @param [out]   uint8_t *writebuff  : write data buffer
+ * @param [in]    uint16_t byte       : the number of write bytes
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_write_byte(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg, uint16_t l_arg,
+                        uint8_t *writebuff, uint16_t byte);
+
+/* Function Name: _sd_calc_erase_sector */
+/**************************************************************************//**
+ * @fn            int32_t _sd_calc_erase_sector(st_sdhndl_t *p_hndl)
+ * @brief         calculate erase sector. <br>
+ *                This function calculate erase sector for SD Phy Ver2.0.
+ * @warning       transfer type is PIO
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_calc_erase_sector(st_sdhndl_t *p_hndl);
+
+/* ---- sd_trns.c ---- */
+/* Function Name: _sd_software_trans */
+/**************************************************************************//**
+ * @fn            int32_t _sd_software_trans(st_sdhndl_t *p_hndl, uint8_t *buff, int32_t cnt, int32_t dir)
+ * @brief         transfer data by software. <br>
+ *                transfer data to/from card by software <br>
+ *                this operations are used multiple command data phase <br>
+ *                if dir is SD_TRANS_READ, data is from card to host <br>
+ *                if dir is SD_TRANS_WRITE, data is from host to card
+ * @warning       transfer finished, check CMD12 sequence refer to All end
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [out]   uint8_t *buff       : destination/source data buffer
+ * @param [in]    int32_t cnt         : number of transfer bytes
+ * @param [in]    int32_t dir         : transfer direction
+ * @retval        p_hndl->error  : SD handle error value
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_software_trans(st_sdhndl_t *p_hndl, uint8_t *buff, int32_t cnt, int32_t dir);
+
+/* Function Name: _sd_dma_trans */
+/**************************************************************************//**
+ * @fn            int32_t _sd_dma_trans(st_sdhndl_t *p_hndl, int32_t cnt)
+ * @brief         transfer data by DMA. <br>
+ *                transfer data to/from card by DMA <br>
+ *                this operations are multiple command data phase
+ * @warning       transfer finished, check CMD12 sequence refer to All end
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t cnt         : number of transfer bytes
+ * @retval        p_hndl->error  : SD handle error value
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_dma_trans(st_sdhndl_t *p_hndl, int32_t cnt);
+
+/* ---- sd_read.c ---- */
+    /* no function */
+
+/* ---- sd_write.c ---- */
+/* Function Name: _sd_write_sect */
+/**************************************************************************//**
+ * @fn            int32_t _sd_write_sect(st_sdhndl_t *p_hndl, uint8_t *buff, uint32_t psn,
+ *                      int32_t cnt, int32_t writemode);
+ * @brief         write sector data to card. <br>
+ *                write sector data from physical sector number (=psn) by the
+ *                number of sectors (=cnt) <br>
+ *                if SD Driver mode is SD_MODE_SW, data transfer by
+ *                sddev_read_data function <br>
+ *                if SD Driver mode is SD_MODE_DMA, data transfer by DMAC
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [out]   uint8_t *buff       : write data buffer
+ * @param [in]    uint32_t psn        : write physical sector number
+ * @param [in]    int32_t cnt         : number of write sectors
+ * @param [in]    int32_t writemode   : memory card write mode, <br>
+ *                  SD_WRITE_WITH_PREERASE : pre-erease write <br>
+ *                  SD_WRITE_OVERWRITE     : overwrite
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_write_sect(st_sdhndl_t *p_hndl, uint8_t *buff, uint32_t psn,
+                        int32_t cnt, int32_t writemode);
+
+/* ---- sd_cd.c ---- */
+/* Function Name: _sd_check_media */
+/**************************************************************************//**
+ * @fn            int32_t _sd_check_media(st_sdhndl_t *p_hndl)
+ * @brief         check card insertion <br>
+ *                if card is inserted, return SD_OK <br>
+ *                if card is not inserted, return SD_ERR <br>
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : card is inserted
+ * @retval        SD_ERR : card is not inserted
+ *****************************************************************************/
+int32_t _sd_check_media(st_sdhndl_t *p_hndl);
+
+/* ---- sd_cmd.c ---- */
+/* Function Name: _sd_send_cmd */
+/**************************************************************************//**
+ * @fn            int32_t _sd_send_cmd(st_sdhndl_t *p_hndl, uint16_t cmd)
+ * @brief         issue SD command, hearafter wait recive response
+ * @warning       not get response and check response errors
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint16_t cmd        : command code
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_send_cmd(st_sdhndl_t *p_hndl, uint16_t cmd);
+
+/* Function Name: _sd_send_acmd */
+/**************************************************************************//**
+ * @fn            int32_t _sd_send_acmd(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg, uint16_t l_arg)
+ * @brief         issue application specific command, hearafter wait recive
+ *                response <br>
+ *                issue CMD55 preceide application specific command
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint16_t cmd        : command code
+ * @param [in]    uint16_t h_arg      : command argument high [31 : 16]
+ * @param [in]    uint16_t l_arg      : command argument low [15 : 0]
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_send_acmd(st_sdhndl_t *p_hndl, uint16_t cmd, uint16_t h_arg, uint16_t l_arg);
+
+/* Function Name: _sd_send_mcmd */
+/**************************************************************************//**
+ * @fn            int32_t _sd_send_mcmd(st_sdhndl_t *p_hndl, uint16_t cmd, uint32_t startaddr)
+ * @brief         issue multiple command (CMD18 or CMD25) <br>
+ *                wait response <br>
+ *                set read start address to startaddr <br>
+ *                after this function finished, start data transfer
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint16_t cmd        : command code (CMD18 or CMD25)
+ * @param [in]    uint32_t startaddr  : data address (command argument)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_send_mcmd(st_sdhndl_t *p_hndl, uint16_t cmd, uint32_t startaddr);
+
+/* Function Name: _sd_card_send_cmd_arg */
+/**************************************************************************//**
+ * @fn            int32_t _sd_card_send_cmd_arg(st_sdhndl_t *p_hndl, uint16_t cmd,
+ *                      int32_t resp, uint16_t h_arg, uint16_t l_arg)
+ * @brief         issue general SD command. <br>
+ *                issue command specified cmd code <br>
+ *                get and check response
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint16_t cmd        : command code (CMD18 or CMD25)
+ * @param [in]    int32_t  resp       : command response
+ * @param [in]    uint16_t h_arg      : command argument high [31 : 16]
+ * @param [in]    uint16_t l_arg      : command argument low [15 : 0]
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_card_send_cmd_arg(st_sdhndl_t *p_hndl, uint16_t cmd, int32_t resp, uint16_t h_arg, uint16_t l_arg);
+
+/* Function Name: _sd_set_arg */
+/**************************************************************************//**
+ * @fn            void _sd_set_arg(st_sdhndl_t *p_hndl, uint16_t h_arg, uint16_t l_arg)
+ * @brief         set command argument to SDHI <br>
+ *                h_arg means higher 16bits [31 : 16] and  set SD_ARG0 <br>
+ *                l_arg means lower 16bits [15 : 0] and set SD_ARG1
+ * @warning       SD_ARG0 and SD_ARG1 are like little endian order
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint16_t h_arg      : command argument high [31 : 16]
+ * @param [in]    uint16_t l_arg      : command argument low [15 : 0]
+ * @retval        none
+ *****************************************************************************/
+void _sd_set_arg(st_sdhndl_t *p_hndl, uint16_t h_arg, uint16_t l_arg);
+
+/* Function Name: _sd_card_send_ocr */
+/**************************************************************************//**
+ * @fn            int32_t _sd_card_send_ocr(st_sdhndl_t *p_hndl, int32_t type)
+ * @brief         get OCR register and check card operation voltage <br>
+ *                if type is SD_MEDIA_SD, issue ACMD41 <br>
+ *                if type is SD_MEDIA_MMC, issue CMD1
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t type        : card type
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_card_send_ocr(st_sdhndl_t *p_hndl, int32_t type);
+
+/* Function Name: _sd_check_resp_error */
+/**************************************************************************//**
+ * @fn            int32_t _sd_check_resp_error(st_sdhndl_t *p_hndl)
+ * @brief         distinguish error bit from R1 response <br>
+ *                set the error bit to p_hndl->error
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : no error detected
+ * @retval        SD_ERR : any errors detected
+ *****************************************************************************/
+int32_t _sd_check_resp_error(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_get_resp */
+/**************************************************************************//**
+ * @fn            int32_t _sd_get_resp(st_sdhndl_t *p_hndl, int32_t resp)
+ * @brief         get response and check response errors. <br>
+ *                get response value from RESP register <br>
+ *                R1, R2, R3,(R4, R5) and R6 types are available
+ *                specify response type by the argument resp <br>
+ *                set response value to SD handle member
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t resp        : response type
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_get_resp(st_sdhndl_t *p_hndl, int32_t resp);
+
+/* Function Name: _sd_check_csd */
+/**************************************************************************//**
+ * @fn            int32_t _sd_check_csd(st_sdhndl_t *p_hndl)
+ * @brief         check CSD register and get following information <br>
+ *                Transfer Speed <br>
+ *                Command Class <br>
+ *                Read Block Length <br>
+ *                Copy Bit <br>
+ *                Write Protect Bit <br>
+ *                File Format Group <br>
+ *                Number of Erase Sector
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_check_csd(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_check_info2_err */
+/**************************************************************************//**
+ * @fn            int32_t _sd_check_info2_err(st_sdhndl_t *p_hndl)
+ * @brief         check SD_INFO2 register errors. <br>
+ *                check error bit of SD_INFO2 register <br>
+ *                set the error bit to p_hndl->error
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_check_info2_err(st_sdhndl_t *p_hndl);
+
+/* ---- sd_int.c ---- */
+/* Function Name: _sd_set_int_mask */
+/**************************************************************************//**
+ * @fn            int32_t _sd_set_int_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+ * @brief         set SD_INFO1 and SD_INFO2 interrupt mask. <br>
+ *                set int_info1_mask and int_info2_mask depend on the mask bits
+ *                value <br>
+ *                if mask bit is one, it is enabled <br>
+ *                if mask bit is zero, it is disabled
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint64_t mask1      : SD_INFO1_MASK1 bits value
+ * @param [in]    uint64_t mask2      : SD_INFO1_MASK2 bits value
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_set_int_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2);
+
+/* Function Name: _sd_clear_int_mask */
+/**************************************************************************//**
+ * @fn            int32_t _sd_clear_int_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+ * @brief         clear SD_INFO1 and SD_INFO2 interrupt mask. <br>
+ *                clear int_cc_status_mask depend on the mask bits value <br>
+ *                if mask bit is one, it is disabled <br>
+ *                if mask bit is zero, it is enabled
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint64_t mask1      : SD_INFO1_MASK1 bits value
+ * @param [in]    uint64_t mask2      : SD_INFO1_MASK2 bits value
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_clear_int_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2);
+
+/* Function Name: _sd_get_int */
+/**************************************************************************//**
+ * @fn            int32_t _sd_get_int(st_sdhndl_t *p_hndl)
+ * @brief         get SD_INFO1 and SD_INFO2 interrupt elements. <br>
+ *                get SD_INFO1 and SD_INFO2 bits <br>
+ *                examine enabled elements <br>
+ *                hearafter, clear SD_INFO1 and SD_INFO2 bits <br>
+ *                save those bits to int_info1 or int_info2
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_get_int(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_clear_info */
+/**************************************************************************//**
+ * @fn            int32_t _sd_clear_info(st_sdhndl_t *p_hndl, uint64_t clear_info1, uint64_t clear_info2)
+ * @brief         clear int_info bits. <br>
+ *                clear int_info1 and int_info2 depend on the clear value
+ * @warning       SD_INFO1 and SD_INFO2 bits are not cleared
+ * @param [out]   st_sdhndl_t *p_hndl  : SD handle
+ * @param [in]    uint64_t clear_info1 : int_info1 clear bits value
+ * @param [in]    uint64_t clear_info2 : int_info2 clear bits value
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_clear_info(st_sdhndl_t *p_hndl, uint64_t clear_info1, uint64_t clear_info2);
+
+/* Function Name: _sd_set_int_dm_mask */
+/**************************************************************************//**
+ * @fn            int32_t _sd_set_int_dm_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+ * @brief         set DM_CM_INFO1_MASK and DM_CM_INFO2_MASK interrupt mask. <br>
+ *                set int_dm_info1_mask and int_dm_info2_mask depend on the mask bits
+ *                value <br>
+ *                if mask bit is one, it is enabled <br>
+ *                if mask bit is zero, it is disabled <br>
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint64_t mask1      : DM_CM_INFO1_MASK bits value
+ * @param [in]    uint64_t mask2      : DM_CM_INFO2_MASK bits value
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_set_int_dm_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2);
+
+/* Function Name: _sd_clear_int_dm_mask */
+/**************************************************************************//**
+ * @fn            int32_t _sd_clear_int_dm_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2)
+ * @brief         clear DM_CM_INFO1_MASK and DM_CM_INFO2_MASK interrupt mask. <br>
+ *                clear int_dm_info1_mask and int_dm_info2_mask depend on the mask bits value <br>
+ *                if mask bit is one, it is disabled <br>
+ *                if mask bit is zero, it is enabled <br>
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    uint64_t mask1      : DM_CM_INFO1_MASK bits value
+ * @param [in]    uint64_t mask2      : DM_CM_INFO2_MASK bits value
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_clear_int_dm_mask(st_sdhndl_t *p_hndl, uint64_t mask1, uint64_t mask2);
+
+/* Function Name: _sd_get_int_dm */
+/**************************************************************************//**
+ * @fn            int32_t _sd_get_int_dm(st_sdhndl_t *p_hndl);
+ * @brief         get DM_CM_INFO1 and DM_CM_INFO2 interrupt elements. <br>
+ *                get DM_CM_INFO1 and DM_CM_INFO2 bits <br>
+ *                examine enabled elements <br>
+ *                hearafter, clear DM_CM_INFO1 and DM_CM_INFO2 bits <br>
+ *                save those bits to int_dm_info1 or int_dm_info2
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : any interrupt occured
+ * @retval        SD_ERR : no interrupt occured
+ *****************************************************************************/
+int32_t _sd_get_int_dm(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_clear_dm_info */
+/**************************************************************************//**
+ * @fn            int32_t _sd_clear_dm_info(st_sdhndl_t *p_hndl, uint64_t clear_info1, uint64_t clear_info2)
+ * @brief         clear int_dm_info bits. <br>
+ *                clear int_dm_info1 and int_dm_info2 depend on the clear value
+ * @warning       DM_CM_INFO1 and DM_CM_INFO2 bits are not cleared
+ * @param [out]   st_sdhndl_t *p_hndl  : SD handle
+ * @param [in]    uint64_t clear_info1 : int_dm_info1 clear bits value
+ * @param [in]    uint64_t clear_info2 : int_dm_info2 clear bits value
+ * @retval        SD_OK : end of succeed
+ *****************************************************************************/
+int32_t _sd_clear_dm_info(st_sdhndl_t *p_hndl, uint64_t clear_info1, uint64_t clear_info2);
+
+/* ---- sd_util.c ---- */
+/* Function Name: _sd_set_clock */
+/**************************************************************************//**
+ * @fn            int32_t _sd_set_clock(st_sdhndl_t *p_hndl, int32_t clock, int32_t enable)
+ * @brief         control SD clock. <br>
+ *                supply or halt SD clock <br>
+ *                if enable is SD_CLOCK_ENABLE, supply SD clock <br>
+ *                if enable is SD_CLOCK_DISKABLE, halt SD clock <br>
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t clock       : SD clock frequency
+ * @param [in]    int32_t enable      : supply or halt SD clock
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_set_clock(st_sdhndl_t *p_hndl, int32_t clock, int32_t enable);
+
+/* Function Name: _sd_set_port */
+/**************************************************************************//**
+ * @fn            int32_t _sd_set_port(st_sdhndl_t *p_hndl, int32_t port)
+ * @brief         control data bus width. <br>
+ *                change data bus width <br>
+ *                if port is SD_PORT_SERIAL, set data bus width 1bit <br>
+ *                if port is SD_PORT_PARALEL, set data bus width 4bits <br>
+ *                change between 1bit and 4bits by ACMD6
+ * @warning       before execute this function, check card supporting bus
+ *                width <br>
+ *                SD memory card is 4bits support mandatory
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t port        : setting bus with
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_set_port(st_sdhndl_t *p_hndl, int32_t port);
+
+/* Function Name: _sd_iswp */
+/**************************************************************************//**
+ * @fn            int32_t _sd_iswp(st_sdhndl_t *p_hndl)
+ * @brief         check hardware write protect refer to SDHI register <br>
+ *                if WP pin is disconnected to SDHI, return value has no
+ *                meaning
+ * @warning       don't check CSD write protect bits and ROM card
+ * @param [in]    st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_WP_OFF (0) : not write protected
+ * @retval        SD_WP_HW  (1) : write protected
+ *****************************************************************************/
+int32_t _sd_iswp(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_set_err */
+/**************************************************************************//**
+ * @fn            int32_t _sd_set_err(st_sdhndl_t *p_hndl, int32_t error)
+ * @brief         set errors information. <br>
+ *                set error information (=error) to SD Handle member
+ *                (=p_hndl->error)
+ * @warning       if p_hndl->error was already set, no overwrite it
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t error       : setting error information
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_set_err(st_sdhndl_t *p_hndl, int32_t error);
+
+/* Function Name: _sd_bit_search */
+/**************************************************************************//**
+ * @fn            int32_t _sd_bit_search(uint16_t data)
+ * @brief         get bit information. <br>
+ *                check every bits of argument (data) from LSB <br>
+ *                return first bit whose value is 1'b <br>
+ *                bit number is big endian (MSB is 0)
+ * @warning       just 16bits value can be applied
+ * @param [in]    uint16_t data : checked data
+ * @retval        not less than 0 : bit number has 1'b
+ * @retval        -1 : no bit has 1'b
+ *****************************************************************************/
+int32_t _sd_bit_search(uint16_t data);
+
+/* Function Name: _sd_get_size */
+/**************************************************************************//**
+ * @fn            int32_t _sd_get_size(st_sdhndl_t *p_hndl, uint32_t area)
+ * @brief         get card size. <br>
+ *                get memory card size
+ * @warning       protect area is just the number of all sectors
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t area        : memory area (bit0 : user area, bit1 : protect area)
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_get_size(st_sdhndl_t *p_hndl, uint32_t area);
+
+/* Function Name: _sd_standby */
+/**************************************************************************//**
+ * @fn            int32_t _sd_standby(st_sdhndl_t *p_hndl)
+ * @brief         transfer card to stand-by state. <br>
+ *                transfer card from transfer state to stand-by state
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_standby(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_active */
+/**************************************************************************//**
+ * @fn            int32_t _sd_active(st_sdhndl_t *p_hndl)
+ * @brief         transfer card to transfer state. <br>
+ *                transfer card from stand-by state to transfer state
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_active(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_inactive */
+/**************************************************************************//**
+ * @fn            int32_t _sd_inactive(st_sdhndl_t *p_hndl)
+ * @brief         transfer card to inactive state. <br>
+ *                transfer card from any state to inactive state
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @retval        SD_OK  : end of succeed
+ * @retval        SD_ERR : end of error
+ *****************************************************************************/
+int32_t _sd_inactive(st_sdhndl_t *p_hndl);
+
+/* Function Name: _sd_memset */
+/**************************************************************************//**
+ * @fn            int32_t _sd_memset(uint8_t *p, uint8_t data, uint32_t cnt)
+ * @brief         set memory. <br>
+ *                fill memory filling data(=data) from start address(=p)
+ *                by filling size(=cnt)
+ * @warning       .
+ * @param [out]   uint8_t *p   : start address of memory
+ * @param [in]    uint8_t data : filling data
+ * @param [in]    uint32_t cnt : filling size
+ * @retval        0 : end of succeed
+ *****************************************************************************/
+int32_t _sd_memset(uint8_t *p, uint8_t data, uint32_t cnt);
+
+/* Function Name: _sd_memcpy */
+/**************************************************************************//**
+ * @fn            int32_t _sd_memcpy(uint8_t *dst, uint8_t *src, uint32_t cnt)
+ * @brief         copy memory. <br>
+ *                copy data from source address(=src) to destination address
+ *                (=dst) by copy size(=cnt)
+ * @warning       .
+ * @param [out]   uint8_t *dst : destination address
+ * @param [in]    uint8_t *src : source address
+ * @param [in]    uint32_t cnt : copy size
+ * @retval        0 : end of succeed
+ *****************************************************************************/
+int32_t _sd_memcpy(uint8_t *dst, uint8_t *src, uint32_t cnt);
+
+/* Function Name: _sd_rand */
+/**************************************************************************//**
+ * @fn            uint16_t _sd_rand(void)
+ * @brief         create Volume ID Number. <br>
+ *                get Volume ID Number <br>
+ *                Volume ID Number is created by pseudo random number
+ * @warning       .
+ * @param [in]    none
+ * @retval        created Volume ID Number
+ *****************************************************************************/
+uint16_t _sd_rand(void);
+
+/* Function Name: _sd_srand */
+/**************************************************************************//**
+ * @fn            void    _sd_srand(uint32_t seed)
+ * @brief         set initial value of Volume ID Number.
+ * @warning       .
+ * @param [in]    uint32_t seed : initial seting value
+ * @retval        none
+ *****************************************************************************/
+void    _sd_srand(uint32_t seed);
+
+/* Function Name: _sd_wait_rbusy */
+/**************************************************************************//**
+ * @fn            int32_t _sd_wait_rbusy(st_sdhndl_t *p_hndl, int32_t time)
+ * @brief         wait response busy. <br>
+ *                wait response busy finished
+ * @warning       .
+ * @param [out]   st_sdhndl_t *p_hndl : SD handle
+ * @param [in]    int32_t time        : response busy wait interval
+ * @retval        SD_OK  : response busy finished
+ * @retval        SD_ERR : response busy not finished
+ *****************************************************************************/
+int32_t _sd_wait_rbusy(st_sdhndl_t *p_hndl, int32_t time);
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+#endif  /* SD_H   */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/src/sd/inc/sys_sel.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,92 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sys_sel.h
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : SD Driver system select option
+* Operation    :
+* Limitations  : None
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02     Support for OS
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+#ifndef SYS_SEL_H
+#define SYS_SEL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#if(1) /* mbed */
+#if defined(TARGET_RZ_A2XX)
+#define DRIVER_NAME             "RENESAS RZ/A2 SD Driver Ver1.20"
+#else
+    error!!
+#endif
+#else
+/* target configration */
+#define TARGET_RZ_A2
+
+#if defined(TARGET_RZ_A2)
+#define DRIVER_NAME             "RENESAS RZ/A2 SD Driver Ver1.20"
+#else
+    error!!
+#endif
+#endif
+
+/* ==== configuration ===== */
+/* 16bits width */
+#define SD_REG_SHIFT            (0u)
+#define SD_BYTE_OFFSET          (0x1000u)   /* Change the base address from SCC to SDHI/MMCHI. */
+
+/* ==== number of ports ==== */
+#define NUM_PORT                (2)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+#endif /* SYS_SEL_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/userdef/sd_dev_dmacdrv.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,512 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_dev_dmacdrv.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : RZ/A2M SD Sample Program - DMAC Sample Program (Main)
+* Operation    : 
+* Limitations  : None
+******************************************************************************
+* History : DD.MM.YYYY Version Description
+*         : 16.03.2018 1.00    First Release
+*         : 14.12.2018 1.01    Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02    Support for OS
+*         : 29.05.2019 1.20    Correspond to internal coding rules
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#if(1) // mbed
+#include "cpg_iodefine.h"
+#else
+#include "r_mmu_lld_rza2m.h"
+#include "r_stb_lld_rza2m.h"
+#endif
+#include "r_sdif.h"
+#include "sd.h"
+#include "sd_dev_dmacdrv.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#if(1) // mbed
+#define     UNUSED_PARAM(param)             (void)(param)
+#endif
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: sd_DMAC_PeriReqInit
+* Description  : Initialize DMAC.
+* Arguments    : int32_t  sd_port : channel no (0 or 1)
+*              : uint32_t buff    : buffer addrees to transfer datas
+*              : int32_t  dir     : direction to transfer
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sd_DMAC_PeriReqInit(int32_t sd_port, uint32_t buff, int32_t dir)
+{
+    st_sdhndl_t *p_hndl;
+    uint32_t    paddr;
+#if(1) /* mbed */
+#else
+    e_mmu_err_t e_mmu_err;
+#endif
+
+    if ((0 != sd_port) && (1 != sd_port))
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+    
+    /* Cast to an appropriate type */
+    if (NULL == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* set DMA controller */
+    /* W (CC_EXT_MODE, H'0000_0002) */
+    SD_OUTP(p_hndl, CC_EXT_MODE, (uint64_t)(SD_INP(p_hndl, CC_EXT_MODE) | CC_EXT_MODE_DMASDRW));
+
+    if (SD_TRANS_READ == dir)
+    {
+        /* W (DM_CM_DTRAN_MODE, "channel01", "bus width") */
+        SD_OUTP(p_hndl, DM_CM_DTRAN_MODE, DM_CM_DTRAN_MODE_READ);
+    }
+    else
+    {
+        /* W (DM_CM_DTRAN_MODE, "channel00", "bus width") */
+        SD_OUTP(p_hndl, DM_CM_DTRAN_MODE, DM_CM_DTRAN_MODE_WRITE);
+    }
+
+    /* W (DM_DTRAN_ADDR, "address") */
+#if(1) /* mbed */
+    paddr = buff;
+    SD_OUTP(p_hndl, DM_DTRAN_ADDR, paddr);
+#else
+    e_mmu_err = R_MMU_VAtoPA(buff, &paddr);
+
+    if (MMU_SUCCESS == e_mmu_err)
+    {
+        /* Cast to an appropriate type */
+        SD_OUTP(p_hndl, DM_DTRAN_ADDR, paddr);
+    }
+    else
+    {
+        return SD_ERR;
+    }
+#endif
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sd_DMAC_PeriReqInit
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sd_DMAC_Open
+* Description  : Start DMAC.
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : int32_t dir     : direction to transfer
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sd_DMAC_Open(int32_t sd_port, int32_t dir)
+{
+    st_sdhndl_t  *p_hndl;
+
+    if ((0 != sd_port) && (1 != sd_port))
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* enable dtranend and dtranerr */
+    if (SD_TRANS_READ == dir)
+    {
+        /* Cast to an appropriate type */
+        (void)_sd_set_int_dm_mask(p_hndl, DM_CM_INFO1_MASK_DTRANEND1, DM_CM_INFO2_MASK_DTRANERR1);
+    }
+    else
+    {
+        /* Cast to an appropriate type */
+        (void)_sd_set_int_dm_mask(p_hndl, DM_CM_INFO1_MASK_DTRANEND0, DM_CM_INFO2_MASK_DTRANERR0);
+    }
+
+    /* W (DM_CM_DTRAN_CTRL, H'0000_0001) */
+    SD_OUTP(p_hndl, DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_DM_START);
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sd_DMAC_Open
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sd_DMAC_Close
+* Description  : Stop DMAC.
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sd_DMAC_Close(int32_t sd_port)
+{
+    st_sdhndl_t  *p_hndl;
+
+    if ((0 != sd_port) && (1 != sd_port))
+    {
+        return SD_ERR;
+    }
+
+    p_hndl = SD_GET_HNDLS(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL == p_hndl)
+    {
+        return SD_ERR;  /* not initilized */
+    }
+
+    /* W (DM_CM_INFO1, H'0000_0000) */
+    SD_OUTP(p_hndl, DM_CM_INFO1, (uint64_t)0);
+
+    /* SD_BUF disable DMA transfer */
+    /* W (CC_EXT_MODE, H'0000_0000) */
+    SD_OUTP(p_hndl, CC_EXT_MODE, (uint64_t)(SD_INP(p_hndl, CC_EXT_MODE) & ~CC_EXT_MODE_DMASDRW));
+
+    /* disable dtransend and dtranerr */
+    (void)_sd_clear_int_dm_mask(p_hndl,
+
+                                /* Cast to an appropriate type */
+                                (DM_CM_INFO1_MASK_DTRANEND0|DM_CM_INFO1_MASK_DTRANEND1),
+
+                                /* Cast to an appropriate type */
+                                (DM_CM_INFO2_MASK_DTRANERR0|DM_CM_INFO2_MASK_DTRANERR1));
+
+    /* Clear dm_cm_info */
+    (void)_sd_clear_dm_info(p_hndl,
+
+                            /* Cast to an appropriate type */
+                            (DM_CM_INFO1_MASK_DTRANEND0|DM_CM_INFO1_MASK_DTRANEND1),
+
+                            /* Cast to an appropriate type */
+                            (DM_CM_INFO2_MASK_DTRANERR0|DM_CM_INFO2_MASK_DTRANERR1));
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sd_DMAC_Close
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sd_DMAC_Reset
+* Description  : Soft resets of the SDHI module built-in DMAC.
+* Arguments    : int32_t  sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sd_DMAC_Reset(int32_t sd_port)
+{
+#if(1) /* mbed */
+    int32_t               ret;
+    st_sdhndl_t           *p_hndl;
+    st_sdhi_info_dev_ch_t *p_ch;
+    volatile uint8_t      reg_read_8;
+    volatile uint64_t     dummy_read_64;
+
+    ret  = SD_OK;
+
+    if ((sd_port != 0) && (sd_port != 1)) {
+        ret = SD_ERR;
+    } else {
+        p_hndl = SD_GET_HNDLS(sd_port);
+        if (p_hndl == NULL) {
+            ret = SD_ERR;  /* not initilized */
+        } else {
+            p_ch = sddev_get_dev_ch_instance(sd_port);
+            if (p_ch != NULL) {
+                /* (1) Transition to Software Reset State */
+                /* (b) Procedure for transition to the software reset state of modules for which the STBREQ register
+                   has a corresponding bit */
+                /* 1. Set the corresponding bit in the STBREQ register to 1 to generate a request to stop the module. */
+                /* 2. Confirm that the corresponding bit in the STBACK register has been set to 1.  */
+                if (sd_port == 0) {
+                    while (1) {
+                        CPG.STBREQ1.BYTE |= 0x04;
+                        reg_read_8 = CPG.STBREQ1.BYTE; /* dummy read */
+                        reg_read_8 = CPG.STBACK1.BYTE;
+                        if ((reg_read_8 & 0x04) != 0) {
+                            break;
+                        }
+                    }
+                } else {
+                    while (1) {
+                        CPG.STBREQ1.BYTE |= 0x02;
+                        reg_read_8 = CPG.STBREQ1.BYTE;
+                        if ((reg_read_8 & 0x02) != 0) {
+                            break;
+                        }
+                    }
+                }
+
+                /* 3. Set the SRST bit of the corresponding module to 1, then dummy-read the same register. */
+                /* Logic reversed */
+                SD_OUTP(p_hndl, DM_CM_RST, DM_CM_RST_RESET);
+                dummy_read_64 = SD_INP(p_hndl, DM_CM_RST);
+                (void)dummy_read_64;
+            } else { /* if (p_ch != NULL) */
+                ret = SD_ERR;
+            }
+        }
+    }
+    return ret;
+#else
+    int32_t               ret;
+    st_sdhndl_t           *p_hndl;
+    st_sdhi_info_dev_ch_t *p_ch;
+    e_stb_err_t           e_stb_err;
+    volatile uint64_t     dummy_read_64;
+
+    ret  = SD_OK;
+
+    if ((0 != sd_port) && (1 != sd_port))
+    {
+        ret = SD_ERR;
+    }
+    else
+    {
+        p_hndl = SD_GET_HNDLS(sd_port);
+
+        /* Cast to an appropriate type */
+        if (NULL == p_hndl)
+        {
+            ret = SD_ERR;  /* not initilized */
+        }
+        else
+        {
+            p_ch = sddev_get_dev_ch_instance(sd_port);
+
+            /* Cast to an appropriate type */
+            if (NULL != p_ch)
+            {
+                /*
+                   (1) Transition to Software Reset State
+                   (b) Procedure for transition to the software reset state of modules for which the STBREQ register
+                    has a corresponding bit
+                   1. Set the corresponding bit in the STBREQ register to 1 to generate a request to stop the module.
+                   2. Confirm that the corresponding bit in the STBACK register has been set to 1.
+                */
+                e_stb_err = STB_AGAIN;
+                while (STB_AGAIN == e_stb_err)
+                {
+                    e_stb_err = R_STB_RequestModuleStop(p_ch->stb.stb_ch);
+                }
+                if (STB_SUCCESS == e_stb_err)
+                {
+                    /* 3. Set the SRST bit of the corresponding module to 1, then dummy-read the same register. */
+                    /* Logic reversed *//* Cast to an appropriate type */
+                    SD_OUTP(p_hndl, DM_CM_RST, DM_CM_RST_RESET);
+
+                    /* Cast to an appropriate type */
+                    dummy_read_64 = SD_INP(p_hndl, DM_CM_RST);
+
+                    /* Cast to an appropriate type */
+                    UNUSED_PARAM(dummy_read_64);
+                }
+                else
+                {
+                    ret = SD_ERR;
+                }
+            }
+            else /* if (NULL != p_ch) */
+            {
+                ret = SD_ERR;
+            }
+        }
+    }
+    return ret;
+#endif
+}
+/*******************************************************************************
+ End of function sd_DMAC_Reset
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sd_DMAC_Released
+* Description  : Soft resets released of the SDHI module built-in DMAC.
+* Arguments    : int32_t  sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sd_DMAC_Released(int32_t sd_port)
+{
+#if(1) /* mbed */
+    int32_t               ret;
+    st_sdhndl_t           *p_hndl;
+    st_sdhi_info_dev_ch_t *p_ch;
+    volatile uint8_t      reg_read_8;
+    volatile uint64_t     dummy_read_64;
+
+    ret  = SD_OK;
+
+    if ((sd_port != 0) && (sd_port != 1)) {
+        ret = SD_ERR;
+    } else { /* if ((sd_port != 0) && (sd_port != 1)) */
+        p_hndl = SD_GET_HNDLS(sd_port);
+        if (p_hndl == NULL) {
+            ret = SD_ERR;  /* not initilized */
+        } else { /* if (p_hndl == NULL) */
+            p_ch = sddev_get_dev_ch_instance(sd_port);
+            if (p_ch != NULL) {
+                /* (2) Canceling Software Reset */
+                /* (b) Procedure for release from the software reset state of modules for which the STBREQ register
+                       has a corresponding bit  */
+                /* 1. Clear the SRST bit of the corresponding module to 0, then dummy-read the same register.   */
+                /* Logic reversed */
+                SD_OUTP(p_hndl, DM_CM_RST, DM_CM_RST_RELEASED);
+                dummy_read_64 = SD_INP(p_hndl, DM_CM_RST);
+                (void)dummy_read_64;
+
+                /* 2. Clear the corresponding bit in the STBREQ register to 0 to cancel the request to stop the module. */
+                /* 3. Confirm that the corresponding bit in the STBACK register has been cleared to 0. */
+                if (sd_port == 0) {
+                    while (1) {
+                        CPG.STBREQ1.BYTE &= ~0x04;
+                        reg_read_8 = CPG.STBREQ1.BYTE; /* dummy read */
+                        reg_read_8 = CPG.STBACK1.BYTE;
+                        if ((reg_read_8 & 0x04) == 0) {
+                            break;
+                        }
+                    }
+                } else {
+                    while (1) {
+                        CPG.STBREQ1.BYTE &= ~0x02;
+                        reg_read_8 = CPG.STBREQ1.BYTE; /* dummy read */
+                        reg_read_8 = CPG.STBACK1.BYTE;
+                        if ((reg_read_8 & 0x02) == 0) {
+                            break;
+                        }
+                    }
+                }
+            } else { /* if (p_ch != NULL) */
+                ret = SD_ERR;
+            }
+        }
+    }
+    return ret;
+#else
+    int32_t               ret;
+    st_sdhndl_t           *p_hndl;
+    st_sdhi_info_dev_ch_t *p_ch;
+    e_stb_err_t           e_stb_err;
+    volatile uint64_t     dummy_read_64;
+
+    ret  = SD_OK;
+
+    if ((0 != sd_port) && (1 != sd_port))
+    {
+        ret = SD_ERR;
+    }
+    else /* if ((0 != sd_port) && (1 != sd_port)) */
+    {
+        p_hndl = SD_GET_HNDLS(sd_port);
+
+        /* Cast to an appropriate type */
+        if (NULL == p_hndl)
+        {
+            ret = SD_ERR;  /* not initilized */
+        }
+        else /* if (NULL == p_hndl) */
+        {
+            p_ch = sddev_get_dev_ch_instance(sd_port);
+
+            /* Cast to an appropriate type */
+            if (NULL != p_ch)
+            {
+                /* (2) Canceling Software Reset */
+                /* (b) Procedure for release from the software reset state of modules for which the STBREQ register
+                       has a corresponding bit  */
+                /* 1. Clear the SRST bit of the corresponding module to 0, then dummy-read the same register.   */
+                /* Logic reversed *//* Cast to an appropriate type */
+                SD_OUTP(p_hndl, DM_CM_RST, DM_CM_RST_RELEASED);
+
+                /* Cast to an appropriate type */
+                dummy_read_64 = SD_INP(p_hndl, DM_CM_RST);
+
+                /* Cast to an appropriate type */
+                UNUSED_PARAM(dummy_read_64);
+
+                /* 2. Clear the corresponding bit in the STBREQ register to 0 to cancel the request to stop the module.
+                   3. Confirm that the corresponding bit in the STBACK register has been cleared to 0. */
+                e_stb_err = STB_AGAIN;
+                while (STB_AGAIN == e_stb_err)
+                {
+                    e_stb_err = R_STB_RequestModuleStart(p_ch->stb.stb_ch);
+                }
+                if (STB_SUCCESS != e_stb_err)
+                {
+                    ret = SD_ERR;
+                }
+            }
+            else /* if (NULL != p_ch) */
+            {
+                ret = SD_ERR;
+            }
+        }
+    }
+    return ret;
+#endif
+}
+/*******************************************************************************
+ End of function sd_DMAC_Released
+ ******************************************************************************/
+
+/* End of File */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/userdef/sd_dev_dmacdrv.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,168 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/*******************************************************************************
+* File Name    : sd_dev_dmacdrv.h
+* Version      : 1.20
+* Description  : RZ/A2M SD Sample Program - DMAC Sample Program
+******************************************************************************/
+/*****************************************************************************
+* History : DD.MM.YYYY Version  Description
+*         : 16.03.2018 1.00     First Release
+*         : 14.12.2018 1.01     Changed the DMAC soft reset procedure.
+*         : 29.05.2019 1.20     Correspond to internal coding rules
+******************************************************************************/
+#if(1) // mbed
+#include "cmsis_os.h"
+#include "irq_ctrl.h"
+#else
+#include "r_stb_lld_rza2m.h"
+#include "r_intc_lld_rza2m.h"
+#endif
+#include "r_sd_cfg.h"
+
+#ifndef SD_DEV_DMACDRV_H
+#define SD_DEV_DMACDRV_H
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct
+{
+    struct
+    {
+        bool_t                  stb_pon_init;
+#if(1) // mbed
+#else
+        e_stb_module_t          stb_ch;
+#endif
+    } stb;
+    struct
+    {
+#if(1) // mbed
+        IRQn_ID_t               int_id;
+        uint32_t                int_priority;
+        void                    (* p_func)(void);
+#else
+        e_r_drv_intc_intid_t    int_id;
+        e_r_drv_intc_priority_t int_priority;
+        void                    (* p_func)(uint32_t int_sense);
+#endif
+    } intc;
+    struct
+    {
+        bool_t                  gpio_init;
+        bool_t                  gpio_vol_init;
+    } gpio;
+#ifdef SD_CFG_HWINT
+    struct
+    {
+#if(1) // mbed
+        osSemaphoreId_t         sem_sync;
+        osSemaphoreId_t         sem_dma;
+#else
+        uint32_t                sem_sync;
+        uint32_t                sem_dma;
+#endif
+    } semaphore;
+#endif /* #ifdef SD_CFG_HWINT */
+} st_sdhi_info_dev_ch_t;
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+/* Function Name: sd_DMAC_PeriReqInit */
+/**************************************************************************//**
+ * @fn            int32_t sd_DMAC_PeriReqInit(int32_t sd_port, uint32_t buff, int32_t dir)
+ * @brief         Initialize DMAC.
+ * @warning       .
+ * @param [in]    int32_t  sd_port : channel no (0 or 1).
+ * @param [in]    uint32_t buff    : buffer addrees to transfer datas.
+ * @param [in]    int32_t  dir     : direction to transfer.
+ * @retval        success : SD_OK.
+ * @retval        fail    : SD_ERR.
+ *****************************************************************************/
+int32_t sd_DMAC_PeriReqInit(int32_t sd_port, uint32_t buff, int32_t dir);
+
+/* Function Name: sd_DMAC_Open */
+/**************************************************************************//**
+ * @fn            int32_t sd_DMAC_Open(int32_t sd_port, int32_t dir)
+ * @brief         Start DMAC.
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1).
+ * @param [in]    int32_t dir     : direction to transfer.
+ * @retval        success : SD_OK.
+ * @retval        fail    : SD_ERR.
+ *****************************************************************************/
+int32_t sd_DMAC_Open(int32_t sd_port, int32_t dir);
+
+/* Function Name: sd_DMAC_Close */
+/**************************************************************************//**
+ * @fn            int32_t sd_DMAC_Close(int32_t sd_port)
+ * @brief         Stop DMAC.
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1).
+ * @retval        success : SD_OK.
+ * @retval        fail    : SD_ERR.
+ *****************************************************************************/
+int32_t sd_DMAC_Close(int32_t sd_port);
+
+/* Function Name: sd_DMAC_Reset */
+/**************************************************************************//**
+ * @fn            int32_t sd_DMAC_Reset(int32_t sd_port)
+ * @brief         Soft resets of the SDHI module built-in DMAC.
+ * @warning       .
+ * @param [in]    int32_t  sd_port : channel no (0 or 1).
+ * @retval        success : SD_OK.
+ * @retval        fail    : SD_ERR.
+ *****************************************************************************/
+int32_t sd_DMAC_Reset(int32_t sd_port);
+
+/* Function Name: sd_DMAC_Released */
+/**************************************************************************//**
+ * @fn            int32_t sd_DMAC_Released(int32_t sd_port)
+ * @brief         Soft resets released of the SDHI module built-in DMAC.
+ * @warning       .
+ * @param [in]    int32_t  sd_port : channel no (0 or 1).
+ * @retval        success : SD_OK.
+ * @retval        fail    : SD_ERR.
+ *****************************************************************************/
+int32_t sd_DMAC_Released(int32_t sd_port);
+
+/* Function Name: sddev_get_dev_ch_instance */
+/**************************************************************************//**
+ * @fn            st_sdhi_info_dev_ch_t *sddev_get_dev_ch_instance(int32_t sd_port)
+ * @brief         Get SDHI driver target CPU interface information object.
+ * @warning       .
+ * @param [in]    int32_t sd_port : channel no (0 or 1).
+ * @retval        success : pointer to SDHI driver target CPU interface information.
+ * @retval        fail    : NULL.
+ *****************************************************************************/
+st_sdhi_info_dev_ch_t *sddev_get_dev_ch_instance(int32_t sd_port);
+
+#endif  /* SD_DEV_DMACDRV_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SDBlockDevice_GRBoard/TARGET_RZ_A2XX/sdhi-driver/r_sdhi_simplified/userdef/sd_dev_low.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1845 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/******************************************************************************
+* System Name  : SDHI Driver
+* File Name    : sd_dev_low.c
+* Version      : 1.20
+* Device(s)    : RZ/A2M
+* Tool-Chain   : e2 studio (GCC ARM Embedded)
+* OS           : None
+* H/W Platform : RZ/A2M Evaluation Board
+* Description  : RZ/A2M SD Driver Sample Program
+* Operation    : 
+* Limitations  : Ch0 and Ch1 can't be used at the same time, because the timers
+*              : used on Ch0 and Ch1 are common.
+******************************************************************************
+* History : DD.MM.YYYY Version Description
+*         : 16.03.2018 1.00    First Release
+*         : 14.12.2018 1.01    Changed the DMAC soft reset procedure.
+*         : 28.12.2018 1.02    Support for OS
+*         : 29.05.2019 1.20    Correspond to internal coding rules
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "iobitmask.h"
+#if(1) // mbed
+#include "cmsis.h"
+#include "cmsis_os.h"
+#include "irq_ctrl.h"
+#include "mbed_wait_api.h"
+#include "platform/mbed_critical.h"
+#else
+#include "rza_io_regrw.h"
+#include "r_intc_lld_rza2m.h"
+#include "r_stb_lld_rza2m.h"
+#include "r_gpio_lld_rza2m.h"
+#include "r_devlink_wrapper.h"
+#include "r_os_abstraction_api.h"
+#include "r_compiler_abstraction_api.h"
+#endif
+#include "r_sdif.h"
+#include "r_sd_cfg.h"
+#include "sd_dev_dmacdrv.h"
+#include "r_sdhi_simplified_drv_sc_cfg.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define INT_PRV_LEVEL_SDHI      (26u)       /* SDHI interrupt level  */
+
+#define SDHI_PRV_CH_0           (0)
+#define SDHI_PRV_CH_1           (1)
+#define SDHI_PRV_CH_NUM         (2)
+
+#define SDHI_PRV_PPOC_POC_3_3V  (1u)
+
+#define SDHI_PRV_CLK_TDSEL_3_3V (3u)
+
+#define SDHI_PRV_CARDDET_TIME   (1000uL)
+#define SDHI_PRV_POWERON_TIME   (100uL)
+
+#ifdef SD_CFG_HWINT
+#define SDHI_PRV_MAX_WAITTIME   (0xFFFFuL)
+
+#else /* #ifdef SD_CFG_HWINT */
+#define SDHI_PRV_1MSEC          (1uL)
+
+#endif /* #ifdef SD_CFG_HWINT */
+
+#define SDHI_PRV_TO_SPEED       (512uL)
+#define SDHI_PRV_1024BYTE       (1024uL)
+#define SDHI_PRV_1000MSEC       (1000uL)
+
+#if(1) // mbed
+#define     UNUSED_PARAM(param)             (void)(param)
+#endif
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+/* static uint8_t g_sdhi_priority_backup; */
+
+static int32_t sddev_init_voltage(int32_t sd_port);
+#if(1) // mbed
+static void sddev_sd_int_handler_0(void);
+static void sddev_sd_int_handler_1(void);
+osSemaphoreDef(sdint_sem_sync);
+osSemaphoreDef(sdint_sem_dma);
+#else
+static void sddev_sd_int_handler_0(uint32_t int_sense);
+static void sddev_sd_int_handler_1(uint32_t int_sense);
+#endif
+
+#if(1) // mbed
+static st_sdhi_info_dev_ch_t s_sdhi_dev_ch[SDHI_PRV_CH_NUM] =
+{
+    /*--- ch 0 ---*/
+    {
+        { false                                                             }, /* stb  */
+        { SDHI0_0_IRQn,          INT_PRV_LEVEL_SDHI, sddev_sd_int_handler_0 }, /* intc */
+        { false,                 false                                      }, /* gpio */
+#ifdef SD_CFG_HWINT
+        { 0uL,                   0uL                                        }  /* semaphore */
+#endif /* #ifdef SD_CFG_HWINT */
+    },
+
+    /*--- ch 1 ---*/
+    {
+        { false                                                             }, /* stb  */
+        { SDHI1_0_IRQn,          INT_PRV_LEVEL_SDHI, sddev_sd_int_handler_1 }, /* intc */
+        { false,                 false                                      }, /* gpio */
+#ifdef SD_CFG_HWINT
+        { 0uL,                   0uL                                        }  /* semaphore */
+#endif /* #ifdef SD_CFG_HWINT */
+    }
+};
+#else
+static st_sdhi_info_dev_ch_t s_sdhi_dev_ch[SDHI_PRV_CH_NUM] =
+{
+    /*--- ch 0 ---*/
+    {
+        { false,                 MODULE_SDMMC0                              }, /* stb  */
+        { INTC_ID_SDMMC_SDHI0_0, INT_PRV_LEVEL_SDHI, sddev_sd_int_handler_0 }, /* intc */
+        { false,                 false                                      }, /* gpio */
+#ifdef SD_CFG_HWINT
+        { 0uL,                   0uL                                        }  /* semaphore */
+#endif /* #ifdef SD_CFG_HWINT */
+    },
+
+    /*--- ch 1 ---*/
+    {
+        { false,                 MODULE_SDMMC1                              }, /* stb  */
+        { INTC_ID_SDMMC_SDHI1_0, INT_PRV_LEVEL_SDHI, sddev_sd_int_handler_1 }, /* intc */
+        { false,                 false                                      }, /* gpio */
+#ifdef SD_CFG_HWINT
+        { 0uL,                   0uL                                        }  /* semaphore */
+#endif /* #ifdef SD_CFG_HWINT */
+    }
+};
+#endif
+
+#if(1) // mbed
+#else
+/*--- PD1 voltage ---*/
+static const r_gpio_port_pin_t s_sd_init_ch0_voltage_pin_list[] =
+{
+    /* Cast to an appropriate type */
+    GPIO_PORT_D_PIN_1,
+};
+
+static st_r_drv_gpio_pin_list_t s_sd_init_ch0_voltage =
+{
+    &s_sd_init_ch0_voltage_pin_list[0],                                 /* p_pin_list   */
+    (sizeof(s_sd_init_ch0_voltage_pin_list))/sizeof(r_gpio_port_pin_t), /* count        */
+    GPIO_SUCCESS                                                        /* err(r/w)     */
+};
+
+/* Cast to an appropriate type */
+static st_r_drv_gpio_pin_rw_t s_sd_ch0_voltage_3_3 = { GPIO_PORT_D_PIN_1, GPIO_LEVEL_HIGH, GPIO_SUCCESS };
+
+/* SD current */
+static const st_r_drv_gpio_sc_config_t s_sd_gpio_current_ch0[] =
+{
+/*  { pin,               { function(no used),    tint(no used),     current           } } */
+    
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_CLK,  { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_12mA } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_CMD,  { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT0, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT1, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT2, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT3, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT4, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT5, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT6, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_DAT7, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD0_RST,  { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } }
+};
+
+static const st_r_drv_gpio_sc_config_t s_sd_gpio_current_ch1[] =
+{
+/*  { pin,               { function(no used),    tint(no used),     current           } } */
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD1_CLK,  { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_12mA } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD1_CMD,  { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD1_DAT0, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD1_DAT1, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD1_DAT2, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+
+    /* Cast to an appropriate type */
+    { GPIO_PIN_SD1_DAT3, { GPIO_FUNC_SC_DEFAULT, GPIO_TINT_DISABLE, GPIO_CURRENT_6mA  } },
+};
+
+static st_r_drv_gpio_pin_init_table_t s_sd_gpio_current[] =
+{
+/*    p_config_table,          count,                                                           err(r/w) */
+    { &s_sd_gpio_current_ch0[0], ((sizeof(s_sd_gpio_current_ch0))/sizeof(st_r_drv_gpio_sc_config_t)), GPIO_SUCCESS },
+    { &s_sd_gpio_current_ch1[0], ((sizeof(s_sd_gpio_current_ch1))/sizeof(st_r_drv_gpio_sc_config_t)), GPIO_SUCCESS }
+};
+#endif
+
+/******************************************************************************
+* Function Name: sddev_init
+* Description  : Initialize H/W to use SDHI
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_init(int32_t sd_port)
+{
+#if(1) // mbed
+    int32_t               ret;
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret  = SD_OK;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    if (p_ch != NULL) {
+        core_util_critical_section_enter();
+
+        /* --- SDHI, clear module standby start ---*/
+        /* [Canceling Module Standby Function] */
+        /* a. Release from the module standby state after the activation of the
+              module by a power-on reset while the MSTP bit is set to 1
+           1. Clear the MSTP bit to 0.
+           2. After that, dummy-read the same register. */
+
+        /* b. Release from the module standby state after a transition to standby
+              following activation of the module
+           1. Clear the MSTP bit to 0, then dummy-read the same register.   */
+        volatile uint8_t reg_read_8;
+
+        if (sd_port == 0) {
+            CPG.STBCR10.BYTE &= ~0x0C;
+            reg_read_8 = CPG.STBCR10.BYTE; /* dummy read */
+        } else  {
+            CPG.STBCR10.BYTE &= ~0x03u;
+            reg_read_8 = CPG.STBCR10.BYTE; /* dummy read */
+        }
+        (void)reg_read_8;
+
+        if (p_ch->stb.stb_pon_init == false) {
+            /* case a */
+            p_ch->stb.stb_pon_init = true;
+        } else {
+            /* case b */
+            if (sd_port == 0) {
+                while (1) {
+                    CPG.STBREQ1.BYTE &= ~0x04;
+                    reg_read_8 = CPG.STBREQ1.BYTE; /* dummy read */
+                    reg_read_8 = CPG.STBACK1.BYTE;
+                    if ((reg_read_8 & 0x04) == 0) {
+                        break;
+                    }
+                }
+            } else {
+                while (1) {
+                    CPG.STBREQ1.BYTE &= ~0x02;
+                    reg_read_8 = CPG.STBREQ1.BYTE; /* dummy read */
+                    reg_read_8 = CPG.STBACK1.BYTE;
+                    if ((reg_read_8 & 0x02) == 0) {
+                        break;
+                    }
+                }
+            }
+        }
+        /* --- SDHI, clear module standby end ---*/
+
+        core_util_critical_section_exit();
+
+#ifdef SD_CFG_HWINT
+        if (ret == SD_OK) {
+            /* ---- Register SDHI interrupt handler ---- */
+            (void)IRQ_SetHandler(p_ch->intc.int_id, p_ch->intc.p_func);
+            /* ---- Set priority of SDHI interrupt handler to INT_LEVEL_SDHI ---- */
+            GIC_SetConfiguration(p_ch->intc.int_id, 1);
+            (void)IRQ_SetPriority(p_ch->intc.int_id, p_ch->intc.int_priority);
+            /* ---- Validate SDHI interrupt ---- */
+            (void)IRQ_Enable(p_ch->intc.int_id);
+
+            if (p_ch->semaphore.sem_sync == NULL) {
+                p_ch->semaphore.sem_sync = osSemaphoreNew(0xffff, 0, osSemaphore(sdint_sem_sync));
+            }
+            if (p_ch->semaphore.sem_sync == NULL) {
+                ret = SD_ERR;
+            }
+            if (p_ch->semaphore.sem_dma == NULL) {
+                p_ch->semaphore.sem_dma = osSemaphoreNew(0xffff, 0, osSemaphore(sdint_sem_dma));
+            }
+            if (p_ch->semaphore.sem_dma == NULL) {
+                ret = SD_ERR;
+            }
+            if (ret == SD_ERR) {
+                if (p_ch->semaphore.sem_sync != NULL) {
+                    osSemaphoreDelete(p_ch->semaphore.sem_sync);
+                    p_ch->semaphore.sem_sync = NULL;
+                }
+                if (p_ch->semaphore.sem_dma != NULL) {
+                    osSemaphoreDelete(p_ch->semaphore.sem_dma);
+                    p_ch->semaphore.sem_dma = NULL;
+                }
+            }
+        }
+#endif /* #ifdef SD_CFG_HWINT */
+    } else { /* if (p_ch != NULL) */
+        ret = SD_ERR;
+    }
+    return ret;
+#else
+    int32_t               ret;
+    st_sdhi_info_dev_ch_t *p_ch;
+    uint32_t              was_masked;
+    e_stb_err_t           e_stb_err;
+    int_t                 gpio_handle;
+    int_t                 gpio_err;
+#ifdef SD_CFG_HWINT
+    e_r_drv_intc_err_t    e_intc_err;
+    bool_t                chk;
+#endif /* #ifdef SD_CFG_HWINT */
+    int32_t               sc_port;
+
+    ret  = SD_OK;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+        was_masked = __disable_irq();
+
+        /* --- SDHI, clear module standby start ---*/
+        /* [Canceling Module Standby Function] */
+        /* a. Release from the module standby state after the activation of the
+              module by a power-on reset while the MSTP bit is set to 1
+           1. Clear the MSTP bit to 0.
+           2. After that, dummy-read the same register. */
+
+        /* b. Release from the module standby state after a transition to standby
+              following activation of the module
+           1. Clear the MSTP bit to 0, then dummy-read the same register.   */
+        e_stb_err = R_STB_StartModule(p_ch->stb.stb_ch);
+        if (STB_SUCCESS == e_stb_err)
+        {
+            if (false == p_ch->stb.stb_pon_init)
+            {
+                /* case a */
+                p_ch->stb.stb_pon_init = true;
+            }
+            else
+            {
+                /* case b */
+                /* No timer monitering. */
+                e_stb_err = STB_AGAIN;
+                while (STB_AGAIN == e_stb_err)
+                {
+                    /* 2. Clear the corresponding bit in the STBREQ register to 0
+                          to cancel the request to stop the module.
+                       3. Confirm that the corresponding bit in the STBACK register
+                          has been cleared to 0, indicating the completion of release
+                          from standby. */
+                    e_stb_err = R_STB_RequestModuleStart(p_ch->stb.stb_ch);
+                }
+            }
+        }
+        if (STB_SUCCESS != e_stb_err)
+        {
+            ret = SD_ERR;
+        }
+
+        /* --- SDHI, clear module standby end ---*/
+
+        /* --- SDx_CD, SDx_WP(x = 0(ch0) or 1(ch1)) start --- */
+        if (SD_OK == ret)
+        {
+            if (false == p_ch->gpio.gpio_init)
+            {
+                /* --- Open GPIO --- */
+                gpio_handle = direct_open("gpio", 0);
+                if (gpio_handle < 0)
+                {
+                    ret = SD_ERR;
+                }
+                else
+                {
+                    /* --- Control GPIO --- */
+                    ret = sddev_get_sc_table_config_ch(sd_port, &sc_port);
+                    if (SD_OK == ret)
+                    {
+                        gpio_err = direct_control(gpio_handle,
+
+                                                /* Cast to an appropriate type */
+                                                (uint32_t)CTL_GPIO_INIT_BY_TABLE,
+
+                                                /* Cast to an appropriate type */
+                                                (st_r_drv_sdhi_sc_config_t *)&SDHI_SC_TABLE[sc_port].pin);
+                        if (gpio_err < 0)
+                        {
+                            ret = SD_ERR;
+                        }
+                        else
+                        {
+                            p_ch->gpio.gpio_init = true;
+                        }
+                    }
+
+                    /* --- Close GPIO --- */
+                    (void)direct_close(gpio_handle);
+                }
+            } /* if (false == p_ch->gpio.gpio_init) */
+        }
+
+        /* --- SDx_CD, SDx_WP(x = 0(ch0) or 1(ch1)) end --- */
+
+        if (SD_OK == ret)
+        {
+            ret = sddev_init_voltage(sd_port);  /* Initialize voltage 3.3V */
+        }
+
+        if (0uL == was_masked)
+        {
+            __enable_irq();
+        }
+
+#ifdef SD_CFG_HWINT
+        if (SD_OK == ret)
+        {
+            /* ---- Register SDHI interrupt handler start ---- */
+            e_intc_err = R_INTC_RegistIntFunc(p_ch->intc.int_id, p_ch->intc.p_func);
+            if (INTC_SUCCESS != e_intc_err)
+            {
+                /* Invalid id */
+                ret = SD_ERR;
+            }
+            else
+            {
+                /* ---- Set priority of SDHI interrupt handler to INT_PRV_LEVEL_SDHI ---- */
+                e_intc_err = R_INTC_SetPriority(p_ch->intc.int_id, p_ch->intc.int_priority);
+                if (INTC_SUCCESS != e_intc_err)
+                {
+                    /* Invalid id or invalid priority */
+                    ret = SD_ERR;
+                }
+                else
+                {
+                    /* ---- Validate SDHI interrupt ---- */
+                    e_intc_err = R_INTC_Enable(p_ch->intc.int_id);
+                    if (INTC_SUCCESS != e_intc_err)
+                    {
+                        /* Invalid id */
+                        ret = SD_ERR;
+                    }
+                }
+            }
+
+            /* ---- Register SDHI interrupt handler end ---- */
+
+            if (SD_ERR == ret)
+            {
+                /* --- Invalidate SDHI interrupt --- */
+                e_intc_err = R_INTC_Disable(p_ch->intc.int_id);
+                if (INTC_SUCCESS != e_intc_err)
+                {
+                    /* DO NOTHING */
+                    ;
+                }
+
+                /* --- Unregister SDHI interrupt handler --- *//* Cast to an appropriate type */
+                e_intc_err = R_INTC_RegistIntFunc(p_ch->intc.int_id, NULL);
+                if (INTC_SUCCESS != e_intc_err)
+                {
+                    /* DO NOTHING */
+                    ;
+                }
+            }
+        }
+
+        if (SD_OK == ret)
+        {
+            /* --- Create semaphore start --- */
+            if (0uL == p_ch->semaphore.sem_sync)
+            {
+                chk = R_OS_SemaphoreCreate(&p_ch->semaphore.sem_sync, 1uL);
+                if (true == chk)
+                {
+                    chk = R_OS_SemaphoreWait(&p_ch->semaphore.sem_sync, 0uL);
+                }
+                if (false == chk)
+                {
+                    ret = SD_ERR;
+                }
+            }
+            if (0uL == p_ch->semaphore.sem_dma)
+            {
+                chk = R_OS_SemaphoreCreate(&p_ch->semaphore.sem_dma, 1uL);
+                if (true == chk)
+                {
+                    chk = R_OS_SemaphoreWait(&p_ch->semaphore.sem_dma, 0uL);
+                }
+                if (false == chk)
+                {
+                    ret = SD_ERR;
+                }
+            }
+
+            /* --- Create semaphore end --- */
+
+            if (SD_ERR == ret)
+            {
+                /* --- Delete semaphore --- */
+                R_OS_SemaphoreDelete(&p_ch->semaphore.sem_sync);      /* p_ch->semaphore.sem_sync = 0 */
+                R_OS_SemaphoreDelete(&p_ch->semaphore.sem_dma);       /* p_ch->semaphore.sem_dma  = 0 */
+            }
+        }
+#endif /* #ifdef SD_CFG_HWINT */
+
+        if (SD_OK == ret)
+        {
+            /* ---- wait card detect ---- */
+            R_OS_TaskSleep(SDHI_PRV_CARDDET_TIME);
+        }
+    }
+    else /* if (NULL != p_ch) */
+    {
+        ret = SD_ERR;
+    }
+    return ret;
+#endif
+}
+/*******************************************************************************
+ End of function sddev_init
+ ******************************************************************************/
+
+#if(1) // mbed
+#else
+/******************************************************************************
+* Function Name: sddev_init_voltage
+* Description  : SDHI initialize voltage(sd_port = 0,1)
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+******************************************************************************/
+static int32_t sddev_init_voltage(int32_t sd_port)
+{
+    int32_t ret;
+    int_t   gpio_handle;
+    int_t   gpio_err;
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret = SD_OK;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+        /* --- Open GPIO --- */
+        gpio_handle = direct_open("gpio", 0);
+        if (gpio_handle < 0)
+        {
+            ret = SD_ERR;
+        }
+        else /* if (gpio_handle < 0) */
+        {
+            if(SDHI_PRV_CH_0 == sd_port)
+            {
+                if (false == p_ch->gpio.gpio_vol_init)
+                {
+                    /*--- Control GPIO (PD1 = High(3.3V)) ---*//* Cast to an appropriate type */
+                    gpio_err = direct_control(gpio_handle, (uint32_t)CTL_GPIO_INIT_BY_PIN_LIST,
+                                                &s_sd_init_ch0_voltage);
+                    if (gpio_err < 0)
+                    {
+                        ret = SD_ERR;
+                    }
+                    else
+                    {
+                        p_ch->gpio.gpio_vol_init = true;
+                    }
+                }
+                else
+                {
+                    /*--- Control GPIO (PD1 = High(3.3V)) ---*//* Cast to an appropriate type */
+                    gpio_err = direct_control(gpio_handle, (uint32_t)CTL_GPIO_PIN_WRITE, &s_sd_ch0_voltage_3_3);
+                    if (gpio_err < 0)
+                    {
+                        ret = SD_ERR;
+                    }
+                }
+                if (SD_OK == ret)
+                {
+                    /* GPIO.PPOC.BIT.POC2 = 1(3.3V) */
+                    RZA_IO_RegWrite_32((volatile uint32_t*)&GPIO.PPOC.LONG,
+                                        SDHI_PRV_PPOC_POC_3_3V,
+                                        GPIO_PPOC_POC2_SHIFT,
+                                        GPIO_PPOC_POC2);
+
+                    /* GPIO.PSDMMC0.BIT.SD0_CLK_TDSEL = 3(3.3V) */
+                    RZA_IO_RegWrite_32((volatile uint32_t*)&GPIO.PSDMMC0.LONG,
+                                        SDHI_PRV_CLK_TDSEL_3_3V,
+                                        GPIO_PSDMMC0_SD0_CLK_TDSEL_SHIFT,
+                                        GPIO_PSDMMC0_SD0_CLK_TDSEL);
+
+                    /*--- Control GPIO ---*/
+                    gpio_err = direct_control(gpio_handle, (uint32_t)CTL_GPIO_INIT_BY_TABLE,
+                                                &s_sd_gpio_current[sd_port]);
+                    if (gpio_err < 0)
+                    {
+                        ret = SD_ERR;
+                    }
+                }
+            }
+            else /* if(SDHI_PRV_CH_0 == sd_port) */
+            {
+                /* GPIO.PPOC.BIT.POC3 = 1(3.3V) */
+                RZA_IO_RegWrite_32((volatile uint32_t*)&GPIO.PPOC.LONG,
+                                    SDHI_PRV_PPOC_POC_3_3V,
+                                    GPIO_PPOC_POC3_SHIFT,
+                                    GPIO_PPOC_POC3);
+
+                /* GPIO.PSDMMC2.BIT.SD1_CLK_TDSEL = 3(3.3V) */
+                RZA_IO_RegWrite_32((volatile uint32_t*)&GPIO.PSDMMC2.LONG,
+                                    SDHI_PRV_CLK_TDSEL_3_3V,
+                                    GPIO_PSDMMC2_SD1_CLK_TDSEL_SHIFT,
+                                    GPIO_PSDMMC2_SD1_CLK_TDSEL);
+
+                /*--- Control GPIO ---*/
+                gpio_err = direct_control(gpio_handle, (uint32_t)CTL_GPIO_INIT_BY_TABLE, &s_sd_gpio_current[sd_port]);
+                if ( gpio_err < 0 )
+                {
+                    ret = SD_ERR;
+                }
+            } /* if(SDHI_PRV_CH_0 == sd_port) */
+
+            /* --- Close GPIO --- */
+            (void)direct_close(gpio_handle);
+
+        } /* if (gpio_handle < 0) */
+    }
+    else /* if (NULL != p_ch) */
+    {
+        ret = SD_ERR;
+    }
+
+    return ret;
+}
+/*******************************************************************************
+ End of function sddev_init_voltage
+ ******************************************************************************/
+#endif
+
+/******************************************************************************
+* Function Name: sddev_power_on
+* Description  : Power-on H/W to use SDHI
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_power_on(int32_t sd_port)
+{
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    /* ---Power On SD ---- */
+
+    /* ---- Wait for  SD Wake up ---- */
+#if(1) // mbed
+    wait_ms(SDHI_PRV_POWERON_TIME);
+#else
+    R_OS_TaskSleep(SDHI_PRV_POWERON_TIME);
+#endif
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sddev_power_on
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_power_off
+* Description  : Power-off H/W to use SDHI
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_power_off(int32_t sd_port)
+{
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sddev_power_off
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_read_data
+* Description  : read from SDHI buffer FIFO
+* Arguments    : int32_t sd_port   : channel no (0 or 1)
+*              : uint8_t *buff     : buffer addrees to store reading datas
+*              : uint32_t reg_addr : SDIP FIFO address
+*              : int32_t num       : counts to read(unit:byte)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_read_data(int32_t sd_port, uint8_t *buff, uint32_t reg_addr, int32_t num)
+{
+    int32_t  i;
+    int32_t  cnt;
+    uint64_t *p_reg;
+    uint64_t *p_l;
+    uint8_t  *p_c;
+    volatile uint64_t tmp;
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    /* Cast to an appropriate type */
+    p_reg = (uint64_t *)(reg_addr);
+
+    cnt = (num / 8);
+
+    /* Cast to an appropriate type */
+    if (0uL != ((uint32_t)buff & 0x7uL))
+    {
+        /* Cast to an appropriate type */
+        p_c = (uint8_t *)buff;
+        for (i = cnt; i > 0 ; i--)
+        {
+            tmp = *p_reg;
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp);
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp >> 8);
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp >> 16);
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp >> 24);
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp >> 32);
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp >> 40);
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp >> 48);
+
+            /* Cast to an appropriate type */
+            *p_c++ = (uint8_t)(tmp >> 56);
+        }
+
+        cnt = (num % 8);
+        if (0 != cnt)
+        {
+            tmp = *p_reg;
+            for (i = cnt; i > 0 ; i--)
+            {
+                /* Cast to an appropriate type */
+                *p_c++ = (uint8_t)(tmp);
+                tmp >>= 8;
+            }
+        }
+    }
+    else
+    {
+        /* Cast to an appropriate type */
+        p_l = (uint64_t *)buff;
+        for (i = cnt; i > 0 ; i--)
+        {
+            *p_l++ = *p_reg;
+        }
+
+        cnt = (num % 8);
+        if (0 != cnt)
+        {
+            /* Cast to an appropriate type */
+            p_c = (uint8_t *)p_l;
+            tmp = *p_reg;
+            for (i = cnt; i > 0 ; i--)
+            {
+                /* Cast to an appropriate type */
+                *p_c++ = (uint8_t)(tmp);
+                tmp >>= 8;
+            }
+        }
+    }
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sddev_read_data
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_write_data
+* Description  : write to SDHI buffer FIFO
+* Arguments    : int32_t sd_port   : channel no (0 or 1)
+*              : uint8_t *buff     : buffer addrees to store writting datas
+*              : uint32_t reg_addr : SDIP FIFO address
+*              : int32_t num       : counts to write(unit:byte)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_write_data(int32_t sd_port, uint8_t *buff, uint32_t reg_addr, int32_t num)
+{
+    int32_t  i;
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    /* Cast to an appropriate type */
+    uint64_t *p_reg = (uint64_t *)(reg_addr);
+
+    /* Cast to an appropriate type */
+    uint64_t *p_buff = (uint64_t *)buff;
+    uint64_t tmp;
+
+    /* dont care non 8byte alignment data */
+    num += 7;
+    num /= 8;
+
+    /* Cast to an appropriate type */
+    if (((uint32_t)buff & 0x7uL) != 0uL)
+    {
+        for (i = num; i > 0 ; i--)
+        {
+            /* Cast to an appropriate type */
+            tmp  = (uint64_t)(*buff++);
+
+            /* Cast to an appropriate type */
+            tmp |= ((uint64_t)(*buff++) << 8);
+
+            /* Cast to an appropriate type */
+            tmp |= ((uint64_t)(*buff++) << 16);
+
+            /* Cast to an appropriate type */
+            tmp |= ((uint64_t)(*buff++) << 24);
+
+            /* Cast to an appropriate type */
+            tmp |= ((uint64_t)(*buff++) << 32);
+
+            /* Cast to an appropriate type */
+            tmp |= ((uint64_t)(*buff++) << 40);
+
+            /* Cast to an appropriate type */
+            tmp |= ((uint64_t)(*buff++) << 48);
+
+            /* Cast to an appropriate type */
+            tmp |= ((uint64_t)(*buff++) << 56);
+            *p_reg = tmp;
+        }
+    }
+    else
+    {
+        for (i = num; i > 0 ; i--)
+        {
+            *p_reg = *p_buff++;
+        }
+    }
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sddev_write_data
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_get_clockdiv
+* Description  : Get clock div value.
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : int32_t clock   : request clock frequency
+*              :   SD_CLK_50MHZ
+*              :   SD_CLK_25MHZ
+*              :   SD_CLK_20MHZ
+*              :   SD_CLK_10MHZ
+*              :   SD_CLK_5MHZ
+*              :   SD_CLK_1MHZ
+*              :   SD_CLK_400KHZ
+* Return Value : clock div value
+*              :   SD_DIV_4   : 1/4   clock
+*              :   SD_DIV_8   : 1/8   clock
+*              :   SD_DIV_16  : 1/16  clock
+*              :   SD_DIV_32  : 1/32  clock
+*              :   SD_DIV_256 : 1/256 clock
+*              :   SD_DIV_512 : 1/512 clock
+******************************************************************************/
+uint32_t sddev_get_clockdiv(int32_t sd_port, int32_t clock)
+{
+    uint32_t div;
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    switch (clock)
+    {
+        case SD_CLK_50MHZ:
+            div = SD_DIV_4;        /* 132MHz/4 = 33MHz      */
+            break;
+        case SD_CLK_25MHZ:
+            div = SD_DIV_8;        /* 132MHz/8 = 16.5MHz    */
+            break;
+        case SD_CLK_20MHZ:
+            div = SD_DIV_8;        /* 132MHz/8 = 16.5MHz    */
+            break;
+        case SD_CLK_10MHZ:
+            div = SD_DIV_16;       /* 132MHz/16 = 8.3MHz    */
+            break;
+        case SD_CLK_5MHZ:
+            div = SD_DIV_32;       /* 132MHz/32 = 4.1MHz    */
+            break;
+        case SD_CLK_1MHZ:
+            div = SD_DIV_256;      /* 132MHz/256 = 515.6kHz */
+            break;
+        case SD_CLK_400KHZ:
+            div = SD_DIV_512;      /* 132MHz/512 = 257.8kHz */
+            break;
+        default:
+            div = SD_DIV_512;      /* 132MHz/512 = 257.8kHz */
+            break;
+    }
+
+    return div;
+}
+/*******************************************************************************
+ End of function sddev_get_clockdiv
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_set_port
+* Description  : setting ports to use SDHI
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : int32_t mode    : SD_PORT_PARALLEL : 4bit mode
+*                                : SD_PORT_SERIAL   : 1bit mode
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_set_port(int32_t sd_port, int32_t mode)
+{
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(mode);
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sddev_set_port
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_int_wait
+* Description  : Waitting for SDHI Interrupt
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : int32_t time    : time out value to wait interrupt
+* Return Value : get interrupt : SD_OK
+*              : time out      : SD_ERR
+******************************************************************************/
+int32_t sddev_int_wait(int32_t sd_port, int32_t time)
+{
+#if(1) // mbed
+    int32_t             ret;
+#ifdef SD_CFG_HWINT
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret  = SD_ERR;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    if (p_ch != NULL) {
+        if (osSemaphoreAcquire(p_ch->semaphore.sem_sync, time) == osOK) {
+            ret = SD_OK;
+        }
+    }
+#else /* #ifdef SD_CFG_HWINT */
+    uint32_t waittime = (uint32_t)time;
+
+    /* interrupt generated? */
+    ret = sd_check_int(sd_port);
+    while ((ret == SD_ERR) && (waittime > 0uL)) {
+        wait_ms(SDHI_PRV_1MSEC);
+        waittime--;
+
+        /* interrupt generated? */
+        ret = sd_check_int(sd_port);
+    }
+
+#endif /* #ifdef SD_CFG_HWINT */
+
+    return ret;
+#else
+    int32_t  ret;
+    uint32_t waittime;
+
+#ifdef SD_CFG_HWINT
+    bool_t   chk;
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret  = SD_ERR;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+        /* Cast to an appropriate type */
+        waittime = (uint32_t)time;
+        chk = false;
+
+        while ((false == chk) && (waittime > SDHI_PRV_MAX_WAITTIME))
+        {
+            chk = R_OS_SemaphoreWait(&p_ch->semaphore.sem_sync, SDHI_PRV_MAX_WAITTIME);
+            waittime -= SDHI_PRV_MAX_WAITTIME;
+        }
+        if (false == chk)
+        {
+            chk = R_OS_SemaphoreWait(&p_ch->semaphore.sem_sync, waittime);
+        }
+        if (true == chk)
+        {
+            ret = SD_OK;
+        }
+    }
+
+#else /* #ifdef SD_CFG_HWINT */
+    waittime = (uint32_t)time;
+
+    /* interrupt generated? */
+    ret = sd_check_int(sd_port);
+    while ((SD_ERR == ret) && (waittime > 0uL))
+    {
+        R_OS_TaskSleep(SDHI_PRV_1MSEC);
+        waittime--;
+
+        /* interrupt generated? */
+        ret = sd_check_int(sd_port);
+    }
+
+#endif /* #ifdef SD_CFG_HWINT */
+
+    return ret;
+#endif
+}
+/*******************************************************************************
+ End of function sddev_int_wait
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_init_dma
+* Description  : Initialize DMAC to transfer data from SDHI FIFO
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : uint32_t buff   : buffer addrees to transfer datas
+*              : int32_t dir     : direction to transfer
+*              :                 :   0 : FIFO -> buffer
+*              :                 :   1 : buffer -> FIFO
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_init_dma(int32_t sd_port, uint32_t buff, int32_t dir)
+{
+#ifdef    SD_CFG_TRNS_DMA
+    int32_t ret = SD_ERR;
+
+    ret = sd_DMAC_PeriReqInit(sd_port, buff, dir);
+    if (SD_OK == ret)
+    {
+        ret = sd_DMAC_Open(sd_port, dir);
+    }
+    return ret;
+
+#else
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port); 
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(buff); 
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(dir); 
+
+    return SD_OK;
+
+#endif
+}
+/*******************************************************************************
+ End of function sddev_init_dma
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_wait_dma_end
+* Description  : Wait to complete DMAC transfer
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : int32_t cnt     : counts to transfer(unit:byte)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_wait_dma_end(int32_t sd_port, int32_t cnt)
+{
+#ifdef SD_CFG_TRNS_DMA
+#if(1) // mbed
+    int32_t             ret;
+    uint32_t            waittime;
+
+#ifdef SD_CFG_HWINT
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret  = SD_ERR;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+    
+    if (p_ch != NULL)
+    {
+        /* Caluculate timeout time (as 512kByte/sec)    */
+        waittime = ((((uint32_t)cnt / SDHI_PRV_TO_SPEED) / SDHI_PRV_1024BYTE) * SDHI_PRV_1000MSEC);
+        if (waittime < SDHI_PRV_1000MSEC)
+        {
+            waittime = SDHI_PRV_1000MSEC;
+        }
+
+        if (osSemaphoreAcquire(p_ch->semaphore.sem_dma, waittime) == osOK) {
+            ret = SD_OK;
+        }
+    }
+
+#else /* #ifdef SD_CFG_HWINT */
+    /* Caluculate timeout time (as 512kByte/sec)    */
+    waittime = ((((uint32_t)cnt / SDHI_PRV_TO_SPEED) / SDHI_PRV_1024BYTE) * SDHI_PRV_1000MSEC);
+    if (waittime < SDHI_PRV_1000MSEC)
+    {
+        waittime = SDHI_PRV_1000MSEC;
+    }
+
+    /* interrupt generated? */
+    ret = sd_check_int_dm(sd_port);
+    while ((ret == SD_ERR) && (waittime > 0uL))
+    {
+        wait_ms(SDHI_PRV_1MSEC);
+        waittime--;
+
+        /* interrupt generated? */
+        ret = sd_check_int_dm(sd_port);
+    }
+
+#endif /* #ifdef SD_CFG_HWINT */
+
+    return ret;
+
+#else
+    int32_t  ret;
+    uint32_t waittime;
+
+#ifdef SD_CFG_HWINT
+    bool_t   chk;
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret  = SD_ERR;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+        /* Caluculate timeout time (as 512kByte/sec)    */
+        waittime = ((((uint32_t)cnt / SDHI_PRV_TO_SPEED) / SDHI_PRV_1024BYTE) * SDHI_PRV_1000MSEC);
+        if (waittime < SDHI_PRV_1000MSEC)
+        {
+            waittime = SDHI_PRV_1000MSEC;
+        }
+        chk = false;
+
+        while ((false == chk) && (waittime > SDHI_PRV_MAX_WAITTIME))
+        {
+            chk = R_OS_SemaphoreWait(&p_ch->semaphore.sem_dma, SDHI_PRV_MAX_WAITTIME);
+            waittime -= SDHI_PRV_MAX_WAITTIME;
+        }
+        if (false == chk)
+        {
+            chk = R_OS_SemaphoreWait(&p_ch->semaphore.sem_dma, waittime);
+        }
+        if (true == chk)
+        {
+            ret = SD_OK;
+        }
+    }
+
+#else /* #ifdef SD_CFG_HWINT */
+    /* Caluculate timeout time (as 512kByte/sec)    */
+    waittime = ((((uint32_t)cnt / SDHI_PRV_TO_SPEED) / SDHI_PRV_1024BYTE) * SDHI_PRV_1000MSEC);
+    if (waittime < SDHI_PRV_1000MSEC)
+    {
+        waittime = SDHI_PRV_1000MSEC;
+    }
+
+    /* interrupt generated? */
+    ret = sd_check_int_dm(sd_port);
+    while ((SD_ERR == ret) && (waittime > 0uL))
+    {
+        R_OS_TaskSleep(SDHI_PRV_1MSEC);
+        waittime--;
+
+        /* interrupt generated? */
+        ret = sd_check_int_dm(sd_port);
+    }
+
+#endif /* #ifdef SD_CFG_HWINT */
+
+    return ret;
+
+#endif
+#else /* #ifdef SD_CFG_TRNS_DMA */
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port); 
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(cnt); 
+
+    return SD_OK;
+
+#endif /* #ifdef SD_CFG_TRNS_DMA */
+}
+/*******************************************************************************
+ End of function sddev_wait_dma_end
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_disable_dma
+* Description  : Disable DMAC transfer
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_disable_dma(int32_t sd_port)
+{
+#ifdef SD_CFG_TRNS_DMA
+    int32_t ret;
+
+    ret = sd_DMAC_Close(sd_port);
+
+    return ret;
+
+#else
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port); 
+
+    return SD_OK;
+
+#endif
+}
+/*******************************************************************************
+ End of function sddev_disable_dma
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_reset_dma
+* Description  : Reset of the SDHI module built-in DMAC.
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_reset_dma(int32_t sd_port)
+{
+    int32_t ret;
+
+    ret = sd_DMAC_Reset(sd_port);
+    if (SD_OK == ret)
+    {
+        ret = sd_DMAC_Released(sd_port);
+    }
+    return ret;
+}
+/*******************************************************************************
+ End of function sddev_reset_dma
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_finalize_dma
+* Description  : Finalize of the SDHI module built-in DMAC.
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_finalize_dma(int32_t sd_port)
+{
+    int32_t ret;
+
+    ret = sd_DMAC_Reset(sd_port);
+
+    return ret;
+}
+/*******************************************************************************
+ End of function sddev_finalize_dma
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_loc_cpu
+* Description  : lock cpu to disable interrupt
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_loc_cpu(int32_t sd_port)
+{
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    /* R_INTC_GetMaskLevel(&g_sdhi_priority_backup); */
+    /* R_INTC_SetMaskLevel(0); */
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sddev_loc_cpu
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_unl_cpu
+* Description  : unlock cpu to enable interrupt
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_unl_cpu(int32_t sd_port)
+{
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    /* R_INTC_SetMaskLevel(g_sdhi_priority_backup); */
+
+    return SD_OK;
+}
+/*******************************************************************************
+ End of function sddev_unl_cpu
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_finalize
+* Description  : finalize SDHI
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_finalize(int32_t sd_port)
+{
+#if(1) // mbed
+    int32_t               ret;
+    st_sdhi_info_dev_ch_t *p_ch;
+    volatile uint8_t      reg_read_8;
+
+    ret  = SD_OK;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    if (p_ch != NULL) {
+#if(1)
+        core_util_critical_section_enter();
+        if (sd_port == 0) {
+            while (1) {
+                CPG.STBREQ1.BYTE |= 0x04;
+                reg_read_8 = CPG.STBREQ1.BYTE; /* dummy read */
+                reg_read_8 = CPG.STBACK1.BYTE;
+                if ((reg_read_8 & 0x04) != 0) {
+                    break;
+                }
+            }
+            CPG.STBCR10.BYTE |= 0x0C;
+            reg_read_8 = CPG.STBCR10.BYTE; /* dummy read */
+        } else {
+            while (1) {
+                CPG.STBREQ1.BYTE |= 0x02;
+                reg_read_8 = CPG.STBREQ1.BYTE; /* dummy read */
+                reg_read_8 = CPG.STBACK1.BYTE;
+                if ((reg_read_8 & 0x02) != 0) {
+                    break;
+                }
+            }
+            CPG.STBCR10.BYTE |= 0x03u;
+            reg_read_8 = CPG.STBCR10.BYTE; /* dummy read */
+        }
+        core_util_critical_section_exit();
+#endif
+
+#ifdef SD_CFG_HWINT
+        /* --- Invalidate SDHI interrupt --- */
+        (void)IRQ_Disable(p_ch->intc.int_id);
+
+        /* --- Unregister SDHI interrupt handler --- */
+        (void)IRQ_SetHandler(p_ch->intc.int_id, NULL);
+
+        /* --- Delete semaphore --- */
+        if (p_ch->semaphore.sem_sync != NULL) {
+            osSemaphoreDelete(p_ch->semaphore.sem_sync);
+            p_ch->semaphore.sem_sync = NULL;
+        }
+        if (p_ch->semaphore.sem_dma != NULL) {
+            osSemaphoreDelete(p_ch->semaphore.sem_dma);
+            p_ch->semaphore.sem_dma = NULL;
+        }
+#endif
+    }
+    else /* if (p_ch != NULL) */
+    {
+        ret = SD_ERR;
+    }
+    return ret;
+#else
+    e_stb_err_t           e_stb_err;
+    int32_t               ret;
+    uint32_t              was_masked;
+    st_sdhi_info_dev_ch_t *p_ch;
+#ifdef SD_CFG_HWINT
+    e_r_drv_intc_err_t  e_intc_err;
+#endif /* #ifdef SD_CFG_HWINT */
+
+    ret  = SD_OK;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+        was_masked = __disable_irq();
+
+        /* No timer monitering. */
+        e_stb_err = STB_AGAIN;
+        while (STB_AGAIN == e_stb_err)
+        {
+            /* [Transition to Module Standby Function]
+               1. Set the corresponding bit in the STBREQ register to 1 to
+                  generate a request to stop the module.
+               2. Confirm that the module is ready to be stopped by the
+                  corresponding bit in the STBACK register being set to 1.  */
+            e_stb_err = R_STB_RequestModuleStop(p_ch->stb.stb_ch);
+        }
+        if (STB_SUCCESS == e_stb_err)
+        {
+            /* 3. Set the MSTP bit of the corresponding module to 1. */
+            e_stb_err = R_STB_StopModule(p_ch->stb.stb_ch);
+        }
+        else
+        {
+            ret = SD_ERR;
+        }
+
+        if (0uL == was_masked)
+        {
+            /* enable all irq */
+            __enable_irq();
+        }
+        
+#ifdef SD_CFG_HWINT
+        /* --- Invalidate SDHI interrupt --- */
+        e_intc_err = R_INTC_Disable(p_ch->intc.int_id);
+        if (INTC_SUCCESS != e_intc_err)
+        {
+            /* invalid id */
+            ret = SD_ERR;
+        }
+
+        /* --- Unregister SDHI interrupt handler --- *//* Cast to an appropriate type */
+        e_intc_err = R_INTC_RegistIntFunc(p_ch->intc.int_id, NULL);
+        if (INTC_SUCCESS != e_intc_err)
+        {
+            /* invalid id */
+            ret = SD_ERR;
+        }
+
+        /* --- Delete semaphore --- */
+        R_OS_SemaphoreDelete(&p_ch->semaphore.sem_sync);      /* p_ch->semaphore.sem_sync = 0 */
+        R_OS_SemaphoreDelete(&p_ch->semaphore.sem_dma);       /* p_ch->semaphore.sem_dma  = 0 */
+#endif
+    }
+    else /* if (NULL != p_ch) */
+    {
+        ret = SD_ERR;
+    }
+    return ret;
+#endif
+}
+/*******************************************************************************
+ End of function sddev_finalize
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_sd_int_handler_0
+* Description  : Setting Interrupt function for SDHI(INTC_ID_SDMMC_SDHI0_0)
+* Arguments    : uint32_t int_sense : Interrupt mode
+* Return Value : none
+******************************************************************************/
+#if(1) // mbed
+static void sddev_sd_int_handler_0(void)
+#else
+static void sddev_sd_int_handler_0(uint32_t int_sense)
+#endif
+{
+#if(1) // mbed
+#else
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(int_sense);
+#endif
+
+    sd_int_handler(0);
+    sd_int_dm_handler(0);
+}
+/*******************************************************************************
+ End of function sddev_sd_int_handler_0
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_sd_int_handler_1
+* Description  : Setting Interrupt function for SDHI(INTC_ID_SDMMC_SDHI1_0)
+* Arguments    : uint32_t int_sense : Interrupt mode
+* Return Value : none
+******************************************************************************/
+#if(1) // mbed
+static void sddev_sd_int_handler_1(void)
+#else
+static void sddev_sd_int_handler_1(uint32_t int_sense)
+#endif
+{
+#if(1) // mbed
+#else
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(int_sense);
+#endif
+
+    sd_int_handler(1);
+    sd_int_dm_handler(1);
+}
+/*******************************************************************************
+ End of function sddev_sd_int_handler_1
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_cd_layout
+* Description  : CD Terminal Support Confirmation
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : Support     : SD_OK
+*              : Not Support : SD_ERR
+******************************************************************************/
+int32_t sddev_cd_layout(int32_t sd_port)
+{
+    int32_t ret;
+    int32_t sc_port;
+    
+    ret = sddev_get_sc_table_config_ch(sd_port, &sc_port);
+    if (SD_OK == ret)
+    {
+        if (SD_CD_ENABLED != SDHI_SC_TABLE[sc_port].config.cd)
+        {
+            ret = SD_ERR;
+        }
+    }
+    return ret;
+}
+/*******************************************************************************
+ End of function sddev_cd_layout
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_wp_layout
+* Description  : WP Terminal Support Confirmation
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : Support     : SD_OK
+*              : Not Support : SD_ERR
+******************************************************************************/
+int32_t sddev_wp_layout(int32_t sd_port)
+{
+    int32_t ret;
+    int32_t sc_port;
+
+    ret = sddev_get_sc_table_config_ch(sd_port, &sc_port);
+    if (SD_OK == ret)
+    {
+        if (SD_WP_ENABLED != SDHI_SC_TABLE[sc_port].config.wp)
+        {
+            ret = SD_ERR;
+        }
+    }
+    return ret;
+}
+/*******************************************************************************
+ End of function sddev_wp_layout
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_get_sc_table_config_ch
+* Description  : Get the channel number of the table generated by the smart
+*              : configurator.
+* Arguments    : int32_t sd_port    : channel no (0 or 1)
+*              : int32_t *p_sc_port : pointer to sc channel no
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t sddev_get_sc_table_config_ch(int32_t sd_port, int32_t *p_sc_port)
+{
+    int32_t ret;
+    int32_t ch_num;
+    int32_t cnt;
+
+    ret = SD_ERR;
+
+    /* Cast to an appropriate type */
+    if (NULL != p_sc_port)
+    {
+        ch_num = (sizeof(SDHI_SC_TABLE))/sizeof(st_r_drv_sdhi_sc_config_t);
+
+        for (cnt = 0; cnt < ch_num; cnt++)
+        {
+            if (SDHI_SC_TABLE[cnt].channel == sd_port)
+            {
+                ret = SD_OK;
+                *p_sc_port = cnt;
+                break;
+            }
+        }
+    }
+    return ret;
+}
+/*******************************************************************************
+ End of function sddev_get_sc_table_config_ch
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: sddev_get_dev_ch_instance
+* Description  : Get SDHI driver target CPU interface information object
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+* Return Value : success : pointer to SDHI driver target CPU interface information
+*              : fail    : NULL
+******************************************************************************/
+st_sdhi_info_dev_ch_t *sddev_get_dev_ch_instance(int32_t sd_port)
+{
+    st_sdhi_info_dev_ch_t *p_info;
+
+    if ((sd_port >= SDHI_PRV_CH_0) && (sd_port < SDHI_PRV_CH_NUM))
+    {
+        p_info = &s_sdhi_dev_ch[sd_port];
+    }
+    else
+    {
+        /* Cast to an appropriate type */
+        p_info = NULL;
+
+        /* NON_NOTICE_ASSERT: channel range over */
+    }
+    return p_info;
+}
+/*******************************************************************************
+ End of function sddev_get_dev_ch_instance
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: SD_status_callback_function
+* Description  : Callback interrupt function for SDHI protocol status control
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : int32_t cd      : no used
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t SD_status_callback_function(int32_t sd_port, int32_t cd)
+{
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(cd);
+
+#ifdef SD_CFG_HWINT
+    int32_t               ret;
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret  = SD_ERR;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+#if(1) // mbed
+        (void)osSemaphoreRelease(p_ch->semaphore.sem_sync);
+#else
+        R_OS_SemaphoreRelease(&p_ch->semaphore.sem_sync);
+#endif
+        ret = SD_OK;
+    }
+    return ret;
+
+#else /* #ifdef SD_CFG_HWINT */
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    return SD_OK;
+
+#endif /* #ifdef SD_CFG_HWINT */
+}
+/*******************************************************************************
+ End of function SD_status_callback_function
+ ******************************************************************************/
+
+/******************************************************************************
+* Function Name: SD_dma_end_callback_function
+* Description  : Callback interrupt function for complete DMA transfer control
+* Arguments    : int32_t sd_port : channel no (0 or 1)
+*              : int32_t cd      : no used
+* Return Value : success : SD_OK
+*              : fail    : SD_ERR
+******************************************************************************/
+int32_t SD_dma_end_callback_function(int32_t sd_port, int32_t cd)
+{
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(cd);
+
+#ifdef SD_CFG_HWINT
+    int32_t               ret;
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    ret  = SD_ERR;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+#if(1) // mbed
+        (void)osSemaphoreRelease(p_ch->semaphore.sem_dma);
+#else
+        R_OS_SemaphoreRelease(&p_ch->semaphore.sem_dma);
+#endif
+        ret = SD_OK;
+    }
+    return ret;
+
+#else /* #ifdef SD_CFG_HWINT */
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+    return SD_OK;
+
+#endif /* #ifdef SD_CFG_HWINT */
+}
+/*******************************************************************************
+ End of function SD_dma_end_callback_function
+ ******************************************************************************/
+
+/******************************************************************************
+ * Function Name: SD_confirm_semaphore
+ * Description  : Confirm semaphore status
+ * Arguments    : int32_t sd_port : channel no (0 or 1)
+ * Return Value : none
+ *****************************************************************************/
+void SD_confirm_semaphore(int32_t sd_port)
+{
+#ifdef SD_CFG_HWINT
+#if(1) // mbed
+    st_sdhi_info_dev_ch_t  *p_ch;
+
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    if (p_ch != NULL) {
+        while (osSemaphoreAcquire(p_ch->semaphore.sem_sync, 0) == osOK);
+    }
+#else
+    bool_t                chk;
+    st_sdhi_info_dev_ch_t *p_ch;
+
+    chk  = true;
+    p_ch = sddev_get_dev_ch_instance(sd_port);
+
+    /* Cast to an appropriate type */
+    if (NULL != p_ch)
+    {
+        while (true == chk)
+        {
+            chk = R_OS_SemaphoreWait(&p_ch->semaphore.sem_sync, 0uL);
+        }
+    }
+#endif
+
+#else /* #ifdef SD_CFG_HWINT */
+
+    /* Cast to an appropriate type */
+    UNUSED_PARAM(sd_port);
+
+#endif /* #ifdef SD_CFG_HWINT */
+}
+/*******************************************************************************
+ End of function SD_confirm_semaphore
+ ******************************************************************************/
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/SdUsbConnect.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,152 @@
+/* Copyright (c) 2017 dkato
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**************************************************************************//**
+* @file          SdUsbConnect.h
+* @brief         
+******************************************************************************/
+#ifndef SD_USB_CONNECT_H
+#define SD_USB_CONNECT_H
+
+#include "mbed.h"
+#include "FATFileSystem.h"
+#include "SDBlockDevice_GRBoard.h"
+#include "USBHostConf.h"
+#if USBHOST_MSD
+#include "USBHostMSD.h"
+#endif
+
+/** A class to communicate a StorageConnect
+ *
+ */
+class SdUsbConnect {
+public:
+
+    typedef enum {
+        STORAGE_NON = 0,           /*!< NON         */
+        STORAGE_SD,                /*!< SD          */
+        STORAGE_USB                /*!< USB         */
+    } storage_type_t;
+
+    SdUsbConnect(const char *name) : fs(name), storage_type(STORAGE_NON) {}
+
+    bool connected(storage_type_t type = STORAGE_NON) {
+        if (type == STORAGE_SD) {
+            return sd.connected();
+        }
+      #if USBHOST_MSD
+        if (type == STORAGE_USB) {
+            return usb.connected();
+        }
+      #endif
+        if (storage_type == STORAGE_SD) {
+            return sd.connected();
+        }
+      #if USBHOST_MSD
+        if (storage_type == STORAGE_USB) {
+            return usb.connected();
+        }
+      #endif
+
+        return false;
+    }
+
+    storage_type_t connect(storage_type_t type = STORAGE_NON) {
+        if ((storage_type == STORAGE_SD) && (!sd.connected())) {
+            fs.unmount();
+            storage_type = STORAGE_NON;
+        }
+      #if USBHOST_MSD
+        if ((storage_type == STORAGE_USB) && (!usb.connected())) {
+            fs.unmount();
+            storage_type = STORAGE_NON;
+        }
+      #endif
+        if ((type == STORAGE_SD) && (storage_type != STORAGE_SD)) {
+            if (sd.connect()) {
+                if (storage_type != STORAGE_NON) {
+                    fs.unmount();
+                }
+                fs.mount(&sd);
+                storage_type = STORAGE_SD;
+            }
+      #if USBHOST_MSD
+        } else if ((type == STORAGE_USB) && (storage_type != STORAGE_USB)) {
+            if (usb.connect()) {
+                if (storage_type != STORAGE_NON) {
+                    fs.unmount();
+                }
+                fs.mount(&usb);
+                storage_type = STORAGE_USB;
+            }
+      #endif
+        } else if (storage_type == STORAGE_NON) {
+            if (sd.connect()) {
+                fs.mount(&sd);
+                storage_type = STORAGE_SD;
+          #if USBHOST_MSD
+            } else if (usb.connect()) {
+                fs.mount(&usb);
+                storage_type = STORAGE_USB;
+          #endif
+            } else {
+                // do nothing
+            }
+        } else {
+            // do nothing
+        }
+
+        return storage_type;
+    }
+
+    storage_type_t wait_connect(storage_type_t type = STORAGE_NON) {
+        while (connect(type) == STORAGE_NON) {
+            ThisThread::sleep_for(100);
+        }
+        return storage_type;
+    }
+
+    bool format(storage_type_t type = STORAGE_NON, int allocation_unit = 0) {
+        if ((storage_type == STORAGE_SD) && (sd.connected())) {
+            fs.unmount();
+            fs.format(&sd, allocation_unit);
+            fs.mount(&sd);
+            return true;
+        }
+      #if USBHOST_MSD
+        if ((storage_type == STORAGE_USB) && (usb.connected())) {
+            fs.unmount();
+            fs.format(&usb, allocation_unit);
+            fs.mount(&usb);
+            return true;
+        }
+      #endif
+        return false;
+    }
+
+    FATFileSystem * get_fs() {
+        return &fs;
+    }
+
+private:
+    FATFileSystem fs;
+    SDBlockDevice_GRBoard sd;
+  #if USBHOST_MSD
+    USBHostMSD usb;
+  #endif
+    storage_type_t storage_type;
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/IUSBEnumerator.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,36 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IUSBENUMERATOR_H_
+#define IUSBENUMERATOR_H_
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+
+/*
+Generic interface to implement for "smart" USB enumeration
+*/
+
+class IUSBEnumerator
+{
+public:
+    virtual void setVidPid(uint16_t vid, uint16_t pid) = 0;
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) = 0; //Must return true if the interface should be parsed
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) = 0; //Must return true if the endpoint will be used
+};
+
+#endif /*IUSBENUMERATOR_H_*/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/inc/devdrv_intc.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1 @@
+#include "cmsis.h"

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/inc/devdrv_usb_host_api.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,329 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : devdrv_usb_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_API_H
+#define USB_HOST_API_H
+
+#include "r_typedefs.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_PORTNUM                            (2)
+
+#define USB_HOST_ELT_INTERRUPT_LEVEL                (9)
+
+#define USBHCLOCK_X1_48MHZ                          (0x0000u)       /* USB_X1_48MHz */
+#define USBHCLOCK_EXTAL_12MHZ                       (0x0004u)       /* EXTAL_12MHz  */
+
+#define USB_HOST_MAX_DEVICE                         (10)
+
+#define USB_HOST_ON                                 (1)
+#define USB_HOST_OFF                                (0)
+#define USB_HOST_YES                                (1)
+#define USB_HOST_NO                                 (0)
+
+#define USB_HOST_NON_SPEED                          (0)
+#define USB_HOST_LOW_SPEED                          (1)
+#define USB_HOST_FULL_SPEED                         (2)
+#define USB_HOST_HIGH_SPEED                         (3)
+
+/* DEVDRV_SUCCESS(0) & DEVDRV_ERROR(-1) is dev_drv.h */
+#define DEVDRV_USBH_STALL                           (-2)
+#define DEVDRV_USBH_TIMEOUT                         (-3)
+#define DEVDRV_USBH_NAK_TIMEOUT                     (-4)
+#define DEVDRV_USBH_DETACH_ERR                      (-5)
+#define DEVDRV_USBH_SETUP_ERR                       (-6)
+#define DEVDRV_USBH_CTRL_COM_ERR                    (-7)
+#define DEVDRV_USBH_COM_ERR                         (-8)
+#define DEVDRV_USBH_DEV_ADDR_ERR                    (-9)
+
+#define USB_HOST_ATTACH                             (1)
+#define USB_HOST_DETACH                             (0)
+
+#define USB_HOST_MAX_PIPE_NO                        (9u)
+#define USB_HOST_PIPE0                              (0)
+#define USB_HOST_PIPE1                              (1)
+#define USB_HOST_PIPE2                              (2)
+#define USB_HOST_PIPE3                              (3)
+#define USB_HOST_PIPE4                              (4)
+#define USB_HOST_PIPE5                              (5)
+#define USB_HOST_PIPE6                              (6)
+#define USB_HOST_PIPE7                              (7)
+#define USB_HOST_PIPE8                              (8)
+#define USB_HOST_PIPE9                              (9)
+
+#define USB_HOST_ISO                                (0xc000u)
+#define USB_HOST_INTERRUPT                          (0x8000u)
+#define USB_HOST_BULK                               (0x4000u)
+
+#define USB_HOST_PIPE_IDLE                          (0x00)
+#define USB_HOST_PIPE_WAIT                          (0x01)
+#define USB_HOST_PIPE_DONE                          (0x02)
+#define USB_HOST_PIPE_NORES                         (0x03)
+#define USB_HOST_PIPE_STALL                         (0x04)
+#define USB_HOST_PIPE_ERROR                         (0x05)
+
+#define USB_HOST_NONE                               (0x0000u)
+#define USB_HOST_BFREFIELD                          (0x0400u)
+#define USB_HOST_BFREON                             (0x0400u)
+#define USB_HOST_BFREOFF                            (0x0000u)
+#define USB_HOST_DBLBFIELD                          (0x0200u)
+#define USB_HOST_DBLBON                             (0x0200u)
+#define USB_HOST_DBLBOFF                            (0x0000u)
+#define USB_HOST_CNTMDFIELD                         (0x0100u)
+#define USB_HOST_CNTMDON                            (0x0100u)
+#define USB_HOST_CNTMDOFF                           (0x0000u)
+#define USB_HOST_SHTNAKON                           (0x0080u)
+#define USB_HOST_SHTNAKOFF                          (0x0000u)
+#define USB_HOST_DIRFIELD                           (0x0010u)
+#define USB_HOST_DIR_H_OUT                          (0x0010u)
+#define USB_HOST_DIR_H_IN                           (0x0000u)
+#define USB_HOST_EPNUMFIELD                         (0x000fu)
+
+#define USB_HOST_CUSE                               (0)
+#define USB_HOST_D0USE                              (1)
+#define USB_HOST_D0DMA                              (2)
+#define USB_HOST_D1USE                              (3)
+#define USB_HOST_D1DMA                              (4)
+
+#define USB_HOST_CFIFO_USE                          (0x0000)
+#define USB_HOST_D0FIFO_USE                         (0x1000)
+#define USB_HOST_D1FIFO_USE                         (0x2000)
+#define USB_HOST_D0FIFO_DMA                         (0x5000)
+#define USB_HOST_D1FIFO_DMA                         (0x6000)
+
+#define USB_HOST_BUF2FIFO                           (0)
+#define USB_HOST_FIFO2BUF                           (1)
+
+#define USB_HOST_DRV_DETACHED                       (0x0000)
+#define USB_HOST_DRV_ATTACHED                       (0x0001)
+#define USB_HOST_DRV_GET_DEVICE_DESC_64             (0x0002)
+#define USB_HOST_DRV_POWERED                        (0x0003)
+#define USB_HOST_DRV_DEFAULT                        (0x0004)
+#define USB_HOST_DRV_SET_ADDRESS                    (0x0005)
+#define USB_HOST_DRV_ADDRESSED                      (0x0006)
+#define USB_HOST_DRV_GET_DEVICE_DESC_18             (0x0007)
+#define USB_HOST_DRV_GET_CONGIG_DESC_9              (0x0008)
+#define USB_HOST_DRV_GET_CONGIG_DESC                (0x0009)
+#define USB_HOST_DRV_SET_CONFIG                     (0x000a)
+#define USB_HOST_DRV_CONFIGURED                     (0x000b)
+#define USB_HOST_DRV_SUSPEND                        (0x1000)
+#define USB_HOST_DRV_NORES                          (0x0100)
+#define USB_HOST_DRV_STALL                          (0x0200)
+
+#define USB_HOST_TESTMODE_FORCE                     (0x000du)
+#define USB_HOST_TESTMODE_TESTPACKET                (0x000cu)
+#define USB_HOST_TESTMODE_SE0_NAK                   (0x000bu)
+#define USB_HOST_TESTMODE_K                         (0x000au)
+#define USB_HOST_TESTMODE_J                         (0x0009u)
+#define USB_HOST_TESTMODE_NORMAL                    (0x0000u)
+
+#define USB_HOST_DT_DEVICE                          (0x01)
+#define USB_HOST_DT_CONFIGURATION                   (0x02)
+#define USB_HOST_DT_STRING                          (0x03)
+#define USB_HOST_DT_INTERFACE                       (0x04)
+#define USB_HOST_DT_ENDPOINT                        (0x05)
+#define USB_HOST_DT_DEVICE_QUALIFIER                (0x06)
+#define USB_HOST_DT_OTHER_SPEED_CONFIGURATION       (0x07)
+#define USB_HOST_DT_INTERFACE_POWER                 (0x08)
+
+#define USB_HOST_IF_CLS_NOT                         (0x00)
+#define USB_HOST_IF_CLS_AUDIO                       (0x01)
+#define USB_HOST_IF_CLS_CDC_CTRL                    (0x02)
+#define USB_HOST_IF_CLS_HID                         (0x03)
+#define USB_HOST_IF_CLS_PHYSICAL                    (0x05)
+#define USB_HOST_IF_CLS_IMAGE                       (0x06)
+#define USB_HOST_IF_CLS_PRINTER                     (0x07)
+#define USB_HOST_IF_CLS_MASS                        (0x08)
+#define USB_HOST_IF_CLS_HUB                         (0x09)
+#define USB_HOST_IF_CLS_CDC_DATA                    (0x0a)
+#define USB_HOST_IF_CLS_CRAD                        (0x0b)
+#define USB_HOST_IF_CLS_CONTENT                     (0x0d)
+#define USB_HOST_IF_CLS_VIDEO                       (0x0e)
+#define USB_HOST_IF_CLS_DIAG                        (0xdc)
+#define USB_HOST_IF_CLS_WIRELESS                    (0xe0)
+#define USB_HOST_IF_CLS_APL                         (0xfe)
+#define USB_HOST_IF_CLS_VENDOR                      (0xff)
+#define USB_HOST_IF_CLS_HELE                        (0xaa)
+
+#define USB_HOST_EP_DIR_MASK                        (0x80)
+#define USB_HOST_EP_OUT                             (0x00)
+#define USB_HOST_EP_IN                              (0x80)
+#define USB_HOST_EP_TYPE                            (0x03)
+#define USB_HOST_EP_CNTRL                           (0x00)
+#define USB_HOST_EP_ISO                             (0x01)
+#define USB_HOST_EP_BULK                            (0x02)
+#define USB_HOST_EP_INT                             (0x03)
+#define USB_HOST_EP_NUM_MASK                        (0x0f)
+
+#define USB_HOST_PIPE_IN                            (0)
+#define USB_HOST_PIPE_OUT                           (1)
+
+#define USB_END_POINT_ERROR                         (0xffff)
+
+#define USB_HOST_REQ_GET_STATUS                     (0x0000)
+#define USB_HOST_REQ_CLEAR_FEATURE                  (0x0100)
+#define USB_HOST_REQ_RESERVED2                      (0x0200)
+#define USB_HOST_REQ_SET_FEATURE                    (0x0300)
+#define USB_HOST_REQ_RESERVED4                      (0x0400)
+#define USB_HOST_REQ_SET_ADDRESS                    (0x0500)
+#define USB_HOST_REQ_GET_DESCRIPTOR                 (0x0600)
+#define USB_HOST_REQ_SET_DESCRIPTOR                 (0x0700)
+#define USB_HOST_REQ_GET_CONFIGURATION              (0x0800)
+#define USB_HOST_REQ_SET_CONFIGURATION              (0x0900)
+#define USB_HOST_REQ_GET_INTERFACE                  (0x0a00)
+#define USB_HOST_REQ_SET_INTERFACE                  (0x0b00)
+#define USB_HOST_REQ_SYNCH_FRAME                    (0x0c00)
+
+#define USB_HOST_REQTYPE_HOST_TO_DEVICE             (0x0000)
+#define USB_HOST_REQTYPE_DEVICE_TO_HOST             (0x0080)
+#define USB_HOST_REQTYPE_STANDARD                   (0x0020)
+#define USB_HOST_REQTYPE_CLASS                      (0x0040)
+#define USB_HOST_REQTYPE_VENDOR                     (0x0060)
+#define USB_HOST_REQTYPE_DEVICE                     (0x0000)
+#define USB_HOST_REQTYPE_INTERFACE                  (0x0001)
+#define USB_HOST_REQTYPE_ENDPOINT                   (0x0002)
+#define USB_HOST_REQTYPE_OTHER                      (0x0003)
+
+#define USB_HOST_DESCTYPE_DEVICE                    (0x0100)
+#define USB_HOST_DESCTYPE_CONFIGURATION             (0x0200)
+#define USB_HOST_DESCTYPE_STRING                    (0x0300)
+#define USB_HOST_DESCTYPE_INTERFACE                 (0x0400)
+#define USB_HOST_DESCTYPE_ENDPOINT                  (0x0500)
+#define USB_HOST_DESCTYPE_DEVICE_QUALIFIER          (0x0600)
+#define USB_HOST_DESCTYPE_OTHER_SPEED_CONFIGURATION (0x0700)
+#define USB_HOST_DESCTYPE_INTERFACE_POWER           (0x0800)
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+typedef struct
+{
+    uint16_t    pipe_number;
+    uint16_t    pipe_cfg;
+    uint16_t    pipe_buf;
+    uint16_t    pipe_max_pktsize;
+    uint16_t    pipe_cycle;
+    uint16_t    fifo_port;
+} USB_HOST_CFG_PIPETBL_t;
+
+typedef struct
+{
+    uint32_t    fifo;
+    uint32_t    buffer;
+    uint32_t    bytes;
+    uint32_t    dir;
+    uint32_t    size;
+} USB_HOST_DMA_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+uint16_t R_USB_api_host_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t R_USB_api_host_enumeration(uint16_t root, uint16_t devadr);
+int32_t R_USB_api_host_detach(uint16_t root);
+int32_t R_USB_api_host_data_in(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_data_in2(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf, uint32_t *bytes);
+int32_t R_USB_api_host_data_out(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_control_transfer(uint16_t root, uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t R_USB_api_host_set_endpoint(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t R_USB_api_host_clear_endpoint(uint16_t root, USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t R_USB_api_host_clear_endpoint_pipe(uint16_t root, uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t R_USB_api_host_SetEndpointTable(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+
+int32_t R_USB_api_host_GetDeviceDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_GetConfigDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_SetConfig(uint16_t root, uint16_t devadr, uint16_t confignum);
+int32_t R_USB_api_host_SetInterface(uint16_t root, uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t R_USB_api_host_ClearStall(uint16_t root, uint16_t devadr, uint16_t ep_dir);
+uint16_t R_USB_api_host_GetUsbDeviceState(uint16_t root);
+
+void    R_USB_api_host_elt_clocksel(uint16_t clockmode);
+void    R_USB_api_host_elt_4_4(uint16_t root);
+void    R_USB_api_host_elt_4_5(uint16_t root);
+void    R_USB_api_host_elt_4_6(uint16_t root);
+void    R_USB_api_host_elt_4_7(uint16_t root);
+void    R_USB_api_host_elt_4_8(uint16_t root);
+void    R_USB_api_host_elt_4_9(uint16_t root);
+void    R_USB_api_host_elt_get_desc(uint16_t root);
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host_api.h"
+#include "usb1_host_api.h"
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#ifdef USB0_HOST_API_H
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void     Userdef_USB_usb0_host_attach(void);
+void     Userdef_USB_usb0_host_detach(void);
+void     Userdef_USB_usb0_host_delay_1ms(void);
+void     Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void     Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void     Userdef_USB_usb0_host_delay_500ns(void);
+void     Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t Userdef_USB_usb0_host_stop_dma1(void);
+void     Userdef_USB_usb0_host_notice(const char * format);
+void     Userdef_USB_usb0_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#ifdef USB1_HOST_API_H
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void     Userdef_USB_usb1_host_attach(void);
+void     Userdef_USB_usb1_host_detach(void);
+void     Userdef_USB_usb1_host_delay_1ms(void);
+void     Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void     Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void     Userdef_USB_usb1_host_delay_500ns(void);
+void     Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t Userdef_USB_usb1_host_stop_dma1(void);
+void     Userdef_USB_usb1_host_notice(const char * format);
+void     Userdef_USB_usb1_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#endif /* USB_HOST_API_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/inc/usb_host.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_H
+#define USB_HOST_H
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_DEVICE_0               (0u)
+#define USB_HOST_DEVICE_1               (1u)
+#define USB_HOST_DEVICE_2               (2u)
+#define USB_HOST_DEVICE_3               (3u)
+#define USB_HOST_DEVICE_4               (4u)
+#define USB_HOST_DEVICE_5               (5u)
+#define USB_HOST_DEVICE_6               (6u)
+#define USB_HOST_DEVICE_7               (7u)
+#define USB_HOST_DEVICE_8               (8u)
+#define USB_HOST_DEVICE_9               (9u)
+#define USB_HOST_DEVICE_10              (10u)
+
+#define USB_HOST_ENDPOINT_DESC          (0x05)
+
+#define USB_HOST_BITUPLLE               (0x0002u)
+#define USB_HOST_BITUCKSEL              (0x0004u)
+#define USB_HOST_BITBWAIT               (0x003fu)
+
+#define USB_HOST_BUSWAIT_02             (0x0000u)
+#define USB_HOST_BUSWAIT_03             (0x0001u)
+#define USB_HOST_BUSWAIT_04             (0x0002u)
+#define USB_HOST_BUSWAIT_05             (0x0003u)
+#define USB_HOST_BUSWAIT_06             (0x0004u)
+#define USB_HOST_BUSWAIT_07             (0x0005u)
+#define USB_HOST_BUSWAIT_08             (0x0006u)
+#define USB_HOST_BUSWAIT_09             (0x0007u)
+#define USB_HOST_BUSWAIT_10             (0x0008u)
+#define USB_HOST_BUSWAIT_11             (0x0009u)
+#define USB_HOST_BUSWAIT_12             (0x000au)
+#define USB_HOST_BUSWAIT_13             (0x000bu)
+#define USB_HOST_BUSWAIT_14             (0x000cu)
+#define USB_HOST_BUSWAIT_15             (0x000du)
+#define USB_HOST_BUSWAIT_16             (0x000eu)
+#define USB_HOST_BUSWAIT_17             (0x000fu)
+
+#define USB_HOST_FS_JSTS                (0x0001u)
+#define USB_HOST_LS_JSTS                (0x0002u)
+
+#define USB_HOST_BITRST                 (0x0040u)
+#define USB_HOST_BITRESUME              (0x0020u)
+#define USB_HOST_BITUACT                (0x0010u)
+#define USB_HOST_HSPROC                 (0x0004u)
+#define USB_HOST_HSMODE                 (0x0003u)
+#define USB_HOST_FSMODE                 (0x0002u)
+#define USB_HOST_LSMODE                 (0x0001u)
+#define USB_HOST_UNDECID                (0x0000u)
+
+#define USB_HOST_BITRCNT                (0x8000u)
+#define USB_HOST_BITDREQE               (0x1000u)
+#define USB_HOST_BITMBW                 (0x0c00u)
+#define USB_HOST_BITMBW_8               (0x0000u)
+#define USB_HOST_BITMBW_16              (0x0400u)
+#define USB_HOST_BITMBW_32              (0x0800u)
+#define USB_HOST_BITBYTE_LITTLE         (0x0000u)
+#define USB_HOST_BITBYTE_BIG            (0x0100u)
+#define USB_HOST_BITISEL                (0x0020u)
+#define USB_HOST_BITCURPIPE             (0x000fu)
+
+#define USB_HOST_CFIFO_READ             (0x0000u)
+#define USB_HOST_CFIFO_WRITE            (0x0020u)
+
+#define USB_HOST_BITBVAL                (0x8000u)
+#define USB_HOST_BITBCLR                (0x4000u)
+#define USB_HOST_BITFRDY                (0x2000u)
+#define USB_HOST_BITDTLN                (0x0fffu)
+
+#define USB_HOST_BITBEMPE               (0x0400u)
+#define USB_HOST_BITNRDYE               (0x0200u)
+#define USB_HOST_BITBRDYE               (0x0100u)
+#define USB_HOST_BITBEMP                (0x0400u)
+#define USB_HOST_BITNRDY                (0x0200u)
+#define USB_HOST_BITBRDY                (0x0100u)
+
+#define USB_HOST_BITBCHGE               (0x4000u)
+#define USB_HOST_BITDTCHE               (0x1000u)
+#define USB_HOST_BITATTCHE              (0x0800u)
+#define USB_HOST_BITEOFERRE             (0x0040u)
+#define USB_HOST_BITBCHG                (0x4000u)
+#define USB_HOST_BITDTCH                (0x1000u)
+#define USB_HOST_BITATTCH               (0x0800u)
+#define USB_HOST_BITEOFERR              (0x0040u)
+
+#define USB_HOST_BITSIGNE               (0x0020u)
+#define USB_HOST_BITSACKE               (0x0010u)
+#define USB_HOST_BITSIGN                (0x0020u)
+#define USB_HOST_BITSACK                (0x0010u)
+
+#define USB_HOST_BITSUREQ               (0x4000u)
+#define USB_HOST_BITSQSET               (0x0080u)
+#define USB_HOST_PID_STALL2             (0x0003u)
+#define USB_HOST_PID_STALL              (0x0002u)
+#define USB_HOST_PID_BUF                (0x0001u)
+#define USB_HOST_PID_NAK                (0x0000u)
+
+#define USB_HOST_PIPExBUF               (64u)
+
+#define USB_HOST_D0FIFO                 (0)
+#define USB_HOST_D1FIFO                 (1)
+#define USB_HOST_DMA_READY              (0)
+#define USB_HOST_DMA_BUSY               (1)
+#define USB_HOST_DMA_BUSYEND            (2)
+
+#define USB_HOST_FIFO_USE               (0x7000)
+
+#define USB_HOST_FIFOERROR              (0xffff)
+#define USB_HOST_WRITEEND               (0)
+#define USB_HOST_WRITESHRT              (1)
+#define USB_HOST_WRITING                (2)
+#define USB_HOST_WRITEDMA               (3)
+#define USB_HOST_READEND                (0)
+#define USB_HOST_READSHRT               (1)
+#define USB_HOST_READING                (2)
+#define USB_HOST_READOVER               (3)
+#define USB_HOST_READZERO               (4)
+
+#define USB_HOST_CMD_IDLE               (0x0000)
+#define USB_HOST_CMD_DOING              (0x0001)
+#define USB_HOST_CMD_DONE               (0x0002)
+#define USB_HOST_CMD_NORES              (0x0003)
+#define USB_HOST_CMD_STALL              (0x0004)
+#define USB_HOST_CMD_FIELD              (0x000f)
+
+#if 0
+#define USB_HOST_CHG_CMDFIELD( r, v )   do { r &= ( ~USB_HOST_CMD_FIELD );  \
+                                         r |= v;                } while(0)
+#endif
+
+#define USB_HOST_MODE_WRITE             (0x0100)
+#define USB_HOST_MODE_READ              (0x0200)
+#define USB_HOST_MODE_NO_DATA           (0x0300)
+#define USB_HOST_MODE_FIELD             (0x0f00)
+
+#define USB_HOST_STAGE_SETUP            (0x0010)
+#define USB_HOST_STAGE_DATA             (0x0020)
+#define USB_HOST_STAGE_STATUS           (0x0030)
+#define USB_HOST_STAGE_FIELD            (0x00f0)
+
+#if 0
+#define USB_HOST_CHG_STAGEFIELD( r, v ) do { r &= ( ~USB_HOST_STAGE_FIELD );    \
+                                         r |= v;                } while(0)
+#endif
+
+#define USB_HOST_DEVADD_MASK            (0x7fc0)
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern uint16_t g_usb_host_elt_clockmode;
+
+#endif /* USB_HOST_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/inc/usb_host_version.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,35 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb_host_version.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_VERSION_H
+#define USB_HOST_VERSION_H
+
+#define USB_HOST_LOCAL_Rev      "VER080_140709"
+
+#endif
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/ohci_wrapp_RZ_A1.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1520 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <string.h>
+#include "cmsis.h"
+#include "cmsis_os.h"
+#include "ohci_wrapp_RZ_A1.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+#include "rza_io_regrw.h"
+#include "usb_host_setting.h"
+
+/* ------------------ HcControl Register --------------------- */
+#define OR_CONTROL_PLE                  (0x00000004)
+#define OR_CONTROL_IE                   (0x00000008)
+#define OR_CONTROL_CLE                  (0x00000010)
+#define OR_CONTROL_BLE                  (0x00000020)
+/* ----------------- HcCommandStatus Register ----------------- */
+#define OR_CMD_STATUS_HCR               (0x00000001)
+#define OR_CMD_STATUS_CLF               (0x00000002)
+#define OR_CMD_STATUS_BLF               (0x00000004)
+#define OR_CMD_STATUS_OCR               (0x00000008)
+/* --------------- HcInterruptStatus Register ----------------- */
+#define OR_INTR_STATUS_WDH              (0x00000002)
+#define OR_INTR_STATUS_RHSC             (0x00000040)
+/* --------------- HcInterruptEnable Register ----------------- */
+#define OR_INTR_ENABLE_WDH              (0x00000002)
+#define OR_INTR_ENABLE_RHSC             (0x00000040)
+/* -------------- HcRhPortStatus[1:NDP] Register -------------- */
+#define OR_RH_PORT_CSC                  (0x00010000)
+#define OR_RH_PORT_LSDA                 (0x00000200)
+#define OR_RH_PORT_PRS                  (0x00000010)
+#define OR_RH_PORT_POCI                 (0x00000008)
+#define OR_RH_PORT_CCS                  (0x00000001)
+
+#define ED_FORMAT                       (0x00008000)   /* Format */
+#define ED_SKIP                         (0x00004000)   /* Skip this ep in queue */
+#define ED_TOGLE_CARRY                  (0x00000002)
+#define ED_HALTED                       (0x00000001)
+
+#define TD_SETUP                        (0x00000000)   /* Direction of Setup Packet */
+#define TD_OUT                          (0x00080000)   /* Direction Out */
+#define TD_TOGGLE_0                     (0x02000000)   /* Toggle 0 */
+#define TD_TOGGLE_1                     (0x03000000)   /* Toggle 1 */
+
+/* -------------- USB Standard Requests  -------------- */
+#define GET_STATUS                      (0x00)
+#define SET_FEATURE                     (0x03)
+#define SET_ADDRESS                     (0x05)
+
+#define TD_CTL_MSK_DP                   (0x00180000)
+#define TD_CTL_MSK_T                    (0x03000000)
+#define TD_CTL_MSK_CC                   (0xF0000000)
+#define TD_CTL_MSK_EC                   (0x0C000000)
+#define TD_CTL_SHFT_CC                  (28)
+#define TD_CTL_SHFT_EC                  (26)
+#define TD_CTL_SHFT_T                   (24)
+#define ED_SHFT_TOGLE_CARRY             (1)
+#define SIG_GEN_LIST_REQ                (1)
+#if (ISO_TRANS_MAX_NUM > 0)
+#define TD_PSW_MSK_CC                   (0xF000)
+#define TD_PSW_SHFT_CC                  (12)
+#define TD_CTL_MSK_FC                   (0x07000000)
+#define TD_CTL_SHFT_FC                  (24)
+#endif
+
+#define CTL_TRANS_TIMEOUT               (1000)
+#define BLK_TRANS_TIMEOUT               (5)
+#define TOTAL_SEM_NUM                   (5 + (2 * INT_TRANS_MAX_NUM) + (2 * ISO_TRANS_MAX_NUM))
+
+#define PORT_LOW_SPEED                  (0x00000200)
+#define PORT_HIGH_SPEED                 (0x00000400)
+#define PORT_NUM                        (16 + 1) /* num + root(1) */
+
+typedef struct tag_hctd {
+    uint32_t         control;        /* Transfer descriptor control */
+    uint8_t          *currBufPtr;    /* Physical address of current buffer pointer */
+    struct tag_hctd  *nextTD;        /* Physical pointer to next Transfer Descriptor */
+    uint8_t          *bufEnd;        /* Physical address of end of buffer */
+} hctd_t;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+#define PSW_NUM                         (8)
+typedef struct tag_hcisotd {
+    uint32_t           control;      /* Transfer descriptor control */
+    uint8_t            *bufferPage0; /* Buffer Page 0 */
+    struct tag_hcisotd *nextTD;      /* Physical pointer to next Transfer Descriptor */
+    uint8_t            *bufEnd;      /* Physical address of end of buffer */
+    uint16_t           offsetPSW[PSW_NUM]; /* Offset/PSW */
+} hcisotd_t;
+#endif
+
+typedef struct tag_hced {
+    uint32_t         control;        /* Endpoint descriptor control */
+    uint32_t         tailTD;         /* Physical address of tail in Transfer descriptor list */
+    uint32_t         headTD;         /* Physcial address of head in Transfer descriptor list */
+    struct tag_hced  *nextED;        /* Physical address of next Endpoint descriptor */
+} hced_t;
+
+typedef struct tag_hcca {
+    uint32_t         IntTable[32];   /* Interrupt Table */
+    uint32_t         FrameNumber;    /* Frame Number */
+    uint32_t         DoneHead;       /* Done Head */
+    volatile uint8_t Reserved[116];  /* Reserved for future use */
+    volatile uint8_t Unknown[4];     /* Unused */
+} hcca_t;
+
+typedef struct tag_usb_ohci_reg {
+    volatile uint32_t HcRevision;
+    volatile uint32_t HcControl;
+    volatile uint32_t HcCommandStatus;
+    volatile uint32_t HcInterruptStatus;
+    volatile uint32_t HcInterruptEnable;
+    volatile uint32_t HcInterruptDisable;
+    volatile uint32_t HcHCCA;
+    volatile uint32_t HcPeriodCurrentED;
+    volatile uint32_t HcControlHeadED;
+    volatile uint32_t HcControlCurrentED;
+    volatile uint32_t HcBulkHeadED;
+    volatile uint32_t HcBulkCurrentED;
+    volatile uint32_t HcDoneHead;
+    volatile uint32_t HcFmInterval;
+    volatile uint32_t HcFmRemaining;
+    volatile uint32_t HcFmNumber;
+    volatile uint32_t HcPeriodicStart;
+    volatile uint32_t HcLSThreshold;
+    volatile uint32_t HcRhDescriptorA;
+    volatile uint32_t HcRhDescriptorB;
+    volatile uint32_t HcRhStatus;
+    volatile uint32_t HcRhPortStatus1;
+} usb_ohci_reg_t;
+
+typedef struct tag_genelal_ed {
+    osThreadId_t    tskid;
+    osSemaphoreId_t semid_wait;
+    osSemaphoreId_t semid_list;
+    void            *p_curr_td;     /* pointer of hctd_t or hcisotd_t */
+    hced_t          *p_curr_ed;
+    uint32_t        pipe_no;
+    uint32_t        trans_wait;
+    uint32_t        cycle_time;
+    uint8_t         *p_start_buf;
+#if (ISO_TRANS_MAX_NUM > 0)
+    uint32_t        psw_idx;
+#endif
+} genelal_ed_t;
+
+typedef struct tag_tdinfo {
+    uint32_t         count;
+    uint32_t         direction;
+    uint32_t         msp;
+    uint16_t         devadr;
+    uint16_t         speed;         /* 1:Speed = Low */
+    uint8_t          endpoint_no;
+} tdinfo_t;
+
+typedef struct tag_split_trans {
+    uint16_t        root_devadr;
+    uint16_t        get_port;
+    uint16_t        port_speed;
+    uint16_t        reset_port;
+    uint32_t        seq_cnt;
+    uint32_t        port_sts_bits[PORT_NUM];
+} split_trans_t;
+
+static void callback_task(void const * argument);
+static void control_ed_task(void const * argument);
+static void bulk_ed_task(void const * argument);
+static void int_ed_task(void const * argument);
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index);
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed);
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed);
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed);
+static void set_split_trans_setting(void);
+static void control_trans(genelal_ed_t *p_g_ed);
+static void bulk_trans(genelal_ed_t *p_g_ed);
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static uint32_t chk_cycle(hced_t *p_ed);
+static void int_trans(genelal_ed_t *p_g_ed);
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info);
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed);
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument);
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index);
+static void chk_iso_td_done(genelal_ed_t *p_g_ed);
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed);
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static void iso_trans(genelal_ed_t *p_g_ed);
+#endif
+static void connect_check(void);
+
+extern USB_HOST_CFG_PIPETBL_t  usb_host_blk_ep_tbl1[];
+extern USB_HOST_CFG_PIPETBL_t  usb_host_int_ep_tbl1[];
+#if (ISO_TRANS_MAX_NUM > 0)
+extern USB_HOST_CFG_PIPETBL_t  usb_host_iso_ep_tbl1[];
+#endif
+
+static usb_ohci_reg_t  usb_reg;
+static usb_ohci_reg_t  *p_usb_reg     = &usb_reg;
+static usbisr_fnc_t    *p_usbisr_cb   = NULL;
+static osSemaphoreId_t semid_cb       = NULL;
+static uint32_t        connect_change = 0xFFFFFFFF;
+static uint32_t        connect_status = 0;
+static uint32_t        init_end       = 0;
+static genelal_ed_t    ctl_ed;
+static genelal_ed_t    blk_ed;
+static genelal_ed_t    int_ed[INT_TRANS_MAX_NUM];
+static split_trans_t   split_ctl;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static genelal_ed_t   iso_ed[ISO_TRANS_MAX_NUM];
+#endif
+
+osSemaphoreDef(ohciwrapp_sem_01);
+osSemaphoreDef(ohciwrapp_sem_02);
+osSemaphoreDef(ohciwrapp_sem_03);
+osSemaphoreDef(ohciwrapp_sem_04);
+osSemaphoreDef(ohciwrapp_sem_05);
+osSemaphoreDef(ohciwrapp_sem_06);
+osSemaphoreDef(ohciwrapp_sem_07);
+#if (INT_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_08);
+osSemaphoreDef(ohciwrapp_sem_09);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+osSemaphoreDef(ohciwrapp_sem_10);
+osSemaphoreDef(ohciwrapp_sem_11);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+osSemaphoreDef(ohciwrapp_sem_12);
+osSemaphoreDef(ohciwrapp_sem_13);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+osSemaphoreDef(ohciwrapp_sem_14);
+osSemaphoreDef(ohciwrapp_sem_15);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_16);
+osSemaphoreDef(ohciwrapp_sem_17);
+#endif
+
+osThreadDef(callback_task,   osPriorityHigh,        576);
+osThreadDef(control_ed_task, osPriorityNormal,      576);
+osThreadDef(bulk_ed_task,    osPriorityNormal,      576);
+static void int_ed_task_1(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_1,   osPriorityNormal,      576);
+#if (INT_TRANS_MAX_NUM >= 2)
+static void int_ed_task_2(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_2,   osPriorityNormal,      576);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+static void int_ed_task_3(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_3,   osPriorityNormal,      576);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+static void int_ed_task_4(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_4,   osPriorityNormal,      576);
+#endif
+
+#if (ISO_TRANS_MAX_NUM >= 1)
+static void iso_ed_task_1(void const * argument) {
+    iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_1,   osPriorityAboveNormal, 576);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+static void iso_ed_task_2(void const * argument) {
+    iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_2,   osPriorityAboveNormal, 576);
+#endif
+
+void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) {
+    static const osSemaphoreAttr_t * const sem_def_tbl[TOTAL_SEM_NUM] = {
+        osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03)
+      , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06)
+      , osSemaphore(ohciwrapp_sem_07)
+#if (INT_TRANS_MAX_NUM >= 2)
+      , osSemaphore(ohciwrapp_sem_08), osSemaphore(ohciwrapp_sem_09)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+      , osSemaphore(ohciwrapp_sem_10), osSemaphore(ohciwrapp_sem_11)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+      , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+      , osSemaphore(ohciwrapp_sem_14), osSemaphore(ohciwrapp_sem_15)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+      , osSemaphore(ohciwrapp_sem_16), osSemaphore(ohciwrapp_sem_17)
+#endif
+    };
+    static const osThreadDef_t * const int_tsk_def_tbl[INT_TRANS_MAX_NUM] = {
+        osThread(int_ed_task_1)
+#if (INT_TRANS_MAX_NUM >= 2)
+      , osThread(int_ed_task_2)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+      , osThread(int_ed_task_3)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+      , osThread(int_ed_task_4)
+#endif
+    };
+#if (ISO_TRANS_MAX_NUM > 0)
+    static const osThreadDef_t * const iso_tsk_def_tbl[ISO_TRANS_MAX_NUM] = {
+        osThread(iso_ed_task_1)
+#if (ISO_TRANS_MAX_NUM >= 2)
+      , osThread(iso_ed_task_2)
+#endif
+    };
+#endif
+
+    uint32_t cnt;
+    uint32_t index = 0;
+
+    /* Disables interrupt for usb */
+    GIC_DisableIRQ(USBIXUSBIX);
+
+#if defined(TARGET_GR_LYCHEE) /* mbed */
+    /* P7_5(USB1_EN) */
+    GPIOP7      &= ~0x0020;         /* Outputs low level */
+    GPIOPMC7    &= ~0x0020;         /* Port mode */
+    GPIOPM7     &= ~0x0020;         /* Output mode */
+#else
+#if (USB_HOST_CH == 0)
+    /* P4_1(USB0_EN) */
+    GPIOP4      &= ~0x0002;         /* Outputs low level */
+    GPIOPMC4    &= ~0x0002;         /* Port mode */
+    GPIOPM4     &= ~0x0002;         /* Output mode */
+#else
+#if MBED_CONF_APP_AUDIO_CAMERA_SHIELD
+    /* P3_8(USB1_EN) */
+    GPIOP3      &= ~0x0100;         /* Outputs low level */
+    GPIOPMC3    &= ~0x0100;         /* Port mode */
+    GPIOPM3     &= ~0x0100;         /* Output mode */
+#endif
+#endif
+#endif
+
+    p_usbisr_cb = p_usbisr_fnc;
+#if (USB_HOST_HISPEED == 0)
+    g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED;
+#else
+    g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+#endif
+    p_usb_reg->HcRevision         = 0x00000010;
+    p_usb_reg->HcControl          = 0x00000000;
+    p_usb_reg->HcCommandStatus    = 0x00000000;
+    p_usb_reg->HcInterruptStatus  = 0x00000000;
+    p_usb_reg->HcInterruptEnable  = 0x00000000;
+    p_usb_reg->HcInterruptDisable = 0x00000000;
+    p_usb_reg->HcHCCA             = 0x00000000;
+    p_usb_reg->HcPeriodCurrentED  = 0x00000000;
+    p_usb_reg->HcControlHeadED    = 0x00000000;
+    p_usb_reg->HcControlCurrentED = 0x00000000;
+    p_usb_reg->HcBulkHeadED       = 0x00000000;
+    p_usb_reg->HcBulkCurrentED    = 0x00000000;
+    p_usb_reg->HcDoneHead         = 0x00000000;
+    p_usb_reg->HcFmInterval       = 0x00002EDF;
+    p_usb_reg->HcFmRemaining      = 0x00002EDF;
+    p_usb_reg->HcFmNumber         = 0x00000000;
+    p_usb_reg->HcPeriodicStart    = 0x00000000;
+    p_usb_reg->HcLSThreshold      = 0x00000628;
+    p_usb_reg->HcRhDescriptorA    = 0xFF000901;
+    p_usb_reg->HcRhDescriptorB    = 0x00020000;
+    p_usb_reg->HcRhStatus         = 0x00000000;
+    p_usb_reg->HcRhPortStatus1    = 0x00000000;
+
+#if defined(TARGET_GR_LYCHEE) /* mbed */
+    GPIOP7      |=  0x0020;         /* P7_5 Outputs high level */
+    osDelay(5);
+    GPIOP7      &= ~0x0020;         /* P7_5 Outputs low level */
+    osDelay(10);
+#else
+#if (USB_HOST_CH == 0)
+    GPIOP4      |=  0x0002;         /* P4_1 Outputs high level */
+    osDelay(5);
+    GPIOP4      &= ~0x0002;         /* P4_1 Outputs low level */
+    osDelay(10);
+#else
+#if MBED_CONF_APP_AUDIO_CAMERA_SHIELD
+    GPIOP3      |=  0x0100;         /* P3_8 Outputs high level */
+    osDelay(5);
+    GPIOP3      &= ~0x0100;         /* P3_8 Outputs low level */
+    osDelay(10);
+#else
+    osDelay(15);
+#endif
+#endif
+#endif
+
+    if (init_end == 0) {
+        (void)memset(&ctl_ed, 0, sizeof(ctl_ed));
+        (void)memset(&blk_ed, 0, sizeof(blk_ed));
+        (void)memset(&int_ed[0], 0, sizeof(int_ed));
+#if (ISO_TRANS_MAX_NUM > 0)
+        (void)memset(&iso_ed[0], 0, sizeof(iso_ed));
+#endif
+
+        /* callback */
+        semid_cb = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+        index++;
+        (void)osThreadCreate(osThread(callback_task), 0);
+
+        /* control transfer */
+        ctl_ed.semid_wait = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+        index++;
+        ctl_ed.semid_list = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+        index++;
+        ctl_ed.tskid = osThreadCreate(osThread(control_ed_task), 0);
+
+        /* bulk transfer */
+        blk_ed.semid_wait = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+        index++;
+        blk_ed.semid_list = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+        index++;
+        blk_ed.tskid = osThreadCreate(osThread(bulk_ed_task), 0);
+
+        /* interrupt transfer */
+        for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+            int_ed[cnt].semid_wait = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+            index++;
+            int_ed[cnt].semid_list = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+            index++;
+            int_ed[cnt].tskid = osThreadCreate(int_tsk_def_tbl[cnt], (void *)cnt);
+        }
+
+#if (ISO_TRANS_MAX_NUM > 0)
+        /* isochronous transfer */
+        for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+            iso_ed[cnt].semid_wait = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+            index++;
+            iso_ed[cnt].semid_list = osSemaphoreNew(0xffff, 0, sem_def_tbl[index]);
+            index++;
+            iso_ed[cnt].tskid = osThreadCreate(iso_tsk_def_tbl[cnt], (void *)cnt);
+        }
+#endif
+        init_end = 1;
+    }
+}
+
+uint32_t ohciwrapp_reg_r(uint32_t reg_ofs) {
+    if (init_end == 0) {
+        return 0;
+    }
+
+    return *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs);
+}
+
+void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) {
+    uint32_t cnt;
+    uint32_t last_data;
+    hcca_t   *p_hcca;
+
+    if (init_end == 0) {
+        return;
+    }
+
+    switch (reg_ofs) {
+        case OHCI_REG_CONTROL:
+            last_data            = p_usb_reg->HcControl;
+            p_usb_reg->HcControl = (set_data & 0x000007FF);
+            if ((last_data & OR_CONTROL_CLE) != (set_data & OR_CONTROL_CLE)) {
+                /* change CLE */
+                if ((set_data & OR_CONTROL_CLE) != 0) {
+                    (void)osSemaphoreRelease(ctl_ed.semid_list);
+                } else {
+                    if (ctl_ed.trans_wait == 1) {
+                        ctl_ed.trans_wait = 0;
+                        (void)osSemaphoreRelease(ctl_ed.semid_wait);
+                    }
+                    (void)osSemaphoreAcquire (ctl_ed.semid_list, osWaitForever);
+                }
+            }
+            if ((last_data & OR_CONTROL_BLE) != (set_data & OR_CONTROL_BLE)) {
+                /* change BLE */
+                if ((set_data & OR_CONTROL_BLE) != 0) {
+                    (void)osSemaphoreRelease(blk_ed.semid_list);
+                } else {
+                    if (blk_ed.trans_wait == 1) {
+                        blk_ed.trans_wait = 0;
+                        (void)osSemaphoreRelease(blk_ed.semid_wait);
+                    }
+                    (void)osSemaphoreAcquire (blk_ed.semid_list, osWaitForever);
+                }
+            }
+#if (ISO_TRANS_MAX_NUM > 0)
+            if ((last_data & OR_CONTROL_IE) != (set_data & OR_CONTROL_IE)) {
+                /* change IE */
+                for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+                    if ((set_data & OR_CONTROL_IE) != 0) {
+                        (void)osSemaphoreRelease(iso_ed[cnt].semid_list);
+                    } else {
+                        if (iso_ed[cnt].trans_wait == 1) {
+                            iso_ed[cnt].trans_wait = 0;
+                            (void)osSemaphoreRelease(iso_ed[cnt].semid_wait);
+                        }
+                        (void)osSemaphoreAcquire (iso_ed[cnt].semid_list, osWaitForever);
+                    }
+                }
+            }
+#endif
+            if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) {
+                /* change PLE */
+                for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+                    if ((set_data & OR_CONTROL_PLE) != 0) {
+                        (void)osSemaphoreRelease(int_ed[cnt].semid_list);
+                    } else {
+                        if (int_ed[cnt].trans_wait == 1) {
+                            int_ed[cnt].trans_wait = 0;
+                            (void)osSemaphoreRelease(int_ed[cnt].semid_wait);
+                        }
+                        (void)osSemaphoreAcquire (int_ed[cnt].semid_list, osWaitForever);
+                    }
+                }
+            }
+            break;
+        case OHCI_REG_COMMANDSTATUS:
+            if ((set_data & OR_CMD_STATUS_HCR) != 0) {    /* HostController Reset */
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR;
+                if (usbx_api_host_init(16, g_usbx_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) {
+                    ohciwrapp_loc_Connect(1);
+                }
+                p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR;
+            }
+            if ((set_data & OR_CMD_STATUS_CLF) != 0) {
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+                osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+            }
+            if ((set_data & OR_CMD_STATUS_BLF) != 0) {
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+                osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+            }
+            if ((set_data & OR_CMD_STATUS_OCR) != 0) {
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_OCR;
+            } else {
+                p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_OCR;
+            }
+            break;
+        case OHCI_REG_INTERRUPTSTATUS:
+            if (((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) != 0)
+             && ((set_data & OR_INTR_STATUS_WDH) != 0)) {
+                if (p_usb_reg->HcDoneHead != 0x00000000) {
+                    p_hcca                       =  (hcca_t *)p_usb_reg->HcHCCA;
+                    p_hcca->DoneHead             =  p_usb_reg->HcDoneHead;
+                    p_usb_reg->HcDoneHead        =  0x00000000;
+                    p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+                    (void)osSemaphoreRelease(semid_cb);
+                } else {
+                    p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_WDH;
+                }
+            }
+            if ((set_data & OR_INTR_STATUS_RHSC) != 0) {
+                p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_RHSC;
+            }
+            break;
+        case OHCI_REG_INTERRUPTENABLE:
+        case OHCI_REG_INTERRUPTDISABLE:
+        case OHCI_REG_HCCA:
+        case OHCI_REG_CONTROLHEADED:
+        case OHCI_REG_CONTROLCURRENTED:
+        case OHCI_REG_BULKHEADED:
+        case OHCI_REG_BULKCURRENTED:
+        case OHCI_REG_FMINTERVAL:
+        case OHCI_REG_FMREMAINING:
+        case OHCI_REG_PERIODICSTART:
+        case OHCI_REG_LSTHRESHOLD:
+        case OHCI_REG_RHDESCRIPTORA:
+        case OHCI_REG_RHDESCRIPTORB:
+        case OHCI_REG_RHSTATUS:
+            *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs) = set_data;
+            break;
+        case OHCI_REG_RHPORTSTATUS1:
+            p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000);
+            if ((set_data & OR_RH_PORT_PRS) != 0) {    /* Set Port Reset */
+                p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS;
+                usbx_host_UsbBusReset();
+                p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS;
+            }
+            break;
+        case OHCI_REG_REVISION:
+        case OHCI_REG_PERIODCURRENTED:
+        case OHCI_REG_DONEHEADED:
+        case OHCI_REG_FMNUMBER:
+        default:
+            /* Do Nothing */
+            break;
+    }
+}
+
+static void callback_task(void const * argument) {
+    usbisr_fnc_t *p_wk_cb = p_usbisr_cb;
+
+    if (p_wk_cb == NULL) {
+        return;
+    }
+
+    while (1) {
+        osSemaphoreAcquire (semid_cb, osWaitForever);
+        if (connect_change != 0xFFFFFFFF) {
+            connect_change = 0xFFFFFFFF;
+            connect_check();
+        }
+        p_wk_cb();
+    }
+}
+
+static void control_ed_task(void const * argument) {
+    while (1) {
+        osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+        (void)osSemaphoreAcquire (ctl_ed.semid_list, osWaitForever);
+        while ((p_usb_reg->HcControl & OR_CONTROL_CLE) != 0) {
+            if ((p_usb_reg->HcControlCurrentED == 0)
+             && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0)) {
+                p_usb_reg->HcControlCurrentED =  p_usb_reg->HcControlHeadED;
+                p_usb_reg->HcCommandStatus    &= ~OR_CMD_STATUS_CLF;
+            }
+            if (p_usb_reg->HcControlCurrentED != 0) {
+                ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED;
+                if (chk_genelal_ed(&ctl_ed) != 0) {
+                    control_trans(&ctl_ed);
+                    p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+                }
+                p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED;
+            } else {
+                break;
+            }
+        }
+        if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0) {
+            osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+        }
+        (void)osSemaphoreRelease(ctl_ed.semid_list);
+    }
+}
+
+static void bulk_ed_task(void const * argument) {
+    while (1) {
+        osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+        (void)osSemaphoreAcquire (blk_ed.semid_list, osWaitForever);
+        while ((p_usb_reg->HcControl & OR_CONTROL_BLE) != 0) {
+            if ((p_usb_reg->HcBulkCurrentED == 0)
+             && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0)) {
+                p_usb_reg->HcBulkCurrentED =  p_usb_reg->HcBulkHeadED;
+                p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_BLF;
+            }
+            if (p_usb_reg->HcBulkCurrentED != 0) {
+                blk_ed.p_curr_ed = (hced_t *)p_usb_reg->HcBulkCurrentED;
+                if (chk_genelal_ed(&blk_ed) != 0) {
+                    bulk_trans(&blk_ed);
+                    p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+                }
+                p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED;
+            } else {
+                break;
+            }
+        }
+        if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0) {
+            osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+        }
+        (void)osSemaphoreRelease(blk_ed.semid_list);
+    }
+}
+
+static void int_ed_task(void const * argument) {
+    genelal_ed_t *p_int_ed = &int_ed[(uint32_t)argument];
+    uint32_t     cnt;
+    uint32_t     wait_cnt = 0;
+    hcca_t       *p_hcca;
+    hced_t       *p_ed;
+
+    while (1) {
+        (void)osSemaphoreAcquire (p_int_ed->semid_list, osWaitForever);
+        if (p_int_ed->p_curr_ed == NULL) {
+            for (cnt = 0; (cnt < 32) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+                                                 && (p_int_ed->p_curr_ed == NULL); cnt++) {
+                p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+                p_ed   = (hced_t *)p_hcca->IntTable[cnt];
+                while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+                                                        && (p_int_ed->p_curr_ed == NULL)) {
+                    if (int_trans_doing(p_ed, (uint32_t)argument) == 0) {
+                        p_int_ed->p_curr_ed = p_ed;
+                        if (chk_genelal_ed(p_int_ed) != 0) {
+                            int_trans_setting(p_int_ed, (uint32_t)argument);
+                        } else {
+                            p_int_ed->p_curr_ed = NULL;
+                        }
+                    }
+                    p_ed = p_ed->nextED;
+                }
+            }
+        }
+        if (p_int_ed->p_curr_ed != NULL) {
+            while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) {
+                if (chk_genelal_ed(p_int_ed) != 0) {
+                    int_trans(p_int_ed);
+                    (void)osSemaphoreAcquire (p_int_ed->semid_wait, osWaitForever);
+                    usbx_host_stop_transfer(p_int_ed->pipe_no);
+                    wait_cnt = p_int_ed->cycle_time;
+                } else {
+                    if (wait_cnt > 0) {
+                        wait_cnt--;
+                    } else {
+                        p_int_ed->p_curr_ed = NULL;
+                    }
+                    break;
+                }
+            }
+        }
+        (void)osSemaphoreRelease(p_int_ed->semid_list);
+        if (p_int_ed->p_curr_ed == NULL) {
+            osDelay(10);
+        } else {
+            osDelay(1);
+        }
+    }
+}
+
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index) {
+    uint32_t cnt;
+    int32_t  ret = 0;
+
+    for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+        if ((index != cnt) && (int_ed[cnt].p_curr_ed == p_ed)) {
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){
+    int32_t ret   = 0;
+    hced_t  *p_ed = p_g_ed->p_curr_ed;
+
+    if (((p_ed->control & ED_SKIP)   != 0)
+     || ((p_ed->control & ED_FORMAT) != 0)
+     || ((p_ed->headTD & ED_HALTED)  != 0)
+     || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+        /* Do Nothing */
+    } else if ((p_ed->control & 0x0000007F) > 10) {
+        p_ed->headTD |= ED_HALTED;
+    } else {
+        p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+        if (p_g_ed->p_curr_td == NULL) {
+            p_ed->headTD |= ED_HALTED;
+        } else {
+            hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+            p_g_ed->p_start_buf = p_td->currBufPtr;
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed) {
+    hcca_t   *p_hcca;
+    hctd_t   *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    uint32_t ConditionCode = RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+    if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+        p_g_ed->p_curr_ed->headTD = ((uint32_t)p_td->nextTD & 0xFFFFFFF0)
+                                  | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+        p_td->nextTD              = (hctd_t *)p_usb_reg->HcDoneHead;
+        p_usb_reg->HcDoneHead     = (uint32_t)p_g_ed->p_curr_td;
+        if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+            p_hcca                       =  (hcca_t *)p_usb_reg->HcHCCA;
+            p_hcca->DoneHead             =  p_usb_reg->HcDoneHead;
+            p_usb_reg->HcDoneHead        =  0x00000000;
+            p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+            (void)osSemaphoreRelease(semid_cb);
+        }
+    }
+}
+
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed) {
+    uint8_t   *p_buf;
+    tdinfo_t  td_info;
+    hctd_t    *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+    /* Hi-Speed mode only */
+    if (g_usbx_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) {
+        return;
+    }
+
+    if (RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) {
+        return;
+    }
+
+    get_td_info(p_g_ed, &td_info);
+    p_buf = p_g_ed->p_start_buf;
+
+    if (td_info.direction == 0) {
+        uint8_t  bRequest = p_buf[1];
+        uint16_t wValue   = (p_buf[3] << 8) + p_buf[2];
+        uint16_t wIndx    = (p_buf[5] << 8) + p_buf[4];
+        uint16_t devadd;
+
+        if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) {
+            /* SET_ADDRESS */
+            usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+            usbx_host_set_devadd(wValue, &devadd);
+            if (split_ctl.root_devadr == 0) {
+                split_ctl.root_devadr = wValue; /* New Address */
+            }
+        } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == SET_FEATURE)
+                && (wValue == 0x0004) && (split_ctl.root_devadr != 0)) {
+            /* SET_FEATURE PORT_RESET */
+            split_ctl.reset_port = (wIndx & 0x00FF);
+        } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == GET_STATUS)) {
+            /* GET_STATUS */
+            split_ctl.get_port = wIndx;
+            split_ctl.seq_cnt = 1;
+        } else {
+            /* Do Nothing */
+        }
+    } else if (td_info.direction == 2) {
+        if ((td_info.devadr == split_ctl.root_devadr) && (split_ctl.seq_cnt == 1)) {
+            if (split_ctl.get_port < PORT_NUM) {
+                split_ctl.port_sts_bits[split_ctl.get_port] = (p_buf[1] << 8) + p_buf[0];
+            }
+            split_ctl.seq_cnt = 0;
+        }
+    } else {
+        /* Do Nothing */
+    }
+}
+
+static void set_split_trans_setting(void) {
+    uint16_t port_speed;
+    uint16_t devadd;
+
+    if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) {
+        usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+        RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+        RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+        if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) {
+            port_speed = USB_HOST_HIGH_SPEED;
+        } else if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_LOW_SPEED) != 0) {
+            port_speed = USB_HOST_LOW_SPEED;
+        } else {
+            port_speed = USB_HOST_FULL_SPEED;
+        }
+        RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+        split_ctl.reset_port = 0;
+    }
+}
+
+static void control_trans(genelal_ed_t *p_g_ed) {
+    hctd_t   *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    tdinfo_t td_info;
+    uint16_t devadd;
+
+    get_td_info(p_g_ed, &td_info);
+
+    if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+        if (td_info.devadr == 0) {
+            set_split_trans_setting();
+        }
+    } else {
+        /* When a non-Hi-Speed, the communication speed is determined from the TD. */
+        usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+        if (td_info.speed == 1) {
+            RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        } else {
+            RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        }
+        usbx_host_set_devadd(td_info.devadr, &devadd);
+    }
+
+    USB20X.DCPMAXP  = (td_info.devadr << 12) + td_info.msp;
+    if (td_info.direction == 0) {
+        g_usbx_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+    } else  if (td_info.count != 0) {
+        g_usbx_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE);
+    } else {
+        g_usbx_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE);
+    }
+    g_usbx_host_pipe_status[USB_HOST_PIPE0]  = USB_HOST_PIPE_WAIT;
+    p_g_ed->pipe_no    = USB_HOST_PIPE0;
+
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 0) {
+            uint16_t Req  = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0];
+            uint16_t Val  = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2];
+            uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4];
+            uint16_t Len  = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6];
+
+            g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd;
+            usbx_host_SetupStage(Req, Val, Indx, Len);
+        } else if (td_info.direction == 1) {
+            usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr);
+        } else {
+            usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr);
+        }
+
+        (void)osSemaphoreAcquire (p_g_ed->semid_wait, CTL_TRANS_TIMEOUT);
+        if (p_g_ed->trans_wait == 1) {
+            p_g_ed->trans_wait = 0;
+            RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+        }
+    }
+
+    g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usbx_host_CmdStage |= USB_HOST_CMD_IDLE;
+    g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+}
+
+static void bulk_trans(genelal_ed_t *p_g_ed) {
+    hctd_t                 *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    hced_t                 *p_ed = p_g_ed->p_curr_ed;
+    tdinfo_t               td_info;
+    USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_blk_ep_tbl1[0];
+    uint8_t                wk_table[6];
+
+    get_td_info(p_g_ed, &td_info);
+
+    wk_table[0] = 0;
+    wk_table[1] = USB_HOST_ENDPOINT_DESC;
+    wk_table[2] = td_info.endpoint_no;
+    if (td_info.direction == 2) {
+        wk_table[2] |= USB_HOST_EP_IN;
+    }
+    wk_table[3] = USB_HOST_EP_BULK;
+    wk_table[4] = (uint8_t)td_info.msp;
+    wk_table[5] = (uint8_t)(td_info.msp >> 8);
+    p_g_ed->pipe_no    = user_table->pipe_number;
+    usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+    set_togle(p_g_ed->pipe_no, p_td, p_ed);
+
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 1) {
+            usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        } else {
+            usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        }
+
+        (void)osSemaphoreAcquire (p_g_ed->semid_wait, BLK_TRANS_TIMEOUT);
+        usbx_host_stop_transfer(p_g_ed->pipe_no);
+    }
+}
+
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+    hctd_t                 *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    hced_t                 *p_ed = p_g_ed->p_curr_ed;
+    tdinfo_t               td_info;
+    USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_int_ep_tbl1[index];
+    uint8_t                wk_table[6];
+    uint32_t               cycle_time;
+    uint16_t               devadd;
+
+    get_td_info(p_g_ed, &td_info);
+
+    wk_table[0] = 0;
+    wk_table[1] = USB_HOST_ENDPOINT_DESC;
+    wk_table[2] = td_info.endpoint_no;
+    if (td_info.direction == 2) {
+        wk_table[2] |= USB_HOST_EP_IN;
+    }
+    wk_table[3] = USB_HOST_EP_INT;
+    wk_table[4] = (uint8_t)td_info.msp;
+    wk_table[5] = (uint8_t)(td_info.msp >> 8);
+    cycle_time  = chk_cycle(p_ed);
+    p_g_ed->cycle_time = cycle_time;
+    user_table->pipe_cycle = 0;
+    while (cycle_time > 1) {
+        cycle_time >>= 1;
+        user_table->pipe_cycle++;
+    }
+    if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+        usbx_host_get_devadd(td_info.devadr, &devadd);
+        if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+            user_table->pipe_cycle += 3;
+            if (user_table->pipe_cycle > 7) {
+                user_table->pipe_cycle = 7;
+            }
+        }
+    }
+
+    p_g_ed->pipe_no    = user_table->pipe_number;
+    usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+    set_togle(p_g_ed->pipe_no, p_td, p_ed);
+}
+
+static uint32_t chk_cycle(hced_t *p_ed) {
+    uint32_t     cnt;
+    uint32_t     hit_cnt    = 0;
+    uint32_t     cycle_time = 1;
+    hcca_t       *p_hcca;
+    hced_t       *p_wk_ed;
+
+    p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+
+    for (cnt = 0; cnt < 32; cnt++) {
+        p_wk_ed = (hced_t *)p_hcca->IntTable[cnt];
+        while (p_wk_ed != NULL) {
+            if (p_wk_ed == p_ed) {
+                hit_cnt++;
+                break;
+            }
+            p_wk_ed = p_wk_ed->nextED;
+        }
+    }
+    if (hit_cnt < 2) {
+        cycle_time = 32;
+    } else if (hit_cnt < 4) {
+        cycle_time = 16;
+    } else if (hit_cnt < 8) {
+        cycle_time = 8;
+    } else if (hit_cnt < 16) {
+        cycle_time = 4;
+    } else if (hit_cnt < 32) {
+        cycle_time = 2;
+    } else{
+        cycle_time = 1;
+    }
+
+    return cycle_time;
+}
+
+static void int_trans(genelal_ed_t *p_g_ed) {
+    hctd_t   *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    tdinfo_t td_info;
+
+    get_td_info(p_g_ed, &td_info);
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 1) {
+            usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        } else {
+            usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        }
+    }
+}
+
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) {
+    hced_t *p_ed = p_g_ed->p_curr_ed;
+
+    p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F);
+    p_td_info->msp         = (p_ed->control >> 16) & 0x000007FF;
+    p_td_info->devadr      = p_ed->control & 0x0000000F;
+    p_td_info->speed       = (p_ed->control >> 13) & 0x00000001;
+    p_td_info->direction   = (p_ed->control >> 11) & 0x00000003;
+
+    if ((p_ed->control & ED_FORMAT) == 0) {
+        hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+        if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+            if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) {
+                p_td_info->direction = 0;
+            } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) {
+                p_td_info->direction = 1;
+            } else {
+                p_td_info->direction = 2;
+            }
+        }
+        if (p_td->currBufPtr != NULL) {
+            p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1;
+        } else {
+            p_td_info->count     = 0;
+        }
+    } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+        hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+        if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+            if ((p_isotd->control & TD_CTL_MSK_DP) == TD_SETUP) {
+                p_td_info->direction = 0;
+            } else if ((p_isotd->control & TD_CTL_MSK_DP) == TD_OUT) {
+                p_td_info->direction = 1;
+            } else {
+                p_td_info->direction = 2;
+            }
+        }
+#endif
+    }
+}
+
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) {
+    if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) {
+        usbx_host_set_sqclr(pipe);
+    } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) {
+        usbx_host_set_sqset(pipe);
+    } else if ((p_ed->headTD & ED_TOGLE_CARRY) == 0) {
+        usbx_host_set_sqclr(pipe);
+    } else {
+        usbx_host_set_sqset(pipe);
+    }
+}
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument) {
+    genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument];
+    uint32_t     wait_cnt = 0;
+    hcca_t       *p_hcca;
+    hced_t       *p_ed;
+
+    while (1) {
+        (void)osSemaphoreAcquire (p_iso_ed->semid_list, osWaitForever);
+        if (p_iso_ed->p_curr_ed == NULL) {
+            p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+            p_ed   = (hced_t *)p_hcca->IntTable[0];
+            while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0)
+                                                    && (p_iso_ed->p_curr_ed == NULL)) {
+                if (iso_trans_doing(p_ed, (uint32_t)argument) == 0) {
+                    p_iso_ed->p_curr_ed = p_ed;
+                    if (chk_iso_ed(p_iso_ed) != 0) {
+                        iso_trans_setting(p_iso_ed, (uint32_t)argument);
+                    } else {
+                        p_iso_ed->p_curr_ed = NULL;
+                    }
+                }
+                p_ed = p_ed->nextED;
+            }
+            p_iso_ed->psw_idx = 0;
+        }
+        if (p_iso_ed->p_curr_ed != NULL) {
+            while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) {
+                if (chk_iso_ed(p_iso_ed) != 0) {
+                    hcisotd_t *p_isotd = (hcisotd_t *)p_iso_ed->p_curr_td;
+                    uint32_t  starting_frame = p_isotd->control & 0x0000FFFF;
+                    uint32_t  wait_time = 0;
+                    uint32_t  wk_HcFmNumber = p_usb_reg->HcFmNumber;
+
+                    if (starting_frame > wk_HcFmNumber) {
+                        wait_time = starting_frame - wk_HcFmNumber;
+                    } else {
+                        wait_time = (0xFFFF - wk_HcFmNumber) + starting_frame;
+                    }
+                    if ((wait_time >= 2) && (wait_time <= 1000)) {
+                        for (int cnt = 0; cnt < (wait_time - 1); cnt++) {
+                            osDelay(1);
+                            p_usb_reg->HcFmNumber = (wk_HcFmNumber + cnt) & 0x0000FFFF;
+                        }
+                    }
+                    p_iso_ed->psw_idx   = 0;
+                    iso_trans(p_iso_ed);
+                    (void)osSemaphoreAcquire (p_iso_ed->semid_wait, osWaitForever);
+                    wait_cnt = 8;
+                } else {
+                    if (wait_cnt > 0) {
+                        wait_cnt--;
+                    } else {
+                        p_iso_ed->p_curr_ed = NULL;
+                    }
+                    break;
+                }
+            }
+        }
+        (void)osSemaphoreRelease(p_iso_ed->semid_list);
+        if (p_iso_ed->p_curr_ed == NULL) {
+            osDelay(10);
+        } else {
+            osDelay(1);
+        }
+    }
+}
+
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index) {
+    uint32_t cnt;
+    int32_t  ret = 0;
+
+    for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+        if ((index != cnt) && (iso_ed[cnt].p_curr_ed == p_ed)) {
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static void chk_iso_td_done(genelal_ed_t *p_g_ed) {
+    hcca_t    *p_hcca;
+    hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+    uint32_t  ConditionCode = RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+    if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+        p_g_ed->p_curr_ed->headTD = ((uint32_t)p_isotd->nextTD & 0xFFFFFFF0)
+                                  | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+        p_isotd->nextTD           = (hcisotd_t *)p_usb_reg->HcDoneHead;
+        p_usb_reg->HcDoneHead     = (uint32_t)p_g_ed->p_curr_td;
+        if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+            p_hcca                       =  (hcca_t *)p_usb_reg->HcHCCA;
+            p_hcca->DoneHead             =  p_usb_reg->HcDoneHead;
+            p_usb_reg->HcDoneHead        =  0x00000000;
+            p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+            (void)osSemaphoreRelease(semid_cb);
+        }
+    }
+}
+
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed){
+    int32_t ret   = 0;
+    hced_t  *p_ed = p_g_ed->p_curr_ed;
+
+    if (((p_ed->control & ED_SKIP)   != 0)
+     || ((p_ed->control & ED_FORMAT) == 0)
+     || ((p_ed->headTD & ED_HALTED)  != 0)
+     || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+        /* Do Nothing */
+    } else if ((p_ed->control & 0x0000007F) > 10) {
+        p_ed->headTD |= ED_HALTED;
+    } else {
+        p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+        if (p_g_ed->p_curr_td == NULL) {
+            p_ed->headTD |= ED_HALTED;
+        } else {
+            hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+            p_g_ed->p_start_buf = p_isotd->bufferPage0;
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+    tdinfo_t               td_info;
+    USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_iso_ep_tbl1[index];
+    uint8_t                wk_table[6];
+    uint16_t               devadd;
+
+    get_td_info(p_g_ed, &td_info);
+
+    wk_table[0] = 0;
+    wk_table[1] = USB_HOST_ENDPOINT_DESC;
+    wk_table[2] = td_info.endpoint_no;
+    if (td_info.direction == 2) {
+        wk_table[2] |= USB_HOST_EP_IN;
+    }
+    wk_table[3] = USB_HOST_EP_ISO;
+    wk_table[4] = (uint8_t)td_info.msp;
+    wk_table[5] = (uint8_t)(td_info.msp >> 8);
+    p_g_ed->cycle_time = 1;
+    user_table->pipe_cycle = 0;
+    if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+        usbx_host_get_devadd(td_info.devadr, &devadd);
+        if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+            user_table->pipe_cycle += 3;
+        }
+    }
+
+    p_g_ed->pipe_no    = user_table->pipe_number;
+    usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+}
+
+static void iso_trans(genelal_ed_t *p_g_ed) {
+    hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+    tdinfo_t  td_info;
+    uint32_t  buff_addr;
+    uint32_t  data_size;
+
+    if (((uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00001000) == 0) {
+        buff_addr = (uint32_t)p_isotd->bufferPage0 & 0xFFFFF000;
+    } else {
+        buff_addr = (uint32_t)p_isotd->bufEnd & 0xFFFFF000;
+    }
+    buff_addr |= (uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00000FFF;
+
+    if (p_g_ed->psw_idx < RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+        data_size = p_isotd->offsetPSW[p_g_ed->psw_idx + 1] - p_isotd->offsetPSW[p_g_ed->psw_idx];
+    } else {
+        data_size = (uint32_t)p_isotd->bufEnd - buff_addr + 1;
+    }
+    p_isotd->offsetPSW[p_g_ed->psw_idx] = (uint16_t)data_size;
+
+    get_td_info(p_g_ed, &td_info);
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 1) {
+            usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+        } else {
+            usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+        }
+    }
+}
+#endif
+
+static void connect_check(void) {
+    uint32_t type = 0;
+    uint16_t stat;
+    uint16_t devadd = 0;
+    uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1;
+
+    if (usbx_host_CheckAttach() == USB_HOST_ATTACH) {
+        type = 1;
+    }
+
+    if ((((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) == 0) && (type == 0))
+     || (((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) != 0) && (type != 0))) {
+        return;
+    }
+
+    if (type == 0) {
+        usbx_host_UsbDetach();
+        wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS;
+    } else {
+        usbx_host_UsbAttach();
+        stat = usbx_host_UsbBusReset();
+        RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+        RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+        if (stat == USB_HOST_HSMODE) {
+            wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+            RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+            g_usbx_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+        } else if (stat == USB_HOST_FSMODE) {
+            wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+            RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+            g_usbx_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED;
+        } else {
+            wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA;
+            RZA_IO_RegWrite_16(&USB20X.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+            g_usbx_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED;
+        }
+        RZA_IO_RegWrite_16(&devadd, g_usbx_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        usbx_host_init_pipe_status();
+        usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+        wk_HcRhPortStatus1 |= OR_RH_PORT_CCS;
+    }
+    wk_HcRhPortStatus1           |= OR_RH_PORT_CSC;
+    p_usb_reg->HcRhPortStatus1   =  wk_HcRhPortStatus1;
+    p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC;
+    (void)memset(&split_ctl, 0, sizeof(split_ctl));
+}
+
+void ohciwrapp_loc_Connect(uint32_t type) {
+    uint32_t cnt;
+
+    connect_status = type;
+    connect_change = type;
+    if (type == 0) {
+        if (ctl_ed.trans_wait == 1) {
+            ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+        }
+        if (blk_ed.trans_wait == 1) {
+            ohciwrapp_loc_TransEnd(blk_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+        }
+        for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+            if (int_ed[cnt].trans_wait == 1) {
+                ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+            }
+        }
+#if (ISO_TRANS_MAX_NUM > 0)
+        for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+            if (iso_ed[cnt].trans_wait == 1) {
+                hced_t  *p_ed = iso_ed[cnt].p_curr_ed;
+
+                p_ed->headTD |= ED_HALTED;
+                ohciwrapp_loc_TransEnd(iso_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+            }
+        }
+#endif
+    }
+    (void)osSemaphoreRelease(semid_cb);
+}
+
+void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
+    uint32_t     periodic = 0;
+    uint32_t     cnt;
+    uint32_t     sqmon;
+    hced_t       *p_ed;
+    genelal_ed_t *p_wait_ed = NULL;
+
+    if (ctl_ed.pipe_no == pipe) {
+        p_wait_ed = &ctl_ed;
+    } else if (blk_ed.pipe_no == pipe) {
+        p_wait_ed = &blk_ed;
+    } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+        if (p_wait_ed == NULL) {
+            for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+                if (iso_ed[cnt].pipe_no == pipe) {
+                    p_wait_ed = &iso_ed[cnt];
+                    break;
+                }
+            }
+        }
+#endif
+        if (p_wait_ed == NULL) {
+            for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+                if (int_ed[cnt].pipe_no == pipe) {
+                    p_wait_ed = &int_ed[cnt];
+                    periodic = 1;
+                    break;
+                }
+            }
+        }
+    }
+
+    if (p_wait_ed == NULL) {
+        return;
+    }
+    p_ed  = p_wait_ed->p_curr_ed;
+    if (p_ed == NULL) {
+        return;
+    }
+
+    if ((p_ed->control & ED_FORMAT) == 0) {
+        hctd_t    *p_td = (hctd_t *)p_wait_ed->p_curr_td;
+
+        if (p_td != NULL) {
+            if (ConditionCode == TD_CC_NOERROR) {
+                /* ErrorCount */
+                RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+
+                /* CurrentBufferPointer */
+                p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usbx_host_data_count[pipe];
+            } else {
+                /* ErrorCount */
+                RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+            }
+
+            /* DataToggle */
+            sqmon = usbx_host_get_sqmon(pipe);
+            RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T);
+            if (sqmon == 0) {
+                p_ed->headTD &= ~ED_TOGLE_CARRY;
+            } else {
+                p_ed->headTD |= ED_TOGLE_CARRY;
+            }
+
+            /* ConditionCode */
+            RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+            if (p_wait_ed == &ctl_ed) {
+                chk_split_trans_setting(&ctl_ed);
+            }
+            chk_genelal_td_done(p_wait_ed);
+
+            if (periodic != 0) {
+                if (chk_genelal_ed(p_wait_ed) != 0) {
+                    int_trans(p_wait_ed);
+                } else {
+                    p_wait_ed->trans_wait = 0;
+                    (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+                }
+            } else {
+                p_wait_ed->trans_wait = 0;
+                (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+            }
+        }
+    } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+        hcisotd_t *p_isotd = (hcisotd_t *)p_wait_ed->p_curr_td;
+        uint32_t  next_trans = 0;
+
+        if (p_isotd != NULL) {
+            usbx_host_stop_transfer(pipe);
+            p_usb_reg->HcFmNumber = ((p_isotd->control & 0x0000FFFF) + p_wait_ed->psw_idx) & 0x0000FFFF;
+
+            /* Size of packet */
+            p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe];
+
+            /* ConditionCode */
+            RZA_IO_RegWrite_32(&p_isotd->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+            RZA_IO_RegWrite_16(&p_isotd->offsetPSW[p_wait_ed->psw_idx],
+                               (uint16_t)ConditionCode, TD_PSW_SHFT_CC, TD_PSW_MSK_CC);
+
+            if (usbx_host_CheckAttach() != USB_HOST_ATTACH) {
+                p_ed->headTD  |= ED_HALTED;
+            }
+            if (p_wait_ed->psw_idx >= RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+                p_wait_ed->psw_idx = 0;
+                chk_iso_td_done(p_wait_ed);
+            } else {
+                p_wait_ed->psw_idx++;
+            }
+            if (chk_iso_ed(p_wait_ed) != 0) {
+                iso_trans(p_wait_ed);
+                next_trans = 1;
+            }
+            if (next_trans == 0) {
+                p_wait_ed->trans_wait = 0;
+                (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+            }
+        }
+#endif
+    }
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/ohci_wrapp_RZ_A1.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,60 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_H
+#define OHCI_WRAPP_RZ_A1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OHCI_REG_REVISION           (0x00)    /* HcRevision         */
+#define OHCI_REG_CONTROL            (0x04)    /* HcControl          */
+#define OHCI_REG_COMMANDSTATUS      (0x08)    /* HcCommandStatus    */
+#define OHCI_REG_INTERRUPTSTATUS    (0x0C)    /* HcInterruptStatus  */
+#define OHCI_REG_INTERRUPTENABLE    (0x10)    /* HcInterruptEnable  */
+#define OHCI_REG_INTERRUPTDISABLE   (0x14)    /* HcInterruptDisable */
+#define OHCI_REG_HCCA               (0x18)    /* HcHCCA             */
+#define OHCI_REG_PERIODCURRENTED    (0x1C)    /* HcPeriodCurrentED  */
+#define OHCI_REG_CONTROLHEADED      (0x20)    /* HcControlHeadED    */
+#define OHCI_REG_CONTROLCURRENTED   (0x24)    /* HcControlCurrentED */
+#define OHCI_REG_BULKHEADED         (0x28)    /* HcBulkHeadED       */
+#define OHCI_REG_BULKCURRENTED      (0x2C)    /* HcBulkCurrentED    */
+#define OHCI_REG_DONEHEADED         (0x30)    /* HcDoneHead         */
+#define OHCI_REG_FMINTERVAL         (0x34)    /* HcFmInterval       */
+#define OHCI_REG_FMREMAINING        (0x38)    /* HcFmRemaining      */
+#define OHCI_REG_FMNUMBER           (0x3C)    /* HcFmNumber         */
+#define OHCI_REG_PERIODICSTART      (0x40)    /* HcPeriodicStart    */
+#define OHCI_REG_LSTHRESHOLD        (0x44)    /* HcLSThreshold      */
+#define OHCI_REG_RHDESCRIPTORA      (0x48)    /* HcRhDescriptorA    */
+#define OHCI_REG_RHDESCRIPTORB      (0x4C)    /* HcRhDescriptorB    */
+#define OHCI_REG_RHSTATUS           (0x50)    /* HcRhStatus         */
+#define OHCI_REG_RHPORTSTATUS1      (0x54)    /* HcRhPortStatus1    */
+
+typedef void (usbisr_fnc_t)(void);
+
+extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc);
+extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs);
+extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data);
+extern void ohciwrapp_interrupt(uint32_t int_sense);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* OHCI_WRAPP_RZ_A1_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/ohci_wrapp_RZ_A1_local.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,49 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_LOCAL_H
+#define OHCI_WRAPP_RZ_A1_LOCAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ConditionCode */
+#define TD_CC_NOERROR             (0)
+#define TD_CC_CRC                 (1)
+#define TD_CC_BITSTUFFING         (2)
+#define TD_CC_DATATOGGLEMISMATCH  (3)
+#define TD_CC_STALL               (4)
+#define TD_CC_DEVICENOTRESPONDING (5)
+#define TD_CC_PIDCHECKFAILURE     (6)
+#define TD_CC_UNEXPECTEDPID       (7)
+#define TD_CC_DATAOVERRUN         (8)
+#define TD_CC_DATAUNDERRUN        (9)
+#define TD_CC_BUFFEROVERRUN       (12)
+#define TD_CC_BUFFERUNDERRUN      (13)
+#define TD_CC_NOT_ACCESSED_1      (14)
+#define TD_CC_NOT_ACCESSED_2      (15)
+
+extern void ohciwrapp_loc_Connect(uint32_t type);
+extern void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* OHCI_WRAPP_RZ_A1_LOCAL_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/ohci_wrapp_pipe.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,189 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/********************************************************************************************************/
+/* Endpoint Configuration Data Format                                                                   */
+/********************************************************************************************************/
+/*  LINE1: Pipe Window Select Register                                                                  */
+/*      CPU Access PIPE                 : USB_HOST_PIPE1 to USB_HOST_PIPE9      [ ### SET ### ]         */
+/*  LINE2: Pipe Configuration Register                                                                  */
+/*      Transfer Type                   : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Buffer Ready interrupt          : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Double Buffer Mode              : USB_HOST_DBLBON / USB_HOST_DBLBOFF    [ ### SET ### ]         */
+/*      Continuous Transmit:            : USB_HOST_CNTMDON / USB_HOST_CNTMDOFF  [ ### SET ### ]         */
+/*      Short NAK                       : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Transfer Direction              : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Endpoint Number                 : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*  LINE3: Pipe Buffer Configuration Register                                                           */
+/*      Buffer Size                     : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10)                  */
+/*                                                                              [ ### SET ### ]         */
+/*      Buffer Top Number               : (uint16_t)(x)                         [ ### SET ### ]         */
+/*  LINE4: Pipe Maxpacket Size Register                                                                 */
+/*      Max Packet Size                 : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*  LINE5: Pipe Cycle Configuration Register (0x6C)                                                     */
+/*      ISO Buffer Flush Mode           : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      ISO Interval Value              : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*  LINE6: use FIFO port                                                                                */
+/*                                      : USB_HOST_CUSE                         [ ### SET ### ]         */
+/*                                      : USB_HOST_D0USE / USB_HOST_D1USE                               */
+/*                                      : USB_HOST_D0DMA / USB_HOST_D0DMA                               */
+/********************************************************************************************************/
+
+/* Device Address 1 */
+USB_HOST_CFG_PIPETBL_t     usb_host_blk_ep_tbl1[ ] =
+{
+    {
+        USB_HOST_PIPE3,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D0USE
+    },
+
+    {
+        /* Pipe end */
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF
+    }
+};
+
+USB_HOST_CFG_PIPETBL_t     usb_host_int_ep_tbl1[ ] =
+{
+    {
+        USB_HOST_PIPE6,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE7,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE8,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE9,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        /* Pipe end */
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF
+    }
+};
+
+USB_HOST_CFG_PIPETBL_t     usb_host_iso_ep_tbl1[ ] =
+{
+    {
+        USB_HOST_PIPE1,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE2,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(76),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        /* Pipe end */
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF
+    }
+};
+
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/inc/usb0_host.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_H
+#define USB0_HOST_H
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t   g_usb0_host_bit_set[];
+extern uint32_t         g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t          *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t         g_usb0_host_PipeIgnore[];
+extern uint16_t         g_usb0_host_PipeTbl[];
+extern uint16_t         g_usb0_host_pipe_status[];
+extern uint32_t         g_usb0_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t   g_usb0_host_DmaInfo[];
+extern uint16_t         g_usb0_host_DmaPipe[];
+extern uint16_t         g_usb0_host_DmaBval[];
+extern uint16_t         g_usb0_host_DmaStatus[];
+
+extern uint16_t         g_usb0_host_driver_state;
+extern uint16_t         g_usb0_host_ConfigNum;
+extern uint16_t         g_usb0_host_CmdStage;
+extern uint16_t         g_usb0_host_bchg_flag;
+extern uint16_t         g_usb0_host_detach_flag;
+extern uint16_t         g_usb0_host_attach_flag;
+
+extern uint16_t         g_usb0_host_UsbAddress;
+extern uint16_t         g_usb0_host_setUsbAddress;
+extern uint16_t         g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t         g_usb0_host_UsbDeviceSpeed;
+extern uint16_t         g_usb0_host_SupportUsbDeviceSpeed;
+
+extern uint16_t         g_usb0_host_SavReq;
+extern uint16_t         g_usb0_host_SavVal;
+extern uint16_t         g_usb0_host_SavIndx;
+extern uint16_t         g_usb0_host_SavLen;
+
+extern uint16_t  g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void        usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void        usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t    usb0_host_is_hispeed(void);
+uint16_t    usb0_host_is_hispeed_enable(void);
+uint16_t    usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb0_host_write_buffer(uint16_t pipe);
+uint16_t    usb0_host_write_buffer_c(uint16_t pipe);
+uint16_t    usb0_host_write_buffer_d0(uint16_t pipe);
+uint16_t    usb0_host_write_buffer_d1(uint16_t pipe);
+void        usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb0_host_read_buffer(uint16_t pipe);
+uint16_t    usb0_host_read_buffer_c(uint16_t pipe);
+uint16_t    usb0_host_read_buffer_d0(uint16_t pipe);
+uint16_t    usb0_host_read_buffer_d1(uint16_t pipe);
+uint16_t    usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t    usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t    usb0_host_read_dma(uint16_t pipe);
+void        usb0_host_stop_transfer(uint16_t pipe);
+void        usb0_host_brdy_int(uint16_t status, uint16_t int_enb);
+void        usb0_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void        usb0_host_bemp_int(uint16_t status, uint16_t int_enb);
+void        usb0_host_setting_interrupt(uint8_t level);
+void        usb0_host_reset_module(uint16_t clockmode);
+uint16_t    usb0_host_get_buf_size(uint16_t pipe);
+uint16_t    usb0_host_get_mxps(uint16_t pipe);
+void        usb0_host_enable_brdy_int(uint16_t pipe);
+void        usb0_host_disable_brdy_int(uint16_t pipe);
+void        usb0_host_clear_brdy_sts(uint16_t pipe);
+void        usb0_host_enable_bemp_int(uint16_t pipe);
+void        usb0_host_disable_bemp_int(uint16_t pipe);
+void        usb0_host_clear_bemp_sts(uint16_t pipe);
+void        usb0_host_enable_nrdy_int(uint16_t pipe);
+void        usb0_host_disable_nrdy_int(uint16_t pipe);
+void        usb0_host_clear_nrdy_sts(uint16_t pipe);
+void        usb0_host_set_pid_buf(uint16_t pipe);
+void        usb0_host_set_pid_nak(uint16_t pipe);
+void        usb0_host_set_pid_stall(uint16_t pipe);
+void        usb0_host_clear_pid_stall(uint16_t pipe);
+uint16_t    usb0_host_get_pid(uint16_t pipe);
+void        usb0_host_set_sqclr(uint16_t pipe);
+void        usb0_host_set_sqset(uint16_t pipe);
+void        usb0_host_set_csclr(uint16_t pipe);
+void        usb0_host_aclrm(uint16_t pipe);
+void        usb0_host_set_aclrm(uint16_t pipe);
+void        usb0_host_clr_aclrm(uint16_t pipe);
+uint16_t    usb0_host_get_sqmon(uint16_t pipe);
+uint16_t    usb0_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void        usb0_host_init_pipe_status(void);
+int32_t     usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void        usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t    usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void        usb0_host_StatusStage(void);
+void        usb0_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void        usb0_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void        usb0_host_InitModule(void);
+uint16_t    usb0_host_CheckAttach(void);
+void        usb0_host_UsbDetach(void);
+void        usb0_host_UsbDetach2(void);
+void        usb0_host_UsbAttach(void);
+uint16_t    usb0_host_UsbBusReset(void);
+int32_t     usb0_host_UsbResume(void);
+int32_t     usb0_host_UsbSuspend(void);
+void        usb0_host_Enable_DetachINT(void);
+void        usb0_host_Disable_DetachINT(void);
+void        usb0_host_UsbStateManager(void);
+
+
+#endif /* USB0_HOST_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/inc/usb0_host_api.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_API_H
+#define USB0_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void        usb0_host_interrupt(uint32_t int_sense);
+void        usb0_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void        usb0_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t    usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t     usb0_api_host_enumeration(uint16_t devadr);
+int32_t     usb0_api_host_detach(void);
+int32_t     usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t     usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t     usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t     usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t    usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+int32_t     usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t     usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t     usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t     usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t    usb0_api_host_GetUsbDeviceState(void);
+
+void        usb0_api_host_elt_4_4(void);
+void        usb0_api_host_elt_4_5(void);
+void        usb0_api_host_elt_4_6(void);
+void        usb0_api_host_elt_4_7(void);
+void        usb0_api_host_elt_4_8(void);
+void        usb0_api_host_elt_4_9(void);
+void        usb0_api_host_elt_get_desc(void);
+
+void        usb0_host_EL_ModeInit(void);
+void        usb0_host_EL_SetUACT(void);
+void        usb0_host_EL_ClearUACT(void);
+void        usb0_host_EL_SetTESTMODE(uint16_t mode);
+void        usb0_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t    usb0_host_EL_GetINTSTS1(void);
+void        usb0_host_EL_UsbBusReset(void);
+void        usb0_host_EL_UsbAttach(void);
+void        usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb0_host_EL_StatusStage(void);
+void        usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t     usb0_host_EL_UsbSuspend(void);
+int32_t     usb0_host_EL_UsbResume(void);
+
+#if 0   /* prototype in devdrv_usb_host_api.h */
+uint16_t    Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t    Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void        Userdef_USB_usb0_host_attach(void);
+void        Userdef_USB_usb0_host_detach(void);
+void        Userdef_USB_usb0_host_delay_1ms(void);
+void        Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void        Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void        Userdef_USB_usb0_host_delay_500ns(void);
+void        Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t    Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t    Userdef_USB_usb0_host_stop_dma1(void);
+#endif
+
+#endif /* USB0_HOST_API_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/inc/usb0_host_dmacdrv.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_DMACDRV_H
+#define USB0_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+    uint32_t src_addr;      /* Transfer source address                */
+    uint32_t dst_addr;      /* Transfer destination address           */
+    uint32_t count;         /* Transfer byte count                    */
+    uint32_t src_size;      /* Transfer source data size              */
+    uint32_t dst_size;      /* Transfer destination data size         */
+    uint32_t saddr_dir;     /* Transfer source address direction      */
+    uint32_t daddr_dir;     /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE          (0)     /* Single transfer                   */
+#define DMAC_SAMPLE_CONTINUATION    (1)     /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER          (0)     /* Register mode */
+#define DMAC_MODE_LINK              (1)     /* Link mode     */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT           (0)     /* External request                   */
+#define DMAC_REQ_MODE_PERI          (1)     /* On-chip peripheral module request  */
+#define DMAC_REQ_MODE_SOFT          (2)     /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8           (0)     /* 8 bits    */
+#define DMAC_TRANS_SIZE_16          (1)     /* 16 bits   */
+#define DMAC_TRANS_SIZE_32          (2)     /* 32 bits   */
+#define DMAC_TRANS_SIZE_64          (3)     /* 64 bits   */
+#define DMAC_TRANS_SIZE_128         (4)     /* 128 bits  */
+#define DMAC_TRANS_SIZE_256         (5)     /* 256 bits  */
+#define DMAC_TRANS_SIZE_512         (6)     /* 512 bits  */
+#define DMAC_TRANS_SIZE_1024        (7)     /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC       (1)     /* Not increment */
+#define DMAC_TRANS_ADR_INC          (0)     /* Increment     */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL           (0)     /* Falling edge detection */
+#define DMAC_REQ_DET_RISE           (1)     /* Rising edge detection  */
+#define DMAC_REQ_DET_LOW            (2)     /* Low level detection    */
+#define DMAC_REQ_DET_HIGH           (3)     /* High level detection   */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC            (0)     /* DMAREQ is the source/ DMAACK is active when reading      */
+#define DMAC_REQ_DIR_DST            (1)     /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER            (0)     /* Header              */
+#define DMAC_DESC_SRC_ADDR          (1)     /* Source Address      */
+#define DMAC_DESC_DST_ADDR          (2)     /* Destination Address */
+#define DMAC_DESC_COUNT             (3)     /* Transaction Byte    */
+#define DMAC_DESC_CHCFG             (4)     /* Channel Confg       */
+#define DMAC_DESC_CHITVL            (5)     /* Channel Interval    */
+#define DMAC_DESC_CHEXT             (6)     /* Channel Extension   */
+#define DMAC_DESC_LINK_ADDR         (7)     /* Link Address        */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+    DMAC_REQ_USB0_DMA0_TX,      /* USB_0 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA0_RX,      /* USB_0 channel 0 receive FIFO full              */
+    DMAC_REQ_USB0_DMA1_TX,      /* USB_0 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA1_RX,      /* USB_0 channel 1 receive FIFO full              */
+    DMAC_REQ_USB1_DMA0_TX,      /* USB_1 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA0_RX,      /* USB_1 channel 0 receive FIFO full              */
+    DMAC_REQ_USB1_DMA1_TX,      /* USB_1 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA1_RX,      /* USB_1 channel 1 receive FIFO full              */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC1_Open(uint32_t req);
+void usb0_host_DMAC1_Close(uint32_t * remain);
+void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC2_Open(uint32_t req);
+void usb0_host_DMAC2_Close(uint32_t * remain);
+void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif  /* USB0_HOST_DMACDRV_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/common/usb0_host_dataio.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void     usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb0_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d1(uint16_t pipe);
+
+static void     usb0_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void     usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void     usb0_host_clear_transaction_counter(uint16_t pipe);
+static void     usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_start_send_transfer
+* Description  : Starts the USB data communication using pipe specified by the argument.
+* Arguments    : uint16_t  pipe    ; Pipe Number
+*              : uint32_t size     ; Data Size
+*              : uint8_t  *data    ; Data data Address
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t status;
+    uint16_t usefifo;
+    uint16_t mbw;
+
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    usb0_host_clear_bemp_sts(pipe);
+    usb0_host_clear_brdy_sts(pipe);
+    usb0_host_clear_nrdy_sts(pipe);
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+        case USB_HOST_D0FIFO_DMA:
+            usefifo = USB_HOST_D0USE;
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+        case USB_HOST_D1FIFO_DMA:
+            usefifo = USB_HOST_D1USE;
+        break;
+
+        default:
+            usefifo = USB_HOST_CUSE;
+        break;
+    };
+
+    usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+    usb0_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    status = usb0_host_write_buffer(pipe);
+
+    if (status != USB_HOST_FIFOERROR)
+    {
+        usb0_host_set_pid_buf(pipe);
+    }
+
+    return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer
+* Description  : Writes data in the buffer allocated in the pipe specified by
+*              : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer (uint16_t pipe)
+{
+    uint16_t status;
+    uint16_t usefifo;
+
+    g_usb0_host_PipeIgnore[pipe] = 0;
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            status = usb0_host_write_buffer_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            status = usb0_host_write_buffer_d1(pipe);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            status = usb0_host_write_dma_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            status = usb0_host_write_dma_d1(pipe);
+        break;
+
+        default:
+            status = usb0_host_write_buffer_c(pipe);
+        break;
+    };
+
+    switch (status)
+    {
+        case USB_HOST_WRITING:                      /* Continue of data write */
+            usb0_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+            usb0_host_enable_brdy_int(pipe);        /* Enable Ready Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                     /* End of data write */
+        case USB_HOST_WRITESHRT:                    /* End of data write */
+            usb0_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+
+            usb0_host_clear_nrdy_sts(pipe);
+            usb0_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+
+            /* for last transfer */
+            usb0_host_enable_bemp_int(pipe);        /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEDMA:                     /* DMA write */
+            usb0_host_clear_nrdy_sts(pipe);
+            usb0_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+        break;
+
+        case USB_HOST_FIFOERROR:                    /* FIFO access status */
+        default:
+            usb0_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+            usb0_host_disable_bemp_int(pipe);       /* Disable Empty Interrupt */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_c
+* Description  : Writes data in the buffer allocated in the pipe specified in
+*              : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+    }
+    else
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO,  mbw);
+    }
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb0_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb0_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb0_host_write_c_fifo(pipe, (uint16_t)count);
+
+    if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb0_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB200.CFIFOCTR,
+                                USB_CFIFOCTR_BVAL_SHIFT,
+                                USB_CFIFOCTR_BVAL) == 0)
+        {
+            USB200.CFIFOCTR = USB_HOST_BITBVAL;             /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb0_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb0_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count = g_usb0_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb0_host_write_d0_fifo(pipe, (uint16_t)count);
+
+    if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb0_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB200.D0FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb0_host_data_count[pipe] -= count;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb0_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb0_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb0_host_write_d1_fifo(pipe, (uint16_t)count);
+
+    if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb0_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB200.D1FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb0_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D0FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb0_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb0_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1;
+        }
+        else
+        {
+            g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0;
+        }
+
+        dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb0_host_data_count[pipe]    = 0;
+        g_usb0_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write  */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D1FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb0_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb0_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1;
+        }
+        else
+        {
+            g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0;
+        }
+
+        dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb0_host_data_count[pipe]    = 0;
+        g_usb0_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_transfer
+* Description  : Starts USB data reception using the pipe specified in the argument.
+*              : The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t usefifo;
+
+    usb0_host_clear_bemp_sts(pipe);
+    usb0_host_clear_brdy_sts(pipe);
+    usb0_host_clear_nrdy_sts(pipe);
+
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb0_host_start_receive_trns_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb0_host_start_receive_trns_d1(pipe, size, data);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            usb0_host_start_receive_dma_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            usb0_host_start_receive_dma_d1(pipe, size, data);
+        break;
+
+        default:
+            usb0_host_start_receive_trns_c(pipe, size, data);
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+*              : When storing data in the buffer allocated in the pipe specified in the
+*              : argument, BRDY interrupt is generated to read data
+*              : in the interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = size;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+    USB200.CFIFOCTR = USB_HOST_BITBCLR;
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    usb0_host_enable_nrdy_int(pipe);
+    usb0_host_enable_brdy_int(pipe);
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data in the
+*              : interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = size;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    usb0_host_enable_nrdy_int(pipe);
+    usb0_host_enable_brdy_int(pipe);
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = size;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    usb0_host_enable_nrdy_int(pipe);
+    usb0_host_enable_brdy_int(pipe);
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = 0;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb0_host_read_dma(pipe);
+
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d1
+* Description  : Read data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = 0;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb0_host_read_dma(pipe);
+
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Uses FIF0 set in the pipe definition table.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb0_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+    {
+        status = usb0_host_read_buffer_d0(pipe);
+    }
+    else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+    {
+        status = usb0_host_read_buffer_d1(pipe);
+    }
+    else
+    {
+        status = usb0_host_read_buffer_c(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                  /* Continue of data read */
+        break;
+
+        case USB_HOST_READEND:                                  /* End of data read */
+        case USB_HOST_READSHRT:                                 /* End of data read */
+            usb0_host_disable_brdy_int(pipe);
+            g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+            g_usb0_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READOVER:                                 /* buffer over */
+            if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+            {
+                USB200.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+            {
+                USB200.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else
+            {
+                USB200.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+            }
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+#else
+            g_usb0_host_pipe_status[pipe]   = USB_HOST_PIPE_ERROR;
+#endif
+            g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                      /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb0_host_data_count[pipe];
+    }
+    else if (g_usb0_host_data_count[pipe] == dtln)          /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB200.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+    }
+    else
+    {
+        usb0_host_read_c_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb0_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb0_host_data_count[pipe];
+    }
+    else if (g_usb0_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb0_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB200.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb0_host_read_d0_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb0_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d1
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb0_host_data_count[pipe];
+    }
+    else if (g_usb0_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) !=0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb0_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB200.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb0_host_read_d1_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb0_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_dma (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb0_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+    {
+        status = usb0_host_read_dma_d0(pipe);
+    }
+    else
+    {
+        status = usb0_host_read_dma_d1(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                      /* Continue of data read */
+        break;
+
+        case USB_HOST_READZERO:                                     /* End of data read */
+            usb0_host_disable_brdy_int(pipe);
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READEND:                                      /* End of data read */
+        case USB_HOST_READSHRT:                                     /* End of data read */
+            usb0_host_disable_brdy_int(pipe);
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+            }
+        break;
+
+        case USB_HOST_READOVER:                                     /* buffer over */
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+            }
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb0_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb0_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb0_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb0_host_data_count[pipe];
+        }
+        else if (g_usb0_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB200.D0FIFOCTR = USB_HOST_BITBCLR;            /* Clear B_CLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe;        /* not use in read operation */
+        g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0;           /* not use in read operation */
+
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb0_host_data_count[pipe]   -= count;
+        g_usb0_host_data_pointer[pipe] += count;
+        g_usb0_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by DMA transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb0_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb0_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb0_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb0_host_data_count[pipe];
+        }
+        else if (g_usb0_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB200.D1FIFOCTR = USB_HOST_BITBCLR;            /* Clear BCLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe;        /* not use in read operation */
+        g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0;           /* not use in read operation */
+
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb0_host_data_count[pipe]   -= count;
+        g_usb0_host_data_pointer[pipe] += count;
+        g_usb0_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_change_fifo_port
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument. After allocating FIF0, waits in the software
+*              : till the corresponding pipe becomes ready.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR         ; Error
+*              : Others            ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    usb0_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+    for (loop = 0; loop < 4; loop++)
+    {
+        switch (fifosel)
+        {
+            case USB_HOST_CUSE:
+                buffer = USB200.CFIFOCTR;
+            break;
+
+            case USB_HOST_D0USE:
+            case USB_HOST_D0DMA:
+                buffer = USB200.D0FIFOCTR;
+            break;
+
+            case USB_HOST_D1USE:
+            case USB_HOST_D1DMA:
+                buffer = USB200.D1FIFOCTR;
+            break;
+
+            default:
+                buffer = 0;
+            break;
+        }
+
+        if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+        {
+            return buffer;
+        }
+
+        loop2 = 25;
+
+        while (loop2-- > 0)
+        {
+            /* wait */
+        }
+    }
+
+    return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    g_usb0_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB200.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB200.D0FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB200.D1FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe2
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.(DFACC)
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+*              : uint16_t dfacc     ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+    uint16_t buffer;
+    uint32_t loop;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+    uint32_t dummy;
+#endif
+    volatile uint32_t loop2;
+
+    g_usb0_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB200.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB200.D0FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB200.D0FIFO.UINT32;
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB200.D1FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB200.D1FIFO.UINT32;
+                loop = dummy;                   // avoid warning.
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_c_fifo
+* Description  : Writes data in CFIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_c_fifo
+* Description  : Reads data from CFIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H];
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32;
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d0_fifo
+* Description  : Writes data in D0FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d0_fifo
+* Description  : Reads data from D0FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating DOFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  Pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H];
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32;
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d1_fifo
+* Description  : Writes data in D1FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d1_fifo
+* Description  : Reads data from D1FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H];
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32;
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_com_get_dmasize
+* Description  : Calculates access width of DMA transfer by the argument to
+                 return as the Return Value.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : DMA transfer size    : 0   8bit
+*              :                      : 1  16bit
+*              :                      : 2  32bit
+*******************************************************************************/
+static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+
+    if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+    {
+        /*  When transfer byte count is odd         */
+        /* or transfer data area is 8-bit alignment */
+        size = 0;           /* 8bit */
+    }
+    else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+    {
+        /* When the transfer byte count is multiples of 2 */
+        /* or the transfer data area is 16-bit alignment */
+        size = 1;           /* 16bit */
+    }
+    else
+    {
+        /* When the transfer byte count is multiples of 4 */
+        /* or the transfer data area is 32-bit alignment */
+        size = 2;           /* 32bit */
+    }
+
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mbw
+* Description  : Calculates access width of DMA to return the value set in MBW.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : FIFO transfer size   : USB_HOST_BITMBW_8    8bit
+*              :                      : USB_HOST_BITMBW_16  16bit
+*              :                      : USB_HOST_BITMBW_32  32bit
+*******************************************************************************/
+uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+    uint16_t mbw;
+
+    size = usb0_host_com_get_dmasize(trncount, dtptr);
+
+    if (size == 0)
+    {
+        /* 8bit */
+        mbw = USB_HOST_BITMBW_8;
+    }
+    else if (size == 1)
+    {
+        /* 16bit */
+        mbw = USB_HOST_BITMBW_16;
+    }
+    else
+    {
+        /* 32bit */
+        mbw = USB_HOST_BITMBW_32;
+    }
+
+    return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_transaction_counter
+* Description  : Sets transaction counter by the argument(PIPEnTRN).
+*              : Clears transaction before setting to enable transaction counter setting.
+* Arguments    : uint16_t pipe     ; Pipe number
+*              : uint32_t bsize    : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+    uint16_t mxps;
+    uint16_t cnt;
+
+    if (bsize == 0)
+    {
+        return;
+    }
+
+    mxps = usb0_host_get_mxps(pipe);            /* Max Packet Size */
+
+    if ((bsize % mxps) == 0)
+    {
+        cnt = (uint16_t)(bsize / mxps);
+    }
+    else
+    {
+        cnt = (uint16_t)((bsize / mxps) + 1);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE1TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE2TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE3TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE4TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE5TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE9TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_transaction_counter
+* Description  : Clears the transaction counter by the argument.
+*              : After executing this function, the transaction counter is invalid.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_transaction_counter (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_stop_transfer
+* Description  : Stops the USB transfer in the pipe specified by the argument.
+*              : After stopping the USB transfer, clears the buffer allocated in
+*              : the pipe.
+*              : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+*              : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+*              : in the corresponding pipe becomes invalid. Sequence bit is also
+*              : cleared.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_stop_transfer (uint16_t pipe)
+{
+    uint16_t usefifo;
+    uint32_t remain;
+
+    usb0_host_set_pid_nak(pipe);
+
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            remain = Userdef_USB_usb0_host_stop_dma0();
+            usb0_host_dma_stop_d0(pipe, remain);
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            remain = Userdef_USB_usb0_host_stop_dma1();
+            usb0_host_dma_stop_d1(pipe, remain);
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        default:
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.CFIFOCTR =  USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb0_host_disable_brdy_int(pipe);
+    usb0_host_disable_nrdy_int(pipe);
+    usb0_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+    usb0_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d0
+* Description  : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d1
+* Description  : Sets the DFACC setting value in D1FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/common/usb0_host_dma.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+/* #include "usb0_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb0_host_dmaint(uint16_t fifo);
+static void usb0_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb0_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d0
+* Description  : D0FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB200.D0FIFOCTR;
+            dtln   = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+            g_usb0_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d1
+* Description  : D1FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB200.D1FIFOCTR;
+            dtln   = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+            g_usb0_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d0fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+    usb0_host_dmaint(USB_HOST_D0FIFO);
+    g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d1fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+    usb0_host_dmaint(USB_HOST_D1FIFO);
+    g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint
+* Description  : This function is DMA transfer end interrupt
+* Arguments    : uint16_t fifo  ; fifo number
+*              :                ;  USB_HOST_D0FIFO
+*              :                ;  USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint (uint16_t fifo)
+{
+    uint16_t pipe;
+
+    pipe = g_usb0_host_DmaPipe[fifo];
+
+    if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+    {
+        usb0_host_dmaint_buf2fifo(pipe);
+    }
+    else
+    {
+        usb0_host_dmaint_fifo2buf(pipe);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_fifo2buf
+* Description  : Executes read completion from FIFO by DMAC.
+* Arguments    : uint16_t pipe       : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_fifo2buf (uint16_t pipe)
+{
+    uint32_t remain;
+    uint16_t useport;
+
+    if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+    {
+        useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+        if (useport == USB_HOST_D0FIFO_DMA)
+        {
+            remain = Userdef_USB_usb0_host_stop_dma0();
+            usb0_host_dma_stop_d0(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb0_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+        else
+        {
+            remain = Userdef_USB_usb0_host_stop_dma1();
+            usb0_host_dma_stop_d1(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb0_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_buf2fifo
+* Description  : Executes write completion in FIFO by DMAC.
+* Arguments    : uint16_t pipe     : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_buf2fifo (uint16_t pipe)
+{
+    uint16_t useport;
+    uint32_t remain;
+
+    useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    if (useport == USB_HOST_D0FIFO_DMA)
+    {
+        remain = Userdef_USB_usb0_host_stop_dma0();
+        usb0_host_dma_stop_d0(pipe, remain);
+
+        if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+    else
+    {
+        remain = Userdef_USB_usb0_host_stop_dma1();
+        usb0_host_dma_stop_d1(pipe, remain);
+
+        if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+
+    usb0_host_enable_bemp_int(pipe);
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/common/usb0_host_intrn.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_brdy_int
+* Description  : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+*              : According to the pipe that interrupt is generated in,
+*              : reads/writes buffer allocated in the pipe.
+*              : This function is executed in the BRDY interrupt handler.
+*              : This function clears BRDY interrupt status and BEMP interrupt
+*              : status.
+* Arguments    : uint16_t status       ; BRDYSTS Register Value
+*              : uint16_t int_enb      ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint32_t int_sense = 0;
+    uint16_t pipe;
+    uint16_t pipebit;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        pipebit = g_usb0_host_bit_set[pipe];
+
+        if ((status & pipebit) && (int_enb & pipebit))
+        {
+            USB200.BRDYSTS = (uint16_t)~pipebit;
+            USB200.BEMPSTS = (uint16_t)~pipebit;
+
+            if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb0_host_dma_interrupt_d0fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb0_host_read_dma(pipe);
+                    usb0_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb0_host_dma_interrupt_d1fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb0_host_read_dma(pipe);
+                    usb0_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else
+            {
+                if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+                {
+                    usb0_host_read_buffer(pipe);
+                }
+                else
+                {
+                    usb0_host_write_buffer(pipe);
+                }
+            }
+#if(1) /* ohci_wrapp */
+            switch (g_usb0_host_pipe_status[pipe])
+            {
+                case USB_HOST_PIPE_DONE:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+                break;
+                case USB_HOST_PIPE_NORES:
+                case USB_HOST_PIPE_STALL:
+                case USB_HOST_PIPE_ERROR:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+                break;
+                default:
+                    /* Do Nothing */
+                break;
+            }
+#endif
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_nrdy_int
+* Description  : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+*              : Checks NRDY interrupt cause by PID. When the cause if STALL,
+*              : regards the pipe state as STALL and ends the processing.
+*              : Then the cause is not STALL, increments the error count to
+*              : communicate again. When the error count is 3, determines
+*              : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+*              : This function is executed in the NRDY interrupt handler.
+*              : This function clears NRDY interrupt status.
+* Arguments    : uint16_t status       ; NRDYSTS Register Value
+*              : uint16_t int_enb      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB200.NRDYSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+        {
+            if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                    USB_SYSCFG_DCFM_SHIFT,
+                                    USB_SYSCFG_DCFM) == 1)
+            {
+                if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+                {
+                    pid = usb0_host_get_pid(pipe);
+
+                    if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+                    {
+                        g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+                    }
+                    else
+                    {
+#if(1) /* ohci_wrapp */
+                        g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+                        g_usb0_host_PipeIgnore[pipe]++;
+
+                        if (g_usb0_host_PipeIgnore[pipe] == 3)
+                        {
+                            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        }
+                        else
+                        {
+                            usb0_host_set_pid_buf(pipe);
+                        }
+#endif
+                    }
+                }
+            }
+            else
+            {
+                /* USB Function */
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_bemp_int
+* Description  : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments    : uint16_t status       ; BEMPSTS Register Value
+*              : uint16_t int_enb      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+    uint16_t inbuf;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB200.BEMPSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+        {
+            pid = usb0_host_get_pid(pipe);
+
+            if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+            {
+                g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+            }
+            else
+            {
+                inbuf = usb0_host_get_inbuf(pipe);
+
+                if (inbuf == 0)
+                {
+                    usb0_host_disable_bemp_int(pipe);
+                    usb0_host_set_pid_nak(pipe);
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+                }
+            }
+        }
+    }
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/common/usb0_host_lib.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1576 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "devdrv_intc.h"        /* INTC Driver Header   */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_brdy_int
+* Description  : Enables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_brdy_int (uint16_t pipe)
+{
+    /* enable brdy interrupt */
+    USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_brdy_int
+* Description  : Disables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_brdy_int (uint16_t pipe)
+{
+    /* disable brdy interrupt */
+    USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_brdy_sts
+* Description  : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_brdy_sts (uint16_t pipe)
+{
+    /* clear brdy status */
+    USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_bemp_int
+* Description  : Enables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_bemp_int (uint16_t pipe)
+{
+    /* enable bemp interrupt */
+    USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_bemp_int
+* Description  : Disables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_bemp_int (uint16_t pipe)
+{
+    /* disable bemp interrupt */
+    USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_bemp_sts
+* Description  : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_bemp_sts (uint16_t pipe)
+{
+    /* clear bemp status */
+    USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_nrdy_int
+* Description  : Enables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_nrdy_int (uint16_t pipe)
+{
+    /* enable nrdy interrupt */
+    USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_nrdy_int
+* Description  : Disables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_nrdy_int (uint16_t pipe)
+{
+    /* disable nrdy interrupt */
+    USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_nrdy_sts
+* Description  : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_nrdy_sts (uint16_t pipe)
+{
+    /* clear nrdy status */
+    USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed
+* Description  : Returns the result of USB reset hand shake (RHST) as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_HIGH_SPEED  ; Hi-Speed
+*              : USB_HOST_FULL_SPEED  ; Full-Speed
+*              : USB_HOST_LOW_SPEED   ; Low-Speed
+*              : USB_HOST_NON_SPEED   ; error
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed (void)
+{
+    uint16_t rhst;
+    uint16_t speed;
+
+    rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_HSMODE)
+    {
+        speed = USB_HOST_HIGH_SPEED;
+    }
+    else if (rhst == USB_HOST_FSMODE)
+    {
+        speed = USB_HOST_FULL_SPEED;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        speed = USB_HOST_LOW_SPEED;
+    }
+    else
+    {
+        speed = USB_HOST_NON_SPEED;
+    }
+
+    return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed_enable
+* Description  : Returns the USB High-Speed connection enabled status as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+*              : USB_HOST_NO  : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed_enable (void)
+{
+    uint16_t ret;
+
+    ret = USB_HOST_NO;
+
+    if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE) == 1)
+    {
+        ret = USB_HOST_YES;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_buf
+* Description  : Enables communicaqtion in the pipe specified by the argument
+*              : (BUF).
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_buf (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb0_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb0_host_set_pid_nak(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                USB_HOST_PID_BUF,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_nak
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+*              : When the pipe status was enabling communication (BUF) before
+*              : executing before executing this function, waits in the software
+*              : until the pipe becomes ready after setting disabled.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_nak (uint16_t pipe)
+{
+    uint16_t pid;
+    uint16_t pbusy;
+    uint32_t loop;
+
+    pid = usb0_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb0_host_set_pid_stall(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                USB_HOST_PID_NAK,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        for (loop = 0; loop < 200; loop++)
+        {
+            switch (pipe)
+            {
+                case USB_HOST_PIPE0:
+                    pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR,
+                                                USB_DCPCTR_PBUSY_SHIFT,
+                                                USB_DCPCTR_PBUSY);
+                break;
+
+                case USB_HOST_PIPE1:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE2:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE3:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE4:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE5:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE6:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE7:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE8:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE9:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                                USB_PIPEnCTR_9_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_9_PBUSY);
+                break;
+
+                default:
+                    pbusy = 1;
+                break;
+            }
+
+            if (pbusy == 0)
+            {
+                break;
+            }
+
+            Userdef_USB_usb0_host_delay_500ns();
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_stall
+* Description  : Disables communication (STALL) in the pipe specified by the
+*              : argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_stall (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb0_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+    else
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_pid_stall
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_pid_stall (uint16_t pipe)
+{
+    usb0_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_pid
+* Description  : Returns the pipe state specified by the argument.
+* Arguments    : uint16_t pipe          ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_host_get_pid (uint16_t pipe)
+{
+    uint16_t pid;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            pid = RZA_IO_RegRead_16(&USB200.DCPCTR,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+            pid = 0;
+        break;
+    }
+
+    return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_csclr
+* Description  : CSPLIT status clear setting of sprit transaction in specified
+*              : pipe is performed.
+*              : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+*              : in DCPCTR register are continuously changed (when the sequence
+*              : toggle bit of data PID is continuously changed over two or more pipes),
+*              : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+*              : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+*              : In addition, both bits should be operated after PID is set to NAK.
+*              : However, when it is set to the isochronous transfer as the transfer type
+*              : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_csclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                1,
+                                USB_DCPCTR_CSCLR_SHIFT,
+                                USB_DCPCTR_CSCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_CSCLR_SHIFT,
+                                USB_PIPEnCTR_9_CSCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqclr
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA0.
+* Arguments    : uint16_t pipe              ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQCLR_SHIFT,
+                                USB_DCPCTR_SQCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQCLR_SHIFT,
+                                USB_PIPEnCTR_9_SQCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqset
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA1.
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqset (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQSET_SHIFT,
+                                USB_DCPCTR_SQSET);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQSET_SHIFT,
+                                USB_PIPEnCTR_9_SQSET);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_sqmon
+* Description  : Toggle bit of specified pipe is obtained
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb0_host_get_sqmon (uint16_t pipe)
+{
+    uint16_t sqmon;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR,
+                                        USB_DCPCTR_SQMON_SHIFT,
+                                        USB_DCPCTR_SQMON);
+        break;
+
+        case USB_HOST_PIPE1:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE2:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE3:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE4:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE5:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE6:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE7:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE8:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE9:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                        USB_PIPEnCTR_9_SQMON_SHIFT,
+                                        USB_PIPEnCTR_9_SQMON);
+        break;
+
+        default:
+            sqmon = 0;
+        break;
+    }
+
+    return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_aclrm
+* Description  : The buffer of specified pipe is initialized
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_aclrm (uint16_t pipe)
+{
+    usb0_host_set_aclrm(pipe);
+    usb0_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clr_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clr_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                0,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_inbuf
+* Description  : Returns INBUFM of the pipe specified by the argument.
+* Arguments    : uint16_t pipe             ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb0_host_get_inbuf (uint16_t pipe)
+{
+    uint16_t inbuf;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE1:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE2:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE3:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE4:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE5:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE6:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE7:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE8:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE9:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                    USB_PIPEnCTR_9_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_9_INBUFM);
+        break;
+
+        default:
+            inbuf = 0;
+        break;
+    }
+
+    return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_setting_interrupt
+* Description  : Sets the USB module interrupt level.
+* Arguments    : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb0_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+    IRQn_Type d0fifo_dmaintid;
+    IRQn_Type d1fifo_dmaintid;
+
+    InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt);
+    GIC_SetPriority(USBI0_IRQn, level);
+    GIC_EnableIRQ(USBI0_IRQn);
+
+    d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+        GIC_SetPriority(d0fifo_dmaintid, level);
+        GIC_EnableIRQ(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+        GIC_SetPriority(d1fifo_dmaintid, level);
+        GIC_EnableIRQ(d1fifo_dmaintid);
+    }
+#else
+    uint16_t d0fifo_dmaintid;
+    uint16_t d1fifo_dmaintid;
+
+    R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt);
+    R_INTC_SetPriority(INTC_ID_USBI0, level);
+    R_INTC_Enable(INTC_ID_USBI0);
+
+    d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+        R_INTC_SetPriority(d0fifo_dmaintid, level);
+        R_INTC_Enable(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+        R_INTC_SetPriority(d1fifo_dmaintid, level);
+        R_INTC_Enable(d1fifo_dmaintid);
+    }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_reset_module
+* Description  : Initializes the USB module.
+*              : Enables providing clock to the USB module.
+*              : Sets USB bus wait register.
+* Arguments    : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+*              :                    ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb0_host_reset_module (uint16_t clockmode)
+{
+    if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                USB_SYSCFG_UPLLE_SHIFT,
+                                USB_SYSCFG_UPLLE) == 1)
+    {
+        if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+        {
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            USB200.SYSCFG0 = 0;
+            USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+            Userdef_USB_usb0_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            Userdef_USB_usb0_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            0,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        USB200.SYSCFG0 = 0;
+        USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+        Userdef_USB_usb0_host_delay_xms(1);
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            1,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+    }
+
+    USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_buf_size
+* Description  : Obtains pipe buffer size specified by the argument and
+*              : maximum packet size of the USB device in use.
+*              : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+*              : packet size of the USB device using the corresponding pipe.
+*              : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+*              : corresponding pipe is in continuous transfer mode,
+*              : obtains the buffer size allocated in the corresponcing pipe,
+*              : when incontinuous transfer, obtains maximum packet size.
+* Arguments    : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb0_host_get_buf_size (uint16_t pipe)
+{
+    uint16_t size;
+    uint16_t bufsize;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+        {
+            bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+            size    = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+        }
+        else
+        {
+            size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+        }
+    }
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mxps
+* Description  : Obtains maximum packet size of the USB device using the pipe
+*              : specified by the argument.
+* Arguments    : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb0_host_get_mxps (uint16_t pipe)
+{
+    uint16_t size;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+    }
+
+    return size;
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/host/usb0_host_controlrw.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlTransStart
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr ; device address
+*              : uint16_t Req   ; bmRequestType & bRequest
+*              : uint16_t Val   ; wValue
+*              : uint16_t Indx  ; wIndex
+*              : uint16_t Len   ; wLength
+*              : uint8_t  *Buf  ; Data buffer
+* Return Value : DEVDRV_SUCCESS     ;   SUCCESS
+*              : DEVDRV_ERROR       ;   ERROR
+*******************************************************************************/
+int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+                            uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+    if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+    {
+        RZA_IO_RegWrite_16(&USB200.SOFCFG,
+                            1,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]);
+
+    if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+    {
+        g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+        g_usb0_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                    /* Ignore count clear */
+        g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+        if (Len == 0)
+        {
+            g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA;              /* No-data Control */
+        }
+        else
+        {
+            if ((Req & 0x0080) != 0)
+            {
+                g_usb0_host_CmdStage |= USB_HOST_MODE_READ;             /* Control Read */
+            }
+            else
+            {
+                g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE;            /* Control Write */
+            }
+        }
+
+        g_usb0_host_SavReq  = Req;                                      /* save request */
+        g_usb0_host_SavVal  = Val;
+        g_usb0_host_SavIndx = Indx;
+        g_usb0_host_SavLen  = Len;
+    }
+    else
+    {
+        if ((g_usb0_host_SavReq  != Req)  || (g_usb0_host_SavVal != Val)
+         || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len))
+        {
+            return DEVDRV_ERROR;
+        }
+    }
+
+    switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+    {
+        /* --------------- SETUP STAGE --------------- */
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+            usb0_host_SetupStage(Req, Val, Indx, Len);
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE):                /* goto next stage */
+            g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0;                 /* Ignore count clear */
+            switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_READ:
+                    g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_NO_DATA:
+                    g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                break;
+
+                default:
+                break;
+            }
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+            if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+            }
+        break;
+
+        /* --------------- DATA STAGE --------------- */
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+            switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    usb0_host_CtrlWriteStart((uint32_t)Len, Buf);
+                break;
+
+                case USB_HOST_MODE_READ:
+                    usb0_host_CtrlReadStart((uint32_t)Len, Buf);
+                break;
+
+                default:
+                break;
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE):                         /* goto next stage */
+            g_usb0_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                        /* Ignore count clear */
+            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+            if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb0_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        /* --------------- STATUS STAGE --------------- */
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+            usb0_host_StatusStage();
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE):                       /* end of Control transfer */
+            usb0_host_set_pid_nak(USB_HOST_PIPE0);
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE;       /* exit DONE */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+            if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb0_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        default:
+        break;
+    }
+
+    if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+    {
+        RZA_IO_RegWrite_16(&USB200.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_SetupStage
+* Description  : Executes USB control transfer/set up stage.
+* Arguments    : uint16_t Req           ; bmRequestType & bRequest
+*              : uint16_t Val           ; wValue
+*              : uint16_t Indx          ; wIndex
+*              : uint16_t Len           ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN);  /* Status Clear */
+    USB200.USBREQ  = Req;
+    USB200.USBVAL  = Val;
+    USB200.USBINDX = Indx;
+    USB200.USBLENG = Len;
+    USB200.DCPCTR  = USB_HOST_BITSUREQ;                                 /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_StatusStage
+* Description  : Executes USB control transfer/status stage.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_StatusStage (void)
+{
+    uint8_t Buf1[16];
+
+    switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+    {
+        case USB_HOST_MODE_READ:
+            usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1);
+        break;
+
+        case USB_HOST_MODE_WRITE:
+            usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+        break;
+
+        case USB_HOST_MODE_NO_DATA:
+            usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlWriteStart
+* Description  : Executes USB control transfer/data stage(write).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+*              : USB_HOST_WRITEEND  ; End of data write (not null)
+*              : USB_HOST_WRITING   ; Continue of data write
+*              : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t EndFlag_K;
+    uint16_t mbw;
+
+    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb0_host_set_pid_nak(USB_HOST_PIPE0);                              /* Set NAK */
+    g_usb0_host_data_count[USB_HOST_PIPE0]   = Bsize;                   /* Transfer size set */
+    g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table;                   /* Transfer address set */
+
+    USB200.DCPCTR = USB_HOST_BITSQSET;                                  /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb0_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB200.DCPCFG,
+                        1,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+    USB200.CFIFOCTR = USB_HOST_BITBCLR;                                 /* Buffer Clear */
+
+    usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+    EndFlag_K   = usb0_host_write_buffer_c(USB_HOST_PIPE0);
+    /* Host Control sequence */
+    switch (EndFlag_K)
+    {
+        case USB_HOST_WRITESHRT:                                        /* End of data write */
+            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            usb0_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb0_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                                         /* End of data write (not null) */
+        case USB_HOST_WRITING:                                          /* Continue of data write */
+            usb0_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb0_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_FIFOERROR:                                        /* FIFO access error */
+        break;
+
+        default:
+        break;
+    }
+    usb0_host_set_pid_buf(USB_HOST_PIPE0);                              /* Set BUF */
+    return (EndFlag_K);                                                 /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlReadStart
+* Description  : Executes USB control transfer/data stage(read).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t mbw;
+
+    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb0_host_set_pid_nak(USB_HOST_PIPE0);                  /* Set NAK */
+    g_usb0_host_data_count[USB_HOST_PIPE0]   = Bsize;       /* Transfer size set */
+    g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table;       /* Transfer address set */
+
+    USB200.DCPCTR = USB_HOST_BITSQSET;                      /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb0_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB200.DCPCFG,
+                        0,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+    USB200.CFIFOCTR = USB_HOST_BITBCLR;                     /* Buffer Clear */
+
+    usb0_host_enable_nrdy_int(USB_HOST_PIPE0);              /* Error (NORES or STALL) */
+    usb0_host_enable_brdy_int(USB_HOST_PIPE0);              /* Ok */
+    usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+    usb0_host_set_pid_buf(USB_HOST_PIPE0);                  /* Set BUF */
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/host/usb0_host_drv_api.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,892 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_host_init
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint8_t int_level  : USB Module interrupt level
+*              : USBU16  mode       : USB_HOST_HIGH_SPEED
+*                                   : USB_HOST_FULL_SPEED
+*              : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+*              :  USB_HOST_ATTACH
+*              :  USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+    uint16_t         connect;
+    volatile uint8_t dummy_buf;
+
+    CPG.STBCR7 &= 0xfd;                         /*The clock of USB0 modules is permitted */
+    dummy_buf   = CPG.STBCR7;                   /* (Dummy read) */
+#if(1) /* mbed */
+    (void)dummy_buf;
+#endif
+
+    g_usb0_host_SupportUsbDeviceSpeed = mode;
+
+    usb0_host_setting_interrupt(int_level);
+    usb0_host_reset_module(clockmode);
+
+    g_usb0_host_bchg_flag   = USB_HOST_NO;
+    g_usb0_host_detach_flag = USB_HOST_NO;
+    g_usb0_host_attach_flag = USB_HOST_NO;
+
+    g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+    g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb0_host_InitModule();
+
+    connect = usb0_host_CheckAttach();
+
+    if (connect == USB_HOST_ATTACH)
+    {
+        g_usb0_host_attach_flag = USB_HOST_YES;
+    }
+    else
+    {
+        usb0_host_UsbDetach2();
+    }
+
+    return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_enumeration
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR       : device detach
+*              : DEVDRV_SUCCESS               : device enumeration success
+*              : DEVDRV_ERROR                 : device enumeration error
+*******************************************************************************/
+int32_t usb0_api_host_enumeration (uint16_t devadr)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    g_usb0_host_setUsbAddress = devadr;
+
+    while (1)
+    {
+        driver_sts = usb0_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = DEVDRV_USBH_DETACH_ERR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = DEVDRV_SUCCESS;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb0_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_detach
+* Description  : USB detach routine
+* Arguments    : none
+* Return Value : USB_HOST_DETACH : USB detach
+*              : USB_HOST_ATTACH : USB attach
+*              : DEVDRV_ERROR    : error
+*******************************************************************************/
+int32_t usb0_api_host_detach (void)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    while (1)
+    {
+        driver_sts = usb0_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = USB_HOST_DETACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = USB_HOST_ATTACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb0_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_in
+* Description  : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb0_host_start_receive_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;              /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb0_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb0_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb0_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb0_host_stop_transfer(Pipe);
+
+    g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_out
+* Description  : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb0_host_start_send_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;              /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb0_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb0_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb0_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb0_host_stop_transfer(Pipe);
+
+    g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_control_transfer
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Req          ; bmRequestType & bRequest
+*              : uint16_t Val          ; wValue
+*              : uint16_t Indx         ; wIndex
+*              : uint16_t Len          ; wLength
+*              : uint8_t  *buf         ; Buffer
+* Return Value : DEVDRV_SUCCESS           ; success
+*              : DEVDRV_USBH_DETACH_ERR   ; device detach
+*              : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+*              : DEVDRV_USBH_STALL        ; STALL
+*              : DEVDRV_ERROR             ; error
+*******************************************************************************/
+int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+                                                     uint16_t Len, uint8_t * Buf)
+{
+    int32_t  ret;
+
+    do
+    {
+        ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+        if (ret == DEVDRV_SUCCESS)
+        {
+            if (g_usb0_host_detach_flag == USB_HOST_YES)
+            {
+                break;
+            }
+
+            if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+                && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+            {
+                break;
+            }
+        }
+        else
+        {
+            return DEVDRV_ERROR;
+        }
+    } while (1);
+
+    if (g_usb0_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb0_host_pipe_status[USB_HOST_PIPE0])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_CTRL_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_set_endpoint
+* Description  : Sets end point on the information specified in the argument.
+* Arguments    : uint16_t                devadr           ; device address
+*              : uint8_t                *configdescriptor ; device configration descriptor
+*              : USB_HOST_CFG_PIPETBL_t *user_table       ; pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+    uint16_t                ret;
+    uint32_t                end_point;
+    uint32_t                offset;
+    uint32_t                totalLength;
+    USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+    /*  End Point Search */
+    end_point   = 0;
+    offset      = configdescriptor[0];
+    totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+    do
+    {
+        if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+        {
+            pipe_table = &user_table[end_point];
+
+            if (pipe_table->pipe_number == 0xffff)
+            {
+                break;
+            }
+
+            ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+            if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+            {
+                return DEVDRV_ERROR;
+            }
+
+            ++end_point;
+        }
+
+        /* Next End Point Search */
+        offset += configdescriptor[offset];
+
+    } while (offset < totalLength);
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+        user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+        user_table->pipe_max_pktsize  = 0;
+        user_table->pipe_cycle        = 0;
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint_pipe
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : uint16_t pipe_sel                  : Pipe Number
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+
+        if (user_table->pipe_number == pipe_sel)
+        {
+            user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+            user_table->pipe_max_pktsize  = 0;
+            user_table->pipe_cycle        = 0;
+            break;
+        }
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_api_host_SetEndpointTable
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : uint16_t devadr                    : device address
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+*              : uint8_t                *Table      : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN           ; IN endpoint
+*              : USB_HOST_DIR_H_OUT          ; OUT endpoint
+*              : USB_END_POINT_ERROR         ; error
+*******************************************************************************/
+uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+    uint16_t PipeCfg;
+    uint16_t PipeMaxp;
+    uint16_t pipe_number;
+    uint16_t ret;
+    uint16_t ret_flag = 0;                                          // avoid warning.
+
+    pipe_number = user_table->pipe_number;
+
+    if (Table[1] != USB_HOST_ENDPOINT_DESC)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    switch (Table[3] & USB_HOST_EP_TYPE)
+    {
+        case USB_HOST_EP_CNTRL:
+            ret_flag =  USB_END_POINT_ERROR;
+        break;
+
+        case USB_HOST_EP_ISO:
+            if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_ISO;
+        break;
+
+        case USB_HOST_EP_BULK:
+            if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_BULK;
+        break;
+
+        case USB_HOST_EP_INT:
+            if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_INTERRUPT;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Set pipe configuration table */
+    if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN)        /* IN(receive) */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= USB_HOST_DIR_H_IN;
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN);             /* Compulsory SHTNAK */
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+                break;
+
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef  __USB_DMA_BFRE_ENABLE__
+                    /* this routine cannnot be perfomred if read operation is executed in buffer size */
+                    PipeCfg |= USB_HOST_BFREON;
+#endif
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        ret = USB_HOST_PIPE_IN;
+    }
+    else                                                            /* OUT(send)    */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+        }
+        PipeCfg |= USB_HOST_DIR_H_OUT;
+        ret = USB_HOST_PIPE_OUT;
+    }
+
+    switch (user_table->fifo_port)
+    {
+        case USB_HOST_CUSE:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+        break;
+
+        case USB_HOST_D0USE:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+        break;
+
+        case USB_HOST_D1USE:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+        break;
+
+        case USB_HOST_D0DMA:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+        break;
+
+        case USB_HOST_D1DMA:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Endpoint number set              */
+    PipeCfg  |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+    g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+    /* Max packet size set              */
+    PipeMaxp  = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+    if (PipeMaxp == 0u)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    /* Set device address               */
+    PipeMaxp |= (uint16_t)(devadr << 12);
+
+    user_table->pipe_cfg         = PipeCfg;
+    user_table->pipe_max_pktsize = PipeMaxp;
+
+    usb0_host_resetEP(user_table);
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_resetEP
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+    uint16_t pipe;
+
+    /* Host pipe */
+    /* The pipe number of pipe definition table is obtained */
+    pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE);  /* Pipe Number */
+
+    /* FIFO port access pipe is set to initial value */
+    /* The connection with FIFO should be cut before setting the pipe */
+    if (RZA_IO_RegRead_16(&USB200.CFIFOSEL,
+                            USB_CFIFOSEL_CURPIPE_SHIFT,
+                            USB_CFIFOSEL_CURPIPE) == pipe)
+    {
+        usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb0_host_disable_brdy_int(pipe);
+    usb0_host_disable_nrdy_int(pipe);
+    usb0_host_disable_bemp_int(pipe);
+
+    /* Pipe to set is set to NAK */
+    usb0_host_set_pid_nak(pipe);
+
+    /* Pipe is set */
+    USB200.PIPESEL  = pipe;
+
+    USB200.PIPECFG  = tbl->pipe_cfg;
+    USB200.PIPEBUF  = tbl->pipe_buf;
+    USB200.PIPEMAXP = tbl->pipe_max_pktsize;
+    USB200.PIPEPERI = tbl->pipe_cycle;
+
+    g_usb0_host_pipecfg[pipe]  = tbl->pipe_cfg;
+    g_usb0_host_pipebuf[pipe]  = tbl->pipe_buf;
+    g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+    g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+    /* Sequence bit clear */
+    usb0_host_set_sqclr(pipe);
+
+    usb0_host_aclrm(pipe);
+    usb0_host_set_csclr(pipe);
+
+    /* Pipe window selection is set to unused */
+    USB200.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_data_count
+* Description  : Get g_usb0_host_data_count[pipe]
+* Arguments    : uint16_t pipe        ; Pipe Number
+*              : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS    ; success
+*              : DEVDRV_ERROR      ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+    if (pipe > USB_HOST_MAX_PIPE_NO)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    *data_count = g_usb0_host_PipeDataSize[pipe];
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/host/usb0_host_global.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb0_host_bit_set[16] =
+{
+    0x0001, 0x0002, 0x0004, 0x0008,
+    0x0010, 0x0020, 0x0040, 0x0080,
+    0x0100, 0x0200, 0x0400, 0x0800,
+    0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t  g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t  g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t  g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb0_host_DmaInfo[2];
+
+uint16_t  g_usb0_host_DmaPipe[2];
+uint16_t  g_usb0_host_DmaBval[2];
+uint16_t  g_usb0_host_DmaStatus[2];
+
+uint16_t  g_usb0_host_driver_state;
+uint16_t  g_usb0_host_ConfigNum;
+uint16_t  g_usb0_host_CmdStage;
+uint16_t  g_usb0_host_bchg_flag;
+uint16_t  g_usb0_host_detach_flag;
+uint16_t  g_usb0_host_attach_flag;
+
+uint16_t  g_usb0_host_UsbAddress;
+uint16_t  g_usb0_host_setUsbAddress;
+uint16_t  g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t  g_usb0_host_UsbDeviceSpeed;
+uint16_t  g_usb0_host_SupportUsbDeviceSpeed;
+
+uint16_t  g_usb0_host_SavReq;
+uint16_t  g_usb0_host_SavVal;
+uint16_t  g_usb0_host_SavIndx;
+uint16_t  g_usb0_host_SavLen;
+
+uint16_t  g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_init_pipe_status
+* Description  : Initialize pipe status.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_init_pipe_status (void)
+{
+    uint16_t loop;
+
+    g_usb0_host_ConfigNum = 0;
+
+    for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+    {
+        g_usb0_host_pipe_status[loop]   = USB_HOST_PIPE_IDLE;
+        g_usb0_host_PipeDataSize[loop]  = 0;
+
+        /* pipe configuration in usb0_host_resetEP() */
+        g_usb0_host_pipecfg[loop]  = 0;
+        g_usb0_host_pipebuf[loop]  = 0;
+        g_usb0_host_pipemaxp[loop] = 0;
+        g_usb0_host_pipeperi[loop] = 0;
+    }
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/host/usb0_host_usbint.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,508 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_interrupt1(void);
+static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt
+* Description  : Executes USB interrupt.
+*              : Register this function in the USB interrupt handler.
+*              : Set CFIF0 in the pipe set before the interrupt after executing
+*              : this function.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt (uint32_t int_sense)
+{
+    uint16_t savepipe1;
+    uint16_t savepipe2;
+    uint16_t buffer;
+
+    savepipe1 = USB200.CFIFOSEL;
+    savepipe2 = USB200.PIPESEL;
+    usb0_host_interrupt1();
+
+    /* Control transmission changes ISEL within interruption processing. */
+    /* For this reason, write return of ISEL cannot be performed. */
+    buffer = USB200.CFIFOSEL;
+    buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+    buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+    USB200.CFIFOSEL = buffer;
+    USB200.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt1
+* Description  : Execue the USB interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt1 (void)
+{
+    uint16_t intsts0;
+    uint16_t intsts1;
+    uint16_t intenb0;
+    uint16_t intenb1;
+    uint16_t brdysts;
+    uint16_t nrdysts;
+    uint16_t bempsts;
+    uint16_t brdyenb;
+    uint16_t nrdyenb;
+    uint16_t bempenb;
+    volatile uint16_t dumy_sts;
+
+    intsts0 = USB200.INTSTS0;
+    intsts1 = USB200.INTSTS1;
+    intenb0 = USB200.INTENB0;
+    intenb1 = USB200.INTENB1;
+
+    if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+    {
+            USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+            RZA_IO_RegWrite_16(&USB200.INTENB1,
+                                0,
+                                USB_INTENB1_BCHGE_SHIFT,
+                                USB_INTENB1_BCHGE);
+            g_usb0_host_bchg_flag = USB_HOST_YES;
+    }
+    else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+    }
+    else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+        g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+    }
+    else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+          && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+        RZA_IO_RegWrite_16(&USB200.INTENB1,
+                            0,
+                            USB_INTENB1_DTCHE_SHIFT,
+                            USB_INTENB1_DTCHE);
+        g_usb0_host_detach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb0_host_detach();
+
+        usb0_host_UsbDetach2();
+    }
+    else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+          && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+        RZA_IO_RegWrite_16(&USB200.INTENB1,
+                            0,
+                            USB_INTENB1_ATTCHE_SHIFT,
+                            USB_INTENB1_ATTCHE);
+        g_usb0_host_attach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb0_host_attach();
+
+        usb0_host_UsbAttach();
+    }
+    else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+    {
+        brdysts = USB200.BRDYSTS;
+        nrdysts = USB200.NRDYSTS;
+        bempsts = USB200.BEMPSTS;
+        brdyenb = USB200.BRDYENB;
+        nrdyenb = USB200.NRDYENB;
+        bempenb = USB200.BEMPENB;
+
+        if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+        {
+            usb0_host_BRDYInterrupt(brdysts, brdyenb);
+        }
+        else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+        {
+            usb0_host_BEMPInterrupt(bempsts, bempenb);
+        }
+        else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+        {
+            usb0_host_NRDYInterrupt(nrdysts, nrdyenb);
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Three dummy read for clearing interrupt requests */
+    dumy_sts = USB200.INTSTS0;
+    dumy_sts = USB200.INTSTS1;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BRDYInterrupt
+* Description  : Executes USB BRDY interrupt.
+* Arguments    : uint16_t Status   ; BRDYSTS Register Value
+*              : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+        switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+                usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+            break;
+
+            case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB200.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#else
+        switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_MODE_WRITE   | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+                usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+            break;
+
+            case (USB_HOST_MODE_READ   | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB200.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#endif
+    }
+    else
+    {
+        usb0_host_brdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB200.BRDYSTS;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_NRDYInterrupt
+* Description  : Executes USB NRDY interrupt.
+* Arguments    : uint16_t Status        ; NRDYSTS Register Value
+*              : uint16_t Int_enbl      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+        pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else if (pid  == USB_HOST_PID_NAK)
+        {
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        usb0_host_nrdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB200.NRDYSTS;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BEMPInterrupt
+* Description  : Executes USB BEMP interrupt.
+* Arguments    : uint16_t Status        ; BEMPSTS Register Value
+*              : uint16_t Int_enbl      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+        pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+#if(1) /* ohci_wrapp */
+            switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                    ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                break;
+
+                case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb0_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#else
+            switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb0_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#endif
+        }
+    }
+    else
+    {
+        usb0_host_bemp_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB200.BEMPSTS;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/host/usb0_host_usbsig.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_EnableINT_Module(void);
+static void usb0_host_Enable_AttachINT(void);
+static void usb0_host_Disable_AttachINT(void);
+static void usb0_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_InitModule
+* Description  : Initializes the USB module in USB host module.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_InitModule (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+
+    usb0_host_init_pipe_status();
+
+    RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DCFM_SHIFT,
+                        USB_SYSCFG_DCFM);       /* HOST mode */
+    RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DRPD_SHIFT,
+                        USB_SYSCFG_DRPD);       /* PORT0 D+, D- setting */
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                        1,
+                        USB_SYSCFG_USBE_SHIFT,
+                        USB_SYSCFG_USBE);
+
+    USB200.CFIFOSEL  = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB200.D0FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB200.D1FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CheckAttach
+* Description  : Returns the USB device connection state.
+* Arguments    : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+*              :          ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb0_host_CheckAttach (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+    uint16_t rhst;
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_UNDECID)
+    {
+        if (buf1 == USB_HOST_FS_JSTS)
+        {
+            if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+            {
+                RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                                    1,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            else
+            {
+                RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                                    0,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            return USB_HOST_ATTACH;
+        }
+        else if (buf1 == USB_HOST_LS_JSTS)
+        {
+            /* Low Speed Device */
+            RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                                0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE);
+            return USB_HOST_ATTACH;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+    {
+        return USB_HOST_ATTACH;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        return USB_HOST_ATTACH;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbAttach
+* Description  : Connects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbAttach (void)
+{
+    usb0_host_EnableINT_Module();
+    usb0_host_Disable_BchgINT();
+    usb0_host_Disable_AttachINT();
+    usb0_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach (void)
+{
+    uint16_t pipe;
+    uint16_t devadr;
+
+    g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+
+    /* Terminate all the pipes in which communications on port  */
+    /* are currently carried out                                */
+    for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+    {
+        if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+        {
+            if (pipe == USB_HOST_PIPE0)
+            {
+                devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+                                            USB_DCPMAXP_DEVSEL_SHIFT,
+                                            USB_DCPMAXP_DEVSEL);
+            }
+            else
+            {
+                devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+            }
+
+            if (devadr == g_usb0_host_UsbAddress)
+            {
+                usb0_host_stop_transfer(pipe);
+            }
+
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+        }
+    }
+
+    g_usb0_host_ConfigNum  = 0;
+    g_usb0_host_UsbAddress = 0;
+    g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb0_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach2
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach2 (void)
+{
+    usb0_host_Disable_DetachINT();
+    usb0_host_Disable_BchgINT();
+    usb0_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbBusReset
+* Description  : Issues the USB bus reset signal.
+* Arguments    : none
+* Return Value : uint16_t               ; RHST
+*******************************************************************************/
+uint16_t usb0_host_UsbBusReset (void)
+{
+    uint16_t buffer;
+    uint16_t loop;
+
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_USBRST_SHIFT,
+                        USB_DVSTCTR0_USBRST);
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb0_host_delay_xms(50);
+
+    buffer  = USB200.DVSTCTR0;
+    buffer &= (uint16_t)(~(USB_HOST_BITRST));
+    buffer |= USB_HOST_BITUACT;
+    USB200.DVSTCTR0 = buffer;
+
+    Userdef_USB_usb0_host_delay_xms(20);
+
+    for (loop = 0, buffer = USB_HOST_HSPROC;  loop < 3; ++loop)
+    {
+        buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+                                    USB_DVSTCTR0_RHST_SHIFT,
+                                    USB_DVSTCTR0_RHST);
+        if (buffer == USB_HOST_HSPROC)
+        {
+            Userdef_USB_usb0_host_delay_xms(10);
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbResume
+* Description  : Issues the USB resume signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS
+*              :                    ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb0_host_UsbResume (void)
+{
+    uint16_t buf;
+
+    if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+    {
+        /* not SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_RESUME_SHIFT,
+                        USB_DVSTCTR0_RESUME);
+    Userdef_USB_usb0_host_delay_xms(20);
+
+    buf  = USB200.DVSTCTR0;
+    buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+    buf |= USB_HOST_BITUACT;
+    USB200.DVSTCTR0 = buf;
+
+    g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbSuspend
+* Description  : Issues the USB suspend signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS   :not SUSPEND
+*              :                    ; DEVDRV_ERROR     :SUSPEND
+*******************************************************************************/
+int32_t usb0_host_UsbSuspend (void)
+{
+    uint16_t buf;
+
+    if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+    {
+        /* SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb0_host_delay_xms(5);
+
+    buf = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+    if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+    {
+        usb0_host_UsbDetach();
+    }
+    else
+    {
+        g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_DetachINT
+* Description  : Enables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_DetachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        1,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_DetachINT
+* Description  : Disables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_DetachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_AttachINT
+* Description  : Enables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_AttachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        1,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_AttachINT
+* Description  : Disables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_AttachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_BchgINT
+* Description  : Disables the USB bus change detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_BchgINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_devadd
+* Description  : DEVADDn register is set by specified value
+* Arguments    : uint16_t addr             : Device address
+*              : uint16_t *devadd          : Set value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB200.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB200.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB200.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB200.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB200.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB200.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB200.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB200.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB200.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB200.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB200.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_devadd
+* Description  : DEVADDn register is obtained
+* Arguments    : uint16_t addr      : Device address
+*              : uint16_t *devadd   : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB200.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB200.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB200.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB200.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB200.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB200.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB200.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB200.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB200.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB200.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB200.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *devadd = *ptr;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_EnableINT_Module
+* Description  : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+*              : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_EnableINT_Module (void)
+{
+    uint16_t buf;
+
+    buf  = USB200.INTENB0;
+    buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+    USB200.INTENB0 = buf;
+
+    buf  = USB200.INTENB1;
+    buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+    USB200.INTENB1 = buf;
+
+    usb0_host_enable_nrdy_int(USB_HOST_PIPE0);
+    usb0_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/userdef/usb0_host_dmacdrv.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,704 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb0_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE   (255)       /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+    DMAC_REQ_MID,
+    DMAC_REQ_RID,
+    DMAC_REQ_AM,
+    DMAC_REQ_LVL,
+    DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
+{
+  /* MID,RID, AM,LVL,REQD */
+    { 32,  3,  2,  1,  1},      /* USB_0 channel 0 transmit FIFO empty */
+    { 32,  3,  2,  1,  0},      /* USB_0 channel 0 receive FIFO full   */
+    { 33,  3,  2,  1,  1},      /* USB_0 channel 1 transmit FIFO empty */
+    { 33,  3,  2,  1,  0},      /* USB_0 channel 1 receive FIFO full   */
+    { 34,  3,  2,  1,  1},      /* USB_1 channel 0 transmit FIFO empty */
+    { 34,  3,  2,  1,  0},      /* USB_1 channel 0 receive FIFO full   */
+    { 35,  3,  2,  1,  1},      /* USB_1 channel 1 transmit FIFO empty */
+    { 35,  3,  2,  1,  0},      /* USB_1 channel 1 receive FIFO full   */
+};
+
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 1.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 1 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC1.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC1.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC1.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC1_CHCFG_n_DAD_SHIFT,
+                            DMAC1_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC1_CHCFG_n_SAD_SHIFT,
+                            DMAC1_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC1_CHCFG_n_DDS_SHIFT,
+                            DMAC1_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC1_CHCFG_n_SDS_SHIFT,
+                            DMAC1_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_DMS_SHIFT,
+                            DMAC1_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_RSEL_SHIFT,
+                            DMAC1_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_SBE_SHIFT,
+                            DMAC1_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_DEM_SHIFT,
+                            DMAC1_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                1,
+                                DMAC1_CHCFG_n_REN_SHIFT,
+                                DMAC1_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                1,
+                                DMAC1_CHCFG_n_RSW_SHIFT,
+                                DMAC1_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                0,
+                                DMAC1_CHCFG_n_REN_SHIFT,
+                                DMAC1_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                0,
+                                DMAC1_CHCFG_n_RSW_SHIFT,
+                                DMAC1_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_TM_SHIFT,
+                            DMAC1_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            1,
+                            DMAC1_CHCFG_n_SEL_SHIFT,
+                            DMAC1_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            1,
+                            DMAC1_CHCFG_n_HIEN_SHIFT,
+                            DMAC1_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_LOEN_SHIFT,
+                            DMAC1_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC1_CHCFG_n_AM_SHIFT,
+                            DMAC1_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC1_CHCFG_n_LVL_SHIFT,
+                            DMAC1_CHCFG_n_LVL);
+        if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC1_CHCFG_n_REQD_SHIFT,
+                                DMAC1_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                req_direction,
+                                DMAC1_CHCFG_n_REQD_SHIFT,
+                                DMAC1_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC01.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC01_DMARS_CH1_RID_SHIFT,
+                            DMAC01_DMARS_CH1_RID);
+        RZA_IO_RegWrite_32(&DMAC01.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC01_DMARS_CH1_MID_SHIFT,
+                            DMAC01_DMARS_CH1_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Open
+* Description  : Enables DMAC channel 1 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC1_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_EN_SHIFT,
+                                DMAC1_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_TACT_SHIFT,
+                                DMAC1_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                            1,
+                            DMAC1_CHCTRL_n_SWRST_SHIFT,
+                            DMAC1_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
+                                DMAC1_CHCTRL_n_SWRST_SHIFT,
+                                DMAC1_CHCTRL_n_SWRST);
+#if(1) /* mbed */
+        (void)dummy;
+#endif
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                            1,
+                            DMAC1_CHCTRL_n_SETEN_SHIFT,
+                            DMAC1_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                                1,
+                                DMAC1_CHCTRL_n_STG_SHIFT,
+                                DMAC1_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Close
+* Description  : Aborts DMAC channel 1 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                        1,
+                        DMAC1_CHCTRL_n_CLREN_SHIFT,
+                        DMAC1_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_TACT_SHIFT,
+                                DMAC1_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_EN_SHIFT,
+                                DMAC1_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC1.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 1 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 1 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_SR_SHIFT,
+                                DMAC1_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC1.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC1.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC1.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC1.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC1.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC1.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 2.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 2 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC2.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC2.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC2.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC2_CHCFG_n_DAD_SHIFT,
+                            DMAC2_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC2_CHCFG_n_SAD_SHIFT,
+                            DMAC2_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC2_CHCFG_n_DDS_SHIFT,
+                            DMAC2_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC2_CHCFG_n_SDS_SHIFT,
+                            DMAC2_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_DMS_SHIFT,
+                            DMAC2_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_RSEL_SHIFT,
+                            DMAC2_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_SBE_SHIFT,
+                            DMAC2_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_DEM_SHIFT,
+                            DMAC2_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                1,
+                                DMAC2_CHCFG_n_REN_SHIFT,
+                                DMAC2_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                1,
+                                DMAC2_CHCFG_n_RSW_SHIFT,
+                                DMAC2_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                0,
+                                DMAC2_CHCFG_n_REN_SHIFT,
+                                DMAC2_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                0,
+                                DMAC2_CHCFG_n_RSW_SHIFT,
+                                DMAC2_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_TM_SHIFT,
+                            DMAC2_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            2,
+                            DMAC2_CHCFG_n_SEL_SHIFT,
+                            DMAC2_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            1,
+                            DMAC2_CHCFG_n_HIEN_SHIFT,
+                            DMAC2_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_LOEN_SHIFT,
+                            DMAC2_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC2_CHCFG_n_AM_SHIFT,
+                            DMAC2_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC2_CHCFG_n_LVL_SHIFT,
+                            DMAC2_CHCFG_n_LVL);
+        if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC2_CHCFG_n_REQD_SHIFT,
+                                DMAC2_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                req_direction,
+                                DMAC2_CHCFG_n_REQD_SHIFT,
+                                DMAC2_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC23_DMARS_CH2_RID_SHIFT,
+                            DMAC23_DMARS_CH2_RID);
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC23_DMARS_CH2_MID_SHIFT,
+                            DMAC23_DMARS_CH2_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Open
+* Description  : Enables DMAC channel 2 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC2_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_EN_SHIFT,
+                                DMAC2_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_TACT_SHIFT,
+                                DMAC2_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                            1,
+                            DMAC2_CHCTRL_n_SWRST_SHIFT,
+                            DMAC2_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
+                                DMAC2_CHCTRL_n_SWRST_SHIFT,
+                                DMAC2_CHCTRL_n_SWRST);
+#if(1) /* mbed */
+        (void)dummy;
+#endif
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                            1,
+                            DMAC2_CHCTRL_n_SETEN_SHIFT,
+                            DMAC2_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                                1,
+                                DMAC2_CHCTRL_n_STG_SHIFT,
+                                DMAC2_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Close
+* Description  : Aborts DMAC channel 2 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                        1,
+                        DMAC2_CHCTRL_n_CLREN_SHIFT,
+                        DMAC2_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_TACT_SHIFT,
+                                DMAC2_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_EN_SHIFT,
+                                DMAC2_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC2.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 2 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 2 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_SR_SHIFT,
+                                DMAC2_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC2.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC2.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC2.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC2.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC2.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC2.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb0/src/userdef/usb0_host_userdef.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,791 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb0_host.h"
+#include "devdrv_intc.h"        /* INTC Driver Header   */
+#include "usb0_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb0_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid
+* Description  : get D0FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid
+* Description  : get D1FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_attach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_attach (void)
+{
+//    printf("\n");
+//    printf("channel 0 attach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_detach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_detach (void)
+{
+//    printf("\n");
+//    printf("channel 0 detach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_1ms
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_1ms (void)
+{
+    osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_xms
+* Description  : Wait for the software in the period of time specified by the
+*              : argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_xms (uint32_t msec)
+{
+    osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_10us (uint32_t usec)
+{
+#if(1) /* ohci_wrapp */
+    volatile uint32_t i;
+#else
+    volatile int i;
+#endif
+
+    /* Wait 10us (Please change for your MCU) */
+    for (i = 0; i < usec; ++i)
+    {
+        Userdef_USB_usb0_host_delay_10us_2();
+    }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us_2
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb0_host_delay_10us_2 (void)
+{
+    volatile int i;
+    volatile unsigned long tmp;
+
+    /* Wait 1us (Please change for your MCU) */
+    for (i = 0; i < 14; ++i)
+    {
+        tmp = DUMMY_ACCESS;
+    }
+#if(1) /* mbed */
+    (void)tmp;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_500ns
+* Description  : Wait for software for 500ns.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_500ns (void)
+{
+#if(1) /* ohci_wrapp */
+#else
+    volatile int i;
+#endif
+    volatile unsigned long tmp;
+
+    /* Wait 500ns (Please change for your MCU) */
+    /* Wait 500ns I clock 266MHz */
+    tmp = DUMMY_ACCESS;
+#if(1) /* mbed */
+    (void)tmp;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_start_dma
+* Description  : Enables DMA transfer on the information specified by the argument.
+*              : Set DMAC register by this function to enable DMA transfer.
+*              : After executing this function, USB module is set to start DMA
+*              : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments    : USB_HOST_DMA_t *dma   : DMA parameter
+*              :  typedef struct{
+*              :      uint32_t fifo;    FIFO for using
+*              :      uint32_t buffer;  Start address of transfer source/destination
+*              :      uint32_t bytes;   Transfer size(Byte)
+*              :      uint32_t dir;     Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+*              :      uint32_t size;    DMA transfer size
+*              :   } USB_HOST_DMA_t;
+*              : uint16_t dfacc ; 0 : cycle steal mode
+*              :                  1 : 16byte continuous mode
+*              :                  2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+    uint32_t trncount;
+    uint32_t src;
+    uint32_t dst;
+    uint32_t size;
+    uint32_t dir;
+#ifdef CACHE_WRITEBACK
+    uint32_t ptr;
+#endif
+
+    trncount = dma->bytes;
+    dir      = dma->dir;
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        /* DxFIFO determination */
+        dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            src = (uint32_t)(&USB200.D0FIFO.UINT32);
+        }
+        else
+        {
+            src = (uint32_t)(&USB200.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            src += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB200.D0FIFO.UINT32);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB200.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            src += 3;       /* byte access  */
+        }
+#endif
+    }
+    else
+    {
+        /* DxFIFO determination */
+        src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+        }
+        else
+        {
+            dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            dst += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            dst += 3;       /* byte access  */
+        }
+#endif
+    }
+
+#ifdef CACHE_WRITEBACK
+    ptr = (uint32_t)dma->buffer;
+    if ((ptr & 0x20000000ul) == 0)
+    {
+        io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+    }
+#endif
+
+    if (dma->fifo == USB_HOST_D0FIFO_DMA)
+    {
+        usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+    else
+    {
+        usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac0
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t         request_factor = 0;
+    int32_t          ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor       = DMAC_REQ_USB0_DMA0_RX;   /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor       = DMAC_REQ_USB0_DMA0_TX;   /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC1 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac1
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t request_factor = 0;
+    int32_t  ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor =DMAC_REQ_USB0_DMA1_RX;          /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor =DMAC_REQ_USB0_DMA1_TX;          /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC2 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma0
+* Description  : Disables DMA transfer.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+* Notice       : This function should be executed to DMAC executed at the time
+*              : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma0 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb0_host_DMAC1_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma1
+* Description  : Disables DMA transfer.
+*              : This function should be executed to DMAC executed at the time
+*              : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma1 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb0_host_DMAC2_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_notice
+* Description  : Notice of USER
+* Arguments    : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_notice (const char * format)
+{
+//    printf(format);
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_user_rdy
+* Description  : This function notify a user and wait for trigger
+* Arguments    : const char *format
+*              :    uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data)
+{
+//    printf(format, data);
+    getchar();
+
+    return;
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/inc/usb1_host.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_H
+#define USB1_HOST_H
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t   g_usb1_host_bit_set[];
+extern uint32_t         g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t          *g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t         g_usb1_host_PipeIgnore[];
+extern uint16_t         g_usb1_host_PipeTbl[];
+extern uint16_t         g_usb1_host_pipe_status[];
+extern uint32_t         g_usb1_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t   g_usb1_host_DmaInfo[];
+extern uint16_t         g_usb1_host_DmaPipe[];
+extern uint16_t         g_usb1_host_DmaBval[];
+extern uint16_t         g_usb1_host_DmaStatus[];
+
+extern uint16_t         g_usb1_host_driver_state;
+extern uint16_t         g_usb1_host_ConfigNum;
+extern uint16_t         g_usb1_host_CmdStage;
+extern uint16_t         g_usb1_host_bchg_flag;
+extern uint16_t         g_usb1_host_detach_flag;
+extern uint16_t         g_usb1_host_attach_flag;
+
+extern uint16_t         g_usb1_host_UsbAddress;
+extern uint16_t         g_usb1_host_setUsbAddress;
+extern uint16_t         g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t         g_usb1_host_UsbDeviceSpeed;
+extern uint16_t         g_usb1_host_SupportUsbDeviceSpeed;
+
+extern uint16_t         g_usb1_host_SavReq;
+extern uint16_t         g_usb1_host_SavVal;
+extern uint16_t         g_usb1_host_SavIndx;
+extern uint16_t         g_usb1_host_SavLen;
+
+extern uint16_t  g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void        usb1_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void        usb1_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t    usb1_host_is_hispeed(void);
+uint16_t    usb1_host_is_hispeed_enable(void);
+uint16_t    usb1_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb1_host_write_buffer(uint16_t pipe);
+uint16_t    usb1_host_write_buffer_c(uint16_t pipe);
+uint16_t    usb1_host_write_buffer_d0(uint16_t pipe);
+uint16_t    usb1_host_write_buffer_d1(uint16_t pipe);
+void        usb1_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb1_host_read_buffer(uint16_t pipe);
+uint16_t    usb1_host_read_buffer_c(uint16_t pipe);
+uint16_t    usb1_host_read_buffer_d0(uint16_t pipe);
+uint16_t    usb1_host_read_buffer_d1(uint16_t pipe);
+uint16_t    usb1_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb1_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb1_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t    usb1_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t    usb1_host_read_dma(uint16_t pipe);
+void        usb1_host_stop_transfer(uint16_t pipe);
+void        usb1_host_brdy_int(uint16_t status, uint16_t int_enb);
+void        usb1_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void        usb1_host_bemp_int(uint16_t status, uint16_t int_enb);
+void        usb1_host_setting_interrupt(uint8_t level);
+void        usb1_host_reset_module(uint16_t clockmode);
+uint16_t    usb1_host_get_buf_size(uint16_t pipe);
+uint16_t    usb1_host_get_mxps(uint16_t pipe);
+void        usb1_host_enable_brdy_int(uint16_t pipe);
+void        usb1_host_disable_brdy_int(uint16_t pipe);
+void        usb1_host_clear_brdy_sts(uint16_t pipe);
+void        usb1_host_enable_bemp_int(uint16_t pipe);
+void        usb1_host_disable_bemp_int(uint16_t pipe);
+void        usb1_host_clear_bemp_sts(uint16_t pipe);
+void        usb1_host_enable_nrdy_int(uint16_t pipe);
+void        usb1_host_disable_nrdy_int(uint16_t pipe);
+void        usb1_host_clear_nrdy_sts(uint16_t pipe);
+void        usb1_host_set_pid_buf(uint16_t pipe);
+void        usb1_host_set_pid_nak(uint16_t pipe);
+void        usb1_host_set_pid_stall(uint16_t pipe);
+void        usb1_host_clear_pid_stall(uint16_t pipe);
+uint16_t    usb1_host_get_pid(uint16_t pipe);
+void        usb1_host_set_sqclr(uint16_t pipe);
+void        usb1_host_set_sqset(uint16_t pipe);
+void        usb1_host_set_csclr(uint16_t pipe);
+void        usb1_host_aclrm(uint16_t pipe);
+void        usb1_host_set_aclrm(uint16_t pipe);
+void        usb1_host_clr_aclrm(uint16_t pipe);
+uint16_t    usb1_host_get_sqmon(uint16_t pipe);
+uint16_t    usb1_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void        usb1_host_init_pipe_status(void);
+int32_t     usb1_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void        usb1_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb1_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t    usb1_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void        usb1_host_StatusStage(void);
+void        usb1_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void        usb1_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void        usb1_host_InitModule(void);
+uint16_t    usb1_host_CheckAttach(void);
+void        usb1_host_UsbDetach(void);
+void        usb1_host_UsbDetach2(void);
+void        usb1_host_UsbAttach(void);
+uint16_t    usb1_host_UsbBusReset(void);
+int32_t     usb1_host_UsbResume(void);
+int32_t     usb1_host_UsbSuspend(void);
+void        usb1_host_Enable_DetachINT(void);
+void        usb1_host_Disable_DetachINT(void);
+void        usb1_host_UsbStateManager(void);
+
+
+#endif /* USB1_HOST_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/inc/usb1_host_api.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_API_H
+#define USB1_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void        usb1_host_interrupt(uint32_t int_sense);
+void        usb1_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void        usb1_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t    usb1_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t     usb1_api_host_enumeration(uint16_t devadr);
+int32_t     usb1_api_host_detach(void);
+int32_t     usb1_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb1_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb1_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t     usb1_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t     usb1_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t     usb1_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t    usb1_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *Table);
+int32_t     usb1_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t     usb1_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb1_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb1_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t     usb1_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t     usb1_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t    usb1_api_host_GetUsbDeviceState(void);
+
+void        usb1_api_host_elt_4_4(void);
+void        usb1_api_host_elt_4_5(void);
+void        usb1_api_host_elt_4_6(void);
+void        usb1_api_host_elt_4_7(void);
+void        usb1_api_host_elt_4_8(void);
+void        usb1_api_host_elt_4_9(void);
+void        usb1_api_host_elt_get_desc(void);
+
+void        usb1_host_EL_ModeInit(void);
+void        usb1_host_EL_SetUACT(void);
+void        usb1_host_EL_ClearUACT(void);
+void        usb1_host_EL_SetTESTMODE(uint16_t mode);
+void        usb1_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t    usb1_host_EL_GetINTSTS1(void);
+void        usb1_host_EL_UsbBusReset(void);
+void        usb1_host_EL_UsbAttach(void);
+void        usb1_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb1_host_EL_StatusStage(void);
+void        usb1_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t     usb1_host_EL_UsbSuspend(void);
+int32_t     usb1_host_EL_UsbResume(void);
+
+#if 0   /* prototype in devdrv_usb_host_api.h */
+uint16_t    Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t    Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void        Userdef_USB_usb1_host_attach(void);
+void        Userdef_USB_usb1_host_detach(void);
+void        Userdef_USB_usb1_host_delay_1ms(void);
+void        Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void        Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void        Userdef_USB_usb1_host_delay_500ns(void);
+void        Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t    Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t    Userdef_USB_usb1_host_stop_dma1(void);
+#endif
+
+#endif /* USB1_HOST_API_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/inc/usb1_host_dmacdrv.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_DMACDRV_H
+#define USB1_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+    uint32_t src_addr;      /* Transfer source address                */
+    uint32_t dst_addr;      /* Transfer destination address           */
+    uint32_t count;         /* Transfer byte count                    */
+    uint32_t src_size;      /* Transfer source data size              */
+    uint32_t dst_size;      /* Transfer destination data size         */
+    uint32_t saddr_dir;     /* Transfer source address direction      */
+    uint32_t daddr_dir;     /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE          (0)     /* Single transfer                   */
+#define DMAC_SAMPLE_CONTINUATION    (1)     /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER          (0)     /* Register mode */
+#define DMAC_MODE_LINK              (1)     /* Link mode     */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT           (0)     /* External request                   */
+#define DMAC_REQ_MODE_PERI          (1)     /* On-chip peripheral module request  */
+#define DMAC_REQ_MODE_SOFT          (2)     /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8           (0)     /* 8 bits    */
+#define DMAC_TRANS_SIZE_16          (1)     /* 16 bits   */
+#define DMAC_TRANS_SIZE_32          (2)     /* 32 bits   */
+#define DMAC_TRANS_SIZE_64          (3)     /* 64 bits   */
+#define DMAC_TRANS_SIZE_128         (4)     /* 128 bits  */
+#define DMAC_TRANS_SIZE_256         (5)     /* 256 bits  */
+#define DMAC_TRANS_SIZE_512         (6)     /* 512 bits  */
+#define DMAC_TRANS_SIZE_1024        (7)     /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC       (1)     /* Not increment */
+#define DMAC_TRANS_ADR_INC          (0)     /* Increment     */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL           (0)     /* Falling edge detection */
+#define DMAC_REQ_DET_RISE           (1)     /* Rising edge detection  */
+#define DMAC_REQ_DET_LOW            (2)     /* Low level detection    */
+#define DMAC_REQ_DET_HIGH           (3)     /* High level detection   */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC            (0)     /* DMAREQ is the source/ DMAACK is active when reading      */
+#define DMAC_REQ_DIR_DST            (1)     /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER            (0)     /* Header              */
+#define DMAC_DESC_SRC_ADDR          (1)     /* Source Address      */
+#define DMAC_DESC_DST_ADDR          (2)     /* Destination Address */
+#define DMAC_DESC_COUNT             (3)     /* Transaction Byte    */
+#define DMAC_DESC_CHCFG             (4)     /* Channel Confg       */
+#define DMAC_DESC_CHITVL            (5)     /* Channel Interval    */
+#define DMAC_DESC_CHEXT             (6)     /* Channel Extension   */
+#define DMAC_DESC_LINK_ADDR         (7)     /* Link Address        */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+    DMAC_REQ_USB0_DMA0_TX,      /* USB_0 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA0_RX,      /* USB_0 channel 0 receive FIFO full              */
+    DMAC_REQ_USB0_DMA1_TX,      /* USB_0 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA1_RX,      /* USB_0 channel 1 receive FIFO full              */
+    DMAC_REQ_USB1_DMA0_TX,      /* USB_1 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA0_RX,      /* USB_1 channel 0 receive FIFO full              */
+    DMAC_REQ_USB1_DMA1_TX,      /* USB_1 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA1_RX,      /* USB_1 channel 1 receive FIFO full              */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC3_Open(uint32_t req);
+void usb1_host_DMAC3_Close(uint32_t *remain);
+void usb1_host_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb1_host_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC4_Open(uint32_t req);
+void usb1_host_DMAC4_Close(uint32_t *remain);
+void usb1_host_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif  /* USB1_HOST_DMACDRV_H */
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/common/usb1_host_dataio.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb1_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void     usb1_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb1_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d1(uint16_t pipe);
+
+static void     usb1_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void     usb1_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void     usb1_host_clear_transaction_counter(uint16_t pipe);
+static void     usb1_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb1_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb1_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb1_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_start_send_transfer
+* Description  : Starts the USB data communication using pipe specified by the argument.
+* Arguments    : uint16_t  pipe    ; Pipe Number
+*              : uint32_t size     ; Data Size
+*              : uint8_t  *data    ; Data data Address
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t status;
+    uint16_t usefifo;
+    uint16_t mbw;
+
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    usb1_host_clear_bemp_sts(pipe);
+    usb1_host_clear_brdy_sts(pipe);
+    usb1_host_clear_nrdy_sts(pipe);
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+        case USB_HOST_D0FIFO_DMA:
+            usefifo = USB_HOST_D0USE;
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+        case USB_HOST_D1FIFO_DMA:
+            usefifo = USB_HOST_D1USE;
+        break;
+
+        default:
+            usefifo = USB_HOST_CUSE;
+        break;
+    };
+
+    usb1_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+    usb1_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    status = usb1_host_write_buffer(pipe);
+
+    if (status != USB_HOST_FIFOERROR)
+    {
+        usb1_host_set_pid_buf(pipe);
+    }
+
+    return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer
+* Description  : Writes data in the buffer allocated in the pipe specified by
+*              : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer (uint16_t pipe)
+{
+    uint16_t status;
+    uint16_t usefifo;
+
+    g_usb1_host_PipeIgnore[pipe] = 0;
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            status = usb1_host_write_buffer_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            status = usb1_host_write_buffer_d1(pipe);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            status = usb1_host_write_dma_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            status = usb1_host_write_dma_d1(pipe);
+        break;
+
+        default:
+            status = usb1_host_write_buffer_c(pipe);
+        break;
+    };
+
+    switch (status)
+    {
+        case USB_HOST_WRITING:                      /* Continue of data write */
+            usb1_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+            usb1_host_enable_brdy_int(pipe);        /* Enable Ready Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                     /* End of data write */
+        case USB_HOST_WRITESHRT:                    /* End of data write */
+            usb1_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+
+            usb1_host_clear_nrdy_sts(pipe);
+            usb1_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+
+            /* for last transfer */
+            usb1_host_enable_bemp_int(pipe);        /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEDMA:                     /* DMA write */
+            usb1_host_clear_nrdy_sts(pipe);
+            usb1_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+        break;
+
+        case USB_HOST_FIFOERROR:                    /* FIFO access status */
+        default:
+            usb1_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+            usb1_host_disable_bemp_int(pipe);       /* Disable Empty Interrupt */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_c
+* Description  : Writes data in the buffer allocated in the pipe specified in
+*              : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+    }
+    else
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+    }
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb1_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb1_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb1_host_write_c_fifo(pipe, (uint16_t)count);
+
+    if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb1_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB201.CFIFOCTR,
+                                USB_CFIFOCTR_BVAL_SHIFT,
+                                USB_CFIFOCTR_BVAL) == 0)
+        {
+            USB201.CFIFOCTR = USB_HOST_BITBVAL;             /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb1_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb1_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count = g_usb1_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb1_host_write_d0_fifo(pipe, (uint16_t)count);
+
+    if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb1_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB201.D0FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb1_host_data_count[pipe] -= count;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb1_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb1_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb1_host_write_d1_fifo(pipe, (uint16_t)count);
+
+    if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb1_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB201.D1FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb1_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D0FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb1_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb1_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 1;
+        }
+        else
+        {
+            g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0;
+        }
+
+        dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb1_host_data_count[pipe]    = 0;
+        g_usb1_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write  */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D1FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb1_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb1_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 1;
+        }
+        else
+        {
+            g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0;
+        }
+
+        dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb1_host_data_count[pipe]    = 0;
+        g_usb1_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_transfer
+* Description  : Starts USB data reception using the pipe specified in the argument.
+*              : The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t usefifo;
+
+    usb1_host_clear_bemp_sts(pipe);
+    usb1_host_clear_brdy_sts(pipe);
+    usb1_host_clear_nrdy_sts(pipe);
+
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb1_host_start_receive_trns_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb1_host_start_receive_trns_d1(pipe, size, data);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            usb1_host_start_receive_dma_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            usb1_host_start_receive_dma_d1(pipe, size, data);
+        break;
+
+        default:
+            usb1_host_start_receive_trns_c(pipe, size, data);
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+*              : When storing data in the buffer allocated in the pipe specified in the
+*              : argument, BRDY interrupt is generated to read data
+*              : in the interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = size;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+    USB201.CFIFOCTR = USB_HOST_BITBCLR;
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    usb1_host_enable_nrdy_int(pipe);
+    usb1_host_enable_brdy_int(pipe);
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data in the
+*              : interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = size;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    usb1_host_enable_nrdy_int(pipe);
+    usb1_host_enable_brdy_int(pipe);
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = size;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    usb1_host_enable_nrdy_int(pipe);
+    usb1_host_enable_brdy_int(pipe);
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = 0;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb1_host_read_dma(pipe);
+
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d1
+* Description  : Read data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = 0;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb1_host_read_dma(pipe);
+
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Uses FIF0 set in the pipe definition table.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb1_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+    {
+        status = usb1_host_read_buffer_d0(pipe);
+    }
+    else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+    {
+        status = usb1_host_read_buffer_d1(pipe);
+    }
+    else
+    {
+        status = usb1_host_read_buffer_c(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                  /* Continue of data read */
+        break;
+
+        case USB_HOST_READEND:                                  /* End of data read */
+        case USB_HOST_READSHRT:                                 /* End of data read */
+            usb1_host_disable_brdy_int(pipe);
+            g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+            g_usb1_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READOVER:                                 /* buffer over */
+            if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+            {
+                USB201.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+            {
+                USB201.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else
+            {
+                USB201.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+            }
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+#else
+            g_usb1_host_pipe_status[pipe]   = USB_HOST_PIPE_ERROR;
+#endif
+            g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                      /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb1_host_data_count[pipe];
+    }
+    else if (g_usb1_host_data_count[pipe] == dtln)          /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB201.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+    }
+    else
+    {
+        usb1_host_read_c_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb1_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb1_host_data_count[pipe];
+    }
+    else if (g_usb1_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb1_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB201.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb1_host_read_d0_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb1_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d1
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb1_host_data_count[pipe];
+    }
+    else if (g_usb1_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) !=0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb1_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB201.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb1_host_read_d1_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb1_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_dma (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb1_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+    {
+        status = usb1_host_read_dma_d0(pipe);
+    }
+    else
+    {
+        status = usb1_host_read_dma_d1(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                      /* Continue of data read */
+        break;
+
+        case USB_HOST_READZERO:                                     /* End of data read */
+            usb1_host_disable_brdy_int(pipe);
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READEND:                                      /* End of data read */
+        case USB_HOST_READSHRT:                                     /* End of data read */
+            usb1_host_disable_brdy_int(pipe);
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+            }
+        break;
+
+        case USB_HOST_READOVER:                                     /* buffer over */
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+            }
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb1_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb1_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb1_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb1_host_data_count[pipe];
+        }
+        else if (g_usb1_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB201.D0FIFOCTR = USB_HOST_BITBCLR;            /* Clear BCLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb1_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe;        /* not use in read operation */
+        g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0;           /* not use in read operation */
+
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw , dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb1_host_data_count[pipe]   -= count;
+        g_usb1_host_data_pointer[pipe] += count;
+        g_usb1_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by DMA transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb1_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb1_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb1_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb1_host_data_count[pipe];
+        }
+        else if (g_usb1_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB201.D1FIFOCTR = USB_HOST_BITBCLR;            /* Clear BCLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb1_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe;        /* not use in read operation */
+        g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0;           /* not use in read operation */
+
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb1_host_data_count[pipe]   -= count;
+        g_usb1_host_data_pointer[pipe] += count;
+        g_usb1_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_change_fifo_port
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument. After allocating FIF0, waits in the software
+*              : till the corresponding pipe becomes ready.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR         ; Error
+*              : Others            ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb1_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    usb1_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+    for (loop = 0; loop < 4; loop++)
+    {
+        switch (fifosel)
+        {
+            case USB_HOST_CUSE:
+                buffer = USB201.CFIFOCTR;
+            break;
+
+            case USB_HOST_D0USE:
+            case USB_HOST_D0DMA:
+                buffer = USB201.D0FIFOCTR;
+            break;
+
+            case USB_HOST_D1USE:
+            case USB_HOST_D1DMA:
+                buffer = USB201.D1FIFOCTR;
+            break;
+
+            default:
+                buffer = 0;
+            break;
+        }
+
+        if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+        {
+            return buffer;
+        }
+
+        loop2 = 25;
+
+        while (loop2-- > 0)
+        {
+            /* wait */
+        }
+    }
+
+    return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    g_usb1_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB201.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB201.D0FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB201.D1FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe2
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.(DFACC)
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+*              : uint16_t dfacc     ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+    uint16_t buffer;
+    uint32_t loop;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+    uint32_t dummy;
+#endif
+    volatile uint32_t loop2;
+
+    g_usb1_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB201.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB201.D0FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB201.D0FIFO.UINT32;
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB201.D1FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB201.D1FIFO.UINT32;
+                loop = dummy;                   // avoid warning.
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_c_fifo
+* Description  : Writes data in CFIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB201.CFIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_c_fifo
+* Description  : Reads data from CFIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb1_host_data_pointer[pipe] = USB201.CFIFO.UINT8[HH];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT16[H];
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT32;
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d0_fifo
+* Description  : Writes data in D0FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB201.D0FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d0_fifo
+* Description  : Reads data from D0FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating DOFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  Pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb1_host_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H];
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT32;
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d1_fifo
+* Description  : Writes data in D1FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB201.D1FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d1_fifo
+* Description  : Reads data from D1FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb1_host_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H];
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT32;
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_com_get_dmasize
+* Description  : Calculates access width of DMA transfer by the argument to
+                 return as the Return Value.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : DMA transfer size    : 0   8bit
+*              :                      : 1  16bit
+*              :                      : 2  32bit
+*******************************************************************************/
+static uint32_t usb1_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+
+    if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+    {
+        /*  When transfer byte count is odd         */
+        /* or transfer data area is 8-bit alignment */
+        size = 0;           /* 8bit */
+    }
+    else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+    {
+        /* When the transfer byte count is multiples of 2 */
+        /* or the transfer data area is 16-bit alignment */
+        size = 1;           /* 16bit */
+    }
+    else
+    {
+        /* When the transfer byte count is multiples of 4 */
+        /* or the transfer data area is 32-bit alignment */
+        size = 2;           /* 32bit */
+    }
+
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mbw
+* Description  : Calculates access width of DMA to return the value set in MBW.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : FIFO transfer size   : USB_HOST_BITMBW_8    8bit
+*              :                      : USB_HOST_BITMBW_16  16bit
+*              :                      : USB_HOST_BITMBW_32  32bit
+*******************************************************************************/
+uint16_t usb1_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+    uint16_t mbw;
+
+    size = usb1_host_com_get_dmasize(trncount, dtptr);
+
+    if (size == 0)
+    {
+        /* 8bit */
+        mbw = USB_HOST_BITMBW_8;
+    }
+    else if (size == 1)
+    {
+        /* 16bit */
+        mbw = USB_HOST_BITMBW_16;
+    }
+    else
+    {
+        /* 32bit */
+        mbw = USB_HOST_BITMBW_32;
+    }
+
+    return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_transaction_counter
+* Description  : Sets transaction counter by the argument(PIPEnTRN).
+*              : Clears transaction before setting to enable transaction counter setting.
+* Arguments    : uint16_t pipe     ; Pipe number
+*              : uint32_t bsize    : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+    uint16_t mxps;
+    uint16_t cnt;
+
+    if (bsize == 0)
+    {
+        return;
+    }
+
+    mxps = usb1_host_get_mxps(pipe);            /* Max Packet Size */
+
+    if ((bsize % mxps) == 0)
+    {
+        cnt = (uint16_t)(bsize / mxps);
+    }
+    else
+    {
+        cnt = (uint16_t)((bsize / mxps) + 1);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE1TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE2TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE3TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE4TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE5TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE9TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_transaction_counter
+* Description  : Clears the transaction counter by the argument.
+*              : After executing this function, the transaction counter is invalid.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_transaction_counter (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_stop_transfer
+* Description  : Stops the USB transfer in the pipe specified by the argument.
+*              : After stopping the USB transfer, clears the buffer allocated in
+*              : the pipe.
+*              : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+*              : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+*              : in the corresponding pipe becomes invalid. Sequence bit is also
+*              : cleared.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_stop_transfer (uint16_t pipe)
+{
+    uint16_t usefifo;
+    uint32_t remain;
+
+    usb1_host_set_pid_nak(pipe);
+
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            remain = Userdef_USB_usb1_host_stop_dma0();
+            usb1_host_dma_stop_d0(pipe, remain);
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            remain = Userdef_USB_usb1_host_stop_dma1();
+            usb1_host_dma_stop_d1(pipe, remain);
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        default:
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.CFIFOCTR =  USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb1_host_disable_brdy_int(pipe);
+    usb1_host_disable_nrdy_int(pipe);
+    usb1_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+    usb1_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d0
+* Description  : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d1
+* Description  : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/common/usb1_host_dma.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+/* #include "usb1_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb1_host_dmaint(uint16_t fifo);
+static void usb1_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb1_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d0
+* Description  : D0FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB201.D0FIFOCTR;
+            dtln   = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+            g_usb1_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d1
+* Description  : D1FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB201.D1FIFOCTR;
+            dtln = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+            g_usb1_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d0fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+    usb1_host_dmaint(USB_HOST_D0FIFO);
+    g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d1fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+    usb1_host_dmaint(USB_HOST_D1FIFO);
+    g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint
+* Description  : This function is DMA transfer end interrupt
+* Arguments    : uint16_t fifo  ; fifo number
+*              :                ;  USB_HOST_D0FIFO
+*              :                ;  USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint (uint16_t fifo)
+{
+    uint16_t pipe;
+
+    pipe = g_usb1_host_DmaPipe[fifo];
+
+    if (g_usb1_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+    {
+        usb1_host_dmaint_buf2fifo(pipe);
+    }
+    else
+    {
+        usb1_host_dmaint_fifo2buf(pipe);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_fifo2buf
+* Description  : Executes read completion from FIFO by DMAC.
+* Arguments    : uint16_t pipe       : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_fifo2buf (uint16_t pipe)
+{
+    uint32_t remain;
+    uint16_t useport;
+
+    if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+    {
+        useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+        if (useport == USB_HOST_D0FIFO_DMA)
+        {
+            remain = Userdef_USB_usb1_host_stop_dma0();
+            usb1_host_dma_stop_d0(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb1_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+        else
+        {
+            remain = Userdef_USB_usb1_host_stop_dma1();
+            usb1_host_dma_stop_d1(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb1_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_buf2fifo
+* Description  : Executes write completion in FIFO by DMAC.
+* Arguments    : uint16_t pipe     : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_buf2fifo (uint16_t pipe)
+{
+    uint16_t useport;
+    uint32_t remain;
+
+    useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    if (useport == USB_HOST_D0FIFO_DMA)
+    {
+        remain = Userdef_USB_usb1_host_stop_dma0();
+        usb1_host_dma_stop_d0(pipe, remain);
+
+        if (g_usb1_host_DmaBval[USB_HOST_D0FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+    else
+    {
+        remain = Userdef_USB_usb1_host_stop_dma1();
+        usb1_host_dma_stop_d1(pipe, remain);
+
+        if (g_usb1_host_DmaBval[USB_HOST_D1FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+
+    usb1_host_enable_bemp_int(pipe);
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/common/usb1_host_intrn.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_brdy_int
+* Description  : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+*              : According to the pipe that interrupt is generated in,
+*              : reads/writes buffer allocated in the pipe.
+*              : This function is executed in the BRDY interrupt handler.
+*              : This function clears BRDY interrupt status and BEMP interrupt
+*              : status.
+* Arguments    : uint16_t status       ; BRDYSTS Register Value
+*              : uint16_t int_enb      ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint32_t int_sense = 0;
+    uint16_t pipe;
+    uint16_t pipebit;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        pipebit = g_usb1_host_bit_set[pipe];
+
+        if ((status & pipebit) && (int_enb & pipebit))
+        {
+            USB201.BRDYSTS = (uint16_t)~pipebit;
+            USB201.BEMPSTS = (uint16_t)~pipebit;
+
+            if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb1_host_dma_interrupt_d0fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb1_host_read_dma(pipe);
+                    usb1_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb1_host_dma_interrupt_d1fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb1_host_read_dma(pipe);
+                    usb1_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else
+            {
+                if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+                {
+                    usb1_host_read_buffer(pipe);
+                }
+                else
+                {
+                    usb1_host_write_buffer(pipe);
+                }
+            }
+#if(1) /* ohci_wrapp */
+            switch (g_usb1_host_pipe_status[pipe])
+            {
+                case USB_HOST_PIPE_DONE:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+                break;
+                case USB_HOST_PIPE_NORES:
+                case USB_HOST_PIPE_STALL:
+                case USB_HOST_PIPE_ERROR:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+                break;
+                default:
+                    /* Do Nothing */
+                break;
+            }
+#endif
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_nrdy_int
+* Description  : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+*              : Checks NRDY interrupt cause by PID. When the cause if STALL,
+*              : regards the pipe state as STALL and ends the processing.
+*              : Then the cause is not STALL, increments the error count to
+*              : communicate again. When the error count is 3, determines
+*              : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+*              : This function is executed in the NRDY interrupt handler.
+*              : This function clears NRDY interrupt status.
+* Arguments    : uint16_t status       ; NRDYSTS Register Value
+*              : uint16_t int_enb      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB201.NRDYSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+        {
+            if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+                                    USB_SYSCFG_DCFM_SHIFT,
+                                    USB_SYSCFG_DCFM) == 1)
+            {
+                if (g_usb1_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+                {
+                    pid = usb1_host_get_pid(pipe);
+
+                    if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+                    {
+                        g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+                    }
+                    else
+                    {
+#if(1) /* ohci_wrapp */
+                        g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+                        g_usb1_host_PipeIgnore[pipe]++;
+
+                        if (g_usb1_host_PipeIgnore[pipe] == 3)
+                        {
+                            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        }
+                        else
+                        {
+                            usb1_host_set_pid_buf(pipe);
+                        }
+#endif
+                    }
+                }
+            }
+            else
+            {
+                /* USB Function */
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_bemp_int
+* Description  : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments    : uint16_t status       ; BEMPSTS Register Value
+*              : uint16_t int_enb      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+    uint16_t inbuf;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB201.BEMPSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+        {
+            pid = usb1_host_get_pid(pipe);
+
+            if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+            {
+                g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+            }
+            else
+            {
+                inbuf = usb1_host_get_inbuf(pipe);
+
+                if (inbuf == 0)
+                {
+                    usb1_host_disable_bemp_int(pipe);
+                    usb1_host_set_pid_nak(pipe);
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+                }
+            }
+        }
+    }
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/common/usb1_host_lib.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1594 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "devdrv_intc.h"        /* INTC Driver Header   */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_brdy_int
+* Description  : Enables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_brdy_int (uint16_t pipe)
+{
+    /* enable brdy interrupt */
+    USB201.BRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_brdy_int
+* Description  : Disables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_brdy_int (uint16_t pipe)
+{
+    /* disable brdy interrupt */
+    USB201.BRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_brdy_sts
+* Description  : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_brdy_sts (uint16_t pipe)
+{
+    /* clear brdy status */
+    USB201.BRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_bemp_int
+* Description  : Enables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_bemp_int (uint16_t pipe)
+{
+    /* enable bemp interrupt */
+    USB201.BEMPENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_bemp_int
+* Description  : Disables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_bemp_int (uint16_t pipe)
+{
+    /* disable bemp interrupt */
+    USB201.BEMPENB  &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_bemp_sts
+* Description  : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_bemp_sts (uint16_t pipe)
+{
+    /* clear bemp status */
+    USB201.BEMPSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_nrdy_int
+* Description  : Enables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_nrdy_int (uint16_t pipe)
+{
+    /* enable nrdy interrupt */
+    USB201.NRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_nrdy_int
+* Description  : Disables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_nrdy_int (uint16_t pipe)
+{
+    /* disable nrdy interrupt */
+    USB201.NRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_nrdy_sts
+* Description  : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_nrdy_sts (uint16_t pipe)
+{
+    /* clear nrdy status */
+    USB201.NRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed
+* Description  : Returns the result of USB reset hand shake (RHST) as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_HIGH_SPEED  ; Hi-Speed
+*              : USB_HOST_FULL_SPEED  ; Full-Speed
+*              : USB_HOST_LOW_SPEED   ; Low-Speed
+*              : USB_HOST_NON_SPEED   ; error
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed (void)
+{
+    uint16_t rhst;
+    uint16_t speed;
+
+    rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_HSMODE)
+    {
+        speed = USB_HOST_HIGH_SPEED;
+    }
+    else if (rhst == USB_HOST_FSMODE)
+    {
+        speed = USB_HOST_FULL_SPEED;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        speed = USB_HOST_LOW_SPEED;
+    }
+    else
+    {
+        speed = USB_HOST_NON_SPEED;
+    }
+
+    return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed_enable
+* Description  : Returns the USB High-Speed connection enabled status as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+*              : USB_HOST_NO  : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed_enable (void)
+{
+    uint16_t ret;
+
+    ret = USB_HOST_NO;
+
+    if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE) == 1)
+    {
+        ret = USB_HOST_YES;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_buf
+* Description  : Enables communicaqtion in the pipe specified by the argument
+*              : (BUF).
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_buf (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb1_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb1_host_set_pid_nak(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                USB_HOST_PID_BUF,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_nak
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+*              : When the pipe status was enabling communication (BUF) before
+*              : executing before executing this function, waits in the software
+*              : until the pipe becomes ready after setting disabled.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_nak (uint16_t pipe)
+{
+    uint16_t pid;
+    uint16_t pbusy;
+    uint32_t loop;
+
+    pid = usb1_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb1_host_set_pid_stall(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                USB_HOST_PID_NAK,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        for (loop = 0; loop < 200; loop++)
+        {
+            switch (pipe)
+            {
+                case USB_HOST_PIPE0:
+                    pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR,
+                                                USB_DCPCTR_PBUSY_SHIFT,
+                                                USB_DCPCTR_PBUSY);
+                break;
+
+                case USB_HOST_PIPE1:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE2:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE3:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE4:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE5:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE6:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE7:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE8:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE9:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                                USB_PIPEnCTR_9_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_9_PBUSY);
+                break;
+
+                default:
+                    pbusy = 1;
+                break;
+            }
+
+            if (pbusy == 0)
+            {
+                break;
+            }
+
+            Userdef_USB_usb1_host_delay_500ns();
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_stall
+* Description  : Disables communication (STALL) in the pipe specified by the
+*              : argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_stall (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb1_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+    else
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_pid_stall
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_pid_stall (uint16_t pipe)
+{
+    usb1_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_pid
+* Description  : Returns the pipe state specified by the argument.
+* Arguments    : uint16_t pipe          ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_host_get_pid (uint16_t pipe)
+{
+    uint16_t pid;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            pid = RZA_IO_RegRead_16(&USB201.DCPCTR,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+            pid = 0;
+        break;
+    }
+
+    return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_csclr
+* Description  : CSPLIT status clear setting of sprit transaction in specified
+*              : pipe is performed.
+*              : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+*              : in DCPCTR register are continuously changed (when the sequence
+*              : toggle bit of data PID is continuously changed over two or more pipes),
+*              : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+*              : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+*              : In addition, both bits should be operated after PID is set to NAK.
+*              : However, when it is set to the isochronous transfer as the transfer type
+*              : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_csclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                1,
+                                USB_DCPCTR_CSCLR_SHIFT,
+                                USB_DCPCTR_CSCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_CSCLR_SHIFT,
+                                USB_PIPEnCTR_9_CSCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqclr
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA0.
+* Arguments    : uint16_t pipe              ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQCLR_SHIFT,
+                                USB_DCPCTR_SQCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQCLR_SHIFT,
+                                USB_PIPEnCTR_9_SQCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqset
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA1.
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqset (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQSET_SHIFT,
+                                USB_DCPCTR_SQSET);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQSET_SHIFT,
+                                USB_PIPEnCTR_9_SQSET);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_sqmon
+* Description  : Toggle bit of specified pipe is obtained
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb1_host_get_sqmon (uint16_t pipe)
+{
+    uint16_t sqmon;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR,
+                                        USB_DCPCTR_SQMON_SHIFT,
+                                        USB_DCPCTR_SQMON);
+        break;
+
+        case USB_HOST_PIPE1:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE2:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE3:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE4:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE5:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE6:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE7:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE8:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE9:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                        USB_PIPEnCTR_9_SQMON_SHIFT,
+                                        USB_PIPEnCTR_9_SQMON);
+        break;
+
+        default:
+            sqmon = 0;
+        break;
+    }
+
+    return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_aclrm
+* Description  : The buffer of specified pipe is initialized
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_aclrm (uint16_t pipe)
+{
+    usb1_host_set_aclrm(pipe);
+    usb1_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clr_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clr_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                0,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_inbuf
+* Description  : Returns INBUFM of the pipe specified by the argument.
+* Arguments    : uint16_t pipe             ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb1_host_get_inbuf (uint16_t pipe)
+{
+    uint16_t inbuf;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE1:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE2:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE3:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE4:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE5:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE6:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE7:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE8:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE9:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                    USB_PIPEnCTR_9_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_9_INBUFM);
+        break;
+
+        default:
+            inbuf = 0;
+        break;
+    }
+
+    return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_setting_interrupt
+* Description  : Sets the USB module interrupt level.
+* Arguments    : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb1_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+    IRQn_Type d0fifo_dmaintid;
+    IRQn_Type d1fifo_dmaintid;
+
+    InterruptHandlerRegister(USBI1_IRQn, usb1_host_interrupt);
+    GIC_SetPriority(USBI1_IRQn, level);
+    GIC_EnableIRQ(USBI1_IRQn);
+
+    d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+        GIC_SetPriority(d0fifo_dmaintid, level);
+        GIC_EnableIRQ(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+        GIC_SetPriority(d1fifo_dmaintid, level);
+        GIC_EnableIRQ(d1fifo_dmaintid);
+    }
+#else
+    uint16_t d0fifo_dmaintid;
+    uint16_t d1fifo_dmaintid;
+
+    R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_host_interrupt);
+    R_INTC_SetPriority(INTC_ID_USBI1, level);
+    R_INTC_Enable(INTC_ID_USBI1);
+
+    d0fifo_dmaintid = Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+        R_INTC_SetPriority(d0fifo_dmaintid, level);
+        R_INTC_Enable(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+        R_INTC_SetPriority(d1fifo_dmaintid, level);
+        R_INTC_Enable(d1fifo_dmaintid);
+    }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_reset_module
+* Description  : Initializes the USB module.
+*              : Enables providing clock to the USB module.
+*              : Sets USB bus wait register.
+* Arguments    : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+*              :                    ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb1_host_reset_module (uint16_t clockmode)
+{
+    if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                USB_SYSCFG_UPLLE_SHIFT,
+                                USB_SYSCFG_UPLLE) == 1)
+    {
+        if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+        {
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            USB201.SYSCFG0 = 0;
+            USB200.SYSCFG0 = 0;
+            USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+            Userdef_USB_usb1_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            Userdef_USB_usb1_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                            0,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            0,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        USB201.SYSCFG0 = 0;
+        USB200.SYSCFG0 = 0;
+        USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+        Userdef_USB_usb1_host_delay_xms(1);
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            1,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                            1,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+    }
+
+    USB201.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_buf_size
+* Description  : Obtains pipe buffer size specified by the argument and
+*              : maximum packet size of the USB device in use.
+*              : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+*              : packet size of the USB device using the corresponding pipe.
+*              : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+*              : corresponding pipe is in continuous transfer mode,
+*              : obtains the buffer size allocated in the corresponcing pipe,
+*              : when incontinuous transfer, obtains maximum packet size.
+* Arguments    : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb1_host_get_buf_size (uint16_t pipe)
+{
+    uint16_t size;
+    uint16_t bufsize;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+        {
+            bufsize = RZA_IO_RegRead_16(&g_usb1_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+            size    = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+        }
+        else
+        {
+            size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+        }
+    }
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mxps
+* Description  : Obtains maximum packet size of the USB device using the pipe
+*              : specified by the argument.
+* Arguments    : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb1_host_get_mxps (uint16_t pipe)
+{
+    uint16_t size;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+    }
+
+    return size;
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/host/usb1_host_controlrw.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlTransStart
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr ; device address
+*              : uint16_t Req   ; bmRequestType & bRequest
+*              : uint16_t Val   ; wValue
+*              : uint16_t Indx  ; wIndex
+*              : uint16_t Len   ; wLength
+*              : uint8_t  *Buf  ; Data buffer
+* Return Value : DEVDRV_SUCCESS     ;   SUCCESS
+*              : DEVDRV_ERROR       ;   ERROR
+*******************************************************************************/
+int32_t usb1_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+                            uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+    if (g_usb1_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+    {
+        RZA_IO_RegWrite_16(&USB201.SOFCFG,
+                            1,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    USB201.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb1_host_default_max_packet[devadr]);
+
+    if (g_usb1_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+    {
+        g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+        g_usb1_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                    /* Ignore count clear */
+        g_usb1_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+        if (Len == 0)
+        {
+            g_usb1_host_CmdStage |= USB_HOST_MODE_NO_DATA;              /* No-data Control */
+        }
+        else
+        {
+            if ((Req & 0x0080) != 0)
+            {
+                g_usb1_host_CmdStage |= USB_HOST_MODE_READ;             /* Control Read */
+            }
+            else
+            {
+                g_usb1_host_CmdStage |= USB_HOST_MODE_WRITE;            /* Control Write */
+            }
+        }
+
+        g_usb1_host_SavReq  = Req;                                      /* save request */
+        g_usb1_host_SavVal  = Val;
+        g_usb1_host_SavIndx = Indx;
+        g_usb1_host_SavLen  = Len;
+    }
+    else
+    {
+        if ((g_usb1_host_SavReq  != Req)  || (g_usb1_host_SavVal != Val)
+         || (g_usb1_host_SavIndx != Indx) || (g_usb1_host_SavLen != Len))
+        {
+            return DEVDRV_ERROR;
+        }
+    }
+
+    switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+    {
+        /* --------------- SETUP STAGE --------------- */
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+            usb1_host_SetupStage(Req, Val, Indx, Len);
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE):                /* goto next stage */
+            g_usb1_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                /* Ignore count clear */
+            switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_READ:
+                    g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_NO_DATA:
+                    g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                break;
+
+                default:
+                break;
+            }
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+            if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+            }
+        break;
+
+        /* --------------- DATA STAGE --------------- */
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+            switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    usb1_host_CtrlWriteStart((uint32_t)Len, Buf);
+                break;
+
+                case USB_HOST_MODE_READ:
+                    usb1_host_CtrlReadStart((uint32_t)Len, Buf);
+                break;
+
+                default:
+                break;
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE):                         /* goto next stage */
+            g_usb1_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                        /* Ignore count clear */
+            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+            if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb1_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        /* --------------- STATUS STAGE --------------- */
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+            usb1_host_StatusStage();
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE):                       /* end of Control transfer */
+            usb1_host_set_pid_nak(USB_HOST_PIPE0);
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE;       /* exit DONE */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+            if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb1_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        default:
+        break;
+    }
+
+    if (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+    {
+        RZA_IO_RegWrite_16(&USB201.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_SetupStage
+* Description  : Executes USB control transfer/set up stage.
+* Arguments    : uint16_t Req           ; bmRequestType & bRequest
+*              : uint16_t Val           ; wValue
+*              : uint16_t Indx          ; wIndex
+*              : uint16_t Len           ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb1_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    USB201.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN);  /* Status Clear */
+    USB201.USBREQ  = Req;
+    USB201.USBVAL  = Val;
+    USB201.USBINDX = Indx;
+    USB201.USBLENG = Len;
+    USB201.DCPCTR  = USB_HOST_BITSUREQ;                                 /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_StatusStage
+* Description  : Executes USB control transfer/status stage.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_StatusStage (void)
+{
+    uint8_t Buf1[16];
+
+    switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+    {
+        case USB_HOST_MODE_READ:
+            usb1_host_CtrlWriteStart((uint32_t)0, (uint8_t*)&Buf1);
+        break;
+
+        case USB_HOST_MODE_WRITE:
+            usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+        break;
+
+        case USB_HOST_MODE_NO_DATA:
+            usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlWriteStart
+* Description  : Executes USB control transfer/data stage(write).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+*              : USB_HOST_WRITEEND  ; End of data write (not null)
+*              : USB_HOST_WRITING   ; Continue of data write
+*              : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb1_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t EndFlag_K;
+    uint16_t mbw;
+
+    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb1_host_set_pid_nak(USB_HOST_PIPE0);                              /* Set NAK */
+    g_usb1_host_data_count[USB_HOST_PIPE0]   = Bsize;                   /* Transfer size set */
+    g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table;                   /* Transfer address set */
+
+    USB201.DCPCTR = USB_HOST_BITSQSET;                                  /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb1_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB201.DCPCFG,
+                        1,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+    USB201.CFIFOCTR = USB_HOST_BITBCLR;                                 /* Buffer Clear */
+
+    usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+    EndFlag_K = usb1_host_write_buffer_c(USB_HOST_PIPE0);
+    /* Host Control sequence */
+    switch (EndFlag_K)
+    {
+        case USB_HOST_WRITESHRT:                                        /* End of data write */
+            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            usb1_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb1_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                                         /* End of data write (not null) */
+        case USB_HOST_WRITING:                                          /* Continue of data write */
+            usb1_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb1_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_FIFOERROR:                                        /* FIFO access error */
+        break;
+
+        default:
+        break;
+    }
+    usb1_host_set_pid_buf(USB_HOST_PIPE0);                              /* Set BUF */
+    return (EndFlag_K);                                                 /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlReadStart
+* Description  : Executes USB control transfer/data stage(read).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t mbw;
+
+    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb1_host_set_pid_nak(USB_HOST_PIPE0);                  /* Set NAK */
+    g_usb1_host_data_count[USB_HOST_PIPE0]   = Bsize;       /* Transfer size set */
+    g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table;       /* Transfer address set */
+
+    USB201.DCPCTR     = USB_HOST_BITSQSET;                  /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb1_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB201.DCPCFG,
+                        0,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+    USB201.CFIFOCTR = USB_HOST_BITBCLR;                     /* Buffer Clear */
+
+    usb1_host_enable_nrdy_int(USB_HOST_PIPE0);              /* Error (NORES or STALL) */
+    usb1_host_enable_brdy_int(USB_HOST_PIPE0);              /* Ok */
+    usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+    usb1_host_set_pid_buf(USB_HOST_PIPE0);                  /* Set BUF */
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/host/usb1_host_drv_api.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,892 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_host_init
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint8_t int_level  : USB Module interrupt level
+*              : USBU16  mode       : USB_HOST_HIGH_SPEED
+*                                   : USB_HOST_FULL_SPEED
+*              : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+*              :  USB_HOST_ATTACH
+*              :  USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb1_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+    uint16_t         connect;
+    volatile uint8_t dummy_buf;
+
+    CPG.STBCR7 &= 0xfc;                         /*The clock of USB0/1 modules is permitted */
+    dummy_buf   = CPG.STBCR7;                   /* (Dummy read) */
+#if(1) /* mbed */
+    (void)dummy_buf;
+#endif
+
+    g_usb1_host_SupportUsbDeviceSpeed = mode;
+
+    usb1_host_setting_interrupt(int_level);
+    usb1_host_reset_module(clockmode);
+
+    g_usb1_host_bchg_flag   = USB_HOST_NO;
+    g_usb1_host_detach_flag = USB_HOST_NO;
+    g_usb1_host_attach_flag = USB_HOST_NO;
+
+    g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+    g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb1_host_InitModule();
+
+    connect = usb1_host_CheckAttach();
+
+    if (connect == USB_HOST_ATTACH)
+    {
+        g_usb1_host_attach_flag = USB_HOST_YES;
+    }
+    else
+    {
+        usb1_host_UsbDetach2();
+    }
+
+    return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_enumeration
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR       : device detach
+*              : DEVDRV_SUCCESS               : device enumeration success
+*              : DEVDRV_ERROR                 : device enumeration error
+*******************************************************************************/
+int32_t usb1_api_host_enumeration (uint16_t devadr)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    g_usb1_host_setUsbAddress = devadr;
+
+    while (1)
+    {
+        driver_sts = usb1_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = DEVDRV_USBH_DETACH_ERR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = DEVDRV_SUCCESS;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb1_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_detach
+* Description  : USB detach routine
+* Arguments    : none
+* Return Value : USB_HOST_DETACH : USB detach
+*              : USB_HOST_ATTACH : USB attach
+*              : DEVDRV_ERROR    : error
+*******************************************************************************/
+int32_t usb1_api_host_detach (void)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    while (1)
+    {
+        driver_sts = usb1_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = USB_HOST_DETACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = USB_HOST_ATTACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb1_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_in
+* Description  : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb1_host_start_receive_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;                /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb1_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb1_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb1_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb1_host_stop_transfer(Pipe);
+
+    g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_out
+* Description  : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb1_host_start_send_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;              /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb1_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb1_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb1_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb1_host_stop_transfer(Pipe);
+
+    g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_control_transfer
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Req          ; bmRequestType & bRequest
+*              : uint16_t Val          ; wValue
+*              : uint16_t Indx         ; wIndex
+*              : uint16_t Len          ; wLength
+*              : uint8_t  *buf         ; Buffer
+* Return Value : DEVDRV_SUCCESS           ; success
+*              : DEVDRV_USBH_DETACH_ERR   ; device detach
+*              : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+*              : DEVDRV_USBH_STALL        ; STALL
+*              : DEVDRV_ERROR             ; error
+*******************************************************************************/
+int32_t usb1_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+                                                     uint16_t Len, uint8_t * Buf)
+{
+    int32_t  ret;
+
+    do
+    {
+        ret = usb1_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+        if (ret == DEVDRV_SUCCESS)
+        {
+            if (g_usb1_host_detach_flag == USB_HOST_YES)
+            {
+                break;
+            }
+
+            if ((g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+                && (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+            {
+                break;
+            }
+        }
+        else
+        {
+            return DEVDRV_ERROR;
+        }
+    } while (1);
+
+    if (g_usb1_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb1_host_pipe_status[USB_HOST_PIPE0])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_CTRL_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_set_endpoint
+* Description  : Sets end point on the information specified in the argument.
+* Arguments    : uint16_t                devadr           ; device address
+*              : uint8_t                *configdescriptor ; device configration descriptor
+*              : USB_HOST_CFG_PIPETBL_t *user_table       ; pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+    uint16_t                ret;
+    uint32_t                end_point;
+    uint32_t                offset;
+    uint32_t                totalLength;
+    USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+    /*  End Point Search */
+    end_point   = 0;
+    offset      = configdescriptor[0];
+    totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+    do
+    {
+        if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+        {
+            pipe_table = &user_table[end_point];
+
+            if (pipe_table->pipe_number == 0xffff)
+            {
+                break;
+            }
+
+            ret = usb1_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+            if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+            {
+                return DEVDRV_ERROR;
+            }
+
+            ++end_point;
+        }
+
+        /* Next End Point Search */
+        offset += configdescriptor[offset];
+
+    } while (offset < totalLength);
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : uint16_t pipe_sel                  : Pipe Number
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+        user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+        user_table->pipe_max_pktsize  = 0;
+        user_table->pipe_cycle        = 0;
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint_pipe
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+
+        if (user_table->pipe_number == pipe_sel)
+        {
+            user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+            user_table->pipe_max_pktsize  = 0;
+            user_table->pipe_cycle        = 0;
+            break;
+        }
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_api_host_SetEndpointTable
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : uint16_t devadr                    : device address
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+*              : uint8_t                *Table      : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN           ; IN endpoint
+*              : USB_HOST_DIR_H_OUT          ; OUT endpoint
+*              : USB_END_POINT_ERROR         ; error
+*******************************************************************************/
+uint16_t usb1_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+    uint16_t PipeCfg;
+    uint16_t PipeMaxp;
+    uint16_t pipe_number;
+    uint16_t ret;
+    uint16_t ret_flag = 0;                                  // avoid warning.
+
+    pipe_number = user_table->pipe_number;
+
+    if (Table[1] != USB_HOST_ENDPOINT_DESC)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    switch (Table[3] & USB_HOST_EP_TYPE)
+    {
+        case USB_HOST_EP_CNTRL:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+
+        case USB_HOST_EP_ISO:
+            if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_ISO;
+        break;
+
+        case USB_HOST_EP_BULK:
+            if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_BULK;
+        break;
+
+        case USB_HOST_EP_INT:
+            if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_INTERRUPT;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Set pipe configuration table */
+    if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN)        /* IN(receive) */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= USB_HOST_DIR_H_IN;
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN);             /* Compulsory SHTNAK */
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+                break;
+
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef  __USB_DMA_BFRE_ENABLE__
+                    /* this routine cannnot be perfomred if read operation is executed in buffer size */
+                    PipeCfg |= USB_HOST_BFREON;
+#endif
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        ret = USB_HOST_PIPE_IN;
+    }
+    else                                                            /* OUT(send)    */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+        }
+        PipeCfg |= USB_HOST_DIR_H_OUT;
+        ret = USB_HOST_PIPE_OUT;
+    }
+
+    switch (user_table->fifo_port)
+    {
+        case USB_HOST_CUSE:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+        break;
+
+        case USB_HOST_D0USE:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+        break;
+
+        case USB_HOST_D1USE:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+        break;
+
+        case USB_HOST_D0DMA:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+        break;
+
+        case USB_HOST_D1DMA:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Endpoint number set              */
+    PipeCfg  |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+    g_usb1_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+    /* Max packet size set              */
+    PipeMaxp  = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+    if (PipeMaxp == 0u)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    /* Set device address               */
+    PipeMaxp |= (uint16_t)(devadr << 12);
+
+    user_table->pipe_cfg         = PipeCfg;
+    user_table->pipe_max_pktsize = PipeMaxp;
+
+    usb1_host_resetEP(user_table);
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_resetEP
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+    uint16_t pipe;
+
+    /* Host pipe */
+    /* The pipe number of pipe definition table is obtained */
+    pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE);  /* Pipe Number */
+
+    /* FIFO port access pipe is set to initial value */
+    /* The connection with FIFO should be cut before setting the pipe */
+    if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
+                            USB_CFIFOSEL_CURPIPE_SHIFT,
+                            USB_CFIFOSEL_CURPIPE) == pipe)
+    {
+        usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb1_host_disable_brdy_int(pipe);
+    usb1_host_disable_nrdy_int(pipe);
+    usb1_host_disable_bemp_int(pipe);
+
+    /* Pipe to set is set to NAK */
+    usb1_host_set_pid_nak(pipe);
+
+    /* Pipe is set */
+    USB201.PIPESEL  = pipe;
+
+    USB201.PIPECFG  = tbl->pipe_cfg;
+    USB201.PIPEBUF  = tbl->pipe_buf;
+    USB201.PIPEMAXP = tbl->pipe_max_pktsize;
+    USB201.PIPEPERI = tbl->pipe_cycle;
+
+    g_usb1_host_pipecfg[pipe]  = tbl->pipe_cfg;
+    g_usb1_host_pipebuf[pipe]  = tbl->pipe_buf;
+    g_usb1_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+    g_usb1_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+    /* Sequence bit clear */
+    usb1_host_set_sqclr(pipe);
+
+    usb1_host_aclrm(pipe);
+    usb1_host_set_csclr(pipe);
+
+    /* Pipe window selection is set to unused */
+    USB201.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_data_count
+* Description  : Get g_usb0_host_data_count[pipe]
+* Arguments    : uint16_t pipe        ; Pipe Number
+*              : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS    ; success
+*              : DEVDRV_ERROR      ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+    if (pipe > USB_HOST_MAX_PIPE_NO)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    *data_count = g_usb1_host_PipeDataSize[pipe];
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/host/usb1_host_global.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb1_host_bit_set[16] =
+{
+    0x0001, 0x0002, 0x0004, 0x0008,
+    0x0010, 0x0020, 0x0040, 0x0080,
+    0x0100, 0x0200, 0x0400, 0x0800,
+    0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t  g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t  g_usb1_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t  g_usb1_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb1_host_DmaInfo[2];
+
+uint16_t  g_usb1_host_DmaPipe[2];
+uint16_t  g_usb1_host_DmaBval[2];
+uint16_t  g_usb1_host_DmaStatus[2];
+
+uint16_t  g_usb1_host_driver_state;
+uint16_t  g_usb1_host_ConfigNum;
+uint16_t  g_usb1_host_CmdStage;
+uint16_t  g_usb1_host_bchg_flag;
+uint16_t  g_usb1_host_detach_flag;
+uint16_t  g_usb1_host_attach_flag;
+
+uint16_t  g_usb1_host_UsbAddress;
+uint16_t  g_usb1_host_setUsbAddress;
+uint16_t  g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t  g_usb1_host_UsbDeviceSpeed;
+uint16_t  g_usb1_host_SupportUsbDeviceSpeed;
+
+uint16_t  g_usb1_host_SavReq;
+uint16_t  g_usb1_host_SavVal;
+uint16_t  g_usb1_host_SavIndx;
+uint16_t  g_usb1_host_SavLen;
+
+uint16_t  g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_init_pipe_status
+* Description  : Initialize pipe status.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_init_pipe_status (void)
+{
+    uint16_t loop;
+
+    g_usb1_host_ConfigNum = 0;
+
+    for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+    {
+        g_usb1_host_pipe_status[loop]   = USB_HOST_PIPE_IDLE;
+        g_usb1_host_PipeDataSize[loop]  = 0;
+
+        /* pipe configuration in usb1_host_resetEP() */
+        g_usb1_host_pipecfg[loop]  = 0;
+        g_usb1_host_pipebuf[loop]  = 0;
+        g_usb1_host_pipemaxp[loop] = 0;
+        g_usb1_host_pipeperi[loop] = 0;
+    }
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/host/usb1_host_usbint.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,509 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_interrupt1(void);
+static void usb1_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt
+* Description  : Executes USB interrupt.
+*              : Register this function in the USB interrupt handler.
+*              : Set CFIF0 in the pipe set before the interrupt after executing
+*              : this function.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt (uint32_t int_sense)
+{
+    uint16_t savepipe1;
+    uint16_t savepipe2;
+    uint16_t buffer;
+
+    savepipe1 = USB201.CFIFOSEL;
+    savepipe2 = USB201.PIPESEL;
+    usb1_host_interrupt1();
+
+    /* Control transmission changes ISEL within interruption processing. */
+    /* For this reason, write return of ISEL cannot be performed. */
+    buffer = USB201.CFIFOSEL;
+    buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+    buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+    USB201.CFIFOSEL = buffer;
+    USB201.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt1
+* Description  : Execue the USB interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt1 (void)
+{
+    uint16_t intsts0;
+    uint16_t intsts1;
+    uint16_t intenb0;
+    uint16_t intenb1;
+    uint16_t brdysts;
+    uint16_t nrdysts;
+    uint16_t bempsts;
+    uint16_t brdyenb;
+    uint16_t nrdyenb;
+    uint16_t bempenb;
+    volatile uint16_t dumy_sts;
+
+    intsts0 = USB201.INTSTS0;
+    intsts1 = USB201.INTSTS1;
+    intenb0 = USB201.INTENB0;
+    intenb1 = USB201.INTENB1;
+
+    if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+    {
+            USB201.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+            RZA_IO_RegWrite_16(&USB201.INTENB1,
+                                0,
+                                USB_INTENB1_BCHGE_SHIFT,
+                                USB_INTENB1_BCHGE);
+            g_usb1_host_bchg_flag = USB_HOST_YES;
+    }
+    else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+    }
+    else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+        g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+    }
+    else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+          && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+        RZA_IO_RegWrite_16(&USB201.INTENB1,
+                            0,
+                            USB_INTENB1_DTCHE_SHIFT,
+                            USB_INTENB1_DTCHE);
+        g_usb1_host_detach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb1_host_detach();
+
+        usb1_host_UsbDetach2();
+    }
+    else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+          && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+        RZA_IO_RegWrite_16(&USB201.INTENB1,
+                            0,
+                            USB_INTENB1_ATTCHE_SHIFT,
+                            USB_INTENB1_ATTCHE);
+        g_usb1_host_attach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb1_host_attach();
+
+        usb1_host_UsbAttach();
+    }
+    else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+    {
+        brdysts = USB201.BRDYSTS;
+        nrdysts = USB201.NRDYSTS;
+        bempsts = USB201.BEMPSTS;
+        brdyenb = USB201.BRDYENB;
+        nrdyenb = USB201.NRDYENB;
+        bempenb = USB201.BEMPENB;
+
+        if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+        {
+            usb1_host_BRDYInterrupt(brdysts, brdyenb);
+        }
+        else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+        {
+            usb1_host_BEMPInterrupt(bempsts, bempenb);
+        }
+        else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+        {
+            usb1_host_NRDYInterrupt(nrdysts, nrdyenb);
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Three dummy read for clearing interrupt requests */
+    dumy_sts = USB201.INTSTS0;
+    dumy_sts = USB201.INTSTS1;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BRDYInterrupt
+* Description  : Executes USB BRDY interrupt.
+* Arguments    : uint16_t Status   ; BRDYSTS Register Value
+*              : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB201.BRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+        switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+                usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+            break;
+
+            case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB201.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#else
+        switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_MODE_WRITE   | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+                usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+            break;
+
+            case (USB_HOST_MODE_READ   | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB201.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#endif
+    }
+    else
+    {
+        usb1_host_brdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB201.BRDYSTS;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_NRDYInterrupt
+* Description  : Executes USB NRDY interrupt.
+* Arguments    : uint16_t Status        ; NRDYSTS Register Value
+*              : uint16_t Int_enbl      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB201.NRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+        pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+
+        }
+        else if (pid  == USB_HOST_PID_NAK)
+        {
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        usb1_host_nrdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB201.NRDYSTS;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BEMPInterrupt
+* Description  : Executes USB BEMP interrupt.
+* Arguments    : uint16_t Status        ; BEMPSTS Register Value
+*              : uint16_t Int_enbl      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB201.BEMPSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+        pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+#if(1) /* ohci_wrapp */
+            switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                    ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                break;
+
+                case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb1_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#else
+            switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb1_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#endif
+        }
+    }
+    else
+    {
+        usb1_host_bemp_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB201.BEMPSTS;
+#if(1) /* mbed */
+    (void)dumy_sts;
+#endif
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/host/usb1_host_usbsig.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_EnableINT_Module(void);
+static void usb1_host_Enable_AttachINT(void);
+static void usb1_host_Disable_AttachINT(void);
+static void usb1_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_InitModule
+* Description  : Initializes the USB module in USB host module.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_InitModule (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+
+    usb1_host_init_pipe_status();
+
+    RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DCFM_SHIFT,
+                        USB_SYSCFG_DCFM);       /* HOST mode */
+    RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DRPD_SHIFT,
+                        USB_SYSCFG_DRPD);       /* PORT0 D+, D- setting */
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                        1,
+                        USB_SYSCFG_USBE_SHIFT,
+                        USB_SYSCFG_USBE);
+
+    USB201.CFIFOSEL  = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB201.D0FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB201.D1FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CheckAttach
+* Description  : Returns the USB device connection state.
+* Arguments    : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+*              :          ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb1_host_CheckAttach (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+    uint16_t rhst;
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_UNDECID)
+    {
+        if (buf1 == USB_HOST_FS_JSTS)
+        {
+            if (g_usb1_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+            {
+                RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                                    1,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            else
+            {
+                RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                                    0,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            return USB_HOST_ATTACH;
+        }
+        else if (buf1 == USB_HOST_LS_JSTS)
+        {
+            /* Low Speed Device */
+            RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                                0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE);
+            return USB_HOST_ATTACH;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+    {
+        return USB_HOST_ATTACH;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        return USB_HOST_ATTACH;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbAttach
+* Description  : Connects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbAttach (void)
+{
+    usb1_host_EnableINT_Module();
+    usb1_host_Disable_BchgINT();
+    usb1_host_Disable_AttachINT();
+    usb1_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach (void)
+{
+    uint16_t pipe;
+    uint16_t devadr;
+
+    g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+
+    /* Terminate all the pipes in which communications on port  */
+    /* are currently carried out                                */
+    for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+    {
+        if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+        {
+            if (pipe == USB_HOST_PIPE0)
+            {
+                devadr = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+                                            USB_DCPMAXP_DEVSEL_SHIFT,
+                                            USB_DCPMAXP_DEVSEL);
+            }
+            else
+            {
+                devadr = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+            }
+
+            if (devadr == g_usb1_host_UsbAddress)
+            {
+                usb1_host_stop_transfer(pipe);
+            }
+
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+        }
+    }
+
+    g_usb1_host_ConfigNum  = 0;
+    g_usb1_host_UsbAddress = 0;
+    g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb1_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach2
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach2 (void)
+{
+    usb1_host_Disable_DetachINT();
+    usb1_host_Disable_BchgINT();
+    usb1_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbBusReset
+* Description  : Issues the USB bus reset signal.
+* Arguments    : none
+* Return Value : uint16_t               ; RHST
+*******************************************************************************/
+uint16_t usb1_host_UsbBusReset (void)
+{
+    uint16_t buffer;
+    uint16_t loop;
+
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_USBRST_SHIFT,
+                        USB_DVSTCTR0_USBRST);
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb1_host_delay_xms(50);
+
+    buffer  = USB201.DVSTCTR0;
+    buffer &= (uint16_t)(~(USB_HOST_BITRST));
+    buffer |= USB_HOST_BITUACT;
+    USB201.DVSTCTR0 = buffer;
+
+    Userdef_USB_usb1_host_delay_xms(20);
+
+    for (loop = 0, buffer = USB_HOST_HSPROC;  loop < 3; ++loop)
+    {
+        buffer = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+                                    USB_DVSTCTR0_RHST_SHIFT,
+                                    USB_DVSTCTR0_RHST);
+        if (buffer == USB_HOST_HSPROC)
+        {
+            Userdef_USB_usb1_host_delay_xms(10);
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbResume
+* Description  : Issues the USB resume signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS
+*              :                    ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb1_host_UsbResume (void)
+{
+    uint16_t buf;
+
+    if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+    {
+        /* not SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_RESUME_SHIFT,
+                        USB_DVSTCTR0_RESUME);
+    Userdef_USB_usb1_host_delay_xms(20);
+
+    buf  = USB201.DVSTCTR0;
+    buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+    buf |= USB_HOST_BITUACT;
+    USB201.DVSTCTR0 = buf;
+
+    g_usb1_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbSuspend
+* Description  : Issues the USB suspend signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS   :not SUSPEND
+*              :                    ; DEVDRV_ERROR     :SUSPEND
+*******************************************************************************/
+int32_t usb1_host_UsbSuspend (void)
+{
+    uint16_t buf;
+
+    if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+    {
+        /* SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb1_host_delay_xms(5);
+
+    buf = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+    if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+    {
+        usb1_host_UsbDetach();
+    }
+    else
+    {
+        g_usb1_host_driver_state |= USB_HOST_DRV_SUSPEND;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_DetachINT
+* Description  : Enables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_DetachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        1,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_DetachINT
+* Description  : Disables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_DetachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_AttachINT
+* Description  : Enables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_AttachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        1,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_AttachINT
+* Description  : Disables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_AttachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_BchgINT
+* Description  : Disables the USB bus change detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_BchgINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_devadd
+* Description  : DEVADDn register is set by specified value
+* Arguments    : uint16_t addr             : Device address
+*              : uint16_t *devadd          : Set value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB201.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB201.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB201.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB201.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB201.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB201.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB201.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB201.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB201.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB201.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB201.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_devadd
+* Description  : DEVADDn register is obtained
+* Arguments    : uint16_t addr      : Device address
+*              : uint16_t *devadd   : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB201.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB201.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB201.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB201.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB201.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB201.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB201.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB201.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB201.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB201.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB201.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *devadd = *ptr;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_EnableINT_Module
+* Description  : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+*              : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_EnableINT_Module (void)
+{
+    uint16_t buf;
+
+    buf  = USB201.INTENB0;
+    buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+    USB201.INTENB0 = buf;
+
+    buf  = USB201.INTENB1;
+    buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+    USB201.INTENB1 = buf;
+
+    usb1_host_enable_nrdy_int(USB_HOST_PIPE0);
+    usb1_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/userdef/usb1_host_dmacdrv.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,704 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb1_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE   (255)       /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+    DMAC_REQ_MID,
+    DMAC_REQ_RID,
+    DMAC_REQ_AM,
+    DMAC_REQ_LVL,
+    DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] =
+{
+  /* MID,RID, AM,LVL,REQD */
+    { 32,  3,  2,  1,  1},      /* USB_0 channel 0 transmit FIFO empty */
+    { 32,  3,  2,  1,  0},      /* USB_0 channel 0 receive FIFO full   */
+    { 33,  3,  2,  1,  1},      /* USB_0 channel 1 transmit FIFO empty */
+    { 33,  3,  2,  1,  0},      /* USB_0 channel 1 receive FIFO full   */
+    { 34,  3,  2,  1,  1},      /* USB_1 channel 0 transmit FIFO empty */
+    { 34,  3,  2,  1,  0},      /* USB_1 channel 0 receive FIFO full   */
+    { 35,  3,  2,  1,  1},      /* USB_1 channel 1 transmit FIFO empty */
+    { 35,  3,  2,  1,  0},      /* USB_1 channel 1 receive FIFO full   */
+};
+
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 3.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 3 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC3.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC3.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC3.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC3_CHCFG_n_DAD_SHIFT,
+                            DMAC3_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC3_CHCFG_n_SAD_SHIFT,
+                            DMAC3_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC3_CHCFG_n_DDS_SHIFT,
+                            DMAC3_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC3_CHCFG_n_SDS_SHIFT,
+                            DMAC3_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_DMS_SHIFT,
+                            DMAC3_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_RSEL_SHIFT,
+                            DMAC3_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_SBE_SHIFT,
+                            DMAC3_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_DEM_SHIFT,
+                            DMAC3_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                1,
+                                DMAC3_CHCFG_n_REN_SHIFT,
+                                DMAC3_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                1,
+                                DMAC3_CHCFG_n_RSW_SHIFT,
+                                DMAC3_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                0,
+                                DMAC3_CHCFG_n_REN_SHIFT,
+                                DMAC3_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                0,
+                                DMAC3_CHCFG_n_RSW_SHIFT,
+                                DMAC3_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_TM_SHIFT,
+                            DMAC3_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            3,
+                            DMAC3_CHCFG_n_SEL_SHIFT,
+                            DMAC3_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            1,
+                            DMAC3_CHCFG_n_HIEN_SHIFT,
+                            DMAC3_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_LOEN_SHIFT,
+                            DMAC3_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC3_CHCFG_n_AM_SHIFT,
+                            DMAC3_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC3_CHCFG_n_LVL_SHIFT,
+                            DMAC3_CHCFG_n_LVL);
+        if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC3_CHCFG_n_REQD_SHIFT,
+                                DMAC3_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                req_direction,
+                                DMAC3_CHCFG_n_REQD_SHIFT,
+                                DMAC3_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC23_DMARS_CH3_RID_SHIFT,
+                            DMAC23_DMARS_CH3_RID);
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC23_DMARS_CH3_MID_SHIFT,
+                            DMAC23_DMARS_CH3_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Open
+* Description  : Enables DMAC channel 3 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC3_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_EN_SHIFT,
+                                DMAC3_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_TACT_SHIFT,
+                                DMAC3_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                            1,
+                            DMAC3_CHCTRL_n_SWRST_SHIFT,
+                            DMAC3_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
+                                DMAC3_CHCTRL_n_SWRST_SHIFT,
+                                DMAC3_CHCTRL_n_SWRST);
+#if(1) /* mbed */
+        (void)dummy;
+#endif
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                            1,
+                            DMAC3_CHCTRL_n_SETEN_SHIFT,
+                            DMAC3_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                                1,
+                                DMAC3_CHCTRL_n_STG_SHIFT,
+                                DMAC3_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Close
+* Description  : Aborts DMAC channel 3 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                        1,
+                        DMAC3_CHCTRL_n_CLREN_SHIFT,
+                        DMAC3_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_TACT_SHIFT,
+                                DMAC3_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_EN_SHIFT,
+                                DMAC3_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC3.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 3 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 3 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_SR_SHIFT,
+                                DMAC3_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC3.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC3.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC3.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC3.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC3.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC3.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 4.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 4 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC4.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC4.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC4.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC4_CHCFG_n_DAD_SHIFT,
+                            DMAC4_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC4_CHCFG_n_SAD_SHIFT,
+                            DMAC4_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC4_CHCFG_n_DDS_SHIFT,
+                            DMAC4_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC4_CHCFG_n_SDS_SHIFT,
+                            DMAC4_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_DMS_SHIFT,
+                            DMAC4_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_RSEL_SHIFT,
+                            DMAC4_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_SBE_SHIFT,
+                            DMAC4_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_DEM_SHIFT,
+                            DMAC4_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                1,
+                                DMAC4_CHCFG_n_REN_SHIFT,
+                                DMAC4_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                1,
+                                DMAC4_CHCFG_n_RSW_SHIFT,
+                                DMAC4_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                0,
+                                DMAC4_CHCFG_n_REN_SHIFT,
+                                DMAC4_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                0,
+                                DMAC4_CHCFG_n_RSW_SHIFT,
+                                DMAC4_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_TM_SHIFT,
+                            DMAC4_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            4,
+                            DMAC4_CHCFG_n_SEL_SHIFT,
+                            DMAC4_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            1,
+                            DMAC4_CHCFG_n_HIEN_SHIFT,
+                            DMAC4_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_LOEN_SHIFT,
+                            DMAC4_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC4_CHCFG_n_AM_SHIFT,
+                            DMAC4_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC4_CHCFG_n_LVL_SHIFT,
+                            DMAC4_CHCFG_n_LVL);
+        if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC4_CHCFG_n_REQD_SHIFT,
+                                DMAC4_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                req_direction,
+                                DMAC4_CHCFG_n_REQD_SHIFT,
+                                DMAC4_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC45.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC45_DMARS_CH4_RID_SHIFT,
+                            DMAC45_DMARS_CH4_RID);
+        RZA_IO_RegWrite_32(&DMAC45.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC45_DMARS_CH4_MID_SHIFT,
+                            DMAC45_DMARS_CH4_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Open
+* Description  : Enables DMAC channel 4 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC4_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_EN_SHIFT,
+                                DMAC4_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_TACT_SHIFT,
+                                DMAC4_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                            1,
+                            DMAC4_CHCTRL_n_SWRST_SHIFT,
+                            DMAC4_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
+                                DMAC4_CHCTRL_n_SWRST_SHIFT,
+                                DMAC4_CHCTRL_n_SWRST);
+#if(1) /* mbed */
+        (void)dummy;
+#endif
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                            1,
+                            DMAC4_CHCTRL_n_SETEN_SHIFT,
+                            DMAC4_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                                1,
+                                DMAC4_CHCTRL_n_STG_SHIFT,
+                                DMAC4_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Close
+* Description  : Aborts DMAC channel 4 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                        1,
+                        DMAC4_CHCTRL_n_CLREN_SHIFT,
+                        DMAC4_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_TACT_SHIFT,
+                                DMAC4_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_EN_SHIFT,
+                                DMAC4_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC4.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 4 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 4 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_SR_SHIFT,
+                                DMAC4_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC4.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC4.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC4.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC4.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC4.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC4.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb1/src/userdef/usb1_host_userdef.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,791 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb1_host.h"
+#include "devdrv_intc.h"        /* INTC Driver Header   */
+#include "usb1_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb1_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb1_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d0fifo_dmaintid
+* Description  : get D0FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d1fifo_dmaintid
+* Description  : get D1FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_attach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_attach (void)
+{
+//    printf("\n");
+//    printf("channel 1 attach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_detach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_detach (void)
+{
+//    printf("\n");
+//    printf("channel 1 detach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_1ms
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_1ms (void)
+{
+    osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_xms
+* Description  : Wait for the software in the period of time specified by the
+*              : argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_xms (uint32_t msec)
+{
+    osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_10us (uint32_t usec)
+{
+#if(1) /* ohci_wrapp */
+    volatile uint32_t i;
+#else
+    volatile int i;
+#endif
+
+    /* Wait 10us (Please change for your MCU) */
+    for (i = 0; i < usec; ++i)
+    {
+        Userdef_USB_usb1_host_delay_10us_2();
+    }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us_2
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb1_host_delay_10us_2 (void)
+{
+    volatile int i;
+    volatile unsigned long tmp;
+
+    /* Wait 1us (Please change for your MCU) */
+    for (i = 0; i < 14; ++i)
+    {
+        tmp = DUMMY_ACCESS;
+    }
+#if(1) /* mbed */
+    (void)tmp;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_500ns
+* Description  : Wait for software for 500ns.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_500ns (void)
+{
+#if(1) /* ohci_wrapp */
+#else
+    volatile int i;
+#endif
+    volatile unsigned long tmp;
+
+    /* Wait 500ns (Please change for your MCU) */
+    /* Wait 500ns I clock 266MHz */
+    tmp = DUMMY_ACCESS;
+#if(1) /* mbed */
+    (void)tmp;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_start_dma
+* Description  : Enables DMA transfer on the information specified by the argument.
+*              : Set DMAC register by this function to enable DMA transfer.
+*              : After executing this function, USB module is set to start DMA
+*              : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments    : USB_HOST_DMA_t *dma   : DMA parameter
+*              :  typedef struct{
+*              :      uint32_t fifo;    FIFO for using
+*              :      uint32_t buffer;  Start address of transfer source/destination
+*              :      uint32_t bytes;   Transfer size(Byte)
+*              :      uint32_t dir;     Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+*              :      uint32_t size;    DMA transfer size
+*              :   } USB_HOST_DMA_t;
+*              : uint16_t dfacc ; 0 : cycle steal mode
+*              :                  1 : 16byte continuous mode
+*              :                  2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+    uint32_t trncount;
+    uint32_t src;
+    uint32_t dst;
+    uint32_t size;
+    uint32_t dir;
+#ifdef CACHE_WRITEBACK
+    uint32_t ptr;
+#endif
+
+    trncount = dma->bytes;
+    dir      = dma->dir;
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        /* DxFIFO determination */
+        dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            src = (uint32_t)(&USB201.D0FIFO.UINT32);
+        }
+        else
+        {
+            src = (uint32_t)(&USB201.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            src += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB201.D0FIFO.UINT32);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB201.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            src += 3;       /* byte access  */
+        }
+#endif
+    }
+    else
+    {
+        /* DxFIFO determination */
+        src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+        }
+        else
+        {
+            dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            dst += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            dst += 3;       /* byte access  */
+        }
+#endif
+    }
+
+#ifdef CACHE_WRITEBACK
+    ptr = (uint32_t)dma->buffer;
+    if ((ptr & 0x20000000ul) == 0)
+    {
+        io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+    }
+#endif
+
+    if (dma->fifo == USB_HOST_D0FIFO_DMA)
+    {
+        usb1_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+    else
+    {
+        usb1_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac0
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t         request_factor = 0;
+    int32_t          ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor       = DMAC_REQ_USB1_DMA0_RX;   /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor       = DMAC_REQ_USB1_DMA0_TX;   /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb1_host_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC3_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb1_host_DMAC3_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC3 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac1
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t request_factor = 0;
+    int32_t  ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor =DMAC_REQ_USB1_DMA1_RX;          /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor =DMAC_REQ_USB1_DMA1_TX;          /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb1_host_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC4_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb1_host_DMAC4_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC4 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma0
+* Description  : Disables DMA transfer.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+* Notice       : This function should be executed to DMAC executed at the time
+*              : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma0 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb1_host_DMAC3_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma1
+* Description  : Disables DMA transfer.
+*              : This function should be executed to DMAC executed at the time
+*              : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma1 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb1_host_DMAC4_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_notice
+* Description  : Notice of USER
+* Arguments    : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_notice (const char * format)
+{
+//    printf(format);
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_user_rdy
+* Description  : This function notify a user and wait for trigger
+* Arguments    : const char *format
+*              :    uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_user_rdy (const char * format, uint16_t data)
+{
+//    printf(format, data);
+    getchar();
+
+    return;
+}
+
+/* End of File */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A1XX/usb_host_setting.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,109 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef USB_HOST_SETTING_H
+#define USB_HOST_SETTING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_HOST_CH                           0
+#define USB_HOST_HISPEED                      1
+
+#define INT_TRANS_MAX_NUM                     4    /* min:1 max:4 */
+#define ISO_TRANS_MAX_NUM                     0    /* min:0 max:2 */
+
+#ifdef MBED_CONF_APP_USB_HOST_CH
+#undef USB_HOST_CH
+#define USB_HOST_CH                           MBED_CONF_APP_USB_HOST_CH
+#endif
+#if defined(TARGET_GR_LYCHEE) /* mbed */
+#undef USB_HOST_CH
+#define USB_HOST_CH                           1
+#endif
+
+#if (USB_HOST_CH == 0)
+#include "usb0_host.h"
+#define USB20X                                USB200
+#define USBIXUSBIX                            USBI0_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed     g_usb0_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed            g_usb0_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage                  g_usb0_host_CmdStage
+#define g_usbx_host_pipe_status               g_usb0_host_pipe_status
+#define g_usbx_host_data_pointer              g_usb0_host_data_pointer
+#define g_usbx_host_data_count                g_usb0_host_data_count
+#define usbx_api_host_init                    usb0_api_host_init
+#define usbx_host_UsbBusReset                 usb0_host_UsbBusReset
+#define usbx_host_get_devadd                  usb0_host_get_devadd
+#define usbx_host_set_devadd                  usb0_host_set_devadd
+#define usbx_host_SetupStage                  usb0_host_SetupStage
+#define usbx_host_CtrlWriteStart              usb0_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart               usb0_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable        usb0_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer         usb0_host_start_send_transfer
+#define usbx_host_start_receive_transfer      usb0_host_start_receive_transfer
+#define usbx_host_stop_transfer               usb0_host_stop_transfer
+#define usbx_host_set_sqclr                   usb0_host_set_sqclr
+#define usbx_host_set_sqset                   usb0_host_set_sqset
+#define usbx_host_CheckAttach                 usb0_host_CheckAttach
+#define usbx_host_UsbDetach                   usb0_host_UsbDetach
+#define usbx_host_UsbAttach                   usb0_host_UsbAttach
+#define usbx_host_init_pipe_status            usb0_host_init_pipe_status
+#define usbx_host_get_sqmon                   usb0_host_get_sqmon
+#else
+#include "usb1_host.h"
+#define USB20X                                USB201
+#define USBIXUSBIX                            USBI1_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed     g_usb1_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed            g_usb1_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage                  g_usb1_host_CmdStage
+#define g_usbx_host_pipe_status               g_usb1_host_pipe_status
+#define g_usbx_host_data_pointer              g_usb1_host_data_pointer
+#define g_usbx_host_data_count                g_usb1_host_data_count
+#define usbx_api_host_init                    usb1_api_host_init
+#define usbx_host_UsbBusReset                 usb1_host_UsbBusReset
+#define usbx_host_get_devadd                  usb1_host_get_devadd
+#define usbx_host_set_devadd                  usb1_host_set_devadd
+#define usbx_host_SetupStage                  usb1_host_SetupStage
+#define usbx_host_CtrlWriteStart              usb1_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart               usb1_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable        usb1_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer         usb1_host_start_send_transfer
+#define usbx_host_start_receive_transfer      usb1_host_start_receive_transfer
+#define usbx_host_stop_transfer               usb1_host_stop_transfer
+#define usbx_host_set_sqclr                   usb1_host_set_sqclr
+#define usbx_host_set_sqset                   usb1_host_set_sqset
+#define usbx_host_CheckAttach                 usb1_host_CheckAttach
+#define usbx_host_UsbDetach                   usb1_host_UsbDetach
+#define usbx_host_UsbAttach                   usb1_host_UsbAttach
+#define usbx_host_init_pipe_status            usb1_host_init_pipe_status
+#define usbx_host_get_sqmon                   usb1_host_get_sqmon
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* USB_HOST_SETTING_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A2XX/NonCacheMem.c	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,480 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* @file         util.c
+* $Rev: 456 $
+* $Date:: 2014-07-08 19:47:01 +0900#$
+* @brief        Utilities
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+/***************************************************************************
+ * Platform Includes
+ ***************************************************************************/
+#include <string.h>
+
+/***************************************************************************
+ * SDK Includes
+ ***************************************************************************/
+#include "mbed_rtos_storage.h"
+#include "rtx_lib.h"
+#include "NonCacheMem.h"
+
+/***************************************************************************
+ * Application Includes
+ ***************************************************************************/
+
+/* Gather following contents by the component unit of the object. */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define MPL_TBL_MAX             (1L)
+
+#define CHK_ALIGN_4             (0x00000003uL)
+#define UTIL_MTX_WAIT_TIME      (0xFFFFFFFFuL)
+#define ADJOINING_PREV          (0x00000001uL)
+#define ADJOINING_NEXT          (0x00000002uL)
+
+/* error codes */
+#define R_UTIL_RET_OK              (0L)
+#define R_UTIL_RET_ERROR_RESOURCE  (-1L)
+#define R_UTIL_RET_ERROR_ID        (-2L)
+#define R_UTIL_RET_ERROR_ISR       (-3L)
+#define R_UTIL_RET_ERROR_TIMEOUT   (-4L)
+#define R_UTIL_RET_ERROR_INIT      (-5L)
+#define R_UTIL_RET_ERROR_PARAMETER (-6L)
+#define R_UTIL_RET_ERROR_PAR       (-7L)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+struct mem_struct
+{
+    struct mem_struct *     sp_next;
+    uint32_t                size;
+};
+typedef struct mem_struct mem_st;
+
+typedef struct
+{
+    osMutexId_t             pool_mtx_id;
+    uint32_t                total_size;
+    mem_st *                p_top_mem;
+    mem_st *                p_free_list;
+    mem_st *                p_use_list;
+} mpl_st;
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+/* OS resource definition */
+static mbed_rtos_storage_mutex_t _mtx_obj_mem[MPL_TBL_MAX];
+
+/* Memory definition */
+static mpl_st sa_mpl[MPL_TBL_MAX] = {
+    {NULL, 0, NULL, NULL, NULL}
+};
+
+static int32_t mem_id = -1;
+
+static int32_t R_UTIL_CreatePool(uint32_t const mpl_size, void * const p_mpl);
+//static int32_t R_UTIL_DeletePool(int32_t const pool_id);
+static int32_t R_UTIL_GetPool(int32_t const pool_id, uint32_t const get_size, void ** const pp_get_mem);
+static int32_t R_UTIL_RelPool(int32_t const pool_id, void * const p_rel_mem);
+
+void * AllocNonCacheMem(uint32_t len) {
+    static uint8_t non_cache_buf[1024 * 32] __attribute((section("NC_BSS"),aligned(4)));  //4 bytes aligned!
+    void * p_get_mem;
+
+    if (mem_id < 0) {
+        mem_id = R_UTIL_CreatePool(sizeof(non_cache_buf), (void *)non_cache_buf);
+    }
+    if (R_UTIL_GetPool(mem_id, len, &p_get_mem) != R_UTIL_RET_OK) {
+        p_get_mem = NULL;
+    }
+    return p_get_mem;
+}
+
+void FreeNonCacheMem(void * buf) {
+    R_UTIL_RelPool(mem_id, buf);
+}
+
+/**************************************************************************//**
+* Function Name: R_UTIL_CreatePool<br>
+* @brief         Memory pool create processing<br>
+*
+*                Description:<br>
+*                Process that returns the Memory pool control number of unused
+* @param[in]     mpl_size        :Size of the variable-size memory pool area (in bytes).
+* @param[in]     p_mpl           :Start address of the variable-size memory pool area.
+* @retval        R_UTIL_RET_OK             :Success.
+* @retval        R_UTIL_RET_ERROR_RESOURCE :Maximum resource count.
+* @retval        R_UTIL_RET_ERROR_ISR      :This API cannot be called from interrupt service routines.
+* @retval        R_UTIL_RET_ERROR_INIT     :Initialization isn't complete.
+* @retval        R_UTIL_RET_ERROR_PARAMETER:Parameter error.
+******************************************************************************/
+static int32_t R_UTIL_CreatePool(uint32_t const mpl_size, void * const p_mpl)
+{
+    int32_t result;
+
+    if ((p_mpl == NULL) || (mpl_size <= sizeof(mem_st))
+     || (((uint32_t)p_mpl & CHK_ALIGN_4) != 0uL) || ((mpl_size & CHK_ALIGN_4) != 0uL))
+    {
+        result = R_UTIL_RET_ERROR_PARAMETER;
+    }
+    else
+    {
+        int32_t  index;
+
+        result = R_UTIL_RET_ERROR_RESOURCE;
+        for (index = 0L; index < MPL_TBL_MAX; index++)
+        {
+            mpl_st * const sp_mpl = &sa_mpl[index];
+
+            if (sp_mpl->pool_mtx_id == NULL)
+            {
+                osMutexAttr_t attr = { 0 };
+                memset(&_mtx_obj_mem[index], 0, sizeof(os_mutex_t));
+                attr.name = "alloc_non_cache_mem_mutex";
+                attr.cb_mem = &_mtx_obj_mem[index];
+                attr.cb_size = sizeof(os_mutex_t);
+                attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+
+                osMutexId_t work_mtx_id = osMutexNew(&attr);
+
+                if (work_mtx_id != NULL)
+                {
+                    mem_st * const sp_mem = (mem_st *)p_mpl;
+
+                    sp_mem->sp_next         = NULL;
+                    sp_mem->size            = mpl_size;
+                    sp_mpl->total_size      = mpl_size;
+                    sp_mpl->p_top_mem       = sp_mem;
+                    sp_mpl->p_free_list     = sp_mem;
+                    sp_mpl->p_use_list      = NULL;
+                    sp_mpl->pool_mtx_id     = work_mtx_id;
+                    result                  = index;
+                }
+                break;
+            }
+        }
+    }
+
+    return result;
+}
+
+#if(0)
+/**************************************************************************//**
+* Function Name: R_UTIL_DeletePool<br>
+* @brief         Memory pool delete processing<br>
+*
+*                Description:<br>
+*                Removal process Memory pool<br>
+* @param[in]     pool_id         :Pool control number
+* @retval        R_UTIL_RET_OK             :Success.
+* @retval        R_UTIL_RET_ERROR_ID       :The parameter signal_id is incorrect.
+* @retval        R_UTIL_RET_ERROR_ISR      :This API cannot be called from interrupt service routines.
+* @retval        R_UTIL_RET_ERROR_INIT     :Initialization isn't complete.
+******************************************************************************/
+static int32_t R_UTIL_DeletePool(int32_t const pool_id)
+{
+    int32_t result;
+
+    /* Checks Arguments */
+    if ((pool_id < 0) || (pool_id >= MPL_TBL_MAX) || (sa_mpl[pool_id].pool_mtx_id == NULL))
+    {
+        result = R_UTIL_RET_ERROR_ID;
+    }
+    else
+    {
+        mpl_st * const sp_mpl = &sa_mpl[pool_id];
+
+        /* Deletes a specified memory pool */
+        (void)osMutexAcquire(sp_mpl->pool_mtx_id, UTIL_MTX_WAIT_TIME);
+        (void)osMutexDelete(sp_mpl->pool_mtx_id);
+        (void)memset(sp_mpl, 0, sizeof(mpl_st));
+        result = R_UTIL_RET_OK;
+    }
+
+    return result;
+}
+#endif
+
+/**************************************************************************//**
+* Function Name: R_UTIL_GetPool<br>
+* @brief         Memory get processing<br>
+*
+*                Description:<br>
+*                Memory get processing<br>
+* @param[in]     pool_id         :Pool control number
+* @param[in]     get_size        :Signals
+* @param[in]     p_get_mem       :Wait mode
+* @retval        R_UTIL_RET_OK             :Success.
+* @retval        R_UTIL_RET_ERROR_RESOURCE :Maximum resource count.
+* @retval        R_UTIL_RET_ERROR_ID       :The parameter signal_id is incorrect.
+* @retval        R_UTIL_RET_ERROR_ISR      :This API cannot be called from interrupt service routines.
+* @retval        R_UTIL_RET_ERROR_TIMEOUT  :Signal not occurred within timeout.
+* @retval        R_UTIL_RET_ERROR_INIT     :Initialization isn't complete.
+* @retval        R_UTIL_RET_ERROR_PARAMETER:Parameter error.
+******************************************************************************/
+static int32_t R_UTIL_GetPool(int32_t const pool_id, uint32_t const get_size, void ** const pp_get_mem)
+{
+    int32_t        result;
+    uint32_t const work_get_size = ((get_size + CHK_ALIGN_4) & ~CHK_ALIGN_4) + sizeof(mem_st);
+
+    /* Checks Arguments */
+    if ((pool_id < 0) || (pool_id >= MPL_TBL_MAX) || (sa_mpl[pool_id].pool_mtx_id == NULL))
+    {
+        result = R_UTIL_RET_ERROR_ID;
+    }
+    else if ((pp_get_mem == NULL) || (((uint32_t)pp_get_mem & CHK_ALIGN_4) != 0uL)
+          || (work_get_size >= sa_mpl[pool_id].total_size))
+    {
+        result = R_UTIL_RET_ERROR_PARAMETER;
+    }
+    /* Waits until a Mutex becomes available */
+    else if (osMutexAcquire(sa_mpl[pool_id].pool_mtx_id, UTIL_MTX_WAIT_TIME) != osOK)
+    {
+        result = R_UTIL_RET_ERROR_ISR;
+    }
+    else
+    {
+        mpl_st * const sp_mpl      = &sa_mpl[pool_id];
+        mem_st *  sp_free_mem      = sp_mpl->p_free_list;
+        mem_st *  sp_pre_mem       = NULL;
+        mem_st *  sp_bestfit_mem   = NULL;
+        mem_st ** spp_pre_mem_next = &sp_mpl->p_free_list;
+
+        /* Searches a usable space */
+        while (sp_free_mem != NULL)
+        {
+            if ((sp_free_mem->size >= work_get_size)
+             && ((sp_bestfit_mem == NULL) || ((sp_bestfit_mem->size) > (sp_free_mem->size))))
+            {
+                sp_bestfit_mem = sp_free_mem;
+                if (sp_pre_mem != NULL)
+                {
+                    spp_pre_mem_next = &sp_pre_mem->sp_next;
+                }
+                if (sp_free_mem->size == work_get_size)
+                {
+                    break;
+                }
+            }
+            sp_pre_mem  = sp_free_mem;
+            sp_free_mem = sp_free_mem->sp_next;
+        }
+
+        if (sp_bestfit_mem == NULL)
+        {
+            /* no usable space */
+            *pp_get_mem = NULL;
+            result      = R_UTIL_RET_ERROR_RESOURCE;
+        }
+        else
+        {
+            if ((sp_bestfit_mem->size - work_get_size) >= sizeof(mem_st))
+            {
+                /* Split the space, to use the first part. */
+                mem_st * const sp_next_free_mem = (mem_st *)((uint8_t *)sp_bestfit_mem + work_get_size);
+
+                sp_next_free_mem->size    = sp_bestfit_mem->size - work_get_size;
+                sp_next_free_mem->sp_next = sp_bestfit_mem->sp_next;
+                sp_bestfit_mem->size      = work_get_size;
+                *spp_pre_mem_next         = sp_next_free_mem;
+            }
+            else
+            {
+                /* Removed from the free-list. */
+                *spp_pre_mem_next = sp_bestfit_mem->sp_next;
+            }
+
+            /* Add to the top of the use-list. */
+            sp_bestfit_mem->sp_next = sp_mpl->p_use_list;
+            sp_mpl->p_use_list      = sp_bestfit_mem;
+
+            /* Set the memory space. */
+            *pp_get_mem = (void *)((uint8_t *)sp_bestfit_mem + sizeof(mem_st));
+            result      = R_UTIL_RET_OK;
+        }
+        (void)osMutexRelease(sp_mpl->pool_mtx_id);
+    }
+
+    return result;
+}
+
+/**************************************************************************//**
+* Function Name: R_UTIL_RelPool<br>
+* @brief         Signal wait processing<br>
+*
+*                Description:<br>
+*                Signal wait processing<br>
+* @param[in]     signal_id       :Signal control number
+* @param[in]     signals         :Signals
+* @param[in]     mode            :Wait mode
+* @param[in]     p_signal_ptn    :Signal pattern causing a task to be released form waiting
+* @param[in]     timeout         :Value of timeout[system tick].
+* @retval        R_UTIL_RET_OK             :Success.
+* @retval        R_UTIL_RET_ERROR_RESOURCE :Maximum resource count.
+* @retval        R_UTIL_RET_ERROR_ID       :The parameter signal_id is incorrect.
+* @retval        R_UTIL_RET_ERROR_ISR      :This API cannot be called from interrupt service routines.
+* @retval        R_UTIL_RET_ERROR_TIMEOUT  :Signal not occurred within timeout.
+* @retval        R_UTIL_RET_ERROR_INIT     :Initialization isn't complete.
+* @retval        R_UTIL_RET_ERROR_PARAMETER:Parameter error.
+******************************************************************************/
+static int32_t R_UTIL_RelPool(int32_t const pool_id, void * const p_rel_mem)
+{
+    int32_t result;
+
+    /* Checks Arguments */
+    if ((pool_id < 0) || (pool_id >= MPL_TBL_MAX) || (sa_mpl[pool_id].pool_mtx_id == NULL))
+    {
+        result = R_UTIL_RET_ERROR_ID;
+    }
+    else if ((p_rel_mem == NULL) || (((uint32_t)p_rel_mem & CHK_ALIGN_4) != 0uL) || ((uint32_t)p_rel_mem <= sizeof(mem_st)))
+    {
+        result = R_UTIL_RET_ERROR_PARAMETER;
+    }
+    else
+    {
+        mpl_st * const sp_mpl     = &sa_mpl[pool_id];
+        mem_st * const sp_del_mem = (mem_st *)(uint8_t *)((uint32_t)p_rel_mem - sizeof(mem_st));
+
+        /* Check the range of memory. */
+        if ((sp_del_mem < sp_mpl->p_top_mem)
+         || (((uint32_t)sp_del_mem + sp_del_mem->size) > ((uint32_t)sp_mpl->p_top_mem + sp_mpl->total_size)))
+        {
+            result = R_UTIL_RET_ERROR_PARAMETER;
+        }
+        /* Waits until a Mutex becomes available */
+        else if (osMutexAcquire(sa_mpl[pool_id].pool_mtx_id, UTIL_MTX_WAIT_TIME) != osOK)
+        {
+            result = R_UTIL_RET_ERROR_ISR;
+        }
+        else
+        {
+            mem_st *  sp_mem;
+            mem_st ** spp_pre_mem_next;
+            mem_st *  sp_pre_mem;
+
+            /* Check the memory has been registered in the use-list. */
+            sp_mem            = sp_mpl->p_use_list;
+            spp_pre_mem_next  = &sp_mpl->p_use_list;
+            sp_pre_mem        = NULL;
+            while (sp_mem != NULL)
+            {
+                if (sp_mem == sp_del_mem)
+                {
+                    /* Removed from the use-list. */
+                    if (sp_pre_mem != NULL)
+                    {
+                        spp_pre_mem_next = &sp_pre_mem->sp_next;
+                    }
+                    *spp_pre_mem_next  = sp_mem->sp_next;
+                    break;
+                }
+                sp_pre_mem = sp_mem;
+                sp_mem     = sp_mem->sp_next;
+            }
+            if (sp_mem == NULL)
+            {
+                /* It ends, when not registering with a use-list. */
+                result = R_UTIL_RET_ERROR_RESOURCE;
+            }
+            else
+            {
+                uint32_t  chek_flg        = 0uL;
+                mem_st *  sp_pre_address  = NULL;
+                mem_st *  sp_next_address = NULL;
+
+                /* It is searched whether there is any adjoining memory */
+                sp_mem            =  sp_mpl->p_free_list;
+                spp_pre_mem_next  =  &sp_mpl->p_free_list;
+                sp_pre_mem        =  NULL;
+                while ((sp_mem != NULL) && (chek_flg != (ADJOINING_PREV | ADJOINING_NEXT)))
+                {
+                    if (((uint32_t)sp_mem + sp_mem->size) == (uint32_t)sp_del_mem)
+                    {
+                        sp_pre_address  =  sp_mem;
+                        chek_flg        |= ADJOINING_PREV;
+                    }
+                    else if (((uint32_t)sp_del_mem + sp_del_mem->size) == (uint32_t)sp_mem)
+                    {
+                        sp_next_address =  sp_mem;
+                        if (sp_pre_mem != NULL)
+                        {
+                            spp_pre_mem_next = &sp_pre_mem->sp_next;
+                        }
+                        chek_flg        |= ADJOINING_NEXT;
+                    }
+                    else
+                    {
+                        /* Do Nothing */
+                    }
+                    sp_pre_mem = sp_mem;
+                    sp_mem     = sp_mem->sp_next;
+                }
+
+                if ((sp_pre_address != NULL) && (sp_next_address != NULL))
+                {
+                    /* It joins to the memory of previous and next. */
+                    *spp_pre_mem_next    =  sp_next_address->sp_next;
+                    sp_pre_address->size += (sp_del_mem->size + sp_next_address->size);
+                }
+                else if (sp_pre_address != NULL)
+                {
+                    /* It joints to the previous memory. */
+                    sp_pre_address->size += sp_del_mem->size;
+                }
+                else if (sp_next_address != NULL)
+                {
+                    /* It joints to the next memory. */
+                    *spp_pre_mem_next   =  sp_del_mem;
+                    sp_del_mem->sp_next =  sp_next_address->sp_next;
+                    sp_del_mem->size    += sp_next_address->size;
+                }
+                else
+                {
+                    /* It adds to the head of a free-list. */
+                    sp_del_mem->sp_next = sp_mpl->p_free_list;
+                    sp_mpl->p_free_list = sp_del_mem;
+                }
+                (void)osMutexRelease(sp_mpl->pool_mtx_id);
+                result = R_UTIL_RET_OK;
+            }
+        }
+    }
+
+    return result;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/TARGET_RENESAS/TARGET_RZ_A2XX/NonCacheMem.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef NON_CACHE_MEM_H
+#define NON_CACHE_MEM_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/* Gather following contents by the component unit of the object. */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+extern void * AllocNonCacheMem(uint32_t len);
+extern void FreeNonCacheMem(void * buf);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* NON_CACHE_MEM_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBDeviceConnected.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,124 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBDeviceConnected.h"
+#include "dbg.h"
+
+USBDeviceConnected::USBDeviceConnected() {
+    init();
+}
+
+void USBDeviceConnected::init() {
+    hub_nb = 0;
+    port = 0;
+    vid = 0;
+    pid = 0;
+    nb_interf = 0;
+    enumerated = false;
+    activeAddr = false;
+    sizeControlEndpoint = 8;
+    device_class = 0;
+    device_subclass = 0;
+    proto = 0;
+    speed = false;
+    for (int i = 0; i < MAX_INTF; i++) {
+        memset((void *)&intf[i], 0, sizeof(INTERFACE));
+        intf[i].in_use = false;
+        for (int j = 0; j < MAX_ENDPOINT_PER_INTERFACE; j++) {
+            intf[i].ep[j] = NULL;
+            strcpy(intf[i].name, "Unknown");
+        }
+    }
+    hub_parent = NULL;
+    hub = NULL;
+    nb_interf = 0;
+}
+
+INTERFACE * USBDeviceConnected::getInterface(uint8_t index) {
+    if (index >= MAX_INTF)
+        return NULL;
+
+    if (intf[index].in_use)
+        return &intf[index];
+
+    return NULL;
+}
+
+bool USBDeviceConnected::addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) {
+    if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use)) {
+        return false;
+    }
+    intf[intf_nb].in_use = true;
+    intf[intf_nb].intf_class = intf_class;
+    intf[intf_nb].intf_subclass = intf_subclass;
+    intf[intf_nb].intf_protocol = intf_protocol;
+    intf[intf_nb].nb_endpoint = 0;
+    return true;
+}
+
+bool USBDeviceConnected::addEndpoint(uint8_t intf_nb, USBEndpoint * ept) {
+    if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use == false) || (intf[intf_nb].nb_endpoint >= MAX_ENDPOINT_PER_INTERFACE)) {
+        return false;
+    }
+    intf[intf_nb].nb_endpoint++;
+
+    for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+        if (intf[intf_nb].ep[i] == NULL) {
+            intf[intf_nb].ep[i] = ept;
+            return true;
+        }
+    }
+    return false;
+}
+
+void USBDeviceConnected::init(uint8_t hub_, uint8_t port_, bool lowSpeed_) {
+    USB_DBG("init dev: %p", this);
+    init();
+    hub_nb = hub_;
+    port = port_;
+    speed = lowSpeed_;
+}
+
+void USBDeviceConnected::disconnect() {
+    for(int i = 0; i < MAX_INTF; i++) {
+        if (intf[i].detach) intf[i].detach.call();
+    }
+    init();
+}
+
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index) {
+    if (intf_nb >= MAX_INTF) {
+        return NULL;
+    }
+    for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+        if ((intf[intf_nb].ep[i]->getType() == type) && (intf[intf_nb].ep[i]->getDir() == dir)) {
+            if(index) {
+                index--;
+            } else {
+                return intf[intf_nb].ep[i];
+            }
+        }
+    }
+    return NULL;
+}
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, uint8_t index) {
+    if ((intf_nb >= MAX_INTF) || (index >= MAX_ENDPOINT_PER_INTERFACE)) {
+        return NULL;
+    }
+    return intf[intf_nb].ep[index];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBDeviceConnected.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,186 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBDEVICECONNECTED_H
+#define USBDEVICECONNECTED_H
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+#include "Callback.h"
+
+class USBHostHub;
+
+typedef struct {
+    bool in_use;
+    uint8_t nb_endpoint;
+    uint8_t intf_class;
+    uint8_t intf_subclass;
+    uint8_t intf_protocol;
+    USBEndpoint * ep[MAX_ENDPOINT_PER_INTERFACE];
+    Callback<void()> detach;
+    char name[10];
+} INTERFACE;
+
+/**
+* USBDeviceConnected class
+*/
+class USBDeviceConnected
+{
+public:
+
+    /**
+    * Constructor
+    */
+    USBDeviceConnected();
+
+    /**
+    * Attach an USBEndpoint to this device
+    *
+    * @param intf_nb interface number
+    * @param ep pointeur on the USBEndpoint which will be attached
+    * @returns true if successful, false otherwise
+    */
+    bool addEndpoint(uint8_t intf_nb, USBEndpoint * ep);
+
+    /**
+    * Retrieve an USBEndpoint by its TYPE and DIRECTION
+    *
+    * @param intf_nb the interface on which to lookup the USBEndpoint
+    * @param type type of the USBEndpoint looked for
+    * @param dir direction of the USBEndpoint looked for
+    * @param index the index of the USBEndpoint whitin the interface
+    * @returns pointer on the USBEndpoint if found, NULL otherwise
+    */
+    USBEndpoint * getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index = 0);
+
+    /**
+    * Retrieve an USBEndpoint by its index
+    *
+    * @param intf_nb interface number
+    * @param index index of the USBEndpoint
+    * @returns pointer on the USBEndpoint if found, NULL otherwise
+    */
+    USBEndpoint * getEndpoint(uint8_t intf_nb, uint8_t index);
+
+    /**
+    * Add a new interface to this device
+    *
+    * @param intf_nb interface number
+    * @param intf_class interface class
+    * @param intf_subclass interface subclass
+    * @param intf_protocol interface protocol
+    * @returns true if successful, false otherwise
+    */
+    bool addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol);
+
+    /**
+    * Get a specific interface
+    *
+    * @param index index of the interface to be fetched
+    * @returns interface
+    */
+    INTERFACE * getInterface(uint8_t index);
+
+    /**
+     *  Attach a member function to call when a the device has been disconnected
+     *
+     *  @param intf_nb interface number
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    inline void onDisconnect(uint8_t intf_nb, T* tptr, void (T::*mptr)(void)) {
+        if ((mptr != NULL) && (tptr != NULL)) {
+            onDisconnect(intf_nb, callback(tptr, mptr));
+        }
+    }
+
+    /**
+     * Attach a callback called when the device has been disconnected
+     *
+     *  @param intf_nb interface number
+     *  @param fn function pointer
+     */
+    inline void onDisconnect(uint8_t intf_nb, Callback<void()> fn) {
+        if (fn) {
+            intf[intf_nb].detach = fn;
+        }
+    }
+
+    /**
+    * Disconnect the device by calling a callback function registered by a driver
+    */
+    void disconnect();
+
+    // setters
+    void init(uint8_t hub, uint8_t port, bool lowSpeed);
+    inline void setAddress(uint8_t addr_) { addr = addr_; };
+    inline void setVid(uint16_t vid_) { vid = vid_; };
+    inline void setPid(uint16_t pid_) { pid = pid_; };
+    inline void setClass(uint8_t device_class_) { device_class = device_class_; };
+    inline void setSubClass(uint8_t device_subclass_) { device_subclass = device_subclass_; };
+    inline void setProtocol(uint8_t pr) { proto = pr; };
+    inline void setSizeControlEndpoint(uint32_t size) { sizeControlEndpoint = size; };
+    inline void activeAddress(bool active) { activeAddr = active; };
+    inline void setEnumerated() { enumerated = true; };
+    inline void setNbIntf(uint8_t nb_intf) {nb_interf = nb_intf; };
+    inline void setHubParent(USBHostHub * hub) { hub_parent = hub; };
+    inline void setName(const char * name_, uint8_t intf_nb) { strcpy(intf[intf_nb].name, name_); };
+
+    //getters
+    inline uint8_t     getPort() { return port; };
+    inline uint8_t     getHub() { return hub_nb; };
+    inline uint8_t     getAddress() { return addr; };
+    inline uint16_t    getVid() { return vid; };
+    inline uint16_t    getPid() { return pid; };
+    inline uint8_t     getClass() { return device_class; };
+    inline uint8_t     getSubClass() { return device_subclass; };
+    inline uint8_t     getProtocol() { return proto; };
+    inline bool        getSpeed() { return speed; };
+    inline uint32_t    getSizeControlEndpoint() { return sizeControlEndpoint; };
+    inline bool        isActiveAddress() { return activeAddr; };
+    inline bool        isEnumerated() { return enumerated; };
+    inline USBHostHub * getHubParent() { return hub_parent; };
+    inline uint8_t      getNbIntf() { return nb_interf; };
+    inline const char * getName(uint8_t intf_nb) { return intf[intf_nb].name; };
+
+    // in case this device is a hub
+    USBHostHub * hub;
+
+private:
+    USBHostHub * hub_parent;
+
+    INTERFACE intf[MAX_INTF];
+    uint32_t sizeControlEndpoint;
+    uint8_t hub_nb;
+    uint8_t port;
+    uint16_t vid;
+    uint16_t pid;
+    uint8_t addr;
+    uint8_t device_class;
+    uint8_t device_subclass;
+    uint8_t proto;
+    bool speed;
+    volatile bool activeAddr;
+    volatile bool enumerated;
+    uint8_t nb_interf;
+
+    void init();
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBEndpoint.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,163 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "dbg.h"
+#include "USBEndpoint.h"
+#if !defined(USBHOST_OTHER)
+void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD* td_list_[2])
+{
+    hced = hced_;
+    type = type_;
+    dir = dir_;
+    setup = (type == CONTROL_ENDPOINT) ? true : false;
+
+    //TDs have been allocated by the host
+    memcpy((HCTD**)td_list, td_list_, sizeof(HCTD*)*2); //TODO: Maybe should add a param for td_list size... at least a define
+    memset(td_list_[0], 0, sizeof(HCTD));
+    memset(td_list_[1], 0, sizeof(HCTD));
+
+    td_list[0]->ep = this;
+    td_list[1]->ep = this;
+
+    hced->control = 0;
+    //Empty queue
+    hced->tailTD = td_list[0];
+    hced->headTD = td_list[0];
+    hced->nextED = 0;
+
+    address = (ep_number & 0x7F) | ((dir - 1) << 7);
+
+    hced->control = ((ep_number & 0x7F) << 7)                         // Endpoint address
+                    | (type != CONTROL_ENDPOINT ? ( dir << 11) : 0 )  // direction : Out = 1, 2 = In
+                    | ((size & 0x3ff) << 16);                         // MaxPkt Size
+
+    transfer_len = 0;
+    transferred = 0;
+    buf_start = 0;
+    nextEp = NULL;
+
+    td_current = td_list[0];
+    td_next = td_list[1];
+
+    intf_nb = 0;
+
+    state = USB_TYPE_IDLE;
+}
+
+void USBEndpoint::setSize(uint32_t size)
+{
+    hced->control &= ~(0x3ff << 16);
+    hced->control |= (size << 16);
+}
+
+
+void USBEndpoint::setDeviceAddress(uint8_t addr)
+{
+    hced->control &= ~(0x7f);
+    hced->control |= (addr & 0x7F);
+}
+
+void USBEndpoint::setSpeed(uint8_t speed)
+{
+    hced->control &= ~(1 << 13);
+    hced->control |= (speed << 13);
+}
+#endif
+
+//Only for control Eps
+void USBEndpoint::setNextToken(uint32_t token)
+{
+    switch (token) {
+        case TD_SETUP:
+            dir = OUT;
+            setup = true;
+            break;
+        case TD_IN:
+            dir = IN;
+            setup = false;
+            break;
+        case TD_OUT:
+            dir = OUT;
+            setup = false;
+            break;
+    }
+}
+struct {
+    USB_TYPE type;
+    const char * str;
+} static type_string[] = {
+/*0*/   {USB_TYPE_OK, "USB_TYPE_OK"},
+        {USB_TYPE_CRC_ERROR, "USB_TYPE_CRC_ERROR"},
+        {USB_TYPE_BIT_STUFFING_ERROR, "USB_TYPE_BIT_STUFFING_ERROR"},
+        {USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR, "USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR"},
+        {USB_TYPE_STALL_ERROR, "USB_TYPE_STALL_ERROR"},
+/*5*/   {USB_TYPE_DEVICE_NOT_RESPONDING_ERROR, "USB_TYPE_DEVICE_NOT_RESPONDING_ERROR"},
+        {USB_TYPE_PID_CHECK_FAILURE_ERROR, "USB_TYPE_PID_CHECK_FAILURE_ERROR"},
+        {USB_TYPE_UNEXPECTED_PID_ERROR, "USB_TYPE_UNEXPECTED_PID_ERROR"},
+        {USB_TYPE_DATA_OVERRUN_ERROR, "USB_TYPE_DATA_OVERRUN_ERROR"},
+        {USB_TYPE_DATA_UNDERRUN_ERROR, "USB_TYPE_DATA_UNDERRUN_ERROR"},
+/*10*/  {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+        {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+        {USB_TYPE_BUFFER_OVERRUN_ERROR, "USB_TYPE_BUFFER_OVERRUN_ERROR"},
+        {USB_TYPE_BUFFER_UNDERRUN_ERROR, "USB_TYPE_BUFFER_UNDERRUN_ERROR"},
+        {USB_TYPE_DISCONNECTED, "USB_TYPE_DISCONNECTED"},
+/*15*/  {USB_TYPE_FREE, "USB_TYPE_FREE"},
+        {USB_TYPE_IDLE, "USB_TYPE_IDLE"},
+        {USB_TYPE_PROCESSING, "USB_TYPE_PROCESSING"},
+        {USB_TYPE_ERROR, "USB_TYPE_ERROR"}
+};
+const char * USBEndpoint::getStateString() {
+    return type_string[state].str;
+}
+
+#if !defined(USBHOST_OTHER)
+void USBEndpoint::setState(uint8_t st) {
+    if (st > 18)
+        return;
+    state = type_string[st].type;
+}
+
+USB_TYPE USBEndpoint::queueTransfer()
+{
+    transfer_len = (uint32_t)td_current->bufEnd - (uint32_t)td_current->currBufPtr + 1;
+    transferred = transfer_len;
+    buf_start = (uint8_t *)td_current->currBufPtr;
+
+    //Now add this free TD at this end of the queue
+    state = USB_TYPE_PROCESSING;
+    td_current->nextTD = (hcTd*)td_next;
+    hced->tailTD = td_next;
+    return USB_TYPE_PROCESSING;
+}
+
+void USBEndpoint::unqueueTransfer(volatile HCTD * td)
+{
+    td->control=0;
+    td->currBufPtr=0;
+    td->bufEnd=0;
+    td->nextTD=0;
+    hced->headTD = (HCTD *)((uint32_t)hced->tailTD | ((uint32_t)hced->headTD & 0x2)); //Carry bit
+    td_current = td_next;
+    td_next = td;
+}
+
+void USBEndpoint::queueEndpoint(USBEndpoint * ed)
+{
+    nextEp = ed;
+    hced->nextED = (ed == NULL) ? 0 : (hcEd*)(ed->getHCED());
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBEndpoint.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,179 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBENDPOINT_H
+#define USBENDPOINT_H
+
+#include "Callback.h"
+#include "USBHostTypes.h"
+#include "rtos.h"
+
+class USBDeviceConnected;
+
+/**
+* USBEndpoint class
+*/
+class USBEndpoint
+{
+public:
+    /**
+    * Constructor
+    */
+    USBEndpoint() {
+        state = USB_TYPE_FREE;
+        nextEp = NULL;
+    };
+
+    /**
+    * Initialize an endpoint
+    *
+    * @param hced hced associated to the endpoint
+    * @param type endpoint type
+    * @param dir endpoint direction
+    * @param size endpoint size
+    * @param ep_number endpoint number
+    * @param td_list array of two allocated transfer descriptors
+    */
+
+    void init(HCED * hced, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t ep_number, HCTD* td_list[2]);
+
+    /**
+    * Set next token. Warning: only useful for the control endpoint
+    *
+    * @param token IN, OUT or SETUP token
+    */
+    void setNextToken(uint32_t token);
+
+    /**
+    * Queue an endpoint
+    *
+    * @param endpoint endpoint which will be queued in the linked list
+    */
+    void queueEndpoint(USBEndpoint * endpoint);
+
+
+    /**
+    * Queue a transfer on the endpoint
+    */
+    USB_TYPE queueTransfer();
+
+    /**
+    * Unqueue a transfer from the endpoint
+    *
+    * @param td hctd which will be unqueued
+    */
+    void unqueueTransfer(volatile HCTD * td);
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     * @param func A pointer to a void function, or 0 to set as none
+     */
+    inline void attach(Callback<void()> func) {
+        rx = func;
+    }
+
+    /** Attach a function to call when touch panel int
+     *
+     * @param obj pointer to the object to call the member function on
+     * @param method pointer to the member function to be called
+     */
+    template<typename T>
+    inline void attach(T* obj, void (T::*method)()) {
+        // Underlying call thread safe
+        attach(callback(obj, method));
+    }
+
+    /**
+    * Call the handler associted to the end of a transfer
+    */
+    inline void call() {
+        if (rx)
+            rx.call();
+    };
+
+
+    // setters
+    inline void setState(USB_TYPE st) { state = st; }
+    void setState(uint8_t st);
+    void setDeviceAddress(uint8_t addr);
+    inline void setLengthTransferred(int len) { transferred = len; };
+    void setSpeed(uint8_t speed);
+    void setSize(uint32_t size);
+    inline void setDir(ENDPOINT_DIRECTION d) { dir = d; }
+    inline void setIntfNb(uint8_t intf_nb_) { intf_nb = intf_nb_; };
+
+    // getters
+    const char *                getStateString();
+    inline USB_TYPE             getState() { return state; }
+    inline ENDPOINT_TYPE        getType() { return type; };
+#ifdef  USBHOST_OTHER
+    inline uint8_t              getDeviceAddress() { return  device_address; };
+    inline uint32_t             getSize() { return size; };
+#else
+    inline uint8_t              getDeviceAddress() { return hced->control & 0x7f; };
+	inline uint32_t             getSize() { return (hced->control >> 16) & 0x3ff; };
+    inline volatile HCTD *      getHeadTD() { return (volatile HCTD*) ((uint32_t)hced->headTD & ~0xF); };
+#endif
+    inline int                  getLengthTransferred() { return transferred; }
+    inline uint8_t *            getBufStart() { return buf_start; }
+    inline uint8_t              getAddress(){ return address; };
+    inline volatile HCTD**      getTDList() { return td_list; };
+    inline volatile HCED *      getHCED() { return hced; };
+    inline ENDPOINT_DIRECTION   getDir() { return dir; }
+    inline volatile HCTD *      getProcessedTD() { return td_current; };
+    inline volatile HCTD*       getNextTD() { return td_current; };
+    inline bool                 isSetup() { return setup; }
+    inline USBEndpoint *        nextEndpoint() { return (USBEndpoint*)nextEp; };
+    inline uint8_t              getIntfNb() { return intf_nb; };
+
+    USBDeviceConnected * dev;
+
+    Queue<uint8_t, 1> ep_queue;
+
+private:
+    ENDPOINT_TYPE type;
+    volatile USB_TYPE state;
+    ENDPOINT_DIRECTION dir;
+#ifdef USBHOST_OTHER 
+	uint32_t size;
+	uint32_t ep_number;
+	uint32_t speed;
+    uint8_t device_address;
+#endif
+    bool setup;
+
+    uint8_t address;
+
+    int transfer_len;
+    int transferred;
+    uint8_t * buf_start;
+
+    Callback<void()> rx;
+
+    USBEndpoint* nextEp;
+
+    // USBEndpoint descriptor
+    volatile HCED * hced;
+
+    volatile HCTD * td_list[2];
+    volatile HCTD * td_current;
+    volatile HCTD * td_next;
+
+    uint8_t intf_nb;
+
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHALHost.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,169 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHALHOST_H
+#define USBHALHOST_H
+
+#include "USBHostTypes.h"
+#include "USBHostConf.h"
+
+class USBHostHub;
+
+/**
+* USBHALHost class
+*/
+class USBHALHost {
+protected:
+
+    /**
+    * Constructor
+    * init variables and memory where will be stored HCCA, ED and TD
+    */
+    USBHALHost();
+
+    /**
+    * Initialize host controller. Enable USB interrupts. This part is not in the constructor because,
+    * this function calls a virtual method if a device is already connected
+    */
+    void init();
+
+    /**
+    * reset the root hub
+    */
+    void resetRootHub();
+
+    /**
+    * return the value contained in the control HEAD ED register
+    *
+    * @returns address of the control Head ED
+    */
+    uint32_t controlHeadED();
+
+    /**
+    * return the value contained in the bulk HEAD ED register
+    *
+    * @returns address of the bulk head ED
+    */
+    uint32_t bulkHeadED();
+
+    /**
+    * return the value of the head interrupt ED contained in the HCCA
+    *
+    * @returns address of the head interrupt ED contained in the HCCA
+    */
+    uint32_t interruptHeadED();
+
+    /**
+    * Update the head ED for control transfers
+    */
+    void updateControlHeadED(uint32_t addr);
+
+    /**
+    * Update the head ED for bulk transfers
+    */
+    void updateBulkHeadED(uint32_t addr);
+
+    /**
+    * Update the head ED for interrupt transfers
+    */
+    void updateInterruptHeadED(uint32_t addr);
+
+    /**
+    * Enable List for the specified endpoint type
+    *
+    * @param type enable the list of ENDPOINT_TYPE type
+    */
+    void enableList(ENDPOINT_TYPE type);
+
+    /**
+    * Disable List for the specified endpoint type
+    *
+    * @param type disable the list of ENDPOINT_TYPE type
+    */
+    bool disableList(ENDPOINT_TYPE type);
+
+    /**
+    * Virtual method called when a device has been connected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param lowSpeed 1 if low speed, 0 otherwise
+    * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+    */
+    virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL) = 0;
+
+    /**
+    * Virtual method called when a device has been disconnected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+    * @param addr list of the TDs which have been completed to dequeue freed TDs
+    */
+    virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr) = 0;
+
+    /**
+    * Virtual method called when a transfer has been completed
+    *
+    * @param addr list of the TDs which have been completed
+    */
+    virtual void transferCompleted(volatile uint32_t addr) = 0;
+
+    /**
+    * Find a memory section for a new ED
+    *
+    * @returns the address of the new ED
+    */
+    volatile uint8_t * getED();
+
+    /**
+    * Find a memory section for a new TD
+    *
+    * @returns the address of the new TD
+    */
+    volatile uint8_t * getTD();
+
+    /**
+    * Release a previous memory section reserved for an ED
+    *
+    * @param ed address of the ED
+    */
+    void freeED(volatile uint8_t * ed);
+
+    /**
+    * Release a previous memory section reserved for an TD
+    *
+    * @param td address of the TD
+    */
+    void freeTD(volatile uint8_t * td);
+
+private:
+    static void _usbisr(void);
+    void UsbIrqhandler();
+
+    void memInit();
+
+    HCCA volatile * usb_hcca;           //256 bytes aligned
+    uint8_t volatile  * usb_edBuf;      //4 bytes aligned
+    uint8_t volatile  * usb_tdBuf;      //4 bytes aligned
+
+    static USBHALHost * instHost;
+
+    bool volatile  edBufAlloc[MAX_ENDPOINT];
+    bool volatile tdBufAlloc[MAX_TD];
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHALHost_LPC17.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,325 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC2460)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+// bits of the USB/OTG clock control register
+#define HOST_CLK_EN     (1<<0)
+#define DEV_CLK_EN      (1<<1)
+#define PORTSEL_CLK_EN  (1<<3)
+#define AHB_CLK_EN      (1<<4)
+
+// bits of the USB/OTG clock status register
+#define HOST_CLK_ON     (1<<0)
+#define DEV_CLK_ON      (1<<1)
+#define PORTSEL_CLK_ON  (1<<3)
+#define AHB_CLK_ON      (1<<4)
+
+// we need host clock, OTG/portsel clock and AHB clock
+#define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256)));  //256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+    instHost = this;
+    memInit();
+    memset((void*)usb_hcca, 0, HCCA_SIZE);
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        edBufAlloc[i] = false;
+    }
+    for (int i = 0; i < MAX_TD; i++) {
+        tdBufAlloc[i] = false;
+    }
+}
+
+void USBHALHost::init() {
+    NVIC_DisableIRQ(USB_IRQn);
+
+    //Cut power
+    LPC_SC->PCONP &= ~(1UL<<31);
+    wait_ms(100);
+
+    // turn on power for USB
+    LPC_SC->PCONP       |= (1UL<<31);
+
+    // Enable USB host clock, port selection and AHB clock
+    LPC_USB->USBClkCtrl |= CLOCK_MASK;
+
+    // Wait for clocks to become available
+    while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
+
+    // it seems the bits[0:1] mean the following
+    // 0: U1=device, U2=host
+    // 1: U1=host, U2=host
+    // 2: reserved
+    // 3: U1=host, U2=device
+    // NB: this register is only available if OTG clock (aka "port select") is enabled!!
+    // since we don't care about port 2, set just bit 0 to 1 (U1=host)
+    LPC_USB->OTGStCtrl |= 1;
+
+    // now that we've configured the ports, we can turn off the portsel clock
+    LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
+
+    // configure USB D+/D- pins
+    // P0[29] = USB_D+, 01
+    // P0[30] = USB_D-, 01
+    LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
+    LPC_PINCON->PINSEL1 |=  ((1<<26) | (1<<28));
+
+    LPC_USB->HcControl       = 0; // HARDWARE RESET
+    LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
+    LPC_USB->HcBulkHeadED    = 0; // Initialize Bulk list head to Zero
+
+    // Wait 100 ms before apply reset
+    wait_ms(100);
+
+    // software reset
+    LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
+
+    // Write Fm Interval and Largest Data Packet Counter
+    LPC_USB->HcFmInterval    = DEFAULT_FMINTERVAL;
+    LPC_USB->HcPeriodicStart = FI * 90 / 100;
+
+    // Put HC in operational state
+    LPC_USB->HcControl  = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+    // Set Global Power
+    LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
+
+    LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
+
+    // Clear Interrrupt Status
+    LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
+
+    LPC_USB->HcInterruptEnable  = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+
+    // Enable the USB Interrupt
+    NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+
+    NVIC_EnableIRQ(USB_IRQn);
+
+    // Check for any connected devices
+    if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+        //Device connected
+        wait_ms(150);
+        USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
+        deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+    }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+    return LPC_USB->HcControlHeadED;
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+    return LPC_USB->HcBulkHeadED;
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+    return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+    LPC_USB->HcBulkHeadED = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+    LPC_USB->HcControlHeadED = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+    usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
+            LPC_USB->HcControl |= OR_CONTROL_CLE;
+            break;
+        case ISOCHRONOUS_ENDPOINT:
+            break;
+        case BULK_ENDPOINT:
+            LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
+            LPC_USB->HcControl |= OR_CONTROL_BLE;
+            break;
+        case INTERRUPT_ENDPOINT:
+            LPC_USB->HcControl |= OR_CONTROL_PLE;
+            break;
+    }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            if(LPC_USB->HcControl & OR_CONTROL_CLE) {
+                LPC_USB->HcControl &= ~OR_CONTROL_CLE;
+                return true;
+            }
+            return false;
+        case ISOCHRONOUS_ENDPOINT:
+            return false;
+        case BULK_ENDPOINT:
+            if(LPC_USB->HcControl & OR_CONTROL_BLE){
+                LPC_USB->HcControl &= ~OR_CONTROL_BLE;
+                return true;
+            }
+            return false;
+        case INTERRUPT_ENDPOINT:
+            if(LPC_USB->HcControl & OR_CONTROL_PLE) {
+                LPC_USB->HcControl &= ~OR_CONTROL_PLE;
+                return true;
+            }
+            return false;
+    }
+    return false;
+}
+
+
+void USBHALHost::memInit() {
+    usb_hcca = (volatile HCCA *)usb_buf;
+    usb_edBuf = usb_buf + HCCA_SIZE;
+    usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED() {
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        if ( !edBufAlloc[i] ) {
+            edBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+        }
+    }
+    perror("Could not allocate ED\r\n");
+    return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+    int i;
+    for (i = 0; i < MAX_TD; i++) {
+        if ( !tdBufAlloc[i] ) {
+            tdBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+        }
+    }
+    perror("Could not allocate TD\r\n");
+    return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+    int i;
+    i = (ed - usb_edBuf) / ED_SIZE;
+    edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+    int i;
+    i = (td - usb_tdBuf) / TD_SIZE;
+    tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+    // Initiate port reset
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
+
+    while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
+
+    // ...and clear port reset signal
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+}
+
+
+void USBHALHost::_usbisr(void) {
+    if (instHost) {
+        instHost->UsbIrqhandler();
+    }
+}
+
+void USBHALHost::UsbIrqhandler() {
+    if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
+    {
+
+        uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
+
+        // Root hub status change interrupt
+        if (int_status & OR_INTR_STATUS_RHSC) {
+            if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
+                if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
+                    // When DRWE is on, Connect Status Change
+                    // means a remote wakeup event.
+                } else {
+
+                    //Root device connected
+                    if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+
+                        // wait 150ms to avoid bounce
+                        wait_ms(150);
+
+                        //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+                        deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+                    }
+
+                    //Root device disconnected
+                    else {
+
+                        if (!(int_status & OR_INTR_STATUS_WDH)) {
+                            usb_hcca->DoneHead = 0;
+                        }
+
+                        // wait 200ms to avoid bounce
+                        wait_ms(200);
+
+                        deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+                        if (int_status & OR_INTR_STATUS_WDH) {
+                            usb_hcca->DoneHead = 0;
+                            LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+                        }
+                    }
+                }
+                LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+            }
+            if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
+                LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+            }
+            LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
+        }
+
+        // Writeback Done Head interrupt
+        if (int_status & OR_INTR_STATUS_WDH) {
+            transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+            LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+        }
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHALHost_RZ_A1.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,282 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_RZ_A1XX)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+#include "ohci_wrapp_RZ_A1.h"
+
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+#define ALIGNE_MSK (0x0000000F)
+
+static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK];  //16 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+    instHost = this;
+    memInit();
+    memset((void*)usb_hcca, 0, HCCA_SIZE);
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        edBufAlloc[i] = false;
+    }
+    for (int i = 0; i < MAX_TD; i++) {
+        tdBufAlloc[i] = false;
+    }
+}
+
+void USBHALHost::init() {
+    ohciwrapp_init(&_usbisr);
+
+    ohciwrapp_reg_w(OHCI_REG_CONTROL, 1);       // HARDWARE RESET
+    ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
+    ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0);    // Initialize Bulk list head to Zero
+
+    // Wait 100 ms before apply reset
+    wait_ms(100);
+
+    // software reset
+    ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR);
+
+    // Write Fm Interval and Largest Data Packet Counter
+    ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL);
+    ohciwrapp_reg_w(OHCI_REG_PERIODICSTART,  FI * 90 / 100);
+
+    // Put HC in operational state
+    ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER);
+    // Set Global Power
+    ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC);
+
+    ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca));
+
+    // Clear Interrrupt Status
+    ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS));
+
+    ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC);
+
+    // Enable the USB Interrupt
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+
+    // Check for any connected devices
+    if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+        //Device connected
+        wait_ms(150);
+        USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1));
+        deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
+    }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+    return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED);
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+    return ohciwrapp_reg_r(OHCI_REG_BULKHEADED);
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+    return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+    ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr);
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+    ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr);
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+    usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+    uint32_t wk_data;
+
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF);
+            wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE);
+            ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+            break;
+        case ISOCHRONOUS_ENDPOINT:
+            break;
+        case BULK_ENDPOINT:
+            ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF);
+            wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE);
+            ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+            break;
+        case INTERRUPT_ENDPOINT:
+            wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE);
+            ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+            break;
+    }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+    uint32_t wk_data;
+
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+            if(wk_data & OR_CONTROL_CLE) {
+                wk_data &= ~OR_CONTROL_CLE;
+                ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+                return true;
+            }
+            return false;
+        case ISOCHRONOUS_ENDPOINT:
+            return false;
+        case BULK_ENDPOINT:
+            wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+            if(wk_data & OR_CONTROL_BLE) {
+                wk_data &= ~OR_CONTROL_BLE;
+                ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+                return true;
+            }
+            return false;
+        case INTERRUPT_ENDPOINT:
+            wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+            if(wk_data & OR_CONTROL_PLE) {
+                wk_data &= ~OR_CONTROL_PLE;
+                ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+                return true;
+            }
+            return false;
+    }
+    return false;
+}
+
+
+void USBHALHost::memInit() {
+    volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK);
+
+    usb_hcca = (volatile HCCA *)p_wk_buf;
+    usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE);
+    usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE));
+}
+
+volatile uint8_t * USBHALHost::getED() {
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        if ( !edBufAlloc[i] ) {
+            edBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+        }
+    }
+    perror("Could not allocate ED\r\n");
+    return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+    int i;
+    for (i = 0; i < MAX_TD; i++) {
+        if ( !tdBufAlloc[i] ) {
+            tdBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+        }
+    }
+    perror("Could not allocate TD\r\n");
+    return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+    int i;
+    i = (ed - usb_edBuf) / ED_SIZE;
+    edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+    int i;
+    i = (td - usb_tdBuf) / TD_SIZE;
+    tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+    // Initiate port reset
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS);
+
+    while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS);
+
+    // ...and clear port reset signal
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+}
+
+
+void USBHALHost::_usbisr(void) {
+    if (instHost) {
+        instHost->UsbIrqhandler();
+    }
+}
+
+void USBHALHost::UsbIrqhandler() {
+    uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
+    uint32_t data;
+
+    if (int_status != 0) { //Is there something to actually process?
+        // Root hub status change interrupt
+        if (int_status & OR_INTR_STATUS_RHSC) {
+            if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) {
+                if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) {
+                    // When DRWE is on, Connect Status Change
+                    // means a remote wakeup event.
+                } else {
+
+                    //Root device connected
+                    if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+
+                        // wait 150ms to avoid bounce
+                        wait_ms(150);
+
+                        //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+                        data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA;
+                        deviceConnected(0, 1, data);
+                    }
+
+                    //Root device disconnected
+                    else {
+                        deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+                    }
+                }
+                ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+            }
+            if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) {
+                ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+            }
+            ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC);
+        }
+
+        // Writeback Done Head interrupt
+        if (int_status & OR_INTR_STATUS_WDH) {
+            transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+            ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+        }
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHALHost_RZ_A2.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,316 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_RZ_A2XX)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+#include "pinmap.h"
+
+/**** User Selection ****/
+#if defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF)
+#define USB_HOST_CH        1
+#elif defined(TARGET_RZ_A2M_SBEV)
+#define USB_HOST_CH        0
+#endif
+
+#if USB_HOST_CH == 0
+#define USB_MX       USB01
+#define USBX0        USB00
+#define USBHIX_IRQn  USBHI0_IRQn
+#else
+#define USB_MX       USB11
+#define USBX0        USB10
+#define USBHIX_IRQn  USBHI1_IRQn
+#endif
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("NC_BSS"),aligned(256)));  //256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+    instHost = this;
+    memInit();
+    memset((void*)usb_hcca, 0, HCCA_SIZE);
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        edBufAlloc[i] = false;
+    }
+    for (int i = 0; i < MAX_TD; i++) {
+        tdBufAlloc[i] = false;
+    }
+}
+
+void USBHALHost::init() {
+    volatile uint8_t dummy_8;
+
+    GIC_DisableIRQ(USBHIX_IRQn);
+
+#if USB_HOST_CH == 0
+    pin_function(PC_6, 1); // VBUSEN0
+    pin_function(PC_7, 1); // OVRCUR0
+    CPG.STBCR6.BIT.MSTP61 = 0;
+    dummy_8 = CPG.STBCR6.BYTE;
+    CPG.STBREQ3.BYTE &= ~0x03;
+    dummy_8 = CPG.STBREQ3.BYTE;
+#else
+    pin_function(PC_0, 1); // VBUSIN1
+    pin_function(PC_5, 1); // VBUSEN1
+    pin_function(P7_5, 5); // OVRCUR1
+    CPG.STBCR6.BIT.MSTP60 = 0;
+    dummy_8 = CPG.STBCR6.BYTE;
+    CPG.STBREQ3.BYTE &= ~0x0C;
+    dummy_8 = CPG.STBREQ3.BYTE;
+#endif
+    (void)dummy_8;
+
+#if defined(TARGET_RZ_A2M_SBEV)
+    USBX0.PHYCLK_CTRL.BIT.UCLKSEL = 0;       /* EXTAL */
+#else
+    USBX0.PHYCLK_CTRL.BIT.UCLKSEL = 1;       /* USB_X1 */
+#endif
+
+    USBX0.PHYIF_CTRL.LONG = 0x00000000;
+    USBX0.COMMCTRL.BIT.OTG_PERI = 0;        /* 0 : Host, 1 : Peri */
+    USB_MX.LPSTS.WORD   |= 0x4000u;
+    USBX0.USBCTR.LONG = 0x00000000;
+    wait_ms(1);
+    USBX0.LINECTRL1.LONG = 0;
+
+    USBX0.HCCONTROL.LONG       = 0; // HARDWARE RESET
+    USBX0.HCCONTROLHEADED.LONG = 0; // Initialize Control list head to Zero
+    USBX0.HCBULKHEADED.LONG    = 0; // Initialize Bulk list head to Zero
+
+    wait_ms(1);
+    USBX0.HCRHPORTSTATUS1.LONG = 0x00000100;
+
+    // Wait 100 ms before apply reset
+    wait_ms(100);
+
+    // software reset
+    USBX0.HCCOMMANDSTATUS.LONG = OR_CMD_STATUS_HCR;
+
+    // Write Fm Interval and Largest Data Packet Counter
+    USBX0.HCFMINTERVAL.LONG    = DEFAULT_FMINTERVAL;
+    USBX0.HCPERIODICSTART.LONG = FI * 90 / 100;
+
+    // Put HC in operational state
+    USBX0.HCCONTROL.LONG  = (USBX0.HCCONTROL.LONG & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+    // Set Global Power
+    USBX0.HCRHSTATUS.LONG = OR_RH_STATUS_LPSC;
+
+    USBX0.HCHCCA.LONG = (uint32_t)(usb_hcca);
+
+    // Clear Interrrupt Status
+    USBX0.HCINTERRUPTSTATUS.LONG |= USBX0.HCINTERRUPTSTATUS.LONG;
+
+    USBX0.HCINTERRUPTENABLE.LONG  = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+
+    // Enable the USB Interrupt
+    InterruptHandlerRegister(USBHIX_IRQn, &_usbisr);
+    GIC_SetConfiguration(USBHIX_IRQn, 1);
+    GIC_SetPriority(USBHIX_IRQn, 0x80);
+
+    USBX0.INT_ENABLE.BIT.USBH_INTAEN = 1;
+    USBX0.REGEN_CG_CTRL.LONG = 0;
+
+    USBX0.HCRHPORTSTATUS1.LONG = OR_RH_PORT_CSC;
+    USBX0.HCRHPORTSTATUS1.LONG = OR_RH_PORT_PRSC;
+
+    GIC_EnableIRQ(USBHIX_IRQn);
+
+    // Check for any connected devices
+    if (USBX0.HCRHPORTSTATUS1.LONG & OR_RH_PORT_CCS) {
+        //Device connected
+        wait_ms(150);
+        USB_DBG("Device connected (%08x)\n\r", USBX0.HCRHPORTSTATUS1.LONG);
+        deviceConnected(0, 1, USBX0.HCRHPORTSTATUS1.LONG & OR_RH_PORT_LSDA);
+    }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+    return USBX0.HCCONTROLHEADED.LONG;
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+    return USBX0.HCBULKHEADED.LONG;
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+    return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+    USBX0.HCBULKHEADED.LONG = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+    USBX0.HCCONTROLHEADED.LONG = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+    usb_hcca->IntTable[0] = addr;
+}
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            USBX0.HCCOMMANDSTATUS.LONG = OR_CMD_STATUS_CLF;
+            USBX0.HCCONTROL.LONG |= OR_CONTROL_CLE;
+            break;
+        case ISOCHRONOUS_ENDPOINT:
+            break;
+        case BULK_ENDPOINT:
+            USBX0.HCCOMMANDSTATUS.LONG = OR_CMD_STATUS_BLF;
+            USBX0.HCCONTROL.LONG |= OR_CONTROL_BLE;
+            break;
+        case INTERRUPT_ENDPOINT:
+            USBX0.HCCONTROL.LONG |= OR_CONTROL_PLE;
+            break;
+    }
+}
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            if(USBX0.HCCONTROL.LONG & OR_CONTROL_CLE) {
+                USBX0.HCCONTROL.LONG &= ~OR_CONTROL_CLE;
+                return true;
+            }
+            return false;
+        case ISOCHRONOUS_ENDPOINT:
+            return false;
+        case BULK_ENDPOINT:
+            if(USBX0.HCCONTROL.LONG & OR_CONTROL_BLE){
+                USBX0.HCCONTROL.LONG &= ~OR_CONTROL_BLE;
+                return true;
+            }
+            return false;
+        case INTERRUPT_ENDPOINT:
+            if(USBX0.HCCONTROL.LONG & OR_CONTROL_PLE) {
+                USBX0.HCCONTROL.LONG &= ~OR_CONTROL_PLE;
+                return true;
+            }
+            return false;
+    }
+    return false;
+}
+
+void USBHALHost::memInit() {
+    usb_hcca = (volatile HCCA *)usb_buf;
+    usb_edBuf = usb_buf + HCCA_SIZE;
+    usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED() {
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        if ( !edBufAlloc[i] ) {
+            edBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+        }
+    }
+    perror("Could not allocate ED\r\n");
+    return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+    int i;
+    for (i = 0; i < MAX_TD; i++) {
+        if ( !tdBufAlloc[i] ) {
+            tdBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+        }
+    }
+    perror("Could not allocate TD\r\n");
+    return NULL; //Could not alloc TD
+}
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+    int i;
+    i = (ed - usb_edBuf) / ED_SIZE;
+    edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+    int i;
+    i = (td - usb_tdBuf) / TD_SIZE;
+    tdBufAlloc[i] = false;
+}
+
+void USBHALHost::resetRootHub() {
+    // Initiate port reset
+    USBX0.HCRHPORTSTATUS1.LONG = OR_RH_PORT_PRS;
+
+    while (USBX0.HCRHPORTSTATUS1.LONG & OR_RH_PORT_PRS);
+
+    // ...and clear port reset signal
+    USBX0.HCRHPORTSTATUS1.LONG = OR_RH_PORT_PRSC;
+}
+
+void USBHALHost::_usbisr(void) {
+    if (instHost) {
+        instHost->UsbIrqhandler();
+    }
+}
+
+void USBHALHost::UsbIrqhandler() {
+    if( USBX0.HCINTERRUPTSTATUS.LONG & USBX0.HCINTERRUPTENABLE.LONG ) //Is there something to actually process?
+    {
+
+        uint32_t int_status = USBX0.HCINTERRUPTSTATUS.LONG & USBX0.HCINTERRUPTENABLE.LONG;
+
+        // Root hub status change interrupt
+        if (int_status & OR_INTR_STATUS_RHSC) {
+            if (USBX0.HCRHPORTSTATUS1.LONG & OR_RH_PORT_CSC) {
+                if (USBX0.HCRHSTATUS.LONG & OR_RH_STATUS_DRWE) {
+                    // When DRWE is on, Connect Status Change
+                    // means a remote wakeup event.
+                } else {
+
+                    //Root device connected
+                    if (USBX0.HCRHPORTSTATUS1.LONG & OR_RH_PORT_CCS) {
+                        //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+                        deviceConnected(0, 1, USBX0.HCRHPORTSTATUS1.LONG & OR_RH_PORT_LSDA);
+                    }
+
+                    //Root device disconnected
+                    else {
+                        deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+                    }
+                }
+                USBX0.HCRHPORTSTATUS1.LONG = OR_RH_PORT_CSC;
+            }
+            if (USBX0.HCRHPORTSTATUS1.LONG & OR_RH_PORT_PRSC) {
+                USBX0.HCRHPORTSTATUS1.LONG = OR_RH_PORT_PRSC;
+            }
+            USBX0.HCINTERRUPTSTATUS.LONG = OR_INTR_STATUS_RHSC;
+        }
+
+        // Writeback Done Head interrupt
+        if (int_status & OR_INTR_STATUS_WDH) {
+            transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+            USBX0.HCINTERRUPTSTATUS.LONG = OR_INTR_STATUS_WDH;
+        }
+    }
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHost.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,1193 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "USBHost.h"
+#include "USBHostHub.h"
+
+USBHost * USBHost::instHost = NULL;
+
+#define DEVICE_CONNECTED_EVENT      (1 << 0)
+#define DEVICE_DISCONNECTED_EVENT   (1 << 1)
+#define TD_PROCESSED_EVENT          (1 << 2)
+
+#define MAX_TRY_ENUMERATE_HUB       3
+
+#define MIN(a, b) ((a > b) ? b : a)
+
+/**
+* How interrupts are processed:
+*    - new device connected:
+*       - a message is queued in queue_usb_event with the id DEVICE_CONNECTED_EVENT
+*       - when the usb_thread receives the event, it:
+*           - resets the device
+*           - reads the device descriptor
+*           - sets the address of the device
+*           - if it is a hub, enumerates it
+*   - device disconnected:
+*       - a message is queued in queue_usb_event with the id DEVICE_DISCONNECTED_EVENT
+*       - when the usb_thread receives the event, it:
+*           - free the device and all its children (hub)
+*   - td processed
+*       - a message is queued in queue_usb_event with the id TD_PROCESSED_EVENT
+*       - when the usb_thread receives the event, it:
+*           - call the callback attached to the endpoint where the td is attached
+*/
+void USBHost::usb_process() {
+
+    bool controlListState;
+    bool bulkListState;
+    bool interruptListState;
+    USBEndpoint * ep;
+    uint8_t i, j, res, timeout_set_addr = 10;
+#if defined(TARGET_RZ_A2XX)
+    uint8_t * buf = (uint8_t *)AllocNonCacheMem(8);
+#else
+    uint8_t buf[8];
+#endif
+    bool too_many_hub;
+    int idx;
+
+#if DEBUG_TRANSFER
+    uint8_t * buf_transfer;
+#endif
+
+#if MAX_HUB_NB
+    uint8_t k;
+#endif
+
+    while(1) {
+        osEvent evt = mail_usb_event.get();
+
+        if (evt.status == osEventMail) {
+
+            message_t * usb_msg = (message_t*)evt.value.p;
+
+            switch (usb_msg->event_id) {
+
+                // a new device has been connected
+                case DEVICE_CONNECTED_EVENT:
+                    too_many_hub = false;
+                    buf[4] = 0;
+
+                    do
+                    {
+                      Lock lock(this);
+
+                      for (i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+                          if (!deviceInUse[i]) {
+                              USB_DBG_EVENT("new device connected: %p\r\n", &devices[i]);
+                              devices[i].init(usb_msg->hub, usb_msg->port, usb_msg->lowSpeed);
+                              deviceReset[i] = false;
+                              deviceInited[i] = true;
+                              break;
+                          }
+                      }
+
+                      if (i == MAX_DEVICE_CONNECTED) {
+                          USB_ERR("Too many device connected!!\r\n");
+                          continue;
+                      }
+
+                      if (!controlEndpointAllocated) {
+                          control = newEndpoint(CONTROL_ENDPOINT, OUT, 0x08, 0x00);
+                          addEndpoint(NULL, 0, (USBEndpoint*)control);
+                          controlEndpointAllocated = true;
+                      }
+
+  #if MAX_HUB_NB
+                      if (usb_msg->hub_parent)
+                          devices[i].setHubParent((USBHostHub *)(usb_msg->hub_parent));
+  #endif
+
+                      for (j = 0; j < timeout_set_addr; j++) {
+
+                          resetDevice(&devices[i]);
+
+                          // set size of control endpoint
+                          devices[i].setSizeControlEndpoint(8);
+
+                          devices[i].activeAddress(false);
+
+                          // get first 8 bit of device descriptor
+                          // and check if we deal with a hub
+                          USB_DBG("usb_thread read device descriptor on dev: %p\r\n", &devices[i]);
+                          res = getDeviceDescriptor(&devices[i], buf, 8);
+
+                          if (res != USB_TYPE_OK) {
+                              USB_ERR("usb_thread could not read dev descr");
+                              continue;
+                          }
+
+                          // set size of control endpoint
+                          devices[i].setSizeControlEndpoint(buf[7]);
+
+                          // second step: set an address to the device
+                          res = setAddress(&devices[i], devices[i].getAddress());
+
+                          if (res != USB_TYPE_OK) {
+                              USB_ERR("SET ADDR FAILED");
+                              continue;
+                          }
+                          devices[i].activeAddress(true);
+                          USB_DBG("Address of %p: %d", &devices[i], devices[i].getAddress());
+
+                          // try to read again the device descriptor to check if the device
+                          // answers to its new address
+                          res = getDeviceDescriptor(&devices[i], buf, 8);
+
+                          if (res == USB_TYPE_OK) {
+                              break;
+                          }
+
+                          ThisThread::sleep_for(100);
+                      }
+
+                      USB_INFO("New device connected: %p [hub: %d - port: %d]", &devices[i], usb_msg->hub, usb_msg->port);
+
+  #if MAX_HUB_NB
+                      if (buf[4] == HUB_CLASS) {
+                          for (k = 0; k < MAX_HUB_NB; k++) {
+                              if (hub_in_use[k] == false) {
+                                  for (uint8_t j = 0; j < MAX_TRY_ENUMERATE_HUB; j++) {
+                                      if (hubs[k].connect(&devices[i])) {
+                                          devices[i].hub = &hubs[k];
+                                          hub_in_use[k] = true;
+                                          break;
+                                      }
+                                  }
+                                  if (hub_in_use[k] == true)
+                                      break;
+                              }
+                          }
+
+                          if (k == MAX_HUB_NB) {
+                              USB_ERR("Too many hubs connected!!\r\n");
+                              too_many_hub = true;
+                          }
+                      }
+
+                      if (usb_msg->hub_parent)
+                          ((USBHostHub *)(usb_msg->hub_parent))->deviceConnected(&devices[i]);
+  #endif
+
+                      if ((i < MAX_DEVICE_CONNECTED) && !too_many_hub) {
+                          deviceInUse[i] = true;
+                      }
+
+                    } while(0);
+
+                    break;
+
+                // a device has been disconnected
+                case DEVICE_DISCONNECTED_EVENT:
+
+                    do
+                    {
+                      Lock lock(this);
+
+                      controlListState = disableList(CONTROL_ENDPOINT);
+                      bulkListState = disableList(BULK_ENDPOINT);
+                      interruptListState = disableList(INTERRUPT_ENDPOINT);
+
+                      idx = findDevice(usb_msg->hub, usb_msg->port, (USBHostHub *)(usb_msg->hub_parent));
+                      if (idx != -1) {
+                          freeDevice((USBDeviceConnected*)&devices[idx]);
+                      }
+
+                      if (controlListState) enableList(CONTROL_ENDPOINT);
+                      if (bulkListState) enableList(BULK_ENDPOINT);
+                      if (interruptListState) enableList(INTERRUPT_ENDPOINT);
+
+                    } while(0);
+
+                    break;
+
+                // a td has been processed
+                // call callback on the ed associated to the td
+                // we are not in ISR -> users can use printf in their callback method
+                case TD_PROCESSED_EVENT:
+                    ep = (USBEndpoint *) ((HCTD *)usb_msg->td_addr)->ep;
+                    if (usb_msg->td_state == USB_TYPE_IDLE) {
+                        USB_DBG_EVENT("call callback on td %p [ep: %p state: %s - dev: %p - %s]", usb_msg->td_addr, ep, ep->getStateString(), ep->dev, ep->dev->getName(ep->getIntfNb()));
+
+#if DEBUG_TRANSFER
+                        if (ep->getDir() == IN) {
+                            buf_transfer = ep->getBufStart();
+                            printf("READ SUCCESS [%d bytes transferred - td: 0x%08X] on ep: [%p - addr: %02X]: ",  ep->getLengthTransferred(), usb_msg->td_addr, ep, ep->getAddress());
+                            for (int i = 0; i < ep->getLengthTransferred(); i++)
+                                printf("%02X ", buf_transfer[i]);
+                            printf("\r\n\r\n");
+                        }
+#endif
+                        ep->call();
+                    } else {
+                        idx = findDevice(ep->dev);
+                        if (idx != -1) {
+                            if (deviceInUse[idx]) {
+                                USB_WARN("td %p processed but not in idle state: %s [ep: %p - dev: %p - %s]", usb_msg->td_addr, ep->getStateString(), ep, ep->dev, ep->dev->getName(ep->getIntfNb()));
+                                ep->setState(USB_TYPE_IDLE);
+                            }
+                        }
+                    }
+                    break;
+            }
+
+            mail_usb_event.free(usb_msg);
+        }
+    }
+}
+
+USBHost::USBHost() : usbThread(osPriorityNormal, USB_THREAD_STACK)
+{
+#ifndef USBHOST_OTHER
+    headControlEndpoint = NULL;
+    headBulkEndpoint = NULL;
+    headInterruptEndpoint = NULL;
+    tailControlEndpoint = NULL;
+    tailBulkEndpoint = NULL;
+    tailInterruptEndpoint = NULL;
+#endif
+    lenReportDescr = 0;
+
+    controlEndpointAllocated = false;
+
+    for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        deviceInUse[i] = false;
+        devices[i].setAddress(i + 1);
+        deviceReset[i] = false;
+        deviceInited[i] = false;
+        for (uint8_t j = 0; j < MAX_INTF; j++)
+            deviceAttachedDriver[i][j] = false;
+    }
+
+#if MAX_HUB_NB
+    for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+        hubs[i].setHost(this);
+        hub_in_use[i] = false;
+    }
+#endif
+
+#if defined(TARGET_RZ_A2XX)
+    setupPacket = (uint8_t *)AllocNonCacheMem(8);
+    data        = (uint8_t *)AllocNonCacheMem(415);
+#endif
+    usbThread.start(callback(this, &USBHost::usb_process));
+}
+
+USBHost::Lock::Lock(USBHost* pHost) : m_pHost(pHost)
+{
+  m_pHost->usb_mutex.lock();
+}
+
+USBHost::Lock::~Lock()
+{
+  m_pHost->usb_mutex.unlock();
+}
+
+void USBHost::transferCompleted(volatile uint32_t addr)
+{
+    uint8_t state;
+
+    if(addr == 0)
+        return;
+
+    volatile HCTD* tdList = NULL;
+
+    //First we must reverse the list order and dequeue each TD
+    do {
+        volatile HCTD* td = (volatile HCTD*)addr;
+        addr = (uint32_t)td->nextTD; //Dequeue from physical list
+        td->nextTD = (hcTd*)tdList; //Enqueue into reversed list
+        tdList = td;
+    } while(addr);
+
+    while(tdList != NULL) {
+        volatile HCTD* td = tdList;
+        tdList = (volatile HCTD*)td->nextTD; //Dequeue element now as it could be modified below
+        if (td->ep != NULL) {
+            USBEndpoint * ep = (USBEndpoint *)(td->ep);
+
+#ifdef USBHOST_OTHER
+            state =  ((HCTD *)td)->state;
+            if (state == USB_TYPE_IDLE)
+                ep->setLengthTransferred((uint32_t)td->currBufPtr - (uint32_t)ep->getBufStart());
+
+#else
+            if (((HCTD *)td)->control >> 28) {
+                state = ((HCTD *)td)->control >> 28;
+            } else {
+                if (td->currBufPtr) {
+                    ep->setLengthTransferred((uint32_t)td->currBufPtr - (uint32_t)ep->getBufStart());
+                }
+                state = 16 /*USB_TYPE_IDLE*/;
+            }
+#endif
+
+            ep->unqueueTransfer(td);
+
+            if (ep->getType() != CONTROL_ENDPOINT) {
+                // callback on the processed td will be called from the usb_thread (not in ISR)
+                message_t * usb_msg = mail_usb_event.alloc();
+                usb_msg->event_id = TD_PROCESSED_EVENT;
+                usb_msg->td_addr = (void *)td;
+                usb_msg->td_state = state;
+                mail_usb_event.put(usb_msg);
+            }
+            ep->setState(state);
+            ep->ep_queue.put((uint8_t*)1);
+        }
+    }
+}
+
+USBHost * USBHost::getHostInst()
+{
+    if (instHost == NULL) {
+        instHost = new USBHost();
+        instHost->init();
+    }
+    return instHost;
+}
+
+
+/*
+ * Called when a device has been connected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent)
+{
+    // be sure that the new device connected is not already connected...
+    int idx = findDevice(hub, port, hub_parent);
+    if (idx != -1) {
+        if (deviceInited[idx])
+            return;
+    }
+
+    message_t * usb_msg = mail_usb_event.alloc();
+    usb_msg->event_id = DEVICE_CONNECTED_EVENT;
+    usb_msg->hub = hub;
+    usb_msg->port = port;
+    usb_msg->lowSpeed = lowSpeed;
+    usb_msg->hub_parent = hub_parent;
+    mail_usb_event.put(usb_msg);
+}
+
+/*
+ * Called when a device has been disconnected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr)
+{
+    // be sure that the device disconnected is connected...
+    int idx = findDevice(hub, port, hub_parent);
+    if (idx != -1) {
+        if (!deviceInUse[idx])
+            return;
+    } else {
+        return;
+    }
+
+    message_t * usb_msg = mail_usb_event.alloc();
+    usb_msg->event_id = DEVICE_DISCONNECTED_EVENT;
+    usb_msg->hub = hub;
+    usb_msg->port = port;
+    usb_msg->hub_parent = hub_parent;
+    mail_usb_event.put(usb_msg);
+}
+
+void USBHost::freeDevice(USBDeviceConnected * dev)
+{
+    USBEndpoint * ep = NULL;
+    HCED * ed = NULL;
+
+#if MAX_HUB_NB
+    if (dev->getClass() == HUB_CLASS) {
+        if (dev->hub == NULL) {
+            USB_ERR("HUB NULL!!!!!\r\n");
+        } else {
+            dev->hub->hubDisconnected();
+            for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+                if (dev->hub == &hubs[i]) {
+                    hub_in_use[i] = false;
+                    break;
+                }
+            }
+        }
+    }
+
+    // notify hub parent that this device has been disconnected
+    if (dev->getHubParent())
+        dev->getHubParent()->deviceDisconnected(dev);
+
+#endif
+
+    int idx = findDevice(dev);
+    if (idx != -1) {
+        deviceInUse[idx] = false;
+        deviceReset[idx] = false;
+
+        for (uint8_t j = 0; j < MAX_INTF; j++) {
+            deviceAttachedDriver[idx][j] = false;
+            if (dev->getInterface(j) != NULL) {
+                USB_DBG("FREE INTF %d on dev: %p, %p, nb_endpot: %d, %s", j, (void *)dev->getInterface(j), dev, dev->getInterface(j)->nb_endpoint, dev->getName(j));
+                for (int i = 0; i < dev->getInterface(j)->nb_endpoint; i++) {
+                    if ((ep = dev->getEndpoint(j, i)) != NULL) {
+#ifndef USBHOST_OTHER
+                        ed = (HCED *)ep->getHCED();
+                        ed->control |= (1 << 14); //sKip bit
+#endif
+                        unqueueEndpoint(ep);
+
+                        freeTD((volatile uint8_t*)ep->getTDList()[0]);
+                        freeTD((volatile uint8_t*)ep->getTDList()[1]);
+
+                        freeED((uint8_t *)ep->getHCED());
+                    }
+                    printList(BULK_ENDPOINT);
+                    printList(INTERRUPT_ENDPOINT);
+                }
+                USB_INFO("Device disconnected [%p - %s - hub: %d - port: %d]", dev, dev->getName(j), dev->getHub(), dev->getPort());
+            }
+        }
+        dev->disconnect();
+    }
+}
+
+
+void USBHost::unqueueEndpoint(USBEndpoint * ep)
+{
+#ifdef USBHOST_OTHER
+    ep->setState(USB_TYPE_FREE);
+#else
+    USBEndpoint * prec = NULL;
+    USBEndpoint * current = NULL;
+
+    for (int i = 0; i < 2; i++) {
+        current = (i == 0) ? (USBEndpoint*)headBulkEndpoint : (USBEndpoint*)headInterruptEndpoint;
+        prec = current;
+        while (current != NULL) {
+            if (current == ep) {
+                if (current->nextEndpoint() != NULL) {
+                    prec->queueEndpoint(current->nextEndpoint());
+                    if (current == headBulkEndpoint) {
+                        updateBulkHeadED((uint32_t)current->nextEndpoint()->getHCED());
+                        headBulkEndpoint = current->nextEndpoint();
+                    } else if (current == headInterruptEndpoint) {
+                        updateInterruptHeadED((uint32_t)current->nextEndpoint()->getHCED());
+                        headInterruptEndpoint = current->nextEndpoint();
+                    }
+                }
+                // here we are dequeuing the queue of ed
+                // we need to update the tail pointer
+                else {
+                    prec->queueEndpoint(NULL);
+                    if (current == headBulkEndpoint) {
+                        updateBulkHeadED(0);
+                        headBulkEndpoint = current->nextEndpoint();
+                    } else if (current == headInterruptEndpoint) {
+                        updateInterruptHeadED(0);
+                        headInterruptEndpoint = current->nextEndpoint();
+                    }
+
+                    // modify tail
+                    switch (current->getType()) {
+                        case BULK_ENDPOINT:
+                            tailBulkEndpoint = prec;
+                            break;
+                        case INTERRUPT_ENDPOINT:
+                            tailInterruptEndpoint = prec;
+                            break;
+                        default:
+                            break;
+                    }
+                }
+                current->setState(USB_TYPE_FREE);
+                return;
+            }
+            prec = current;
+            current = current->nextEndpoint();
+        }
+    }
+#endif
+}
+
+
+USBDeviceConnected * USBHost::getDevice(uint8_t index)
+{
+    if ((index >= MAX_DEVICE_CONNECTED) || (!deviceInUse[index])) {
+        return NULL;
+    }
+    return (USBDeviceConnected*)&devices[index];
+}
+
+// create an USBEndpoint descriptor. the USBEndpoint is not linked
+USBEndpoint * USBHost::newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr)
+{
+    int i = 0;
+    HCED * ed = (HCED *)getED();
+    HCTD* td_list[2] = { (HCTD*)getTD(), (HCTD*)getTD() };
+
+    memset((void *)td_list[0], 0x00, sizeof(HCTD));
+    memset((void *)td_list[1], 0x00, sizeof(HCTD));
+
+    // search a free USBEndpoint
+    for (i = 0; i < MAX_ENDPOINT; i++) {
+        if (endpoints[i].getState() == USB_TYPE_FREE) {
+            endpoints[i].init(ed, type, dir, size, addr, td_list);
+            USB_DBG("USBEndpoint created (%p): type: %d, dir: %d, size: %d, addr: %d, state: %s", &endpoints[i], type, dir, size, addr, endpoints[i].getStateString());
+            return &endpoints[i];
+        }
+    }
+    USB_ERR("could not allocate more endpoints!!!!");
+    return NULL;
+}
+
+
+USB_TYPE USBHost::resetDevice(USBDeviceConnected * dev)
+{
+    int index = findDevice(dev);
+    if (index != -1) {
+        USB_DBG("Resetting hub %d, port %d\n", dev->getHub(), dev->getPort());
+        ThisThread::sleep_for(100);
+        if (dev->getHub() == 0) {
+            resetRootHub();
+        }
+#if MAX_HUB_NB
+        else {
+            dev->getHubParent()->portReset(dev->getPort());
+        }
+#endif
+        ThisThread::sleep_for(100);
+        deviceReset[index] = true;
+        return USB_TYPE_OK;
+    }
+
+    return USB_TYPE_ERROR;
+}
+
+// link the USBEndpoint to the linked list and attach an USBEndpoint to a device
+bool USBHost::addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep)
+{
+
+    if (ep == NULL) {
+        return false;
+    }
+
+#ifndef USBHOST_OTHER
+    HCED * prevEd;
+
+#endif
+    // set device address in the USBEndpoint descriptor
+    if (dev == NULL) {
+        ep->setDeviceAddress(0);
+    } else {
+        ep->setDeviceAddress(dev->getAddress());
+    }
+
+    if ((dev != NULL) && dev->getSpeed()) {
+        ep->setSpeed(dev->getSpeed());
+    }
+
+    ep->setIntfNb(intf_nb);
+
+#ifndef USBHOST_OTHER
+    // queue the new USBEndpoint on the ED list
+    switch (ep->getType()) {
+
+        case CONTROL_ENDPOINT:
+            prevEd = ( HCED*) controlHeadED();
+            if (!prevEd) {
+                updateControlHeadED((uint32_t) ep->getHCED());
+                USB_DBG_TRANSFER("First control USBEndpoint: %08X", (uint32_t) ep->getHCED());
+                headControlEndpoint = ep;
+                tailControlEndpoint = ep;
+                return true;
+            }
+            tailControlEndpoint->queueEndpoint(ep);
+            tailControlEndpoint = ep;
+            return true;
+
+        case BULK_ENDPOINT:
+            prevEd = ( HCED*) bulkHeadED();
+            if (!prevEd) {
+                updateBulkHeadED((uint32_t) ep->getHCED());
+                USB_DBG_TRANSFER("First bulk USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+                headBulkEndpoint = ep;
+                tailBulkEndpoint = ep;
+                break;
+            }
+            USB_DBG_TRANSFER("Queue BULK Ed %p after %p\r\n",ep->getHCED(), prevEd);
+            tailBulkEndpoint->queueEndpoint(ep);
+            tailBulkEndpoint = ep;
+            break;
+
+        case INTERRUPT_ENDPOINT:
+            prevEd = ( HCED*) interruptHeadED();
+            if (!prevEd) {
+                updateInterruptHeadED((uint32_t) ep->getHCED());
+                USB_DBG_TRANSFER("First interrupt USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+                headInterruptEndpoint = ep;
+                tailInterruptEndpoint = ep;
+                break;
+            }
+            USB_DBG_TRANSFER("Queue INTERRUPT Ed %p after %p\r\n",ep->getHCED(), prevEd);
+            tailInterruptEndpoint->queueEndpoint(ep);
+            tailInterruptEndpoint = ep;
+            break;
+        default:
+            return false;
+    }
+
+#endif
+    ep->dev = dev;
+    dev->addEndpoint(intf_nb, ep);
+
+    return true;
+}
+
+
+int USBHost::findDevice(USBDeviceConnected * dev)
+{
+    for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        if (dev == &devices[i]) {
+            return i;
+        }
+    }
+    return -1;
+}
+
+int USBHost::findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent)
+{
+    for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        if (devices[i].getHub() == hub && devices[i].getPort() == port) {
+            if (hub_parent != NULL) {
+                if (hub_parent == devices[i].getHubParent())
+                    return i;
+            } else {
+                return i;
+            }
+        }
+    }
+    return -1;
+}
+
+void USBHost::printList(ENDPOINT_TYPE type)
+{
+#if (DEBUG_EP_STATE) && !defined(USBHOST_OTHER)
+    volatile HCED * hced;
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            hced = (HCED *)controlHeadED();
+            break;
+        case BULK_ENDPOINT:
+            hced = (HCED *)bulkHeadED();
+            break;
+        case INTERRUPT_ENDPOINT:
+            hced = (HCED *)interruptHeadED();
+            break;
+    }
+    volatile HCTD * hctd = NULL;
+    const char * type_str = (type == BULK_ENDPOINT) ? "BULK" :
+                            ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" :
+                            ((type == CONTROL_ENDPOINT) ? "CONTROL" : "ISOCHRONOUS"));
+    printf("State of %s:\r\n", type_str);
+    while (hced != NULL) {
+        uint8_t dir = ((hced->control & (3 << 11)) >> 11);
+        printf("hced: %p [ADDR: %d, DIR: %s, EP_NB: 0x%X]\r\n", hced,
+                                                   hced->control & 0x7f,
+                                                   (dir == 1) ? "OUT" : ((dir == 0) ? "FROM_TD":"IN"),
+                                                    (hced->control & (0xf << 7)) >> 7);
+        hctd = (HCTD *)((uint32_t)(hced->headTD) & ~(0xf));
+        while (hctd != hced->tailTD) {
+            printf("\thctd: %p [DIR: %s]\r\n", hctd, ((hctd->control & (3 << 19)) >> 19) == 1 ? "OUT" : "IN");
+            hctd = hctd->nextTD;
+        }
+        printf("\thctd: %p\r\n", hctd);
+        hced = hced->nextED;
+    }
+    printf("\r\n\r\n");
+#endif
+}
+
+
+// add a transfer on the TD linked list
+USB_TYPE USBHost::addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len)
+{
+    USB_TYPE ret=USB_TYPE_PROCESSING;
+	td_mutex.lock();
+
+    // allocate a TD which will be freed in TDcompletion
+    volatile HCTD * td = ed->getNextTD();
+    if (td == NULL) {
+        return USB_TYPE_ERROR;
+    }
+
+#ifndef USBHOST_OTHER 
+    uint32_t token = (ed->isSetup() ? TD_SETUP : ( (ed->getDir() == IN) ? TD_IN : TD_OUT ));
+
+    uint32_t td_toggle;
+
+    if (ed->getType() == CONTROL_ENDPOINT) {
+        if (ed->isSetup()) {
+            td_toggle = TD_TOGGLE_0;
+        } else {
+            td_toggle = TD_TOGGLE_1;
+        }
+    } else {
+        td_toggle = 0;
+    }
+
+    td->control      = (TD_ROUNDING | token | TD_DELAY_INT(0) | td_toggle | TD_CC);
+    td->currBufPtr   = buf;
+    td->bufEnd       = (buf + (len - 1));
+
+    ENDPOINT_TYPE type = ed->getType();
+
+    disableList(type);
+    ed->queueTransfer();
+    printList(type);
+    enableList(type);
+#else
+	/*  call method specific for endpoint  */
+	td->currBufPtr   = buf;
+	td->size = len;
+	ret = ed->queueTransfer();
+#endif
+
+    td_mutex.unlock();
+
+    return ret;
+}
+
+
+
+USB_TYPE USBHost::getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr)
+{
+    USB_TYPE t = controlRead(  dev,
+                         USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+                         GET_DESCRIPTOR,
+                         (DEVICE_DESCRIPTOR << 8) | (0),
+                         0, buf, MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf));
+    if (len_dev_descr)
+        *len_dev_descr = MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf);
+
+    return t;
+}
+
+USB_TYPE USBHost::getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr)
+{
+    USB_TYPE res;
+    uint16_t total_conf_descr_length = 0;
+
+    // fourth step: get the beginning of the configuration descriptor to have the total length of the conf descr
+    res = controlRead(  dev,
+                        USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+                        GET_DESCRIPTOR,
+                        (CONFIGURATION_DESCRIPTOR << 8) | (0),
+                        0, buf, CONFIGURATION_DESCRIPTOR_LENGTH);
+
+    if (res != USB_TYPE_OK) {
+        USB_ERR("GET CONF 1 DESCR FAILED");
+        return res;
+    }
+    total_conf_descr_length = buf[2] | (buf[3] << 8);
+    total_conf_descr_length = MIN(max_len_buf, total_conf_descr_length);
+
+    if (len_conf_descr)
+        *len_conf_descr = total_conf_descr_length;
+
+    USB_DBG("TOTAL_LENGTH: %d \t NUM_INTERF: %d", total_conf_descr_length, buf[4]);
+
+    return controlRead(  dev,
+                         USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+                         GET_DESCRIPTOR,
+                         (CONFIGURATION_DESCRIPTOR << 8) | (0),
+                         0, buf, total_conf_descr_length);
+}
+
+
+USB_TYPE USBHost::setAddress(USBDeviceConnected * dev, uint8_t address) {
+    return controlWrite(    dev,
+                            USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+                            SET_ADDRESS,
+                            address,
+                            0, NULL, 0);
+
+}
+
+USB_TYPE USBHost::setConfiguration(USBDeviceConnected * dev, uint8_t conf)
+{
+    return controlWrite( dev,
+                         USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+                         SET_CONFIGURATION,
+                         conf,
+                         0, NULL, 0);
+}
+
+uint8_t USBHost::numberDriverAttached(USBDeviceConnected * dev) {
+    int index = findDevice(dev);
+    uint8_t cnt = 0;
+    if (index == -1)
+        return 0;
+    for (uint8_t i = 0; i < MAX_INTF; i++) {
+        if (deviceAttachedDriver[index][i])
+            cnt++;
+    }
+    return cnt;
+}
+
+// enumerate a device with the control USBEndpoint
+USB_TYPE USBHost::enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator)
+{
+    uint16_t total_conf_descr_length = 0;
+    USB_TYPE res;
+
+    do
+    {
+      Lock lock(this);
+
+      // don't enumerate a device which all interfaces are registered to a specific driver
+      int index = findDevice(dev);
+
+      if (index == -1) {
+          return USB_TYPE_ERROR;
+      }
+
+      uint8_t nb_intf_attached = numberDriverAttached(dev);
+      USB_DBG("dev: %p nb_intf: %d", dev, dev->getNbIntf());
+      USB_DBG("dev: %p nb_intf_attached: %d", dev, nb_intf_attached);
+      if ((nb_intf_attached != 0) && (dev->getNbIntf() == nb_intf_attached)) {
+          USB_DBG("Don't enumerate dev: %p because all intf are registered with a driver", dev);
+          return USB_TYPE_OK;
+      }
+
+      USB_DBG("Enumerate dev: %p", dev);
+
+      // third step: get the whole device descriptor to see vid, pid
+      res = getDeviceDescriptor(dev, data, DEVICE_DESCRIPTOR_LENGTH);
+
+      if (res != USB_TYPE_OK) {
+          USB_DBG("GET DEV DESCR FAILED");
+          return res;
+      }
+
+      dev->setClass(data[4]);
+      dev->setSubClass(data[5]);
+      dev->setProtocol(data[6]);
+      dev->setVid(data[8] | (data[9] << 8));
+      dev->setPid(data[10] | (data[11] << 8));
+      USB_DBG("CLASS: %02X \t VID: %04X \t PID: %04X", data[4], data[8] | (data[9] << 8), data[10] | (data[11] << 8));
+
+      pEnumerator->setVidPid( data[8] | (data[9] << 8), data[10] | (data[11] << 8) );
+
+      res = getConfigurationDescriptor(dev, data, 415, &total_conf_descr_length);
+      if (res != USB_TYPE_OK) {
+          return res;
+      }
+
+  #if (DEBUG > 3)
+      USB_DBG("CONFIGURATION DESCRIPTOR:\r\n");
+      for (int i = 0; i < total_conf_descr_length; i++)
+          printf("%02X ", data[i]);
+      printf("\r\n\r\n");
+  #endif
+
+      // Parse the configuration descriptor
+      parseConfDescr(dev, data, total_conf_descr_length, pEnumerator);
+
+      // only set configuration if not enumerated before
+      if (!dev->isEnumerated()) {
+
+          USB_DBG("Set configuration 1 on dev: %p", dev);
+          // sixth step: set configuration (only 1 supported)
+          res = setConfiguration(dev, 1);
+
+          if (res != USB_TYPE_OK) {
+              USB_DBG("SET CONF FAILED");
+              return res;
+          }
+      }
+
+      dev->setEnumerated();
+
+      // Now the device is enumerated!
+      USB_DBG("dev %p is enumerated\r\n", dev);
+
+    } while(0);
+
+    // Some devices may require this delay
+    ThisThread::sleep_for(100);
+
+    return USB_TYPE_OK;
+}
+// this method fills the USBDeviceConnected object: class,.... . It also add endpoints found in the descriptor.
+void USBHost::parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator)
+{
+    uint32_t index = 0;
+    uint32_t len_desc = 0;
+    uint8_t id = 0;
+    int nb_endpoints_used = 0;
+    USBEndpoint * ep = NULL;
+    uint8_t intf_nb = 0;
+    bool parsing_intf = false;
+    uint8_t current_intf = 0;
+
+    while (index < len) {
+        len_desc = conf_descr[index];
+        id = conf_descr[index+1];
+        switch (id) {
+            case CONFIGURATION_DESCRIPTOR:
+                USB_DBG("dev: %p has %d intf", dev, conf_descr[4]);
+                dev->setNbIntf(conf_descr[4]);
+                break;
+            case INTERFACE_DESCRIPTOR:
+                if(pEnumerator->parseInterface(conf_descr[index + 2], conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7])) {
+                    if (intf_nb++ <= MAX_INTF) {
+                        current_intf = conf_descr[index + 2];
+                        dev->addInterface(current_intf, conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7]);
+                        nb_endpoints_used = 0;
+                        USB_DBG("ADD INTF %d on device %p: class: %d, subclass: %d, proto: %d", current_intf, dev, conf_descr[index + 5],conf_descr[index + 6],conf_descr[index + 7]);
+                    } else {
+                        USB_DBG("Drop intf...");
+                    }
+                    parsing_intf = true;
+                } else {
+                    parsing_intf = false;
+                }
+                break;
+            case ENDPOINT_DESCRIPTOR:
+                if (parsing_intf && (intf_nb <= MAX_INTF) ) {
+                    if (nb_endpoints_used < MAX_ENDPOINT_PER_INTERFACE) {
+                        if( pEnumerator->useEndpoint(current_intf, (ENDPOINT_TYPE)(conf_descr[index + 3] & 0x03), (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1)) ) {
+                            // if the USBEndpoint is isochronous -> skip it (TODO: fix this)
+                            if ((conf_descr[index + 3] & 0x03) != ISOCHRONOUS_ENDPOINT) {
+                                ep = newEndpoint((ENDPOINT_TYPE)(conf_descr[index+3] & 0x03),
+                                                 (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1),
+                                                 conf_descr[index + 4] | (conf_descr[index + 5] << 8),
+                                                 conf_descr[index + 2] & 0x0f);
+                                USB_DBG("ADD USBEndpoint %p, on interf %d on device %p", ep, current_intf, dev);
+                                if (ep != NULL && dev != NULL) {
+                                    addEndpoint(dev, current_intf, ep);
+                                } else {
+                                    USB_DBG("EP NULL");
+                                }
+                                nb_endpoints_used++;
+                            } else {
+                                USB_DBG("ISO USBEndpoint NOT SUPPORTED");
+                            }
+                        }
+                    }
+                }
+                break;
+            case HID_DESCRIPTOR:
+                lenReportDescr = conf_descr[index + 7] | (conf_descr[index + 8] << 8);
+                break;
+            default:
+                break;
+        }
+        index += len_desc;
+    }
+}
+
+
+USB_TYPE USBHost::bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::generalTransfer(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking, ENDPOINT_TYPE type, bool write) {
+
+#if DEBUG_TRANSFER
+    const char * type_str = (type == BULK_ENDPOINT) ? "BULK" : ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" : "ISOCHRONOUS");
+    USB_DBG_TRANSFER("----- %s %s [dev: %p - %s - hub: %d - port: %d - addr: %d - ep: %02X]------", type_str, (write) ? "WRITE" : "READ", dev, dev->getName(ep->getIntfNb()), dev->getHub(), dev->getPort(), dev->getAddress(), ep->getAddress());
+#endif
+
+    Lock lock(this);
+
+    USB_TYPE res;
+    ENDPOINT_DIRECTION dir = (write) ? OUT : IN;
+
+    if (dev == NULL) {
+        USB_ERR("dev NULL");
+        return USB_TYPE_ERROR;
+    }
+
+    if (ep == NULL) {
+        USB_ERR("ep NULL");
+        return USB_TYPE_ERROR;
+    }
+
+    if (ep->getState() != USB_TYPE_IDLE) {
+        USB_WARN("[ep: %p - dev: %p - %s] NOT IDLE: %s", ep, ep->dev, ep->dev->getName(ep->getIntfNb()), ep->getStateString());
+        return ep->getState();
+    }
+
+    if ((ep->getDir() != dir) || (ep->getType() != type)) {
+        USB_ERR("[ep: %p - dev: %p] wrong dir or bad USBEndpoint type", ep, ep->dev);
+        return USB_TYPE_ERROR;
+    }
+
+    if (dev->getAddress() != ep->getDeviceAddress()) {
+        USB_ERR("[ep: %p - dev: %p] USBEndpoint addr and device addr don't match", ep, ep->dev);
+        return USB_TYPE_ERROR;
+    }
+
+#if DEBUG_TRANSFER
+    if (write) {
+        USB_DBG_TRANSFER("%s WRITE buffer", type_str);
+        for (int i = 0; i < ep->getLengthTransferred(); i++)
+            printf("%02X ", buf[i]);
+        printf("\r\n\r\n");
+    }
+#endif
+    res = addTransfer(ep, buf, len);
+
+    if ((blocking)&& (res == USB_TYPE_PROCESSING)) {
+
+        ep->ep_queue.get();
+        res = ep->getState();
+
+        USB_DBG_TRANSFER("%s TRANSFER res: %s on ep: %p\r\n", type_str, ep->getStateString(), ep);
+
+        if (res != USB_TYPE_IDLE) {
+            return res;
+        }
+
+        return USB_TYPE_OK;
+    }
+
+    return res;
+
+}
+
+
+USB_TYPE USBHost::controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+    return controlTransfer(dev, requestType, request, value, index, buf, len, false);
+}
+
+USB_TYPE USBHost::controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+    return controlTransfer(dev, requestType, request, value, index, buf, len, true);
+}
+
+USB_TYPE USBHost::controlTransfer(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len, bool write)
+{
+    Lock lock(this);
+    USB_DBG_TRANSFER("----- CONTROL %s [dev: %p - hub: %d - port: %d] ------", (write) ? "WRITE" : "READ", dev, dev->getHub(), dev->getPort());
+
+    int length_transfer = len;
+    USB_TYPE res;
+    uint32_t token;
+
+    control->setSpeed(dev->getSpeed());
+    control->setSize(dev->getSizeControlEndpoint());
+    if (dev->isActiveAddress()) {
+        control->setDeviceAddress(dev->getAddress());
+    } else {
+        control->setDeviceAddress(0);
+    }
+
+    USB_DBG_TRANSFER("Control transfer on device: %d\r\n", control->getDeviceAddress());
+    fillControlBuf(requestType, request, value, index, len);
+
+#if DEBUG_TRANSFER
+    USB_DBG_TRANSFER("SETUP PACKET: ");
+    for (int i = 0; i < 8; i++)
+        printf("%01X ", setupPacket[i]);
+    printf("\r\n");
+#endif
+
+    control->setNextToken(TD_SETUP);
+    res = addTransfer(control, (uint8_t*)setupPacket, 8);
+
+    if (res == USB_TYPE_PROCESSING) control->ep_queue.get();
+    res = control->getState();
+
+    USB_DBG_TRANSFER("CONTROL setup stage %s", control->getStateString());
+
+    if (res != USB_TYPE_IDLE) {
+        return res;
+    }
+
+    if (length_transfer) {
+        token = (write) ? TD_OUT : TD_IN;
+        control->setNextToken(token);
+        res = addTransfer(control, (uint8_t *)buf, length_transfer);
+
+        if (res == USB_TYPE_PROCESSING) control->ep_queue.get();
+        res = control->getState();
+
+#if DEBUG_TRANSFER
+        USB_DBG_TRANSFER("CONTROL %s stage %s", (write) ? "WRITE" : "READ", control->getStateString());
+        if (write) {
+            USB_DBG_TRANSFER("CONTROL WRITE buffer");
+            for (int i = 0; i < control->getLengthTransferred(); i++)
+                printf("%02X ", buf[i]);
+            printf("\r\n\r\n");
+        } else {
+            USB_DBG_TRANSFER("CONTROL READ SUCCESS [%d bytes transferred]", control->getLengthTransferred());
+            for (int i = 0; i < control->getLengthTransferred(); i++)
+                printf("%02X ", buf[i]);
+            printf("\r\n\r\n");
+        }
+#endif
+
+        if (res != USB_TYPE_IDLE) {
+            return res;
+        }
+    }
+
+    token = (write) ? TD_IN : TD_OUT;
+    control->setNextToken(token);
+    res = addTransfer(control, NULL, 0);
+
+    if (res == USB_TYPE_PROCESSING) control->ep_queue.get();
+    res = control->getState();
+
+    USB_DBG_TRANSFER("CONTROL ack stage %s", control->getStateString());
+
+    if (res != USB_TYPE_IDLE)
+        return res;
+
+    return USB_TYPE_OK;
+}
+
+
+void USBHost::fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len)
+{
+    setupPacket[0] = requestType;
+    setupPacket[1] = request;
+    setupPacket[2] = (uint8_t) value;
+    setupPacket[3] = (uint8_t) (value >> 8);
+    setupPacket[4] = (uint8_t) index;
+    setupPacket[5] = (uint8_t) (index >> 8);
+    setupPacket[6] = (uint8_t) len;
+    setupPacket[7] = (uint8_t) (len >> 8);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHost.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,407 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_H
+#define USBHOST_H
+#ifdef TARGET_STM
+#include "mbed.h" 
+#endif
+#include "USBHALHost.h"
+#include "USBDeviceConnected.h"
+#include "IUSBEnumerator.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+#include "dbg.h"
+#include "USBHostHub.h"
+#if defined(TARGET_RZ_A2XX)
+#include "NonCacheMem.h"
+#endif
+
+/**
+* USBHost class
+*   This class is a singleton. All drivers have a reference on the static USBHost instance
+*/
+class USBHost : public USBHALHost {
+public:
+    /**
+    * Static method to create or retrieve the single USBHost instance
+    */
+    static USBHost * getHostInst();
+
+    /**
+    * Control read: setup stage, data stage and status stage
+    *
+    * @param dev the control read will be done for this device
+    * @param requestType request type
+    * @param request request
+    * @param value value
+    * @param index index
+    * @param buf pointer on a buffer where will be store the data received
+    * @param len length of the transfer
+    *
+    * @returns status of the control read
+    */
+    USB_TYPE controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+    /**
+    * Control write: setup stage, data stage and status stage
+    *
+    * @param dev the control write will be done for this device
+    * @param requestType request type
+    * @param request request
+    * @param value value
+    * @param index index
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    *
+    * @returns status of the control write
+    */
+    USB_TYPE controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+    /**
+    * Bulk read
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to read a packet
+    * @param buf pointer on a buffer where will be store the data received
+    * @param len length of the transfer
+    * @param blocking if true, the read is blocking (wait for completion)
+    *
+    * @returns status of the bulk read
+    */
+    USB_TYPE bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Bulk write
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to write a packet
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    * @param blocking if true, the write is blocking (wait for completion)
+    *
+    * @returns status of the bulk write
+    */
+    USB_TYPE bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Interrupt read
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to write a packet
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    * @param blocking if true, the read is blocking (wait for completion)
+    *
+    * @returns status of the interrupt read
+    */
+    USB_TYPE interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Interrupt write
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to write a packet
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    * @param blocking if true, the write is blocking (wait for completion)
+    *
+    * @returns status of the interrupt write
+    */
+    USB_TYPE interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Enumerate a device.
+    *
+    * @param dev device which will be enumerated
+    *
+    * @returns status of the enumeration
+    */
+    USB_TYPE enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator);
+
+    /**
+    * reset a specific device
+    *
+    * @param dev device which will be resetted
+    */
+    USB_TYPE resetDevice(USBDeviceConnected * dev);
+
+    /**
+    * Get a device
+    *
+    * @param index index of the device which will be returned
+    *
+    * @returns pointer on the "index" device
+    */
+    USBDeviceConnected * getDevice(uint8_t index);
+
+    /*
+    * If there is a HID device connected, the host stores the length of the report descriptor.
+    * This avoid to the driver to re-ask the configuration descriptor to request the report descriptor
+    *
+    * @returns length of the report descriptor
+    */
+    inline uint16_t getLengthReportDescr() {
+        return lenReportDescr;
+    };
+
+    /**
+     *  register a driver into the host associated with a callback function called when the device is disconnected
+     *
+     *  @param dev device
+     *  @param intf interface number
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, T* tptr, void (T::*mptr)(void)) {
+        int index = findDevice(dev);
+        if ((index != -1) && (mptr != NULL) && (tptr != NULL)) {
+            USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+            deviceAttachedDriver[index][intf] = true;
+            dev->onDisconnect(intf, tptr, mptr);
+        }
+    }
+
+    /**
+     * register a driver into the host associated with a callback function called when the device is disconnected
+     *
+     * @param dev device
+     * @param intf interface number
+     * @param fn callback called when the specified device has been disconnected
+     */
+    inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, void (*fn)(void)) {
+        int index = findDevice(dev);
+        if ((index != -1) && (fn != NULL)) {
+            USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+            deviceAttachedDriver[index][intf] = true;
+            dev->onDisconnect(intf, fn);
+        }
+    }
+
+    /**
+     * Instantiate to protect USB thread from accessing shared objects (USBConnectedDevices and Interfaces)
+     */
+    class Lock
+    {
+    public:
+      Lock(USBHost* pHost);
+      ~Lock();
+    private:
+      USBHost* m_pHost;
+    };
+
+    friend class USBHostHub;
+
+protected:
+
+    /**
+    * Virtual method called when a transfer has been completed
+    *
+    * @param addr list of the TDs which have been completed
+    */
+    virtual void transferCompleted(volatile uint32_t addr);
+
+    /**
+    * Virtual method called when a device has been connected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param lowSpeed 1 if low speed, 0 otherwise
+    * @param hub_parent reference on the parent hub
+    */
+    virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL);
+
+    /**
+    * Virtuel method called when a device has been disconnected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param addr list of the TDs which have been completed to dequeue freed TDs
+    */
+    virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr);
+
+
+private:
+    // singleton class -> constructor is private
+    USBHost();
+    static USBHost * instHost;
+    uint16_t  lenReportDescr;
+
+    // endpoints
+    void unqueueEndpoint(USBEndpoint * ep) ;
+    USBEndpoint  endpoints[MAX_ENDPOINT];
+    USBEndpoint* volatile  control;
+
+    USBEndpoint* volatile  headControlEndpoint;
+    USBEndpoint* volatile  headBulkEndpoint;
+    USBEndpoint* volatile  headInterruptEndpoint;
+
+    USBEndpoint* volatile  tailControlEndpoint;
+    USBEndpoint* volatile  tailBulkEndpoint;
+    USBEndpoint* volatile  tailInterruptEndpoint;
+
+    bool controlEndpointAllocated;
+
+    // devices connected
+    USBDeviceConnected devices[MAX_DEVICE_CONNECTED];
+    bool  deviceInUse[MAX_DEVICE_CONNECTED];
+    bool  deviceAttachedDriver[MAX_DEVICE_CONNECTED][MAX_INTF];
+    bool  deviceReset[MAX_DEVICE_CONNECTED];
+    bool  deviceInited[MAX_DEVICE_CONNECTED];
+
+#if MAX_HUB_NB
+    USBHostHub hubs[MAX_HUB_NB];
+    bool hub_in_use[MAX_HUB_NB];
+#endif
+
+    // to store a setup packet
+#if defined(TARGET_RZ_A2XX)
+    uint8_t * setupPacket;
+#else
+    uint8_t  setupPacket[8];
+#endif
+
+    typedef struct {
+        uint8_t event_id;
+        void * td_addr;
+        uint8_t hub;
+        uint8_t port;
+        uint8_t lowSpeed;
+        uint8_t td_state;
+        void * hub_parent;
+    } message_t;
+
+    Thread usbThread;
+    void usb_process();
+    Mail<message_t, 10> mail_usb_event;
+    rtos::Mutex usb_mutex;
+    rtos::Mutex td_mutex;
+
+    // buffer for conf descriptor
+#if defined(TARGET_RZ_A2XX)
+    uint8_t * data;
+#else
+    uint8_t data[415];
+#endif
+
+    /**
+    * Add a transfer on the TD linked list associated to an ED
+    *
+    * @param ed the transfer is associated to this ed
+    * @param buf pointer on a buffer where will be read/write data to send or receive
+    * @param len transfer length
+    *
+    * @return status of the transfer
+    */
+    USB_TYPE addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len) ;
+
+    /**
+    * Link the USBEndpoint to the linked list and attach an USBEndpoint this USBEndpoint to a device
+    *
+    * @param dev pointer on a USBDeviceConnected object
+    * @param ep pointer on the USBEndpoint which will be added
+    *
+    * return true if successful
+    */
+    bool addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep) ;
+
+    /**
+    * Create an USBEndpoint descriptor. Warning: the USBEndpoint is not linked.
+    *
+    * @param type USBEndpoint type (CONTROL_ENDPOINT, BULK_ENDPOINT, INTERRUPT_ENDPOINT)
+    * @param dir USBEndpoint direction (no meaning for CONTROL_ENDPOINT)
+    * @param size USBEndpoint max packet size
+    * @param addr USBEndpoint address
+    *
+    * @returns pointer on the USBEndpoint created
+    */
+    USBEndpoint * newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr) ;
+
+    /**
+    * Request the device descriptor
+    *
+    * @param dev request the device descriptor on this device
+    * @param buf buffer to store the device descriptor
+    * @param max_len_buf maximum size of buf
+    * @param len_dev_descr pointer to store the length of the packet transferred
+    */
+    USB_TYPE getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr = NULL);
+
+    /**
+    * Request the configuration descriptor
+    *
+    * @param dev request the configuration descriptor on this device
+    * @param buf buffer to store the configuration descriptor
+    * @param max_len_buf maximum size of buf
+    * @param len_conf_descr pointer to store the length of the packet transferred
+    */
+    USB_TYPE getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr = NULL);
+
+    /**
+    * Set the address of a specific device
+    *
+    * @param dev device to set the address
+    * @param address address
+    */
+    USB_TYPE setAddress(USBDeviceConnected * dev, uint8_t address);
+
+    /**
+    * Set the configuration of a device
+    *
+    * @param dev device on which the specified configuration will be activated
+    * @param conf configuration number to activate (usually 1)
+    */
+    USB_TYPE setConfiguration(USBDeviceConnected * dev, uint8_t conf);
+
+    /**
+    * Free a specific device
+    *
+    * @param dev device to be freed
+    */
+    void freeDevice(USBDeviceConnected * dev);
+
+    USB_TYPE controlTransfer(   USBDeviceConnected * dev,
+                                uint8_t requestType,
+                                uint8_t request,
+                                uint32_t value,
+                                uint32_t index,
+                                uint8_t * buf,
+                                uint32_t len,
+                                bool write);
+
+    USB_TYPE generalTransfer(   USBDeviceConnected * dev,
+                                USBEndpoint * ep,
+                                uint8_t * buf,
+                                uint32_t len,
+                                bool blocking,
+                                ENDPOINT_TYPE type,
+                                bool write) ;
+
+    void fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len) ;
+    void parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator) ;
+    int findDevice(USBDeviceConnected * dev) ;
+    int findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent = NULL) ;
+    uint8_t numberDriverAttached(USBDeviceConnected * dev);
+
+    /////////////////////////
+    /// FOR DEBUG
+    /////////////////////////
+    void printList(ENDPOINT_TYPE type);
+
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHostConf.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,108 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_CONF_H
+#define USBHOST_CONF_H
+
+#if defined(TARGET_RZ_A1XX) || defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF) || defined(TARGET_RZ_A2M_SBEV)
+
+/*
+* Maximum number of devices that can be connected
+* to the usb host
+*/
+#define MAX_DEVICE_CONNECTED        5
+
+/*
+* Maximum of Hub connected to the usb host
+*/
+#define MAX_HUB_NB                  2
+
+/*
+* Maximum number of ports on a USB hub
+*/
+#define MAX_HUB_PORT                4
+
+/*
+* Enable USBHostMSD
+*/
+#define USBHOST_MSD                 1
+
+/*
+* Enable USBHostKeyboard
+*/
+#define USBHOST_KEYBOARD            1
+
+/*
+* Enable USBHostMouse
+*/
+#define USBHOST_MOUSE               1
+
+/*
+* Enable USBHostSerial or USBHostMultiSerial (if set > 1)
+*/
+#define USBHOST_SERIAL              1
+
+/*
+* Enable USB3Gmodule
+*/
+#define USBHOST_3GMODULE            1
+
+/*
+* Enable USB MIDI
+*/
+#define USBHOST_MIDI                1 
+
+/*
+* Maximum number of interfaces of a usb device
+*/
+#define MAX_INTF                    4
+
+/*
+* Maximum number of endpoints on each interface
+*/
+#define MAX_ENDPOINT_PER_INTERFACE  3
+
+/*
+* Maximum number of endpoint descriptors that can be allocated
+*/
+#define MAX_ENDPOINT                (MAX_DEVICE_CONNECTED * MAX_INTF * MAX_ENDPOINT_PER_INTERFACE)
+
+#else
+
+#define MAX_DEVICE_CONNECTED        5
+#define MAX_HUB_NB                  2
+#define MAX_HUB_PORT                4
+#define USBHOST_MSD                 0
+#define USBHOST_KEYBOARD            0
+#define USBHOST_MOUSE               0
+#define USBHOST_SERIAL              0
+#define USBHOST_3GMODULE            0
+#define USBHOST_MIDI                0 
+#define MAX_INTF                    4
+#define MAX_ENDPOINT_PER_INTERFACE  3
+#define MAX_ENDPOINT                (MAX_DEVICE_CONNECTED * MAX_INTF * MAX_ENDPOINT_PER_INTERFACE)
+#endif
+/*
+* Maximum number of transfer descriptors that can be allocated
+*/
+#define MAX_TD                      (MAX_ENDPOINT*2)
+
+/*
+* usb_thread stack size
+*/
+#define USB_THREAD_STACK            (256*4 + 2*256*4)
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/USBHostTypes.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,272 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_INC_H
+#define USB_INC_H
+
+#include "mbed.h"
+#include "mbed_toolchain.h"
+
+enum USB_TYPE {
+    USB_TYPE_OK = 0,
+
+    // completion code
+    USB_TYPE_CRC_ERROR = 1,
+    USB_TYPE_BIT_STUFFING_ERROR = 2,
+    USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR = 3,
+    USB_TYPE_STALL_ERROR = 4,
+    USB_TYPE_DEVICE_NOT_RESPONDING_ERROR = 5,
+    USB_TYPE_PID_CHECK_FAILURE_ERROR = 6,
+    USB_TYPE_UNEXPECTED_PID_ERROR = 7,
+    USB_TYPE_DATA_OVERRUN_ERROR = 8,
+    USB_TYPE_DATA_UNDERRUN_ERROR = 9,
+    USB_TYPE_RESERVED = 9,
+    USB_TYPE_RESERVED_ = 10,
+    USB_TYPE_BUFFER_OVERRUN_ERROR = 12,
+    USB_TYPE_BUFFER_UNDERRUN_ERROR = 13,
+
+    // general usb state
+    USB_TYPE_DISCONNECTED = 14,
+    USB_TYPE_FREE = 15,
+    USB_TYPE_IDLE = 16,
+    USB_TYPE_PROCESSING = 17,
+
+    USB_TYPE_ERROR = 18,
+};
+
+
+enum ENDPOINT_DIRECTION {
+    OUT = 1,
+    IN
+};
+
+enum ENDPOINT_TYPE {
+    CONTROL_ENDPOINT = 0,
+    ISOCHRONOUS_ENDPOINT,
+    BULK_ENDPOINT,
+    INTERRUPT_ENDPOINT
+};
+
+#define AUDIO_CLASS     0x01
+#define CDC_CLASS       0x02
+#define HID_CLASS       0x03
+#define MSD_CLASS       0x08
+#define HUB_CLASS       0x09
+#define SERIAL_CLASS    0x0A
+
+#if !defined(USBHOST_OTHER)
+// ------------------ HcControl Register ---------------------
+#define  OR_CONTROL_PLE                 0x00000004
+#define  OR_CONTROL_CLE                 0x00000010
+#define  OR_CONTROL_BLE                 0x00000020
+#define  OR_CONTROL_HCFS                0x000000C0
+#define  OR_CONTROL_HC_RSET             0x00000000
+#define  OR_CONTROL_HC_RES              0x00000040
+#define  OR_CONTROL_HC_OPER             0x00000080
+#define  OR_CONTROL_HC_SUSP             0x000000C0
+// ----------------- HcCommandStatus Register -----------------
+#define  OR_CMD_STATUS_HCR              0x00000001
+#define  OR_CMD_STATUS_CLF              0x00000002
+#define  OR_CMD_STATUS_BLF              0x00000004
+// --------------- HcInterruptStatus Register -----------------
+#define  OR_INTR_STATUS_WDH             0x00000002
+#define  OR_INTR_STATUS_RHSC            0x00000040
+#define  OR_INTR_STATUS_UE              0x00000010
+// --------------- HcInterruptEnable Register -----------------
+#define  OR_INTR_ENABLE_WDH             0x00000002
+#define  OR_INTR_ENABLE_RHSC            0x00000040
+#define  OR_INTR_ENABLE_MIE             0x80000000
+// ---------------- HcRhDescriptorA Register ------------------
+#define  OR_RH_STATUS_LPSC              0x00010000
+#define  OR_RH_STATUS_DRWE              0x00008000
+// -------------- HcRhPortStatus[1:NDP] Register --------------
+#define  OR_RH_PORT_CCS                 0x00000001
+#define  OR_RH_PORT_PRS                 0x00000010
+#define  OR_RH_PORT_CSC                 0x00010000
+#define  OR_RH_PORT_PRSC                0x00100000
+#define  OR_RH_PORT_LSDA                0x00000200
+#define  OR_RH_PORT_PESC                0x00020000
+#define  OR_RH_PORT_OCIC                0x00080000
+
+#define  FI                     0x2EDF           // 12000 bits per frame (-1)
+#define  DEFAULT_FMINTERVAL     ((((6 * (FI - 210)) / 7) << 16) | FI)
+
+#define  ED_SKIP            (uint32_t) (0x00001000)        // Skip this ep in queue
+
+#define  TD_ROUNDING        (uint32_t) (0x00040000)        // Buffer Rounding
+#define  TD_SETUP           (uint32_t)(0)                  // Direction of Setup Packet
+#define  TD_IN              (uint32_t)(0x00100000)         // Direction In
+#define  TD_OUT             (uint32_t)(0x00080000)         // Direction Out
+#define  TD_DELAY_INT(x)    (uint32_t)((x) << 21)          // Delay Interrupt
+#define  TD_TOGGLE_0        (uint32_t)(0x02000000)         // Toggle 0
+#define  TD_TOGGLE_1        (uint32_t)(0x03000000)         // Toggle 1
+#define  TD_CC              (uint32_t)(0xF0000000)         // Completion Code
+
+#else
+
+#define  TD_SETUP           (uint32_t)(0)                  // Direction of Setup Packet
+#define  TD_IN              (uint32_t)(0x00100000)         // Direction In
+#define  TD_OUT             (uint32_t)(0x00080000)         // Direction Out
+
+#endif
+#define  DEVICE_DESCRIPTOR                     (1)
+#define  CONFIGURATION_DESCRIPTOR              (2)
+#define  INTERFACE_DESCRIPTOR                  (4)
+#define  ENDPOINT_DESCRIPTOR                   (5)
+#define  HID_DESCRIPTOR                        (33)
+
+//  ----------- Control RequestType Fields  -----------
+#define  USB_DEVICE_TO_HOST         0x80
+#define  USB_HOST_TO_DEVICE         0x00
+#define  USB_REQUEST_TYPE_CLASS     0x20
+#define  USB_REQUEST_TYPE_STANDARD  0x00
+#define  USB_RECIPIENT_DEVICE       0x00
+#define  USB_RECIPIENT_INTERFACE    0x01
+#define  USB_RECIPIENT_ENDPOINT     0x02
+
+// -------------- USB Standard Requests  --------------
+#ifndef  SET_ADDRESS
+#define  SET_ADDRESS                0x05
+#endif
+#ifndef  GET_DESCRIPTOR
+#define  GET_DESCRIPTOR             0x06
+#endif
+#ifndef  SET_CONFIGURATION
+#define  SET_CONFIGURATION          0x09
+#endif
+#ifndef  SET_INTERFACE
+#define  SET_INTERFACE              0x0b
+#endif
+#ifndef  CLEAR_FEATURE
+#define  CLEAR_FEATURE              0x01
+#endif
+
+// -------------- USB Descriptor Length  --------------
+#ifndef DEVICE_DESCRIPTOR_LENGTH
+#define DEVICE_DESCRIPTOR_LENGTH            0x12
+#endif
+#ifndef CONFIGURATION_DESCRIPTOR_LENGTH
+#define CONFIGURATION_DESCRIPTOR_LENGTH     0x09
+#endif
+
+// ------------ HostController Transfer Descriptor ------------
+#if defined(USBHOST_OTHER)
+
+typedef struct hcTd {
+	__IO uint32_t state;
+	__IO  uint8_t *  currBufPtr;    // Physical address of current buffer pointer
+	__IO  hcTd *     nextTD;         // Physical pointer to next Transfer Descriptor
+	__IO  uint32_t   size;        // size of buffer
+	void * ep;                      // ep address where a td is linked in
+} PACKED HCTD;
+// ----------- HostController EndPoint Descriptor -------------
+typedef struct hcEd {
+  uint8_t ch_num;
+  void *hhcd;
+} PACKED HCED;
+// ----------- Host Controller Communication Area ------------
+#define HCCA   void
+
+
+#else 
+// -------------OHCI register --------------------------------
+// ------------ HostController Transfer Descriptor ------------
+typedef struct hcTd {
+    __IO  uint32_t   control;        // Transfer descriptor control
+    __IO  uint8_t *  currBufPtr;    // Physical address of current buffer pointer
+    __IO  hcTd *     nextTD;         // Physical pointer to next Transfer Descriptor
+    __IO  uint8_t *  bufEnd;        // Physical address of end of buffer
+    void * ep;                      // ep address where a td is linked in
+    uint32_t dummy[3];              // padding
+} PACKED HCTD;
+// ----------- HostController EndPoint Descriptor -------------
+typedef struct hcEd {
+    __IO  uint32_t  control;        // Endpoint descriptor control
+    __IO  HCTD *  tailTD;           // Physical address of tail in Transfer descriptor list
+    __IO  HCTD *  headTD;           // Physcial address of head in Transfer descriptor list
+    __IO  hcEd *  nextED;         // Physical address of next Endpoint descriptor
+} PACKED HCED;
+// ----------- Host Controller Communication Area ------------
+typedef struct hcca {
+    __IO  uint32_t  IntTable[32];   // Interrupt Table
+    __IO  uint32_t  FrameNumber;    // Frame Number
+    __IO  uint32_t  DoneHead;       // Done Head
+    volatile  uint8_t   Reserved[116];  // Reserved for future use
+    volatile  uint8_t   Unknown[4];     // Unused
+} PACKED HCCA;
+#endif
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t bcdUSB;
+    uint8_t bDeviceClass;
+    uint8_t bDeviceSubClass;
+    uint8_t bDeviceProtocol;
+    uint8_t bMaxPacketSize;
+    uint16_t idVendor;
+    uint16_t idProduct;
+    uint16_t bcdDevice;
+    uint8_t iManufacturer;
+    uint8_t iProduct;
+    uint8_t iSerialNumber;
+    uint8_t bNumConfigurations;
+} PACKED DeviceDescriptor;
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t wTotalLength;
+    uint8_t bNumInterfaces;
+    uint8_t bConfigurationValue;
+    uint8_t iConfiguration;
+    uint8_t bmAttributes;
+    uint8_t bMaxPower;
+} PACKED ConfigurationDescriptor;
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bInterfaceNumber;
+    uint8_t bAlternateSetting;
+    uint8_t bNumEndpoints;
+    uint8_t bInterfaceClass;
+    uint8_t bInterfaceSubClass;
+    uint8_t bInterfaceProtocol;
+    uint8_t iInterface;
+} InterfaceDescriptor;
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bEndpointAddress;
+    uint8_t bmAttributes;
+    uint16_t wMaxPacketSize;
+    uint8_t bInterval;
+} EndpointDescriptor;
+
+typedef struct {
+    uint8_t bDescLength;
+    uint8_t bDescriptorType;
+    uint8_t bNbrPorts;
+    uint16_t wHubCharacteristics;
+    uint8_t bPwrOn2PwrGood;
+    uint8_t bHubContrCurrent;
+    uint8_t DeviceRemovable;
+    uint8_t PortPweCtrlMak;
+} HubDescriptor;
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost/dbg.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,66 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_DEBUG_H
+#define USB_DEBUG_H
+
+//Debug is disabled by default
+#define DEBUG 3 /*INFO,ERR,WARN*/
+#define DEBUG_TRANSFER 0
+#define DEBUG_EP_STATE 0
+#define DEBUG_EVENT 0
+
+#if (DEBUG > 3)
+#define USB_DBG(x, ...) std::printf("[USB_DBG: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG(x, ...)
+#endif
+
+#if (DEBUG > 2)
+#define USB_INFO(x, ...) std::printf("[USB_INFO: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_INFO(x, ...)
+#endif
+
+#if (DEBUG > 1)
+#define USB_WARN(x, ...) std::printf("[USB_WARNING: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_WARN(x, ...)
+#endif
+
+#if (DEBUG > 0)
+#define USB_ERR(x, ...) std::printf("[USB_ERR: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_ERR(x, ...)
+#endif
+
+#if (DEBUG_TRANSFER)
+#define USB_DBG_TRANSFER(x, ...) std::printf("[USB_TRANSFER: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_TRANSFER(x, ...)
+#endif
+
+#if (DEBUG_EVENT)
+#define USB_DBG_EVENT(x, ...) std::printf("[USB_EVENT: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_EVENT(x, ...)
+#endif
+
+
+#endif
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost3GModule/IUSBHostSerial.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,95 @@
+/* IUSBHostSerial.h */
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef IUSBHOSTSERIAL_H_
+#define IUSBHOSTSERIAL_H_
+
+/**
+ * Generic interface to abstract 3G dongles' impl
+ */
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "IUSBHostSerialListener.h"
+
+// This is needed by some versions of GCC
+#undef putc
+#undef getc
+
+class IUSBHostSerial {
+public:
+
+    enum IrqType {
+        RxIrq,
+        TxIrq
+    };
+
+    /*
+    * Get a char from the dongle's serial interface
+    */
+    virtual int getc() = 0;
+
+    /*
+    * Put a char to the dongle's serial interface
+    */
+    virtual int putc(int c) = 0;
+
+    /*
+     *  Read a packet from the dongle's serial interface, to be called after multiple getc() calls
+     */
+    virtual int readPacket() = 0;
+
+    /*
+     *  Write a packet to the dongle's serial interface, to be called after multiple putc() calls
+     */
+    virtual int writePacket() = 0;
+
+    /**
+    * Check the number of bytes available.
+    *
+    * @returns the number of bytes available
+    */
+    virtual int readable() = 0;
+
+    /**
+    * Check the free space in output.
+    *
+    * @returns the number of bytes available
+    */
+    virtual int writeable() = 0;
+
+    /**
+     *  Attach a handler to call when a packet is received / when a packet has been transmitted.
+     *
+     *  @param pListener instance of the listener deriving from the IUSBHostSerialListener
+     */
+    virtual void attach(IUSBHostSerialListener* pListener) = 0;
+
+    /**
+     * Enable or disable readable/writeable callbacks
+     */
+    virtual void setupIrq(bool en, IrqType irq = RxIrq) = 0;
+
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif /* IUSBHOSTSERIAL_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost3GModule/IUSBHostSerialListener.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,37 @@
+/* IUSBHostSerialListener.h */
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#ifndef IUSBHOSTSERIALLISTENER_H_
+#define IUSBHOSTSERIALLISTENER_H_
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+class IUSBHostSerialListener
+{
+public:
+  virtual void readable() = 0; //Called when new data is available
+  virtual void writeable() = 0; //Called when new space is available
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif /* IUSBHOSTSERIALLISTENER_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost3GModule/WANDongle.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,235 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "dbg.h"
+#include <stdint.h>
+#include "rtos.h"
+
+#include "WANDongle.h"
+#include "WANDongleInitializer.h"
+
+WANDongle::WANDongle() : m_pInitializer(NULL), m_serialCount(0), m_totalInitializers(0)
+{
+    host = USBHost::getHostInst();
+    init();
+}
+
+
+bool WANDongle::connected() {
+  return dev_connected;
+}
+
+bool WANDongle::tryConnect()
+{
+  //FIXME should run on USB thread
+
+  USB_DBG("Trying to connect device");
+
+  if (dev_connected) {
+      USB_DBG("Device is already connected!");
+      return true;
+  }
+
+  m_pInitializer = NULL;
+
+  //Protect from concurrent access from USB thread
+  USBHost::Lock lock(host);
+
+  for (int i = 0; i < MAX_DEVICE_CONNECTED; i++)
+  {
+      if ((dev = host->getDevice(i)) != NULL)
+      {
+          m_pInitializer = NULL; //Will be set in setVidPid callback
+
+          USB_DBG("Enumerate");
+          int ret = host->enumerate(dev, this);
+          if(ret)
+          {
+            return false;
+          }
+
+          USB_DBG("Device has VID:%04x PID:%04x", dev->getVid(), dev->getPid());
+
+          if(m_pInitializer) //If an initializer has been found
+          {
+            USB_DBG("m_pInitializer=%p", m_pInitializer);
+            USB_DBG("m_pInitializer->getSerialVid()=%04x", m_pInitializer->getSerialVid());
+            USB_DBG("m_pInitializer->getSerialPid()=%04x", m_pInitializer->getSerialPid());
+            if ((dev->getVid() == m_pInitializer->getSerialVid()) && (dev->getPid() == m_pInitializer->getSerialPid()))
+            {
+              USB_DBG("The dongle is in virtual serial mode");
+              host->registerDriver(dev, 0, this, &WANDongle::init);
+              m_serialCount = m_pInitializer->getSerialPortCount();
+              if( m_serialCount > WANDONGLE_MAX_SERIAL_PORTS )
+              {
+                m_serialCount = WANDONGLE_MAX_SERIAL_PORTS;
+              }
+              for(int j = 0; j < m_serialCount; j++)
+              {
+                USB_DBG("Connecting serial port #%d", j+1);
+                USB_DBG("Ep %p", m_pInitializer->getEp(dev, j, false));
+                USB_DBG("Ep %p", m_pInitializer->getEp(dev, j, true));
+                m_serial[j].connect( dev, m_pInitializer->getEp(dev, j, false), m_pInitializer->getEp(dev, j, true) );
+              }
+
+              USB_DBG("Device connected");
+
+              dev_connected = true;
+
+
+              return true;
+            }
+            else if ((dev->getVid() == m_pInitializer->getMSDVid()) && (dev->getPid() == m_pInitializer->getMSDPid()))
+            {
+              USB_DBG("Vodafone K3370 dongle detected in MSD mode");
+              //Try to switch
+              if( m_pInitializer->switchMode(dev) )
+              {
+                USB_DBG("Switched OK");
+                return false; //Will be connected on a next iteration
+              }
+              else
+              {
+                USB_ERR("Could not switch mode");
+                return false;
+              }
+            }
+          } //if()
+      } //if()
+  } //for()
+  return false;
+}
+
+bool WANDongle::disconnect()
+{
+  dev_connected = false;
+  for(int i = 0; i < WANDONGLE_MAX_SERIAL_PORTS; i++)
+  {
+    m_serial[i].disconnect();
+  }
+  return true;
+}
+
+int WANDongle::getDongleType()
+{
+  if( m_pInitializer != NULL )
+  {
+    return m_pInitializer->getType();
+  }
+  else
+  {
+    return WAN_DONGLE_TYPE_UNKNOWN;
+  }
+}
+
+IUSBHostSerial& WANDongle::getSerial(int index)
+{
+  return m_serial[index];
+}
+
+int WANDongle::getSerialCount()
+{
+  return m_serialCount;
+}
+
+//Private methods
+void WANDongle::init()
+{
+  m_pInitializer = NULL;
+  dev_connected = false;
+  for(int i = 0; i < WANDONGLE_MAX_SERIAL_PORTS; i++)
+  {
+    m_serial[i].init(host);
+  }
+}
+
+
+/*virtual*/ void WANDongle::setVidPid(uint16_t vid, uint16_t pid)
+{
+  WANDongleInitializer* initializer;
+
+  for(int i = 0; i < m_totalInitializers; i++)
+  {
+    initializer = m_Initializers[i];
+    USB_DBG("initializer=%p", initializer);
+    USB_DBG("initializer->getSerialVid()=%04x", initializer->getSerialVid());
+    USB_DBG("initializer->getSerialPid()=%04x", initializer->getSerialPid());
+    if ((dev->getVid() == initializer->getSerialVid()) && (dev->getPid() == initializer->getSerialPid()))
+    {
+      USB_DBG("The dongle is in virtual serial mode");
+      m_pInitializer = initializer;
+      break;
+    }
+    else if ((dev->getVid() == initializer->getMSDVid()) && (dev->getPid() == initializer->getMSDPid()))
+    {
+      USB_DBG("Dongle detected in MSD mode");
+      m_pInitializer = initializer;
+      break;
+    }
+    initializer++;
+  } //for
+  if(m_pInitializer)
+  {
+    m_pInitializer->setVidPid(vid, pid);
+  }
+}
+
+/*virtual*/ bool WANDongle::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+  if(m_pInitializer)
+  {
+    return m_pInitializer->parseInterface(intf_nb, intf_class, intf_subclass, intf_protocol);
+  }
+  else
+  {
+    return false;
+  }
+}
+
+/*virtual*/ bool WANDongle::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+  if(m_pInitializer)
+  {
+    return m_pInitializer->useEndpoint(intf_nb, type, dir);
+  }
+  else
+  {
+    return false;
+  }
+}
+
+
+bool WANDongle::addInitializer(WANDongleInitializer* pInitializer)
+{
+  if (m_totalInitializers >= WANDONGLE_MAX_INITIALIZERS)
+    return false;
+  m_Initializers[m_totalInitializers++] = pInitializer;
+  return true;
+}
+
+WANDongle::~WANDongle()
+{
+  for(int i = 0; i < m_totalInitializers; i++)
+    delete m_Initializers[i];
+}
+
+#endif /* USBHOST_3GMODULE */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost3GModule/WANDongle.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,108 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLE_H
+#define WANDONGLE_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "USBHost.h"
+#include "IUSBHostSerial.h"
+
+#include "rtos.h"
+
+#include "WANDongleSerialPort.h"
+#include "WANDongleInitializer.h"
+#include "IUSBEnumerator.h"
+
+#define WANDONGLE_MAX_OUTEP_SIZE 64
+#define WANDONGLE_MAX_INEP_SIZE 64
+
+/** A class to use a WAN (3G/LTE) access dongle
+ *
+ */
+class WANDongle : public IUSBEnumerator {
+public:
+    /*
+    * Constructor
+    *
+    * @param rootdir mount name
+    */
+    WANDongle();
+
+    /*
+    * Destructor
+    */
+    virtual ~WANDongle();
+
+    /*
+    * Check if a serial port device is connected
+    *
+    * @return true if a serial device is connected
+    */
+    bool connected();
+
+    /*
+     * Try to connect device
+     *
+     * * @return true if connection was successful
+     */
+    bool tryConnect();
+
+    /*
+     * Disconnect device
+     *
+     * * @return true if disconnection was successful
+     */
+    bool disconnect();
+
+    int getDongleType();
+
+    IUSBHostSerial& getSerial(int index);
+    int getSerialCount();
+    bool addInitializer(WANDongleInitializer* pInitializer);
+
+    //From IUSBEnumerator
+
+    virtual void setVidPid(uint16_t vid, uint16_t pid);
+
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+protected:
+    USBHost * host;
+    USBDeviceConnected * dev;
+    bool dev_connected;
+
+    WANDongleInitializer* m_pInitializer;
+
+    void init();
+
+    WANDongleSerialPort m_serial[WANDONGLE_MAX_SERIAL_PORTS];
+    int m_serialCount;
+
+    int m_totalInitializers;
+    WANDongleInitializer* m_Initializers[WANDONGLE_MAX_INITIALIZERS];
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost3GModule/WANDongleInitializer.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,73 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLEINITIALIZER_H
+#define WANDONGLEINITIALIZER_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include <stdint.h>
+
+#include "USBHost.h"
+#include "IUSBEnumerator.h"
+
+// [TODO] move these declarations to a proper place
+#define WANDONGLE_MAX_SERIAL_PORTS 2
+#define WANDONGLE_MAX_INITIALIZERS 6
+
+#define WAN_DONGLE_TYPE_UNKNOWN    (-1)
+
+class WANDongleInitializer : public IUSBEnumerator
+{
+protected:
+    WANDongleInitializer(USBHost* pHost) { m_pHost = pHost; }
+    USBHost* m_pHost;
+    uint8_t m_serialIntfMap[WANDONGLE_MAX_SERIAL_PORTS];
+
+public:
+    virtual ~WANDongleInitializer() {}
+    virtual uint16_t getMSDVid() = 0;
+    virtual uint16_t getMSDPid() = 0;
+
+    virtual uint16_t getSerialVid() = 0;
+    virtual uint16_t getSerialPid() = 0;
+
+    virtual bool switchMode(USBDeviceConnected* pDev) = 0;
+
+    virtual USBEndpoint* getEp(USBDeviceConnected* pDev, int serialPortNumber, bool tx) {
+        return pDev->getEndpoint(m_serialIntfMap[serialPortNumber], BULK_ENDPOINT, tx ? OUT : IN, 0);
+    }
+
+    virtual int getSerialPortCount() = 0;
+
+    virtual void setVidPid(uint16_t vid, uint16_t pid) = 0;
+
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) = 0; //Must return true if the interface should be parsed
+
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) = 0; //Must return true if the endpoint will be used
+
+    virtual int getType() = 0;
+
+    virtual uint8_t getSerialIntf(int index) { return m_serialIntfMap[index]; }
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost3GModule/WANDongleSerialPort.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,351 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#define __DEBUG__ 0
+#ifndef __MODULE__
+#define __MODULE__ "WANDongleSerialPort.cpp"
+#endif
+
+#include "dbg.h"
+#include <stdint.h>
+#include "rtos.h"
+
+#include "WANDongleSerialPort.h"
+
+WANDongleSerialPort::WANDongleSerialPort() : cb_tx_en(false), cb_rx_en(false), listener(NULL)
+{
+#if defined(TARGET_RZ_A2XX)
+  buf_out = (uint8_t *)AllocNonCacheMem(WANDONGLE_MAX_OUTEP_SIZE);
+  buf_in  = (uint8_t *)AllocNonCacheMem(WANDONGLE_MAX_INEP_SIZE);
+#endif
+  reset();
+}
+
+#if defined(TARGET_RZ_A2XX)
+WANDongleSerialPort::~WANDongleSerialPort() {
+  FreeNonCacheMem(buf_out);
+  FreeNonCacheMem(buf_in);
+}
+#endif
+
+void WANDongleSerialPort::init(USBHost* pHost)
+{
+  host = pHost;
+}
+
+void WANDongleSerialPort::reset()
+{
+  tx_mtx.lock();
+  rx_mtx.lock();
+
+  bulk_in = NULL;
+  bulk_out = NULL;
+
+  buf_out_len = 0;
+  max_out_size = 0;
+  lock_tx = false;
+  cb_tx_pending = false;
+
+  buf_in_len = 0;
+  buf_in_read_pos = 0;
+  lock_rx = false;
+  cb_rx_pending = false;
+
+  tx_mtx.unlock();
+  rx_mtx.unlock();
+}
+
+int WANDongleSerialPort::readPacket()
+{
+  USB_DBG("Read packet on %p", this);
+  rx_mtx.lock();
+  if(lock_rx)
+  {
+    USB_ERR("Fail");
+    rx_mtx.unlock();
+    return -1;
+  }
+
+  if( bulk_in == NULL )
+  {
+    USB_WARN("Port is disconnected");
+    rx_mtx.unlock();
+    return -1;
+  }
+
+  lock_rx = true; //Receiving
+  rx_mtx.unlock();
+//  USB_DBG("readPacket");
+  //lock_rx.lock();
+  USB_TYPE res = host->bulkRead(dev, (USBEndpoint *)bulk_in, buf_in, ((USBEndpoint *)bulk_in)->getSize(), false); //Queue transfer
+  if(res != USB_TYPE_PROCESSING)
+  {
+    //lock_rx.unlock();
+    USB_ERR("host->bulkRead() returned %d", res);
+    ThisThread::sleep_for(100);
+    return -1;
+  }
+  return 0;
+}
+
+int WANDongleSerialPort::writePacket()
+{
+  tx_mtx.lock();
+  if(lock_tx)
+  {
+    USB_ERR("Fail");
+    tx_mtx.unlock();
+    return -1;
+  }
+
+  if( bulk_out == NULL )
+  {
+    USB_WARN("Port is disconnected");
+    tx_mtx.unlock();
+    return -1;
+  }
+
+  lock_tx = true; //Transmitting
+  tx_mtx.unlock();
+//  USB_DBG("writePacket");
+
+  //lock_tx.lock();
+  USB_TYPE res = host->bulkWrite(dev, (USBEndpoint *)bulk_out, buf_out, buf_out_len, false); //Queue transfer
+  if(res != USB_TYPE_PROCESSING)
+  {
+    //lock_tx.unlock();
+    USB_ERR("host->bulkWrite() returned %d", res);
+    ThisThread::sleep_for(100);
+    return -1;
+  }
+  return 0;
+}
+
+int WANDongleSerialPort::putc(int c)
+{
+  tx_mtx.lock();
+  if(!lock_tx)
+  {
+    if(buf_out_len < max_out_size)
+    {
+      buf_out[buf_out_len] = (uint8_t)c;
+      buf_out_len++;
+    }
+  }
+  else
+  {
+    USB_ERR("CAN'T WRITE!");
+  }
+  tx_mtx.unlock();
+  return c;
+}
+
+int WANDongleSerialPort::getc()
+{
+  rx_mtx.lock();
+  int c = 0;
+  if(!lock_rx)
+  {
+    if(buf_in_read_pos < buf_in_len)
+    {
+      c = (int)buf_in[buf_in_read_pos];
+      buf_in_read_pos++;
+    }
+  }
+  else
+  {
+    USB_ERR("CAN'T READ!");
+  }
+  rx_mtx.unlock();
+  return c;
+}
+
+int WANDongleSerialPort::readable()
+{
+  rx_mtx.lock();
+  if (lock_rx)
+  {
+    rx_mtx.unlock();
+    return 0;
+  }
+
+ /* if( !lock_rx.trylock() )
+  {
+    return 0;
+  }*/
+  int res = buf_in_len - buf_in_read_pos;
+  //lock_rx.unlock();
+  rx_mtx.unlock();
+  return res;
+}
+
+int WANDongleSerialPort::writeable()
+{
+  tx_mtx.lock();
+  if (lock_tx)
+  {
+    tx_mtx.unlock();
+    return 0;
+  }
+
+  /*if( !lock_tx.trylock() )
+  {
+    return 0;
+  }*/
+  int res = max_out_size - buf_out_len;
+  tx_mtx.unlock();
+ //lock_tx.unlock();
+  return res;
+}
+
+void WANDongleSerialPort::attach(IUSBHostSerialListener* pListener)
+{
+  if(pListener == NULL)
+  {
+    setupIrq(false, RxIrq);
+    setupIrq(false, TxIrq);
+  }
+  listener = pListener;
+  if(pListener != NULL)
+  {
+    setupIrq(true, RxIrq);
+    setupIrq(true, TxIrq);
+  }
+}
+
+void WANDongleSerialPort::setupIrq(bool en, IrqType irq /*= RxIrq*/)
+{
+  switch(irq)
+  {
+  case RxIrq:
+    rx_mtx.lock();
+    cb_rx_en = en;
+    if(en && cb_rx_pending)
+    {
+      cb_rx_pending = false;
+      rx_mtx.unlock();
+      listener->readable(); //Process the interrupt that was raised
+    }
+    else
+    {
+      rx_mtx.unlock();
+    }
+    break;
+  case TxIrq:
+    tx_mtx.lock();
+    cb_tx_en = en;
+    if(en && cb_tx_pending)
+    {
+      cb_tx_pending = false;
+      tx_mtx.unlock();
+      listener->writeable(); //Process the interrupt that was raised
+    }
+    else
+    {
+      tx_mtx.unlock();
+    }
+    break;
+  }
+}
+
+
+void WANDongleSerialPort::connect( USBDeviceConnected* pDev, USBEndpoint* pInEp, USBEndpoint* pOutEp )
+{
+  dev = pDev;
+  bulk_in = pInEp;
+  bulk_out = pOutEp;
+  max_out_size = bulk_out->getSize();
+  if( max_out_size > WANDONGLE_MAX_OUTEP_SIZE )
+  {
+    max_out_size = WANDONGLE_MAX_OUTEP_SIZE;
+  }
+  bulk_in->attach(this, &WANDongleSerialPort::rxHandler);
+  bulk_out->attach(this, &WANDongleSerialPort::txHandler);
+  readPacket(); //Start receiving data
+}
+
+void WANDongleSerialPort::disconnect( )
+{
+    reset();
+}
+
+//Private methods
+
+
+void WANDongleSerialPort::rxHandler()
+{
+  if (((USBEndpoint *) bulk_in)->getState() == USB_TYPE_IDLE) //Success
+  {
+    buf_in_read_pos = 0;
+    buf_in_len = ((USBEndpoint *) bulk_in)->getLengthTransferred(); //Update length
+    //lock_rx.unlock();
+    rx_mtx.lock();
+    lock_rx = false; //Transmission complete
+    if(cb_rx_en)
+    {
+      rx_mtx.unlock();
+      listener->readable(); //Call handler from the IRQ context
+      //readPacket() should be called by the handler subsequently once the buffer has been emptied
+    }
+    else
+    {
+      cb_rx_pending = true; //Queue the callback
+      rx_mtx.unlock();
+    }
+
+  }
+  else //Error, try reading again
+  {
+    //lock_rx.unlock();
+    USB_DBG("Trying again");
+    readPacket();
+  }
+}
+
+void WANDongleSerialPort::txHandler()
+{
+  if (((USBEndpoint *) bulk_out)->getState() == USB_TYPE_IDLE) //Success
+  {
+    tx_mtx.lock();
+    buf_out_len = 0; //Reset length
+    lock_tx = false; //Transmission complete
+    //lock_tx.unlock();
+    if(cb_tx_en)
+    {
+      tx_mtx.unlock();
+      listener->writeable(); //Call handler from the IRQ context
+      //writePacket() should be called by the handler subsequently once the buffer has been filled
+    }
+    else
+    {
+      cb_tx_pending = true; //Queue the callback
+      tx_mtx.unlock();
+    }
+  }
+  else //Error, try reading again
+  {
+    //lock_tx.unlock();
+    writePacket();
+  }
+}
+
+#endif /* USBHOST_3GMODULE */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHost3GModule/WANDongleSerialPort.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,144 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLESERIALPORT_H
+#define WANDONGLESERIALPORT_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "USBHost.h"
+#include "IUSBHostSerial.h"
+
+#include "rtos.h"
+
+
+#define WANDONGLE_MAX_OUTEP_SIZE 64
+#define WANDONGLE_MAX_INEP_SIZE 64
+
+/** A class to use a WAN (3G/LTE) access dongle
+ *
+ */
+class WANDongleSerialPort : public IUSBHostSerial {
+public:
+    /*
+    * Constructor
+    *
+    */
+    WANDongleSerialPort();
+#if defined(TARGET_RZ_A2XX)
+    virtual ~WANDongleSerialPort();
+#endif
+
+    void init( USBHost* pHost );
+
+    void connect( USBDeviceConnected* pDev, USBEndpoint* pInEp, USBEndpoint* pOutEp );
+
+    void disconnect( );
+
+    /*
+    * Get a char from the dongle's serial interface
+    */
+    virtual int getc();
+
+    /*
+    * Put a char to the dongle's serial interface
+    */
+    virtual int putc(int c);
+
+    /*
+     *  Read a packet from the dongle's serial interface, to be called after multiple getc() calls
+     */
+    virtual int readPacket();
+
+    /*
+     *  Write a packet to the dongle's serial interface, to be called after multiple putc() calls
+     */
+    virtual int writePacket();
+
+    /**
+    * Check the number of bytes available.
+    *
+    * @returns the number of bytes available
+    */
+    virtual int readable();
+
+    /**
+    * Check the free space in output.
+    *
+    * @returns the number of bytes available
+    */
+    virtual int writeable();
+
+    /**
+     *  Attach a handler to call when a packet is received / when a packet has been transmitted.
+     *
+     *  @param pListener instance of the listener deriving from the IUSBHostSerialListener
+     */
+    virtual void attach(IUSBHostSerialListener* pListener);
+
+    /**
+     * Enable or disable readable/writeable callbacks
+     */
+    virtual void setupIrq(bool en, IrqType irq = RxIrq);
+
+
+protected:
+    USBEndpoint * bulk_in;
+    USBEndpoint * bulk_out;
+    USBHost * host;
+    USBDeviceConnected * dev;
+
+#if defined(TARGET_RZ_A2XX)
+    uint8_t * buf_out;
+#else
+    uint8_t buf_out[WANDONGLE_MAX_OUTEP_SIZE];
+#endif
+    volatile uint32_t buf_out_len;
+    uint32_t max_out_size;
+    volatile bool lock_tx;
+    volatile bool cb_tx_en;
+    volatile bool cb_tx_pending;
+    rtos::Mutex tx_mtx;
+
+#if defined(TARGET_RZ_A2XX)
+    uint8_t * buf_in;
+#else
+    uint8_t buf_in[WANDONGLE_MAX_INEP_SIZE];
+#endif
+    volatile uint32_t buf_in_len;
+    volatile uint32_t buf_in_read_pos;
+    volatile bool lock_rx;
+    volatile bool cb_rx_en;
+    volatile bool cb_rx_pending;
+    rtos::Mutex rx_mtx;
+
+    IUSBHostSerialListener* listener;
+
+    void reset();
+
+    void rxHandler();
+    void txHandler();
+
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHostHID/USBHostKeyboard.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,192 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostKeyboard.h"
+
+#if USBHOST_KEYBOARD
+
+static uint8_t keymap[4][0x39] = {
+    { 0, 0, 0, 0, 'a', 'b' /*0x05*/,
+      'c', 'd', 'e', 'f', 'g' /*0x0a*/,
+      'h', 'i', 'j', 'k', 'l'/*0x0f*/,
+      'm', 'n', 'o', 'p', 'q'/*0x14*/,
+      'r', 's', 't', 'u', 'v'/*0x19*/,
+      'w', 'x', 'y', 'z', '1'/*0x1E*/,
+      '2', '3', '4', '5', '6'/*0x23*/,
+      '7', '8', '9', '0', 0x0A /*enter*/, /*0x28*/
+      0x1B /*escape*/, 0x08 /*backspace*/, 0x09/*tab*/, 0x20/*space*/, '-', /*0x2d*/
+      '=', '[', ']', '\\', '#', /*0x32*/
+      ';', '\'', 0, ',', '.', /*0x37*/
+      '/'},
+
+    /* CTRL MODIFIER */
+    { 0, 0, 0, 0, 0, 0 /*0x05*/,
+      0, 0, 0, 0, 0 /*0x0a*/,
+      0, 0, 0, 0, 0/*0x0f*/,
+      0, 0, 0, 0, 0/*0x14*/,
+      0, 0, 0, 0, 0/*0x19*/,
+      0, 0, 0, 0, 0/*0x1E*/,
+      0, 0, 0, 0, 0/*0x23*/,
+      0, 0, 0, 0, 0 /*enter*/, /*0x28*/
+      0, 0, 0, 0, 0, /*0x2d*/
+      0, 0, 0, 0, 0, /*0x32*/
+      0, 0, 0, 0, 0, /*0x37*/
+      0},
+
+    /* SHIFT MODIFIER */
+    { 0, 0, 0, 0, 'A', 'B' /*0x05*/,
+      'C', 'D', 'E', 'F', 'G' /*0x0a*/,
+      'H', 'I', 'J', 'K', 'L'/*0x0f*/,
+      'M', 'N', 'O', 'P', 'Q'/*0x14*/,
+      'R', 'S', 'T', 'U', 'V'/*0x19*/,
+      'W', 'X', 'Y', 'Z', '!'/*0x1E*/,
+      '@', '#', '$', '%', '^'/*0x23*/,
+      '&', '*', '(', ')', 0, /*0x28*/
+      0, 0, 0, 0, 0, /*0x2d*/
+      '+', '{', '}', '|', '~', /*0x32*/
+      ':', '"', 0, '<', '>', /*0x37*/
+      '?'},
+
+    /* ALT MODIFIER */
+    { 0, 0, 0, 0, 0, 0 /*0x05*/,
+      0, 0, 0, 0, 0 /*0x0a*/,
+      0, 0, 0, 0, 0/*0x0f*/,
+      0, 0, 0, 0, 0/*0x14*/,
+      0, 0, 0, 0, 0/*0x19*/,
+      0, 0, 0, 0, 0/*0x1E*/,
+      0, 0, 0, 0, 0/*0x23*/,
+      0, 0, 0, 0, 0 /*enter*/, /*0x28*/
+      0, 0, 0, 0, 0, /*0x2d*/
+      0, 0, 0, 0, 0, /*0x32*/
+      0, 0, 0, 0, 0, /*0x37*/
+      0}
+
+};
+
+
+USBHostKeyboard::USBHostKeyboard() {
+    host = USBHost::getHostInst();
+#if defined(TARGET_RZ_A2XX)
+    report  = (uint8_t *)AllocNonCacheMem(9);
+#endif
+    init();
+}
+
+#if defined(TARGET_RZ_A2XX)
+USBHostKeyboard::~USBHostKeyboard() {
+  FreeNonCacheMem(report);
+}
+#endif
+
+void USBHostKeyboard::init() {
+    dev = NULL;
+    int_in = NULL;
+    report_id = 0;
+    onKey = NULL;
+    onKeyCode = NULL;
+    dev_connected = false;
+    keyboard_intf = -1;
+    keyboard_device_found = false;
+}
+
+bool USBHostKeyboard::connected() {
+    return dev_connected;
+}
+
+
+bool USBHostKeyboard::connect() {
+
+    if (dev_connected) {
+        return true;
+    }
+
+    for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        if ((dev = host->getDevice(i)) != NULL) {
+
+            if (host->enumerate(dev, this))
+                break;
+
+            if (keyboard_device_found) {
+                int_in = dev->getEndpoint(keyboard_intf, INTERRUPT_ENDPOINT, IN);
+
+                if (!int_in)
+                    break;
+
+                USB_INFO("New Keyboard device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, keyboard_intf);
+                dev->setName("Keyboard", keyboard_intf);
+                host->registerDriver(dev, keyboard_intf, this, &USBHostKeyboard::init);
+
+                int_in->attach(this, &USBHostKeyboard::rxHandler);
+                host->interruptRead(dev, int_in, report, int_in->getSize(), false);
+
+                dev_connected = true;
+                return true;
+            }
+        }
+    }
+    init();
+    return false;
+}
+
+void USBHostKeyboard::rxHandler() {
+    int len = int_in->getLengthTransferred();
+    int index = (len == 9) ? 1 : 0;
+    int len_listen = int_in->getSize();
+    uint8_t key = 0;
+    if (len == 8 || len == 9) {
+        uint8_t modifier = (report[index] == 4) ? 3 : report[index];
+        len_listen = len;
+        key = keymap[modifier][report[index + 2]];
+        if (key && onKey) {
+            (*onKey)(key);
+        }
+        if ((report[index + 2] || modifier) && onKeyCode) {
+            (*onKeyCode)(report[index + 2], modifier);
+        }
+    }
+    if (dev && int_in)
+        host->interruptRead(dev, int_in, report, len_listen, false);
+}
+
+/*virtual*/ void USBHostKeyboard::setVidPid(uint16_t vid, uint16_t pid)
+{
+    // we don't check VID/PID for keyboard driver
+}
+
+/*virtual*/ bool USBHostKeyboard::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+    if ((keyboard_intf == -1) &&
+        (intf_class == HID_CLASS) &&
+        (intf_subclass == 0x01) &&
+        (intf_protocol == 0x01)) {
+        keyboard_intf = intf_nb;
+        return true;
+    }
+    return false;
+}
+
+/*virtual*/ bool USBHostKeyboard::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+    if (intf_nb == keyboard_intf) {
+        if (type == INTERRUPT_ENDPOINT && dir == IN) {
+            keyboard_device_found = true;
+            return true;
+        }
+    }
+    return false;
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHostHID/USBHostKeyboard.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,109 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTKEYBOARD_H
+#define USBHOSTKEYBOARD_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_KEYBOARD
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB keyboard
+ */
+class USBHostKeyboard : public IUSBEnumerator {
+public:
+
+    /**
+    * Constructor
+    */
+    USBHostKeyboard();
+#if defined(TARGET_RZ_A2XX)
+    ~USBHostKeyboard();
+#endif
+
+    /**
+     * Try to connect a keyboard device
+     *
+     * @return true if connection was successful
+     */
+    bool connect();
+
+    /**
+    * Check if a keyboard is connected
+    *
+    * @returns true if a keyboard is connected
+    */
+    bool connected();
+
+    /**
+     * Attach a callback called when a keyboard event is received
+     *
+     * @param ptr function pointer
+     */
+    inline void attach(void (*ptr)(uint8_t key)) {
+        if (ptr != NULL) {
+            onKey = ptr;
+        }
+    }
+
+    /**
+     * Attach a callback called when a keyboard event is received
+     *
+     * @param ptr function pointer
+     */
+    inline void attach(void (*ptr)(uint8_t keyCode, uint8_t modifier)) {
+        if (ptr != NULL) {
+            onKeyCode = ptr;
+        }
+    }
+
+protected:
+    //From IUSBEnumerator
+    virtual void setVidPid(uint16_t vid, uint16_t pid);
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+    USBHost * host;
+    USBDeviceConnected * dev;
+    USBEndpoint * int_in;
+#if defined(TARGET_RZ_A2XX)
+    uint8_t * report;
+#else
+    uint8_t report[9];
+#endif
+    int keyboard_intf;
+    bool keyboard_device_found;
+
+    bool dev_connected;
+
+    void rxHandler();
+
+    void (*onKey)(uint8_t key);
+    void (*onKeyCode)(uint8_t key, uint8_t modifier);
+
+    int report_id;
+
+    void init();
+
+};
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHostHID/USBHostMouse.cpp	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,230 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostMouse.h"
+
+#if USBHOST_MOUSE
+
+USBHostMouse::USBHostMouse() {
+    host = USBHost::getHostInst();
+#if defined(TARGET_RZ_A2XX)
+    report  = (uint8_t *)AllocNonCacheMem(8);
+#endif
+    init();
+}
+
+#if defined(TARGET_RZ_A2XX)
+USBHostMouse::~USBHostMouse() {
+  FreeNonCacheMem(report);
+}
+#endif
+
+void USBHostMouse::init() {
+    dev = NULL;
+    int_in = NULL;
+    onUpdate = NULL;
+    onButtonUpdate = NULL;
+    onXUpdate = NULL;
+    onYUpdate = NULL;
+    onZUpdate = NULL;
+    report_id = 0;
+    dev_connected = false;
+    mouse_device_found = false;
+    mouse_intf = -1;
+
+    buttons = 0;
+    x = 0;
+    y = 0;
+    z = 0;
+}
+
+bool USBHostMouse::connected() {
+    return dev_connected;
+}
+
+bool USBHostMouse::connect() {
+    int len_listen;
+
+    if (dev_connected) {
+        return true;
+    }
+
+    for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        if ((dev = host->getDevice(i)) != NULL) {
+
+            if(host->enumerate(dev, this))
+                break;
+
+            if (mouse_device_found) {
+
+                int_in = dev->getEndpoint(mouse_intf, INTERRUPT_ENDPOINT, IN);
+                if (!int_in)
+                    break;
+
+                USB_INFO("New Mouse device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, mouse_intf);
+                dev->setName("Mouse", mouse_intf);
+                host->registerDriver(dev, mouse_intf, this, &USBHostMouse::init);
+
+                int_in->attach(this, &USBHostMouse::rxHandler);
+                len_listen = int_in->getSize();
+#if defined(TARGET_RZ_A2XX)
+                if ((uint32_t)len_listen > 8) {
+                    len_listen = 8;
+                }
+#else
+                if ((uint32_t)len_listen > sizeof(report)) {
+                    len_listen = sizeof(report);
+                }
+#endif
+                host->interruptRead(dev, int_in, report, len_listen, false);
+
+                dev_connected = true;
+                return true;
+            }
+        }
+    }
+    init();
+    return false;
+}
+
+void USBHostMouse::rxHandler() {
+    int len_listen = int_in->getSize();
+
+    if ((dev->getVid() == 0x046d) && (dev->getPid() == 0xc52b)) {
+        int wk_x;
+        int wk_y;
+
+        wk_x = ((report[4] & 0x0F) << 8) | report[3];
+        if (wk_x <= 0x7ff) {
+            if (wk_x > 0x7f) {
+                wk_x = 0x7f;
+            }
+        } else {
+            wk_x = -(0xfff - wk_x);
+            if (wk_x < -128) {
+                wk_x = -128;
+            }
+        }
+
+        wk_y = (report[5] << 4) | ((report[4] & 0xF0) >> 4);
+        if (wk_y <= 0x7ff) {
+            if (wk_y > 0x7f) {
+                wk_y = 0x7f;
+            }
+        } else {
+            wk_y = -(0xfff - wk_y);
+            if (wk_y < -128) {
+                wk_y = -128;
+            }
+        }
+
+        if (onUpdate) {
+            (*onUpdate)(report[1] & 0x07, (int8_t)wk_x, (int8_t)wk_y, report[6]);
+        }
+
+        if (onButtonUpdate && (buttons != (report[1] & 0x07))) {
+            (*onButtonUpdate)(report[1] & 0x07);
+        }
+
+        if (onXUpdate && (x != (int8_t)wk_x)) {
+            (*onXUpdate)((int8_t)wk_x);
+        }
+
+        if (onYUpdate && (y != (int8_t)wk_y)) {
+            (*onYUpdate)((int8_t)wk_y);
+        }
+
+        if (onZUpdate && (z != report[6])) {
+            (*onZUpdate)(report[6]);
+        }
+
+        // update mouse state
+        buttons = report[1] & 0x07;
+
+        x = (int8_t)wk_x;
+        y = (int8_t)wk_y;
+        z = report[6];
+    } else {
+        if (onUpdate) {
+            (*onUpdate)(report[0] & 0x07, report[1], report[2], report[3]);
+        }
+
+        if (onButtonUpdate && (buttons != (report[0] & 0x07))) {
+            (*onButtonUpdate)(report[0] & 0x07);
+        }
+
+        if (onXUpdate && (x != report[1])) {
+            (*onXUpdate)(report[1]);
+        }
+
+        if (onYUpdate && (y != report[2])) {
+            (*onYUpdate)(report[2]);
+        }
+
+        if (onZUpdate && (z != report[3])) {
+            (*onZUpdate)(report[3]);
+        }
+
+        // update mouse state
+        buttons = report[0] & 0x07;
+        x = report[1];
+        y = report[2];
+        z = report[3];
+    }
+
+#if defined(TARGET_RZ_A2XX)
+    if ((uint32_t)len_listen > 8) {
+        len_listen = 8;
+    }
+#else
+    if ((uint32_t)len_listen > sizeof(report)) {
+        len_listen = sizeof(report);
+    }
+#endif
+
+    if (dev)
+        host->interruptRead(dev, int_in, report, len_listen, false);
+}
+
+/*virtual*/ void USBHostMouse::setVidPid(uint16_t vid, uint16_t pid)
+{
+    // we don't check VID/PID for mouse driver
+}
+
+/*virtual*/ bool USBHostMouse::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+    if ((mouse_intf == -1) &&
+        (intf_class == HID_CLASS) &&
+        (intf_subclass == 0x01) &&
+        (intf_protocol == 0x02)) {
+        mouse_intf = intf_nb;
+        return true;
+    }
+    return false;
+}
+
+/*virtual*/ bool USBHostMouse::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+    if (intf_nb == mouse_intf) {
+        if (type == INTERRUPT_ENDPOINT && dir == IN) {
+            mouse_device_found = true;
+            return true;
+        }
+    }
+    return false;
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-gr-libs/USBHost_custom/USBHostHID/USBHostMouse.h	Fri Oct 18 03:09:43 2019 +0000
@@ -0,0 +1,146 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTMOUSE_H
+#define USBHOSTMOUSE_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_MOUSE
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB mouse
+ */
+class USBHostMouse : public IUSBEnumerator {
+public:
+
+    /**
+    * Constructor
+    */
+    USBHostMouse();
+#if defined(TARGET_RZ_A2XX)
+    ~USBHostMouse();
+#endif
+
+    /**
+     * Try to connect a mouse device
+     *
+     * @return true if connection was successful
+     */
+    bool connect();
+
+    /**
+    * Check if a mouse is connected
+    *
+    * @returns true if a mouse is connected
+    */
+    bool connected();
+
+    /**
+     * Attach a callback called when a mouse event is received
+     *
+     * @param ptr function pointer
+     */
+    inline void attachEvent(void (*ptr)(uint8_t buttons, int8_t x, int8_t y, int8_t z)) {
+        if (ptr != NULL) {
+            onUpdate = ptr;
+        }
+    }
+
+    /**
+     * Attach a callback called when the button state changes
+     *
+     * @param ptr function pointer
+     */
+    inline void attachButtonEvent(void (*ptr)(uint8_t buttons)) {
+        if (ptr != NULL) {
+            onButtonUpdate = ptr;
+        }
+    }
+
+    /**
+     * Attach a callback called when the X axis value changes
+     *
+     * @param ptr function pointer
+     */
+    inline void attachXEvent(void (*ptr)(int8_t x)) {
+        if (ptr != NULL) {
+            onXUpdate = ptr;
+        }
+    }
+
+    /**
+     * Attach a callback called when the Y axis value changes
+     *
+     * @param ptr function pointer
+     */
+    inline void attachYEvent(void (*ptr)(int8_t y)) {
+        if (ptr != NULL) {
+            onYUpdate = ptr;
+        }
+    }
+
+    /**
+     * Attach a callback called when the Z axis value changes (scrolling)
+     *
+     * @param ptr function pointer
+     */
+    inline void attachZEvent(void (*ptr)(int8_t z)) {
+        if (ptr != NULL) {
+            onZUpdate = ptr;
+        }
+    }
+
+protected:
+    //From IUSBEnumerator
+    virtual void setVidPid(uint16_t vid, uint16_t pid);
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+    USBHost * host;
+    USBDeviceConnected * dev;
+    USBEndpoint * int_in;
+#if defined(TARGET_RZ_A2XX)
+    uint8_t * report;
+#else
+    uint8_t report[8];
+#endif
+
+    bool dev_connected;
+    bool mouse_device_found;
+    int mouse_intf;
+
+    uint8_t buttons;
+    int8_t x;
+    int8_t y;
+    int8_t z;
+
+    void rxHandler();
+    void (*onUpdate)(uint8_t buttons, int8_t x, int8_t y, int8_t z);
+    void (*onButtonUpdate)(uint8_t buttons);
+    void (*onXUpdate)(int8_t x);
+    void (*onYUpdate)(int8_t y);
+    void (*onZUpdate)(int8_t z);
+    int report_id;
+    void init();
+};
+
+#endif
+
+#endif