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mbed-gr-libs/R_BSP/api/R_BSP_SsifDef.h@0:e9fd5575b10e, 2019-10-18 (annotated)

Committer:
anhtran
Date:
Fri Oct 18 03:09:43 2019 +0000
Revision:
0:e9fd5575b10e
abc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
anhtran 0:e9fd5575b10e 1 /*******************************************************************************
anhtran 0:e9fd5575b10e 2 * DISCLAIMER
anhtran 0:e9fd5575b10e 3 * This software is supplied by Renesas Electronics Corporation and is only
anhtran 0:e9fd5575b10e 4 * intended for use with Renesas products. No other uses are authorized. This
anhtran 0:e9fd5575b10e 5 * software is owned by Renesas Electronics Corporation and is protected under
anhtran 0:e9fd5575b10e 6 * all applicable laws, including copyright laws.
anhtran 0:e9fd5575b10e 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
anhtran 0:e9fd5575b10e 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
anhtran 0:e9fd5575b10e 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
anhtran 0:e9fd5575b10e 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
anhtran 0:e9fd5575b10e 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
anhtran 0:e9fd5575b10e 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
anhtran 0:e9fd5575b10e 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
anhtran 0:e9fd5575b10e 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
anhtran 0:e9fd5575b10e 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
anhtran 0:e9fd5575b10e 16 * Renesas reserves the right, without notice, to make changes to this software
anhtran 0:e9fd5575b10e 17 * and to discontinue the availability of this software. By using this software,
anhtran 0:e9fd5575b10e 18 * you agree to the additional terms and conditions found by accessing the
anhtran 0:e9fd5575b10e 19 * following link:
anhtran 0:e9fd5575b10e 20 * http://www.renesas.com/disclaimer
anhtran 0:e9fd5575b10e 21 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
anhtran 0:e9fd5575b10e 22 *******************************************************************************/
anhtran 0:e9fd5575b10e 23 /**************************************************************************//**
anhtran 0:e9fd5575b10e 24 * @file R_BSP_SsifDef.h
anhtran 0:e9fd5575b10e 25 * @brief SSIF defines
anhtran 0:e9fd5575b10e 26 ******************************************************************************/
anhtran 0:e9fd5575b10e 27
anhtran 0:e9fd5575b10e 28 #ifndef R_BSP_SSIF_DEF_H
anhtran 0:e9fd5575b10e 29 #define R_BSP_SSIF_DEF_H
anhtran 0:e9fd5575b10e 30
anhtran 0:e9fd5575b10e 31 /******************************************************************************
anhtran 0:e9fd5575b10e 32 Includes <System Includes> , "Project Includes"
anhtran 0:e9fd5575b10e 33 ******************************************************************************/
anhtran 0:e9fd5575b10e 34
anhtran 0:e9fd5575b10e 35 #ifdef __cplusplus
anhtran 0:e9fd5575b10e 36 extern "C"
anhtran 0:e9fd5575b10e 37 {
anhtran 0:e9fd5575b10e 38 #endif /* __cplusplus */
anhtran 0:e9fd5575b10e 39
anhtran 0:e9fd5575b10e 40 /******************************************************************************
anhtran 0:e9fd5575b10e 41 Defines
anhtran 0:e9fd5575b10e 42 *****************************************************************************/
anhtran 0:e9fd5575b10e 43
anhtran 0:e9fd5575b10e 44 /******************************************************************************
anhtran 0:e9fd5575b10e 45 Constant Macros
anhtran 0:e9fd5575b10e 46 *****************************************************************************/
anhtran 0:e9fd5575b10e 47 #if defined(TARGET_RZA1H)
anhtran 0:e9fd5575b10e 48 #define SSIF_NUM_CHANS (6u) /**< Number of SSIF channels */
anhtran 0:e9fd5575b10e 49 #else
anhtran 0:e9fd5575b10e 50 #define SSIF_NUM_CHANS (4u) /**< Number of SSIF channels */
anhtran 0:e9fd5575b10e 51 #endif
anhtran 0:e9fd5575b10e 52
anhtran 0:e9fd5575b10e 53 #define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u) /* Disable SSIRDR->STRMDIN0 route */
anhtran 0:e9fd5575b10e 54 #define SSIF_CFG_ENABLE_ROMDEC_DIRECT (0xDEC0DEC1u) /* Enable SSIRDR->STRMDIN0 route */
anhtran 0:e9fd5575b10e 55
anhtran 0:e9fd5575b10e 56 /******************************************************************************
anhtran 0:e9fd5575b10e 57 Function Macros
anhtran 0:e9fd5575b10e 58 *****************************************************************************/
anhtran 0:e9fd5575b10e 59
anhtran 0:e9fd5575b10e 60 /******************************************************************************
anhtran 0:e9fd5575b10e 61 Enumerated Types
anhtran 0:e9fd5575b10e 62 *****************************************************************************/
anhtran 0:e9fd5575b10e 63
anhtran 0:e9fd5575b10e 64 /** SSICR:CKS(Clock source for oversampling) */
anhtran 0:e9fd5575b10e 65 typedef enum
anhtran 0:e9fd5575b10e 66 {
anhtran 0:e9fd5575b10e 67 SSIF_CFG_CKS_AUDIO_X1 = 0, /**< select AUDIO_X1 */
anhtran 0:e9fd5575b10e 68 SSIF_CFG_CKS_AUDIO_CLK = 1 /**< select AUIDIO_CLK */
anhtran 0:e9fd5575b10e 69 } ssif_chcfg_cks_t;
anhtran 0:e9fd5575b10e 70
anhtran 0:e9fd5575b10e 71 /** SSICR:CHNL(Audio channels per system word) */
anhtran 0:e9fd5575b10e 72 typedef enum
anhtran 0:e9fd5575b10e 73 {
anhtran 0:e9fd5575b10e 74 SSIF_CFG_MULTI_CH_1 = 0, /**< 1ch within systemword (on tdm=0) */
anhtran 0:e9fd5575b10e 75 SSIF_CFG_MULTI_CH_2 = 1, /**< 2ch within systemword (on tdm=0) */
anhtran 0:e9fd5575b10e 76 SSIF_CFG_MULTI_CH_3 = 2, /**< 3ch within systemword (on tdm=0) */
anhtran 0:e9fd5575b10e 77 SSIF_CFG_MULTI_CH_4 = 3 /**< 4ch within systemword (on tdm=0) */
anhtran 0:e9fd5575b10e 78 } ssif_chcfg_multi_ch_t;
anhtran 0:e9fd5575b10e 79
anhtran 0:e9fd5575b10e 80 /** SSICR:DWL(Data word length) */
anhtran 0:e9fd5575b10e 81 typedef enum
anhtran 0:e9fd5575b10e 82 {
anhtran 0:e9fd5575b10e 83 SSIF_CFG_DATA_WORD_8 = 0, /**< Data word length 8 */
anhtran 0:e9fd5575b10e 84 SSIF_CFG_DATA_WORD_16 = 1, /**< Data word length 16 */
anhtran 0:e9fd5575b10e 85 SSIF_CFG_DATA_WORD_18 = 2, /**< Data word length 18 */
anhtran 0:e9fd5575b10e 86 SSIF_CFG_DATA_WORD_20 = 3, /**< Data word length 20 */
anhtran 0:e9fd5575b10e 87 SSIF_CFG_DATA_WORD_22 = 4, /**< Data word length 22 */
anhtran 0:e9fd5575b10e 88 SSIF_CFG_DATA_WORD_24 = 5, /**< Data word length 24 */
anhtran 0:e9fd5575b10e 89 SSIF_CFG_DATA_WORD_32 = 6 /**< Data word length 32 */
anhtran 0:e9fd5575b10e 90 } ssif_chcfg_data_word_t;
anhtran 0:e9fd5575b10e 91
anhtran 0:e9fd5575b10e 92 /** SSICR:SWL(System word length) */
anhtran 0:e9fd5575b10e 93 typedef enum
anhtran 0:e9fd5575b10e 94 {
anhtran 0:e9fd5575b10e 95 SSIF_CFG_SYSTEM_WORD_8 = 0, /**< System word length 8 */
anhtran 0:e9fd5575b10e 96 SSIF_CFG_SYSTEM_WORD_16 = 1, /**< System word length 16 */
anhtran 0:e9fd5575b10e 97 SSIF_CFG_SYSTEM_WORD_24 = 2, /**< System word length 24 */
anhtran 0:e9fd5575b10e 98 SSIF_CFG_SYSTEM_WORD_32 = 3, /**< System word length 32 */
anhtran 0:e9fd5575b10e 99 SSIF_CFG_SYSTEM_WORD_48 = 4, /**< System word length 48 */
anhtran 0:e9fd5575b10e 100 SSIF_CFG_SYSTEM_WORD_64 = 5, /**< System word length 64 */
anhtran 0:e9fd5575b10e 101 SSIF_CFG_SYSTEM_WORD_128 = 6, /**< System word length 128 */
anhtran 0:e9fd5575b10e 102 SSIF_CFG_SYSTEM_WORD_256 = 7 /**< System word length 256 */
anhtran 0:e9fd5575b10e 103 } ssif_chcfg_system_word_t;
anhtran 0:e9fd5575b10e 104
anhtran 0:e9fd5575b10e 105 /** SSICR:SCKP(Clock polarity) */
anhtran 0:e9fd5575b10e 106 typedef enum
anhtran 0:e9fd5575b10e 107 {
anhtran 0:e9fd5575b10e 108 SSIF_CFG_FALLING = 0, /**< Falling edge */
anhtran 0:e9fd5575b10e 109 SSIF_CFG_RISING = 1 /**< Rising edge */
anhtran 0:e9fd5575b10e 110 } ssif_chcfg_clock_pol_t;
anhtran 0:e9fd5575b10e 111
anhtran 0:e9fd5575b10e 112 /** SSICR:SWSP(Word select polarity) */
anhtran 0:e9fd5575b10e 113 typedef enum
anhtran 0:e9fd5575b10e 114 {
anhtran 0:e9fd5575b10e 115 SSIF_CFG_WS_LOW = 0, /**< Low for ther 1st channel(not TDM) */
anhtran 0:e9fd5575b10e 116 SSIF_CFG_WS_HIGH = 1 /**< High for the 1st channel(not TDM) */
anhtran 0:e9fd5575b10e 117 } ssif_chcfg_ws_pol_t;
anhtran 0:e9fd5575b10e 118
anhtran 0:e9fd5575b10e 119 /** SSICR:SPDP(Serial padding polarity) */
anhtran 0:e9fd5575b10e 120 typedef enum
anhtran 0:e9fd5575b10e 121 {
anhtran 0:e9fd5575b10e 122 SSIF_CFG_PADDING_LOW = 0, /**< Padding bits are low */
anhtran 0:e9fd5575b10e 123 SSIF_CFG_PADDING_HIGH = 1 /**< Padding bits are high */
anhtran 0:e9fd5575b10e 124 } ssif_chcfg_padding_pol_t;
anhtran 0:e9fd5575b10e 125
anhtran 0:e9fd5575b10e 126 /** SSICR:SDTA(Serial data alignment) */
anhtran 0:e9fd5575b10e 127 typedef enum
anhtran 0:e9fd5575b10e 128 {
anhtran 0:e9fd5575b10e 129 SSIF_CFG_DATA_FIRST = 0, /**< Data first */
anhtran 0:e9fd5575b10e 130 SSIF_CFG_PADDING_FIRST = 1 /**< Padding bits first */
anhtran 0:e9fd5575b10e 131 } ssif_chcfg_serial_alignment_t;
anhtran 0:e9fd5575b10e 132
anhtran 0:e9fd5575b10e 133 /** SSICR:PDTA(Parallel data alignment) */
anhtran 0:e9fd5575b10e 134 typedef enum
anhtran 0:e9fd5575b10e 135 {
anhtran 0:e9fd5575b10e 136 SSIF_CFG_LEFT = 0, /**< Left aligned */
anhtran 0:e9fd5575b10e 137 SSIF_CFG_RIGHT = 1 /**< Right aligned */
anhtran 0:e9fd5575b10e 138 } ssif_chcfg_parallel_alignment_t;
anhtran 0:e9fd5575b10e 139
anhtran 0:e9fd5575b10e 140 /** SSICR:DEL(Serial data delay) */
anhtran 0:e9fd5575b10e 141 typedef enum
anhtran 0:e9fd5575b10e 142 {
anhtran 0:e9fd5575b10e 143 SSIF_CFG_DELAY = 0, /**< 1 clock delay */
anhtran 0:e9fd5575b10e 144 SSIF_CFG_NO_DELAY = 1 /**< No delay */
anhtran 0:e9fd5575b10e 145 } ssif_chcfg_ws_delay_t;
anhtran 0:e9fd5575b10e 146
anhtran 0:e9fd5575b10e 147 /** SSICR:CKDV(Serial oversampling clock division ratio) */
anhtran 0:e9fd5575b10e 148 typedef enum
anhtran 0:e9fd5575b10e 149 {
anhtran 0:e9fd5575b10e 150 SSIF_CFG_CKDV_BITS_1 = 0,
anhtran 0:e9fd5575b10e 151 SSIF_CFG_CKDV_BITS_2 = 1,
anhtran 0:e9fd5575b10e 152 SSIF_CFG_CKDV_BITS_4 = 2,
anhtran 0:e9fd5575b10e 153 SSIF_CFG_CKDV_BITS_8 = 3,
anhtran 0:e9fd5575b10e 154 SSIF_CFG_CKDV_BITS_16 = 4,
anhtran 0:e9fd5575b10e 155 SSIF_CFG_CKDV_BITS_32 = 5,
anhtran 0:e9fd5575b10e 156 SSIF_CFG_CKDV_BITS_64 = 6,
anhtran 0:e9fd5575b10e 157 SSIF_CFG_CKDV_BITS_128 = 7,
anhtran 0:e9fd5575b10e 158 SSIF_CFG_CKDV_BITS_6 = 8,
anhtran 0:e9fd5575b10e 159 SSIF_CFG_CKDV_BITS_12 = 9,
anhtran 0:e9fd5575b10e 160 SSIF_CFG_CKDV_BITS_24 = 10,
anhtran 0:e9fd5575b10e 161 SSIF_CFG_CKDV_BITS_48 = 11,
anhtran 0:e9fd5575b10e 162 SSIF_CFG_CKDV_BITS_96 = 12
anhtran 0:e9fd5575b10e 163 } ssif_chcfg_ckdv_t;
anhtran 0:e9fd5575b10e 164
anhtran 0:e9fd5575b10e 165
anhtran 0:e9fd5575b10e 166 /** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
anhtran 0:e9fd5575b10e 167 typedef enum
anhtran 0:e9fd5575b10e 168 {
anhtran 0:e9fd5575b10e 169 SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
anhtran 0:e9fd5575b10e 170 SSIF_CFG_ENABLE_NOISE_CANCEL = 1 /**< Use noise cancel function */
anhtran 0:e9fd5575b10e 171 } ssif_chcfg_noise_cancel_t;
anhtran 0:e9fd5575b10e 172
anhtran 0:e9fd5575b10e 173
anhtran 0:e9fd5575b10e 174 /** SSITDMR:TDM(TDM mode) */
anhtran 0:e9fd5575b10e 175 typedef enum
anhtran 0:e9fd5575b10e 176 {
anhtran 0:e9fd5575b10e 177 SSIF_CFG_DISABLE_TDM = 0, /**< not TDM mode */
anhtran 0:e9fd5575b10e 178 SSIF_CFG_ENABLE_TDM = 1 /**< set TDM mode */
anhtran 0:e9fd5575b10e 179 } ssif_chcfg_tdm_t;
anhtran 0:e9fd5575b10e 180
anhtran 0:e9fd5575b10e 181 /******************************************************************************
anhtran 0:e9fd5575b10e 182 Structures
anhtran 0:e9fd5575b10e 183 *****************************************************************************/
anhtran 0:e9fd5575b10e 184
anhtran 0:e9fd5575b10e 185 /** It's used for ROMDEC direct transfer mode and the call back function registration. */
anhtran 0:e9fd5575b10e 186 typedef struct
anhtran 0:e9fd5575b10e 187 {
anhtran 0:e9fd5575b10e 188 uint32_t mode; /**< Enable/Disable SSIRDR->STRMDIN0 route (Invalid in GR_LYCHEE) */
anhtran 0:e9fd5575b10e 189 void (*p_cbfunc)(void); /**< SSIF error callback function (Invalid in GR_LYCHEE) */
anhtran 0:e9fd5575b10e 190 } ssif_chcfg_romdec_t;
anhtran 0:e9fd5575b10e 191
anhtran 0:e9fd5575b10e 192 /** This structure contains the configuration settings */
anhtran 0:e9fd5575b10e 193 typedef struct
anhtran 0:e9fd5575b10e 194 {
anhtran 0:e9fd5575b10e 195 bool enabled; /**< The enable flag for the channel */
anhtran 0:e9fd5575b10e 196 uint8_t int_level; /**< Interrupt priority for the channel */
anhtran 0:e9fd5575b10e 197 bool slave_mode; /**< Mode of operation */
anhtran 0:e9fd5575b10e 198 uint32_t sample_freq; /**< Audio Sampling frequency(Hz) */
anhtran 0:e9fd5575b10e 199 ssif_chcfg_cks_t clk_select; /**< SSICR-CKS : Audio clock select */
anhtran 0:e9fd5575b10e 200 ssif_chcfg_multi_ch_t multi_ch; /**< SSICR-CHNL: Audio channels per system word */
anhtran 0:e9fd5575b10e 201 ssif_chcfg_data_word_t data_word; /**< SSICR-DWL : Data word length */
anhtran 0:e9fd5575b10e 202 ssif_chcfg_system_word_t system_word; /**< SSICR-SWL : System word length */
anhtran 0:e9fd5575b10e 203 ssif_chcfg_clock_pol_t bclk_pol; /**< SSICR-SCKP: Bit Clock polarity */
anhtran 0:e9fd5575b10e 204 ssif_chcfg_ws_pol_t ws_pol; /**< SSICR-SWSP: Word Clock polarity */
anhtran 0:e9fd5575b10e 205 ssif_chcfg_padding_pol_t padding_pol; /**< SSICR-SPDP: Padding polarity */
anhtran 0:e9fd5575b10e 206 ssif_chcfg_serial_alignment_t serial_alignment; /**< SSICR-SDTA: Serial data alignment */
anhtran 0:e9fd5575b10e 207 ssif_chcfg_parallel_alignment_t parallel_alignment; /**< SSICR-PDTA: Parallel data alignment */
anhtran 0:e9fd5575b10e 208 ssif_chcfg_ws_delay_t ws_delay; /**< SSICR-DEL : Serial clock delay */
anhtran 0:e9fd5575b10e 209 ssif_chcfg_noise_cancel_t noise_cancel; /**< GPIO-SNCR : Noise cancel */
anhtran 0:e9fd5575b10e 210 ssif_chcfg_tdm_t tdm_mode; /**< SSITDMR-TDM: TDM mode */
anhtran 0:e9fd5575b10e 211 ssif_chcfg_romdec_t romdec_direct; /**< DMA : SSIRDR->STRMDIN0 route settings (Invalid in GR_LYCHEE) */
anhtran 0:e9fd5575b10e 212 } ssif_channel_cfg_t;
anhtran 0:e9fd5575b10e 213
anhtran 0:e9fd5575b10e 214 /******************************************************************************
anhtran 0:e9fd5575b10e 215 IOCTLS
anhtran 0:e9fd5575b10e 216 *****************************************************************************/
anhtran 0:e9fd5575b10e 217
anhtran 0:e9fd5575b10e 218 #define SSIF_CONFIG_CHANNEL (7)
anhtran 0:e9fd5575b10e 219 #define SSIF_GET_STATUS (13)
anhtran 0:e9fd5575b10e 220
anhtran 0:e9fd5575b10e 221 #ifdef __cplusplus
anhtran 0:e9fd5575b10e 222 }
anhtran 0:e9fd5575b10e 223 #endif /* __cplusplus */
anhtran 0:e9fd5575b10e 224
anhtran 0:e9fd5575b10e 225 #endif /* R_BSP_SSIF_DEF_H */