Anh Tran / Mbed OS GR-Boards_WebCamera

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mbed-gr-libs/DeepStandby/TARGET_RZ_A1XX/DeepStandby.cpp@0:e9fd5575b10e, 2019-10-18 (annotated)

Committer:
anhtran
Date:
Fri Oct 18 03:09:43 2019 +0000
Revision:
0:e9fd5575b10e
abc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
anhtran 0:e9fd5575b10e 1 /**********************************************************************************************************************
anhtran 0:e9fd5575b10e 2 * DISCLAIMER
anhtran 0:e9fd5575b10e 3 * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
anhtran 0:e9fd5575b10e 4 * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
anhtran 0:e9fd5575b10e 5 * applicable laws, including copyright laws.
anhtran 0:e9fd5575b10e 6 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
anhtran 0:e9fd5575b10e 7 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
anhtran 0:e9fd5575b10e 8 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
anhtran 0:e9fd5575b10e 9 * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
anhtran 0:e9fd5575b10e 10 * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
anhtran 0:e9fd5575b10e 11 * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
anhtran 0:e9fd5575b10e 12 * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
anhtran 0:e9fd5575b10e 13 * this software. By using this software, you agree to the additional terms and conditions found by accessing the
anhtran 0:e9fd5575b10e 14 * following link:
anhtran 0:e9fd5575b10e 15 * http://www.renesas.com/disclaimer
anhtran 0:e9fd5575b10e 16 *
anhtran 0:e9fd5575b10e 17 * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
anhtran 0:e9fd5575b10e 18 *********************************************************************************************************************/
anhtran 0:e9fd5575b10e 19
anhtran 0:e9fd5575b10e 20 #include "DeepStandby.h"
anhtran 0:e9fd5575b10e 21 #include "cpg_iobitmask.h"
anhtran 0:e9fd5575b10e 22
anhtran 0:e9fd5575b10e 23 #if defined(TARGET_RZ_A1H)
anhtran 0:e9fd5575b10e 24 #define CANCEL_SRC_BIT_BUTTON0 (0) // Not supported (P6_0)
anhtran 0:e9fd5575b10e 25 #define CANCEL_SRC_BIT_BUTTON1 (0) // Not supported
anhtran 0:e9fd5575b10e 26 #elif defined(TARGET_GR_LYCHEE)
anhtran 0:e9fd5575b10e 27 #define CANCEL_SRC_BIT_BUTTON0 (1 << 9) // P7_2
anhtran 0:e9fd5575b10e 28 #define CANCEL_SRC_BIT_BUTTON1 (1 << 4) // P7_3
anhtran 0:e9fd5575b10e 29 #else
anhtran 0:e9fd5575b10e 30 #warning "This board is not supported."
anhtran 0:e9fd5575b10e 31 #define CANCEL_SRC_BIT_BUTTON0 (0) // Not supported
anhtran 0:e9fd5575b10e 32 #define CANCEL_SRC_BIT_BUTTON1 (0) // Not supported
anhtran 0:e9fd5575b10e 33 #endif
anhtran 0:e9fd5575b10e 34 #define CANCEL_SRC_BIT_RTC (1 << 6) // RTCAR
anhtran 0:e9fd5575b10e 35
anhtran 0:e9fd5575b10e 36 void DeepStandby::SetDeepStandbySimple(cancel_src_simple_t *src)
anhtran 0:e9fd5575b10e 37 {
anhtran 0:e9fd5575b10e 38 cancel_src_direct_t src_direct;
anhtran 0:e9fd5575b10e 39
anhtran 0:e9fd5575b10e 40 if (src == NULL) {
anhtran 0:e9fd5575b10e 41 return;
anhtran 0:e9fd5575b10e 42 }
anhtran 0:e9fd5575b10e 43
anhtran 0:e9fd5575b10e 44 src_direct.rramkp = 0x0E; // RRAMKP1, RRAMKP2, RRAMKP3
anhtran 0:e9fd5575b10e 45 src_direct.dsssr = 0x0000;
anhtran 0:e9fd5575b10e 46 src_direct.dsesr = 0x0000;
anhtran 0:e9fd5575b10e 47 src_direct.usbdsssr = 0x0000;
anhtran 0:e9fd5575b10e 48
anhtran 0:e9fd5575b10e 49 if (src->button0) {
anhtran 0:e9fd5575b10e 50 src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON0;
anhtran 0:e9fd5575b10e 51 }
anhtran 0:e9fd5575b10e 52 if (src->button1) {
anhtran 0:e9fd5575b10e 53 src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON1;
anhtran 0:e9fd5575b10e 54 }
anhtran 0:e9fd5575b10e 55 if (src->rtc) {
anhtran 0:e9fd5575b10e 56 src_direct.dsssr |= CANCEL_SRC_BIT_RTC;
anhtran 0:e9fd5575b10e 57 }
anhtran 0:e9fd5575b10e 58
anhtran 0:e9fd5575b10e 59 SetDeepStandbyDirect(&src_direct);
anhtran 0:e9fd5575b10e 60 }
anhtran 0:e9fd5575b10e 61
anhtran 0:e9fd5575b10e 62
anhtran 0:e9fd5575b10e 63 void DeepStandby::SetDeepStandbyDirect(cancel_src_direct_t *src)
anhtran 0:e9fd5575b10e 64 {
anhtran 0:e9fd5575b10e 65 volatile uint32_t dummy_32;
anhtran 0:e9fd5575b10e 66 volatile uint16_t dummy_16;
anhtran 0:e9fd5575b10e 67 volatile uint8_t dummy_8;
anhtran 0:e9fd5575b10e 68
anhtran 0:e9fd5575b10e 69 if (src == NULL) {
anhtran 0:e9fd5575b10e 70 return;
anhtran 0:e9fd5575b10e 71 }
anhtran 0:e9fd5575b10e 72
anhtran 0:e9fd5575b10e 73 // 1. Set the standby_mode_en bit of the power control register in the PL310 to 1.
anhtran 0:e9fd5575b10e 74 L2C.REG15_POWER_CTRL = 0x00000001uL;
anhtran 0:e9fd5575b10e 75 dummy_32 = L2C.REG15_POWER_CTRL;
anhtran 0:e9fd5575b10e 76
anhtran 0:e9fd5575b10e 77 // 2. Set the RRAMKP3 to RRAMKP0 bits in RRAMKP for the corresponding on-chip data-retention RAM area
anhtran 0:e9fd5575b10e 78 // that must be retained. Transfer the programs to be retained to the specified areas of the on-chip
anhtran 0:e9fd5575b10e 79 // data-retention RAM.
anhtran 0:e9fd5575b10e 80 CPG.RRAMKP = src->rramkp;
anhtran 0:e9fd5575b10e 81 dummy_8 = CPG.RRAMKP;
anhtran 0:e9fd5575b10e 82
anhtran 0:e9fd5575b10e 83 // 3. Set the RAMBOOT and EBUSKEEPE bits in DSCTR to specify the activation method for returning from
anhtran 0:e9fd5575b10e 84 // deep standby mode and to select whether the external memory control pin status is retained or not.
anhtran 0:e9fd5575b10e 85 CPG.DSCTR = 0; // Activation Method : External memory
anhtran 0:e9fd5575b10e 86 dummy_8 = CPG.DSCTR;
anhtran 0:e9fd5575b10e 87
anhtran 0:e9fd5575b10e 88 // 4. When canceling deep standby mode by an interrupt, set the corresponding bit in DSSSR to select
anhtran 0:e9fd5575b10e 89 // the pin or source to cancel deep standby mode. In this case, specify the input signal detection
anhtran 0:e9fd5575b10e 90 // mode for the selected pin with the corresponding bit in DSESR.
anhtran 0:e9fd5575b10e 91 CPG.DSSSR = src->dsssr;
anhtran 0:e9fd5575b10e 92 dummy_16 = CPG.DSSSR;
anhtran 0:e9fd5575b10e 93 CPG.DSESR = src->dsesr;
anhtran 0:e9fd5575b10e 94 dummy_16 = CPG.DSESR;
anhtran 0:e9fd5575b10e 95
anhtran 0:e9fd5575b10e 96 // 5. Execute read and write of an arbitrary but the same address for each page in the on-chip data-
anhtran 0:e9fd5575b10e 97 // retention RAM area. When this is not executed, data last written may not be written to the on-chip
anhtran 0:e9fd5575b10e 98 // data-retention RAM. If there is a write to the on-chip data-retention RAM after this time, execute
anhtran 0:e9fd5575b10e 99 // this processing after the last write to the on-chip dataretention RAM.
anhtran 0:e9fd5575b10e 100 L1C_CleanInvalidateDCacheAll(); // Clean and invalidate the whole data cache.
anhtran 0:e9fd5575b10e 101
anhtran 0:e9fd5575b10e 102 // On-Chip Data Retention RAM Page 1 of bank 0
anhtran 0:e9fd5575b10e 103 dummy_32 = *((uint32_t *)0x20004000); // Read
anhtran 0:e9fd5575b10e 104 *((uint32_t *)0x20004000) = dummy_32; // Write
anhtran 0:e9fd5575b10e 105
anhtran 0:e9fd5575b10e 106 // On-Chip Data Retention RAM Page 2 of bank 0
anhtran 0:e9fd5575b10e 107 dummy_32 = *((uint32_t *)0x20008000); // Read
anhtran 0:e9fd5575b10e 108 *((uint32_t *)0x20008000) = dummy_32; // Write
anhtran 0:e9fd5575b10e 109
anhtran 0:e9fd5575b10e 110 // On-Chip Data Retention RAM Page 3 of bank 0
anhtran 0:e9fd5575b10e 111 dummy_32 = *((uint32_t *)0x20010000); // Read
anhtran 0:e9fd5575b10e 112 *((uint32_t *)0x20010000) = dummy_32; // Write
anhtran 0:e9fd5575b10e 113
anhtran 0:e9fd5575b10e 114 L1C_CleanDCacheAll(); // Clean the whole data cache.
anhtran 0:e9fd5575b10e 115
anhtran 0:e9fd5575b10e 116 // 6. Set the STBY and DEEP bits in the STBCR1 register to 1, and then read this register.
anhtran 0:e9fd5575b10e 117 CPG.STBCR1 = CPG_STBCR1_DEEP | CPG_STBCR1_STBY; // deep standby mode
anhtran 0:e9fd5575b10e 118 dummy_8 = CPG.STBCR1;
anhtran 0:e9fd5575b10e 119
anhtran 0:e9fd5575b10e 120 // 7. Clear the flag in the DSFR register.
anhtran 0:e9fd5575b10e 121 dummy_16 = CPG.DSFR;
anhtran 0:e9fd5575b10e 122 CPG.DSFR = 0;
anhtran 0:e9fd5575b10e 123 dummy_16 = CPG.DSFR;
anhtran 0:e9fd5575b10e 124
anhtran 0:e9fd5575b10e 125 // 8. Set the CPU interface control register (ICCICR) of the interrupt controller to 0 so that the CPU
anhtran 0:e9fd5575b10e 126 // is not notified of interrupts other than NMIs. Then, read the ICCICR register.
anhtran 0:e9fd5575b10e 127 INTC.ICCICR = 0;
anhtran 0:e9fd5575b10e 128 dummy_32 = INTC.ICCICR;
anhtran 0:e9fd5575b10e 129
anhtran 0:e9fd5575b10e 130 // Compiler warning measures
anhtran 0:e9fd5575b10e 131 (void)dummy_32;
anhtran 0:e9fd5575b10e 132 (void)dummy_16;
anhtran 0:e9fd5575b10e 133 (void)dummy_8;
anhtran 0:e9fd5575b10e 134
anhtran 0:e9fd5575b10e 135 // Execute the WFI instruction
anhtran 0:e9fd5575b10e 136 while (1) {
anhtran 0:e9fd5575b10e 137 __WFI();
anhtran 0:e9fd5575b10e 138 }
anhtran 0:e9fd5575b10e 139 }
anhtran 0:e9fd5575b10e 140
anhtran 0:e9fd5575b10e 141 bool DeepStandby::GetCancelSourceSimple(cancel_src_simple_t *src)
anhtran 0:e9fd5575b10e 142 {
anhtran 0:e9fd5575b10e 143 volatile uint16_t dsfr = CPG.DSFR;
anhtran 0:e9fd5575b10e 144
anhtran 0:e9fd5575b10e 145 if (dsfr == 0x0000) {
anhtran 0:e9fd5575b10e 146 return false;
anhtran 0:e9fd5575b10e 147 }
anhtran 0:e9fd5575b10e 148
anhtran 0:e9fd5575b10e 149 if (src != NULL) {
anhtran 0:e9fd5575b10e 150 if (dsfr & CANCEL_SRC_BIT_BUTTON0) {
anhtran 0:e9fd5575b10e 151 src->button0 = true;
anhtran 0:e9fd5575b10e 152 } else {
anhtran 0:e9fd5575b10e 153 src->button0 = false;
anhtran 0:e9fd5575b10e 154 }
anhtran 0:e9fd5575b10e 155 if (dsfr & CANCEL_SRC_BIT_BUTTON1) {
anhtran 0:e9fd5575b10e 156 src->button1 = true;
anhtran 0:e9fd5575b10e 157 } else {
anhtran 0:e9fd5575b10e 158 src->button1 = false;
anhtran 0:e9fd5575b10e 159 }
anhtran 0:e9fd5575b10e 160 if (dsfr & CANCEL_SRC_BIT_RTC) {
anhtran 0:e9fd5575b10e 161 src->rtc = true;
anhtran 0:e9fd5575b10e 162 } else {
anhtran 0:e9fd5575b10e 163 src->rtc = false;
anhtran 0:e9fd5575b10e 164 }
anhtran 0:e9fd5575b10e 165 }
anhtran 0:e9fd5575b10e 166
anhtran 0:e9fd5575b10e 167 return true;
anhtran 0:e9fd5575b10e 168 }
anhtran 0:e9fd5575b10e 169
anhtran 0:e9fd5575b10e 170 bool DeepStandby::GetCancelSourceDirect(uint16_t *dsfr, uint8_t *usbdsfr)
anhtran 0:e9fd5575b10e 171 {
anhtran 0:e9fd5575b10e 172 volatile uint16_t wk_dsfr = CPG.DSFR;
anhtran 0:e9fd5575b10e 173
anhtran 0:e9fd5575b10e 174 if (wk_dsfr == 0x0000) {
anhtran 0:e9fd5575b10e 175 return false;
anhtran 0:e9fd5575b10e 176 }
anhtran 0:e9fd5575b10e 177
anhtran 0:e9fd5575b10e 178 if (dsfr != NULL) {
anhtran 0:e9fd5575b10e 179 *dsfr = wk_dsfr;
anhtran 0:e9fd5575b10e 180 }
anhtran 0:e9fd5575b10e 181
anhtran 0:e9fd5575b10e 182 if (usbdsfr != NULL) {
anhtran 0:e9fd5575b10e 183 *usbdsfr = 0x00;
anhtran 0:e9fd5575b10e 184 }
anhtran 0:e9fd5575b10e 185
anhtran 0:e9fd5575b10e 186 return true;
anhtran 0:e9fd5575b10e 187 }
anhtran 0:e9fd5575b10e 188