Anh Tran / Mbed OS GR-Boards_WebCamera

test public

Dependencies:   HttpServer_snapshot_mbed-os

mbed-gr-libs/GR-PEACH_video/DisplayBase.cpp@0:e9fd5575b10e, 2019-10-18 (annotated)

Committer:
anhtran
Date:
Fri Oct 18 03:09:43 2019 +0000
Revision:
0:e9fd5575b10e
abc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
anhtran 0:e9fd5575b10e 1 /*******************************************************************************
anhtran 0:e9fd5575b10e 2 * DISCLAIMER
anhtran 0:e9fd5575b10e 3 * This software is supplied by Renesas Electronics Corporation and is only
anhtran 0:e9fd5575b10e 4 * intended for use with Renesas products. No other uses are authorized. This
anhtran 0:e9fd5575b10e 5 * software is owned by Renesas Electronics Corporation and is protected under
anhtran 0:e9fd5575b10e 6 * all applicable laws, including copyright laws.
anhtran 0:e9fd5575b10e 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
anhtran 0:e9fd5575b10e 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
anhtran 0:e9fd5575b10e 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
anhtran 0:e9fd5575b10e 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
anhtran 0:e9fd5575b10e 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
anhtran 0:e9fd5575b10e 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
anhtran 0:e9fd5575b10e 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
anhtran 0:e9fd5575b10e 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
anhtran 0:e9fd5575b10e 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
anhtran 0:e9fd5575b10e 16 * Renesas reserves the right, without notice, to make changes to this software
anhtran 0:e9fd5575b10e 17 * and to discontinue the availability of this software. By using this software,
anhtran 0:e9fd5575b10e 18 * you agree to the additional terms and conditions found by accessing the
anhtran 0:e9fd5575b10e 19 * following link:
anhtran 0:e9fd5575b10e 20 * http://www.renesas.com/disclaimer
anhtran 0:e9fd5575b10e 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
anhtran 0:e9fd5575b10e 22 *******************************************************************************/
anhtran 0:e9fd5575b10e 23 #include <string.h>
anhtran 0:e9fd5575b10e 24 #include "DisplayBace.h"
anhtran 0:e9fd5575b10e 25 #include "gr_board_vdc5.h"
anhtran 0:e9fd5575b10e 26
anhtran 0:e9fd5575b10e 27 /**************************************************************************//**
anhtran 0:e9fd5575b10e 28 * @brief Constructor of the DisplayBase class
anhtran 0:e9fd5575b10e 29 * @param[in] None
anhtran 0:e9fd5575b10e 30 * @retval None
anhtran 0:e9fd5575b10e 31 ******************************************************************************/
anhtran 0:e9fd5575b10e 32 DisplayBase::DisplayBase( void )
anhtran 0:e9fd5575b10e 33 {
anhtran 0:e9fd5575b10e 34 /* Lcd setting (default) */
anhtran 0:e9fd5575b10e 35 _lcd_config.lcd_type = LCD_TYPE_PARALLEL_RGB; /* LVDS or Pararel RGB */
anhtran 0:e9fd5575b10e 36 _lcd_config.intputClock = 66.67f; /* P1 clk [MHz] ex. 66.67 */
anhtran 0:e9fd5575b10e 37 _lcd_config.outputClock = 40.00f; /* LCD clk [MHz] ex. 33.33 */
anhtran 0:e9fd5575b10e 38
anhtran 0:e9fd5575b10e 39 _lcd_config.lcd_outformat = LCD_OUTFORMAT_RGB888; /* Output format select */
anhtran 0:e9fd5575b10e 40 _lcd_config.lcd_edge = EDGE_FALLING; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
anhtran 0:e9fd5575b10e 41
anhtran 0:e9fd5575b10e 42 _lcd_config.h_toatal_period = (800u + 40u + 128u+ 88u); /* Free-running Hsync period */
anhtran 0:e9fd5575b10e 43 _lcd_config.v_toatal_period = (600u + 1u + 4u + 23u); /* Free-running Vsync period */
anhtran 0:e9fd5575b10e 44 _lcd_config.h_disp_widht = 800u; /* LCD display area size, horizontal width */
anhtran 0:e9fd5575b10e 45 _lcd_config.v_disp_widht = 600u; /* LCD display area size, vertical width */
anhtran 0:e9fd5575b10e 46 _lcd_config.h_back_porch = (128u+ 88u); /* LCD display horizontal back porch period */
anhtran 0:e9fd5575b10e 47 _lcd_config.v_back_porch = (4u + 23u); /* LCD display vertical back porch period */
anhtran 0:e9fd5575b10e 48
anhtran 0:e9fd5575b10e 49 _lcd_config.h_sync_port = LCD_TCON_PIN_0; /* TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 50 _lcd_config.h_sync_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 51 _lcd_config.h_sync_width = 128u; /* Hsync width */
anhtran 0:e9fd5575b10e 52
anhtran 0:e9fd5575b10e 53 _lcd_config.v_sync_port = LCD_TCON_PIN_1; /* TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 54 _lcd_config.v_sync_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 55 _lcd_config.v_sync_width = 4u; /* Vsync width */
anhtran 0:e9fd5575b10e 56
anhtran 0:e9fd5575b10e 57 _lcd_config.de_port = LCD_TCON_PIN_NON; /* TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 58 _lcd_config.de_port_polarity = SIG_POL_NOT_INVERTED; /* Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 59
anhtran 0:e9fd5575b10e 60 /* Digital video input setting (default) */
anhtran 0:e9fd5575b10e 61 _video_input_sel = INPUT_SEL_VDEC; /* Video decoder output signals */
anhtran 0:e9fd5575b10e 62 _video_ext_in_config.inp_format = VIDEO_EXTIN_FORMAT_BT601;
anhtran 0:e9fd5575b10e 63 _video_ext_in_config.inp_pxd_edge = EDGE_RISING; /* Clock edge select for capturing data */
anhtran 0:e9fd5575b10e 64 _video_ext_in_config.inp_vs_edge = EDGE_RISING; /* Clock edge select for capturing Vsync signals */
anhtran 0:e9fd5575b10e 65 _video_ext_in_config.inp_hs_edge = EDGE_RISING; /* Clock edge select for capturing Hsync signals */
anhtran 0:e9fd5575b10e 66 _video_ext_in_config.inp_endian_on = OFF; /* External input bit endian change on/off */
anhtran 0:e9fd5575b10e 67 _video_ext_in_config.inp_swap_on = OFF; /* External input B/R signal swap on/off */
anhtran 0:e9fd5575b10e 68 _video_ext_in_config.inp_vs_inv = SIG_POL_NOT_INVERTED; /* External input DV_VSYNC inversion control */
anhtran 0:e9fd5575b10e 69 _video_ext_in_config.inp_hs_inv = SIG_POL_INVERTED; /* External input DV_HSYNC inversion control */
anhtran 0:e9fd5575b10e 70 _video_ext_in_config.inp_f525_625 = EXTIN_LINE_525; /* Number of lines for BT.656 external input */
anhtran 0:e9fd5575b10e 71 _video_ext_in_config.inp_h_pos = EXTIN_H_POS_CRYCBY; /* Y/Cb/Y/Cr data string start timing to Hsync reference */
anhtran 0:e9fd5575b10e 72 _video_ext_in_config.cap_vs_pos = 6u; /* Capture start position from Vsync */
anhtran 0:e9fd5575b10e 73 _video_ext_in_config.cap_hs_pos = 302u; /* Capture start position form Hsync */
anhtran 0:e9fd5575b10e 74 _video_ext_in_config.cap_width = 640u; /* Capture width */
anhtran 0:e9fd5575b10e 75 _video_ext_in_config.cap_height = 468u; /* Capture height should be a multiple of 4 */
anhtran 0:e9fd5575b10e 76
anhtran 0:e9fd5575b10e 77 #if defined(TARGET_RZ_A2XX)
anhtran 0:e9fd5575b10e 78 /* mipi */
anhtran 0:e9fd5575b10e 79 _video_mipi_config.mipi_lanenum = 2;
anhtran 0:e9fd5575b10e 80 _video_mipi_config.mipi_vc = 0;
anhtran 0:e9fd5575b10e 81 _video_mipi_config.mipi_interlace = 0;
anhtran 0:e9fd5575b10e 82 _video_mipi_config.mipi_laneswap = 0; /* Progressive */
anhtran 0:e9fd5575b10e 83 _video_mipi_config.mipi_frametop = 0;
anhtran 0:e9fd5575b10e 84 _video_mipi_config.mipi_outputrate = 80;
anhtran 0:e9fd5575b10e 85
anhtran 0:e9fd5575b10e 86 _video_mipi_config.mipi_phy_timing.mipi_ths_prepare = 0x00000012u;
anhtran 0:e9fd5575b10e 87 _video_mipi_config.mipi_phy_timing.mipi_ths_settle = 0x00000019u;
anhtran 0:e9fd5575b10e 88 _video_mipi_config.mipi_phy_timing.mipi_tclk_prepare = 0x0000000Fu;
anhtran 0:e9fd5575b10e 89 _video_mipi_config.mipi_phy_timing.mipi_tclk_settle = 0x0000001Eu;
anhtran 0:e9fd5575b10e 90 _video_mipi_config.mipi_phy_timing.mipi_tclk_miss = 0x00000008u;
anhtran 0:e9fd5575b10e 91 _video_mipi_config.mipi_phy_timing.mipi_t_init_slave = 0x0000338Fu;
anhtran 0:e9fd5575b10e 92
anhtran 0:e9fd5575b10e 93 memset(&_video_vin_setup, 0, sizeof(_video_vin_setup));
anhtran 0:e9fd5575b10e 94 #endif
anhtran 0:e9fd5575b10e 95 } /* End of constructor method () */
anhtran 0:e9fd5575b10e 96
anhtran 0:e9fd5575b10e 97 /**************************************************************************//**
anhtran 0:e9fd5575b10e 98 * @brief Graphics initialization processing
anhtran 0:e9fd5575b10e 99 * @param[in] lcd_config : LCD configuration
anhtran 0:e9fd5575b10e 100 * @retval error code
anhtran 0:e9fd5575b10e 101 ******************************************************************************/
anhtran 0:e9fd5575b10e 102 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 103 DisplayBase::Graphics_init( const lcd_config_t * lcd_config )
anhtran 0:e9fd5575b10e 104 {
anhtran 0:e9fd5575b10e 105 if( lcd_config != NULL ) {
anhtran 0:e9fd5575b10e 106 _lcd_config.lcd_type = lcd_config->lcd_type; /* LVDS or Pararel RGB */
anhtran 0:e9fd5575b10e 107 _lcd_config.intputClock = lcd_config->intputClock; /* P1 clk [MHz] ex. 66.67 */
anhtran 0:e9fd5575b10e 108 _lcd_config.outputClock = lcd_config->outputClock; /* LCD clk [MHz] ex. 33.33 */
anhtran 0:e9fd5575b10e 109
anhtran 0:e9fd5575b10e 110 _lcd_config.lcd_outformat = lcd_config->lcd_outformat; /* Output format select */
anhtran 0:e9fd5575b10e 111 _lcd_config.lcd_edge = lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
anhtran 0:e9fd5575b10e 112
anhtran 0:e9fd5575b10e 113 _lcd_config.h_toatal_period = lcd_config->h_toatal_period; /* Free-running Hsync period */
anhtran 0:e9fd5575b10e 114 _lcd_config.v_toatal_period = lcd_config->v_toatal_period; /* Free-running Vsync period */
anhtran 0:e9fd5575b10e 115 _lcd_config.h_disp_widht = lcd_config->h_disp_widht; /* LCD display area size, horizontal width */
anhtran 0:e9fd5575b10e 116 _lcd_config.v_disp_widht = lcd_config->v_disp_widht; /* LCD display area size, vertical width */
anhtran 0:e9fd5575b10e 117 _lcd_config.h_back_porch = lcd_config->h_back_porch; /* LCD display horizontal back porch period */
anhtran 0:e9fd5575b10e 118 _lcd_config.v_back_porch = lcd_config->v_back_porch; /* LCD display vertical back porch period */
anhtran 0:e9fd5575b10e 119
anhtran 0:e9fd5575b10e 120 _lcd_config.h_sync_port = lcd_config->h_sync_port; /* TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 121 _lcd_config.h_sync_port_polarity = lcd_config->h_sync_port_polarity;/* Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 122 _lcd_config.h_sync_width = lcd_config->h_sync_width; /* Hsync width */
anhtran 0:e9fd5575b10e 123
anhtran 0:e9fd5575b10e 124 _lcd_config.v_sync_port = lcd_config->v_sync_port; /* TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 125 _lcd_config.v_sync_port_polarity = lcd_config->v_sync_port_polarity;/* Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 126 _lcd_config.v_sync_width = lcd_config->v_sync_width; /* Vsync width */
anhtran 0:e9fd5575b10e 127
anhtran 0:e9fd5575b10e 128 _lcd_config.de_port = lcd_config->de_port; /* TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 129 _lcd_config.de_port_polarity = lcd_config->de_port_polarity; /* Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 130 }
anhtran 0:e9fd5575b10e 131
anhtran 0:e9fd5575b10e 132 return (graphics_error_t)DRV_Graphics_Init( (drv_lcd_config_t *)&_lcd_config );
anhtran 0:e9fd5575b10e 133 } /* End of method Graphics_init() */
anhtran 0:e9fd5575b10e 134
anhtran 0:e9fd5575b10e 135 /**************************************************************************//**
anhtran 0:e9fd5575b10e 136 * @brief Graphics Video initialization processing
anhtran 0:e9fd5575b10e 137 * @param[in] video_input_sel : Input select
anhtran 0:e9fd5575b10e 138 * @param[in] video_ext_in_config : Digtal video input configuration
anhtran 0:e9fd5575b10e 139 * @retval error code
anhtran 0:e9fd5575b10e 140 ******************************************************************************/
anhtran 0:e9fd5575b10e 141 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 142 DisplayBase::Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config )
anhtran 0:e9fd5575b10e 143 {
anhtran 0:e9fd5575b10e 144 graphics_error_t error;
anhtran 0:e9fd5575b10e 145
anhtran 0:e9fd5575b10e 146 if ((video_input_sel == INPUT_SEL_EXT)
anhtran 0:e9fd5575b10e 147 || (video_input_sel == INPUT_SEL_CEU)) {
anhtran 0:e9fd5575b10e 148 _video_input_sel = video_input_sel;
anhtran 0:e9fd5575b10e 149
anhtran 0:e9fd5575b10e 150 if (video_ext_in_config != NULL) {
anhtran 0:e9fd5575b10e 151 /* Signals supplied via the external input pins */
anhtran 0:e9fd5575b10e 152 /* if using Video decoder output signals, not using value. */
anhtran 0:e9fd5575b10e 153 _video_ext_in_config.inp_format = video_ext_in_config->inp_format;
anhtran 0:e9fd5575b10e 154 _video_ext_in_config.inp_pxd_edge = video_ext_in_config->inp_pxd_edge;
anhtran 0:e9fd5575b10e 155 _video_ext_in_config.inp_vs_edge = video_ext_in_config->inp_vs_edge;
anhtran 0:e9fd5575b10e 156 _video_ext_in_config.inp_hs_edge = video_ext_in_config->inp_hs_edge;
anhtran 0:e9fd5575b10e 157 _video_ext_in_config.inp_endian_on = video_ext_in_config->inp_endian_on;
anhtran 0:e9fd5575b10e 158 _video_ext_in_config.inp_swap_on = video_ext_in_config->inp_swap_on;
anhtran 0:e9fd5575b10e 159 _video_ext_in_config.inp_vs_inv = video_ext_in_config->inp_vs_inv;
anhtran 0:e9fd5575b10e 160 _video_ext_in_config.inp_hs_inv = video_ext_in_config->inp_hs_inv;
anhtran 0:e9fd5575b10e 161 _video_ext_in_config.inp_f525_625 = video_ext_in_config->inp_f525_625;
anhtran 0:e9fd5575b10e 162 _video_ext_in_config.inp_h_pos = video_ext_in_config->inp_h_pos;
anhtran 0:e9fd5575b10e 163 _video_ext_in_config.cap_vs_pos = video_ext_in_config->cap_vs_pos;
anhtran 0:e9fd5575b10e 164 _video_ext_in_config.cap_hs_pos = video_ext_in_config->cap_hs_pos;
anhtran 0:e9fd5575b10e 165 _video_ext_in_config.cap_width = video_ext_in_config->cap_width;
anhtran 0:e9fd5575b10e 166 _video_ext_in_config.cap_height = video_ext_in_config->cap_height;
anhtran 0:e9fd5575b10e 167 }
anhtran 0:e9fd5575b10e 168 error = (graphics_error_t)DRV_Graphics_Video_init( (drv_video_input_sel_t)video_input_sel,
anhtran 0:e9fd5575b10e 169 (drv_video_ext_in_config_t *)&_video_ext_in_config );
anhtran 0:e9fd5575b10e 170 } else {
anhtran 0:e9fd5575b10e 171 error = GRAPHICS_PARAM_RANGE_ERR;
anhtran 0:e9fd5575b10e 172 }
anhtran 0:e9fd5575b10e 173
anhtran 0:e9fd5575b10e 174 return error;
anhtran 0:e9fd5575b10e 175 } /* End of method Graphics_Video_init() */
anhtran 0:e9fd5575b10e 176
anhtran 0:e9fd5575b10e 177 /**************************************************************************//**
anhtran 0:e9fd5575b10e 178 * @brief Graphics Video initialization processing
anhtran 0:e9fd5575b10e 179 * @param[in] video_input_sel : Input select
anhtran 0:e9fd5575b10e 180 * @param[in] video_mipi_config : MIPI configuration
anhtran 0:e9fd5575b10e 181 * @param[in] video_vin_setup : MIPI configuration
anhtran 0:e9fd5575b10e 182 * @retval error code
anhtran 0:e9fd5575b10e 183 ******************************************************************************/
anhtran 0:e9fd5575b10e 184 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 185 DisplayBase::Graphics_Video_init( video_input_sel_t video_input_sel, video_mipi_param_t * video_mipi_config, video_vin_setup_t * video_vin_setup )
anhtran 0:e9fd5575b10e 186 {
anhtran 0:e9fd5575b10e 187 graphics_error_t error = GRAPHICS_VDC5_ERR;
anhtran 0:e9fd5575b10e 188
anhtran 0:e9fd5575b10e 189 #if defined(TARGET_RZ_A2XX)
anhtran 0:e9fd5575b10e 190 if (video_input_sel == INPUT_SEL_MIPI) {
anhtran 0:e9fd5575b10e 191 _video_input_sel = video_input_sel;
anhtran 0:e9fd5575b10e 192
anhtran 0:e9fd5575b10e 193 if (video_mipi_config != NULL) {
anhtran 0:e9fd5575b10e 194 memcpy(&_video_mipi_config, video_mipi_config, sizeof(_video_mipi_config));
anhtran 0:e9fd5575b10e 195 }
anhtran 0:e9fd5575b10e 196 if (video_vin_setup != NULL) {
anhtran 0:e9fd5575b10e 197 memcpy(&_video_vin_setup, video_vin_setup, sizeof(_video_vin_setup));
anhtran 0:e9fd5575b10e 198 }
anhtran 0:e9fd5575b10e 199 error = (graphics_error_t)DRV_Graphics_Video_init( (drv_video_input_sel_t)video_input_sel,
anhtran 0:e9fd5575b10e 200 (drv_video_ext_in_config_t *)&_video_ext_in_config );
anhtran 0:e9fd5575b10e 201 } else {
anhtran 0:e9fd5575b10e 202 error = GRAPHICS_PARAM_RANGE_ERR;
anhtran 0:e9fd5575b10e 203 }
anhtran 0:e9fd5575b10e 204 #endif
anhtran 0:e9fd5575b10e 205
anhtran 0:e9fd5575b10e 206 return error;
anhtran 0:e9fd5575b10e 207 } /* End of method Graphics_Video_init() */
anhtran 0:e9fd5575b10e 208
anhtran 0:e9fd5575b10e 209 /**************************************************************************//**
anhtran 0:e9fd5575b10e 210 * @brief LCD I/O initialization processing
anhtran 0:e9fd5575b10e 211 * @param[in] pin : Pointer of the pin assignment
anhtran 0:e9fd5575b10e 212 * @param[in] pin_count : Total number of the pin assignment
anhtran 0:e9fd5575b10e 213 * @retval error code
anhtran 0:e9fd5575b10e 214 ******************************************************************************/
anhtran 0:e9fd5575b10e 215 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 216 DisplayBase::Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count )
anhtran 0:e9fd5575b10e 217 {
anhtran 0:e9fd5575b10e 218 return (graphics_error_t)DRV_Graphics_Lcd_Port_Init( pin, pin_count );
anhtran 0:e9fd5575b10e 219 } /* End of method Graphics_Lcd_Port_Init() */
anhtran 0:e9fd5575b10e 220
anhtran 0:e9fd5575b10e 221 /**************************************************************************//**
anhtran 0:e9fd5575b10e 222 * @brief LVDS I/O port initialization processing
anhtran 0:e9fd5575b10e 223 * @param[in] pin : Pointer of the pin assignment
anhtran 0:e9fd5575b10e 224 * @param[in] pin_count : Total number of the pin assignment
anhtran 0:e9fd5575b10e 225 * @retval error code
anhtran 0:e9fd5575b10e 226 ******************************************************************************/
anhtran 0:e9fd5575b10e 227 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 228 DisplayBase::Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count )
anhtran 0:e9fd5575b10e 229 {
anhtran 0:e9fd5575b10e 230 return (graphics_error_t)DRV_Graphics_Lvds_Port_Init( pin, pin_count );
anhtran 0:e9fd5575b10e 231 } /* End of method Graphics_Lvds_Port_Init() */
anhtran 0:e9fd5575b10e 232
anhtran 0:e9fd5575b10e 233 /**************************************************************************//**
anhtran 0:e9fd5575b10e 234 * @brief Digital video input I/O port initialization processing
anhtran 0:e9fd5575b10e 235 * @param[in] pin : Pointer of the pin assignment
anhtran 0:e9fd5575b10e 236 * @param[in] pin_count : Total number of the pin assignment
anhtran 0:e9fd5575b10e 237 * @retval error code
anhtran 0:e9fd5575b10e 238 ******************************************************************************/
anhtran 0:e9fd5575b10e 239 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 240 DisplayBase::Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count )
anhtran 0:e9fd5575b10e 241 {
anhtran 0:e9fd5575b10e 242 return (graphics_error_t)DRV_Graphics_Dvinput_Port_Init( pin, pin_count );
anhtran 0:e9fd5575b10e 243 } /* End of method Graphics_Dvinput_Port_Init() */
anhtran 0:e9fd5575b10e 244
anhtran 0:e9fd5575b10e 245 /**************************************************************************//**
anhtran 0:e9fd5575b10e 246 * @brief CEU input I/O port initialization processing
anhtran 0:e9fd5575b10e 247 * @param[in] pin : Pointer of the pin assignment
anhtran 0:e9fd5575b10e 248 * @param[in] pin_count : Total number of the pin assignment
anhtran 0:e9fd5575b10e 249 * @retval error code
anhtran 0:e9fd5575b10e 250 ******************************************************************************/
anhtran 0:e9fd5575b10e 251 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 252 DisplayBase::Graphics_Ceu_Port_Init( PinName *pin, unsigned int pin_count )
anhtran 0:e9fd5575b10e 253 {
anhtran 0:e9fd5575b10e 254 return (graphics_error_t)DRV_Graphics_CEU_Port_Init( pin, pin_count );
anhtran 0:e9fd5575b10e 255 } /* End of method Graphics_Ceu_Port_Init() */
anhtran 0:e9fd5575b10e 256
anhtran 0:e9fd5575b10e 257 /**************************************************************************//**
anhtran 0:e9fd5575b10e 258 * @brief IRQ interrupt handler setting
anhtran 0:e9fd5575b10e 259 * @param[in] irq : VDC5 interrupt type
anhtran 0:e9fd5575b10e 260 * @param[in] num : Interrupt line number
anhtran 0:e9fd5575b10e 261 * @param[in] * callback : Interrupt callback function pointer
anhtran 0:e9fd5575b10e 262 * @retval error code
anhtran 0:e9fd5575b10e 263 ******************************************************************************/
anhtran 0:e9fd5575b10e 264 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 265 DisplayBase::Graphics_Irq_Handler_Set( int_type_t irq, unsigned short num, void (* callback)(int_type_t) )
anhtran 0:e9fd5575b10e 266 {
anhtran 0:e9fd5575b10e 267 return (graphics_error_t)DRV_Graphics_Irq_Handler_Set( (vdc5_int_type_t)irq, num, (void (*)(vdc5_int_type_t))callback );
anhtran 0:e9fd5575b10e 268 } /* End of method Graphics_Irq_Handler_Set() */
anhtran 0:e9fd5575b10e 269
anhtran 0:e9fd5575b10e 270 /**************************************************************************//**
anhtran 0:e9fd5575b10e 271 * @brief Graphics surface read start processing
anhtran 0:e9fd5575b10e 272 * @param[in] layer_id : Graphics layer ID
anhtran 0:e9fd5575b10e 273 * @retval error code
anhtran 0:e9fd5575b10e 274 ******************************************************************************/
anhtran 0:e9fd5575b10e 275 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 276 DisplayBase::Graphics_Start( graphics_layer_t layer_id )
anhtran 0:e9fd5575b10e 277 {
anhtran 0:e9fd5575b10e 278 return (graphics_error_t)DRV_Graphics_Start( (drv_graphics_layer_t)layer_id );
anhtran 0:e9fd5575b10e 279 } /* End of method Graphics_Start() */
anhtran 0:e9fd5575b10e 280
anhtran 0:e9fd5575b10e 281 /**************************************************************************//**
anhtran 0:e9fd5575b10e 282 * @brief Graphics surface read stop processing
anhtran 0:e9fd5575b10e 283 * @param[in] layer_id : Graphics layer ID
anhtran 0:e9fd5575b10e 284 * @retval error code
anhtran 0:e9fd5575b10e 285 ******************************************************************************/
anhtran 0:e9fd5575b10e 286 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 287 DisplayBase::Graphics_Stop( graphics_layer_t layer_id )
anhtran 0:e9fd5575b10e 288 {
anhtran 0:e9fd5575b10e 289 return (graphics_error_t)DRV_Graphics_Stop( (drv_graphics_layer_t)layer_id );
anhtran 0:e9fd5575b10e 290 } /* End of method Graphics_Stop() */
anhtran 0:e9fd5575b10e 291
anhtran 0:e9fd5575b10e 292 /**************************************************************************//**
anhtran 0:e9fd5575b10e 293 * @brief Video surface write start processing
anhtran 0:e9fd5575b10e 294 * @param[in] video_input_channel : Video input channel
anhtran 0:e9fd5575b10e 295 * @retval error code
anhtran 0:e9fd5575b10e 296 ******************************************************************************/
anhtran 0:e9fd5575b10e 297 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 298 DisplayBase::Video_Start( video_input_channel_t video_input_channel )
anhtran 0:e9fd5575b10e 299 {
anhtran 0:e9fd5575b10e 300 graphics_error_t error = GRAPHICS_OK;
anhtran 0:e9fd5575b10e 301
anhtran 0:e9fd5575b10e 302 /* Digital video inputs : supporting video_input_channel 0 only. */
anhtran 0:e9fd5575b10e 303 if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
anhtran 0:e9fd5575b10e 304 error = GRAPHICS_PARAM_RANGE_ERR;
anhtran 0:e9fd5575b10e 305 }
anhtran 0:e9fd5575b10e 306
anhtran 0:e9fd5575b10e 307 if( error == GRAPHICS_OK ) {
anhtran 0:e9fd5575b10e 308 error = (graphics_error_t)DRV_Video_Start( (drv_video_input_channel_t)video_input_channel );
anhtran 0:e9fd5575b10e 309 }
anhtran 0:e9fd5575b10e 310 return error;
anhtran 0:e9fd5575b10e 311 } /* End of method Video_Start() */
anhtran 0:e9fd5575b10e 312
anhtran 0:e9fd5575b10e 313 /**************************************************************************//**
anhtran 0:e9fd5575b10e 314 * @brief Video surface write stop processing
anhtran 0:e9fd5575b10e 315 * @param[in] video_input_channel : Video input channel
anhtran 0:e9fd5575b10e 316 * @retval error code
anhtran 0:e9fd5575b10e 317 ******************************************************************************/
anhtran 0:e9fd5575b10e 318 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 319 DisplayBase::Video_Stop( video_input_channel_t video_input_channel )
anhtran 0:e9fd5575b10e 320 {
anhtran 0:e9fd5575b10e 321 graphics_error_t error = GRAPHICS_OK;
anhtran 0:e9fd5575b10e 322
anhtran 0:e9fd5575b10e 323 /* Digital video inputs : supporting video_input_channel 0 only. */
anhtran 0:e9fd5575b10e 324 if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
anhtran 0:e9fd5575b10e 325 error = GRAPHICS_PARAM_RANGE_ERR;
anhtran 0:e9fd5575b10e 326 }
anhtran 0:e9fd5575b10e 327
anhtran 0:e9fd5575b10e 328 if( error == GRAPHICS_OK ) {
anhtran 0:e9fd5575b10e 329 error = (graphics_error_t)DRV_Video_Stop(
anhtran 0:e9fd5575b10e 330 (drv_video_input_channel_t)video_input_channel );
anhtran 0:e9fd5575b10e 331 }
anhtran 0:e9fd5575b10e 332 return error;
anhtran 0:e9fd5575b10e 333 } /* End of method Video_Stop() */
anhtran 0:e9fd5575b10e 334
anhtran 0:e9fd5575b10e 335 /**************************************************************************//**
anhtran 0:e9fd5575b10e 336 * @brief Graphics surface read process setting
anhtran 0:e9fd5575b10e 337 *
anhtran 0:e9fd5575b10e 338 * Description:<br>
anhtran 0:e9fd5575b10e 339 * This function supports the following 4 image format.
anhtran 0:e9fd5575b10e 340 * YCbCr422, RGB565, RGB888, ARGB8888
anhtran 0:e9fd5575b10e 341 * @param[in] layer_id : Graphics layer ID
anhtran 0:e9fd5575b10e 342 * @param[in] framebuff : Base address of the frame buffer
anhtran 0:e9fd5575b10e 343 * @param[in] fb_stride : Line offset address of the frame buffer
anhtran 0:e9fd5575b10e 344 * @param[in] gr_format : Format of the frame buffer read signal
anhtran 0:e9fd5575b10e 345 * @param[in] wr_rd_swa : frame buffer swap setting
anhtran 0:e9fd5575b10e 346 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
anhtran 0:e9fd5575b10e 347 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
anhtran 0:e9fd5575b10e 348 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
anhtran 0:e9fd5575b10e 349 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
anhtran 0:e9fd5575b10e 350 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
anhtran 0:e9fd5575b10e 351 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
anhtran 0:e9fd5575b10e 352 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
anhtran 0:e9fd5575b10e 353 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
anhtran 0:e9fd5575b10e 354 * @param[in] gr_rect : Graphics display area
anhtran 0:e9fd5575b10e 355 * @param[in] gr_clut : CLUT setup parameter
anhtran 0:e9fd5575b10e 356 * @retval Error code
anhtran 0:e9fd5575b10e 357 ******************************************************************************/
anhtran 0:e9fd5575b10e 358 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 359 DisplayBase::Graphics_Read_Setting(
anhtran 0:e9fd5575b10e 360 graphics_layer_t layer_id,
anhtran 0:e9fd5575b10e 361 void * framebuff,
anhtran 0:e9fd5575b10e 362 unsigned int fb_stride,
anhtran 0:e9fd5575b10e 363 graphics_format_t gr_format,
anhtran 0:e9fd5575b10e 364 wr_rd_swa_t wr_rd_swa,
anhtran 0:e9fd5575b10e 365 rect_t * gr_rect,
anhtran 0:e9fd5575b10e 366 clut_t * gr_clut )
anhtran 0:e9fd5575b10e 367 {
anhtran 0:e9fd5575b10e 368 rect_t rect;
anhtran 0:e9fd5575b10e 369
anhtran 0:e9fd5575b10e 370 rect.hs = gr_rect->hs + _lcd_config.h_back_porch;
anhtran 0:e9fd5575b10e 371 rect.vs = gr_rect->vs + _lcd_config.v_back_porch;
anhtran 0:e9fd5575b10e 372 rect.hw = gr_rect->hw;
anhtran 0:e9fd5575b10e 373 rect.vw = gr_rect->vw;
anhtran 0:e9fd5575b10e 374
anhtran 0:e9fd5575b10e 375 return (graphics_error_t)DRV_Graphics_Read_Setting(
anhtran 0:e9fd5575b10e 376 (drv_graphics_layer_t)layer_id,
anhtran 0:e9fd5575b10e 377 framebuff,
anhtran 0:e9fd5575b10e 378 fb_stride,
anhtran 0:e9fd5575b10e 379 (drv_graphics_format_t)gr_format,
anhtran 0:e9fd5575b10e 380 (drv_wr_rd_swa_t)wr_rd_swa,
anhtran 0:e9fd5575b10e 381 (drv_rect_t *)&rect,
anhtran 0:e9fd5575b10e 382 (drv_clut_t *)gr_clut);
anhtran 0:e9fd5575b10e 383 } /* End of method Graphics_Read_Setting() */
anhtran 0:e9fd5575b10e 384
anhtran 0:e9fd5575b10e 385 /**************************************************************************//**
anhtran 0:e9fd5575b10e 386 * @brief Graphics surface read process changing
anhtran 0:e9fd5575b10e 387 *
anhtran 0:e9fd5575b10e 388 * Description:<br>
anhtran 0:e9fd5575b10e 389 * This function is used to swap buffers.
anhtran 0:e9fd5575b10e 390 *
anhtran 0:e9fd5575b10e 391 * @param[in] layer_id : Graphics layer ID
anhtran 0:e9fd5575b10e 392 * @param[in] framebuff : Base address of the frame buffer
anhtran 0:e9fd5575b10e 393 * @retval Error code
anhtran 0:e9fd5575b10e 394 ******************************************************************************/
anhtran 0:e9fd5575b10e 395 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 396 DisplayBase::Graphics_Read_Change ( graphics_layer_t layer_id, void * framebuff)
anhtran 0:e9fd5575b10e 397 {
anhtran 0:e9fd5575b10e 398 return (graphics_error_t)DRV_Graphics_Read_Change(
anhtran 0:e9fd5575b10e 399 (drv_graphics_layer_t)layer_id, framebuff );
anhtran 0:e9fd5575b10e 400 } /* End of method Graphics_Read_Change() */
anhtran 0:e9fd5575b10e 401
anhtran 0:e9fd5575b10e 402 /**************************************************************************//**
anhtran 0:e9fd5575b10e 403 * @brief Video surface write process setting
anhtran 0:e9fd5575b10e 404 * This function set the video write process. Input form is weave
anhtran 0:e9fd5575b10e 405 * (progressive) mode fixed.
anhtran 0:e9fd5575b10e 406 * This function supports the following 3 image format.
anhtran 0:e9fd5575b10e 407 * YCbCr422, RGB565, RGB888
anhtran 0:e9fd5575b10e 408 * @param[in] video_input_ch : Video input channel
anhtran 0:e9fd5575b10e 409 * @param[in] col_sys : Analog video signal color system
anhtran 0:e9fd5575b10e 410 * @param[in] adc_vinsel : Video input pin
anhtran 0:e9fd5575b10e 411 * @param[in] framebuff : Base address of the frame buffer
anhtran 0:e9fd5575b10e 412 * @param[in] fb_stride [byte] : Line offset address of the frame buffer
anhtran 0:e9fd5575b10e 413 * @param[in] video_format : Frame buffer video-signal writing format
anhtran 0:e9fd5575b10e 414 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
anhtran 0:e9fd5575b10e 415 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
anhtran 0:e9fd5575b10e 416 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
anhtran 0:e9fd5575b10e 417 * @param[in] wr_rd_swa : frame buffer swap setting
anhtran 0:e9fd5575b10e 418 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
anhtran 0:e9fd5575b10e 419 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
anhtran 0:e9fd5575b10e 420 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
anhtran 0:e9fd5575b10e 421 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
anhtran 0:e9fd5575b10e 422 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
anhtran 0:e9fd5575b10e 423 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
anhtran 0:e9fd5575b10e 424 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
anhtran 0:e9fd5575b10e 425 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
anhtran 0:e9fd5575b10e 426 * @param[in] video_write_size_vw [px]: output v width
anhtran 0:e9fd5575b10e 427 * @param[in] video_write_size_hw [px]: output h width
anhtran 0:e9fd5575b10e 428 * @param[in] video_adc_vinsel : Input pin control
anhtran 0:e9fd5575b10e 429 * @retval Error code
anhtran 0:e9fd5575b10e 430 ******************************************************************************/
anhtran 0:e9fd5575b10e 431 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 432 DisplayBase::Video_Write_Setting(
anhtran 0:e9fd5575b10e 433 video_input_channel_t video_input_channel,
anhtran 0:e9fd5575b10e 434 graphics_video_col_sys_t col_sys,
anhtran 0:e9fd5575b10e 435 void * framebuff,
anhtran 0:e9fd5575b10e 436 unsigned int fb_stride,
anhtran 0:e9fd5575b10e 437 video_format_t video_format,
anhtran 0:e9fd5575b10e 438 wr_rd_swa_t wr_rd_swa,
anhtran 0:e9fd5575b10e 439 unsigned short write_buff_vw,
anhtran 0:e9fd5575b10e 440 unsigned short write_buff_hw,
anhtran 0:e9fd5575b10e 441 video_adc_vinsel_t video_adc_vinsel )
anhtran 0:e9fd5575b10e 442
anhtran 0:e9fd5575b10e 443 {
anhtran 0:e9fd5575b10e 444 graphics_error_t error = GRAPHICS_OK;
anhtran 0:e9fd5575b10e 445
anhtran 0:e9fd5575b10e 446 if( _video_input_sel == INPUT_SEL_VDEC ) {
anhtran 0:e9fd5575b10e 447 if( col_sys == COL_SYS_NTSC_358 || col_sys == COL_SYS_NTSC_443 || col_sys == COL_SYS_NTSC_443_60 ) {
anhtran 0:e9fd5575b10e 448 if( (write_buff_vw / 2u) > 240u ) {
anhtran 0:e9fd5575b10e 449 error = GRAPHICS_VIDEO_NTSC_SIZE_ERR;
anhtran 0:e9fd5575b10e 450 }
anhtran 0:e9fd5575b10e 451 } else {
anhtran 0:e9fd5575b10e 452 if( (write_buff_vw / 2u) > 280u ) {
anhtran 0:e9fd5575b10e 453 error = GRAPHICS_VIDEO_PAL_SIZE_ERR;
anhtran 0:e9fd5575b10e 454 }
anhtran 0:e9fd5575b10e 455 }
anhtran 0:e9fd5575b10e 456
anhtran 0:e9fd5575b10e 457 if( write_buff_hw > 800u ) {
anhtran 0:e9fd5575b10e 458 error = GRAPHICS_PARAM_RANGE_ERR;
anhtran 0:e9fd5575b10e 459 }
anhtran 0:e9fd5575b10e 460 if( error == GRAPHICS_OK ) {
anhtran 0:e9fd5575b10e 461 error = (graphics_error_t)DRV_Video_Write_Setting(
anhtran 0:e9fd5575b10e 462 (drv_video_input_channel_t)video_input_channel,
anhtran 0:e9fd5575b10e 463 (drv_graphics_video_col_sys_t)col_sys,
anhtran 0:e9fd5575b10e 464 framebuff,
anhtran 0:e9fd5575b10e 465 fb_stride,
anhtran 0:e9fd5575b10e 466 (drv_video_format_t)video_format,
anhtran 0:e9fd5575b10e 467 (drv_wr_rd_swa_t)wr_rd_swa,
anhtran 0:e9fd5575b10e 468 write_buff_vw,
anhtran 0:e9fd5575b10e 469 write_buff_hw,
anhtran 0:e9fd5575b10e 470 (drv_video_adc_vinsel_t)video_adc_vinsel);
anhtran 0:e9fd5575b10e 471 }
anhtran 0:e9fd5575b10e 472 } else if( _video_input_sel == INPUT_SEL_EXT ) {
anhtran 0:e9fd5575b10e 473 rect_t cap_area;
anhtran 0:e9fd5575b10e 474
anhtran 0:e9fd5575b10e 475 cap_area.hs = _video_ext_in_config.cap_hs_pos * 2;
anhtran 0:e9fd5575b10e 476 cap_area.hw = _video_ext_in_config.cap_width * 2;
anhtran 0:e9fd5575b10e 477 cap_area.vs = _video_ext_in_config.cap_vs_pos;
anhtran 0:e9fd5575b10e 478 cap_area.vw = _video_ext_in_config.cap_height;
anhtran 0:e9fd5575b10e 479
anhtran 0:e9fd5575b10e 480 error = (graphics_error_t) DRV_Video_Write_Setting_Digital(
anhtran 0:e9fd5575b10e 481 framebuff,
anhtran 0:e9fd5575b10e 482 fb_stride,
anhtran 0:e9fd5575b10e 483 (drv_video_format_t)video_format,
anhtran 0:e9fd5575b10e 484 (drv_wr_rd_swa_t)wr_rd_swa,
anhtran 0:e9fd5575b10e 485 write_buff_vw,
anhtran 0:e9fd5575b10e 486 write_buff_hw,
anhtran 0:e9fd5575b10e 487 (drv_rect_t *)&cap_area );
anhtran 0:e9fd5575b10e 488 } else if( _video_input_sel == INPUT_SEL_CEU ) {
anhtran 0:e9fd5575b10e 489 error = (graphics_error_t) DRV_Video_Write_Setting_Ceu(
anhtran 0:e9fd5575b10e 490 framebuff,
anhtran 0:e9fd5575b10e 491 fb_stride,
anhtran 0:e9fd5575b10e 492 (drv_video_format_t)video_format,
anhtran 0:e9fd5575b10e 493 (drv_wr_rd_swa_t)wr_rd_swa,
anhtran 0:e9fd5575b10e 494 write_buff_vw,
anhtran 0:e9fd5575b10e 495 write_buff_hw,
anhtran 0:e9fd5575b10e 496 (drv_video_ext_in_config_t *)&_video_ext_in_config);
anhtran 0:e9fd5575b10e 497 #if defined(TARGET_RZ_A2XX)
anhtran 0:e9fd5575b10e 498 } else if( _video_input_sel == INPUT_SEL_MIPI ) {
anhtran 0:e9fd5575b10e 499 error = (graphics_error_t) DRV_Video_Write_Setting_Mipi(
anhtran 0:e9fd5575b10e 500 framebuff,
anhtran 0:e9fd5575b10e 501 fb_stride,
anhtran 0:e9fd5575b10e 502 (drv_video_format_t)video_format,
anhtran 0:e9fd5575b10e 503 (drv_wr_rd_swa_t)wr_rd_swa,
anhtran 0:e9fd5575b10e 504 write_buff_vw,
anhtran 0:e9fd5575b10e 505 write_buff_hw,
anhtran 0:e9fd5575b10e 506 (drv_mipi_param_t *)&_video_mipi_config,
anhtran 0:e9fd5575b10e 507 (drv_vin_setup_t *)&_video_vin_setup);
anhtran 0:e9fd5575b10e 508 #endif
anhtran 0:e9fd5575b10e 509 } else {
anhtran 0:e9fd5575b10e 510 error = GRAPHICS_PARAM_RANGE_ERR;
anhtran 0:e9fd5575b10e 511 }
anhtran 0:e9fd5575b10e 512 return error;
anhtran 0:e9fd5575b10e 513 } /* End of method Video_Write_Setting() */
anhtran 0:e9fd5575b10e 514
anhtran 0:e9fd5575b10e 515 /**************************************************************************//**
anhtran 0:e9fd5575b10e 516 * @brief Graphics surface write process changing
anhtran 0:e9fd5575b10e 517 * This function is used to swap buffers of the weave write processing.
anhtran 0:e9fd5575b10e 518 * @param[in] video_input_ch : Video input channle
anhtran 0:e9fd5575b10e 519 * @param[in] framebuff : Base address of the frame buffer
anhtran 0:e9fd5575b10e 520 * @param[in] fb_stride : Line offset address of the frame buffer
anhtran 0:e9fd5575b10e 521 * @retval Error code
anhtran 0:e9fd5575b10e 522 ******************************************************************************/
anhtran 0:e9fd5575b10e 523 DisplayBase::graphics_error_t
anhtran 0:e9fd5575b10e 524 DisplayBase::Video_Write_Change (
anhtran 0:e9fd5575b10e 525 video_input_channel_t video_input_channel, void * framebuff, uint32_t fb_stride )
anhtran 0:e9fd5575b10e 526 {
anhtran 0:e9fd5575b10e 527 return (graphics_error_t)DRV_Video_Write_Change(
anhtran 0:e9fd5575b10e 528 (drv_video_input_channel_t)video_input_channel, framebuff, fb_stride );
anhtran 0:e9fd5575b10e 529 } /* End of method Video_Write_Change() */
anhtran 0:e9fd5575b10e 530
anhtran 0:e9fd5575b10e 531 /* End of file */