Anh Tran / Mbed OS GR-Boards_WebCamera

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Dependencies:   HttpServer_snapshot_mbed-os

mbed-gr-libs/DeepStandby/TARGET_RZ_A2XX/DeepStandby.cpp@0:e9fd5575b10e, 2019-10-18 (annotated)

Committer:
anhtran
Date:
Fri Oct 18 03:09:43 2019 +0000
Revision:
0:e9fd5575b10e
abc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
anhtran 0:e9fd5575b10e 1 /**********************************************************************************************************************
anhtran 0:e9fd5575b10e 2 * DISCLAIMER
anhtran 0:e9fd5575b10e 3 * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
anhtran 0:e9fd5575b10e 4 * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
anhtran 0:e9fd5575b10e 5 * applicable laws, including copyright laws.
anhtran 0:e9fd5575b10e 6 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
anhtran 0:e9fd5575b10e 7 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
anhtran 0:e9fd5575b10e 8 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
anhtran 0:e9fd5575b10e 9 * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
anhtran 0:e9fd5575b10e 10 * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
anhtran 0:e9fd5575b10e 11 * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
anhtran 0:e9fd5575b10e 12 * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
anhtran 0:e9fd5575b10e 13 * this software. By using this software, you agree to the additional terms and conditions found by accessing the
anhtran 0:e9fd5575b10e 14 * following link:
anhtran 0:e9fd5575b10e 15 * http://www.renesas.com/disclaimer
anhtran 0:e9fd5575b10e 16 *
anhtran 0:e9fd5575b10e 17 * Copyright (C) 2019 Renesas Electronics Corporation. All rights reserved.
anhtran 0:e9fd5575b10e 18 *********************************************************************************************************************/
anhtran 0:e9fd5575b10e 19
anhtran 0:e9fd5575b10e 20 #include "DeepStandby.h"
anhtran 0:e9fd5575b10e 21
anhtran 0:e9fd5575b10e 22 #if defined(TARGET_RZ_A2M_EVB) || defined(TARGET_RZ_A2M_EVB_HF)
anhtran 0:e9fd5575b10e 23 #define CANCEL_SRC_BIT_BUTTON0 (1 << 11) // PJ_1
anhtran 0:e9fd5575b10e 24 #define CANCEL_SRC_BIT_BUTTON1 (1 << 8) // NMI
anhtran 0:e9fd5575b10e 25 #elif defined(TARGET_RZ_A2M_SBEV)
anhtran 0:e9fd5575b10e 26 #define CANCEL_SRC_BIT_BUTTON0 (0) // Not supported (PC_5)
anhtran 0:e9fd5575b10e 27 #define CANCEL_SRC_BIT_BUTTON1 (1 << 8) // NMI
anhtran 0:e9fd5575b10e 28 #elif defined(TARGET_SEMB1402)
anhtran 0:e9fd5575b10e 29 #define CANCEL_SRC_BIT_BUTTON0 (1 << 3) // PE_1
anhtran 0:e9fd5575b10e 30 #define CANCEL_SRC_BIT_BUTTON1 (0) // Not supported (PE_0)
anhtran 0:e9fd5575b10e 31 #else
anhtran 0:e9fd5575b10e 32 #warning "This board is not supported."
anhtran 0:e9fd5575b10e 33 #define CANCEL_SRC_BIT_BUTTON0 (0) // Not supported
anhtran 0:e9fd5575b10e 34 #define CANCEL_SRC_BIT_BUTTON1 (0) // Not supported
anhtran 0:e9fd5575b10e 35 #endif
anhtran 0:e9fd5575b10e 36 #define CANCEL_SRC_BIT_RTC (1 << 7) // RTCAR1
anhtran 0:e9fd5575b10e 37
anhtran 0:e9fd5575b10e 38 void DeepStandby::SetDeepStandbySimple(cancel_src_simple_t *src)
anhtran 0:e9fd5575b10e 39 {
anhtran 0:e9fd5575b10e 40 cancel_src_direct_t src_direct;
anhtran 0:e9fd5575b10e 41
anhtran 0:e9fd5575b10e 42 if (src == NULL) {
anhtran 0:e9fd5575b10e 43 return;
anhtran 0:e9fd5575b10e 44 }
anhtran 0:e9fd5575b10e 45
anhtran 0:e9fd5575b10e 46 src_direct.rramkp = 0x0E; // RRAMKP1, RRAMKP2, RRAMKP3
anhtran 0:e9fd5575b10e 47 src_direct.dsssr = 0x0000;
anhtran 0:e9fd5575b10e 48 src_direct.dsesr = 0x0000;
anhtran 0:e9fd5575b10e 49 src_direct.usbdsssr = 0x0000;
anhtran 0:e9fd5575b10e 50
anhtran 0:e9fd5575b10e 51 if (src->button0) {
anhtran 0:e9fd5575b10e 52 src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON0;
anhtran 0:e9fd5575b10e 53 }
anhtran 0:e9fd5575b10e 54 if (src->button1) {
anhtran 0:e9fd5575b10e 55 src_direct.dsssr |= CANCEL_SRC_BIT_BUTTON1;
anhtran 0:e9fd5575b10e 56 }
anhtran 0:e9fd5575b10e 57 if (src->rtc) {
anhtran 0:e9fd5575b10e 58 src_direct.dsssr |= CANCEL_SRC_BIT_RTC;
anhtran 0:e9fd5575b10e 59 }
anhtran 0:e9fd5575b10e 60
anhtran 0:e9fd5575b10e 61 SetDeepStandbyDirect(&src_direct);
anhtran 0:e9fd5575b10e 62 }
anhtran 0:e9fd5575b10e 63
anhtran 0:e9fd5575b10e 64 void DeepStandby::SetDeepStandbyDirect(cancel_src_direct_t *src)
anhtran 0:e9fd5575b10e 65 {
anhtran 0:e9fd5575b10e 66 volatile uint32_t dummy_32;
anhtran 0:e9fd5575b10e 67 volatile uint16_t dummy_16;
anhtran 0:e9fd5575b10e 68 volatile uint8_t dummy_8;
anhtran 0:e9fd5575b10e 69
anhtran 0:e9fd5575b10e 70 if (src == NULL) {
anhtran 0:e9fd5575b10e 71 return;
anhtran 0:e9fd5575b10e 72 }
anhtran 0:e9fd5575b10e 73
anhtran 0:e9fd5575b10e 74 // 1. Set the standby_mode_en bit of the power control register in the PL310 to 1.
anhtran 0:e9fd5575b10e 75 pl310.REG15_POWER_CTRL.BIT.standby_mode_en = 1;
anhtran 0:e9fd5575b10e 76 dummy_32 = pl310.REG15_POWER_CTRL.LONG;
anhtran 0:e9fd5575b10e 77
anhtran 0:e9fd5575b10e 78 // 2. Set the RRAMKP3 to RRAMKP0 bits in RRAMKP for the corresponding on-chip data-retention RAM area
anhtran 0:e9fd5575b10e 79 // that must be retained. Transfer the programs to be retained to the specified areas of the on-chip
anhtran 0:e9fd5575b10e 80 // data-retention RAM.
anhtran 0:e9fd5575b10e 81 PMG.RRAMKP.BYTE = src->rramkp;
anhtran 0:e9fd5575b10e 82 dummy_8 = PMG.RRAMKP.BYTE;
anhtran 0:e9fd5575b10e 83
anhtran 0:e9fd5575b10e 84 // 3. Set the RAMBOOT and EBUSKEEPE bits in DSCTR to specify the activation method for returning from
anhtran 0:e9fd5575b10e 85 // deep standby mode and to select whether the external memory control pin status is retained or not.
anhtran 0:e9fd5575b10e 86
anhtran 0:e9fd5575b10e 87 // Activation Method : External memory
anhtran 0:e9fd5575b10e 88 PMG.DSCTR.BIT.RAMBOOT = 0;
anhtran 0:e9fd5575b10e 89 PMG.DSCTR.BIT.EBUSKEEPE = 0;
anhtran 0:e9fd5575b10e 90 dummy_8 = PMG.DSCTR.BYTE;
anhtran 0:e9fd5575b10e 91
anhtran 0:e9fd5575b10e 92 // 4. When canceling deep standby mode by an interrupt, set the corresponding bit in DSSSR to select
anhtran 0:e9fd5575b10e 93 // the pin or source to cancel deep standby mode. In this case, specify the input signal detection
anhtran 0:e9fd5575b10e 94 // mode for the selected pin with the corresponding bit in DSESR.
anhtran 0:e9fd5575b10e 95 PMG.DSSSR.WORD = src->dsssr;
anhtran 0:e9fd5575b10e 96 dummy_16 = PMG.DSSSR.WORD;
anhtran 0:e9fd5575b10e 97
anhtran 0:e9fd5575b10e 98 PMG.DSESR.WORD = src->dsesr;
anhtran 0:e9fd5575b10e 99 dummy_16 = PMG.DSESR.WORD;
anhtran 0:e9fd5575b10e 100
anhtran 0:e9fd5575b10e 101 PMG.USBDSSSR.BYTE = src->usbdsssr;
anhtran 0:e9fd5575b10e 102 dummy_8 = PMG.USBDSSSR.BYTE;
anhtran 0:e9fd5575b10e 103 PMG.DSCNT.BIT.CNTD = 0;
anhtran 0:e9fd5575b10e 104 dummy_16 = PMG.DSCNT.WORD;
anhtran 0:e9fd5575b10e 105
anhtran 0:e9fd5575b10e 106 // 5. Execute read and write of an arbitrary but the same address for each page in the on-chip data-
anhtran 0:e9fd5575b10e 107 // retention RAM area. When this is not executed, data last written may not be written to the on-chip
anhtran 0:e9fd5575b10e 108 // data-retention RAM. If there is a write to the on-chip data-retention RAM after this time, execute
anhtran 0:e9fd5575b10e 109 // this processing after the last write to the on-chip dataretention RAM.
anhtran 0:e9fd5575b10e 110 L1C_CleanInvalidateDCacheAll(); // Clean and invalidate the whole data cache.
anhtran 0:e9fd5575b10e 111
anhtran 0:e9fd5575b10e 112 // On-Chip Data Retention RAM Page 1
anhtran 0:e9fd5575b10e 113 dummy_32 = *((uint32_t *)0x80004000); // Read
anhtran 0:e9fd5575b10e 114 *((uint32_t *)0x80004000) = dummy_32; // Write
anhtran 0:e9fd5575b10e 115
anhtran 0:e9fd5575b10e 116 // On-Chip Data Retention RAM Page 2
anhtran 0:e9fd5575b10e 117 dummy_32 = *((uint32_t *)0x80008000); // Read
anhtran 0:e9fd5575b10e 118 *((uint32_t *)0x80008000) = dummy_32; // Write
anhtran 0:e9fd5575b10e 119
anhtran 0:e9fd5575b10e 120 // On-Chip Data Retention RAM Page 3
anhtran 0:e9fd5575b10e 121 dummy_32 = *((uint32_t *)0x80010000); // Read
anhtran 0:e9fd5575b10e 122 *((uint32_t *)0x80010000) = dummy_32; // Write
anhtran 0:e9fd5575b10e 123
anhtran 0:e9fd5575b10e 124 L1C_CleanDCacheAll(); // Clean the whole data cache.
anhtran 0:e9fd5575b10e 125
anhtran 0:e9fd5575b10e 126 // 6. Set the STBY and DEEP bits in the STBCR1 register to 1, and then read this register.
anhtran 0:e9fd5575b10e 127
anhtran 0:e9fd5575b10e 128 // deep standby mode
anhtran 0:e9fd5575b10e 129 CPG.STBCR1.BIT.DEEP = 1;
anhtran 0:e9fd5575b10e 130 CPG.STBCR1.BIT.STBY = 1;
anhtran 0:e9fd5575b10e 131 dummy_8 = CPG.STBCR1.BYTE;
anhtran 0:e9fd5575b10e 132
anhtran 0:e9fd5575b10e 133 // 7. Clear the flag in the DSFR register.
anhtran 0:e9fd5575b10e 134 dummy_16 = PMG.DSFR.WORD;
anhtran 0:e9fd5575b10e 135 PMG.DSFR.WORD = 0;
anhtran 0:e9fd5575b10e 136 dummy_16 = PMG.DSFR.WORD;
anhtran 0:e9fd5575b10e 137 dummy_8 = PMG.USBDSFR.BYTE;
anhtran 0:e9fd5575b10e 138 PMG.USBDSFR.BYTE = 0;
anhtran 0:e9fd5575b10e 139 dummy_8 = PMG.USBDSFR.BYTE;
anhtran 0:e9fd5575b10e 140
anhtran 0:e9fd5575b10e 141 // 8. Set the CPU interface control register (GICC_CTLR) of the interrupt controller to 0 so that the CPU
anhtran 0:e9fd5575b10e 142 // is not notified of interrupts other than NMIs. Then, read the GICC_CTLR register.
anhtran 0:e9fd5575b10e 143 INTC.GICC_CTLR.LONG = 0;
anhtran 0:e9fd5575b10e 144 dummy_32 = INTC.GICC_CTLR.LONG;
anhtran 0:e9fd5575b10e 145
anhtran 0:e9fd5575b10e 146 // Compiler warning measures
anhtran 0:e9fd5575b10e 147 (void)dummy_32;
anhtran 0:e9fd5575b10e 148 (void)dummy_16;
anhtran 0:e9fd5575b10e 149 (void)dummy_8;
anhtran 0:e9fd5575b10e 150
anhtran 0:e9fd5575b10e 151 // Execute the WFI instruction
anhtran 0:e9fd5575b10e 152 while (1) {
anhtran 0:e9fd5575b10e 153 __WFI();
anhtran 0:e9fd5575b10e 154 }
anhtran 0:e9fd5575b10e 155 }
anhtran 0:e9fd5575b10e 156
anhtran 0:e9fd5575b10e 157 bool DeepStandby::GetCancelSourceSimple(cancel_src_simple_t *src)
anhtran 0:e9fd5575b10e 158 {
anhtran 0:e9fd5575b10e 159 volatile uint16_t dsfr = PMG.DSFR.WORD;
anhtran 0:e9fd5575b10e 160
anhtran 0:e9fd5575b10e 161 if (dsfr == 0x0000) {
anhtran 0:e9fd5575b10e 162 return false;
anhtran 0:e9fd5575b10e 163 }
anhtran 0:e9fd5575b10e 164
anhtran 0:e9fd5575b10e 165 if (src != NULL) {
anhtran 0:e9fd5575b10e 166 if (dsfr & CANCEL_SRC_BIT_BUTTON0) {
anhtran 0:e9fd5575b10e 167 src->button0 = true;
anhtran 0:e9fd5575b10e 168 } else {
anhtran 0:e9fd5575b10e 169 src->button0 = false;
anhtran 0:e9fd5575b10e 170 }
anhtran 0:e9fd5575b10e 171 if (dsfr & CANCEL_SRC_BIT_BUTTON1) {
anhtran 0:e9fd5575b10e 172 src->button1 = true;
anhtran 0:e9fd5575b10e 173 } else {
anhtran 0:e9fd5575b10e 174 src->button1 = false;
anhtran 0:e9fd5575b10e 175 }
anhtran 0:e9fd5575b10e 176 if (dsfr & CANCEL_SRC_BIT_RTC) {
anhtran 0:e9fd5575b10e 177 src->rtc = true;
anhtran 0:e9fd5575b10e 178 } else {
anhtran 0:e9fd5575b10e 179 src->rtc = false;
anhtran 0:e9fd5575b10e 180 }
anhtran 0:e9fd5575b10e 181 }
anhtran 0:e9fd5575b10e 182
anhtran 0:e9fd5575b10e 183 return true;
anhtran 0:e9fd5575b10e 184 }
anhtran 0:e9fd5575b10e 185
anhtran 0:e9fd5575b10e 186 bool DeepStandby::GetCancelSourceDirect(uint16_t *dsfr, uint8_t *usbdsfr)
anhtran 0:e9fd5575b10e 187 {
anhtran 0:e9fd5575b10e 188 volatile uint16_t wk_dsfr = PMG.DSFR.WORD;
anhtran 0:e9fd5575b10e 189 volatile uint8_t wk_usbdsfr = PMG.USBDSFR.BYTE;
anhtran 0:e9fd5575b10e 190
anhtran 0:e9fd5575b10e 191 if ((wk_dsfr == 0x0000) && (wk_usbdsfr == 0x00)) {
anhtran 0:e9fd5575b10e 192 return false;
anhtran 0:e9fd5575b10e 193 }
anhtran 0:e9fd5575b10e 194
anhtran 0:e9fd5575b10e 195 if (dsfr != NULL) {
anhtran 0:e9fd5575b10e 196 *dsfr = wk_dsfr;
anhtran 0:e9fd5575b10e 197 }
anhtran 0:e9fd5575b10e 198
anhtran 0:e9fd5575b10e 199 if (usbdsfr != NULL) {
anhtran 0:e9fd5575b10e 200 *usbdsfr = wk_usbdsfr;
anhtran 0:e9fd5575b10e 201 }
anhtran 0:e9fd5575b10e 202
anhtran 0:e9fd5575b10e 203 return true;
anhtran 0:e9fd5575b10e 204 }
anhtran 0:e9fd5575b10e 205