Anh Tran / Mbed OS GR-Boards_WebCamera

test public

Dependencies:   HttpServer_snapshot_mbed-os

mbed-gr-libs/R_BSP/common/R_BSP_Scux.cpp@0:e9fd5575b10e, 2019-10-18 (annotated)

Committer:
anhtran
Date:
Fri Oct 18 03:09:43 2019 +0000
Revision:
0:e9fd5575b10e
abc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
anhtran 0:e9fd5575b10e 1 /*******************************************************************************
anhtran 0:e9fd5575b10e 2 * DISCLAIMER
anhtran 0:e9fd5575b10e 3 * This software is supplied by Renesas Electronics Corporation and is only
anhtran 0:e9fd5575b10e 4 * intended for use with Renesas products. No other uses are authorized. This
anhtran 0:e9fd5575b10e 5 * software is owned by Renesas Electronics Corporation and is protected under
anhtran 0:e9fd5575b10e 6 * all applicable laws, including copyright laws.
anhtran 0:e9fd5575b10e 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
anhtran 0:e9fd5575b10e 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
anhtran 0:e9fd5575b10e 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
anhtran 0:e9fd5575b10e 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
anhtran 0:e9fd5575b10e 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
anhtran 0:e9fd5575b10e 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
anhtran 0:e9fd5575b10e 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
anhtran 0:e9fd5575b10e 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
anhtran 0:e9fd5575b10e 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
anhtran 0:e9fd5575b10e 16 * Renesas reserves the right, without notice, to make changes to this software
anhtran 0:e9fd5575b10e 17 * and to discontinue the availability of this software. By using this software,
anhtran 0:e9fd5575b10e 18 * you agree to the additional terms and conditions found by accessing the
anhtran 0:e9fd5575b10e 19 * following link:
anhtran 0:e9fd5575b10e 20 * http://www.renesas.com/disclaimer*
anhtran 0:e9fd5575b10e 21 * Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
anhtran 0:e9fd5575b10e 22 *******************************************************************************/
anhtran 0:e9fd5575b10e 23
anhtran 0:e9fd5575b10e 24 #include "R_BSP_Scux.h"
anhtran 0:e9fd5575b10e 25 #if (R_BSP_SCUX_ENABLE == 1)
anhtran 0:e9fd5575b10e 26 #include "r_bsp_cmn.h"
anhtran 0:e9fd5575b10e 27 #include "scux_if.h"
anhtran 0:e9fd5575b10e 28
anhtran 0:e9fd5575b10e 29 #define CH_ERR_NUM (-1) /* Channel error number */
anhtran 0:e9fd5575b10e 30 #define INT_LEVEL_MAX (0xF7) /* The maximum value of the interrupt level */
anhtran 0:e9fd5575b10e 31 #define REQ_BUFF_NUM_MIN (1) /* The minimum value of the request buffer */
anhtran 0:e9fd5575b10e 32 #define REQ_BUFF_NUM_MAX (128) /* The maximum value of the request buffer */
anhtran 0:e9fd5575b10e 33 #define INPUT_DIV_INIT_VALUE (1000U) /* The initial value of input divide ratio */
anhtran 0:e9fd5575b10e 34 #define OUTPUT_DIV_INIT_VALUE (0U) /* The initial value of output divide ratio */
anhtran 0:e9fd5575b10e 35 #define INPUT_WS_INIT_VALUE (1U) /* The initial value of input WS frequency */
anhtran 0:e9fd5575b10e 36 #define OUTPUT_WS_INIT_VALUE (96000U) /* The initial value of output WS frequency */
anhtran 0:e9fd5575b10e 37 #define FREQ_TIOC3A_INIT_VALUE (1U) /* The initial value of frequency of TIOC3 */
anhtran 0:e9fd5575b10e 38 #define FREQ_TIOC4A_INIT_VALUE (1U) /* The initial value of frequency of TIOC4 */
anhtran 0:e9fd5575b10e 39 #define WAIT_SAMPLE_INIT_VALUE (0U) /* The initial value of wait time */
anhtran 0:e9fd5575b10e 40 #define MIN_RATE_PER_INIT_VALUE (98U) /* The initial value of minimum rate */
anhtran 0:e9fd5575b10e 41 #define DIV_RATIO_CLK_AUDIO_22050HZ (1024U) /* Divide ratio when the frequency is 22050Hz */
anhtran 0:e9fd5575b10e 42 #define DIV_RATIO_CLK_AUDIO_44100HZ (512U) /* Divide ratio when the frequency is 44100Hz */
anhtran 0:e9fd5575b10e 43 #define DIV_RATIO_CLK_AUDIO_88200HZ (256U) /* Divide ratio when the frequency is 88200Hz */
anhtran 0:e9fd5575b10e 44 #define DIV_RATIO_CLK_USB_24000HZ (2000U) /* Divide ratio when the frequency is 24000Hz */
anhtran 0:e9fd5575b10e 45 #define DIV_RATIO_CLK_USB_32000HZ (1500U) /* Divide ratio when the frequency is 36000Hz */
anhtran 0:e9fd5575b10e 46 #define DIV_RATIO_CLK_USB_48000HZ (1000U) /* Divide ratio when the frequency is 48000Hz */
anhtran 0:e9fd5575b10e 47 #define DIV_RATIO_CLK_USB_64000HZ (750U) /* Divide ratio when the frequency is 64000Hz */
anhtran 0:e9fd5575b10e 48 #define DIV_RATIO_CLK_USB_96000HZ (500U) /* Divide ratio when the frequency is 96000Hz */
anhtran 0:e9fd5575b10e 49
anhtran 0:e9fd5575b10e 50 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg);
anhtran 0:e9fd5575b10e 51
anhtran 0:e9fd5575b10e 52 R_BSP_Scux::R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
anhtran 0:e9fd5575b10e 53 scux_channel_cfg_t scux_cfg;
anhtran 0:e9fd5575b10e 54 int32_t result;
anhtran 0:e9fd5575b10e 55 bool init_result;
anhtran 0:e9fd5575b10e 56
anhtran 0:e9fd5575b10e 57 if (channel >= SCUX_CH_NUM) {
anhtran 0:e9fd5575b10e 58 result = EERROR;
anhtran 0:e9fd5575b10e 59 } else if (int_level > INT_LEVEL_MAX) {
anhtran 0:e9fd5575b10e 60 result = EERROR;
anhtran 0:e9fd5575b10e 61 } else if ((max_write_num < REQ_BUFF_NUM_MIN) || (max_write_num > REQ_BUFF_NUM_MAX)) {
anhtran 0:e9fd5575b10e 62 result = EERROR;
anhtran 0:e9fd5575b10e 63 } else if ((max_read_num < REQ_BUFF_NUM_MIN) || (max_read_num > REQ_BUFF_NUM_MAX)) {
anhtran 0:e9fd5575b10e 64 result = EERROR;
anhtran 0:e9fd5575b10e 65 } else {
anhtran 0:e9fd5575b10e 66 result = R_BSP_CMN_Init();
anhtran 0:e9fd5575b10e 67 if (result == ESUCCESS) {
anhtran 0:e9fd5575b10e 68 scux_ch = (int32_t)channel;
anhtran 0:e9fd5575b10e 69
anhtran 0:e9fd5575b10e 70 scux_cfg.enabled = true;
anhtran 0:e9fd5575b10e 71 scux_cfg.int_level = int_level;
anhtran 0:e9fd5575b10e 72
anhtran 0:e9fd5575b10e 73 switch (channel) {
anhtran 0:e9fd5575b10e 74 case SCUX_CH_0:
anhtran 0:e9fd5575b10e 75 scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
anhtran 0:e9fd5575b10e 76 break;
anhtran 0:e9fd5575b10e 77 case SCUX_CH_1:
anhtran 0:e9fd5575b10e 78 scux_cfg.route = SCUX_ROUTE_SRC1_MEM;
anhtran 0:e9fd5575b10e 79 break;
anhtran 0:e9fd5575b10e 80 case SCUX_CH_2:
anhtran 0:e9fd5575b10e 81 scux_cfg.route = SCUX_ROUTE_SRC2_MEM;
anhtran 0:e9fd5575b10e 82 break;
anhtran 0:e9fd5575b10e 83 case SCUX_CH_3:
anhtran 0:e9fd5575b10e 84 scux_cfg.route = SCUX_ROUTE_SRC3_MEM;
anhtran 0:e9fd5575b10e 85 break;
anhtran 0:e9fd5575b10e 86 default:
anhtran 0:e9fd5575b10e 87 /* NOTREACHED on At the time of a normal performance */
anhtran 0:e9fd5575b10e 88 scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
anhtran 0:e9fd5575b10e 89 break;
anhtran 0:e9fd5575b10e 90 }
anhtran 0:e9fd5575b10e 91
anhtran 0:e9fd5575b10e 92 init_result = set_src_init_cfg(&scux_cfg.src_cfg);
anhtran 0:e9fd5575b10e 93 if (init_result != false) {
anhtran 0:e9fd5575b10e 94 init_result = init_channel(R_SCUX_MakeCbTbl_mbed(), (int32_t)channel, &scux_cfg, max_write_num, max_read_num);
anhtran 0:e9fd5575b10e 95 if (init_result == false) {
anhtran 0:e9fd5575b10e 96 result = EERROR;
anhtran 0:e9fd5575b10e 97 }
anhtran 0:e9fd5575b10e 98 } else {
anhtran 0:e9fd5575b10e 99 result = EERROR;
anhtran 0:e9fd5575b10e 100 }
anhtran 0:e9fd5575b10e 101 }
anhtran 0:e9fd5575b10e 102 }
anhtran 0:e9fd5575b10e 103
anhtran 0:e9fd5575b10e 104 if (result != ESUCCESS) {
anhtran 0:e9fd5575b10e 105 scux_ch = CH_ERR_NUM;
anhtran 0:e9fd5575b10e 106 }
anhtran 0:e9fd5575b10e 107 }
anhtran 0:e9fd5575b10e 108
anhtran 0:e9fd5575b10e 109 R_BSP_Scux::~R_BSP_Scux(void) {
anhtran 0:e9fd5575b10e 110 }
anhtran 0:e9fd5575b10e 111
anhtran 0:e9fd5575b10e 112 bool R_BSP_Scux::TransStart(void) {
anhtran 0:e9fd5575b10e 113 return ioctl(SCUX_IOCTL_SET_START, NULL);
anhtran 0:e9fd5575b10e 114 }
anhtran 0:e9fd5575b10e 115
anhtran 0:e9fd5575b10e 116 bool R_BSP_Scux::FlushStop(void (* const callback)(int32_t)) {
anhtran 0:e9fd5575b10e 117 return ioctl(SCUX_IOCTL_SET_FLUSH_STOP, (void *)callback);
anhtran 0:e9fd5575b10e 118 }
anhtran 0:e9fd5575b10e 119
anhtran 0:e9fd5575b10e 120 bool R_BSP_Scux::ClearStop(void) {
anhtran 0:e9fd5575b10e 121 return ioctl(SCUX_IOCTL_SET_CLEAR_STOP, NULL);
anhtran 0:e9fd5575b10e 122 }
anhtran 0:e9fd5575b10e 123
anhtran 0:e9fd5575b10e 124 bool R_BSP_Scux::SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param) {
anhtran 0:e9fd5575b10e 125 scux_src_cfg_t src_cfg;
anhtran 0:e9fd5575b10e 126 bool init_result;
anhtran 0:e9fd5575b10e 127 bool ret = true;
anhtran 0:e9fd5575b10e 128 int32_t i;
anhtran 0:e9fd5575b10e 129
anhtran 0:e9fd5575b10e 130 if (scux_ch == CH_ERR_NUM) {
anhtran 0:e9fd5575b10e 131 ret = false;
anhtran 0:e9fd5575b10e 132 } else if (p_src_param == NULL) {
anhtran 0:e9fd5575b10e 133 ret = false;
anhtran 0:e9fd5575b10e 134 } else if ((p_src_param->mode_sync != false) && (p_src_param->src_enable == false)) {
anhtran 0:e9fd5575b10e 135 ret = false;
anhtran 0:e9fd5575b10e 136 } else {
anhtran 0:e9fd5575b10e 137 init_result = set_src_init_cfg(&src_cfg);
anhtran 0:e9fd5575b10e 138 if (init_result != true) {
anhtran 0:e9fd5575b10e 139 ret = false;
anhtran 0:e9fd5575b10e 140 } else {
anhtran 0:e9fd5575b10e 141 src_cfg.src_enable = p_src_param->src_enable;
anhtran 0:e9fd5575b10e 142 src_cfg.mode_sync = p_src_param->mode_sync;
anhtran 0:e9fd5575b10e 143
anhtran 0:e9fd5575b10e 144 switch (p_src_param->word_len) {
anhtran 0:e9fd5575b10e 145 case SCUX_DATA_LEN_24:
anhtran 0:e9fd5575b10e 146 /* fall through */
anhtran 0:e9fd5575b10e 147 case SCUX_DATA_LEN_16:
anhtran 0:e9fd5575b10e 148 /* fall through */
anhtran 0:e9fd5575b10e 149 case SCUX_DATA_LEN_16_TO_24:
anhtran 0:e9fd5575b10e 150 src_cfg.word_len = p_src_param->word_len;
anhtran 0:e9fd5575b10e 151 break;
anhtran 0:e9fd5575b10e 152 default:
anhtran 0:e9fd5575b10e 153 ret = false;
anhtran 0:e9fd5575b10e 154 break;
anhtran 0:e9fd5575b10e 155 }
anhtran 0:e9fd5575b10e 156
anhtran 0:e9fd5575b10e 157 if (ret == true) {
anhtran 0:e9fd5575b10e 158 if (p_src_param->mode_sync != false) {
anhtran 0:e9fd5575b10e 159 switch (p_src_param->input_rate) {
anhtran 0:e9fd5575b10e 160 case SAMPLING_RATE_8000HZ:
anhtran 0:e9fd5575b10e 161 src_cfg.input_rate_sync = SCUX_SYNC_RATE_8;
anhtran 0:e9fd5575b10e 162 break;
anhtran 0:e9fd5575b10e 163 case SAMPLING_RATE_11025HZ:
anhtran 0:e9fd5575b10e 164 src_cfg.input_rate_sync = SCUX_SYNC_RATE_11_025;
anhtran 0:e9fd5575b10e 165 break;
anhtran 0:e9fd5575b10e 166 case SAMPLING_RATE_12000HZ:
anhtran 0:e9fd5575b10e 167 src_cfg.input_rate_sync = SCUX_SYNC_RATE_12;
anhtran 0:e9fd5575b10e 168 break;
anhtran 0:e9fd5575b10e 169 case SAMPLING_RATE_16000HZ:
anhtran 0:e9fd5575b10e 170 src_cfg.input_rate_sync = SCUX_SYNC_RATE_16;
anhtran 0:e9fd5575b10e 171 break;
anhtran 0:e9fd5575b10e 172 case SAMPLING_RATE_22050HZ:
anhtran 0:e9fd5575b10e 173 src_cfg.input_rate_sync = SCUX_SYNC_RATE_22_05;
anhtran 0:e9fd5575b10e 174 break;
anhtran 0:e9fd5575b10e 175 case SAMPLING_RATE_24000HZ:
anhtran 0:e9fd5575b10e 176 src_cfg.input_rate_sync = SCUX_SYNC_RATE_24;
anhtran 0:e9fd5575b10e 177 break;
anhtran 0:e9fd5575b10e 178 case SAMPLING_RATE_32000HZ:
anhtran 0:e9fd5575b10e 179 src_cfg.input_rate_sync = SCUX_SYNC_RATE_32;
anhtran 0:e9fd5575b10e 180 break;
anhtran 0:e9fd5575b10e 181 case SAMPLING_RATE_44100HZ:
anhtran 0:e9fd5575b10e 182 src_cfg.input_rate_sync = SCUX_SYNC_RATE_44_1;
anhtran 0:e9fd5575b10e 183 break;
anhtran 0:e9fd5575b10e 184 case SAMPLING_RATE_48000HZ:
anhtran 0:e9fd5575b10e 185 src_cfg.input_rate_sync = SCUX_SYNC_RATE_48;
anhtran 0:e9fd5575b10e 186 break;
anhtran 0:e9fd5575b10e 187 case SAMPLING_RATE_64000HZ:
anhtran 0:e9fd5575b10e 188 src_cfg.input_rate_sync = SCUX_SYNC_RATE_64;
anhtran 0:e9fd5575b10e 189 break;
anhtran 0:e9fd5575b10e 190 case SAMPLING_RATE_88200HZ:
anhtran 0:e9fd5575b10e 191 src_cfg.input_rate_sync = SCUX_SYNC_RATE_88_2;
anhtran 0:e9fd5575b10e 192 break;
anhtran 0:e9fd5575b10e 193 case SAMPLING_RATE_96000HZ:
anhtran 0:e9fd5575b10e 194 src_cfg.input_rate_sync = SCUX_SYNC_RATE_96;
anhtran 0:e9fd5575b10e 195 break;
anhtran 0:e9fd5575b10e 196 default:
anhtran 0:e9fd5575b10e 197 ret = false;
anhtran 0:e9fd5575b10e 198 break;
anhtran 0:e9fd5575b10e 199 }
anhtran 0:e9fd5575b10e 200 } else {
anhtran 0:e9fd5575b10e 201 switch (p_src_param->input_rate) {
anhtran 0:e9fd5575b10e 202 case SAMPLING_RATE_22050HZ:
anhtran 0:e9fd5575b10e 203 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
anhtran 0:e9fd5575b10e 204 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_22050HZ;
anhtran 0:e9fd5575b10e 205 break;
anhtran 0:e9fd5575b10e 206 case SAMPLING_RATE_24000HZ:
anhtran 0:e9fd5575b10e 207 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
anhtran 0:e9fd5575b10e 208 src_cfg.input_div_async = DIV_RATIO_CLK_USB_24000HZ;
anhtran 0:e9fd5575b10e 209 break;
anhtran 0:e9fd5575b10e 210 case SAMPLING_RATE_32000HZ:
anhtran 0:e9fd5575b10e 211 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
anhtran 0:e9fd5575b10e 212 src_cfg.input_div_async = DIV_RATIO_CLK_USB_32000HZ;
anhtran 0:e9fd5575b10e 213 break;
anhtran 0:e9fd5575b10e 214 case SAMPLING_RATE_44100HZ:
anhtran 0:e9fd5575b10e 215 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
anhtran 0:e9fd5575b10e 216 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_44100HZ;
anhtran 0:e9fd5575b10e 217 break;
anhtran 0:e9fd5575b10e 218 case SAMPLING_RATE_48000HZ:
anhtran 0:e9fd5575b10e 219 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
anhtran 0:e9fd5575b10e 220 src_cfg.input_div_async = DIV_RATIO_CLK_USB_48000HZ;
anhtran 0:e9fd5575b10e 221 break;
anhtran 0:e9fd5575b10e 222 case SAMPLING_RATE_64000HZ:
anhtran 0:e9fd5575b10e 223 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
anhtran 0:e9fd5575b10e 224 src_cfg.input_div_async = DIV_RATIO_CLK_USB_64000HZ;
anhtran 0:e9fd5575b10e 225 break;
anhtran 0:e9fd5575b10e 226 case SAMPLING_RATE_88200HZ:
anhtran 0:e9fd5575b10e 227 src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
anhtran 0:e9fd5575b10e 228 src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_88200HZ;
anhtran 0:e9fd5575b10e 229 break;
anhtran 0:e9fd5575b10e 230 case SAMPLING_RATE_96000HZ:
anhtran 0:e9fd5575b10e 231 src_cfg.input_clk_async = SCUX_CLK_USB_X1;
anhtran 0:e9fd5575b10e 232 src_cfg.input_div_async = DIV_RATIO_CLK_USB_96000HZ;
anhtran 0:e9fd5575b10e 233 break;
anhtran 0:e9fd5575b10e 234 default:
anhtran 0:e9fd5575b10e 235 ret = false;
anhtran 0:e9fd5575b10e 236 break;
anhtran 0:e9fd5575b10e 237 }
anhtran 0:e9fd5575b10e 238 }
anhtran 0:e9fd5575b10e 239 }
anhtran 0:e9fd5575b10e 240
anhtran 0:e9fd5575b10e 241 if (ret == true) {
anhtran 0:e9fd5575b10e 242 if (p_src_param->mode_sync != false) {
anhtran 0:e9fd5575b10e 243 switch (p_src_param->output_rate) {
anhtran 0:e9fd5575b10e 244 case SAMPLING_RATE_44100HZ:
anhtran 0:e9fd5575b10e 245 src_cfg.output_rate_sync = SCUX_SYNC_RATE_44_1;
anhtran 0:e9fd5575b10e 246 break;
anhtran 0:e9fd5575b10e 247 case SAMPLING_RATE_48000HZ:
anhtran 0:e9fd5575b10e 248 src_cfg.output_rate_sync = SCUX_SYNC_RATE_48;
anhtran 0:e9fd5575b10e 249 break;
anhtran 0:e9fd5575b10e 250 case SAMPLING_RATE_96000HZ:
anhtran 0:e9fd5575b10e 251 src_cfg.output_rate_sync = SCUX_SYNC_RATE_96;
anhtran 0:e9fd5575b10e 252 break;
anhtran 0:e9fd5575b10e 253 default:
anhtran 0:e9fd5575b10e 254 ret = false;
anhtran 0:e9fd5575b10e 255 break;
anhtran 0:e9fd5575b10e 256 }
anhtran 0:e9fd5575b10e 257 } else {
anhtran 0:e9fd5575b10e 258 switch (p_src_param->output_rate) {
anhtran 0:e9fd5575b10e 259 case SAMPLING_RATE_44100HZ:
anhtran 0:e9fd5575b10e 260 src_cfg.output_ws = SAMPLING_RATE_44100HZ;
anhtran 0:e9fd5575b10e 261 break;
anhtran 0:e9fd5575b10e 262 case SAMPLING_RATE_48000HZ:
anhtran 0:e9fd5575b10e 263 src_cfg.output_ws = SAMPLING_RATE_48000HZ;
anhtran 0:e9fd5575b10e 264 break;
anhtran 0:e9fd5575b10e 265 case SAMPLING_RATE_88200HZ:
anhtran 0:e9fd5575b10e 266 src_cfg.output_ws = SAMPLING_RATE_88200HZ;
anhtran 0:e9fd5575b10e 267 break;
anhtran 0:e9fd5575b10e 268 case SAMPLING_RATE_96000HZ:
anhtran 0:e9fd5575b10e 269 src_cfg.output_ws = SAMPLING_RATE_96000HZ;
anhtran 0:e9fd5575b10e 270 break;
anhtran 0:e9fd5575b10e 271 default:
anhtran 0:e9fd5575b10e 272 ret = false;
anhtran 0:e9fd5575b10e 273 break;
anhtran 0:e9fd5575b10e 274 }
anhtran 0:e9fd5575b10e 275 }
anhtran 0:e9fd5575b10e 276 }
anhtran 0:e9fd5575b10e 277
anhtran 0:e9fd5575b10e 278 if (ret == true) {
anhtran 0:e9fd5575b10e 279 for (i = 0; i < SCUX_USE_CH_2; i++) {
anhtran 0:e9fd5575b10e 280 switch (p_src_param->select_in_data_ch[i]) {
anhtran 0:e9fd5575b10e 281 case SELECT_IN_DATA_CH_0:
anhtran 0:e9fd5575b10e 282 src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_0;
anhtran 0:e9fd5575b10e 283 break;
anhtran 0:e9fd5575b10e 284 case SELECT_IN_DATA_CH_1:
anhtran 0:e9fd5575b10e 285 src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_1;
anhtran 0:e9fd5575b10e 286 break;
anhtran 0:e9fd5575b10e 287 default:
anhtran 0:e9fd5575b10e 288 ret = false;
anhtran 0:e9fd5575b10e 289 break;
anhtran 0:e9fd5575b10e 290 }
anhtran 0:e9fd5575b10e 291 }
anhtran 0:e9fd5575b10e 292 }
anhtran 0:e9fd5575b10e 293
anhtran 0:e9fd5575b10e 294 if (ret == true) {
anhtran 0:e9fd5575b10e 295 ret = ioctl(SCUX_IOCTL_SET_SRC_CFG, (void *)&src_cfg);
anhtran 0:e9fd5575b10e 296 }
anhtran 0:e9fd5575b10e 297 }
anhtran 0:e9fd5575b10e 298 }
anhtran 0:e9fd5575b10e 299
anhtran 0:e9fd5575b10e 300 return ret;
anhtran 0:e9fd5575b10e 301 }
anhtran 0:e9fd5575b10e 302
anhtran 0:e9fd5575b10e 303 bool R_BSP_Scux::GetWriteStat(uint32_t * const p_write_stat) {
anhtran 0:e9fd5575b10e 304 return ioctl(SCUX_IOCTL_GET_WRITE_STAT, (void *)p_write_stat);
anhtran 0:e9fd5575b10e 305 }
anhtran 0:e9fd5575b10e 306
anhtran 0:e9fd5575b10e 307 bool R_BSP_Scux::GetReadStat(uint32_t * const p_read_stat) {
anhtran 0:e9fd5575b10e 308 return ioctl(SCUX_IOCTL_GET_READ_STAT, (void *)p_read_stat);
anhtran 0:e9fd5575b10e 309 }
anhtran 0:e9fd5575b10e 310
anhtran 0:e9fd5575b10e 311 /**************************************************************************//**
anhtran 0:e9fd5575b10e 312 * Function Name: set_src_init_cfg
anhtran 0:e9fd5575b10e 313 * @brief SRC configuration initialization.
anhtran 0:e9fd5575b10e 314 *
anhtran 0:e9fd5575b10e 315 * Description:<br>
anhtran 0:e9fd5575b10e 316 *
anhtran 0:e9fd5575b10e 317 * @param[in] src_cfg SRC configuration.
anhtran 0:e9fd5575b10e 318 * @retval true Setting success.
anhtran 0:e9fd5575b10e 319 * false Setting fails.
anhtran 0:e9fd5575b10e 320 ******************************************************************************/
anhtran 0:e9fd5575b10e 321 static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg) {
anhtran 0:e9fd5575b10e 322 bool ret = true;
anhtran 0:e9fd5575b10e 323
anhtran 0:e9fd5575b10e 324 if (src_cfg == NULL) {
anhtran 0:e9fd5575b10e 325 ret = false;
anhtran 0:e9fd5575b10e 326 } else {
anhtran 0:e9fd5575b10e 327 src_cfg->src_enable = true;
anhtran 0:e9fd5575b10e 328 src_cfg->use_ch = SCUX_USE_CH_2;
anhtran 0:e9fd5575b10e 329 src_cfg->word_len = SCUX_DATA_LEN_16;
anhtran 0:e9fd5575b10e 330 src_cfg->mode_sync = true;
anhtran 0:e9fd5575b10e 331 src_cfg->input_rate_sync = SCUX_SYNC_RATE_48;
anhtran 0:e9fd5575b10e 332 src_cfg->input_clk_async = SCUX_CLK_USB_X1;
anhtran 0:e9fd5575b10e 333 src_cfg->input_div_async = INPUT_DIV_INIT_VALUE;
anhtran 0:e9fd5575b10e 334 src_cfg->output_rate_sync = SCUX_SYNC_RATE_96;
anhtran 0:e9fd5575b10e 335 src_cfg->output_clk_async = SCUX_CLK_SSIF0_WS;
anhtran 0:e9fd5575b10e 336 src_cfg->output_div_async = OUTPUT_DIV_INIT_VALUE;
anhtran 0:e9fd5575b10e 337 src_cfg->input_ws = INPUT_WS_INIT_VALUE;
anhtran 0:e9fd5575b10e 338 src_cfg->output_ws = OUTPUT_WS_INIT_VALUE;
anhtran 0:e9fd5575b10e 339 src_cfg->freq_tioc3a = FREQ_TIOC3A_INIT_VALUE;
anhtran 0:e9fd5575b10e 340 src_cfg->freq_tioc4a = FREQ_TIOC4A_INIT_VALUE;
anhtran 0:e9fd5575b10e 341 src_cfg->delay_mode = SCUX_DELAY_NORMAL;
anhtran 0:e9fd5575b10e 342 src_cfg->wait_sample = WAIT_SAMPLE_INIT_VALUE;
anhtran 0:e9fd5575b10e 343 src_cfg->min_rate_percentage = MIN_RATE_PER_INIT_VALUE;
anhtran 0:e9fd5575b10e 344 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_0] = SCUX_AUDIO_CH_0;
anhtran 0:e9fd5575b10e 345 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_1] = SCUX_AUDIO_CH_1;
anhtran 0:e9fd5575b10e 346 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_2] = SCUX_AUDIO_CH_2;
anhtran 0:e9fd5575b10e 347 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_3] = SCUX_AUDIO_CH_3;
anhtran 0:e9fd5575b10e 348 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_4] = SCUX_AUDIO_CH_4;
anhtran 0:e9fd5575b10e 349 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_5] = SCUX_AUDIO_CH_5;
anhtran 0:e9fd5575b10e 350 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_6] = SCUX_AUDIO_CH_6;
anhtran 0:e9fd5575b10e 351 src_cfg->select_in_data_ch[SCUX_AUDIO_CH_7] = SCUX_AUDIO_CH_7;
anhtran 0:e9fd5575b10e 352 }
anhtran 0:e9fd5575b10e 353
anhtran 0:e9fd5575b10e 354 return ret;
anhtran 0:e9fd5575b10e 355 }
anhtran 0:e9fd5575b10e 356
anhtran 0:e9fd5575b10e 357 #endif /* R_BSP_SCUX_ENABLE */