Anh Tran / Mbed OS GR-Boards_WebCamera

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mbed-gr-libs/GR-PEACH_video/DisplayBace.h@0:e9fd5575b10e, 2019-10-18 (annotated)

Committer:
anhtran
Date:
Fri Oct 18 03:09:43 2019 +0000
Revision:
0:e9fd5575b10e
abc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
anhtran 0:e9fd5575b10e 1 /*******************************************************************************
anhtran 0:e9fd5575b10e 2 * DISCLAIMER
anhtran 0:e9fd5575b10e 3 * This software is supplied by Renesas Electronics Corporation and is only
anhtran 0:e9fd5575b10e 4 * intended for use with Renesas products. No other uses are authorized. This
anhtran 0:e9fd5575b10e 5 * software is owned by Renesas Electronics Corporation and is protected under
anhtran 0:e9fd5575b10e 6 * all applicable laws, including copyright laws.
anhtran 0:e9fd5575b10e 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
anhtran 0:e9fd5575b10e 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
anhtran 0:e9fd5575b10e 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
anhtran 0:e9fd5575b10e 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
anhtran 0:e9fd5575b10e 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
anhtran 0:e9fd5575b10e 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
anhtran 0:e9fd5575b10e 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
anhtran 0:e9fd5575b10e 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
anhtran 0:e9fd5575b10e 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
anhtran 0:e9fd5575b10e 16 * Renesas reserves the right, without notice, to make changes to this software
anhtran 0:e9fd5575b10e 17 * and to discontinue the availability of this software. By using this software,
anhtran 0:e9fd5575b10e 18 * you agree to the additional terms and conditions found by accessing the
anhtran 0:e9fd5575b10e 19 * following link:
anhtran 0:e9fd5575b10e 20 * http://www.renesas.com/disclaimer
anhtran 0:e9fd5575b10e 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
anhtran 0:e9fd5575b10e 22 *******************************************************************************/
anhtran 0:e9fd5575b10e 23 /**************************************************************************//**
anhtran 0:e9fd5575b10e 24 * @file DisplayBase.h
anhtran 0:e9fd5575b10e 25 * @brief Display driver wrapper class for GR-PEACH
anhtran 0:e9fd5575b10e 26 ******************************************************************************/
anhtran 0:e9fd5575b10e 27
anhtran 0:e9fd5575b10e 28 #ifndef MBED_DISPLAYBASE_H
anhtran 0:e9fd5575b10e 29 #define MBED_DISPLAYBASE_H
anhtran 0:e9fd5575b10e 30
anhtran 0:e9fd5575b10e 31 #include "pinmap.h"
anhtran 0:e9fd5575b10e 32
anhtran 0:e9fd5575b10e 33 /*! @class DisplayBase
anhtran 0:e9fd5575b10e 34 * @brief Display driver wrapper class for GR-PEACH
anhtran 0:e9fd5575b10e 35 */
anhtran 0:e9fd5575b10e 36 class DisplayBase
anhtran 0:e9fd5575b10e 37 {
anhtran 0:e9fd5575b10e 38
anhtran 0:e9fd5575b10e 39 public:
anhtran 0:e9fd5575b10e 40 /*! @enum video_input_channel_t
anhtran 0:e9fd5575b10e 41 @brief Video input channel select
anhtran 0:e9fd5575b10e 42 */
anhtran 0:e9fd5575b10e 43 typedef enum {
anhtran 0:e9fd5575b10e 44 VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */
anhtran 0:e9fd5575b10e 45 VIDEO_INPUT_CHANNEL_1 /*!< Video input channel 1 */
anhtran 0:e9fd5575b10e 46 } video_input_channel_t;
anhtran 0:e9fd5575b10e 47
anhtran 0:e9fd5575b10e 48 /*! @enum video_adc_vinsel_t
anhtran 0:e9fd5575b10e 49 @brief Input pin control
anhtran 0:e9fd5575b10e 50 */
anhtran 0:e9fd5575b10e 51 typedef enum {
anhtran 0:e9fd5575b10e 52 VIDEO_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input */
anhtran 0:e9fd5575b10e 53 VIDEO_ADC_VINSEL_VIN2 /*!< VIN2 input */
anhtran 0:e9fd5575b10e 54 } video_adc_vinsel_t;
anhtran 0:e9fd5575b10e 55
anhtran 0:e9fd5575b10e 56 /*! @enum graphics_layer_t
anhtran 0:e9fd5575b10e 57 @brief Graphics layer select
anhtran 0:e9fd5575b10e 58 */
anhtran 0:e9fd5575b10e 59 typedef enum {
anhtran 0:e9fd5575b10e 60 GRAPHICS_LAYER_0 = 0, /*!< Graphics layer 0 */
anhtran 0:e9fd5575b10e 61 GRAPHICS_LAYER_1, /*!< Graphics layer 1 */
anhtran 0:e9fd5575b10e 62 GRAPHICS_LAYER_2, /*!< Graphics layer 2 */
anhtran 0:e9fd5575b10e 63 GRAPHICS_LAYER_3 /*!< Graphics layer 3 */
anhtran 0:e9fd5575b10e 64 } graphics_layer_t;
anhtran 0:e9fd5575b10e 65
anhtran 0:e9fd5575b10e 66 /*! @enum graphics_error_t
anhtran 0:e9fd5575b10e 67 @brief Error codes
anhtran 0:e9fd5575b10e 68 */
anhtran 0:e9fd5575b10e 69 typedef enum {
anhtran 0:e9fd5575b10e 70 GRAPHICS_OK = 0, /*!< Normal termination */
anhtran 0:e9fd5575b10e 71 GRAPHICS_VDC5_ERR = -1, /*!< VDC5 driver error */
anhtran 0:e9fd5575b10e 72 GRAPHICS_FORMA_ERR = -2, /*!< Not support format */
anhtran 0:e9fd5575b10e 73 GRAPHICS_LAYER_ERR = -3, /*!< Invalid layer ID error */
anhtran 0:e9fd5575b10e 74 GRAPHICS_CHANNLE_ERR = -4, /*!< Invalid channel error */
anhtran 0:e9fd5575b10e 75 GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */
anhtran 0:e9fd5575b10e 76 GRAPHICS_VIDEO_PAL_SIZE_ERR = -6, /*!< Video Write size(vw) error */
anhtran 0:e9fd5575b10e 77 GRAPHICS_PARAM_RANGE_ERR = -7 /*!< Parameter range error */
anhtran 0:e9fd5575b10e 78 } graphics_error_t;
anhtran 0:e9fd5575b10e 79
anhtran 0:e9fd5575b10e 80 /*! @enum graphics_format_t
anhtran 0:e9fd5575b10e 81 @brief Graphics layer read format selects
anhtran 0:e9fd5575b10e 82 */
anhtran 0:e9fd5575b10e 83 typedef enum {
anhtran 0:e9fd5575b10e 84 GRAPHICS_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
anhtran 0:e9fd5575b10e 85 GRAPHICS_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
anhtran 0:e9fd5575b10e 86 GRAPHICS_FORMAT_RGB888, /*!< RGB888 (4byte / px) */
anhtran 0:e9fd5575b10e 87 GRAPHICS_FORMAT_ARGB8888, /*!< ARGB8888 (4byte / px) */
anhtran 0:e9fd5575b10e 88 GRAPHICS_FORMAT_ARGB4444, /*!< ARGB4444 (2byte / px) */
anhtran 0:e9fd5575b10e 89 GRAPHICS_FORMAT_CLUT8, /*!< CLUT8 (1byte / px) */
anhtran 0:e9fd5575b10e 90 GRAPHICS_FORMAT_CLUT4, /*!< CLUT4 (0.5byte / px) */
anhtran 0:e9fd5575b10e 91 GRAPHICS_FORMAT_CLUT1 /*!< CLUT1 (0.125byte / px) */
anhtran 0:e9fd5575b10e 92 } graphics_format_t;
anhtran 0:e9fd5575b10e 93
anhtran 0:e9fd5575b10e 94 /*! @enum video_format_t
anhtran 0:e9fd5575b10e 95 @brief Video writing format selects
anhtran 0:e9fd5575b10e 96 */
anhtran 0:e9fd5575b10e 97 typedef enum {
anhtran 0:e9fd5575b10e 98 VIDEO_FORMAT_YCBCR422 = 0, /*!< YCbCr422 (2byte / px) */
anhtran 0:e9fd5575b10e 99 VIDEO_FORMAT_RGB565, /*!< RGB565 (2byte / px) */
anhtran 0:e9fd5575b10e 100 VIDEO_FORMAT_RGB888, /*!< RGB888 (4byte / px) */
anhtran 0:e9fd5575b10e 101 VIDEO_FORMAT_RAW8 /*!< RAW8 (1byte / px) */
anhtran 0:e9fd5575b10e 102 } video_format_t;
anhtran 0:e9fd5575b10e 103
anhtran 0:e9fd5575b10e 104 /*! @enum wr_rd_swa_t
anhtran 0:e9fd5575b10e 105 @brief Frame buffer swap setting
anhtran 0:e9fd5575b10e 106 */
anhtran 0:e9fd5575b10e 107 typedef enum {
anhtran 0:e9fd5575b10e 108 WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */
anhtran 0:e9fd5575b10e 109 WR_RD_WRSWA_8BIT, /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
anhtran 0:e9fd5575b10e 110 WR_RD_WRSWA_16BIT, /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
anhtran 0:e9fd5575b10e 111 WR_RD_WRSWA_16_8BIT, /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
anhtran 0:e9fd5575b10e 112 WR_RD_WRSWA_32BIT, /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
anhtran 0:e9fd5575b10e 113 WR_RD_WRSWA_32_8BIT, /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
anhtran 0:e9fd5575b10e 114 WR_RD_WRSWA_32_16BIT, /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
anhtran 0:e9fd5575b10e 115 WR_RD_WRSWA_32_16_8BIT, /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
anhtran 0:e9fd5575b10e 116 } wr_rd_swa_t;
anhtran 0:e9fd5575b10e 117
anhtran 0:e9fd5575b10e 118 /*! @enum lcd_tcon_pin_t
anhtran 0:e9fd5575b10e 119 @brief LCD tcon output pin selects
anhtran 0:e9fd5575b10e 120 */
anhtran 0:e9fd5575b10e 121 typedef enum {
anhtran 0:e9fd5575b10e 122 LCD_TCON_PIN_NON = -1, /*!< Not using output */
anhtran 0:e9fd5575b10e 123 LCD_TCON_PIN_0, /*!< LCD_TCON0 */
anhtran 0:e9fd5575b10e 124 LCD_TCON_PIN_1, /*!< LCD_TCON1 */
anhtran 0:e9fd5575b10e 125 LCD_TCON_PIN_2, /*!< LCD_TCON2 */
anhtran 0:e9fd5575b10e 126 LCD_TCON_PIN_3, /*!< LCD_TCON3 */
anhtran 0:e9fd5575b10e 127 LCD_TCON_PIN_4, /*!< LCD_TCON4 */
anhtran 0:e9fd5575b10e 128 } lcd_tcon_pin_t;
anhtran 0:e9fd5575b10e 129
anhtran 0:e9fd5575b10e 130 /*! @enum lcd_outformat_t
anhtran 0:e9fd5575b10e 131 @brief LCD output format selects
anhtran 0:e9fd5575b10e 132 */
anhtran 0:e9fd5575b10e 133 typedef enum {
anhtran 0:e9fd5575b10e 134 LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 or LVDS */
anhtran 0:e9fd5575b10e 135 LCD_OUTFORMAT_RGB666, /*!< RGB666 */
anhtran 0:e9fd5575b10e 136 LCD_OUTFORMAT_RGB565 /*!< RGB565 */
anhtran 0:e9fd5575b10e 137 } lcd_outformat_t;
anhtran 0:e9fd5575b10e 138
anhtran 0:e9fd5575b10e 139 /*! @enum edge_t
anhtran 0:e9fd5575b10e 140 @brief Edge of a signal
anhtran 0:e9fd5575b10e 141 */
anhtran 0:e9fd5575b10e 142 typedef enum {
anhtran 0:e9fd5575b10e 143 EDGE_RISING = 0, /*!< Rising edge */
anhtran 0:e9fd5575b10e 144 EDGE_FALLING = 1 /*!< Falling edge */
anhtran 0:e9fd5575b10e 145 } edge_t;
anhtran 0:e9fd5575b10e 146
anhtran 0:e9fd5575b10e 147 /*! @enum lcd_type_t
anhtran 0:e9fd5575b10e 148 @brief LCD type
anhtran 0:e9fd5575b10e 149 */
anhtran 0:e9fd5575b10e 150 typedef enum {
anhtran 0:e9fd5575b10e 151 LCD_TYPE_LVDS = 0, /*!< LVDS control */
anhtran 0:e9fd5575b10e 152 LCD_TYPE_PARALLEL_RGB /*!< RGB parallel signal control */
anhtran 0:e9fd5575b10e 153 } lcd_type_t;
anhtran 0:e9fd5575b10e 154
anhtran 0:e9fd5575b10e 155 /*! @enum sig_pol_t
anhtran 0:e9fd5575b10e 156 @brief Polarity of a signal
anhtran 0:e9fd5575b10e 157 */
anhtran 0:e9fd5575b10e 158 typedef enum {
anhtran 0:e9fd5575b10e 159 SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */
anhtran 0:e9fd5575b10e 160 SIG_POL_INVERTED /*!< Inverted */
anhtran 0:e9fd5575b10e 161 } sig_pol_t;
anhtran 0:e9fd5575b10e 162
anhtran 0:e9fd5575b10e 163 /*! @enum int_type_t
anhtran 0:e9fd5575b10e 164 @brief Interrupt type
anhtran 0:e9fd5575b10e 165 */
anhtran 0:e9fd5575b10e 166 typedef enum {
anhtran 0:e9fd5575b10e 167 INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */
anhtran 0:e9fd5575b10e 168 INT_TYPE_S0_LO_VSYNC, /*!< Vsync signal output from scaler 0 */
anhtran 0:e9fd5575b10e 169 INT_TYPE_S0_VSYNCERR, /*!< Missing Vsync signal for scaler 0 */
anhtran 0:e9fd5575b10e 170 INT_TYPE_VLINE, /*!< Specified line signal for panel output in graphics 3 */
anhtran 0:e9fd5575b10e 171 INT_TYPE_S0_VFIELD, /*!< Field end signal for recording function in scaler 0 */
anhtran 0:e9fd5575b10e 172 INT_TYPE_IV1_VBUFERR, /*!< Frame buffer write overflow signal for scaler 0 */
anhtran 0:e9fd5575b10e 173 INT_TYPE_IV3_VBUFERR, /*!< Frame buffer read underflow signal for graphics 0 */
anhtran 0:e9fd5575b10e 174 INT_TYPE_IV5_VBUFERR, /*!< Frame buffer read underflow signal for graphics 2 */
anhtran 0:e9fd5575b10e 175 INT_TYPE_IV6_VBUFERR, /*!< Frame buffer read underflow signal for graphics 3 */
anhtran 0:e9fd5575b10e 176 INT_TYPE_S0_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 0 */
anhtran 0:e9fd5575b10e 177 INT_TYPE_S1_VI_VSYNC, /*!< Vsync signal input to scaler 1 */
anhtran 0:e9fd5575b10e 178 INT_TYPE_S1_LO_VSYNC, /*!< Vsync signal output from scaler 1 */
anhtran 0:e9fd5575b10e 179 INT_TYPE_S1_VSYNCERR, /*!< Missing Vsync signal for scaler 1 */
anhtran 0:e9fd5575b10e 180 INT_TYPE_S1_VFIELD, /*!< Field end signal for recording function in scaler 1 */
anhtran 0:e9fd5575b10e 181 INT_TYPE_IV2_VBUFERR, /*!< Frame buffer write overflow signal for scaler 1 */
anhtran 0:e9fd5575b10e 182 INT_TYPE_IV4_VBUFERR, /*!< Frame buffer read underflow signal for graphics 1 */
anhtran 0:e9fd5575b10e 183 INT_TYPE_S1_WLINE, /*!< Write specification line signal input to scaling-down control block in scaler 1 */
anhtran 0:e9fd5575b10e 184 INT_TYPE_OIR_VI_VSYNC, /*!< Vsync signal input to output image generator */
anhtran 0:e9fd5575b10e 185 INT_TYPE_OIR_LO_VSYNC, /*!< Vsync signal output from output image generator */
anhtran 0:e9fd5575b10e 186 INT_TYPE_OIR_VLINE, /*!< Specified line signal for panel output in output image generator */
anhtran 0:e9fd5575b10e 187 INT_TYPE_OIR_VFIELD, /*!< Field end signal for recording function in output image generator */
anhtran 0:e9fd5575b10e 188 INT_TYPE_IV7_VBUFERR, /*!< Frame buffer write overflow signal for output image generator */
anhtran 0:e9fd5575b10e 189 INT_TYPE_IV8_VBUFERR, /*!< Frame buffer read underflow signal for graphics (OIR) */
anhtran 0:e9fd5575b10e 190 INT_TYPE_NUM /*!< The number of VDC5 interrupt types */
anhtran 0:e9fd5575b10e 191 } int_type_t;
anhtran 0:e9fd5575b10e 192
anhtran 0:e9fd5575b10e 193 /*! @enum graphics_video_col_sys_t
anhtran 0:e9fd5575b10e 194 @brief Video color system
anhtran 0:e9fd5575b10e 195 */
anhtran 0:e9fd5575b10e 196 typedef enum {
anhtran 0:e9fd5575b10e 197 COL_SYS_NTSC_358 = 0, /*!< NTSC-3.58 */
anhtran 0:e9fd5575b10e 198 COL_SYS_NTSC_443 = 1, /*!< NTSC-4.43 */
anhtran 0:e9fd5575b10e 199 COL_SYS_PAL_443 = 2, /*!< PAL-4.43 */
anhtran 0:e9fd5575b10e 200 COL_SYS_PAL_M = 3, /*!< PAL-M */
anhtran 0:e9fd5575b10e 201 COL_SYS_PAL_N = 4, /*!< PAL-N */
anhtran 0:e9fd5575b10e 202 COL_SYS_SECAM = 5, /*!< SECAM */
anhtran 0:e9fd5575b10e 203 COL_SYS_NTSC_443_60 = 6, /*!< NTSC-4.43 (60Hz) */
anhtran 0:e9fd5575b10e 204 COL_SYS_PAL_60 = 7, /*!< PAL-60 */
anhtran 0:e9fd5575b10e 205 } graphics_video_col_sys_t;
anhtran 0:e9fd5575b10e 206
anhtran 0:e9fd5575b10e 207 /*! @enum video_input_sel_t
anhtran 0:e9fd5575b10e 208 @brief External Input select
anhtran 0:e9fd5575b10e 209 */
anhtran 0:e9fd5575b10e 210 typedef enum {
anhtran 0:e9fd5575b10e 211 INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
anhtran 0:e9fd5575b10e 212 INPUT_SEL_EXT = 1, /*!< Signals supplied via the external input pins */
anhtran 0:e9fd5575b10e 213 INPUT_SEL_CEU = 2, /*!< Signals supplied via the CEU input pins */
anhtran 0:e9fd5575b10e 214 INPUT_SEL_MIPI = 3 /*!< Signals supplied via the MIPI input pins */
anhtran 0:e9fd5575b10e 215 } video_input_sel_t;
anhtran 0:e9fd5575b10e 216
anhtran 0:e9fd5575b10e 217 /*! @enum video_extin_format_t
anhtran 0:e9fd5575b10e 218 @brief External input format select
anhtran 0:e9fd5575b10e 219 */
anhtran 0:e9fd5575b10e 220 typedef enum {
anhtran 0:e9fd5575b10e 221 VIDEO_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 Not support */
anhtran 0:e9fd5575b10e 222 VIDEO_EXTIN_FORMAT_RGB666, /*!< RGB666 */
anhtran 0:e9fd5575b10e 223 VIDEO_EXTIN_FORMAT_RGB565, /*!< RGB565 */
anhtran 0:e9fd5575b10e 224 VIDEO_EXTIN_FORMAT_BT656, /*!< BT6556 */
anhtran 0:e9fd5575b10e 225 VIDEO_EXTIN_FORMAT_BT601, /*!< BT6501 */
anhtran 0:e9fd5575b10e 226 VIDEO_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
anhtran 0:e9fd5575b10e 227 VIDEO_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 Not support */
anhtran 0:e9fd5575b10e 228 } video_extin_format_t;
anhtran 0:e9fd5575b10e 229
anhtran 0:e9fd5575b10e 230 /*! @enum onoff_t
anhtran 0:e9fd5575b10e 231 @brief On/off
anhtran 0:e9fd5575b10e 232 */
anhtran 0:e9fd5575b10e 233 typedef enum {
anhtran 0:e9fd5575b10e 234 OFF = 0, /*!< Off */
anhtran 0:e9fd5575b10e 235 ON = 1 /*!< On */
anhtran 0:e9fd5575b10e 236 } onoff_t;
anhtran 0:e9fd5575b10e 237
anhtran 0:e9fd5575b10e 238 /*! @enum extin_input_line_t
anhtran 0:e9fd5575b10e 239 @brief Number of lines for BT.656 external input
anhtran 0:e9fd5575b10e 240 */
anhtran 0:e9fd5575b10e 241 typedef enum {
anhtran 0:e9fd5575b10e 242 EXTIN_LINE_525 = 0, /*!< 525 lines */
anhtran 0:e9fd5575b10e 243 EXTIN_LINE_625 = 1 /*!< 625 lines */
anhtran 0:e9fd5575b10e 244 } extin_input_line_t;
anhtran 0:e9fd5575b10e 245
anhtran 0:e9fd5575b10e 246 /*! @enum extin_h_pos_t
anhtran 0:e9fd5575b10e 247 @brief Y/Cb/Y/Cr data string start timing
anhtran 0:e9fd5575b10e 248 */
anhtran 0:e9fd5575b10e 249 typedef enum {
anhtran 0:e9fd5575b10e 250 EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
anhtran 0:e9fd5575b10e 251 EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
anhtran 0:e9fd5575b10e 252 EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
anhtran 0:e9fd5575b10e 253 EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
anhtran 0:e9fd5575b10e 254 EXTIN_H_POS_NUM
anhtran 0:e9fd5575b10e 255 } extin_h_pos_t;
anhtran 0:e9fd5575b10e 256
anhtran 0:e9fd5575b10e 257 /*! @struct rect_t
anhtran 0:e9fd5575b10e 258 @brief The relative position within the graphics display area
anhtran 0:e9fd5575b10e 259 */
anhtran 0:e9fd5575b10e 260 typedef struct {
anhtran 0:e9fd5575b10e 261 unsigned short vs; /*!< Vertical start pos */
anhtran 0:e9fd5575b10e 262 unsigned short vw; /*!< Vertical width (height) */
anhtran 0:e9fd5575b10e 263 unsigned short hs; /*!< Horizontal start pos */
anhtran 0:e9fd5575b10e 264 unsigned short hw; /*!< Horizontal width */
anhtran 0:e9fd5575b10e 265 } rect_t;
anhtran 0:e9fd5575b10e 266
anhtran 0:e9fd5575b10e 267 /*! @struct clut_t
anhtran 0:e9fd5575b10e 268 @brief CLUT setup parameter
anhtran 0:e9fd5575b10e 269 */
anhtran 0:e9fd5575b10e 270 typedef struct {
anhtran 0:e9fd5575b10e 271 uint32_t color_num; /*!< The number of colors in CLUT */
anhtran 0:e9fd5575b10e 272 const uint32_t * clut; /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
anhtran 0:e9fd5575b10e 273 } clut_t;
anhtran 0:e9fd5575b10e 274
anhtran 0:e9fd5575b10e 275 /*! @struct lcd_config_t
anhtran 0:e9fd5575b10e 276 @brief LCD configuration
anhtran 0:e9fd5575b10e 277 */
anhtran 0:e9fd5575b10e 278 typedef struct {
anhtran 0:e9fd5575b10e 279 lcd_type_t lcd_type; /*!< LVDS or Pararel RGB */
anhtran 0:e9fd5575b10e 280 double intputClock; /*!< P1 clk [MHz] ex. 66.67f */
anhtran 0:e9fd5575b10e 281 double outputClock; /*!< LCD clk [MHz] ex. 33.33f */
anhtran 0:e9fd5575b10e 282
anhtran 0:e9fd5575b10e 283 lcd_outformat_t lcd_outformat; /*!< Output format select */
anhtran 0:e9fd5575b10e 284 edge_t lcd_edge; /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */
anhtran 0:e9fd5575b10e 285
anhtran 0:e9fd5575b10e 286 unsigned short h_toatal_period; /*!< Free-running Hsync period */
anhtran 0:e9fd5575b10e 287 unsigned short v_toatal_period; /*!< Free-running Vsync period */
anhtran 0:e9fd5575b10e 288 unsigned short h_disp_widht; /*!< LCD display area size, horizontal width */
anhtran 0:e9fd5575b10e 289 unsigned short v_disp_widht; /*!< LCD display area size, vertical width */
anhtran 0:e9fd5575b10e 290 unsigned short h_back_porch; /*!< LCD display horizontal back porch period */
anhtran 0:e9fd5575b10e 291 unsigned short v_back_porch; /*!< LCD display vertical back porch period */
anhtran 0:e9fd5575b10e 292
anhtran 0:e9fd5575b10e 293 lcd_tcon_pin_t h_sync_port; /*!< TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 294 sig_pol_t h_sync_port_polarity; /*!< Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 295 unsigned short h_sync_width; /*!< Hsync width */
anhtran 0:e9fd5575b10e 296
anhtran 0:e9fd5575b10e 297 lcd_tcon_pin_t v_sync_port; /*!< TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 298 sig_pol_t v_sync_port_polarity; /*!< Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 299 unsigned short v_sync_width; /*!< Vsync width */
anhtran 0:e9fd5575b10e 300
anhtran 0:e9fd5575b10e 301 lcd_tcon_pin_t de_port; /*!< TCONn or Not use(-1) */
anhtran 0:e9fd5575b10e 302 sig_pol_t de_port_polarity; /*!< Polarity inversion control of signal */
anhtran 0:e9fd5575b10e 303 } lcd_config_t;
anhtran 0:e9fd5575b10e 304
anhtran 0:e9fd5575b10e 305 /*! @struct video_ext_in_config_t
anhtran 0:e9fd5575b10e 306 @brief Digital Video Input configuration
anhtran 0:e9fd5575b10e 307 */
anhtran 0:e9fd5575b10e 308 typedef struct {
anhtran 0:e9fd5575b10e 309 video_extin_format_t inp_format; /*!< External Input Format Select */
anhtran 0:e9fd5575b10e 310 edge_t inp_pxd_edge; /*!< Clock Edge Select for Capturing External Input Video Image */
anhtran 0:e9fd5575b10e 311 edge_t inp_vs_edge; /*!< Clock Edge Select for Capturing External Input Vsync Signal */
anhtran 0:e9fd5575b10e 312 edge_t inp_hs_edge; /*!< Clock Edge Select for Capturing External Input Hsync Signal */
anhtran 0:e9fd5575b10e 313 onoff_t inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control */
anhtran 0:e9fd5575b10e 314 onoff_t inp_swap_on; /*!< External Input Bit Endian Change On/Off Control */
anhtran 0:e9fd5575b10e 315 sig_pol_t inp_vs_inv; /*!< External Input Vsync Signal DV_VSYNC Inversion Control */
anhtran 0:e9fd5575b10e 316 sig_pol_t inp_hs_inv; /*!< External Input Hsync Signal DV_HSYNC Inversion Control */
anhtran 0:e9fd5575b10e 317 extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
anhtran 0:e9fd5575b10e 318 extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
anhtran 0:e9fd5575b10e 319 unsigned short cap_vs_pos; /*!< Capture start position from Vsync */
anhtran 0:e9fd5575b10e 320 unsigned short cap_hs_pos; /*!< Capture start position form Hsync */
anhtran 0:e9fd5575b10e 321 unsigned short cap_width; /*!< Capture width */
anhtran 0:e9fd5575b10e 322 unsigned short cap_height; /*!< Capture height should be a multiple of 4.*/
anhtran 0:e9fd5575b10e 323 } video_ext_in_config_t;
anhtran 0:e9fd5575b10e 324
anhtran 0:e9fd5575b10e 325 /* mipi phy timing struct */
anhtran 0:e9fd5575b10e 326 typedef struct {
anhtran 0:e9fd5575b10e 327 uint16_t mipi_ths_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0 state) */
anhtran 0:e9fd5575b10e 328 uint16_t mipi_ths_settle; /*!< Setting of the period in which a transition to the HS state is ignored after the TTHS_PREPARE period begins */
anhtran 0:e9fd5575b10e 329 uint16_t mipi_tclk_prepare; /*!< Setting of the duration of the LP-00 state (immediately before entry to the HS-0) */
anhtran 0:e9fd5575b10e 330 uint16_t mipi_tclk_settle; /*!< Setting of the period in which a transition to the HS state is ignored after the TCLK_PREPARE period begins */
anhtran 0:e9fd5575b10e 331 uint16_t mipi_tclk_miss; /*!< Setting of the period in which the absence of the clock is detected, and the HS-RX is disabled */
anhtran 0:e9fd5575b10e 332 uint16_t mipi_t_init_slave; /*!< Minimum duration of the INIT state */
anhtran 0:e9fd5575b10e 333 } video_mipi_phy_timing_t;
anhtran 0:e9fd5575b10e 334
anhtran 0:e9fd5575b10e 335 /* mipi parameter struct */
anhtran 0:e9fd5575b10e 336 typedef struct {
anhtran 0:e9fd5575b10e 337 uint8_t mipi_lanenum; /*!< Mipi Lane Num */
anhtran 0:e9fd5575b10e 338 uint8_t mipi_vc; /*!< Mipi Virtual Channel */
anhtran 0:e9fd5575b10e 339 uint8_t mipi_interlace; /*!< Interlace or Progressive */
anhtran 0:e9fd5575b10e 340 uint8_t mipi_laneswap; /*!< Mipi Lane Swap Setting */
anhtran 0:e9fd5575b10e 341 uint16_t mipi_frametop; /*!< (for Interlace)Top Field Packet ID */
anhtran 0:e9fd5575b10e 342 uint16_t mipi_outputrate; /*!< Mipi Data Send Speed(Mbit per sec) */
anhtran 0:e9fd5575b10e 343 video_mipi_phy_timing_t mipi_phy_timing; /*!< Mipi D-PHY timing settings */
anhtran 0:e9fd5575b10e 344 } video_mipi_param_t;
anhtran 0:e9fd5575b10e 345
anhtran 0:e9fd5575b10e 346 /*! Vin parameter Struct */
anhtran 0:e9fd5575b10e 347 typedef struct {
anhtran 0:e9fd5575b10e 348 uint16_t vin_preclip_starty; /*!< Pre Area Clip Start Line */
anhtran 0:e9fd5575b10e 349 uint16_t vin_preclip_endy; /*!< Pre Area Clip End Line */
anhtran 0:e9fd5575b10e 350 uint16_t vin_preclip_startx; /*!< Pre Area Clip Start Column */
anhtran 0:e9fd5575b10e 351 uint16_t vin_preclip_endx; /*!< Pre Area Clip End Column */
anhtran 0:e9fd5575b10e 352 } video_vin_preclip_t;
anhtran 0:e9fd5575b10e 353
anhtran 0:e9fd5575b10e 354 typedef struct {
anhtran 0:e9fd5575b10e 355 uint8_t vin_scaleon; /*!< Scaling On or OFF */
anhtran 0:e9fd5575b10e 356 uint8_t vin_interpolation; /*!< Scaling Interpolation */
anhtran 0:e9fd5575b10e 357 uint16_t vin_scale_h; /*!< Horizontal multiple */
anhtran 0:e9fd5575b10e 358 uint16_t vin_scale_v; /*!< vertical multiple */
anhtran 0:e9fd5575b10e 359 } video_vin_scale_t;
anhtran 0:e9fd5575b10e 360
anhtran 0:e9fd5575b10e 361 typedef struct {
anhtran 0:e9fd5575b10e 362 uint16_t vin_afterclip_size_x; /*!< After Area Clip horizontal size */
anhtran 0:e9fd5575b10e 363 uint16_t vin_afterclip_size_y; /*!< After Area Clip vertical size */
anhtran 0:e9fd5575b10e 364 } video_vin_afterclip_t;
anhtran 0:e9fd5575b10e 365
anhtran 0:e9fd5575b10e 366 /*! YCbCr422 input data alignment */
anhtran 0:e9fd5575b10e 367 typedef enum
anhtran 0:e9fd5575b10e 368 {
anhtran 0:e9fd5575b10e 369 VIN_Y_UPPER = 0, /*!< Upper bit is Y, lower bit is CbCr */
anhtran 0:e9fd5575b10e 370 VIN_CB_UPPER, /*!< Upper bit is CbCr, lower bit is Y */
anhtran 0:e9fd5575b10e 371 } video_vin_input_align_t;
anhtran 0:e9fd5575b10e 372
anhtran 0:e9fd5575b10e 373 /*! Output data byte swap mode */
anhtran 0:e9fd5575b10e 374 typedef enum
anhtran 0:e9fd5575b10e 375 {
anhtran 0:e9fd5575b10e 376 VIN_SWAP_OFF = 0, /*!< Not swap */
anhtran 0:e9fd5575b10e 377 VIN_SWAP_ON, /*!< Swap */
anhtran 0:e9fd5575b10e 378 } video_vin_output_swap_t;
anhtran 0:e9fd5575b10e 379
anhtran 0:e9fd5575b10e 380 typedef struct {
anhtran 0:e9fd5575b10e 381 video_vin_preclip_t vin_preclip; /*!< Pre Area Clip Parameter */
anhtran 0:e9fd5575b10e 382 video_vin_scale_t vin_scale; /*!< Scale Parameter */
anhtran 0:e9fd5575b10e 383 video_vin_afterclip_t vin_afterclip; /*!< After Area Clip Parameter */
anhtran 0:e9fd5575b10e 384 uint8_t vin_yuv_clip; /*!< YUV Range Clip Parameter */
anhtran 0:e9fd5575b10e 385 uint8_t vin_lut; /*!< LUT Conversion On or OFF */
anhtran 0:e9fd5575b10e 386 uint8_t vin_inputformat; /*!< Input Image Format */
anhtran 0:e9fd5575b10e 387 uint8_t vin_outputformat; /*!< Output Image Format */
anhtran 0:e9fd5575b10e 388 uint8_t vin_outputendian; /*!< Output Data Endian*/
anhtran 0:e9fd5575b10e 389 uint8_t vin_dither; /*!< (for RGB565 or ARGB1555)Output Data Dithering On or Off */
anhtran 0:e9fd5575b10e 390 uint8_t vin_interlace; /*!< (for Interlace input)Capture Method */
anhtran 0:e9fd5575b10e 391 uint8_t vin_alpha_val8; /*!< (for ARGB8888)Alpha Value */
anhtran 0:e9fd5575b10e 392 uint8_t vin_alpha_val1; /*!< (for ARGB1555)Alpha Value */
anhtran 0:e9fd5575b10e 393 uint16_t vin_stride; /*!< Stride (byte) */
anhtran 0:e9fd5575b10e 394 uint32_t vin_ycoffset; /*!< (for YC separate output)Address Offset Value */
anhtran 0:e9fd5575b10e 395 video_vin_input_align_t vin_input_align; /*!< YCbCr422 input data alignment */
anhtran 0:e9fd5575b10e 396 video_vin_output_swap_t vin_output_swap; /*!< Output data byte swap mode */
anhtran 0:e9fd5575b10e 397 } video_vin_setup_t;
anhtran 0:e9fd5575b10e 398
anhtran 0:e9fd5575b10e 399 /** Constructor method of display base object
anhtran 0:e9fd5575b10e 400 */
anhtran 0:e9fd5575b10e 401 DisplayBase( void );
anhtran 0:e9fd5575b10e 402
anhtran 0:e9fd5575b10e 403 /** Graphics initialization processing<br>
anhtran 0:e9fd5575b10e 404 * If not using display, set NULL in parameter.
anhtran 0:e9fd5575b10e 405 * @param[in] lcd_config : LCD configuration
anhtran 0:e9fd5575b10e 406 * @retval Error code
anhtran 0:e9fd5575b10e 407 */
anhtran 0:e9fd5575b10e 408 graphics_error_t Graphics_init( const lcd_config_t * lcd_config );
anhtran 0:e9fd5575b10e 409
anhtran 0:e9fd5575b10e 410 /** Graphics Video initialization processing<br>
anhtran 0:e9fd5575b10e 411 * If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
anhtran 0:e9fd5575b10e 412 * @param[in] video_input_sel : Input select
anhtran 0:e9fd5575b10e 413 * @param[in] video_ext_in_config : Video configuration
anhtran 0:e9fd5575b10e 414 * @retval error code
anhtran 0:e9fd5575b10e 415 */
anhtran 0:e9fd5575b10e 416 graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config );
anhtran 0:e9fd5575b10e 417
anhtran 0:e9fd5575b10e 418 /** Graphics Video initialization processing<br>
anhtran 0:e9fd5575b10e 419 * @param[in] video_input_sel : Input select
anhtran 0:e9fd5575b10e 420 * @param[in] video_mipi_config : MIPI configuration
anhtran 0:e9fd5575b10e 421 * @param[in] video_vin_setup : MIPI configuration
anhtran 0:e9fd5575b10e 422 * @retval error code
anhtran 0:e9fd5575b10e 423 */
anhtran 0:e9fd5575b10e 424 graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_mipi_param_t * video_mipi_config, video_vin_setup_t * video_vin_setup );
anhtran 0:e9fd5575b10e 425
anhtran 0:e9fd5575b10e 426 /** LCD output port initialization processing
anhtran 0:e9fd5575b10e 427 * @param[in] pin : Pin assign for LCD output
anhtran 0:e9fd5575b10e 428 * @param[in] pin_count : Total number of pin assign
anhtran 0:e9fd5575b10e 429 * @retval Error code
anhtran 0:e9fd5575b10e 430 */
anhtran 0:e9fd5575b10e 431 graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count );
anhtran 0:e9fd5575b10e 432
anhtran 0:e9fd5575b10e 433 /** LVDS output port initialization processing
anhtran 0:e9fd5575b10e 434 * @param[in] pin : Pin assign for LVDS output
anhtran 0:e9fd5575b10e 435 * @param[in] pin_count : Total number of pin assign
anhtran 0:e9fd5575b10e 436 * @retval Error code
anhtran 0:e9fd5575b10e 437 */
anhtran 0:e9fd5575b10e 438 graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count );
anhtran 0:e9fd5575b10e 439
anhtran 0:e9fd5575b10e 440 /** Digital video input port initialization processing
anhtran 0:e9fd5575b10e 441 * @param[in] pin : Pin assign for digital video input port
anhtran 0:e9fd5575b10e 442 * @param[in] pin_count : Total number of pin assign
anhtran 0:e9fd5575b10e 443 * @retval Error code
anhtran 0:e9fd5575b10e 444 */
anhtran 0:e9fd5575b10e 445 graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count );
anhtran 0:e9fd5575b10e 446
anhtran 0:e9fd5575b10e 447 /** CEU input port initialization processing
anhtran 0:e9fd5575b10e 448 * @param[in] pin : Pin assign for CEU input port
anhtran 0:e9fd5575b10e 449 * @param[in] pin_count : Total number of pin assign
anhtran 0:e9fd5575b10e 450 * @retval Error code
anhtran 0:e9fd5575b10e 451 */
anhtran 0:e9fd5575b10e 452 graphics_error_t Graphics_Ceu_Port_Init( PinName *pin, unsigned int pin_count );
anhtran 0:e9fd5575b10e 453
anhtran 0:e9fd5575b10e 454 /** Interrupt callback setup
anhtran 0:e9fd5575b10e 455 * This function performs the following processing:
anhtran 0:e9fd5575b10e 456 * - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br>
anhtran 0:e9fd5575b10e 457 * - Registers the specified interrupt callback function.<br>
anhtran 0:e9fd5575b10e 458 * - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br>
anhtran 0:e9fd5575b10e 459 * @param[in] Graphics_Irq_Handler_Set : VDC5 interrupt type
anhtran 0:e9fd5575b10e 460 * @param[in] num : Interrupt line number
anhtran 0:e9fd5575b10e 461 * @param[in] callback : Interrupt callback function pointer
anhtran 0:e9fd5575b10e 462 * @retval Error code
anhtran 0:e9fd5575b10e 463 */
anhtran 0:e9fd5575b10e 464 graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t) );
anhtran 0:e9fd5575b10e 465
anhtran 0:e9fd5575b10e 466 /** Start the graphics surface read process
anhtran 0:e9fd5575b10e 467 * @param[in] layer_id : Graphics layer ID <br />
anhtran 0:e9fd5575b10e 468 * - GRAPHICS_LAYER_0 : Layer 0
anhtran 0:e9fd5575b10e 469 * - GRAPHICS_LAYER_1 : Layer 1
anhtran 0:e9fd5575b10e 470 * - GRAPHICS_LAYER_2 : Layer 2
anhtran 0:e9fd5575b10e 471 * - GRAPHICS_LAYER_3 : Layer 3
anhtran 0:e9fd5575b10e 472 * @retval Error code
anhtran 0:e9fd5575b10e 473 */
anhtran 0:e9fd5575b10e 474 graphics_error_t Graphics_Start( graphics_layer_t layer_id );
anhtran 0:e9fd5575b10e 475
anhtran 0:e9fd5575b10e 476 /** Stop the graphics surface read process
anhtran 0:e9fd5575b10e 477 * @param[in] layer_id : Graphics layer ID <br />
anhtran 0:e9fd5575b10e 478 * - GRAPHICS_LAYER_0 : Layer 0
anhtran 0:e9fd5575b10e 479 * - GRAPHICS_LAYER_1 : Layer 1
anhtran 0:e9fd5575b10e 480 * - GRAPHICS_LAYER_2 : Layer 2
anhtran 0:e9fd5575b10e 481 * - GRAPHICS_LAYER_3 : Layer 3
anhtran 0:e9fd5575b10e 482 * @retval Error code
anhtran 0:e9fd5575b10e 483 */
anhtran 0:e9fd5575b10e 484 graphics_error_t Graphics_Stop( graphics_layer_t layer_id );
anhtran 0:e9fd5575b10e 485
anhtran 0:e9fd5575b10e 486 /** Start the video surface write process
anhtran 0:e9fd5575b10e 487 * @param[in] video_input_channel : Video input channel <br />
anhtran 0:e9fd5575b10e 488 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
anhtran 0:e9fd5575b10e 489 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
anhtran 0:e9fd5575b10e 490 * @retval Error code
anhtran 0:e9fd5575b10e 491 */
anhtran 0:e9fd5575b10e 492 graphics_error_t Video_Start ( video_input_channel_t video_input_channel );
anhtran 0:e9fd5575b10e 493
anhtran 0:e9fd5575b10e 494 /** Stop the video surface write process
anhtran 0:e9fd5575b10e 495 * @param[in] video_input_channel : Video input channel <br />
anhtran 0:e9fd5575b10e 496 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
anhtran 0:e9fd5575b10e 497 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
anhtran 0:e9fd5575b10e 498 * @retval Error code
anhtran 0:e9fd5575b10e 499 */
anhtran 0:e9fd5575b10e 500 graphics_error_t Video_Stop ( video_input_channel_t video_input_channel );
anhtran 0:e9fd5575b10e 501
anhtran 0:e9fd5575b10e 502 /** Graphics surface read process setting
anhtran 0:e9fd5575b10e 503 * @param[in] layer_id : Graphics layer ID <br />
anhtran 0:e9fd5575b10e 504 * - GRAPHICS_LAYER_0 : Layer 0
anhtran 0:e9fd5575b10e 505 * - GRAPHICS_LAYER_1 : Layer 1
anhtran 0:e9fd5575b10e 506 * - GRAPHICS_LAYER_2 : Layer 2
anhtran 0:e9fd5575b10e 507 * - GRAPHICS_LAYER_3 : Layer 3
anhtran 0:e9fd5575b10e 508 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
anhtran 0:e9fd5575b10e 509 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
anhtran 0:e9fd5575b10e 510 * Frame buffer stride should be set to a multiple of 32 or 128
anhtran 0:e9fd5575b10e 511 * in accordance with the frame buffer burst transfer mode.
anhtran 0:e9fd5575b10e 512 * @param[in] gr_format : Format of the frame buffer read signal <br />
anhtran 0:e9fd5575b10e 513 * - GRAPHICS_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
anhtran 0:e9fd5575b10e 514 * - GRAPHICS_FORMAT_RGB565 : RGB565 (2byte/px)
anhtran 0:e9fd5575b10e 515 * - GRAPHICS_FORMAT_RGB888 : RGB888 (4byte/px)
anhtran 0:e9fd5575b10e 516 * - GRAPHICS_FORMAT_ARGB8888 : ARGB8888 (4byte/px)
anhtran 0:e9fd5575b10e 517 * - GRAPHICS_FORMAT_CLUT8 : CLUT8 (1byte/px)
anhtran 0:e9fd5575b10e 518 * - GRAPHICS_FORMAT_CLUT4 : CLUT4 (0.5byte/px)
anhtran 0:e9fd5575b10e 519 * - GRAPHICS_FORMAT_CLUT1 : CLUT1 (0,12byte/px)
anhtran 0:e9fd5575b10e 520 * @param[in] wr_rd_swa : frame buffer swap setting <br />
anhtran 0:e9fd5575b10e 521 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
anhtran 0:e9fd5575b10e 522 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
anhtran 0:e9fd5575b10e 523 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
anhtran 0:e9fd5575b10e 524 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
anhtran 0:e9fd5575b10e 525 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
anhtran 0:e9fd5575b10e 526 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
anhtran 0:e9fd5575b10e 527 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
anhtran 0:e9fd5575b10e 528 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
anhtran 0:e9fd5575b10e 529 * @param[in] gr_rect : Graphics display area
anhtran 0:e9fd5575b10e 530 * @param[in] gr_clut : CLUT setup parameter
anhtran 0:e9fd5575b10e 531 * @retval Error code
anhtran 0:e9fd5575b10e 532 */
anhtran 0:e9fd5575b10e 533 graphics_error_t Graphics_Read_Setting (
anhtran 0:e9fd5575b10e 534 graphics_layer_t layer_id,
anhtran 0:e9fd5575b10e 535 void * framebuff,
anhtran 0:e9fd5575b10e 536 unsigned int fb_stride,
anhtran 0:e9fd5575b10e 537 graphics_format_t gr_format,
anhtran 0:e9fd5575b10e 538 wr_rd_swa_t wr_rd_swa,
anhtran 0:e9fd5575b10e 539 rect_t * gr_rect,
anhtran 0:e9fd5575b10e 540 clut_t * gr_clut = 0 );
anhtran 0:e9fd5575b10e 541
anhtran 0:e9fd5575b10e 542 /** Graphics surface read buffer change process
anhtran 0:e9fd5575b10e 543 * @param[in] layer_id : Graphics layer ID <br />
anhtran 0:e9fd5575b10e 544 * - GRAPHICS_LAYER_0 : Layer 0
anhtran 0:e9fd5575b10e 545 * - GRAPHICS_LAYER_1 : Layer 1
anhtran 0:e9fd5575b10e 546 * - GRAPHICS_LAYER_2 : Layer 2
anhtran 0:e9fd5575b10e 547 * - GRAPHICS_LAYER_3 : Layer 3
anhtran 0:e9fd5575b10e 548 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
anhtran 0:e9fd5575b10e 549 * @retval Error code
anhtran 0:e9fd5575b10e 550 */
anhtran 0:e9fd5575b10e 551 graphics_error_t Graphics_Read_Change (
anhtran 0:e9fd5575b10e 552 graphics_layer_t layer_id,
anhtran 0:e9fd5575b10e 553 void * framebuff);
anhtran 0:e9fd5575b10e 554
anhtran 0:e9fd5575b10e 555 /** Video surface write process setting
anhtran 0:e9fd5575b10e 556 * @param[in] video_input_channel : Video input channel <br />
anhtran 0:e9fd5575b10e 557 * If using digital input, this parameter is not referenced. <br />
anhtran 0:e9fd5575b10e 558 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
anhtran 0:e9fd5575b10e 559 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
anhtran 0:e9fd5575b10e 560 * @param[in] col_sys : Analog video signal color system <br />
anhtran 0:e9fd5575b10e 561 * If using digital input, this parameter is not referenced. <br />
anhtran 0:e9fd5575b10e 562 * - COL_SYS_NTSC_358 : NTSC-3.58
anhtran 0:e9fd5575b10e 563 * - COL_SYS_NTSC_443 : NTSC-4.43
anhtran 0:e9fd5575b10e 564 * - COL_SYS_PAL_443 : PAL-4.43
anhtran 0:e9fd5575b10e 565 * - COL_SYS_PAL_M : PAL-M
anhtran 0:e9fd5575b10e 566 * - COL_SYS_PAL_N : PAL-N
anhtran 0:e9fd5575b10e 567 * - COL_SYS_SECAM : SECAM
anhtran 0:e9fd5575b10e 568 * - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz)
anhtran 0:e9fd5575b10e 569 * - COL_SYS_PAL_60 : PAL-60
anhtran 0:e9fd5575b10e 570 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
anhtran 0:e9fd5575b10e 571 * @param[in] fb_stride : Line offset address of the frame buffer[byte] <br />
anhtran 0:e9fd5575b10e 572 * Frame buffer stride should be set to a multiple of 32 or 128
anhtran 0:e9fd5575b10e 573 * in accordance with the frame buffer burst transfer mode.
anhtran 0:e9fd5575b10e 574 * @param[in] video_format : Frame buffer video-signal writing format <br />
anhtran 0:e9fd5575b10e 575 * - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
anhtran 0:e9fd5575b10e 576 * - VIDEO_FORMAT_RGB565 : RGB565 (2byte/px)
anhtran 0:e9fd5575b10e 577 * - VIDEO_FORMAT_RGB888 : RGB888 (4byte/px)
anhtran 0:e9fd5575b10e 578 * @param[in] wr_rd_swa : frame buffer swap setting <br />
anhtran 0:e9fd5575b10e 579 * - WR_RD_WRSWA_NON : Not swapped: 1-2-3-4-5-6-7-8
anhtran 0:e9fd5575b10e 580 * - WR_RD_WRSWA_8BIT : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
anhtran 0:e9fd5575b10e 581 * - WR_RD_WRSWA_16BIT : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
anhtran 0:e9fd5575b10e 582 * - WR_RD_WRSWA_16_8BIT : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
anhtran 0:e9fd5575b10e 583 * - WR_RD_WRSWA_32BIT : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
anhtran 0:e9fd5575b10e 584 * - WR_RD_WRSWA_32_8BIT : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
anhtran 0:e9fd5575b10e 585 * - WR_RD_WRSWA_32_16BIT : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
anhtran 0:e9fd5575b10e 586 * - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
anhtran 0:e9fd5575b10e 587 * @param[in] video_write_buff_vw : Output height[px] <br />
anhtran 0:e9fd5575b10e 588 * - NTSC format : Max height is 480[px]
anhtran 0:e9fd5575b10e 589 * - PAL format : Max height is 520[px]
anhtran 0:e9fd5575b10e 590 * @param[in] video_write_buff_hw : Output width[px] <br />
anhtran 0:e9fd5575b10e 591 * - Max width : 800[px]
anhtran 0:e9fd5575b10e 592 * @param[in] video_adc_vinsel : Input pin control <br />
anhtran 0:e9fd5575b10e 593 * - VIDEO_ADC_VINSEL_VIN1 : VIN1 input
anhtran 0:e9fd5575b10e 594 * - VIDEO_ADC_VINSEL_VIN2 : VIN2 input
anhtran 0:e9fd5575b10e 595 * @retval Error code
anhtran 0:e9fd5575b10e 596 */
anhtran 0:e9fd5575b10e 597 graphics_error_t Video_Write_Setting (
anhtran 0:e9fd5575b10e 598 video_input_channel_t video_input_channel,
anhtran 0:e9fd5575b10e 599 graphics_video_col_sys_t col_sys,
anhtran 0:e9fd5575b10e 600 void * framebuff,
anhtran 0:e9fd5575b10e 601 unsigned int fb_stride,
anhtran 0:e9fd5575b10e 602 video_format_t video_format,
anhtran 0:e9fd5575b10e 603 wr_rd_swa_t wr_rd_swa,
anhtran 0:e9fd5575b10e 604 unsigned short video_write_buff_vw,
anhtran 0:e9fd5575b10e 605 unsigned short video_write_buff_hw,
anhtran 0:e9fd5575b10e 606 video_adc_vinsel_t video_adc_vinsel = VIDEO_ADC_VINSEL_VIN1 );
anhtran 0:e9fd5575b10e 607
anhtran 0:e9fd5575b10e 608 /** Video surface write buffer change process
anhtran 0:e9fd5575b10e 609 * @param[in] video_input_channel : Video input channel <br />
anhtran 0:e9fd5575b10e 610 * - VIDEO_INPUT_CHANNEL_0 : Video channel 0
anhtran 0:e9fd5575b10e 611 * - VIDEO_INPUT_CHANNEL_1 : Video channel 1
anhtran 0:e9fd5575b10e 612 * @param[in] framebuff : Base address of the frame buffer(Not set NULL)
anhtran 0:e9fd5575b10e 613 * @param[in] fb_stride : Line offset address of the frame buffer <br />
anhtran 0:e9fd5575b10e 614 * Frame buffer stride should be set to a multiple of 32 or 128
anhtran 0:e9fd5575b10e 615 * in accordance with the frame buffer burst transfer mode.
anhtran 0:e9fd5575b10e 616 * @retval Error code
anhtran 0:e9fd5575b10e 617 */
anhtran 0:e9fd5575b10e 618 graphics_error_t Video_Write_Change (
anhtran 0:e9fd5575b10e 619 video_input_channel_t video_input_channel,
anhtran 0:e9fd5575b10e 620 void * framebuff,
anhtran 0:e9fd5575b10e 621 uint32_t fb_stride );
anhtran 0:e9fd5575b10e 622
anhtran 0:e9fd5575b10e 623 protected:
anhtran 0:e9fd5575b10e 624 lcd_config_t _lcd_config;
anhtran 0:e9fd5575b10e 625 video_input_sel_t _video_input_sel;
anhtran 0:e9fd5575b10e 626 video_ext_in_config_t _video_ext_in_config;
anhtran 0:e9fd5575b10e 627 #if defined(TARGET_RZ_A2XX)
anhtran 0:e9fd5575b10e 628 video_mipi_param_t _video_mipi_config;
anhtran 0:e9fd5575b10e 629 video_vin_setup_t _video_vin_setup;
anhtran 0:e9fd5575b10e 630 #endif
anhtran 0:e9fd5575b10e 631 };
anhtran 0:e9fd5575b10e 632
anhtran 0:e9fd5575b10e 633
anhtran 0:e9fd5575b10e 634 #endif /* MBED_DISPLAYBASE_H */