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forkd
Fork of LG2 by
Revision 23:12e6183f04d4, committed 2016-02-03
- Comitter:
- Kovalev_D
- Date:
- Wed Feb 03 10:44:42 2016 +0300
- Parent:
- 21:bc8c1cec3da6
- Commit message:
- [thyz
Changed in this revision
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/=copyZ.bat --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/=copyZ.bat Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,3 @@ +d:\Arhiv\WinRAR a -ag_YYYY_MM_DD#NN -r d:\Arhiv\Host\arhiv\Host_m + +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/JLink Regs CM3.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/JLink Regs CM3.txt Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,32 @@ +0: R0: 0x00 +1: R1: 0x01 +2: R2: 0x02 +3: R3: 0x03 +4: R4: 0x04 +5: R5: 0x05 +6: R6: 0x06 +7: R7: 0x07 +8: R8: 0x08 +9: R9: 0x09 +10: R10: 0x0a +11: R11: 0x0b +12: R12: 0x0c +13: R13: 0x0d +14: R14: 0x0e +15: R15: 0x0f +16: XPSR: 0x10 +17: MSP: 0x11 +18: PSP: 0x12 +19: RAZ: 0x13 +20: CFBP: 0x14 +21: APSR: 0x15 +22: EPSR: 0x16 +23: IPSR: 0x17 +24: PRIMASK: 0x18 +25: BASEPRI: 0x19 +26: FAULTMASK: 0x1a +27: CONTROL: 0x1b +28: BASEPRI_MAX: 0x1c +29: IAPSR: 0x1d +30: EAPSR: 0x1e +31: IEPSR: 0x1f
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/JLinkLog.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/JLinkLog.txt Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1242 @@ + +T09B0 000:317 SEGGER J-Link V4.20p Log File (0000ms, 0316ms total) +T09B0 000:317 DLL Compiled: Nov 19 2010 15:55:07 (0000ms, 0316ms total) +T09B0 000:317 Logging started @ 2013-02-26 14:21 (0000ms, 0316ms total) +T09B0 000:317 JLINK_SetWarnOutHandler(...) (0000ms, 0316ms total) +T09B0 000:317 JLINK_OpenEx(...) +Firmware: J-Link ARM-OB STM32 compiled Dec 15 2010 11:30:03 +Hardware: V7.00 +S/N: 20090928 +Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFull returns O.K. (0118ms, 0316ms total) +T09B0 000:435 JLINK_SetErrorOutHandler(...) (0000ms, 0434ms total) +T09B0 000:435 JLINK_ExecCommand("Device = LPC1768", ...) + JLINK_ExecCommand("map ram 0x10000000 - 0x10007FFF", ...) returns 0x00 (0000ms, 0000ms total) + JLINK_AddMirrorAreaEx(Addr = 0x00000000, Size = 0x00000000) (0000ms, 0000ms total) + returns 0x00 (0001ms, 0434ms total) +T09B0 000:437 JLINK_ExecCommand("ProjectFile = "D:\HOST_16\GLD_ver00_00_LPC1768\JLinkSettings.ini"", ...) returns 0x00 (0000ms, 0435ms total) +T09B0 000:438 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x00 (0000ms, 0435ms total) +T09B0 000:438 JLINK_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0001ms, 0435ms total) +T09B0 000:439 JLINK_SetSpeed(10000) (0001ms, 0436ms total) +T09B0 000:440 JLINK_GetHardwareVersion() returns 0x11170 (0000ms, 0437ms total) +T09B0 000:440 JLINK_GetDLLVersion() returns 42016 (0000ms, 0437ms total) +T09B0 000:440 JLINK_GetFirmwareString(...) (0000ms, 0437ms total) +T09B0 000:443 JLINK_GetDLLVersion() returns 42016 (0000ms, 0437ms total) +T09B0 000:443 JLINK_GetCompileDateTime() (0000ms, 0437ms total) +T09B0 000:444 JLINK_GetFirmwareString(...) (0000ms, 0437ms total) +T09B0 000:445 JLINK_GetHardwareVersion() returns 0x11170 (0000ms, 0437ms total) +T09B0 000:448 JLINK_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x9B TIF> >0x9B TIF> >0x1D7 TIF> >0x13A TIF> >0x13A TIF>TPIU fitted. >0x13A TIF>ETM fitted. >0x13A TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0x13A TIF> >0x13A TIF> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) + -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001050) -- CPU_WriteMem(4 bytes @ 0xE0001054) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_ReadMem(4 bytes @ 0x00000000) -- CPU_ReadMem(4 bytes @ 0x00000004) (0147ms, 0437ms total) +T09B0 000:595 JLINK_GetId() >0x33 TIF> returns 0x2BA01477 (0001ms, 0584ms total) +T09B0 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0585ms total) +T09B0 000:598 JLINK_ReadMem (0xE00FF000, 0x0018 Bytes, ...) -- CPU_ReadMem(24 bytes @ 0xE00FF000) -- Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0585ms total) +T09B0 000:599 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) -- Data: 30 C2 2F 41 returns 0x01 (0001ms, 0586ms total) +T09B0 000:600 JLINK_Halt() returns 0x00 (0000ms, 0587ms total) +T09B0 000:600 JLINK_IsHalted() returns TRUE (0000ms, 0587ms total) +T09B0 000:600 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- Data: 03 00 03 00 returns 0x01 (0001ms, 0587ms total) +T09B0 000:601 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0001ms, 0588ms total) +T09B0 000:602 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 0589ms total) +T09B0 000:603 JLINK_ReadMemU32(0xE0002000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0002000) -- Data: 60 02 00 00 returns 0x01 (0000ms, 0590ms total) +T09B0 000:603 JLINK_ReadMemU32(0xE0001000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- Data: 01 00 00 40 returns 0x01 (0001ms, 0590ms total) +T09B0 000:612 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 0591ms total) +T09B0 000:617 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 0591ms total) +T09B0 000:617 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x800 (0000ms, 0591ms total) +T09B0 000:617 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 0591ms total) +T09B0 000:622 JLINK_GetSpeed() returns 0xFA0 (0000ms, 0591ms total) +T09B0 000:624 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) -- Data: 01 00 00 00 returns 0x01 (0001ms, 0591ms total) +T09B0 000:625 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) -- Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0000ms, 0592ms total) +T09B0 000:625 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) -- Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0592ms total) +T09B0 000:626 JLINK_Halt() returns 0x00 (0001ms, 0593ms total) +T09B0 000:627 JLINK_IsHalted() returns TRUE (0000ms, 0594ms total) +T09B0 000:628 JLINK_WriteMem(0x10000000, 0x01D4 Bytes, ...) -- Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(468 bytes @ 0x10000000) returns 0x1D4 (0006ms, 0594ms total) +T09B0 000:634 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(R15, 0x10000044) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0600ms total) +T09B0 000:634 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000001 (0000ms, 0600ms total) +T09B0 000:634 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0007ms, 0600ms total) +T09B0 000:641 JLINK_IsHalted() returns TRUE (0007ms, 0607ms total) +T09B0 000:648 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0607ms total) +T09B0 000:648 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(R15, 0x10000020) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0607ms total) +T09B0 000:648 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0607ms total) +T09B0 000:649 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0608ms total) +T09B0 000:649 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 0608ms total) +T09B0 000:649 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0608ms total) +T09B0 000:654 JLINK_IsHalted() returns TRUE (0008ms, 0613ms total) +T09B0 000:662 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0613ms total) +T09B0 000:662 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(R15, 0x100000E6) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0613ms total) +T09B0 000:662 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 0613ms total) +T09B0 000:662 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0613ms total) +T09B0 000:667 JLINK_IsHalted() returns FALSE (0000ms, 0618ms total) +T09B0 000:717 JLINK_IsHalted() returns FALSE (0000ms, 0618ms total) +T09B0 000:767 JLINK_IsHalted() returns TRUE (0007ms, 0618ms total) +T09B0 000:774 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0618ms total) +T09B0 000:774 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 0618ms total) +T09B0 000:774 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R0, 0x00001000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(R15, 0x10000020) returns 0x00 (0000ms, 0618ms total) +T09B0 000:775 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0618ms total) +T09B0 000:776 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0619ms total) +T09B0 000:776 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0619ms total) +T09B0 000:776 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0619ms total) +T09B0 000:776 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000004 (0000ms, 0619ms total) +T09B0 000:776 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0619ms total) +T09B0 000:781 JLINK_IsHalted() returns TRUE (0008ms, 0624ms total) +T09B0 000:789 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0624ms total) +T09B0 000:789 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R0, 0x00001000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:789 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0624ms total) +T09B0 000:790 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0624ms total) +T09B0 000:790 JLINK_WriteReg(R15, 0x100000E6) returns 0x00 (0000ms, 0624ms total) +T09B0 000:790 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:790 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0624ms total) +T09B0 000:790 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0624ms total) +T09B0 000:790 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0624ms total) +T09B0 000:790 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 0624ms total) +T09B0 000:790 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0624ms total) +T09B0 000:795 JLINK_IsHalted() returns FALSE (0001ms, 0629ms total) +T09B0 000:846 JLINK_IsHalted() returns FALSE (0000ms, 0629ms total) +T09B0 000:896 JLINK_IsHalted() returns TRUE (0007ms, 0629ms total) +T09B0 000:903 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0629ms total) +T09B0 000:903 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 0629ms total) +T09B0 000:903 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R0, 0x00002000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(R15, 0x10000020) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0629ms total) +T09B0 000:904 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 0629ms total) +T09B0 000:904 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0629ms total) +T09B0 000:910 JLINK_IsHalted() returns TRUE (0008ms, 0635ms total) +T09B0 000:918 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0635ms total) +T09B0 000:918 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R0, 0x00002000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(R15, 0x100000E6) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0635ms total) +T09B0 000:918 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 0635ms total) +T09B0 000:918 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0635ms total) +T09B0 000:924 JLINK_IsHalted() returns FALSE (0001ms, 0641ms total) +T09B0 000:975 JLINK_IsHalted() returns FALSE (0000ms, 0641ms total) +T09B0 001:025 JLINK_IsHalted() returns TRUE (0008ms, 0641ms total) +T09B0 001:033 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0641ms total) +T09B0 001:033 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R0, 0x00003000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0641ms total) +T09B0 001:033 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0641ms total) +T09B0 001:034 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(R15, 0x10000020) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0642ms total) +T09B0 001:034 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 0642ms total) +T09B0 001:034 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0642ms total) +T09B0 001:039 JLINK_IsHalted() returns TRUE (0008ms, 0647ms total) +T09B0 001:047 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0647ms total) +T09B0 001:047 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R0, 0x00003000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0647ms total) +T09B0 001:047 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0001ms, 0647ms total) +T09B0 001:048 JLINK_WriteReg(R15, 0x100000E6) returns 0x00 (0000ms, 0648ms total) +T09B0 001:048 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0648ms total) +T09B0 001:048 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0648ms total) +T09B0 001:048 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0648ms total) +T09B0 001:048 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0648ms total) +T09B0 001:048 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 0648ms total) +T09B0 001:048 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0648ms total) +T09B0 001:053 JLINK_IsHalted() returns FALSE (0001ms, 0653ms total) +T09B0 001:104 JLINK_IsHalted() returns FALSE (0000ms, 0653ms total) +T09B0 001:154 JLINK_IsHalted() returns TRUE (0007ms, 0653ms total) +T09B0 001:161 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0653ms total) +T09B0 001:161 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 0653ms total) +T09B0 001:161 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R0, 0x00004000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(R15, 0x10000020) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0653ms total) +T09B0 001:162 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 0653ms total) +T09B0 001:162 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0007ms, 0653ms total) +T09B0 001:169 JLINK_IsHalted() returns TRUE (0007ms, 0660ms total) +T09B0 001:176 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0660ms total) +T09B0 001:176 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R0, 0x00004000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0660ms total) +T09B0 001:176 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0660ms total) +T09B0 001:177 JLINK_WriteReg(R15, 0x100000E6) returns 0x00 (0000ms, 0660ms total) +T09B0 001:177 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:177 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0660ms total) +T09B0 001:177 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0660ms total) +T09B0 001:177 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0660ms total) +T09B0 001:177 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 0660ms total) +T09B0 001:177 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0660ms total) +T09B0 001:182 JLINK_IsHalted() returns FALSE (0001ms, 0665ms total) +T09B0 001:233 JLINK_IsHalted() returns FALSE (0000ms, 0665ms total) +T09B0 001:283 JLINK_IsHalted() returns TRUE (0007ms, 0665ms total) +T09B0 001:290 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0665ms total) +T09B0 001:290 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0000ms, 0665ms total) +T09B0 001:290 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R0, 0x00005000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(R15, 0x10000020) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:291 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0665ms total) +T09B0 001:292 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0665ms total) +T09B0 001:292 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0665ms total) +T09B0 001:292 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 0665ms total) +T09B0 001:292 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0665ms total) +T09B0 001:298 JLINK_IsHalted() returns TRUE (0007ms, 0671ms total) +T09B0 001:305 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0671ms total) +T09B0 001:305 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R0, 0x00005000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0671ms total) +T09B0 001:305 JLINK_WriteReg(R15, 0x100000E6) returns 0x00 (0001ms, 0671ms total) +T09B0 001:306 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0672ms total) +T09B0 001:306 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0672ms total) +T09B0 001:306 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0672ms total) +T09B0 001:306 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0672ms total) +T09B0 001:306 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 0672ms total) +T09B0 001:306 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 0672ms total) +T09B0 001:311 JLINK_IsHalted() returns FALSE (0001ms, 0677ms total) +T09B0 001:362 JLINK_IsHalted() returns FALSE (0000ms, 0677ms total) +T09B0 001:412 JLINK_IsHalted() returns TRUE (0007ms, 0677ms total) +T09B0 001:419 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0677ms total) +T09B0 001:419 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 0677ms total) +T09B0 001:419 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R0, 0x00000001) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R1, 0x00001000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:420 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_WriteReg(R15, 0x100000A2) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0677ms total) +T09B0 001:421 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 0677ms total) +T09B0 001:421 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0677ms total) +T09B0 001:427 JLINK_IsHalted() returns TRUE (0007ms, 0683ms total) +T09B0 001:434 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0683ms total) +T09B0 001:434 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 0683ms total) +T09B0 001:434 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0683ms total) +T09B0 001:490 JLINK_WriteMem(0x10000000, 0x01D4 Bytes, ...) -- Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(468 bytes @ 0x10000000) returns 0x1D4 (0005ms, 0683ms total) +T09B0 001:495 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 0688ms total) +T09B0 001:495 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 0688ms total) +T09B0 001:495 JLINK_WriteReg(R2, 0x00000002) returns 0x00 (0000ms, 0688ms total) +T09B0 001:495 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0688ms total) +T09B0 001:496 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(R15, 0x10000044) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0689ms total) +T09B0 001:496 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000000F (0000ms, 0689ms total) +T09B0 001:496 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0689ms total) +T09B0 001:502 JLINK_IsHalted() returns TRUE (0008ms, 0695ms total) +T09B0 001:510 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0695ms total) +T09B0 001:510 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 0695ms total) +T09B0 001:510 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0695ms total) +T09B0 001:510 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 00 20 00 10 DD 01 00 00 E5 01 00 00 E7 01 00 00 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0695ms total) +T09B0 001:521 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0706ms total) +T09B0 001:521 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 0706ms total) +T09B0 001:522 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0707ms total) +T09B0 001:522 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 0707ms total) +T09B0 001:522 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0707ms total) +T09B0 001:528 JLINK_IsHalted() returns FALSE (0000ms, 0713ms total) +T09B0 001:578 JLINK_IsHalted() returns TRUE (0007ms, 0713ms total) +T09B0 001:585 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0713ms total) +T09B0 001:585 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 0713ms total) +T09B0 001:585 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0713ms total) +T09B0 001:586 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 4F F0 55 00 19 49 C1 F8 AC 00 00 BF 23 48 00 68 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0713ms total) +T09B0 001:597 JLINK_WriteReg(R0, 0x00000400) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:597 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0724ms total) +T09B0 001:598 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000011 (0000ms, 0724ms total) +T09B0 001:598 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0724ms total) +T09B0 001:604 JLINK_IsHalted() returns FALSE (0000ms, 0730ms total) +T09B0 001:654 JLINK_IsHalted() returns TRUE (0007ms, 0730ms total) +T09B0 001:661 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0730ms total) +T09B0 001:661 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 0730ms total) +T09B0 001:661 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0730ms total) +T09B0 001:662 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 08 60 4F F0 00 00 4F F0 40 21 C8 60 4F F0 3F 00 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0730ms total) +T09B0 001:673 JLINK_WriteReg(R0, 0x00000800) returns 0x00 (0000ms, 0741ms total) +T09B0 001:673 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0741ms total) +T09B0 001:673 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0741ms total) +T09B0 001:674 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 0741ms total) +T09B0 001:674 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0741ms total) +T09B0 001:680 JLINK_IsHalted() returns FALSE (0001ms, 0747ms total) +T09B0 001:731 JLINK_IsHalted() returns TRUE (0007ms, 0747ms total) +T09B0 001:738 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0747ms total) +T09B0 001:738 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 0747ms total) +T09B0 001:738 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0747ms total) +T09B0 001:739 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 00 B5 04 20 73 49 08 60 6B 48 00 68 00 F0 07 02 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0747ms total) +T09B0 001:750 JLINK_WriteReg(R0, 0x00000C00) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0758ms total) +T09B0 001:750 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 0758ms total) +T09B0 001:751 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0759ms total) +T09B0 001:751 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 0759ms total) +T09B0 001:751 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0759ms total) +T09B0 001:757 JLINK_IsHalted() returns FALSE (0001ms, 0765ms total) +T09B0 001:808 JLINK_IsHalted() returns TRUE (0007ms, 0765ms total) +T09B0 001:815 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0765ms total) +T09B0 001:815 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 0765ms total) +T09B0 001:815 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0765ms total) +T09B0 001:816 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 08 61 01 20 7B 49 08 60 00 BF 00 BF 85 48 00 68 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0765ms total) +T09B0 001:827 JLINK_WriteReg(R0, 0x00001000) returns 0x00 (0000ms, 0776ms total) +T09B0 001:827 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0776ms total) +T09B0 001:827 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0776ms total) +T09B0 001:827 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0776ms total) +T09B0 001:827 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0776ms total) +T09B0 001:827 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0776ms total) +T09B0 001:827 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0776ms total) +T09B0 001:827 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0776ms total) +T09B0 001:828 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0777ms total) +T09B0 001:828 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000014 (0000ms, 0777ms total) +T09B0 001:828 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0777ms total) +T09B0 001:834 JLINK_IsHalted() returns FALSE (0001ms, 0783ms total) +T09B0 001:885 JLINK_IsHalted() returns TRUE (0007ms, 0783ms total) +T09B0 001:892 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0783ms total) +T09B0 001:892 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 0783ms total) +T09B0 001:892 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0783ms total) +T09B0 001:893 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 00 F4 00 70 B0 F5 00 7F 06 D0 25 48 00 68 00 F4 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0783ms total) +T09B0 001:904 JLINK_WriteReg(R0, 0x00001400) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0794ms total) +T09B0 001:904 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0001ms, 0794ms total) +T09B0 001:905 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0795ms total) +T09B0 001:905 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 0795ms total) +T09B0 001:905 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0795ms total) +T09B0 001:911 JLINK_IsHalted() returns FALSE (0001ms, 0801ms total) +T09B0 001:962 JLINK_IsHalted() returns TRUE (0007ms, 0801ms total) +T09B0 001:969 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0801ms total) +T09B0 001:969 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 0801ms total) +T09B0 001:969 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0801ms total) +T09B0 001:970 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 31 49 48 66 08 46 40 6E 46 F6 2B 01 48 43 C0 0B ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0801ms total) +T09B0 001:981 JLINK_WriteReg(R0, 0x00001800) returns 0x00 (0000ms, 0812ms total) +T09B0 001:981 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0812ms total) +T09B0 001:981 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0812ms total) +T09B0 001:981 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0812ms total) +T09B0 001:982 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0813ms total) +T09B0 001:982 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 0813ms total) +T09B0 001:982 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0813ms total) +T09B0 001:988 JLINK_IsHalted() returns FALSE (0001ms, 0819ms total) +T09B0 002:039 JLINK_IsHalted() returns TRUE (0008ms, 0819ms total) +T09B0 002:047 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0819ms total) +T09B0 002:047 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 0819ms total) +T09B0 002:047 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0819ms total) +T09B0 002:047 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: C8 65 00 20 4F 49 08 60 54 48 C0 6D 51 49 09 68 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0819ms total) +T09B0 002:058 JLINK_WriteReg(R0, 0x00001C00) returns 0x00 (0000ms, 0830ms total) +T09B0 002:058 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0830ms total) +T09B0 002:058 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0830ms total) +T09B0 002:058 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0830ms total) +T09B0 002:059 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000017 (0000ms, 0830ms total) +T09B0 002:059 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0830ms total) +T09B0 002:065 JLINK_IsHalted() returns FALSE (0001ms, 0836ms total) +T09B0 002:116 JLINK_IsHalted() returns TRUE (0007ms, 0836ms total) +T09B0 002:123 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0836ms total) +T09B0 002:123 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 0836ms total) +T09B0 002:123 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0836ms total) +T09B0 002:124 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 1B E0 12 F0 01 0F 07 D1 1C 68 C4 F3 07 24 89 4D ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0836ms total) +T09B0 002:135 JLINK_WriteReg(R0, 0x00002000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0847ms total) +T09B0 002:135 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0001ms, 0847ms total) +T09B0 002:136 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0848ms total) +T09B0 002:136 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0848ms total) +T09B0 002:136 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0848ms total) +T09B0 002:136 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0848ms total) +T09B0 002:136 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0848ms total) +T09B0 002:136 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 0848ms total) +T09B0 002:136 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0848ms total) +T09B0 002:142 JLINK_IsHalted() returns FALSE (0000ms, 0854ms total) +T09B0 002:192 JLINK_IsHalted() returns TRUE (0007ms, 0854ms total) +T09B0 002:199 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0854ms total) +T09B0 002:199 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 0854ms total) +T09B0 002:199 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0854ms total) +T09B0 002:200 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 10 49 08 60 4F F0 00 00 06 49 C1 F8 48 01 70 47 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0854ms total) +T09B0 002:211 JLINK_WriteReg(R0, 0x00002400) returns 0x00 (0000ms, 0865ms total) +T09B0 002:211 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0865ms total) +T09B0 002:211 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0865ms total) +T09B0 002:211 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0865ms total) +T09B0 002:211 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 0865ms total) +T09B0 002:212 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0866ms total) +T09B0 002:212 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 0866ms total) +T09B0 002:212 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0866ms total) +T09B0 002:218 JLINK_IsHalted() returns FALSE (0001ms, 0872ms total) +T09B0 002:269 JLINK_IsHalted() returns TRUE (0007ms, 0872ms total) +T09B0 002:276 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0872ms total) +T09B0 002:276 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 0872ms total) +T09B0 002:276 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0872ms total) +T09B0 002:277 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 01 27 37 60 6F F0 00 46 0A E0 00 28 07 DA 83 42 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0872ms total) +T09B0 002:288 JLINK_WriteReg(R0, 0x00002800) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0883ms total) +T09B0 002:288 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 0883ms total) +T09B0 002:289 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0884ms total) +T09B0 002:289 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000001A (0000ms, 0884ms total) +T09B0 002:289 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0884ms total) +T09B0 002:295 JLINK_IsHalted() returns FALSE (0001ms, 0890ms total) +T09B0 002:346 JLINK_IsHalted() returns TRUE (0007ms, 0890ms total) +T09B0 002:353 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0890ms total) +T09B0 002:353 JLINK_ClrBPEx(BPHandle = 0x0000001A) returns 0x00 (0000ms, 0890ms total) +T09B0 002:353 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0890ms total) +T09B0 002:354 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: E5 FE BD E8 F0 87 2D E9 F0 47 E4 48 05 68 E4 48 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0890ms total) +T09B0 002:365 JLINK_WriteReg(R0, 0x00002C00) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0901ms total) +T09B0 002:365 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 0901ms total) +T09B0 002:366 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0902ms total) +T09B0 002:366 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000001B (0000ms, 0902ms total) +T09B0 002:366 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0902ms total) +T09B0 002:372 JLINK_IsHalted() returns FALSE (0001ms, 0908ms total) +T09B0 002:423 JLINK_IsHalted() returns TRUE (0007ms, 0908ms total) +T09B0 002:430 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0908ms total) +T09B0 002:430 JLINK_ClrBPEx(BPHandle = 0x0000001B) returns 0x00 (0000ms, 0908ms total) +T09B0 002:430 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0908ms total) +T09B0 002:431 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 0C 48 00 68 20 44 01 90 0B 48 00 68 20 44 00 90 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0908ms total) +T09B0 002:442 JLINK_WriteReg(R0, 0x00003000) returns 0x00 (0000ms, 0919ms total) +T09B0 002:442 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0919ms total) +T09B0 002:442 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0919ms total) +T09B0 002:442 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0919ms total) +T09B0 002:442 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 0919ms total) +T09B0 002:443 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0920ms total) +T09B0 002:443 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000001C (0000ms, 0920ms total) +T09B0 002:443 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0920ms total) +T09B0 002:449 JLINK_IsHalted() returns FALSE (0001ms, 0926ms total) +T09B0 002:500 JLINK_IsHalted() returns TRUE (0007ms, 0926ms total) +T09B0 002:508 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0926ms total) +T09B0 002:508 JLINK_ClrBPEx(BPHandle = 0x0000001C) returns 0x00 (0000ms, 0926ms total) +T09B0 002:508 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0926ms total) +T09B0 002:508 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 10 BD 27 48 00 68 38 B9 00 20 1B 49 08 60 1C 49 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0926ms total) +T09B0 002:519 JLINK_WriteReg(R0, 0x00003400) returns 0x00 (0000ms, 0937ms total) +T09B0 002:519 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0937ms total) +T09B0 002:519 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0937ms total) +T09B0 002:519 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0937ms total) +T09B0 002:519 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0937ms total) +T09B0 002:519 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 0937ms total) +T09B0 002:520 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0938ms total) +T09B0 002:520 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000001D (0000ms, 0938ms total) +T09B0 002:520 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0938ms total) +T09B0 002:526 JLINK_IsHalted() returns FALSE (0000ms, 0944ms total) +T09B0 002:576 JLINK_IsHalted() returns TRUE (0008ms, 0944ms total) +T09B0 002:584 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0944ms total) +T09B0 002:584 JLINK_ClrBPEx(BPHandle = 0x0000001D) returns 0x00 (0000ms, 0944ms total) +T09B0 002:584 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0944ms total) +T09B0 002:584 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 40 1C 3A 4A 10 60 3E 48 50 F8 21 00 BD E8 F8 8F ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0012ms, 0944ms total) +T09B0 002:596 JLINK_WriteReg(R0, 0x00003800) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0956ms total) +T09B0 002:596 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000001E (0000ms, 0956ms total) +T09B0 002:596 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0956ms total) +T09B0 002:602 JLINK_IsHalted() returns FALSE (0001ms, 0962ms total) +T09B0 002:653 JLINK_IsHalted() returns TRUE (0007ms, 0962ms total) +T09B0 002:660 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 0962ms total) +T09B0 002:660 JLINK_ClrBPEx(BPHandle = 0x0000001E) returns 0x00 (0000ms, 0962ms total) +T09B0 002:660 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0962ms total) +T09B0 002:661 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 06 29 0A D1 01 21 99 4A 11 60 10 21 99 4A 11 60 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0962ms total) +T09B0 002:672 JLINK_WriteReg(R0, 0x00003C00) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0973ms total) +T09B0 002:672 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0001ms, 0973ms total) +T09B0 002:673 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0974ms total) +T09B0 002:673 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0974ms total) +T09B0 002:673 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0974ms total) +T09B0 002:673 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0974ms total) +T09B0 002:673 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0974ms total) +T09B0 002:673 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000001F (0000ms, 0974ms total) +T09B0 002:673 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0974ms total) +T09B0 002:679 JLINK_IsHalted() returns FALSE (0000ms, 0980ms total) +T09B0 002:729 JLINK_IsHalted() returns TRUE (0007ms, 0980ms total) +T09B0 002:736 JLINK_ReadReg(R15) returns 0x10000000 (0001ms, 0980ms total) +T09B0 002:737 JLINK_ClrBPEx(BPHandle = 0x0000001F) returns 0x00 (0000ms, 0981ms total) +T09B0 002:737 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0981ms total) +T09B0 002:737 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 00 20 9C 49 08 60 9C 4A 10 60 50 60 03 E0 10 21 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 0981ms total) +T09B0 002:748 JLINK_WriteReg(R0, 0x00004000) returns 0x00 (0000ms, 0992ms total) +T09B0 002:748 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0992ms total) +T09B0 002:748 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 0992ms total) +T09B0 002:748 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0992ms total) +T09B0 002:748 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0992ms total) +T09B0 002:748 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 0992ms total) +T09B0 002:749 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0993ms total) +T09B0 002:749 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000020 (0000ms, 0993ms total) +T09B0 002:749 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 0993ms total) +T09B0 002:755 JLINK_IsHalted() returns FALSE (0000ms, 0999ms total) +T09B0 002:805 JLINK_IsHalted() returns TRUE (0007ms, 0999ms total) +T09B0 002:812 JLINK_ReadReg(R15) returns 0x10000000 (0001ms, 0999ms total) +T09B0 002:813 JLINK_ClrBPEx(BPHandle = 0x00000020) returns 0x00 (0000ms, 1000ms total) +T09B0 002:813 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1000ms total) +T09B0 002:813 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 88 60 08 61 4F F4 80 20 29 49 08 60 22 48 01 F1 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 1000ms total) +T09B0 002:824 JLINK_WriteReg(R0, 0x00004400) returns 0x00 (0001ms, 1011ms total) +T09B0 002:825 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1012ms total) +T09B0 002:825 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000021 (0000ms, 1012ms total) +T09B0 002:825 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1012ms total) +T09B0 002:831 JLINK_IsHalted() returns FALSE (0001ms, 1018ms total) +T09B0 002:882 JLINK_IsHalted() returns TRUE (0008ms, 1018ms total) +T09B0 002:890 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1018ms total) +T09B0 002:890 JLINK_ClrBPEx(BPHandle = 0x00000021) returns 0x00 (0000ms, 1018ms total) +T09B0 002:890 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1018ms total) +T09B0 002:890 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: FF 72 B2 EB 51 5F 08 BF 40 F0 02 00 01 28 08 BF ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 1018ms total) +T09B0 002:902 JLINK_WriteReg(R0, 0x00004800) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1030ms total) +T09B0 002:902 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000022 (0000ms, 1030ms total) +T09B0 002:902 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1030ms total) +T09B0 002:908 JLINK_IsHalted() returns FALSE (0001ms, 1036ms total) +T09B0 002:959 JLINK_IsHalted() returns TRUE (0007ms, 1036ms total) +T09B0 002:966 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1036ms total) +T09B0 002:966 JLINK_ClrBPEx(BPHandle = 0x00000022) returns 0x00 (0000ms, 1036ms total) +T09B0 002:966 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1036ms total) +T09B0 002:967 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 31 46 00 F0 61 FC 22 46 3B 46 00 F0 67 FD 07 46 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 1036ms total) +T09B0 002:978 JLINK_WriteReg(R0, 0x00004C00) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 1047ms total) +T09B0 002:978 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:979 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1047ms total) +T09B0 002:979 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1047ms total) +T09B0 002:979 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1047ms total) +T09B0 002:979 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000023 (0000ms, 1047ms total) +T09B0 002:979 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1047ms total) +T09B0 002:985 JLINK_IsHalted() returns FALSE (0000ms, 1053ms total) +T09B0 003:035 JLINK_IsHalted() returns TRUE (0007ms, 1053ms total) +T09B0 003:042 JLINK_ReadReg(R15) returns 0x10000000 (0001ms, 1053ms total) +T09B0 003:043 JLINK_ClrBPEx(BPHandle = 0x00000023) returns 0x00 (0000ms, 1054ms total) +T09B0 003:043 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1054ms total) +T09B0 003:043 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 70 47 00 00 10 B5 91 EA 03 0F 48 BF 83 F0 00 43 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 1054ms total) +T09B0 003:054 JLINK_WriteReg(R0, 0x00005000) returns 0x00 (0000ms, 1065ms total) +T09B0 003:054 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 1065ms total) +T09B0 003:055 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1066ms total) +T09B0 003:055 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000024 (0000ms, 1066ms total) +T09B0 003:055 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1066ms total) +T09B0 003:061 JLINK_IsHalted() returns FALSE (0001ms, 1072ms total) +T09B0 003:112 JLINK_IsHalted() returns TRUE (0007ms, 1072ms total) +T09B0 003:119 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1072ms total) +T09B0 003:119 JLINK_ClrBPEx(BPHandle = 0x00000024) returns 0x00 (0000ms, 1072ms total) +T09B0 003:119 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1072ms total) +T09B0 003:120 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 86 85 85 84 84 83 83 82 82 81 81 80 00 00 FF 07 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0011ms, 1072ms total) +T09B0 003:131 JLINK_WriteReg(R0, 0x00005400) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1083ms total) +T09B0 003:131 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 1083ms total) +T09B0 003:132 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1084ms total) +T09B0 003:132 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000025 (0000ms, 1084ms total) +T09B0 003:132 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1084ms total) +T09B0 003:138 JLINK_IsHalted() returns FALSE (0001ms, 1090ms total) +T09B0 003:189 JLINK_IsHalted() returns TRUE (0007ms, 1090ms total) +T09B0 003:196 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1090ms total) +T09B0 003:196 JLINK_ClrBPEx(BPHandle = 0x00000025) returns 0x00 (0000ms, 1090ms total) +T09B0 003:196 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1090ms total) +T09B0 003:197 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: A4 1A A4 1E D2 F1 20 03 91 40 30 FA 03 F3 19 43 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0012ms, 1090ms total) +T09B0 003:209 JLINK_WriteReg(R0, 0x00005800) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1102ms total) +T09B0 003:209 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000026 (0000ms, 1102ms total) +T09B0 003:209 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1102ms total) +T09B0 003:215 JLINK_IsHalted() returns FALSE (0001ms, 1108ms total) +T09B0 003:266 JLINK_IsHalted() returns TRUE (0007ms, 1108ms total) +T09B0 003:273 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1108ms total) +T09B0 003:273 JLINK_ClrBPEx(BPHandle = 0x00000026) returns 0x00 (0000ms, 1108ms total) +T09B0 003:273 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1108ms total) +T09B0 003:274 JLINK_WriteMem(0x100001F4, 0x0400 Bytes, ...) -- Data: 70 47 80 F0 00 40 90 EA 01 0F 7F F5 84 AE 81 F0 ... -- CPU_WriteMem(1024 bytes @ 0x100001F4) returns 0x400 (0012ms, 1108ms total) +T09B0 003:286 JLINK_WriteReg(R0, 0x00005C00) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R1, 0x000003B4) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(R15, 0x1000012C) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1120ms total) +T09B0 003:286 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000027 (0000ms, 1120ms total) +T09B0 003:286 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1120ms total) +T09B0 003:292 JLINK_IsHalted() returns FALSE (0001ms, 1126ms total) +T09B0 003:343 JLINK_IsHalted() returns TRUE (0007ms, 1126ms total) +T09B0 003:350 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1126ms total) +T09B0 003:350 JLINK_ClrBPEx(BPHandle = 0x00000027) returns 0x00 (0001ms, 1126ms total) +T09B0 003:351 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R0, 0x00000002) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R1, 0x000003B4) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R2, 0x100001F4) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(R15, 0x100000A2) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1127ms total) +T09B0 003:351 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000028 (0000ms, 1127ms total) +T09B0 003:351 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1127ms total) +T09B0 003:357 JLINK_IsHalted() returns TRUE (0008ms, 1133ms total) +T09B0 003:365 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1133ms total) +T09B0 003:365 JLINK_ClrBPEx(BPHandle = 0x00000028) returns 0x00 (0000ms, 1133ms total) +T09B0 003:365 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1133ms total) +T09B0 003:419 JLINK_WriteMem(0x10000000, 0x01D4 Bytes, ...) -- Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(468 bytes @ 0x10000000) returns 0x1D4 (0006ms, 1133ms total) +T09B0 003:425 JLINK_WriteReg(R0, 0x00000000) returns 0x00 (0000ms, 1139ms total) +T09B0 003:425 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 1139ms total) +T09B0 003:425 JLINK_WriteReg(R2, 0x00000003) returns 0x00 (0000ms, 1139ms total) +T09B0 003:425 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1139ms total) +T09B0 003:425 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1139ms total) +T09B0 003:425 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1139ms total) +T09B0 003:425 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1139ms total) +T09B0 003:425 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1139ms total) +T09B0 003:426 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(R15, 0x10000044) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1140ms total) +T09B0 003:426 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x00000029 (0000ms, 1140ms total) +T09B0 003:426 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0005ms, 1140ms total) +T09B0 003:431 JLINK_IsHalted() returns TRUE (0008ms, 1145ms total) +T09B0 003:439 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1145ms total) +T09B0 003:439 JLINK_ClrBPEx(BPHandle = 0x00000029) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R0, 0xFFFFFFFF) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R1, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R2, 0x00005FB4) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(R15, 0x10000002) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1145ms total) +T09B0 003:439 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000002A (0001ms, 1145ms total) +T09B0 003:440 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1146ms total) +T09B0 003:446 JLINK_IsHalted() returns FALSE (0000ms, 1152ms total) +T09B0 003:496 JLINK_IsHalted() returns FALSE (0000ms, 1152ms total) +T09B0 003:546 JLINK_IsHalted() returns FALSE (0000ms, 1152ms total) +T09B0 003:596 JLINK_IsHalted() returns FALSE (0000ms, 1152ms total) +T09B0 003:646 JLINK_IsHalted() returns FALSE (0000ms, 1152ms total) +T09B0 003:696 JLINK_IsHalted() returns FALSE (0000ms, 1152ms total) +T09B0 003:746 JLINK_IsHalted() returns FALSE (0000ms, 1152ms total) +T09B0 003:796 JLINK_IsHalted() returns TRUE (0007ms, 1152ms total) +T09B0 003:803 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1152ms total) +T09B0 003:803 JLINK_ClrBPEx(BPHandle = 0x0000002A) returns 0x00 (0000ms, 1152ms total) +T09B0 003:803 JLINK_ReadReg(R0) returns 0x89991777 (0001ms, 1152ms total) +T09B0 003:806 JLINK_WriteReg(R0, 0x00000003) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R1, 0x00000000) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R2, 0x00005FB4) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R9, 0x100001CC) returns 0x00 (0000ms, 1153ms total) +T09B0 003:806 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 1153ms total) +T09B0 003:807 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(R13, 0x10000800) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(R14, 0x10000001) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(R15, 0x100000A2) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(MSP, 0x10000800) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(PSP, 0x10000800) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1154ms total) +T09B0 003:807 JLINK_SetBPEx(Addr = 0x10000000, Type = 0xFFFFFFF2) returns 0x0000002B (0000ms, 1154ms total) +T09B0 003:807 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0006ms, 1154ms total) +T09B0 003:813 JLINK_IsHalted() returns TRUE (0007ms, 1160ms total) +T09B0 003:820 JLINK_ReadReg(R15) returns 0x10000000 (0000ms, 1160ms total) +T09B0 003:820 JLINK_ClrBPEx(BPHandle = 0x0000002B) returns 0x00 (0000ms, 1160ms total) +T09B0 003:820 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1160ms total) +T09B0 003:872 JLINK_WriteU32(0xE000EDFC, 0x00000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1160ms total) +T09B0 003:873 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_HALT_WP (0000ms, 1161ms total) +T09B0 003:873 JLINK_Reset() >0x108 TIF>Found SWD-DP with ID 0x2BA01477 >0x33 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x35 TIF> >0x33 TIF> >0x33 TIF> >0x9B TIF> >0x9B TIF> >0x1D7 TIF> >0x13A TIF> >0x13A TIF>TPIU fitted. >0x13A TIF>ETM fitted. >0x13A TIF> FPUnit: 6 code (BP) slots and 2 literal slots >0x13A TIF> >0x13A TIF> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) + -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C)CPU did not halt after bootloader. -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0x00000000) -- CPU_ReadMem(4 bytes @ 0x00000004) (2151ms, 1161ms total) +T09B0 006:026 JLINK_Close() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) (0039ms, 3312ms total)
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/JLinkSettings.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/JLinkSettings.ini Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,23 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ADUC7020X62" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +[SWO] +SWOLogFile=""
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA - êîïèÿ.uvgui.Äìèòðèé --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA - êîïèÿ.uvgui.Äìèòðèé Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1360 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_gui.xsd"> + + <SchemaVersion>-5.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <ViewPool/> + + <SECTreeCtrl> + <View> + <WinId>38003</WinId> + <ViewName>Registers</ViewName> + <TableColWidths>115 115</TableColWidths> + </View> + <View> + <WinId>346</WinId> + <ViewName>Code Coverage</ViewName> + <TableColWidths>1010 160</TableColWidths> + </View> + <View> + <WinId>204</WinId> + <ViewName>Performance Analyzer</ViewName> + <TableColWidths>1170</TableColWidths> + </View> + </SECTreeCtrl> + + <TreeListPane> + <View> + <WinId>1506</WinId> + <ViewName>Symbols</ViewName> + <UserString></UserString> + <TableColWidths>80 80 80</TableColWidths> + </View> + <View> + <WinId>1936</WinId> + <ViewName>Watch 1</ViewName> + <UserString></UserString> + <TableColWidths>80 80 80</TableColWidths> + </View> + <View> + <WinId>1937</WinId> + <ViewName>Watch 2</ViewName> + <UserString></UserString> + <TableColWidths>80 80 80</TableColWidths> + </View> + <View> + <WinId>1935</WinId> + <ViewName>Call Stack + Locals</ViewName> + <UserString></UserString> + <TableColWidths>80 80 80</TableColWidths> + </View> + <View> + <WinId>2506</WinId> + <ViewName>Trace Data</ViewName> + <UserString></UserString> + <TableColWidths>75 135 130 95 70 230 200 150</TableColWidths> + </View> + </TreeListPane> + + <WindowSettings> + <LogicAnalizer> + <ShowLACursor>1</ShowLACursor> + <ShowSignalInfo>1</ShowSignalInfo> + <ShowCycles>0</ShowCycles> + <LeftSideBarSize>0</LeftSideBarSize> + <TimeBaseIndex>-1</TimeBaseIndex> + </LogicAnalizer> + </WindowSettings> + + <WinLayoutEx> + <sActiveDebugView></sActiveDebugView> + <WindowPosition> + <length>44</length> + <flags>2</flags> + <showCmd>3</showCmd> + <MinPosition> + <xPos>-1</xPos> + <yPos>-1</yPos> + </MinPosition> + <MaxPosition> + <xPos>-1</xPos> + <yPos>-1</yPos> + </MaxPosition> + <NormalPosition> + <Top>94</Top> + <Left>1970</Left> + <Right>3172</Right> + <Bottom>1009</Bottom> + </NormalPosition> + </WindowPosition> + <MDIClientArea> + <RegID>0</RegID> + <MDITabState> + <Len>245</Len> + <Data>01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000001000000000000000100000030433A5C55736572735CC4ECE8F2F0E8E95C4465736B746F705C686F73745C536F757263655C4170705C766962726F2E630000000007766962726F2E6300000000FFDC7800FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD50001000000000000000200000074080000B7000000800C000099030000</Data> + </MDITabState> + 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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA.plg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA.plg Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,64 @@ +<html> +<body> +<pre> +<h1>µVision Build Log</h1> +<h2>Project:</h2> +C:\Documents and Settings\PowerARM\×ÀÃæ\LPC1768²âÊÔ³ÌÐò\DMA\LandTiger_DMA.uvproj +Project File Date: 05/12/2010 + +<h2>Output:</h2> +Build target 'LandTiger_DMA' +compiling core_cm3.c... +compiling system_LPC17xx.c... +assembling startup_LPC17xx.s... +compiling dma.c... +Source\App\dma.c(82): error: #20: identifier "FALSE" is undefined +Source\App\dma.c: return ( FALSE ); +Source\App\dma.c: ^ +Source\App\dma.c(89): error: #20: identifier "TRUE" is undefined +Source\App\dma.c: return (TRUE); +Source\App\dma.c: ^ +Source\App\dma.c: Source\App\dma.c: 0 warnings, 2 errors +compiling main.c... +Source\App\main.c(19): error: #5: cannot open source input file "uart.h": No such file or directory +Source\App\main.c: #include "uart.h" +Source\App\main.c: ^ +Source\App\main.c: Source\App\main.c: 0 warnings, 1 error +Target not created +Build target 'LandTiger_DMA' +compiling dma.c... +Source\App\dma.c(82): error: #20: identifier "FALSE" is undefined +Source\App\dma.c: return ( FALSE ); +Source\App\dma.c: ^ +Source\App\dma.c(89): error: #20: identifier "TRUE" is undefined +Source\App\dma.c: return (TRUE); +Source\App\dma.c: ^ +Source\App\dma.c: Source\App\dma.c: 0 warnings, 2 errors +compiling main.c... +Target not created +Build target 'LandTiger_DMA' +compiling dma.c... +Source\App\dma.c(82): error: #20: identifier "FALSE" is undefined +Source\App\dma.c: return ( FALSE ); +Source\App\dma.c: ^ +Source\App\dma.c(89): error: #20: identifier "TRUE" is undefined +Source\App\dma.c: return (TRUE); +Source\App\dma.c: ^ +Source\App\dma.c: Source\App\dma.c: 0 warnings, 2 errors +compiling main.c... +Target not created +Build target 'LandTiger_DMA' +compiling dma.c... +Source\App\dma.c(82): error: #20: identifier "FALSE" is undefined +Source\App\dma.c: return ( FALSE ); +Source\App\dma.c: ^ +Source\App\dma.c(89): error: #20: identifier "TRUE" is undefined +Source\App\dma.c: return (TRUE); +Source\App\dma.c: ^ +Source\App\dma.c: Source\App\dma.c: 0 warnings, 2 errors +Target not created +Build target 'LandTiger_DMA' +compiling dma.c... +linking... +Program Size: Code=1252 RO-data=228 RW-data=12 ZI-data=612 +".\Obj\LandTiger_DMA.axf" - 0 Error(s), 0 Warning(s).
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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA.uvgui.Igor --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA.uvgui.Igor Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1405 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_gui.xsd"> + + <SchemaVersion>1.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <ViewPool/> + + <SECTreeCtrl> + <View> + <WinId>38003</WinId> + <ViewName>Registers</ViewName> + <TableColWidths>115 91</TableColWidths> + </View> + <View> + <WinId>1506</WinId> + <ViewName>Symbols</ViewName> + <TableColWidths>62 22 42</TableColWidths> + </View> + <View> + <WinId>1935</WinId> + <ViewName>Locals</ViewName> + <TableColWidths>822 120</TableColWidths> + </View> + <View> + <WinId>1936</WinId> + <ViewName>Watch 1</ViewName> + <TableColWidths>822 120</TableColWidths> + </View> + <View> + <WinId>1937</WinId> + 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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA.uvgui.admin --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA.uvgui.admin Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1418 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_gui.xsd"> + + <SchemaVersion>-4.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <ViewPool/> + + <SECTreeCtrl> + <View> + <WinId>38003</WinId> + <ViewName>Registers</ViewName> + <TableColWidths>115 93</TableColWidths> + </View> + <View> + <WinId>346</WinId> + <ViewName>Code Coverage</ViewName> + <TableColWidths>597 160</TableColWidths> + </View> + <View> + <WinId>204</WinId> + <ViewName>Performance Analyzer</ViewName> + <TableColWidths>757</TableColWidths> + </View> + </SECTreeCtrl> + + <TreeListPane> + <View> + <WinId>1506</WinId> + <ViewName>Symbols</ViewName> + <UserString></UserString> + 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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA.uvgui.Èãîðü --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA.uvgui.Èãîðü Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1385 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_gui.xsd"> + + <SchemaVersion>-5.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <ViewPool/> + + <SECTreeCtrl> + <View> + <WinId>38003</WinId> + <ViewName>Registers</ViewName> + <TableColWidths>115 275</TableColWidths> + </View> + <View> + <WinId>346</WinId> + <ViewName>Code Coverage</ViewName> + <TableColWidths>370 160</TableColWidths> + </View> + <View> + <WinId>204</WinId> + <ViewName>Performance Analyzer</ViewName> + <TableColWidths>530</TableColWidths> + </View> + </SECTreeCtrl> + + <TreeListPane> + <View> + <WinId>1506</WinId> + <ViewName>Symbols</ViewName> + <UserString></UserString> + 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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA.uvgui_Äìèòðèé.bak --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA.uvgui_Äìèòðèé.bak Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,2280 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_gui.xsd"> + + <SchemaVersion>-2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <ViewPool/> + + <SECTreeCtrl> + <View> + <WinId>38003</WinId> + <ViewName>Registers</ViewName> + <TableColWidths>115 78</TableColWidths> + </View> + <View> + <WinId>346</WinId> + <ViewName>Code Coverage</ViewName> + <TableColWidths>1047 160</TableColWidths> + </View> + <View> + <WinId>204</WinId> + <ViewName>Performance Analyzer</ViewName> + <TableColWidths>1207</TableColWidths> + </View> + </SECTreeCtrl> + + <TreeListPane> + <View> + <WinId>1506</WinId> + <ViewName>Symbols</ViewName> + <UserString></UserString> + <TableColWidths>133 133 133</TableColWidths> + </View> + <View> + <WinId>1936</WinId> + <ViewName>Watch 1</ViewName> + <UserString></UserString> + <TableColWidths>133 133 133</TableColWidths> + </View> + <View> + <WinId>1937</WinId> + <ViewName>Watch 2</ViewName> + <UserString></UserString> + <TableColWidths>133 133 133</TableColWidths> + </View> + <View> + <WinId>1935</WinId> + <ViewName>Call Stack + Locals</ViewName> + <UserString></UserString> + <TableColWidths>237 237 237</TableColWidths> + </View> + <View> + <WinId>2506</WinId> + <ViewName>Trace Data</ViewName> + <UserString></UserString> + <TableColWidths>135 95 230 200</TableColWidths> + </View> + </TreeListPane> + + <WindowSettings> + <LogicAnalizer> + <ShowLACursor>1</ShowLACursor> + <ShowSignalInfo>1</ShowSignalInfo> + <ShowCycles>0</ShowCycles> + </LogicAnalizer> + </WindowSettings> + + <WinLayoutEx> + <sActiveDebugView></sActiveDebugView> + <WindowPosition> + <length>44</length> + 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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA.uvgui_Èãîðü.bak --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA.uvgui_Èãîðü.bak Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1421 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_gui.xsd"> + + <SchemaVersion>-4.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <ViewPool/> + + <SECTreeCtrl> + <View> + <WinId>38003</WinId> + <ViewName>Registers</ViewName> + <TableColWidths>115 63</TableColWidths> + </View> + <View> + <WinId>346</WinId> + <ViewName>Code Coverage</ViewName> + <TableColWidths>582 160</TableColWidths> + </View> + <View> + <WinId>204</WinId> + <ViewName>Performance Analyzer</ViewName> + <TableColWidths>742</TableColWidths> + </View> + </SECTreeCtrl> + + <TreeListPane> + <View> + <WinId>1506</WinId> + <ViewName>Symbols</ViewName> + <UserString></UserString> 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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA.uvproj --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA.uvproj Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,547 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd"> + + <SchemaVersion>1.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>LandTiger_DMA</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>LPC1768</Device> + <Vendor>NXP (founded by Philips)</Vendor> + <Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x2007C000-0x20083FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3")</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile>"STARTUP\NXP\LPC17xx\startup_LPC17xx.s" ("NXP LPC17xx Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000)</FlashDriverDll> + <DeviceId>4868</DeviceId> + <RegisterFile>LPC17xx.H</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:LPC1768$SVD\LPC176x5x.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>NXP\LPC17xx\</RegisterFilePath> + <DBRegisterFilePath>NXP\LPC17xx\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\Obj\</OutputDirectory> + <OutputName>LandTiger_DMA</OutputName> + <CreateExecutable>1</CreateExecutable> + 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<FilePath>.\Source\App\QEI.c</FilePath> + </File> + <File> + <FileName>Global.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\Global.c</FilePath> + </File> + <File> + <FileName>MTimer.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\MTimer.c</FilePath> + </File> + <File> + <FileName>SPI.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\SPI.c</FilePath> + </File> + <File> + <FileName>Command.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\Command.c</FilePath> + </File> + <File> + <FileName>uart_m.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\uart_m.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Read</GroupName> + </Group> + </Groups> + </Target> + </Targets> + +</Project>
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA_LandTiger_DMA.dep --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA_LandTiger_DMA.dep Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,185 @@ +Dependencies for Project 'LandTiger_DMA', Target 'LandTiger_DMA': (DO NOT MODIFY !) +F (.\Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm\startup_LPC17xx.s)(0x512CA352)(--cpu Cortex-M3 --pd "__EVAL SETA 1" -g --apcs=interwork -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" --pd "NO_CRP SETA 1" --list ".\List\startup_LPC17xx.lst" --xref -o ".\Obj\startup_LPC17xx.o" --depend ".\Obj\startup_LPC17xx.d") +F (.\Source\CMSIS\CM3\CoreSupport\core_cm3.c)(0x4AEA5B64)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\core_cm3.o" --omf_browse ".\Obj\core_cm3.crf" --depend ".\Obj\core_cm3.d") +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +F (.\Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.c)(0x4E55F10A)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\system_lpc17xx.o" --omf_browse ".\Obj\system_lpc17xx.crf" --depend ".\Obj\system_lpc17xx.d") +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\LPC17xx.h)(0x4ADBBE7C) +I (.\Source\App\core_cm3.h)(0x511A2CA8) +I (.\Source\App\core_cmInstr.h)(0x511A2CBD) +I (.\Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.h)(0x4BE3EB98) +F (.\Source\App\CyclesSync.c)(0x54561B90)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\cyclessync.o" --omf_browse ".\Obj\cyclessync.crf" --depend ".\Obj\cyclessync.d") +I (Source\App\CyclesSync.h)(0x512C97DD) +I (Source\App\lpc17xx.h)(0x511A2C6E) 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(D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (Source\App\CntrlGLD.h)(0x54565227) +I (Source\App\InputOutput.h)(0x545794BB) +I (Source\App\Parameters.h)(0x5126F9D7) +F (.\Source\App\Dither_Reg.c)(0x51270E27)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\dither_reg.o" --omf_browse ".\Obj\dither_reg.crf" --depend ".\Obj\dither_reg.d") +I (Source\App\lpc17xx.h)(0x511A2C6E) +I (Source\App\core_cm3.h)(0x511A2CA8) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (Source\App\mathDSP.h)(0x4F312C6A) +I (D:\keil\ARM\RV31\INC\dspfns.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\assert.h)(0x4E78433E) +I (Source\App\InputOutput.h)(0x545794BB) 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"D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\main.o" --omf_browse ".\Obj\main.crf" --depend ".\Obj\main.d") +I (Source\App\SIP.h)(0x512C99F5) +I (Source\App\el_lin.h)(0x512C4332) +I (Source\App\CyclesSync.h)(0x512C97DD) +I (Source\App\lpc17xx.h)(0x511A2C6E) +I (Source\App\core_cm3.h)(0x511A2CA8) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (Source\App\CntrlGLD.h)(0x54565227) +I (Source\App\Parameters.h)(0x5126F9D7) +I (Source\App\Dither_Reg.h)(0x4E9FEFA0) +I (Source\App\commandset.h)(0x4F4C8EF2) +I (Source\App\stdint.h)(0x511A2C9B) +I (Source\App\InputOutput.h)(0x545794BB) +I (D:\keil\ARM\RV31\INC\math.h)(0x4E78433E) +F (.\Source\App\PLC_reg.c)(0x5460CF9C)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\plc_reg.o" --omf_browse ".\Obj\plc_reg.crf" --depend ".\Obj\plc_reg.d") +I (Source\App\mathDSP.h)(0x4F312C6A) +I (D:\keil\ARM\RV31\INC\dspfns.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\assert.h)(0x4E78433E) +I (Source\App\CyclesSync.h)(0x512C97DD) +I (Source\App\lpc17xx.h)(0x511A2C6E) +I (Source\App\core_cm3.h)(0x511A2CA8) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (Source\App\CntrlGLD.h)(0x54565227) +I (Source\App\ThermoCalc.h)(0x4F2BF604) +I (D:\keil\ARM\RV31\INC\stdlib.h)(0x4E78433E) +I (Source\App\InputOutput.h)(0x545794BB) +I (Source\App\stdint.h)(0x511A2C9B) +I (D:\keil\ARM\RV31\INC\math.h)(0x4E78433E) +F (.\Source\App\ThermoCalc.c)(0x51270CEF)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\thermocalc.o" --omf_browse ".\Obj\thermocalc.crf" --depend ".\Obj\thermocalc.d") +I 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(D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\assert.h)(0x4E78433E) +I (Source\App\InputOutput.h)(0x545794BB) +I (Source\App\stdint.h)(0x511A2C9B) +I (Source\App\CntrlGLD.h)(0x54565227) +F (.\Source\App\CntrlGLD.c)(0x54561B03)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\cntrlgld.o" --omf_browse ".\Obj\cntrlgld.crf" --depend ".\Obj\cntrlgld.d") +I (Source\App\commandset.h)(0x4F4C8EF2) +I (Source\App\stdint.h)(0x511A2C9B) +I (Source\App\CntrlGLD.h)(0x54565227) +I (Source\App\Cyclessync.h)(0x512C97DD) +I (Source\App\lpc17xx.h)(0x511A2C6E) +I (Source\App\core_cm3.h)(0x511A2CA8) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (D:\keil\ARM\RV31\INC\dspfns.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\assert.h)(0x4E78433E) +I (Source\App\SIP.h)(0x512C99F5) +I (Source\App\el_lin.h)(0x512C4332) +F (.\Source\App\mathDSP.c)(0x512630D8)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\mathdsp.o" --omf_browse ".\Obj\mathdsp.crf" --depend ".\Obj\mathdsp.d") +I (Source\App\mathDSP.h)(0x4F312C6A) +I (D:\keil\ARM\RV31\INC\dspfns.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\assert.h)(0x4E78433E) +I (Source\App\CntrlGLD.h)(0x54565227) +I (D:\keil\ARM\RV31\INC\math.h)(0x4E78433E) +F (.\Source\App\InputOutput.c)(0x5460CFA6)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\inputoutput.o" --omf_browse ".\Obj\inputoutput.crf" --depend ".\Obj\inputoutput.d") +I (Source\App\InputOutput.h)(0x545794BB) +I (Source\App\stdint.h)(0x511A2C9B) +I (Source\App\CyclesSync.h)(0x512C97DD) +I (Source\App\lpc17xx.h)(0x511A2C6E) +I (Source\App\core_cm3.h)(0x511A2CA8) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (Source\App\CntrlGLD.h)(0x54565227) +I (Source\App\el_lin.h)(0x512C4332) +F (.\Source\App\SIP.c)(0x512C9A74)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\sip.o" --omf_browse ".\Obj\sip.crf" --depend ".\Obj\sip.d") +I (Source\App\mathDSP.h)(0x4F312C6A) +I (D:\keil\ARM\RV31\INC\dspfns.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (D:\keil\ARM\RV31\INC\assert.h)(0x4E78433E) +I (Source\App\SIP.h)(0x512C99F5) +I (Source\App\CyclesSync.h)(0x512C97DD) +I (Source\App\lpc17xx.h)(0x511A2C6E) +I (Source\App\core_cm3.h)(0x511A2CA8) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (Source\App\CntrlGLD.h)(0x54565227) +I (Source\App\InputOutput.h)(0x545794BB) +I (Source\App\stdint.h)(0x511A2C9B) +I (Source\App\ThermoCalc.h)(0x4F2BF604) +I (D:\keil\ARM\RV31\INC\stdlib.h)(0x4E78433E) +I (Source\App\el_lin.h)(0x512C4332) +F (.\Source\App\Parameters.c)(0x5126F905)(-c --cpu Cortex-M3 -D__EVAL -g -O0 --apcs=interwork -I.\Source -I.\Source\App -I "D:\keil\ARM\CMSIS\Include" -I "D:\keil\ARM\INC\NXP\LPC17xx" -o ".\Obj\parameters.o" --omf_browse ".\Obj\parameters.crf" --depend ".\Obj\parameters.d") +I (Source\App\CntrlGLD.h)(0x54565227) +I (Source\App\lpc17xx.h)(0x511A2C6E) +I (Source\App\core_cm3.h)(0x511A2CA8) +I (D:\keil\ARM\RV31\INC\stdint.h)(0x4E78433E) +I (Source\App\core_cmInstr.h)(0x511A2CBD) +I (Source\App\core_cmFunc.h)(0x511A2CD3) +I (Source\App\system_LPC17xx.h)(0x511A2CEB) +I (Source\App\Parameters.h)(0x5126F9D7) +I (Source\App\el_lin.h)(0x512C4332)
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA_Target 1.dep --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA_Target 1.dep Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1 @@ +Dependencies for Project 'LandTiger_DMA', Target 'Target 1': (DO NOT MODIFY !)
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA_uvopt.bak --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA_uvopt.bak Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,502 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>LandTiger_DMA</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>1</RunSim> + <RunTarget>0</RunTarget> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\List\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>8</CpuCode> + <Books> + <Book> + <Number>0</Number> + <Title>MCB1700 Schematics (MCB1700)</Title> + <Path>C:\Keil\ARM\PACK\Keil\LPC1700_DFP\2.0.0\Documents\mcb1700-schematics.pdf</Path> + </Book> + <Book> + <Number>1</Number> + <Title>User Manual (MCB1700)</Title> + <Path>C:\Keil\ARM\PACK\Keil\LPC1700_DFP\2.0.0\Documents\mcb1700.chm</Path> + </Book> + <Book> + <Number>2</Number> + <Title>MCB1700 Quick Start Guide (MCB1700)</Title> + <Path>C:\Keil\ARM\PACK\Keil\LPC1700_DFP\2.0.0\Documents\mcb1700_quickstart.pdf</Path> + </Book> + <Book> + <Number>3</Number> + <Title>MCB1700 Evaluation Board Web Page (MCB1700)</Title> + <Path>http://www.keil.com/mcb1700/</Path> + </Book> + </Books> + <DllOpt> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU</SimDllArguments> + <SimDlgDllName>DARMP1.DLL</SimDlgDllName> + <SimDlgDllArguments>-pLPC1768</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDllName>TARMP1.DLL</TargetDlgDllName> + <TargetDlgDllArguments>-pLPC1768</TargetDlgDllArguments> + </DllOpt> + <DebugOpt> + <uSim>0</uSim> + <uTrg>1</uTrg> + <sLdApp>1</sLdApp> + <sGomain>0</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <nTsel>-1</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>SiLabs\SLAB_CM_Keil.dll</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>SLAB_CM_Keil</Key> + <Name>-U -O718 -S3 -C-1 -J0 -K0 -M0 -N0 -TO18 -TC20000000 -TP21 -TDS8031 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN0</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=75,100,450,642,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(313=-1,-1,-1,-1,0)(291=-1,-1,-1,-1,0)(302=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(330=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(381=165,0,540,593,0)(382=-1,-1,-1,-1,0)(383=165,0,540,593,0)(384=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(199=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(261=203,238,509,655,0)(262=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=207,0,981,649,0)(400=225,262,738,734,0)(370=-1,-1,-1,-1,0)(160=255,295,501,629,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGTARM</Key> + <Name>(1010=75,100,450,642,0)(1007=105,133,282,394,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(313=-1,-1,-1,-1,0)(291=-1,-1,-1,-1,0)(302=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(330=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(381=165,0,540,593,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(121=210,247,726,721,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=225,263,738,675,0)(370=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(280=270,244,702,734,0)(240=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGUARM</Key> + <Name>(106=145,143,901,443,0)(107=180,214,510,385,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>JL2CM3</Key> + <Name>-U20090928 -O78 -S8 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000)</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <WatchWindow1> + <Ww> + <count>0</count> + <WinNumber>1</WinNumber> + <ItemText>Cnt_curr,0x0A</ItemText> + </Ww> + <Ww> + <count>1</count> + <WinNumber>1</WinNumber> + <ItemText>time_1_Sec,0x0A</ItemText> + </Ww> + <Ww> + <count>2</count> + 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<GroupNumber>2</GroupNumber> + <FileNumber>16</FileNumber> + <FileType>1</FileType> + <tvExp>0</tvExp> + <Focus>0</Focus> + <ColumnNumber>153348616</ColumnNumber> + <tvExpOptDlg>0</tvExpOptDlg> + <TopLine>20583996</TopLine> + <CurrentLine>3608532</CurrentLine> + <bDave2>0</bDave2> + <PathWithFileName>.\Source\App\Parameters.c</PathWithFileName> + <FilenameWithoutPath>Parameters.c</FilenameWithoutPath> + </File> + </Group> + + <Group> + <GroupName>Read</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + </Group> + +</ProjectOpt>
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/LandTiger_DMA_uvproj.bak --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/LandTiger_DMA_uvproj.bak Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,483 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd"> + + <SchemaVersion>1.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>LandTiger_DMA</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <TargetCommonOption> + <Device>LPC1768</Device> + <Vendor>NXP (founded by Philips)</Vendor> + <Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x2007C000-0x20083FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3")</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile>"STARTUP\NXP\LPC17xx\startup_LPC17xx.s" ("NXP LPC17xx Startup Code")</StartupFile> + <FlashDriverDll>UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000)</FlashDriverDll> + <DeviceId>4868</DeviceId> + <RegisterFile>LPC17xx.H</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:LPC1768$SVD\LPC176x5x.svd</SFDFile> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath>NXP\LPC17xx\</RegisterFilePath> + <DBRegisterFilePath>NXP\LPC17xx\</DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\Obj\</OutputDirectory> + <OutputName>LandTiger_DMA</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>1</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\List\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </BeforeMake> + <AfterMake> + <RunUserProg1>1</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name>fromelf --bin --output=.\obj\LandTiger_DMA.bin .\obj\LandTiger_DMA.axf</UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments>-MPU</SimDllArguments> + <SimDlgDll>DARMP1.DLL</SimDlgDll> + <SimDlgDllArguments>-pLPC1768</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments>-MPU</TargetDllArguments> + <TargetDlgDll>TARMP1.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pLPC1768</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + <Simulator> + <UseSimulator>0</UseSimulator> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>0</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>1</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + <LimitSpeedToRealTime>0</LimitSpeedToRealTime> + </Simulator> + <Target> + <UseTarget>1</UseTarget> + <LoadApplicationAtStartup>1</LoadApplicationAtStartup> + <RunToMain>1</RunToMain> + <RestoreBreakpoints>1</RestoreBreakpoints> + <RestoreWatchpoints>1</RestoreWatchpoints> + <RestoreMemoryDisplay>1</RestoreMemoryDisplay> + <RestoreFunctions>0</RestoreFunctions> + <RestoreToolbox>1</RestoreToolbox> + </Target> + <RunDebugAfterBuild>0</RunDebugAfterBuild> + <TargetSelection>-1</TargetSelection> + <SimDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + </SimDlls> + <TargetDlls> + <CpuDll></CpuDll> + <CpuDllArguments></CpuDllArguments> + <PeripheralDll></PeripheralDll> + <PeripheralDllArguments></PeripheralDllArguments> + <InitializationFile></InitializationFile> + <Driver>SiLabs\SLAB_CM_Keil.dll</Driver> + </TargetDlls> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4098</DriverSelection> + </Flash1> + <Flash2>Segger\JL2CM3.dll</Flash2> + <Flash3>"" ()</Flash3> + <Flash4></Flash4> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M3"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <hadIRAM2>1</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>1</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>1</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x10000000</StartAddress> + <Size>0x8000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x80000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x27fff</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x10000000</StartAddress> + <Size>0x8000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x2007c000</StartAddress> + <Size>0x8000</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>2</wLevel> + <uThumb>0</uThumb> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath>.\Source;.\Source\App</IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <VariousControls> + <MiscControls></MiscControls> + <Define>NO_CRP</Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>1</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x00010000</TextAddressRange> + <DataAddressRange>0x10000000</DataAddressRange> + <ScatterFile>.\Obj\LandTiger_DMA.sct</ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>CMSIS</GroupName> + <Files> + <File> + <FileName>startup_LPC17xx.s</FileName> + <FileType>2</FileType> + <FilePath>.\Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm\startup_LPC17xx.s</FilePath> + </File> + <File> + <FileName>core_cm3.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\CMSIS\CM3\CoreSupport\core_cm3.c</FilePath> + </File> + <File> + <FileName>system_LPC17xx.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>APP</GroupName> + <Files> + <File> + <FileName>CyclesSync.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\CyclesSync.c</FilePath> + </File> + <File> + <FileName>commandset.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\commandset.c</FilePath> + </File> + <File> + <FileName>Dither_Reg.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\Dither_Reg.c</FilePath> + </File> + <File> + <FileName>el_lin.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\el_lin.c</FilePath> + </File> + <File> + <FileName>main.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\main.c</FilePath> + </File> + <File> + <FileName>PLC_reg.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\PLC_reg.c</FilePath> + </File> + <File> + <FileName>ThermoCalc.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\ThermoCalc.c</FilePath> + </File> + <File> + <FileName>HFO_Reg.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\HFO_Reg.c</FilePath> + </File> + <File> + <FileName>CntrlGLD.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\CntrlGLD.c</FilePath> + </File> + <File> + <FileName>mathDSP.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\mathDSP.c</FilePath> + </File> + <File> + <FileName>InputOutput.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\InputOutput.c</FilePath> + </File> + <File> + <FileName>SIP.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\SIP.c</FilePath> + </File> + <File> + <FileName>Parameters.c</FileName> + <FileType>1</FileType> + <FilePath>.\Source\App\Parameters.c</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Read</GroupName> + </Group> + </Groups> + </Target> + </Targets> + +</Project>
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/List/LandTiger_DMA.map --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/List/LandTiger_DMA.map Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1917 @@ +Component: ARM Compiler 5.05 update 2 (build 169) Tool: armlink [4d0f33] + +============================================================================== + +Section Cross References + + startup_lpc17xx.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_lpc17xx.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_lpc17xx.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_lpc17xx.o(RESET) refers to startup_lpc17xx.o(STACK) for __initial_sp + startup_lpc17xx.o(RESET) refers to startup_lpc17xx.o(.text) for Reset_Handler + startup_lpc17xx.o(RESET) refers to cyclessync.o(.text) for TIMER0_IRQHandler + startup_lpc17xx.o(RESET) refers to mtimer.o(.text) for TIMER1_IRQHandler + startup_lpc17xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_lpc17xx.o(.text) refers to system_lpc17xx.o(.text) for SystemInit + startup_lpc17xx.o(.text) refers to __main.o(!!!main) for __main + startup_lpc17xx.o(.text) refers to startup_lpc17xx.o(HEAP) for Heap_Mem + startup_lpc17xx.o(.text) refers to startup_lpc17xx.o(STACK) for Stack_Mem + system_lpc17xx.o(.text) refers to system_lpc17xx.o(.data) for SystemCoreClock + vibro.o(.text) refers to rand.o(.text) for srand + vibro.o(.text) refers to rand.o(.emb_text) for rand + vibro.o(.text) refers to global.o(.text) for VibroPush + vibro.o(.text) refers to vibro.o(.bss) for Main + vibro.o(.text) refers to mtimer.o(.data) for CountV31 + vibro.o(.text) refers to global.o(.data) for Time_vibro + vibro.o(.text) refers to vibro.o(.data) for PeriodCount + vibro.o(.text) refers to qei.o(.bss) for Buff_Restored_sin + vibro.o(.text) refers to inputoutput.o(.bss) for Output + cyclessync.o(.text) refers to el_lin.o(.text) for UART_SwitchSpeed + cyclessync.o(.text) refers to cyclessync.o(.data) for LatchPhase + cyclessync.o(.text) refers to cntrlgld.o(.data) for RgConB + cyclessync.o(.text) refers to sip.o(.data) for Cnt_curr + commandset.o(.text) refers to el_lin.o(.text) for UART_SwitchSpeed + commandset.o(.text) refers to el_lin.o(.bss) for rcv_buf + commandset.o(.text) refers to cyclessync.o(.data) for trm_cycl + commandset.o(.text) refers to cntrlgld.o(.data) for SRgR + commandset.o(.text) refers to el_lin.o(.data) for trm_rate + commandset.o(.text) refers to inputoutput.o(.bss) for Output + commandset.o(.text) refers to commandset.o(.data) for index + commandset.o(.text) refers to dither_reg.o(.text) for VibroDither_Set + commandset.o(.text) refers to inputoutput.o(.text) for Out_G_photo + commandset.o(.text) refers to cyclessync.o(.text) for SwitchRefMeandInt + commandset.o(.text) refers to parameters.o(.text) for LoadFlashParam + commandset.o(.text) refers to dither_reg.o(.data) for In_Flag + commandset.o(.text) refers to cntrlgld.o(.bss) for Device_blk + commandset.o(.text) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + commandset.o(.data) refers to inputoutput.o(.bss) for Output + dither_reg.o(.text) refers to mathdsp.o(.text) for DUP_Filt + dither_reg.o(.text) refers to rand.o(.text) for srand + dither_reg.o(.text) refers to rand.o(.emb_text) for rand + dither_reg.o(.text) refers to inputoutput.o(.bss) for Output + dither_reg.o(.text) refers to cntrlgld.o(.bss) for Device_blk + dither_reg.o(.text) refers to dither_reg.o(.data) for neg_counter + dither_reg.o(.text) refers to sip.o(.data) for Dif_Curr_Vib + dither_reg.o(.text) refers to mathdsp.o(.data) for Vibro_2_CountIn + dither_reg.o(.text) refers to cyclessync.o(.data) for time_1_Sec + dither_reg.o(.text) refers to cntrlgld.o(.data) for RgConA + dither_reg.o(.text) refers to dither_reg.o(.data__ZZ20_arm_global_overflowE1v) for _arm_global_overflow::v + dither_reg.o(.text) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f + dither_reg.o(.text) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + dither_reg.o(.text) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dither_reg.o(.text) refers to cyclessync.o(.text) for CounterIquiryCycle_Init + el_lin.o(.text) refers to el_lin.o(.bss) for rcv_buf + el_lin.o(.text) refers to el_lin.o(.data) for rcv_num_byt + el_lin.o(.text) refers to cntrlgld.o(.bss) for Device_blk + el_lin.o(.text) refers to cntrlgld.o(.data) for Device_Mode + el_lin.o(.text) refers to system_lpc17xx.o(.data) for SystemCoreClock + main.o(.text) refers to system_lpc17xx.o(.text) for SystemInit + main.o(.text) refers to el_lin.o(.text) for DMA_Init + main.o(.text) refers to parameters.o(.text) for FlashDMA_Init + main.o(.text) refers to inputoutput.o(.text) for DAC_ADC_Exchange_Init + main.o(.text) refers to sip.o(.text) for SOI_Init + main.o(.text) refers to cyclessync.o(.text) for IntLatch_Init + main.o(.text) refers to plc_reg.o(.text) for init_PLC + main.o(.text) refers to dither_reg.o(.text) for init_Dither_reg + main.o(.text) refers to vibro.o(.text) for init_Vibro + main.o(.text) refers to mtimer.o(.text) for init_timer + main.o(.text) refers to console.o(.text) for SendToBuffStr + main.o(.text) refers to uart_m.o(.text) for WriteCon + main.o(.text) refers to command.o(.text) for Read_CMD + main.o(.text) refers to global.o(.text) for ButtonLightUP + main.o(.text) refers to thermocalc.o(.text) for clc_ThermoSensors + main.o(.text) refers to hfo_reg.o(.text) for clc_HFO + main.o(.text) refers to cntrlgld.o(.text) for contrl_GLD + main.o(.text) refers to commandset.o(.text) for decode_CMD + main.o(.text) refers to main.o(.data) for flag + main.o(.text) refers to vibro.o(.bss) for Main + main.o(.text) refers to qei.o(.data) for Pulse_midl + main.o(.text) refers to spi.o(.bss) for Spi + main.o(.text) refers to cntrlgld.o(.data) for RgConA + main.o(.text) refers to cntrlgld.o(.bss) for Device_blk + main.o(.text) refers to inputoutput.o(.bss) for Output + main.o(.text) refers to spi.o(.data) for Temp_AMP + main.o(.text) refers to qei.o(.bss) for Buff_16Point + main.o(.text) refers to uart_m.o(.data) for OutBufConCount + main.o(.text) refers to global.o(.data) for Time_1kHz + main.o(.text) refers to command.o(.data) for Rate_Flag + main.o(.text) refers to sip.o(.data) for Curr_Cnt_Vib + plc_reg.o(.text) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + plc_reg.o(.text) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + plc_reg.o(.text) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + plc_reg.o(.text) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + plc_reg.o(.text) refers to sin.o(i.sin) for sin + plc_reg.o(.text) refers to d2f.o(x$fpl$d2f) for __aeabi_d2f + plc_reg.o(.text) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul + plc_reg.o(.text) refers to ffix.o(x$fpl$ffix) for __aeabi_f2iz + plc_reg.o(.text) refers to mathdsp.o(.text) for init_BandPass + plc_reg.o(.text) refers to cntrlgld.o(.bss) for Device_blk + plc_reg.o(.text) refers to inputoutput.o(.bss) for Output + plc_reg.o(.text) refers to plc_reg.o(.data) for WP_reg32 + plc_reg.o(.text) refers to plc_reg.o(.bss) for sin_func + plc_reg.o(.text) refers to thermocalc.o(.data) for IsHeating + plc_reg.o(.text) refers to dither_reg.o(.data__ZZ20_arm_global_overflowE1v) for _arm_global_overflow::v + plc_reg.o(.text) refers to inputoutput.o(.text) for DAC_Output + plc_reg.o(.text) refers to cntrlgld.o(.data) for RgConA + plc_reg.o(.text) refers to cyclessync.o(.data) for time_1_Sec + hfo_reg.o(.text) refers to mathdsp.o(.text) for HFO_MovAverFilt + hfo_reg.o(.text) refers to inputoutput.o(.bss) for Input + hfo_reg.o(.text) refers to cntrlgld.o(.bss) for Device_blk + hfo_reg.o(.text) refers to dither_reg.o(.data__ZZ20_arm_global_overflowE1v) for _arm_global_overflow::v + hfo_reg.o(.text) refers to cntrlgld.o(.data) for RgConA + hfo_reg.o(.text) refers to hfo_reg.o(.data) for hf_reg + thermocalc.o(.text) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + thermocalc.o(.text) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul + thermocalc.o(.text) refers to faddsub_clz.o(x$fpl$frsb) for __aeabi_frsub + thermocalc.o(.text) refers to ffix.o(x$fpl$ffix) for __aeabi_f2iz + thermocalc.o(.text) refers to cntrlgld.o(.bss) for Device_blk + thermocalc.o(.text) refers to thermocalc.o(.bss) for dFuncPer_dTermo + thermocalc.o(.text) refers to thermocalc.o(.data) for Temp_Aver + thermocalc.o(.text) refers to inputoutput.o(.bss) for Input + thermocalc.o(.text) refers to cyclessync.o(.data) for time_1_Sec + thermocalc.o(.text) refers to dither_reg.o(.data__ZZ20_arm_global_overflowE1v) for _arm_global_overflow::v + thermocalc.o(.text) refers to plc_reg.o(.data) for WP_reset_heating + thermocalc.o(.text) refers to cntrlgld.o(.data) for Valid_Data + thermocalc.o(.text) refers to thermocalc.o(i.Max_Saturation) for Max_Saturation + thermocalc.o(.text) refers to dither_reg.o(.data) for VB_Nmin0 + cntrlgld.o(.text) refers to cyclessync.o(.text) for SwitchMode + cntrlgld.o(.text) refers to commandset.o(.text) for GLD_Output + cntrlgld.o(.text) refers to cntrlgld.o(.data) for stop_Rq + cntrlgld.o(.text) refers to el_lin.o(.data) for trm_ena + cntrlgld.o(.text) refers to sip.o(.data) for Dif_Curr_Vib + cntrlgld.o(.text) refers to dither_reg.o(.data__ZZ20_arm_global_overflowE1v) for _arm_global_overflow::v + cntrlgld.o(.data) refers to cntrlgld.o(.text) for Sts_Pulse + mathdsp.o(.text) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + mathdsp.o(.text) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + mathdsp.o(.text) refers to cos.o(i.cos) for cos + mathdsp.o(.text) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + mathdsp.o(.text) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + mathdsp.o(.text) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + mathdsp.o(.text) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + mathdsp.o(.text) refers to cntrlgld.o(.bss) for Device_blk + mathdsp.o(.text) refers to mathdsp.o(.data) for Vibro_Filter_Aperture + mathdsp.o(.text) refers to dither_reg.o(.data__ZZ20_arm_global_overflowE1v) for _arm_global_overflow::v + mathdsp.o(.text) refers to mathdsp.o(.bss) for BufInMovAverPls + inputoutput.o(.text) refers to inputoutput.o(.data) for I2CMasterState + inputoutput.o(.text) refers to inputoutput.o(.bss) for I2CMasterBuffer + inputoutput.o(.text) refers to cyclessync.o(.data) for Sys_Clock + sip.o(.text) refers to llsdiv.o(.text) for __aeabi_ldivmod + sip.o(.text) refers to mathdsp.o(.text) for VibroReduce + sip.o(.text) refers to cyclessync.o(.data) for PrevPeriod + sip.o(.text) refers to sip.o(.data) for temp22 + sip.o(.text) refers to cntrlgld.o(.data) for RgConB + sip.o(.text) refers to inputoutput.o(.bss) for Output + sip.o(.text) refers to thermocalc.o(.data) for TermoCompens_Sum + parameters.o(.text) refers to cntrlgld.o(.bss) for Device_blk + parameters.o(.text) refers to commandset.o(.data) for blt_in_test + console.o(.text) refers to console.o(.data) for InputIndexBO + console.o(.text) refers to console.o(.bss) for BuffOut + qei.o(.text) refers to qei.o(.data) for Dif_QEI + qei.o(.text) refers to qei.o(.bss) for Buff_1Point + qei.o(.text) refers to mtimer.o(.data) for CountV255 + qei.o(.text) refers to vibro.o(.bss) for Main + global.o(.text) refers to global.o(.data) for VibroReg + global.o(.text) refers to main.o(.data) for secPuls + global.o(.text) refers to cntrlgld.o(.data) for pulse_Rq + mtimer.o(.text) refers to qei.o(.text) for D_QEI + mtimer.o(.text) refers to vibro.o(.text) for cheng + mtimer.o(.text) refers to spi.o(.text) for SPI_Exchange + mtimer.o(.text) refers to mtimer.o(.data) for CountV255 + mtimer.o(.text) refers to qei.o(.bss) for Buff_32Point + mtimer.o(.text) refers to qei.o(.data) for CuruAngle + mtimer.o(.text) refers to global.o(.data) for Global_Time + spi.o(.text) refers to spi.o(.bss) for Spi + spi.o(.text) refers to inputoutput.o(.bss) for Input + spi.o(.text) refers to mtimer.o(.data) for CountV31 + spi.o(.text) refers to spi.o(.data) for SinPLC + command.o(.text) refers to uart_m.o(.text) for WriteConN + command.o(.text) refers to vibro.o(.bss) for Main + command.o(.text) refers to global.o(.bss) for BuffTemp + command.o(.text) refers to spi.o(.bss) for Spi + command.o(.text) refers to command.o(.data) for Param1 + command.o(.text) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + command.o(.text) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul + command.o(.text) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + command.o(.text) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + command.o(.text) refers to d2f.o(x$fpl$d2f) for __aeabi_d2f + command.o(.text) refers to ffixu.o(x$fpl$ffixu) for __aeabi_f2uiz + command.o(.text) refers to main.o(.data) for K_DAC + uart_m.o(.text) refers to uart_m.o(.data) for UART0_BPS + uart_m.o(.text) refers to uart_m.o(.bss) for OutCon + llsdiv.o(.text) refers to lludivv7m.o(.text) for __aeabi_uldivmod + rand.o(.emb_text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rand.o(.emb_text) refers to rand.o(.text) for _rand_init + rand.o(.emb_text) refers to rand.o(.bss) for _random_number_data + rand.o(.text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rand.o(.text) refers to rand.o(.bss) for .bss + rand.o(.bss) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rt_memcpy_v6.o(.text) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + d2f.o(x$fpl$d2f) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + d2f.o(x$fpl$d2f) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf + d2f.o(x$fpl$d2f) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + daddsub_clz.o(x$fpl$dadd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$dadd) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1 + daddsub_clz.o(x$fpl$dadd) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + daddsub_clz.o(x$fpl$dadd) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + daddsub_clz.o(x$fpl$drsb) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1 + daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1 + daddsub_clz.o(x$fpl$dsub) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$dsub) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1 + daddsub_clz.o(x$fpl$dsub) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry + ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfix) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfixr) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dmul.o(x$fpl$dmul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dmul.o(x$fpl$dmul) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + dmul.o(x$fpl$dmul) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + f2d.o(x$fpl$f2d) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + f2d.o(x$fpl$f2d) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + f2d.o(x$fpl$f2d) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + faddsub_clz.o(x$fpl$fadd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + faddsub_clz.o(x$fpl$fadd) refers to faddsub_clz.o(x$fpl$fsub) for _fsub1 + faddsub_clz.o(x$fpl$fadd) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf + faddsub_clz.o(x$fpl$fadd) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + faddsub_clz.o(x$fpl$frsb) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + faddsub_clz.o(x$fpl$frsb) refers to faddsub_clz.o(x$fpl$fadd) for _fadd1 + faddsub_clz.o(x$fpl$frsb) refers to faddsub_clz.o(x$fpl$fsub) for _fsub1 + faddsub_clz.o(x$fpl$fsub) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + faddsub_clz.o(x$fpl$fsub) refers to faddsub_clz.o(x$fpl$fadd) for _fadd1 + faddsub_clz.o(x$fpl$fsub) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + ffix.o(x$fpl$ffix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ffix.o(x$fpl$ffix) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + ffix.o(x$fpl$ffixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ffix.o(x$fpl$ffixr) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + ffixu.o(x$fpl$ffixu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ffixu.o(x$fpl$ffixu) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + ffixu.o(x$fpl$ffixur) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ffixu.o(x$fpl$ffixur) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + fflt_clz.o(x$fpl$ffltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fflt_clz.o(x$fpl$fflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fflt_clz.o(x$fpl$ffltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fmul.o(x$fpl$fmul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fmul.o(x$fpl$fmul) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf + fmul.o(x$fpl$fmul) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + cos.o(i.__softfp_cos) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos.o(i.__softfp_cos) refers to cos.o(i.cos) for cos + cos.o(i.cos) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos.o(i.cos) refers to _rserrno.o(.text) for __set_errno + cos.o(i.cos) refers to dunder.o(i.__mathlib_dbl_invalid) for __mathlib_dbl_invalid + cos.o(i.cos) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + cos.o(i.cos) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + cos.o(i.cos) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + cos.o(i.cos) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + cos_x.o(i.____softfp_cos$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos_x.o(i.____softfp_cos$lsc) refers to cos_x.o(i.__cos$lsc) for __cos$lsc + cos_x.o(i.__cos$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos_x.o(i.__cos$lsc) refers to _rserrno.o(.text) for __set_errno + cos_x.o(i.__cos$lsc) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + cos_x.o(i.__cos$lsc) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + cos_x.o(i.__cos$lsc) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + cos_x.o(i.__cos$lsc) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + sin.o(i.__softfp_sin) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin.o(i.__softfp_sin) refers to sin.o(i.sin) for sin + sin.o(i.sin) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin.o(i.sin) refers to _rserrno.o(.text) for __set_errno + sin.o(i.sin) refers to dunder.o(i.__mathlib_dbl_invalid) for __mathlib_dbl_invalid + sin.o(i.sin) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + sin.o(i.sin) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + sin.o(i.sin) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + sin.o(i.sin) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + sin_x.o(i.____softfp_sin$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_x.o(i.____softfp_sin$lsc) refers to sin_x.o(i.__sin$lsc) for __sin$lsc + sin_x.o(i.__sin$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_x.o(i.__sin$lsc) refers to _rserrno.o(.text) for __set_errno + sin_x.o(i.__sin$lsc) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + sin_x.o(i.__sin$lsc) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + sin_x.o(i.__sin$lsc) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + sin_x.o(i.__sin$lsc) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + _rserrno.o(.text) refers to rt_errno_addr_intlibspace.o(.text) for __aeabi_errno_addr + libinit2.o(.ARM.Collect$$libinit$$0000000D) refers (Weak) to rand.o(.text) for _rand_init + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fnaninf.o(x$fpl$fnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fretinf.o(x$fpl$fretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos_i.o(i.__kernel_cos) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos_i.o(i.__kernel_cos) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + cos_i.o(i.__kernel_cos) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + cos_i.o(i.__kernel_cos) refers to poly.o(i.__kernel_poly) for __kernel_poly + cos_i.o(i.__kernel_cos) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + cos_i.o(i.__kernel_cos) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + cos_i.o(i.__kernel_cos) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + cos_i.o(i.__kernel_cos) refers to cos_i.o(.constdata) for .constdata + cos_i.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dunder.o(i.__mathlib_dbl_divzero) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dunder.o(i.__mathlib_dbl_infnan) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + dunder.o(i.__mathlib_dbl_infnan2) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + dunder.o(i.__mathlib_dbl_invalid) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dunder.o(i.__mathlib_dbl_overflow) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + dunder.o(i.__mathlib_dbl_posinfnan) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + dunder.o(i.__mathlib_dbl_underflow) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + rred.o(i.__ieee754_rem_pio2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rred.o(i.__ieee754_rem_pio2) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + rred.o(i.__ieee754_rem_pio2) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + rred.o(i.__ieee754_rem_pio2) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + rred.o(i.__ieee754_rem_pio2) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + rred.o(i.__ieee754_rem_pio2) refers to dflt_clz.o(x$fpl$dflt) for __aeabi_i2d + rred.o(i.__ieee754_rem_pio2) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + rred.o(i.__ieee754_rem_pio2) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + rred.o(i.__ieee754_rem_pio2) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + rred.o(i.__ieee754_rem_pio2) refers to rred.o(.constdata) for .constdata + rred.o(i.__use_accurate_range_reduction) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rred.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i.o(i.__kernel_sin) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i.o(i.__kernel_sin) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + sin_i.o(i.__kernel_sin) refers to dunder.o(i.__mathlib_dbl_underflow) for __mathlib_dbl_underflow + sin_i.o(i.__kernel_sin) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + sin_i.o(i.__kernel_sin) refers to poly.o(i.__kernel_poly) for __kernel_poly + sin_i.o(i.__kernel_sin) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + sin_i.o(i.__kernel_sin) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + sin_i.o(i.__kernel_sin) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + sin_i.o(i.__kernel_sin) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + sin_i.o(i.__kernel_sin) refers to sin_i.o(.constdata) for .constdata + sin_i.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i_x.o(i.____kernel_sin$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i_x.o(i.____kernel_sin$lsc) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + sin_i_x.o(i.____kernel_sin$lsc) refers to poly.o(i.__kernel_poly) for __kernel_poly + sin_i_x.o(i.____kernel_sin$lsc) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + sin_i_x.o(i.____kernel_sin$lsc) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + sin_i_x.o(i.____kernel_sin$lsc) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + sin_i_x.o(i.____kernel_sin$lsc) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + sin_i_x.o(i.____kernel_sin$lsc) refers to sin_i_x.o(.constdata) for .constdata + sin_i_x.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + aeabi_ldiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + rt_errno_addr.o(.text) refers to rt_errno_addr.o(.bss) for __aeabi_errno_addr_data + rt_errno_addr_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + dflt_clz.o(x$fpl$dfltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dfltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + scalbn.o(x$fpl$scalbn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + scalbn.o(x$fpl$scalbn) refers to dcheck1.o(x$fpl$dcheck1) for __fpl_dcheck_NaN1 + fpclassify.o(i.__ARM_fpclassify) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + poly.o(i.__kernel_poly) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + poly.o(i.__kernel_poly) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + poly.o(i.__kernel_poly) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_lpc17xx.o(.text) for __user_initial_stackheap + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + dcheck1.o(x$fpl$dcheck1) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dcheck1.o(x$fpl$dcheck1) refers to retnan.o(x$fpl$retnan) for __fpl_return_NaN + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + retnan.o(x$fpl$retnan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + retnan.o(x$fpl$retnan) refers to trapv.o(x$fpl$trapveneer) for __fpl_cmpreturn + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + trapv.o(x$fpl$trapveneer) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000003) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B) for __rt_lib_shutdown_user_alloc_1 + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing core_cm3.o(.emb_text), (32 bytes). + Removing system_lpc17xx.o(.emb_text), (8 bytes). + Removing vibro.o(.emb_text), (8 bytes). + Removing cyclessync.o(.emb_text), (8 bytes). + Removing commandset.o(.emb_text), (8 bytes). + Removing commandset.o(.bss), (100 bytes). + Removing dither_reg.o(.emb_text), (8 bytes). + Removing el_lin.o(.emb_text), (8 bytes). + Removing main.o(.emb_text), (8 bytes). + Removing plc_reg.o(.emb_text), (8 bytes). + Removing thermocalc.o(.emb_text), (8 bytes). + Removing cntrlgld.o(.emb_text), (8 bytes). + Removing inputoutput.o(.emb_text), (8 bytes). + Removing sip.o(.emb_text), (8 bytes). + Removing parameters.o(.emb_text), (8 bytes). + Removing console.o(.emb_text), (8 bytes). + Removing qei.o(.emb_text), (8 bytes). + Removing mtimer.o(.emb_text), (8 bytes). + Removing spi.o(.emb_text), (8 bytes). + Removing command.o(.emb_text), (8 bytes). + Removing uart_m.o(.emb_text), (8 bytes). + +21 unused section(s) (total 284 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + RESET 0x00000000 Section 196 startup_lpc17xx.o(RESET) + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/dczerorl2.s 0x00000000 Number 0 __dczerorl2.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_ldiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 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command.o(.data) + .data__ZZ20_arm_global_overflowE1v 0x10000154 Section 4 dither_reg.o(.data__ZZ20_arm_global_overflowE1v) + .bss 0x10000158 Section 6144 qei.o(.bss) + .bss 0x10001958 Section 100 global.o(.bss) + .bss 0x100019bc Section 6176 spi.o(.bss) + .bss 0x100031dc Section 8448 uart_m.o(.bss) + .bss 0x100052dc Section 96 libspace.o(.bss) + HEAP 0x10005340 Section 0 startup_lpc17xx.o(HEAP) + Heap_Mem 0x10005340 Data 0 startup_lpc17xx.o(HEAP) + .data 0x2007c000 Section 4 system_lpc17xx.o(.data) + .data 0x2007c004 Section 32 vibro.o(.data) + PeriodCount 0x2007c014 Data 4 vibro.o(.data) + Tnoise 0x2007c018 Data 4 vibro.o(.data) + TempFaza 0x2007c01c Data 4 vibro.o(.data) + CountFaza 0x2007c020 Data 4 vibro.o(.data) + .data 0x2007c024 Section 80 commandset.o(.data) + paramTable 0x2007c038 Data 44 commandset.o(.data) + val 0x2007c064 Data 4 commandset.o(.data) + paramTmpWord 0x2007c068 Data 4 commandset.o(.data) + ptr 0x2007c06c Data 4 commandset.o(.data) + index 0x2007c070 Data 4 commandset.o(.data) + .data 0x2007c074 Section 96 dither_reg.o(.data) + poz_counter 0x2007c0a8 Data 4 dither_reg.o(.data) + neg_counter 0x2007c0ac Data 4 dither_reg.o(.data) + flg_delay 0x2007c0b0 Data 4 dither_reg.o(.data) + SampleAndHoldOut 0x2007c0b4 Data 4 dither_reg.o(.data) + VB_PhasDet_integr 0x2007c0b8 Data 4 dither_reg.o(.data) + dith_period 0x2007c0bc Data 4 dither_reg.o(.data) + out_freq_sum 0x2007c0c0 Data 4 dither_reg.o(.data) + temp 0x2007c0c4 Data 4 dither_reg.o(.data) + Flag 0x2007c0c8 Data 4 dither_reg.o(.data) + PeriodCount 0x2007c0cc Data 4 dither_reg.o(.data) + Tnoise 0x2007c0d0 Data 4 dither_reg.o(.data) + .data 0x2007c0d4 Section 64 el_lin.o(.data) + ToWaitEnd 0x2007c10c Data 4 el_lin.o(.data) + ErrReg 0x2007c110 Data 4 el_lin.o(.data) + .data 0x2007c114 Section 104 main.o(.data) + .data 0x2007c17c Section 4 hfo_reg.o(.data) + hf_reg 0x2007c17c Data 4 hfo_reg.o(.data) + .data 0x2007c180 Section 108 cntrlgld.o(.data) + Device_Mode_Old 0x2007c1e4 Data 4 cntrlgld.o(.data) + Sum_F_ras 0x2007c1e8 Data 4 cntrlgld.o(.data) + .data 0x2007c1f0 Section 76 sip.o(.data) + cntPls_sum_32 0x2007c224 Data 4 sip.o(.data) + last_Cnt_Plus 0x2007c228 Data 4 sip.o(.data) + dif_sum_32 0x2007c22c Data 4 sip.o(.data) + Cnt_Pls 0x2007c230 Data 4 sip.o(.data) + Cnt_Mns 0x2007c234 Data 4 sip.o(.data) + preLast_Cnt_Plus 0x2007c238 Data 4 sip.o(.data) + .data 0x2007c23c Section 56 qei.o(.data) + .data 0x2007c274 Section 28 global.o(.data) + .data 0x2007c290 Section 12 mtimer.o(.data) + .data 0x2007c29c Section 276 spi.o(.data) + .data 0x2007c3b0 Section 132 uart_m.o(.data) + .bss 0x2007c434 Section 112 vibro.o(.bss) + .bss 0x2007c4a4 Section 352 el_lin.o(.bss) + .bss 0x2007c604 Section 400 plc_reg.o(.bss) + .bss 0x2007c794 Section 168 thermocalc.o(.bss) + .bss 0x2007c83c Section 684 cntrlgld.o(.bss) + .bss 0x2007cae8 Section 1704 mathdsp.o(.bss) + BufInDUP_1 0x2007d054 Data 12 mathdsp.o(.bss) + BufInDUP_2 0x2007d060 Data 12 mathdsp.o(.bss) + BufInPLC_1 0x2007d06c Data 12 mathdsp.o(.bss) + BufInPLC_2 0x2007d078 Data 12 mathdsp.o(.bss) + BufOutPLC 0x2007d084 Data 12 mathdsp.o(.bss) + buffer_HF 0x2007d090 Data 256 mathdsp.o(.bss) + .bss 0x2007d190 Section 200 inputoutput.o(.bss) + .bss 0x2007d258 Section 8192 console.o(.bss) + .bss 0x2007f258 Section 228 rand.o(.bss) + STACK 0x2007f340 Section 8192 startup_lpc17xx.o(STACK) + Stack_Mem 0x2007f340 Data 8192 startup_lpc17xx.o(STACK) + __initial_sp 0x20081340 Data 0 startup_lpc17xx.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEX$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __Vectors 0x00000000 Data 4 startup_lpc17xx.o(RESET) + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __arm_preinit_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __rt_locale - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_ctype - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_numeric - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __main 0x000000c5 Thumb Code 8 __main.o(!!!main) + __scatterload 0x000000cd Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x000000cd Thumb Code 44 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x000000cd Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x000000db Thumb Code 0 __scatter.o(!!!scatter) + __decompress 0x00000101 Thumb Code 90 __dczerorl2.o(!!dczerorl2) + __decompress1 0x00000101 Thumb Code 0 __dczerorl2.o(!!dczerorl2) + __scatterload_zeroinit 0x0000015d Thumb Code 28 __scatter_zi.o(!!handler_zi) + __rt_lib_init 0x00000179 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_fp_1 0x0000017b Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + __rt_lib_init_heap_1 0x0000017b Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + __rt_lib_init_preinit_1 0x0000017b Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + __rt_lib_init_rand_2 0x0000017b Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000D) + __rt_lib_init_user_alloc_1 0x0000017b Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_init_alloca_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + __rt_lib_init_argv_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + __rt_lib_init_atexit_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_clock_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + __rt_lib_init_cpp_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + __rt_lib_init_exceptions_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + __rt_lib_init_fp_trap_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_getenv_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + __rt_lib_init_lc_collate_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + __rt_lib_init_lc_ctype_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + __rt_lib_init_lc_monetary_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_numeric_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_lc_time_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_rand_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + __rt_lib_init_return 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033) + __rt_lib_init_signal_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + __rt_lib_init_stdio_1 0x0000017f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + __rt_lib_shutdown 0x00000181 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_fp_trap_1 0x00000183 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) + __rt_lib_shutdown_heap_1 0x00000183 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) + __rt_lib_shutdown_return 0x00000183 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_signal_1 0x00000183 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) + __rt_lib_shutdown_stdio_1 0x00000183 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000003) + __rt_lib_shutdown_user_alloc_1 0x00000183 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B) + __rt_entry 0x00000185 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x00000185 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x00000185 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x0000018b Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x0000018b Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x0000018f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x0000018f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x00000197 Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x00000199 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x00000199 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x0000019d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + rand 0x000001a5 Thumb Code 48 rand.o(.emb_text) + Reset_Handler 0x000001d9 Thumb Code 8 startup_lpc17xx.o(.text) + NMI_Handler 0x000001e1 Thumb Code 2 startup_lpc17xx.o(.text) + HardFault_Handler 0x000001e3 Thumb Code 2 startup_lpc17xx.o(.text) + MemManage_Handler 0x000001e5 Thumb Code 2 startup_lpc17xx.o(.text) + BusFault_Handler 0x000001e7 Thumb Code 2 startup_lpc17xx.o(.text) + UsageFault_Handler 0x000001e9 Thumb Code 2 startup_lpc17xx.o(.text) + SVC_Handler 0x000001eb Thumb Code 2 startup_lpc17xx.o(.text) + DebugMon_Handler 0x000001ed Thumb Code 2 startup_lpc17xx.o(.text) + PendSV_Handler 0x000001ef Thumb Code 2 startup_lpc17xx.o(.text) + SysTick_Handler 0x000001f1 Thumb Code 2 startup_lpc17xx.o(.text) + ADC_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + BOD_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + CAN_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + DMA_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + EINT0_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + EINT1_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + EINT2_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + ENET_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + I2C0_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + I2C1_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + I2C2_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + I2S_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + MCPWM_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + PLL0_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + PLL1_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + PWM1_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + RIT_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + RTC_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + SPI_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + SSP0_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + SSP1_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + UART0_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + UART1_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + UART2_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + UART3_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + USB_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + WDT_IRQHandler 0x000001f3 Thumb Code 0 startup_lpc17xx.o(.text) + __user_initial_stackheap 0x000001f5 Thumb Code 0 startup_lpc17xx.o(.text) + SystemCoreClockUpdate 0x00000215 Thumb Code 306 system_lpc17xx.o(.text) + SystemInit 0x00000347 Thumb Code 294 system_lpc17xx.o(.text) + init_Vibro 0x00000489 Thumb Code 48 vibro.o(.text) + VibroOut 0x000004b9 Thumb Code 96 vibro.o(.text) + CalcAmpN 0x00000519 Thumb Code 246 vibro.o(.text) + cheng 0x0000060f Thumb Code 272 vibro.o(.text) + Latch_Event 0x00000779 Thumb Code 84 cyclessync.o(.text) + QEI_IRQHandler 0x000007cd Thumb Code 58 cyclessync.o(.text) + SetIntLatch 0x00000807 Thumb Code 18 cyclessync.o(.text) + SwitchRefMeandInt 0x00000819 Thumb Code 30 cyclessync.o(.text) + EINT3_IRQHandler 0x00000837 Thumb Code 34 cyclessync.o(.text) + IntLatch_IRQHandler 0x00000859 Thumb Code 24 cyclessync.o(.text) + SwitchMode 0x00000871 Thumb Code 198 cyclessync.o(.text) + ServiceTime 0x00000937 Thumb Code 90 cyclessync.o(.text) + WDTFeed 0x00000991 Thumb Code 12 cyclessync.o(.text) + CounterIquiryCycle_Init 0x0000099d Thumb Code 80 cyclessync.o(.text) + TIMER0_IRQHandler 0x000009ed Thumb Code 102 cyclessync.o(.text) + ExtLatch_Init 0x00000a53 Thumb Code 144 cyclessync.o(.text) + IntLatch_Init 0x00000ae3 Thumb Code 74 cyclessync.o(.text) + WDTInit 0x00000b2d Thumb Code 32 cyclessync.o(.text) + SetSpeedPeriod 0x00000bf1 Thumb Code 66 commandset.o(.text) + B_Delta_BINS 0x00000c33 Thumb Code 38 commandset.o(.text) + B_Delta_SF 0x00000c59 Thumb Code 72 commandset.o(.text) + B_Delta_PS_execution 0x00000ca1 Thumb Code 142 commandset.o(.text) + M_Mirror 0x00000d2f Thumb Code 52 commandset.o(.text) + Mk_Ask1 0x00000d63 Thumb Code 38 commandset.o(.text) + Mk_AskDev 0x00000d89 Thumb Code 38 commandset.o(.text) + GLD_Output 0x00000daf Thumb Code 96 commandset.o(.text) + B_Dev_Mode 0x00000e0f Thumb Code 22 commandset.o(.text) + B_BIT_Mode 0x00000e25 Thumb Code 98 commandset.o(.text) + M_Stimul 0x00000e87 Thumb Code 60 commandset.o(.text) + M_Status 0x00000ec3 Thumb Code 48 commandset.o(.text) + M_Clear 0x00000ef3 Thumb Code 8 commandset.o(.text) + M_Tmp_W 0x00000efb Thumb Code 8 commandset.o(.text) + M_Tmp_R 0x00000f03 Thumb Code 2 commandset.o(.text) + M_ADC_R 0x00000f05 Thumb Code 54 commandset.o(.text) + M_Cnt_R 0x00000f3b Thumb Code 48 commandset.o(.text) + M_Ctl_R 0x00000f6b Thumb Code 66 commandset.o(.text) + M_Ctl_M 0x00000fad Thumb Code 242 commandset.o(.text) + M_Flg_R 0x0000109f Thumb Code 26 commandset.o(.text) + M_Vib_W 0x000010b9 Thumb Code 52 commandset.o(.text) + M_Gph_W 0x000010ed Thumb Code 46 commandset.o(.text) + M_Rate 0x0000111b Thumb Code 386 commandset.o(.text) + M_Reset 0x0000129d Thumb Code 4 commandset.o(.text) + M_Param_R 0x000012a1 Thumb Code 34 commandset.o(.text) + M_Param_W 0x000012c3 Thumb Code 42 commandset.o(.text) + M_LdPar_F 0x000012ed Thumb Code 30 commandset.o(.text) + M_LdPar_D 0x0000130b Thumb Code 14 commandset.o(.text) + M_Start 0x00001319 Thumb Code 20 commandset.o(.text) + M_Stop 0x0000132d Thumb Code 20 commandset.o(.text) + M_Pulse 0x00001341 Thumb Code 20 commandset.o(.text) + B_Rate 0x00001355 Thumb Code 2 commandset.o(.text) + B_Delta 0x00001357 Thumb Code 2 commandset.o(.text) + D_Period_W 0x00001359 Thumb Code 2 commandset.o(.text) + exec_CMD 0x0000135b Thumb Code 750 commandset.o(.text) + decode_CMD 0x00001649 Thumb Code 208 commandset.o(.text) + VibroDither_Set 0x00001759 Thumb Code 26 dither_reg.o(.text) + VibroDither_SwitchOn 0x00001773 Thumb Code 10 dither_reg.o(.text) + VibroDither_SwitchOff 0x0000177d Thumb Code 10 dither_reg.o(.text) + VB_MeanderDelay 0x00001787 Thumb Code 164 dither_reg.o(.text) + VB_PhaseDetectorRate 0x0000182b Thumb Code 40 dither_reg.o(.text) + clc_Dith_regulator 0x00001853 Thumb Code 664 dither_reg.o(.text) + clc_Noise_regulator 0x00001aeb Thumb Code 546 dither_reg.o(.text) + clc_OutFreq_regulator 0x00001d0d Thumb Code 574 dither_reg.o(.text) + VibroDither_Init 0x00001f4b Thumb Code 240 dither_reg.o(.text) + init_Dither_reg 0x0000203b Thumb Code 98 dither_reg.o(.text) + check_lcc 0x000020b9 Thumb Code 54 el_lin.o(.text) + PacketSafing 0x000020ef Thumb Code 2 el_lin.o(.text) + Line_1_Rcv 0x000020f1 Thumb Code 354 el_lin.o(.text) + transm_DAT 0x00002253 Thumb Code 396 el_lin.o(.text) + DMA_Init 0x000023df Thumb Code 60 el_lin.o(.text) + UARTInit 0x0000241b Thumb Code 124 el_lin.o(.text) + UART1_Init 0x00002497 Thumb Code 198 el_lin.o(.text) + UART1_SendByte 0x0000255d Thumb Code 6 el_lin.o(.text) + UART_SwitchSpeed 0x00002563 Thumb Code 132 el_lin.o(.text) + UART_DMA_Init 0x000025e7 Thumb Code 258 el_lin.o(.text) + Led_init 0x00002719 Thumb Code 24 main.o(.text) + Led_Blink 0x00002731 Thumb Code 38 main.o(.text) + main 0x00002757 Thumb Code 854 main.o(.text) + init_PLC 0x00002b85 Thumb Code 300 plc_reg.o(.text) + PLC_MeanderDelay 0x00002cb1 Thumb Code 110 plc_reg.o(.text) + WP_PhaseDetectorRate 0x00002d1f Thumb Code 42 plc_reg.o(.text) + clc_PLC 0x00002d49 Thumb Code 1030 plc_reg.o(.text) + Signal_2_Oscill 0x0000314f Thumb Code 10 plc_reg.o(.text) + clc_WP_sin 0x00003159 Thumb Code 50 plc_reg.o(.text) + clc_HFO 0x000031c9 Thumb Code 368 hfo_reg.o(.text) + StaticTermoCompens 0x0000335d Thumb Code 102 thermocalc.o(.text) + DynamicDeltaCalc 0x000033c3 Thumb Code 212 thermocalc.o(.text) + clc_ThermoSensors 0x00003497 Thumb Code 648 thermocalc.o(.text) + DithFreqRangeCalc 0x0000371f Thumb Code 264 thermocalc.o(.text) + GLD_Stop 0x00003839 Thumb Code 34 cntrlgld.o(.text) + GLD_Status 0x0000385b Thumb Code 62 cntrlgld.o(.text) + Sts_Pause 0x00003899 Thumb Code 66 cntrlgld.o(.text) + Sts_Pulse 0x000038db Thumb Code 78 cntrlgld.o(.text) + Sts_Polling 0x00003929 Thumb Code 266 cntrlgld.o(.text) + GLD_Start 0x00003a33 Thumb Code 80 cntrlgld.o(.text) + GLD_Pulse 0x00003a83 Thumb Code 72 cntrlgld.o(.text) + contrl_GLD 0x00003acb Thumb Code 24 cntrlgld.o(.text) + init_VibroReduce 0x00003b39 Thumb Code 202 mathdsp.o(.text) + VibroReduce 0x00003c03 Thumb Code 242 mathdsp.o(.text) + DUP_Filt 0x00003cf5 Thumb Code 148 mathdsp.o(.text) + PLC_PhaseDetFilt 0x00003d89 Thumb Code 220 mathdsp.o(.text) + init_BandPass 0x00003e65 Thumb Code 686 mathdsp.o(.text) + HFO_MovAverFilt 0x00004113 Thumb Code 96 mathdsp.o(.text) + G_Photo_Exchange 0x00004199 Thumb Code 304 inputoutput.o(.text) + DAC_ADC_Exchange 0x000042c9 Thumb Code 98 inputoutput.o(.text) + ADC_Input 0x0000432b Thumb Code 96 inputoutput.o(.text) + DAC_Output 0x0000438b Thumb Code 2 inputoutput.o(.text) + G_Photo_Init 0x0000438d Thumb Code 76 inputoutput.o(.text) + DAC_ADC_Exchange_Init 0x000043d9 Thumb Code 214 inputoutput.o(.text) + DACInit 0x000044af Thumb Code 22 inputoutput.o(.text) + Out_G_photo 0x000044c5 Thumb Code 20 inputoutput.o(.text) + ResetBitsOfWord 0x00004511 Thumb Code 20 sip.o(.text) + interpolation 0x00004525 Thumb Code 66 sip.o(.text) + clc_Pulses 0x00004567 Thumb Code 684 sip.o(.text) + SOI_Init 0x00004813 Thumb Code 154 sip.o(.text) + init_DefaultParam 0x00004939 Thumb Code 278 parameters.o(.text) + FlashDMA_Init 0x00004a4f Thumb Code 52 parameters.o(.text) + LoadFlashParam 0x00004a83 Thumb Code 114 parameters.o(.text) + UART0_Init_m 0x00004b15 Thumb Code 70 console.o(.text) + UART0_SendByte_m 0x00004b5b Thumb Code 6 console.o(.text) + ClearBuffout 0x00004b61 Thumb Code 12 console.o(.text) + SendToBuffByte 0x00004b6d Thumb Code 34 console.o(.text) + SendToBuff 0x00004b8f Thumb Code 48 console.o(.text) + SendToBuffStr 0x00004bbf Thumb Code 44 console.o(.text) + TakeFromBuff 0x00004beb Thumb Code 56 console.o(.text) + ClearBuffIn 0x00004c23 Thumb Code 12 console.o(.text) + BuffDataReady 0x00004c2f Thumb Code 18 console.o(.text) + ReadDataInBuff 0x00004c41 Thumb Code 40 console.o(.text) + D_QEI 0x00004c89 Thumb Code 666 qei.o(.text) + VibroPush 0x00004f71 Thumb Code 14 global.o(.text) + VibroPull 0x00004f7f Thumb Code 10 global.o(.text) + ButtonLightUP 0x00004f89 Thumb Code 40 global.o(.text) + init_timer 0x00004fc5 Thumb Code 24 mtimer.o(.text) + enable_timer1 0x00004fdd Thumb Code 8 mtimer.o(.text) + TIMER1_IRQHandler 0x00004fe5 Thumb Code 112 mtimer.o(.text) + Init_TIM2 0x00005055 Thumb Code 20 mtimer.o(.text) + enable_timer2 0x00005069 Thumb Code 10 mtimer.o(.text) + TIMER2_IRQHandler 0x00005073 Thumb Code 54 mtimer.o(.text) + DACLInit 0x000050f1 Thumb Code 10 spi.o(.text) + SPI_Exchange 0x000050fb Thumb Code 436 spi.o(.text) + Init_SPI_Exchange 0x000052af Thumb Code 34 spi.o(.text) + Check 0x00005325 Thumb Code 78 command.o(.text) + CMD_Maintenance 0x00005373 Thumb Code 60 command.o(.text) + CMD_Rate 0x000053af Thumb Code 464 command.o(.text) + CMD_M_Control_D8 0x0000557f Thumb Code 342 command.o(.text) + CMD_M_Control_D9 0x000056d5 Thumb Code 128 command.o(.text) + CMD_M_Stymul 0x00005755 Thumb Code 78 command.o(.text) + Getlengf 0x000057a3 Thumb Code 108 command.o(.text) + Read_CMD 0x0000580f Thumb Code 352 command.o(.text) + UART0_Init 0x000059a9 Thumb Code 80 uart_m.o(.text) + UART1_Init_temp 0x000059f9 Thumb Code 80 uart_m.o(.text) + UART2_Init 0x00005a49 Thumb Code 86 uart_m.o(.text) + UART3_Init 0x00005a9f Thumb Code 98 uart_m.o(.text) + UART2_InitSet 0x00005b01 Thumb Code 98 uart_m.o(.text) + UART3_InitSet 0x00005b63 Thumb Code 98 uart_m.o(.text) + UART_InitSet 0x00005bc5 Thumb Code 328 uart_m.o(.text) + UART0_SendByte 0x00005d0d Thumb Code 20 uart_m.o(.text) + UART0_GetChar 0x00005d21 Thumb Code 20 uart_m.o(.text) + UART1_GetChar 0x00005d35 Thumb Code 20 uart_m.o(.text) + UART2_GetChar 0x00005d49 Thumb Code 20 uart_m.o(.text) + UART3_GetChar 0x00005d5d Thumb Code 20 uart_m.o(.text) + UART0_Chek 0x00005d71 Thumb Code 18 uart_m.o(.text) + UART1_Chek 0x00005d83 Thumb Code 66 uart_m.o(.text) + UART2_Chek 0x00005dc5 Thumb Code 18 uart_m.o(.text) + UART3_Chek 0x00005dd7 Thumb Code 18 uart_m.o(.text) + UART0_SendString 0x00005de9 Thumb Code 22 uart_m.o(.text) + UART2_SendByte 0x00005dff Thumb Code 20 uart_m.o(.text) + UART0_SendChar 0x00005e13 Thumb Code 124 uart_m.o(.text) + Delay 0x00005e8f Thumb Code 2 uart_m.o(.text) + ClrDeUART0 0x00005e91 Thumb Code 36 uart_m.o(.text) + SetDeUART0 0x00005eb5 Thumb Code 36 uart_m.o(.text) + Concol 0x00005ed9 Thumb Code 130 uart_m.o(.text) + Concol1 0x00005f5b Thumb Code 102 uart_m.o(.text) + ClrDeUART1 0x00005fc1 Thumb Code 38 uart_m.o(.text) + SetDeUART1 0x00005fe7 Thumb Code 38 uart_m.o(.text) + Concol1Fast 0x0000600d Thumb Code 138 uart_m.o(.text) + ClrDeUART2 0x00006097 Thumb Code 38 uart_m.o(.text) + SetDeUART2 0x000060bd Thumb Code 38 uart_m.o(.text) + Concol2 0x000060e3 Thumb Code 130 uart_m.o(.text) + ClrDeUART3 0x00006165 Thumb Code 38 uart_m.o(.text) + SetDeUART3 0x0000618b Thumb Code 130 uart_m.o(.text) + Concol3 0x0000620d Thumb Code 130 uart_m.o(.text) + Concol2M 0x0000628f Thumb Code 130 uart_m.o(.text) + WriteCon 0x00006311 Thumb Code 48 uart_m.o(.text) + WriteCon1 0x00006341 Thumb Code 48 uart_m.o(.text) + WriteConN 0x00006371 Thumb Code 50 uart_m.o(.text) + WriteCon2 0x000063a3 Thumb Code 48 uart_m.o(.text) + WriteCon3 0x000063d3 Thumb Code 48 uart_m.o(.text) + WriteConF 0x00006403 Thumb Code 46 uart_m.o(.text) + WriteConByte 0x00006431 Thumb Code 30 uart_m.o(.text) + WriteCon1Byte 0x0000644f Thumb Code 30 uart_m.o(.text) + WriteCon2Byte 0x0000646d Thumb Code 30 uart_m.o(.text) + WriteCon3Byte 0x0000648b Thumb Code 30 uart_m.o(.text) + WriteConByteF 0x000064a9 Thumb Code 46 uart_m.o(.text) + ReadCon 0x000064d7 Thumb Code 58 uart_m.o(.text) + ReadCon1 0x00006511 Thumb Code 58 uart_m.o(.text) + ReadCon2 0x0000654b Thumb Code 58 uart_m.o(.text) + ReadCon3 0x00006585 Thumb Code 58 uart_m.o(.text) + ReadChekCon 0x000065bf Thumb Code 162 uart_m.o(.text) + ReadChekCon1 0x00006661 Thumb Code 42 uart_m.o(.text) + ReadChekCon2 0x0000668b Thumb Code 42 uart_m.o(.text) + ReadChekCon3 0x000066b5 Thumb Code 42 uart_m.o(.text) + ChekInCon 0x000066df Thumb Code 20 uart_m.o(.text) + ChekInCon1 0x000066f3 Thumb Code 20 uart_m.o(.text) + ChekInCon2 0x00006707 Thumb Code 20 uart_m.o(.text) + ChekInCon3 0x0000671b Thumb Code 20 uart_m.o(.text) + ChekOutCon 0x0000672f Thumb Code 18 uart_m.o(.text) + ChekOutCon1 0x00006741 Thumb Code 18 uart_m.o(.text) + ChekOutCon2 0x00006753 Thumb Code 18 uart_m.o(.text) + ChekOutCon3 0x00006765 Thumb Code 18 uart_m.o(.text) + __aeabi_ldivmod 0x000067b5 Thumb Code 0 llsdiv.o(.text) + _ll_sdiv 0x000067b5 Thumb Code 72 llsdiv.o(.text) + srand 0x000067fd Thumb Code 42 rand.o(.text) + _rand_init 0x00006827 Thumb Code 4 rand.o(.text) + __aeabi_memcpy 0x00006839 Thumb Code 0 rt_memcpy_v6.o(.text) + __rt_memcpy 0x00006839 Thumb Code 138 rt_memcpy_v6.o(.text) + _memcpy_lastbytes 0x0000689f Thumb Code 0 rt_memcpy_v6.o(.text) + __use_two_region_memory 0x000068c3 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x000068c5 Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x000068c7 Thumb Code 2 heapauxi.o(.text) + __aeabi_uldivmod 0x000068c9 Thumb Code 0 lludivv7m.o(.text) + _ll_udiv 0x000068c9 Thumb Code 238 lludivv7m.o(.text) + __read_errno 0x000069b7 Thumb Code 10 _rserrno.o(.text) + __set_errno 0x000069c1 Thumb Code 12 _rserrno.o(.text) + __aeabi_memcpy4 0x000069cd Thumb Code 0 rt_memcpy_w.o(.text) + __aeabi_memcpy8 0x000069cd Thumb Code 0 rt_memcpy_w.o(.text) + __rt_memcpy_w 0x000069cd Thumb Code 100 rt_memcpy_w.o(.text) + _memcpy_lastbytes_aligned 0x00006a15 Thumb Code 0 rt_memcpy_w.o(.text) + __aeabi_errno_addr 0x00006a31 Thumb Code 8 rt_errno_addr_intlibspace.o(.text) + __errno$intlibspace 0x00006a31 Thumb Code 0 rt_errno_addr_intlibspace.o(.text) + __rt_errno_addr$intlibspace 0x00006a31 Thumb Code 0 rt_errno_addr_intlibspace.o(.text) + __user_libspace 0x00006a39 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x00006a39 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x00006a39 Thumb Code 0 libspace.o(.text) + __user_setup_stackheap 0x00006a41 Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x00006a8b Thumb Code 12 exit.o(.text) + __I$use$semihosting 0x00006a97 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x00006a97 Thumb Code 2 use_no_semi.o(.text) + __semihosting_library_function 0x00006a99 Thumb Code 0 indicate_semi.o(.text) + _sys_exit 0x00006a99 Thumb Code 8 sys_exit.o(.text) + Max_Saturation 0x00006aa5 Thumb Code 12 thermocalc.o(i.Max_Saturation) + __ARM_fpclassify 0x00006ab1 Thumb Code 40 fpclassify.o(i.__ARM_fpclassify) + __ieee754_rem_pio2 0x00006ad9 Thumb Code 828 rred.o(i.__ieee754_rem_pio2) + __kernel_cos 0x00006e61 Thumb Code 230 cos_i.o(i.__kernel_cos) + __kernel_poly 0x00006f5d Thumb Code 170 poly.o(i.__kernel_poly) + __kernel_sin 0x00007009 Thumb Code 224 sin_i.o(i.__kernel_sin) + __mathlib_dbl_infnan 0x000070f5 Thumb Code 6 dunder.o(i.__mathlib_dbl_infnan) + __mathlib_dbl_invalid 0x000070fb Thumb Code 12 dunder.o(i.__mathlib_dbl_invalid) + __mathlib_dbl_underflow 0x00007109 Thumb Code 10 dunder.o(i.__mathlib_dbl_underflow) + cos 0x00007119 Thumb Code 148 cos.o(i.cos) + sin 0x000071b5 Thumb Code 150 sin.o(i.sin) + __aeabi_d2f 0x00007255 Thumb Code 0 d2f.o(x$fpl$d2f) + _d2f 0x00007255 Thumb Code 98 d2f.o(x$fpl$d2f) + __aeabi_dadd 0x000072b9 Thumb Code 0 daddsub_clz.o(x$fpl$dadd) + _dadd 0x000072b9 Thumb Code 332 daddsub_clz.o(x$fpl$dadd) + __fpl_dcheck_NaN1 0x00007409 Thumb Code 10 dcheck1.o(x$fpl$dcheck1) + __aeabi_ddiv 0x00007419 Thumb Code 0 ddiv.o(x$fpl$ddiv) + _ddiv 0x00007419 Thumb Code 552 ddiv.o(x$fpl$ddiv) + __aeabi_d2iz 0x000076c9 Thumb Code 0 dfix.o(x$fpl$dfix) + _dfix 0x000076c9 Thumb Code 94 dfix.o(x$fpl$dfix) + __aeabi_i2d 0x00007727 Thumb Code 0 dflt_clz.o(x$fpl$dflt) + _dflt 0x00007727 Thumb Code 46 dflt_clz.o(x$fpl$dflt) + __aeabi_ui2d 0x00007755 Thumb Code 0 dflt_clz.o(x$fpl$dfltu) + _dfltu 0x00007755 Thumb Code 38 dflt_clz.o(x$fpl$dfltu) + __aeabi_dmul 0x0000777d Thumb Code 0 dmul.o(x$fpl$dmul) + _dmul 0x0000777d Thumb Code 332 dmul.o(x$fpl$dmul) + __fpl_dnaninf 0x000078d1 Thumb Code 156 dnaninf.o(x$fpl$dnaninf) + __fpl_dretinf 0x0000796d Thumb Code 12 dretinf.o(x$fpl$dretinf) + __aeabi_drsub 0x00007979 Thumb Code 0 daddsub_clz.o(x$fpl$drsb) + _drsb 0x00007979 Thumb Code 22 daddsub_clz.o(x$fpl$drsb) + __aeabi_dsub 0x00007991 Thumb Code 0 daddsub_clz.o(x$fpl$dsub) + _dsub 0x00007991 Thumb Code 464 daddsub_clz.o(x$fpl$dsub) + __aeabi_f2d 0x00007b65 Thumb Code 0 f2d.o(x$fpl$f2d) + _f2d 0x00007b65 Thumb Code 86 f2d.o(x$fpl$f2d) + __aeabi_fadd 0x00007bbd Thumb Code 0 faddsub_clz.o(x$fpl$fadd) + _fadd 0x00007bbd Thumb Code 196 faddsub_clz.o(x$fpl$fadd) + __aeabi_f2iz 0x00007c81 Thumb Code 0 ffix.o(x$fpl$ffix) + _ffix 0x00007c81 Thumb Code 54 ffix.o(x$fpl$ffix) + __aeabi_f2uiz 0x00007cb9 Thumb Code 0 ffixu.o(x$fpl$ffixu) + _ffixu 0x00007cb9 Thumb Code 62 ffixu.o(x$fpl$ffixu) + __aeabi_i2f 0x00007cf9 Thumb Code 0 fflt_clz.o(x$fpl$fflt) + _fflt 0x00007cf9 Thumb Code 48 fflt_clz.o(x$fpl$fflt) + __aeabi_ui2f 0x00007d29 Thumb Code 0 fflt_clz.o(x$fpl$ffltu) + _ffltu 0x00007d29 Thumb Code 38 fflt_clz.o(x$fpl$ffltu) + __aeabi_fmul 0x00007d51 Thumb Code 0 fmul.o(x$fpl$fmul) + _fmul 0x00007d51 Thumb Code 258 fmul.o(x$fpl$fmul) + __fpl_fnaninf 0x00007e53 Thumb Code 140 fnaninf.o(x$fpl$fnaninf) + __fpl_fretinf 0x00007edf Thumb Code 10 fretinf.o(x$fpl$fretinf) + __aeabi_frsub 0x00007ee9 Thumb Code 0 faddsub_clz.o(x$fpl$frsb) + _frsb 0x00007ee9 Thumb Code 20 faddsub_clz.o(x$fpl$frsb) + __aeabi_fsub 0x00007efd Thumb Code 0 faddsub_clz.o(x$fpl$fsub) + _fsub 0x00007efd Thumb Code 234 faddsub_clz.o(x$fpl$fsub) + __fpl_return_NaN 0x00007fe7 Thumb Code 100 retnan.o(x$fpl$retnan) + __ARM_scalbn 0x0000804b Thumb Code 92 scalbn.o(x$fpl$scalbn) + __fpl_cmpreturn 0x000080a7 Thumb Code 48 trapv.o(x$fpl$trapveneer) + __I$use$fp 0x000080d6 Number 0 usenofp.o(x$fpl$usenofp) + Region$$Table$$Base 0x000081f8 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x00008228 Number 0 anon$$obj.o(Region$$Table) + Sys_Clock 0x10000000 Data 4 cyclessync.o(.data) + Seconds 0x10000004 Data 4 cyclessync.o(.data) + time_1_Sec 0x10000008 Data 4 cyclessync.o(.data) + trm_cycl 0x1000000c Data 4 cyclessync.o(.data) + count 0x10000010 Data 4 cyclessync.o(.data) + PrevPeriod 0x10000014 Data 4 cyclessync.o(.data) + num 0x10000018 Data 4 cyclessync.o(.data) + Latch_Rdy 0x1000001c Data 4 cyclessync.o(.data) + LatchPhase 0x10000020 Data 4 cyclessync.o(.data) + Ext_Latch_ResetEnable 0x10000024 Data 4 cyclessync.o(.data) + data_Rdy 0x10000028 Data 4 cyclessync.o(.data) + Delay_UART_Enbl 0x1000002c Data 4 cyclessync.o(.data) + main_cycle_latch 0x10000030 Data 4 cyclessync.o(.data) + Out_main_cycle_latch 0x10000034 Data 4 cyclessync.o(.data) + T_latch 0x10000038 Data 4 cyclessync.o(.data) + Out_T_latch 0x1000003c Data 4 cyclessync.o(.data) + temp_T_latch 0x10000040 Data 4 cyclessync.o(.data) + WP_reg32 0x1000004c Data 4 plc_reg.o(.data) + WP_Phase_Det 0x10000050 Data 4 plc_reg.o(.data) + WP_reset_heating 0x10000054 Data 4 plc_reg.o(.data) + WP_reset_cooling 0x10000058 Data 4 plc_reg.o(.data) + MaxDelayPLC 0x1000005c Data 4 plc_reg.o(.data) + phase_Digital 0x10000060 Data 4 plc_reg.o(.data) + TermoCompens_Sum 0x1000008c Data 4 thermocalc.o(.data) + IsHeating 0x10000090 Data 4 thermocalc.o(.data) + TermoCompDelta 0x10000094 Data 4 thermocalc.o(.data) + Temp_Aver 0x10000098 Data 4 thermocalc.o(.data) + TempEvolution 0x1000009c Data 4 thermocalc.o(.data) + StartTermoCompens 0x100000a0 Data 4 thermocalc.o(.data) + BandPassType 0x100000c0 Data 1 mathdsp.o(.data) + highPls 0x100000c4 Data 4 mathdsp.o(.data) + lowPls 0x100000c8 Data 4 mathdsp.o(.data) + aDUP_2 0x100000cc Data 12 mathdsp.o(.data) + bDUP_2 0x100000d8 Data 12 mathdsp.o(.data) + Vibro_Filter_Aperture 0x100000e4 Data 4 mathdsp.o(.data) + Vibro_2_CountIn 0x100000e8 Data 4 mathdsp.o(.data) + I2CMasterState 0x10000104 Data 4 inputoutput.o(.data) + ExchangeErr 0x10000108 Data 4 inputoutput.o(.data) + InputIndexBO 0x10000114 Data 4 console.o(.data) + OutputIndexBO 0x10000118 Data 4 console.o(.data) + InputIndexBI 0x1000011c Data 4 console.o(.data) + OutputIndexBI 0x10000120 Data 4 console.o(.data) + Rate_Flag 0x10000124 Data 4 command.o(.data) + PC_Comand 0x10000128 Data 4 command.o(.data) + n 0x1000012c Data 4 command.o(.data) + CountBuFFIn 0x10000130 Data 4 command.o(.data) + ParamIn 0x10000134 Data 4 command.o(.data) + Err 0x10000138 Data 4 command.o(.data) + N 0x1000013c Data 4 command.o(.data) + CRC_N 0x10000140 Data 4 command.o(.data) + Param1 0x10000144 Data 4 command.o(.data) + Param2 0x10000148 Data 4 command.o(.data) + Param3 0x1000014c Data 4 command.o(.data) + Param4 0x10000150 Data 4 command.o(.data) + _arm_global_overflow::v 0x10000154 Data 4 dither_reg.o(.data__ZZ20_arm_global_overflowE1v) + Buff_32Point 0x10000158 Data 1024 qei.o(.bss) + Buff_16Point 0x10000558 Data 1024 qei.o(.bss) + Buff_16PointD 0x10000958 Data 1024 qei.o(.bss) + Buff_8Point 0x10000d58 Data 1024 qei.o(.bss) + Buff_1Point 0x10001158 Data 1024 qei.o(.bss) + Buff_Restored_sin 0x10001558 Data 1024 qei.o(.bss) + BuffTemp 0x10001958 Data 100 global.o(.bss) + Spi 0x100019bc Data 32 spi.o(.bss) + Buff_ADC_1 0x100019dc Data 1024 spi.o(.bss) + Buff_ADC_2 0x10001ddc Data 1024 spi.o(.bss) + Buff_ADC_3 0x100021dc Data 1024 spi.o(.bss) + Buff_ADC_4 0x100025dc Data 1024 spi.o(.bss) + Buff_ADC_5 0x100029dc Data 1024 spi.o(.bss) + Buff_AMP 0x10002ddc Data 1024 spi.o(.bss) + InCon 0x100031dc Data 1024 uart_m.o(.bss) + OutCon 0x100035dc Data 1024 uart_m.o(.bss) + InCon1 0x100039dc Data 1024 uart_m.o(.bss) + OutCon1 0x10003ddc Data 1024 uart_m.o(.bss) + InCon2 0x100041dc Data 1024 uart_m.o(.bss) + OutCon2 0x100045dc Data 1024 uart_m.o(.bss) + InCon3 0x100049dc Data 1024 uart_m.o(.bss) + OutCon3 0x10004ddc Data 1024 uart_m.o(.bss) + InCon2M 0x100051dc Data 64 uart_m.o(.bss) + OutCon2M 0x1000521c Data 64 uart_m.o(.bss) + InCon3M 0x1000525c Data 64 uart_m.o(.bss) + OutCon3M 0x1000529c Data 64 uart_m.o(.bss) + __libspace_start 0x100052dc Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x1000533c Data 0 libspace.o(.bss) + SystemCoreClock 0x2007c000 Data 4 system_lpc17xx.o(.data) + V1 0x2007c004 Data 4 vibro.o(.data) + Temp 0x2007c008 Data 4 vibro.o(.data) + Flag 0x2007c00c Data 4 vibro.o(.data) + FrecTemp 0x2007c010 Data 4 vibro.o(.data) + CMD_Mode 0x2007c024 Data 4 commandset.o(.data) + CMD_Code 0x2007c028 Data 4 commandset.o(.data) + wrk_period 0x2007c02c Data 4 commandset.o(.data) + blt_in_test 0x2007c030 Data 4 commandset.o(.data) + ScopeMode 0x2007c034 Data 4 commandset.o(.data) + RI_diff 0x2007c074 Data 4 dither_reg.o(.data) + MaxDelay 0x2007c078 Data 4 dither_reg.o(.data) + VB_tau_Ins 0x2007c07c Data 4 dither_reg.o(.data) + VB_Nmin0 0x2007c080 Data 4 dither_reg.o(.data) + VB_Nmax0 0x2007c084 Data 4 dither_reg.o(.data) + In_Flag 0x2007c088 Data 4 dither_reg.o(.data) + SwitchCntInq 0x2007c08c Data 4 dither_reg.o(.data) + accum_error 0x2007c090 Data 4 dither_reg.o(.data) + ph_error 0x2007c094 Data 4 dither_reg.o(.data) + accum_error_old 0x2007c098 Data 4 dither_reg.o(.data) + PhaseShift 0x2007c09c Data 4 dither_reg.o(.data) + temp2 0x2007c0a0 Data 4 dither_reg.o(.data) + temp3 0x2007c0a4 Data 4 dither_reg.o(.data) + rcv_num_byt 0x2007c0d4 Data 4 el_lin.o(.data) + rcv_num_byt_old 0x2007c0d8 Data 4 el_lin.o(.data) + rcv_Rdy 0x2007c0dc Data 4 el_lin.o(.data) + rx_buf_copy 0x2007c0e0 Data 4 el_lin.o(.data) + rcv_byt_copy 0x2007c0e4 Data 4 el_lin.o(.data) + trm_num_byt 0x2007c0e8 Data 4 el_lin.o(.data) + trm_rate 0x2007c0ec Data 4 el_lin.o(.data) + num_of_par 0x2007c0f0 Data 4 el_lin.o(.data) + trm_ena 0x2007c0f4 Data 4 el_lin.o(.data) + line_err 0x2007c0f8 Data 4 el_lin.o(.data) + line_sts 0x2007c0fc Data 4 el_lin.o(.data) + EnablLength 0x2007c100 Data 4 el_lin.o(.data) + EnablTx 0x2007c104 Data 4 el_lin.o(.data) + EnablDMA 0x2007c108 Data 4 el_lin.o(.data) + i1 0x2007c114 Data 4 main.o(.data) + IRQ_Counter 0x2007c118 Data 4 main.o(.data) + timer1_counter 0x2007c11c Data 4 main.o(.data) + temp111 0x2007c120 Data 4 main.o(.data) + temp 0x2007c124 Data 4 main.o(.data) + y 0x2007c128 Data 4 main.o(.data) + CuruAngleOld 0x2007c12c Data 4 main.o(.data) + LightUpCount 0x2007c130 Data 4 main.o(.data) + BackLightCount 0x2007c134 Data 4 main.o(.data) + secPuls 0x2007c138 Data 4 main.o(.data) + CountBI 0x2007c13c Data 4 main.o(.data) + CmmandIn 0x2007c140 Data 4 main.o(.data) + tt 0x2007c144 Data 4 main.o(.data) + th 0x2007c148 Data 4 main.o(.data) + paramV 0x2007c14c Data 4 main.o(.data) + flag 0x2007c150 Data 4 main.o(.data) + TIME 0x2007c154 Data 4 main.o(.data) + t 0x2007c158 Data 4 main.o(.data) + Sec 0x2007c15c Data 4 main.o(.data) + tmpSec 0x2007c160 Data 4 main.o(.data) + SEC 0x2007c164 Data 4 main.o(.data) + mSec 0x2007c168 Data 4 main.o(.data) + tempsec 0x2007c16c Data 4 main.o(.data) + DACF 0x2007c170 Data 4 main.o(.data) + K_DAC 0x2007c174 Data 4 main.o(.data) + LED_TEMP 0x2007c178 Data 4 main.o(.data) + SRgR 0x2007c180 Data 4 cntrlgld.o(.data) + RgConA 0x2007c184 Data 4 cntrlgld.o(.data) + RgConB 0x2007c188 Data 4 cntrlgld.o(.data) + Valid_Data 0x2007c18c Data 4 cntrlgld.o(.data) + ser_num 0x2007c190 Data 4 cntrlgld.o(.data) + Device_Mode 0x2007c194 Data 4 cntrlgld.o(.data) + Tab_Gld_Start 0x2007c198 Data 12 cntrlgld.o(.data) + Tab_Gld_Pulse 0x2007c1a4 Data 4 cntrlgld.o(.data) + Stk_Gld_Start 0x2007c1a8 Data 12 cntrlgld.o(.data) + gyro_Sts 0x2007c1b4 Data 4 cntrlgld.o(.data) + start_Rq 0x2007c1b8 Data 4 cntrlgld.o(.data) + start_Go 0x2007c1bc Data 4 cntrlgld.o(.data) + stop_Rq 0x2007c1c0 Data 4 cntrlgld.o(.data) + pulse_Rq 0x2007c1c4 Data 4 cntrlgld.o(.data) + pulse_Go 0x2007c1c8 Data 4 cntrlgld.o(.data) + state_index 0x2007c1cc Data 4 cntrlgld.o(.data) + sts_work 0x2007c1d0 Data 4 cntrlgld.o(.data) + sts_time 0x2007c1d4 Data 4 cntrlgld.o(.data) + attempt_Str 0x2007c1d8 Data 4 cntrlgld.o(.data) + BIT_number 0x2007c1dc Data 4 cntrlgld.o(.data) + Is_BIT 0x2007c1e0 Data 4 cntrlgld.o(.data) + Old_Cnt_Vib 0x2007c1f0 Data 4 sip.o(.data) + Old_Cnt 0x2007c1f4 Data 4 sip.o(.data) + RefMeand_Cnt_Dif 0x2007c1f8 Data 4 sip.o(.data) + PSdif_sum_Vib_32 0x2007c1fc Data 4 sip.o(.data) + PSdif_sum_Vib_64 0x2007c200 Data 8 sip.o(.data) + dif_Curr_32_Ext 0x2007c208 Data 4 sip.o(.data) + dif_Curr_32_previous 0x2007c20c Data 4 sip.o(.data) + temp22 0x2007c210 Data 4 sip.o(.data) + Curr_Cnt_Vib 0x2007c214 Data 4 sip.o(.data) + Cnt_curr 0x2007c218 Data 4 sip.o(.data) + Dif_Curr_Vib 0x2007c21c Data 4 sip.o(.data) + Dif_Curr_32 0x2007c220 Data 4 sip.o(.data) + Pulse_midl 0x2007c23c Data 4 qei.o(.data) + PulseHalf 0x2007c240 Data 4 qei.o(.data) + CuruAngle 0x2007c244 Data 4 qei.o(.data) + Dif_QEI 0x2007c248 Data 4 qei.o(.data) + FFF 0x2007c24c Data 4 qei.o(.data) + Pulse_8Point 0x2007c250 Data 4 qei.o(.data) + Pulse_16Point 0x2007c254 Data 4 qei.o(.data) + Pulse_32Point 0x2007c258 Data 4 qei.o(.data) + Pulse_16PointD 0x2007c25c Data 4 qei.o(.data) + Iras 0x2007c260 Data 4 qei.o(.data) + Temp_F_ras 0x2007c264 Data 4 qei.o(.data) + yy 0x2007c268 Data 4 qei.o(.data) + Cur_QEI 0x2007c26c Data 4 qei.o(.data) + Last_QEI 0x2007c270 Data 4 qei.o(.data) + VibroReg 0x2007c274 Data 4 global.o(.data) + Global_Time 0x2007c278 Data 4 global.o(.data) + Time_UART 0x2007c27c Data 4 global.o(.data) + Time_Sec 0x2007c280 Data 4 global.o(.data) + Time_vibro 0x2007c284 Data 4 global.o(.data) + Time_1kHz 0x2007c288 Data 4 global.o(.data) + MaxAmp 0x2007c28c Data 4 global.o(.data) + CountV31 0x2007c290 Data 4 mtimer.o(.data) + CountV255 0x2007c294 Data 4 mtimer.o(.data) + CountV64 0x2007c298 Data 4 mtimer.o(.data) + Temp_AMP 0x2007c29c Data 4 spi.o(.data) + Temp_ADC_2 0x2007c2a0 Data 4 spi.o(.data) + Temp_ADC_3 0x2007c2a4 Data 4 spi.o(.data) + Temp_ADC_4 0x2007c2a8 Data 4 spi.o(.data) + Temp_ADC_5 0x2007c2ac Data 4 spi.o(.data) + SinPLC 0x2007c2b0 Data 256 spi.o(.data) + UART0_BPS 0x2007c3b0 Data 4 uart_m.o(.data) + UART1_BPS 0x2007c3b4 Data 4 uart_m.o(.data) + UART2_BPS 0x2007c3b8 Data 4 uart_m.o(.data) + UART3_BPS 0x2007c3bc Data 4 uart_m.o(.data) + UART_LCR 0x2007c3c0 Data 4 uart_m.o(.data) + ConInPnt 0x2007c3c4 Data 4 uart_m.o(.data) + ConInCur 0x2007c3c8 Data 4 uart_m.o(.data) + ConOutPnt 0x2007c3cc Data 4 uart_m.o(.data) + ConOutCur 0x2007c3d0 Data 4 uart_m.o(.data) + ConInPnt1 0x2007c3d4 Data 4 uart_m.o(.data) + ConInCur1 0x2007c3d8 Data 4 uart_m.o(.data) + ConOutPnt1 0x2007c3dc Data 4 uart_m.o(.data) + ConOutCur1 0x2007c3e0 Data 4 uart_m.o(.data) + ConInPnt2 0x2007c3e4 Data 4 uart_m.o(.data) + ConInCur2 0x2007c3e8 Data 4 uart_m.o(.data) + ConOutPnt2 0x2007c3ec Data 4 uart_m.o(.data) + ConOutCur2 0x2007c3f0 Data 4 uart_m.o(.data) + ConInPnt3 0x2007c3f4 Data 4 uart_m.o(.data) + ConInCur3 0x2007c3f8 Data 4 uart_m.o(.data) + ConOutPnt3 0x2007c3fc Data 4 uart_m.o(.data) + ConOutCur3 0x2007c400 Data 4 uart_m.o(.data) + ConInPnt2M 0x2007c404 Data 4 uart_m.o(.data) + ConInCur2M 0x2007c408 Data 4 uart_m.o(.data) + ConOutPnt2M 0x2007c40c Data 4 uart_m.o(.data) + ConOutCur2M 0x2007c410 Data 4 uart_m.o(.data) + ConInPnt3M 0x2007c414 Data 4 uart_m.o(.data) + ConInCur3M 0x2007c418 Data 4 uart_m.o(.data) + ConOutPnt3M 0x2007c41c Data 4 uart_m.o(.data) + ConOutCur3M 0x2007c420 Data 4 uart_m.o(.data) + OutBufConCount 0x2007c424 Data 4 uart_m.o(.data) + OutBufCon1Count 0x2007c428 Data 4 uart_m.o(.data) + OutBufCon2Count 0x2007c42c Data 4 uart_m.o(.data) + OutBufCon3Count 0x2007c430 Data 4 uart_m.o(.data) + Main 0x2007c434 Data 112 vibro.o(.bss) + rcv_copy 0x2007c4a4 Data 64 el_lin.o(.bss) + rcv_buf 0x2007c4e4 Data 64 el_lin.o(.bss) + trm_buf 0x2007c524 Data 64 el_lin.o(.bss) + addr_param 0x2007c564 Data 64 el_lin.o(.bss) + size_param 0x2007c5a4 Data 64 el_lin.o(.bss) + LLI0_TypeDef 0x2007c5e4 Data 16 el_lin.o(.bss) + LLI1_TypeDef 0x2007c5f4 Data 16 el_lin.o(.bss) + sin_func 0x2007c604 Data 400 plc_reg.o(.bss) + dThermoHeatDeltaPer_dTermo 0x2007c794 Data 56 thermocalc.o(.bss) + dThermoCoolDeltaPer_dTermo 0x2007c7cc Data 56 thermocalc.o(.bss) + dFuncPer_dTermo 0x2007c804 Data 56 thermocalc.o(.bss) + Device_blk 0x2007c83c Data 684 cntrlgld.o(.bss) + BufInMovAverPls 0x2007cae8 Data 268 mathdsp.o(.bss) + BufInMovAverMns 0x2007cbf4 Data 268 mathdsp.o(.bss) + BufInMovAverPls_2 0x2007cd00 Data 268 mathdsp.o(.bss) + BufInMovAverMns_2 0x2007ce0c Data 268 mathdsp.o(.bss) + hMovAver 0x2007cf18 Data 268 mathdsp.o(.bss) + aPLC 0x2007d024 Data 12 mathdsp.o(.bss) + bPLC 0x2007d030 Data 12 mathdsp.o(.bss) + aDUP 0x2007d03c Data 12 mathdsp.o(.bss) + bDUP 0x2007d048 Data 12 mathdsp.o(.bss) + Input 0x2007d190 Data 16 inputoutput.o(.bss) + Output 0x2007d1a0 Data 160 inputoutput.o(.bss) + I2CMasterBuffer 0x2007d240 Data 24 inputoutput.o(.bss) + BuffOut 0x2007d258 Data 4096 console.o(.bss) + BuffIn 0x2007e258 Data 4096 console.o(.bss) + _random_number_data 0x2007f258 Data 228 rand.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x000000c5 + + Load Region LR_IROM1 (Base: 0x00000000, Size: 0x000087b4, Max: 0x00027fff, ABSOLUTE, COMPRESSED[0x00008348]) + + Execution Region ER_IROM1 (Base: 0x00000000, Size: 0x00008228, Max: 0x00027fff, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x00000000 0x000000c4 Data RO 3 RESET startup_lpc17xx.o + 0x000000c4 0x00000008 Code RO 825 * !!!main c_w.l(__main.o) + 0x000000cc 0x00000034 Code RO 1117 !!!scatter c_w.l(__scatter.o) + 0x00000100 0x0000005a Code RO 1115 !!dczerorl2 c_w.l(__dczerorl2.o) + 0x0000015a 0x00000002 PAD + 0x0000015c 0x0000001c Code RO 1119 !!handler_zi c_w.l(__scatter_zi.o) + 0x00000178 0x00000002 Code RO 1032 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x0000017a 0x00000000 Code RO 893 .ARM.Collect$$libinit$$00000002 c_w.l(libinit2.o) + 0x0000017a 0x00000000 Code RO 895 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x0000017a 0x00000000 Code RO 898 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x0000017a 0x00000000 Code RO 900 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x0000017a 0x00000004 Code RO 901 .ARM.Collect$$libinit$$0000000D c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 902 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 905 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 907 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 909 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 911 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 913 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 915 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 917 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 919 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 921 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 923 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 925 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 929 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 931 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 933 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x0000017e 0x00000000 Code RO 935 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x0000017e 0x00000002 Code RO 936 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x00000180 0x00000002 Code RO 1079 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x00000182 0x00000000 Code RO 1086 .ARM.Collect$$libshutdown$$00000003 c_w.l(libshutdown2.o) + 0x00000182 0x00000000 Code RO 1089 .ARM.Collect$$libshutdown$$00000006 c_w.l(libshutdown2.o) + 0x00000182 0x00000000 Code RO 1092 .ARM.Collect$$libshutdown$$00000009 c_w.l(libshutdown2.o) + 0x00000182 0x00000000 Code RO 1094 .ARM.Collect$$libshutdown$$0000000B c_w.l(libshutdown2.o) + 0x00000182 0x00000000 Code RO 1097 .ARM.Collect$$libshutdown$$0000000E c_w.l(libshutdown2.o) + 0x00000182 0x00000002 Code RO 1098 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) + 0x00000184 0x00000000 Code RO 885 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x00000184 0x00000000 Code RO 975 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x00000184 0x00000006 Code RO 987 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x0000018a 0x00000000 Code RO 977 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x0000018a 0x00000004 Code RO 978 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x0000018e 0x00000000 Code RO 980 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x0000018e 0x00000008 Code RO 981 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x00000196 0x00000002 Code RO 1037 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x00000198 0x00000000 Code RO 1055 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x00000198 0x00000004 Code RO 1056 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x0000019c 0x00000006 Code RO 1057 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x000001a2 0x00000002 PAD + 0x000001a4 0x00000034 Code RO 816 .emb_text c_w.l(rand.o) + 0x000001d8 0x0000003c Code RO 4 .text startup_lpc17xx.o + 0x00000214 0x00000274 Code RO 25 .text system_lpc17xx.o + 0x00000488 0x000002f0 Code RO 60 .text vibro.o + 0x00000778 0x00000478 Code RO 140 .text cyclessync.o + 0x00000bf0 0x00000b68 Code RO 175 .text commandset.o + 0x00001758 0x00000960 Code RO 239 .text dither_reg.o + 0x000020b8 0x00000660 Code RO 314 .text el_lin.o + 0x00002718 0x0000046c Code RO 346 .text main.o + 0x00002b84 0x00000644 Code RO 407 .text plc_reg.o + 0x000031c8 0x00000194 Code RO 440 .text hfo_reg.o + 0x0000335c 0x000004dc Code RO 458 .text thermocalc.o + 0x00003838 0x00000300 Code RO 499 .text cntrlgld.o + 0x00003b38 0x00000660 Code RO 546 .text mathdsp.o + 0x00004198 0x00000378 Code RO 570 .text inputoutput.o + 0x00004510 0x00000428 Code RO 598 .text sip.o + 0x00004938 0x000001dc Code RO 629 .text parameters.o + 0x00004b14 0x00000174 Code RO 649 .text console.o + 0x00004c88 0x000002e8 Code RO 671 .text qei.o + 0x00004f70 0x00000054 Code RO 698 .text global.o + 0x00004fc4 0x0000012c Code RO 719 .text mtimer.o + 0x000050f0 0x00000234 Code RO 745 .text spi.o + 0x00005324 0x00000684 Code RO 768 .text command.o + 0x000059a8 0x00000e0c Code RO 790 .text uart_m.o + 0x000067b4 0x00000048 Code RO 814 .text c_w.l(llsdiv.o) + 0x000067fc 0x0000003c Code RO 817 .text c_w.l(rand.o) + 0x00006838 0x0000008a Code RO 821 .text c_w.l(rt_memcpy_v6.o) + 0x000068c2 0x00000006 Code RO 823 .text c_w.l(heapauxi.o) + 0x000068c8 0x000000ee Code RO 886 .text c_w.l(lludivv7m.o) + 0x000069b6 0x00000016 Code RO 888 .text c_w.l(_rserrno.o) + 0x000069cc 0x00000064 Code RO 890 .text c_w.l(rt_memcpy_w.o) + 0x00006a30 0x00000008 Code RO 996 .text c_w.l(rt_errno_addr_intlibspace.o) + 0x00006a38 0x00000008 Code RO 1014 .text c_w.l(libspace.o) + 0x00006a40 0x0000004a Code RO 1017 .text c_w.l(sys_stackheap_outer.o) + 0x00006a8a 0x0000000c Code RO 1021 .text c_w.l(exit.o) + 0x00006a96 0x00000002 Code RO 1051 .text c_w.l(use_no_semi.o) + 0x00006a98 0x00000000 Code RO 1053 .text c_w.l(indicate_semi.o) + 0x00006a98 0x0000000c Code RO 1071 .text c_w.l(sys_exit.o) + 0x00006aa4 0x0000000c Code RO 474 i.Max_Saturation thermocalc.o + 0x00006ab0 0x00000028 Code RO 1010 i.__ARM_fpclassify m_ws.l(fpclassify.o) + 0x00006ad8 0x00000388 Code RO 963 i.__ieee754_rem_pio2 m_ws.l(rred.o) + 0x00006e60 0x000000fc Code RO 946 i.__kernel_cos m_ws.l(cos_i.o) + 0x00006f5c 0x000000aa Code RO 1012 i.__kernel_poly m_ws.l(poly.o) + 0x00007006 0x00000002 PAD + 0x00007008 0x000000ec Code RO 968 i.__kernel_sin m_ws.l(sin_i.o) + 0x000070f4 0x00000006 Code RO 950 i.__mathlib_dbl_infnan m_ws.l(dunder.o) + 0x000070fa 0x0000000c Code RO 952 i.__mathlib_dbl_invalid m_ws.l(dunder.o) + 0x00007106 0x00000002 PAD + 0x00007108 0x00000010 Code RO 955 i.__mathlib_dbl_underflow m_ws.l(dunder.o) + 0x00007118 0x0000009c Code RO 870 i.cos m_ws.l(cos.o) + 0x000071b4 0x000000a0 Code RO 878 i.sin m_ws.l(sin.o) + 0x00007254 0x00000062 Code RO 827 x$fpl$d2f fz_ws.l(d2f.o) + 0x000072b6 0x00000002 PAD + 0x000072b8 0x00000150 Code RO 829 x$fpl$dadd fz_ws.l(daddsub_clz.o) + 0x00007408 0x00000010 Code RO 1033 x$fpl$dcheck1 fz_ws.l(dcheck1.o) + 0x00007418 0x000002b0 Code RO 836 x$fpl$ddiv fz_ws.l(ddiv.o) + 0x000076c8 0x0000005e Code RO 839 x$fpl$dfix fz_ws.l(dfix.o) + 0x00007726 0x0000002e Code RO 1001 x$fpl$dflt fz_ws.l(dflt_clz.o) + 0x00007754 0x00000026 Code RO 1000 x$fpl$dfltu fz_ws.l(dflt_clz.o) + 0x0000777a 0x00000002 PAD + 0x0000777c 0x00000154 Code RO 843 x$fpl$dmul fz_ws.l(dmul.o) + 0x000078d0 0x0000009c Code RO 937 x$fpl$dnaninf fz_ws.l(dnaninf.o) + 0x0000796c 0x0000000c Code RO 939 x$fpl$dretinf fz_ws.l(dretinf.o) + 0x00007978 0x00000016 Code RO 830 x$fpl$drsb fz_ws.l(daddsub_clz.o) + 0x0000798e 0x00000002 PAD + 0x00007990 0x000001d4 Code RO 831 x$fpl$dsub fz_ws.l(daddsub_clz.o) + 0x00007b64 0x00000056 Code RO 845 x$fpl$f2d fz_ws.l(f2d.o) + 0x00007bba 0x00000002 PAD + 0x00007bbc 0x000000c4 Code RO 847 x$fpl$fadd fz_ws.l(faddsub_clz.o) + 0x00007c80 0x00000036 Code RO 853 x$fpl$ffix fz_ws.l(ffix.o) + 0x00007cb6 0x00000002 PAD + 0x00007cb8 0x0000003e Code RO 857 x$fpl$ffixu fz_ws.l(ffixu.o) + 0x00007cf6 0x00000002 PAD + 0x00007cf8 0x00000030 Code RO 862 x$fpl$fflt fz_ws.l(fflt_clz.o) + 0x00007d28 0x00000026 Code RO 861 x$fpl$ffltu fz_ws.l(fflt_clz.o) + 0x00007d4e 0x00000002 PAD + 0x00007d50 0x00000102 Code RO 867 x$fpl$fmul fz_ws.l(fmul.o) + 0x00007e52 0x0000008c Code RO 941 x$fpl$fnaninf fz_ws.l(fnaninf.o) + 0x00007ede 0x0000000a Code RO 943 x$fpl$fretinf fz_ws.l(fretinf.o) + 0x00007ee8 0x00000014 Code RO 848 x$fpl$frsb fz_ws.l(faddsub_clz.o) + 0x00007efc 0x000000ea Code RO 849 x$fpl$fsub fz_ws.l(faddsub_clz.o) + 0x00007fe6 0x00000064 Code RO 1049 x$fpl$retnan fz_ws.l(retnan.o) + 0x0000804a 0x0000005c Code RO 1008 x$fpl$scalbn fz_ws.l(scalbn.o) + 0x000080a6 0x00000030 Code RO 1069 x$fpl$trapveneer fz_ws.l(trapv.o) + 0x000080d6 0x00000000 Code RO 945 x$fpl$usenofp fz_ws.l(usenofp.o) + 0x000080d6 0x00000002 PAD + 0x000080d8 0x00000030 Data RO 947 .constdata m_ws.l(cos_i.o) + 0x00008108 0x000000c8 Data RO 965 .constdata m_ws.l(rred.o) + 0x000081d0 0x00000028 Data RO 969 .constdata m_ws.l(sin_i.o) + 0x000081f8 0x00000030 Data RO 1113 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Base: 0x10000000, Size: 0x00005340, Max: 0x00008000, ABSOLUTE, UNINIT, COMPRESSED[0x00000034]) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x10000000 0x0000004c Data RW 141 .data cyclessync.o + 0x1000004c 0x00000040 Data RW 409 .data plc_reg.o + 0x1000008c 0x00000030 Data RW 460 .data thermocalc.o + 0x100000bc 0x00000004 PAD + 0x100000c0 0x00000044 Data RW 548 .data mathdsp.o + 0x10000104 0x00000010 Data RW 572 .data inputoutput.o + 0x10000114 0x00000010 Data RW 651 .data console.o + 0x10000124 0x00000030 Data RW 769 .data command.o + 0x10000154 0x00000004 Data RW 254 .data__ZZ20_arm_global_overflowE1v dither_reg.o + 0x10000158 0x00001800 Zero RW 672 .bss qei.o + 0x10001958 0x00000064 Zero RW 699 .bss global.o + 0x100019bc 0x00001820 Zero RW 746 .bss spi.o + 0x100031dc 0x00002100 Zero RW 791 .bss uart_m.o + 0x100052dc 0x00000060 Zero RW 1015 .bss c_w.l(libspace.o) + 0x1000533c 0x00000004 PAD + 0x10005340 0x00000000 Zero RW 2 HEAP startup_lpc17xx.o + + + Execution Region RW_IRAM2 (Base: 0x2007c000, Size: 0x00005340, Max: 0x00008000, ABSOLUTE, COMPRESSED[0x000000ec]) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x2007c000 0x00000004 Data RW 26 .data system_lpc17xx.o + 0x2007c004 0x00000020 Data RW 62 .data vibro.o + 0x2007c024 0x00000050 Data RW 177 .data commandset.o + 0x2007c074 0x00000060 Data RW 240 .data dither_reg.o + 0x2007c0d4 0x00000040 Data RW 316 .data el_lin.o + 0x2007c114 0x00000068 Data RW 347 .data main.o + 0x2007c17c 0x00000004 Data RW 441 .data hfo_reg.o + 0x2007c180 0x0000006c Data RW 501 .data cntrlgld.o + 0x2007c1ec 0x00000004 PAD + 0x2007c1f0 0x0000004c Data RW 599 .data sip.o + 0x2007c23c 0x00000038 Data RW 673 .data qei.o + 0x2007c274 0x0000001c Data RW 700 .data global.o + 0x2007c290 0x0000000c Data RW 720 .data mtimer.o + 0x2007c29c 0x00000114 Data RW 747 .data spi.o + 0x2007c3b0 0x00000084 Data RW 792 .data uart_m.o + 0x2007c434 0x00000070 Zero RW 61 .bss vibro.o + 0x2007c4a4 0x00000160 Zero RW 315 .bss el_lin.o + 0x2007c604 0x00000190 Zero RW 408 .bss plc_reg.o + 0x2007c794 0x000000a8 Zero RW 459 .bss thermocalc.o + 0x2007c83c 0x000002ac Zero RW 500 .bss cntrlgld.o + 0x2007cae8 0x000006a8 Zero RW 547 .bss mathdsp.o + 0x2007d190 0x000000c8 Zero RW 571 .bss inputoutput.o + 0x2007d258 0x00002000 Zero RW 650 .bss console.o + 0x2007f258 0x000000e4 Zero RW 818 .bss c_w.l(rand.o) + 0x2007f33c 0x00000004 PAD + 0x2007f340 0x00002000 Zero RW 1 STACK startup_lpc17xx.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 768 86 0 108 684 9337 cntrlgld.o + 1668 94 0 48 0 3402 command.o + 2920 306 0 80 0 9737 commandset.o + 372 32 0 16 8192 2674 console.o + 0 0 0 0 0 4504 core_cm3.o + 1144 124 0 76 0 20328 cyclessync.o + 2400 210 0 100 0 10406 dither_reg.o + 1632 148 0 64 352 20536 el_lin.o + 84 20 0 28 100 1387 global.o + 404 36 0 4 0 1386 hfo_reg.o + 888 56 0 16 200 4313 inputoutput.o + 1132 216 0 104 0 2927 main.o + 1632 150 0 68 1704 5238 mathdsp.o + 300 50 0 12 0 17824 mtimer.o + 476 32 0 0 0 1125 parameters.o + 1604 178 0 64 400 5798 plc_reg.o + 744 78 0 56 6144 1891 qei.o + 1064 140 0 76 0 18599 sip.o + 564 84 0 276 6176 2296 spi.o + 60 22 196 0 8192 884 startup_lpc17xx.o + 628 28 0 4 0 1049 system_lpc17xx.o + 1256 124 0 48 168 4707 thermocalc.o + 3596 322 0 132 8448 12862 uart_m.o + 752 90 0 32 112 17871 vibro.o + + ---------------------------------------------------------------------- + 26088 2626 244 1420 40872 181081 Object Totals + 0 0 48 0 0 0 (incl. Generated) + 0 0 0 8 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 90 0 0 0 0 0 __dczerorl2.o + 8 0 0 0 0 68 __main.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 52 8 0 0 0 0 __scatter.o + 28 0 0 0 0 0 __scatter_zi.o + 22 0 0 0 0 100 _rserrno.o + 12 0 0 0 0 72 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 2 0 0 0 0 0 libinit.o + 6 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 72 0 0 0 0 76 llsdiv.o + 238 0 0 0 0 100 lludivv7m.o + 112 18 0 0 228 160 rand.o + 8 4 0 0 0 68 rt_errno_addr_intlibspace.o + 138 0 0 0 0 68 rt_memcpy_v6.o + 100 0 0 0 0 80 rt_memcpy_w.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 98 4 0 0 0 92 d2f.o + 826 16 0 0 0 348 daddsub_clz.o + 16 4 0 0 0 68 dcheck1.o + 688 140 0 0 0 208 ddiv.o + 94 4 0 0 0 92 dfix.o + 84 0 0 0 0 136 dflt_clz.o + 340 12 0 0 0 104 dmul.o + 156 4 0 0 0 92 dnaninf.o + 12 0 0 0 0 68 dretinf.o + 86 4 0 0 0 84 f2d.o + 450 8 0 0 0 236 faddsub_clz.o + 54 4 0 0 0 84 ffix.o + 62 4 0 0 0 84 ffixu.o + 86 0 0 0 0 136 fflt_clz.o + 258 4 0 0 0 84 fmul.o + 140 4 0 0 0 84 fnaninf.o + 10 0 0 0 0 68 fretinf.o + 100 0 0 0 0 68 retnan.o + 92 0 0 0 0 68 scalbn.o + 48 0 0 0 0 68 trapv.o + 0 0 0 0 0 0 usenofp.o + 156 8 0 0 0 104 cos.o + 252 22 48 0 0 124 cos_i.o + 34 6 0 0 0 204 dunder.o + 40 0 0 0 0 68 fpclassify.o + 170 0 0 0 0 96 poly.o + 904 76 200 0 0 140 rred.o + 160 10 0 0 0 108 sin.o + 236 12 40 0 0 128 sin_i.o + + ---------------------------------------------------------------------- + 6700 384 288 0 332 4472 Library Totals + 24 0 0 0 8 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 1024 38 0 0 324 1228 c_w.l + 3700 212 0 0 0 2272 fz_ws.l + 1952 134 288 0 0 972 m_ws.l + + ---------------------------------------------------------------------- + 6700 384 288 0 332 4472 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 32788 3010 532 1420 41204 180817 Grand Totals + 32788 3010 532 288 41204 180817 ELF Image Totals (compressed) + 32788 3010 532 288 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 33320 ( 32.54kB) + Total RW Size (RW Data + ZI Data) 42624 ( 41.63kB) + Total ROM Size (Code + RO Data + RW Data) 33608 ( 32.82kB) + +============================================================================== +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/List/startup_lpc17xx.lst --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/List/startup_lpc17xx.lst Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1200 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;/****************************************************** + *********************** + 2 00000000 ; * @file: startup_LPC17xx.s + 3 00000000 ; * @purpose: CMSIS Cortex-M3 Core Device Startup File + 4 00000000 ; * for the NXP LPC17xx Device Series + 5 00000000 ; * @version: V1.02 + 6 00000000 ; * @date: 27. July 2009 + 7 00000000 ; *------- <<< Use Configuration Wizard in Context Menu + >>> ------------------ + 8 00000000 ; * + 9 00000000 ; * Copyright (C) 2009 ARM Limited. All rights reserved. + + 10 00000000 ; * ARM Limited (ARM) is supplying this software for use + with Cortex-M3 + 11 00000000 ; * processor based microcontrollers. This file can be + freely distributed + 12 00000000 ; * within development tools that are supporting such AR + M based processors. + 13 00000000 ; * + 14 00000000 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, W + HETHER EXPRESS, IMPLIED + 15 00000000 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED + WARRANTIES OF + 16 00000000 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + APPLY TO THIS SOFTWARE. + 17 00000000 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR S + PECIAL, INCIDENTAL, OR + 18 00000000 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + 19 00000000 ; * + 20 00000000 ; ****************************************************** + ***********************/ + 21 00000000 + 22 00000000 + 23 00000000 ; <h> Stack Configuration + 24 00000000 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 25 00000000 ; </h> + 26 00000000 + 27 00000000 00002000 + Stack_Size + EQU 0x00002000 + 28 00000000 + 29 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 30 00000000 Stack_Mem + SPACE Stack_Size + 31 00002000 __initial_sp + 32 00002000 + 33 00002000 + 34 00002000 ; <h> Heap Configuration + 35 00002000 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 36 00002000 ; </h> + 37 00002000 + 38 00002000 00000000 + Heap_Size + EQU 0x00000000 + 39 00002000 + 40 00002000 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 41 00000000 __heap_base + + + +ARM Macro Assembler Page 2 + + + 42 00000000 Heap_Mem + SPACE Heap_Size + 43 00000000 __heap_limit + 44 00000000 + 45 00000000 + 46 00000000 PRESERVE8 + 47 00000000 THUMB + 48 00000000 + 49 00000000 + 50 00000000 ; Vector Table Mapped to Address 0 at Reset + 51 00000000 + 52 00000000 AREA RESET, DATA, READONLY + 53 00000000 EXPORT __Vectors + 54 00000000 + 55 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 56 00000004 00000000 DCD Reset_Handler ; Reset Handler + 57 00000008 00000000 DCD NMI_Handler ; NMI Handler + 58 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 59 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 60 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 61 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 62 0000001C 00000000 DCD 0 ; Reserved + 63 00000020 00000000 DCD 0 ; Reserved + 64 00000024 00000000 DCD 0 ; Reserved + 65 00000028 00000000 DCD 0 ; Reserved + 66 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 67 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 68 00000034 00000000 DCD 0 ; Reserved + 69 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 70 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 71 00000040 + 72 00000040 ; External Interrupts + 73 00000040 00000000 DCD WDT_IRQHandler ; 16: Watchdog T + imer + 74 00000044 00000000 DCD TIMER0_IRQHandler ; 17: Timer0 + 75 00000048 00000000 DCD TIMER1_IRQHandler ; 18: Timer1 + 76 0000004C 00000000 DCD TIMER2_IRQHandler ; 19: Timer2 + 77 00000050 00000000 DCD IntLatch_IRQHandler + ; 20: Timer3 + 78 00000054 00000000 DCD UART0_IRQHandler ; 21: UART0 + 79 00000058 00000000 DCD UART1_IRQHandler ; 22: UART1 + 80 0000005C 00000000 DCD UART2_IRQHandler ; 23: UART2 + 81 00000060 00000000 DCD UART3_IRQHandler ; 24: UART3 + 82 00000064 00000000 DCD PWM1_IRQHandler ; 25: PWM1 + 83 00000068 00000000 DCD I2C0_IRQHandler ; 26: I2C0 + 84 0000006C 00000000 DCD I2C1_IRQHandler ; 27: I2C1 + 85 00000070 00000000 DCD I2C2_IRQHandler ; 28: I2C2 + 86 00000074 00000000 DCD SPI_IRQHandler ; 29: SPI + + + +ARM Macro Assembler Page 3 + + + 87 00000078 00000000 DCD SSP0_IRQHandler ; 30: SSP0 + 88 0000007C 00000000 DCD SSP1_IRQHandler ; 31: SSP1 + 89 00000080 00000000 DCD PLL0_IRQHandler ; 32: PLL0 Lock + (Main PLL) + 90 00000084 00000000 DCD RTC_IRQHandler ; 33: Real Time + Clock + 91 00000088 00000000 DCD EINT0_IRQHandler ; 34: External + Interrupt 0 + 92 0000008C 00000000 DCD EINT1_IRQHandler ; 35: External + Interrupt 1 + 93 00000090 00000000 DCD EINT2_IRQHandler ; 36: External + Interrupt 2 + 94 00000094 00000000 DCD EINT3_IRQHandler ; 37: External + Interrupt 3 + 95 00000098 00000000 DCD ADC_IRQHandler + ; 38: A/D Converter + + 96 0000009C 00000000 DCD BOD_IRQHandler ; 39: Brown-Out + Detect + 97 000000A0 00000000 DCD USB_IRQHandler ; 40: USB + 98 000000A4 00000000 DCD CAN_IRQHandler ; 41: CAN + 99 000000A8 00000000 DCD DMA_IRQHandler ; 42: General Pu + rpose DMA + 100 000000AC 00000000 DCD I2S_IRQHandler ; 43: I2S + 101 000000B0 00000000 DCD ENET_IRQHandler ; 44: Ethernet + 102 000000B4 00000000 DCD RIT_IRQHandler ; 45: Repetitive + Interrupt Timer + 103 000000B8 00000000 DCD MCPWM_IRQHandler ; 46: Motor Co + ntrol PWM + 104 000000BC 00000000 DCD QEI_IRQHandler ; 47: Quadrature + Encoder Interface + 105 000000C0 00000000 DCD PLL1_IRQHandler ; 48: PLL1 Lock + (USB PLL) + 106 000000C4 + 107 000000C4 + 108 000000C4 IF :LNOT::DEF:NO_CRP + 111 ENDIF + 112 000000C4 + 113 000000C4 + 114 000000C4 AREA |.text|, CODE, READONLY + 115 00000000 + 116 00000000 + 117 00000000 ; Reset Handler + 118 00000000 + 119 00000000 Reset_Handler + PROC + 120 00000000 EXPORT Reset_Handler [WEAK +] + 121 00000000 IMPORT SystemInit + 122 00000000 IMPORT __main + 123 00000000 4809 LDR R0, =SystemInit + 124 00000002 4780 BLX R0 + 125 00000004 4809 LDR R0, =__main + 126 00000006 4700 BX R0 + 127 00000008 ENDP + 128 00000008 + 129 00000008 + 130 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + + + +ARM Macro Assembler Page 4 + + + 131 00000008 + 132 00000008 NMI_Handler + PROC + 133 00000008 EXPORT NMI_Handler [WEAK +] + 134 00000008 E7FE B . + 135 0000000A ENDP + 137 0000000A HardFault_Handler + PROC + 138 0000000A EXPORT HardFault_Handler [WEAK +] + 139 0000000A E7FE B . + 140 0000000C ENDP + 142 0000000C MemManage_Handler + PROC + 143 0000000C EXPORT MemManage_Handler [WEAK +] + 144 0000000C E7FE B . + 145 0000000E ENDP + 147 0000000E BusFault_Handler + PROC + 148 0000000E EXPORT BusFault_Handler [WEAK +] + 149 0000000E E7FE B . + 150 00000010 ENDP + 152 00000010 UsageFault_Handler + PROC + 153 00000010 EXPORT UsageFault_Handler [WEAK +] + 154 00000010 E7FE B . + 155 00000012 ENDP + 156 00000012 SVC_Handler + PROC + 157 00000012 EXPORT SVC_Handler [WEAK +] + 158 00000012 E7FE B . + 159 00000014 ENDP + 161 00000014 DebugMon_Handler + PROC + 162 00000014 EXPORT DebugMon_Handler [WEAK +] + 163 00000014 E7FE B . + 164 00000016 ENDP + 165 00000016 PendSV_Handler + PROC + 166 00000016 EXPORT PendSV_Handler [WEAK +] + 167 00000016 E7FE B . + 168 00000018 ENDP + 169 00000018 SysTick_Handler + PROC + 170 00000018 EXPORT SysTick_Handler [WEAK +] + 171 00000018 E7FE B . + 172 0000001A ENDP + 173 0000001A + 174 0000001A Default_Handler + PROC + 175 0000001A + + + +ARM Macro Assembler Page 5 + + + 176 0000001A EXPORT WDT_IRQHandler [WEAK +] + 177 0000001A EXPORT TIMER0_IRQHandler [WEAK +] + 178 0000001A EXPORT TIMER1_IRQHandler [WEAK +] + 179 0000001A EXPORT TIMER2_IRQHandler [WEAK +] + 180 0000001A EXPORT IntLatch_IRQHandler [WEAK +] + 181 0000001A EXPORT UART0_IRQHandler [WEAK +] + 182 0000001A EXPORT UART1_IRQHandler [WEAK +] + 183 0000001A EXPORT UART2_IRQHandler [WEAK +] + 184 0000001A EXPORT UART3_IRQHandler [WEAK +] + 185 0000001A EXPORT PWM1_IRQHandler [WEAK] + 186 0000001A EXPORT I2C0_IRQHandler [WEAK +] + 187 0000001A EXPORT I2C1_IRQHandler [WEAK +] + 188 0000001A EXPORT I2C2_IRQHandler [WEAK +] + 189 0000001A EXPORT SPI_IRQHandler [WEAK +] + 190 0000001A EXPORT SSP0_IRQHandler [WEAK +] + 191 0000001A EXPORT SSP1_IRQHandler [WEAK +] + 192 0000001A EXPORT PLL0_IRQHandler [WEAK +] + 193 0000001A EXPORT RTC_IRQHandler [WEAK +] + 194 0000001A EXPORT EINT0_IRQHandler [WEAK +] + 195 0000001A EXPORT EINT1_IRQHandler [WEAK +] + 196 0000001A EXPORT EINT2_IRQHandler [WEAK +] + 197 0000001A EXPORT EINT3_IRQHandler [WEAK +] + 198 0000001A EXPORT ADC_IRQHandler [WEAK +] + 199 0000001A EXPORT BOD_IRQHandler [WEAK +] + 200 0000001A EXPORT USB_IRQHandler [WEAK +] + 201 0000001A EXPORT CAN_IRQHandler [WEAK +] + 202 0000001A EXPORT DMA_IRQHandler [WEAK +] + 203 0000001A EXPORT I2S_IRQHandler [WEAK +] + 204 0000001A EXPORT ENET_IRQHandler [WEAK +] + 205 0000001A EXPORT RIT_IRQHandler [WEAK +] + + + +ARM Macro Assembler Page 6 + + + 206 0000001A EXPORT MCPWM_IRQHandler [WEAK +] + 207 0000001A EXPORT QEI_IRQHandler [WEAK +] + 208 0000001A EXPORT PLL1_IRQHandler [WEAK +] + 209 0000001A + 210 0000001A WDT_IRQHandler + 211 0000001A TIMER0_IRQHandler + 212 0000001A TIMER1_IRQHandler + 213 0000001A TIMER2_IRQHandler + 214 0000001A IntLatch_IRQHandler + 215 0000001A UART0_IRQHandler + 216 0000001A UART1_IRQHandler + 217 0000001A UART2_IRQHandler + 218 0000001A UART3_IRQHandler + 219 0000001A PWM1_IRQHandler + 220 0000001A I2C0_IRQHandler + 221 0000001A I2C1_IRQHandler + 222 0000001A I2C2_IRQHandler + 223 0000001A SPI_IRQHandler + 224 0000001A SSP0_IRQHandler + 225 0000001A SSP1_IRQHandler + 226 0000001A PLL0_IRQHandler + 227 0000001A RTC_IRQHandler + 228 0000001A EINT0_IRQHandler + 229 0000001A EINT1_IRQHandler + 230 0000001A EINT2_IRQHandler + 231 0000001A EINT3_IRQHandler + 232 0000001A ADC_IRQHandler + 233 0000001A BOD_IRQHandler + 234 0000001A USB_IRQHandler + 235 0000001A CAN_IRQHandler + 236 0000001A DMA_IRQHandler + 237 0000001A I2S_IRQHandler + 238 0000001A ENET_IRQHandler + 239 0000001A RIT_IRQHandler + 240 0000001A MCPWM_IRQHandler + 241 0000001A QEI_IRQHandler + 242 0000001A PLL1_IRQHandler + 243 0000001A + 244 0000001A E7FE B . + 245 0000001C + 246 0000001C ENDP + 247 0000001C + 248 0000001C + 249 0000001C ALIGN + 250 0000001C + 251 0000001C + 252 0000001C ; User Initial Stack & Heap + 253 0000001C + 254 0000001C IF :DEF:__MICROLIB + 261 0000001C + 262 0000001C IMPORT __use_two_region_memory + 263 0000001C EXPORT __user_initial_stackheap + 264 0000001C __user_initial_stackheap + 265 0000001C + 266 0000001C 4804 LDR R0, = Heap_Mem + 267 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size) + + + +ARM Macro Assembler Page 7 + + + 268 00000020 4A03 LDR R2, = (Heap_Mem + Heap_Size) + 269 00000022 4B05 LDR R3, = Stack_Mem + 270 00000024 4770 BX LR + 271 00000026 + 272 00000026 00 00 ALIGN + 273 00000028 + 274 00000028 ENDIF + 275 00000028 + 276 00000028 + 277 00000028 END + 00000000 + 00000000 + 00000000 + 00002000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=.\obj\startup_lpc17xx.d -o.\obj\startup_lpc17xx.o -IC:\Keil_v5\ARM +\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -IC:\Keil_v5\ARM\Inc\NXP\LPC17xx --pre +define="__UVISION_VERSION SETA 515" --predefine="NO_CRP SETA 1" --list=.\list\s +tartup_lpc17xx.lst Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm\start +up_LPC17xx.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 29 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 30 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + At line 267 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 269 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +__initial_sp 00002000 + +Symbol: __initial_sp + Definitions + At line 31 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + At line 55 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 40 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 42 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + At line 266 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 268 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 41 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000000 + +Symbol: __heap_limit + Definitions + At line 43 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 52 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 55 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + At line 53 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s +Comment: __Vectors used once +2 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 114 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + None +Comment: .text unused +ADC_IRQHandler 0000001A + +Symbol: ADC_IRQHandler + Definitions + At line 232 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 95 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 198 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +BOD_IRQHandler 0000001A + +Symbol: BOD_IRQHandler + Definitions + At line 233 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 96 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 199 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 147 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 60 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 148 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +CAN_IRQHandler 0000001A + +Symbol: CAN_IRQHandler + Definitions + At line 235 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 98 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 201 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +DMA_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + +Symbol: DMA_IRQHandler + Definitions + At line 236 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 99 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 202 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 161 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 67 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 162 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 174 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + None +Comment: Default_Handler unused +EINT0_IRQHandler 0000001A + +Symbol: EINT0_IRQHandler + Definitions + At line 228 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 91 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 194 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +EINT1_IRQHandler 0000001A + +Symbol: EINT1_IRQHandler + Definitions + At line 229 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 92 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 195 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +EINT2_IRQHandler 0000001A + +Symbol: EINT2_IRQHandler + Definitions + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + At line 230 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 93 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 196 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +EINT3_IRQHandler 0000001A + +Symbol: EINT3_IRQHandler + Definitions + At line 231 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 94 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 197 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +ENET_IRQHandler 0000001A + +Symbol: ENET_IRQHandler + Definitions + At line 238 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 101 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 204 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 137 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 58 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 138 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +I2C0_IRQHandler 0000001A + +Symbol: I2C0_IRQHandler + Definitions + At line 220 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 83 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 186 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +I2C1_IRQHandler 0000001A + +Symbol: I2C1_IRQHandler + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 221 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 84 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 187 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +I2C2_IRQHandler 0000001A + +Symbol: I2C2_IRQHandler + Definitions + At line 222 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 85 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 188 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +I2S_IRQHandler 0000001A + +Symbol: I2S_IRQHandler + Definitions + At line 237 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 100 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 203 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +IntLatch_IRQHandler 0000001A + +Symbol: IntLatch_IRQHandler + Definitions + At line 214 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 77 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 180 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +MCPWM_IRQHandler 0000001A + +Symbol: MCPWM_IRQHandler + Definitions + At line 240 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 103 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 206 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +MemManage_Handler 0000000C + + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + +Symbol: MemManage_Handler + Definitions + At line 142 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 59 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 143 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 132 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 57 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 133 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +PLL0_IRQHandler 0000001A + +Symbol: PLL0_IRQHandler + Definitions + At line 226 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 89 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 192 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +PLL1_IRQHandler 0000001A + +Symbol: PLL1_IRQHandler + Definitions + At line 242 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 105 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 208 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +PWM1_IRQHandler 0000001A + +Symbol: PWM1_IRQHandler + Definitions + At line 219 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 82 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 185 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +PendSV_Handler 00000016 + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: PendSV_Handler + Definitions + At line 165 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 69 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 166 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +QEI_IRQHandler 0000001A + +Symbol: QEI_IRQHandler + Definitions + At line 241 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 104 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 207 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +RIT_IRQHandler 0000001A + +Symbol: RIT_IRQHandler + Definitions + At line 239 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 102 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + At line 205 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 227 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 90 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 193 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 119 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 56 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 120 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + +SPI_IRQHandler 0000001A + +Symbol: SPI_IRQHandler + Definitions + At line 223 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 86 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 189 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +SSP0_IRQHandler 0000001A + +Symbol: SSP0_IRQHandler + Definitions + At line 224 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 87 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 190 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +SSP1_IRQHandler 0000001A + +Symbol: SSP1_IRQHandler + Definitions + At line 225 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 88 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 191 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 156 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 66 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 157 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 169 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 70 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 170 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +TIMER0_IRQHandler 0000001A + +Symbol: TIMER0_IRQHandler + Definitions + At line 211 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 74 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 177 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +TIMER1_IRQHandler 0000001A + +Symbol: TIMER1_IRQHandler + Definitions + At line 212 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 75 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 178 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +TIMER2_IRQHandler 0000001A + +Symbol: TIMER2_IRQHandler + Definitions + At line 213 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 76 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 179 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +UART0_IRQHandler 0000001A + +Symbol: UART0_IRQHandler + Definitions + At line 215 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 78 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 181 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +UART1_IRQHandler 0000001A + +Symbol: UART1_IRQHandler + Definitions + At line 216 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 79 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 182 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + +m\startup_LPC17xx.s + +UART2_IRQHandler 0000001A + +Symbol: UART2_IRQHandler + Definitions + At line 217 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 80 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 183 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +UART3_IRQHandler 0000001A + +Symbol: UART3_IRQHandler + Definitions + At line 218 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 81 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 184 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +USB_IRQHandler 0000001A + +Symbol: USB_IRQHandler + Definitions + At line 234 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 97 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 200 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 152 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 61 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 153 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +WDT_IRQHandler 0000001A + +Symbol: WDT_IRQHandler + Definitions + At line 210 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 73 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + + At line 176 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +__user_initial_stackheap 0000001C + +Symbol: __user_initial_stackheap + Definitions + At line 264 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 263 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s +Comment: __user_initial_stackheap used once +46 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000000 + +Symbol: Heap_Size + Definitions + At line 38 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + At line 42 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 268 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +Stack_Size 00002000 + +Symbol: Stack_Size + Definitions + At line 27 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + Uses + At line 30 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm +\startup_LPC17xx.s + At line 267 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + +2 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 121 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 123 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 122 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + At line 125 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 262 in file Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\ar +m\startup_LPC17xx.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +396 symbols in table
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/LandTiger_DMA.axf Binary file host/Obj/LandTiger_DMA.axf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/LandTiger_DMA.bin Binary file host/Obj/LandTiger_DMA.bin has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/LandTiger_DMA.build_log.htm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/LandTiger_DMA.build_log.htm Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,61 @@ +<html> +<body> +<pre> +<h1>µVision Build Log</h1> +<h2>Tool Versions:</h2> +IDE-Version: µVision V5.15 +Copyright (C) 2015 ARM Ltd and ARM Germany GmbH. All rights reserved. +License Information: ddd ddd, ddd, LIC=NHY45-GQGII-UK6B6-D2BWS-TX5RY-0TUVM + +Tool Versions: +Toolchain: MDK-ARM Professional Version: 5.15.0 +Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin +C Compiler: Armcc.exe V5.05 update 2 (build 169) +Assembler: Armasm.exe V5.05 update 2 (build 169) +Linker/Locator: ArmLink.exe V5.05 update 2 (build 169) +Library Manager: ArmAr.exe V5.05 update 2 (build 169) +Hex Converter: FromElf.exe V5.05 update 2 (build 169) +CPU DLL: SARMCM3.DLL V5.15.0 +Dialog DLL: DARMP1.DLL V1.25.0.0 +Target DLL: SiLabs\SLAB_CM_Keil.dll V1.0.0.8 +Dialog DLL: TARMP1.DLL V1.24.0.0 + +<h2>Project:</h2> +C:\Users\Äìèòðèé\Desktop\host\LandTiger_DMA.uvproj +Project File Date: 12/28/2015 + +<h2>Output:</h2> +*** Using Compiler 'V5.05 update 2 (build 169)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin' +Rebuild target 'LandTiger_DMA' +assembling startup_LPC17xx.s... +compiling core_cm3.c... +compiling system_LPC17xx.c... +compiling vibro.c... +compiling CyclesSync.c... +compiling commandset.c... +compiling Dither_Reg.c... +compiling el_lin.c... +compiling main.c... +compiling PLC_reg.c... +compiling HFO_Reg.c... +compiling ThermoCalc.c... +compiling CntrlGLD.c... +compiling mathDSP.c... +compiling InputOutput.c... +compiling SIP.c... +compiling Parameters.c... +compiling console.c... +compiling QEI.c... +compiling Global.c... +compiling MTimer.c... +compiling SPI.c... +compiling Command.c... +compiling uart_m.c... +linking... +Program Size: Code=32788 RO-data=532 RW-data=1420 ZI-data=41204 +FromELF: creating hex file... +After Build - User command #1: fromelf --bin --output=.\obj\LandTiger_DMA.bin .\obj\LandTiger_DMA.axf +".\Obj\LandTiger_DMA.axf" - 0 Error(s), 0 Warning(s). +</pre> +</body> +</html>
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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/LandTiger_DMA.htm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/LandTiger_DMA.htm Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,2109 @@ +<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> +<html><head> +<title>Static Call Graph - [.\Obj\LandTiger_DMA.axf]</title></head> +<body><HR> +<H1>Static Call Graph for image .\Obj\LandTiger_DMA.axf</H1><HR> +<BR><P>#<CALLGRAPH># ARM Linker, 5050169: Last Updated: Wed Feb 03 10:39:30 2016 +<BR><P> +<H3>Maximum Stack Usage = 352 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)</H3><H3> +Call chain for Maximum Stack Depth:</H3> +__rt_entry_main ⇒ main ⇒ init_PLC ⇒ init_BandPass ⇒ cos ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +<P> +<H3> +Functions with no stack information +</H3><UL> + <LI><a href="#[fc]">__user_initial_stackheap</a> +</UL> +</UL> +<P> +<H3> +Mutually Recursive functions +</H3> <LI><a href="#[8]">NMI_Handler</a> ⇒ <a href="#[8]">NMI_Handler</a><BR> + <LI><a href="#[9]">HardFault_Handler</a> ⇒ <a href="#[9]">HardFault_Handler</a><BR> + <LI><a href="#[a]">MemManage_Handler</a> ⇒ <a href="#[a]">MemManage_Handler</a><BR> + <LI><a href="#[b]">BusFault_Handler</a> ⇒ <a href="#[b]">BusFault_Handler</a><BR> + <LI><a href="#[c]">UsageFault_Handler</a> ⇒ <a href="#[c]">UsageFault_Handler</a><BR> + <LI><a href="#[d]">SVC_Handler</a> ⇒ <a href="#[d]">SVC_Handler</a><BR> + <LI><a href="#[e]">DebugMon_Handler</a> ⇒ <a href="#[e]">DebugMon_Handler</a><BR> + <LI><a href="#[f]">PendSV_Handler</a> ⇒ <a href="#[f]">PendSV_Handler</a><BR> + <LI><a href="#[10]">SysTick_Handler</a> ⇒ <a href="#[10]">SysTick_Handler</a><BR> + <LI><a href="#[27]">ADC_IRQHandler</a> ⇒ <a href="#[27]">ADC_IRQHandler</a><BR> +</UL> +<P> +<H3> +Function Pointers +</H3><UL> + <LI><a href="#[27]">ADC_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[28]">BOD_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[b]">BusFault_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[2a]">CAN_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[2b]">DMA_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[e]">DebugMon_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[23]">EINT0_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[24]">EINT1_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[25]">EINT2_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[26]">EINT3_IRQHandler</a> from cyclessync.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[2d]">ENET_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[9]">HardFault_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[1b]">I2C0_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[1c]">I2C1_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[1d]">I2C2_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[2c]">I2S_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[15]">IntLatch_IRQHandler</a> from cyclessync.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[2f]">MCPWM_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[a]">MemManage_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[8]">NMI_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[21]">PLL0_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[31]">PLL1_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[1a]">PWM1_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[f]">PendSV_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[30]">QEI_IRQHandler</a> from cyclessync.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[2e]">RIT_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[22]">RTC_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[7]">Reset_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[1e]">SPI_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[1f]">SSP0_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[20]">SSP1_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[d]">SVC_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[5]">Sts_Pause</a> from cntrlgld.o(.text) referenced 2 times from cntrlgld.o(.data) + <LI><a href="#[6]">Sts_Polling</a> from cntrlgld.o(.text) referenced 2 times from cntrlgld.o(.data) + <LI><a href="#[4]">Sts_Pulse</a> from cntrlgld.o(.text) referenced 4 times from cntrlgld.o(.data) + <LI><a href="#[10]">SysTick_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[32]">SystemInit</a> from system_lpc17xx.o(.text) referenced from startup_lpc17xx.o(.text) + <LI><a href="#[12]">TIMER0_IRQHandler</a> from cyclessync.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[13]">TIMER1_IRQHandler</a> from mtimer.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[14]">TIMER2_IRQHandler</a> from mtimer.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[16]">UART0_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[17]">UART1_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[18]">UART2_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[19]">UART3_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[29]">USB_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[c]">UsageFault_Handler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[11]">WDT_IRQHandler</a> from startup_lpc17xx.o(.text) referenced from startup_lpc17xx.o(RESET) + <LI><a href="#[34]">__main</a> from __main.o(!!!main) referenced from startup_lpc17xx.o(.text) +</UL> +<P> +<H3> +Global Symbols +</H3> +<P><STRONG><a name="[34]"></a>__main</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +<BR><BR>[Calls]<UL><LI><a href="#[36]">>></a> __rt_entry +<LI><a href="#[35]">>></a> __scatterload +</UL> + +<P><STRONG><a name="[35]"></a>__scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +<BR><BR>[Called By]<UL><LI><a href="#[34]">>></a> __main +</UL> + +<P><STRONG><a name="[37]"></a>__scatterload_rt2</STRONG> (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[36]">>></a> __rt_entry +</UL> + +<P><STRONG><a name="[122]"></a>__scatterload_rt2_thumb_only</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +<P><STRONG><a name="[123]"></a>__scatterload_null</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +<P><STRONG><a name="[124]"></a>__decompress</STRONG> (Thumb, 90 bytes, Stack size unknown bytes, __dczerorl2.o(!!dczerorl2), UNUSED) + +<P><STRONG><a name="[125]"></a>__decompress1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl2.o(!!dczerorl2), UNUSED) + +<P><STRONG><a name="[126]"></a>__scatterload_zeroinit</STRONG> (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +<P><STRONG><a name="[3d]"></a>__rt_lib_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +<BR><BR>[Called By]<UL><LI><a href="#[3c]">>></a> __rt_entry_li +</UL> + +<P><STRONG><a name="[127]"></a>__rt_lib_init_fp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002)) + +<P><STRONG><a name="[128]"></a>__rt_lib_init_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A)) + +<P><STRONG><a name="[129]"></a>__rt_lib_init_preinit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004)) + +<P><STRONG><a name="[38]"></a>__rt_lib_init_rand_2</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000D)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size +<LI>Call Chain = __rt_lib_init_rand_2 ⇒ _rand_init ⇒ srand +</UL> +<BR>[Calls]<UL><LI><a href="#[39]">>></a> _rand_init +</UL> + +<P><STRONG><a name="[12a]"></a>__rt_lib_init_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +<P><STRONG><a name="[12b]"></a>__rt_lib_init_alloca_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +<P><STRONG><a name="[12c]"></a>__rt_lib_init_argv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C)) + +<P><STRONG><a name="[12d]"></a>__rt_lib_init_atexit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +<P><STRONG><a name="[12e]"></a>__rt_lib_init_clock_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +<P><STRONG><a name="[12f]"></a>__rt_lib_init_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032)) + +<P><STRONG><a name="[130]"></a>__rt_lib_init_exceptions_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +<P><STRONG><a name="[131]"></a>__rt_lib_init_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +<P><STRONG><a name="[132]"></a>__rt_lib_init_getenv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +<P><STRONG><a name="[133]"></a>__rt_lib_init_lc_collate_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011)) + +<P><STRONG><a name="[134]"></a>__rt_lib_init_lc_ctype_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +<P><STRONG><a name="[135]"></a>__rt_lib_init_lc_monetary_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +<P><STRONG><a name="[136]"></a>__rt_lib_init_lc_numeric_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +<P><STRONG><a name="[137]"></a>__rt_lib_init_lc_time_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +<P><STRONG><a name="[138]"></a>__rt_lib_init_rand_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E)) + +<P><STRONG><a name="[139]"></a>__rt_lib_init_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033)) + +<P><STRONG><a name="[13a]"></a>__rt_lib_init_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +<P><STRONG><a name="[13b]"></a>__rt_lib_init_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025)) + +<P><STRONG><a name="[42]"></a>__rt_lib_shutdown</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +<BR><BR>[Called By]<UL><LI><a href="#[41]">>></a> __rt_exit_ls +</UL> + +<P><STRONG><a name="[13c]"></a>__rt_lib_shutdown_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006)) + +<P><STRONG><a name="[13d]"></a>__rt_lib_shutdown_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E)) + +<P><STRONG><a name="[13e]"></a>__rt_lib_shutdown_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +<P><STRONG><a name="[13f]"></a>__rt_lib_shutdown_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009)) + +<P><STRONG><a name="[140]"></a>__rt_lib_shutdown_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000003)) + +<P><STRONG><a name="[141]"></a>__rt_lib_shutdown_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B)) + +<P><STRONG><a name="[36]"></a>__rt_entry</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000)) +<BR><BR>[Called By]<UL><LI><a href="#[34]">>></a> __main +<LI><a href="#[37]">>></a> __scatterload_rt2 +</UL> + +<P><STRONG><a name="[142]"></a>__rt_entry_presh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +<P><STRONG><a name="[3a]"></a>__rt_entry_sh</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size +<LI>Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap +</UL> +<BR>[Calls]<UL><LI><a href="#[3b]">>></a> __user_setup_stackheap +</UL> + +<P><STRONG><a name="[3c]"></a>__rt_entry_li</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +<BR><BR>[Calls]<UL><LI><a href="#[3d]">>></a> __rt_lib_init +</UL> + +<P><STRONG><a name="[143]"></a>__rt_entry_postsh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +<P><STRONG><a name="[3e]"></a>__rt_entry_main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +<BR><BR>[Stack]<UL><LI>Max Depth = 352 + Unknown Stack Size +<LI>Call Chain = __rt_entry_main ⇒ main ⇒ init_PLC ⇒ init_BandPass ⇒ cos ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[3f]">>></a> main +<LI><a href="#[40]">>></a> exit +</UL> + +<P><STRONG><a name="[144]"></a>__rt_entry_postli_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +<P><STRONG><a name="[fd]"></a>__rt_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +<BR><BR>[Called By]<UL><LI><a href="#[40]">>></a> exit +</UL> + +<P><STRONG><a name="[41]"></a>__rt_exit_ls</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +<BR><BR>[Calls]<UL><LI><a href="#[42]">>></a> __rt_lib_shutdown +</UL> + +<P><STRONG><a name="[145]"></a>__rt_exit_prels_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +<P><STRONG><a name="[43]"></a>__rt_exit_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +<BR><BR>[Calls]<UL><LI><a href="#[44]">>></a> _sys_exit +</UL> + +<P><STRONG><a name="[47]"></a>rand</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, rand.o(.emb_text)) +<BR><BR>[Called By]<UL><LI><a href="#[81]">>></a> clc_Noise_regulator +<LI><a href="#[45]">>></a> CalcAmpN +</UL> + +<P><STRONG><a name="[7]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[8]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[8]">>></a> NMI_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[8]">>></a> NMI_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[9]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[9]">>></a> HardFault_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[9]">>></a> HardFault_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[a]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[a]">>></a> MemManage_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[a]">>></a> MemManage_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[b]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[b]">>></a> BusFault_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[b]">>></a> BusFault_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[c]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[c]">>></a> UsageFault_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[c]">>></a> UsageFault_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[d]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[d]">>></a> SVC_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[d]">>></a> SVC_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[e]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[e]">>></a> DebugMon_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[e]">>></a> DebugMon_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[f]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[f]">>></a> PendSV_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[f]">>></a> PendSV_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[10]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[10]">>></a> SysTick_Handler +</UL> +<BR>[Called By]<UL><LI><a href="#[10]">>></a> SysTick_Handler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[27]"></a>ADC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[27]">>></a> ADC_IRQHandler +</UL> +<BR>[Called By]<UL><LI><a href="#[27]">>></a> ADC_IRQHandler +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[28]"></a>BOD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[2a]"></a>CAN_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[2b]"></a>DMA_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[23]"></a>EINT0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[24]"></a>EINT1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[25]"></a>EINT2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[2d]"></a>ENET_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[1b]"></a>I2C0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[1c]"></a>I2C1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[1d]"></a>I2C2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[2c]"></a>I2S_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[2f]"></a>MCPWM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[21]"></a>PLL0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[31]"></a>PLL1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[1a]"></a>PWM1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[2e]"></a>RIT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[22]"></a>RTC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[1e]"></a>SPI_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[1f]"></a>SSP0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[20]"></a>SSP1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[16]"></a>UART0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[17]"></a>UART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[18]"></a>UART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[19]"></a>UART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[29]"></a>USB_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[11]"></a>WDT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_lpc17xx.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[fc]"></a>__user_initial_stackheap</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, startup_lpc17xx.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3b]">>></a> __user_setup_stackheap +</UL> + +<P><STRONG><a name="[90]"></a>SystemCoreClockUpdate</STRONG> (Thumb, 306 bytes, Stack size 0 bytes, system_lpc17xx.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[32]"></a>SystemInit</STRONG> (Thumb, 294 bytes, Stack size 0 bytes, system_lpc17xx.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(.text) +</UL> +<P><STRONG><a name="[99]"></a>init_Vibro</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, vibro.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[d0]"></a>VibroOut</STRONG> (Thumb, 96 bytes, Stack size 0 bytes, vibro.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[14]">>></a> TIMER2_IRQHandler +</UL> + +<P><STRONG><a name="[45]"></a>CalcAmpN</STRONG> (Thumb, 246 bytes, Stack size 8 bytes, vibro.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = CalcAmpN ⇒ srand +</UL> +<BR>[Calls]<UL><LI><a href="#[46]">>></a> srand +<LI><a href="#[47]">>></a> rand +</UL> +<BR>[Called By]<UL><LI><a href="#[48]">>></a> cheng +</UL> + +<P><STRONG><a name="[48]"></a>cheng</STRONG> (Thumb, 272 bytes, Stack size 8 bytes, vibro.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = cheng ⇒ CalcAmpN ⇒ srand +</UL> +<BR>[Calls]<UL><LI><a href="#[49]">>></a> VibroPush +<LI><a href="#[4a]">>></a> VibroPull +<LI><a href="#[45]">>></a> CalcAmpN +</UL> +<BR>[Called By]<UL><LI><a href="#[13]">>></a> TIMER1_IRQHandler +</UL> + +<P><STRONG><a name="[a5]"></a>Latch_Event</STRONG> (Thumb, 84 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[30]"></a>QEI_IRQHandler</STRONG> (Thumb, 58 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[4c]"></a>SetIntLatch</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[64]">>></a> M_Rate +<LI><a href="#[4b]">>></a> SwitchMode +</UL> + +<P><STRONG><a name="[65]"></a>SwitchRefMeandInt</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +<LI><a href="#[64]">>></a> M_Rate +</UL> + +<P><STRONG><a name="[26]"></a>EINT3_IRQHandler</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[15]"></a>IntLatch_IRQHandler</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[4b]"></a>SwitchMode</STRONG> (Thumb, 198 bytes, Stack size 8 bytes, cyclessync.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = SwitchMode ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[4d]">>></a> UART_SwitchSpeed +<LI><a href="#[4c]">>></a> SetIntLatch +</UL> +<BR>[Called By]<UL><LI><a href="#[bf]">>></a> GLD_Status +</UL> + +<P><STRONG><a name="[a7]"></a>ServiceTime</STRONG> (Thumb, 90 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[146]"></a>WDTFeed</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, cyclessync.o(.text), UNUSED) + +<P><STRONG><a name="[4e]"></a>CounterIquiryCycle_Init</STRONG> (Thumb, 80 bytes, Stack size 8 bytes, cyclessync.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = CounterIquiryCycle_Init +</UL> +<BR>[Calls]<UL><LI><a href="#[4f]">>></a> NVIC_DisableIRQ +</UL> +<BR>[Called By]<UL><LI><a href="#[83]">>></a> init_Dither_reg +</UL> + +<P><STRONG><a name="[12]"></a>TIMER0_IRQHandler</STRONG> (Thumb, 102 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[50]"></a>ExtLatch_Init</STRONG> (Thumb, 144 bytes, Stack size 8 bytes, cyclessync.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = ExtLatch_Init +</UL> +<BR>[Calls]<UL><LI><a href="#[4f]">>></a> NVIC_DisableIRQ +<LI><a href="#[51]">>></a> NVIC_EnableIRQ +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[52]"></a>IntLatch_Init</STRONG> (Thumb, 74 bytes, Stack size 8 bytes, cyclessync.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = IntLatch_Init +</UL> +<BR>[Calls]<UL><LI><a href="#[51]">>></a> NVIC_EnableIRQ +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[53]"></a>WDTInit</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, cyclessync.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[4f]">>></a> NVIC_DisableIRQ +</UL> + +<P><STRONG><a name="[5c]"></a>SetSpeedPeriod</STRONG> (Thumb, 66 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +<LI><a href="#[64]">>></a> M_Rate +<LI><a href="#[5f]">>></a> M_Cnt_R +<LI><a href="#[5e]">>></a> M_ADC_R +<LI><a href="#[5b]">>></a> M_Status +</UL> + +<P><STRONG><a name="[6f]"></a>B_Delta_BINS</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[70]"></a>B_Delta_SF</STRONG> (Thumb, 72 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[55]"></a>B_Delta_PS_execution</STRONG> (Thumb, 142 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[54]">>></a> GLD_Output +</UL> + +<P><STRONG><a name="[75]"></a>M_Mirror</STRONG> (Thumb, 52 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[5a]"></a>Mk_Ask1</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6c]">>></a> M_Pulse +<LI><a href="#[6b]">>></a> M_Stop +<LI><a href="#[6a]">>></a> M_Start +<LI><a href="#[69]">>></a> M_LdPar_D +<LI><a href="#[67]">>></a> M_LdPar_F +<LI><a href="#[66]">>></a> M_Param_W +<LI><a href="#[62]">>></a> M_Gph_W +<LI><a href="#[60]">>></a> M_Vib_W +<LI><a href="#[5d]">>></a> M_Tmp_W +<LI><a href="#[59]">>></a> M_Stimul +</UL> + +<P><STRONG><a name="[57]"></a>Mk_AskDev</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[58]">>></a> B_BIT_Mode +<LI><a href="#[56]">>></a> B_Dev_Mode +</UL> + +<P><STRONG><a name="[54]"></a>GLD_Output</STRONG> (Thumb, 96 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = GLD_Output +</UL> +<BR>[Calls]<UL><LI><a href="#[55]">>></a> B_Delta_PS_execution +</UL> +<BR>[Called By]<UL><LI><a href="#[ac]">>></a> contrl_GLD +</UL> + +<P><STRONG><a name="[56]"></a>B_Dev_Mode</STRONG> (Thumb, 22 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = B_Dev_Mode +</UL> +<BR>[Calls]<UL><LI><a href="#[57]">>></a> Mk_AskDev +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[58]"></a>B_BIT_Mode</STRONG> (Thumb, 98 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = B_BIT_Mode +</UL> +<BR>[Calls]<UL><LI><a href="#[57]">>></a> Mk_AskDev +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[59]"></a>M_Stimul</STRONG> (Thumb, 60 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = M_Stimul +</UL> +<BR>[Calls]<UL><LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[5b]"></a>M_Status</STRONG> (Thumb, 48 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = M_Status +</UL> +<BR>[Calls]<UL><LI><a href="#[5c]">>></a> SetSpeedPeriod +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[74]"></a>M_Clear</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[5d]"></a>M_Tmp_W</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, commandset.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> + +<P><STRONG><a name="[76]"></a>M_Tmp_R</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[5e]"></a>M_ADC_R</STRONG> (Thumb, 54 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = M_ADC_R ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[5c]">>></a> SetSpeedPeriod +<LI><a href="#[4d]">>></a> UART_SwitchSpeed +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[5f]"></a>M_Cnt_R</STRONG> (Thumb, 48 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = M_Cnt_R ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[5c]">>></a> SetSpeedPeriod +<LI><a href="#[4d]">>></a> UART_SwitchSpeed +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[79]"></a>M_Ctl_R</STRONG> (Thumb, 66 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[7a]"></a>M_Ctl_M</STRONG> (Thumb, 242 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[77]"></a>M_Flg_R</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[60]"></a>M_Vib_W</STRONG> (Thumb, 52 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = M_Vib_W +</UL> +<BR>[Calls]<UL><LI><a href="#[61]">>></a> VibroDither_Set +<LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[62]"></a>M_Gph_W</STRONG> (Thumb, 46 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = M_Gph_W +</UL> +<BR>[Calls]<UL><LI><a href="#[63]">>></a> Out_G_photo +<LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[64]"></a>M_Rate</STRONG> (Thumb, 386 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = M_Rate ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[5c]">>></a> SetSpeedPeriod +<LI><a href="#[4d]">>></a> UART_SwitchSpeed +<LI><a href="#[65]">>></a> SwitchRefMeandInt +<LI><a href="#[4c]">>></a> SetIntLatch +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[72]"></a>M_Reset</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[78]"></a>M_Param_R</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[66]"></a>M_Param_W</STRONG> (Thumb, 42 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = M_Param_W +</UL> +<BR>[Calls]<UL><LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[67]"></a>M_LdPar_F</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = M_LdPar_F ⇒ LoadFlashParam +</UL> +<BR>[Calls]<UL><LI><a href="#[68]">>></a> LoadFlashParam +<LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[69]"></a>M_LdPar_D</STRONG> (Thumb, 14 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = M_LdPar_D +</UL> +<BR>[Calls]<UL><LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[6a]"></a>M_Start</STRONG> (Thumb, 20 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = M_Start +</UL> +<BR>[Calls]<UL><LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[6b]"></a>M_Stop</STRONG> (Thumb, 20 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = M_Stop +</UL> +<BR>[Calls]<UL><LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[6c]"></a>M_Pulse</STRONG> (Thumb, 20 bytes, Stack size 4 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = M_Pulse +</UL> +<BR>[Calls]<UL><LI><a href="#[5a]">>></a> Mk_Ask1 +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[6e]"></a>B_Rate</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[71]"></a>B_Delta</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[73]"></a>D_Period_W</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, commandset.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +</UL> + +<P><STRONG><a name="[6d]"></a>exec_CMD</STRONG> (Thumb, 750 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = exec_CMD ⇒ M_Rate ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[73]">>></a> D_Period_W +<LI><a href="#[71]">>></a> B_Delta +<LI><a href="#[6e]">>></a> B_Rate +<LI><a href="#[6c]">>></a> M_Pulse +<LI><a href="#[6b]">>></a> M_Stop +<LI><a href="#[6a]">>></a> M_Start +<LI><a href="#[69]">>></a> M_LdPar_D +<LI><a href="#[67]">>></a> M_LdPar_F +<LI><a href="#[66]">>></a> M_Param_W +<LI><a href="#[78]">>></a> M_Param_R +<LI><a href="#[72]">>></a> M_Reset +<LI><a href="#[64]">>></a> M_Rate +<LI><a href="#[62]">>></a> M_Gph_W +<LI><a href="#[60]">>></a> M_Vib_W +<LI><a href="#[77]">>></a> M_Flg_R +<LI><a href="#[7a]">>></a> M_Ctl_M +<LI><a href="#[79]">>></a> M_Ctl_R +<LI><a href="#[5f]">>></a> M_Cnt_R +<LI><a href="#[5e]">>></a> M_ADC_R +<LI><a href="#[76]">>></a> M_Tmp_R +<LI><a href="#[74]">>></a> M_Clear +<LI><a href="#[5b]">>></a> M_Status +<LI><a href="#[59]">>></a> M_Stimul +<LI><a href="#[58]">>></a> B_BIT_Mode +<LI><a href="#[56]">>></a> B_Dev_Mode +<LI><a href="#[75]">>></a> M_Mirror +<LI><a href="#[70]">>></a> B_Delta_SF +<LI><a href="#[6f]">>></a> B_Delta_BINS +<LI><a href="#[5c]">>></a> SetSpeedPeriod +<LI><a href="#[4d]">>></a> UART_SwitchSpeed +<LI><a href="#[65]">>></a> SwitchRefMeandInt +</UL> +<BR>[Called By]<UL><LI><a href="#[7b]">>></a> decode_CMD +</UL> + +<P><STRONG><a name="[7b]"></a>decode_CMD</STRONG> (Thumb, 208 bytes, Stack size 8 bytes, commandset.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = decode_CMD ⇒ exec_CMD ⇒ M_Rate ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[6d]">>></a> exec_CMD +<LI><a href="#[7c]">>></a> __aeabi_memcpy +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[61]"></a>VibroDither_Set</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, dither_reg.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[60]">>></a> M_Vib_W +</UL> + +<P><STRONG><a name="[86]"></a>VibroDither_SwitchOn</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, dither_reg.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[83]">>></a> init_Dither_reg +</UL> + +<P><STRONG><a name="[147]"></a>VibroDither_SwitchOff</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, dither_reg.o(.text), UNUSED) + +<P><STRONG><a name="[7f]"></a>VB_MeanderDelay</STRONG> (Thumb, 164 bytes, Stack size 8 bytes, dither_reg.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[7d]">>></a> clc_Dith_regulator +</UL> + +<P><STRONG><a name="[80]"></a>VB_PhaseDetectorRate</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, dither_reg.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[7d]">>></a> clc_Dith_regulator +</UL> + +<P><STRONG><a name="[7d]"></a>clc_Dith_regulator</STRONG> (Thumb, 664 bytes, Stack size 40 bytes, dither_reg.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[7e]">>></a> DUP_Filt +<LI><a href="#[80]">>></a> VB_PhaseDetectorRate +<LI><a href="#[7f]">>></a> VB_MeanderDelay +</UL> + +<P><STRONG><a name="[81]"></a>clc_Noise_regulator</STRONG> (Thumb, 546 bytes, Stack size 32 bytes, dither_reg.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = clc_Noise_regulator ⇒ srand +</UL> +<BR>[Calls]<UL><LI><a href="#[46]">>></a> srand +<LI><a href="#[47]">>></a> rand +</UL> +<BR>[Called By]<UL><LI><a href="#[82]">>></a> clc_OutFreq_regulator +</UL> + +<P><STRONG><a name="[82]"></a>clc_OutFreq_regulator</STRONG> (Thumb, 574 bytes, Stack size 40 bytes, dither_reg.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 80<LI>Call Chain = clc_OutFreq_regulator ⇒ clc_Noise_regulator ⇒ srand +</UL> +<BR>[Calls]<UL><LI><a href="#[81]">>></a> clc_Noise_regulator +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[85]"></a>VibroDither_Init</STRONG> (Thumb, 240 bytes, Stack size 0 bytes, dither_reg.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[83]">>></a> init_Dither_reg +</UL> + +<P><STRONG><a name="[83]"></a>init_Dither_reg</STRONG> (Thumb, 98 bytes, Stack size 32 bytes, dither_reg.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 312<LI>Call Chain = init_Dither_reg ⇒ init_BandPass ⇒ cos ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[84]">>></a> init_VibroReduce +<LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[85]">>></a> VibroDither_Init +<LI><a href="#[86]">>></a> VibroDither_SwitchOn +<LI><a href="#[4e]">>></a> CounterIquiryCycle_Init +<LI><a href="#[87]">>></a> __aeabi_ui2f +<LI><a href="#[88]">>></a> __aeabi_f2d +<LI><a href="#[89]">>></a> __aeabi_ddiv +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[8c]"></a>check_lcc</STRONG> (Thumb, 54 bytes, Stack size 12 bytes, el_lin.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = check_lcc +</UL> +<BR>[Called By]<UL><LI><a href="#[8b]">>></a> Line_1_Rcv +</UL> + +<P><STRONG><a name="[148]"></a>PacketSafing</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, el_lin.o(.text), UNUSED) + +<P><STRONG><a name="[8b]"></a>Line_1_Rcv</STRONG> (Thumb, 354 bytes, Stack size 4 bytes, el_lin.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = Line_1_Rcv ⇒ check_lcc +</UL> +<BR>[Calls]<UL><LI><a href="#[8c]">>></a> check_lcc +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[ae]"></a>transm_DAT</STRONG> (Thumb, 396 bytes, Stack size 16 bytes, el_lin.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = transm_DAT +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[8e]"></a>DMA_Init</STRONG> (Thumb, 60 bytes, Stack size 0 bytes, el_lin.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[91]"></a>UARTInit</STRONG> (Thumb, 124 bytes, Stack size 8 bytes, el_lin.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = UARTInit +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[92]"></a>UART1_Init</STRONG> (Thumb, 198 bytes, Stack size 8 bytes, el_lin.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = UART1_Init +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[149]"></a>UART1_SendByte</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, el_lin.o(.text), UNUSED) + +<P><STRONG><a name="[4d]"></a>UART_SwitchSpeed</STRONG> (Thumb, 132 bytes, Stack size 8 bytes, el_lin.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = UART_SwitchSpeed +</UL> +<BR>[Called By]<UL><LI><a href="#[6d]">>></a> exec_CMD +<LI><a href="#[64]">>></a> M_Rate +<LI><a href="#[5f]">>></a> M_Cnt_R +<LI><a href="#[5e]">>></a> M_ADC_R +<LI><a href="#[4b]">>></a> SwitchMode +</UL> + +<P><STRONG><a name="[96]"></a>UART_DMA_Init</STRONG> (Thumb, 258 bytes, Stack size 0 bytes, el_lin.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[8d]"></a>Led_init</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, main.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[14a]"></a>Led_Blink</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, main.o(.text), UNUSED) + +<P><STRONG><a name="[3f]"></a>main</STRONG> (Thumb, 854 bytes, Stack size 0 bytes, main.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 352<LI>Call Chain = main ⇒ init_PLC ⇒ init_BandPass ⇒ cos ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[9a]">>></a> init_timer +<LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[9d]">>></a> enable_timer2 +<LI><a href="#[9b]">>></a> enable_timer1 +<LI><a href="#[ac]">>></a> contrl_GLD +<LI><a href="#[ab]">>></a> clc_WP_sin +<LI><a href="#[a8]">>></a> clc_ThermoSensors +<LI><a href="#[a6]">>></a> clc_Pulses +<LI><a href="#[aa]">>></a> clc_PLC +<LI><a href="#[a9]">>></a> clc_HFO +<LI><a href="#[9f]">>></a> WriteCon +<LI><a href="#[a4]">>></a> TakeFromBuff +<LI><a href="#[9e]">>></a> SendToBuffStr +<LI><a href="#[95]">>></a> SOI_Init +<LI><a href="#[a1]">>></a> Read_CMD +<LI><a href="#[9c]">>></a> Init_TIM2 +<LI><a href="#[97]">>></a> G_Photo_Init +<LI><a href="#[ad]">>></a> G_Photo_Exchange +<LI><a href="#[8f]">>></a> FlashDMA_Init +<LI><a href="#[93]">>></a> DAC_ADC_Exchange_Init +<LI><a href="#[94]">>></a> DACInit +<LI><a href="#[a0]">>></a> Concol +<LI><a href="#[a2]">>></a> CMD_Rate +<LI><a href="#[a3]">>></a> ButtonLightUP +<LI><a href="#[8d]">>></a> Led_init +<LI><a href="#[96]">>></a> UART_DMA_Init +<LI><a href="#[92]">>></a> UART1_Init +<LI><a href="#[91]">>></a> UARTInit +<LI><a href="#[8e]">>></a> DMA_Init +<LI><a href="#[ae]">>></a> transm_DAT +<LI><a href="#[8b]">>></a> Line_1_Rcv +<LI><a href="#[83]">>></a> init_Dither_reg +<LI><a href="#[82]">>></a> clc_OutFreq_regulator +<LI><a href="#[63]">>></a> Out_G_photo +<LI><a href="#[68]">>></a> LoadFlashParam +<LI><a href="#[7b]">>></a> decode_CMD +<LI><a href="#[52]">>></a> IntLatch_Init +<LI><a href="#[50]">>></a> ExtLatch_Init +<LI><a href="#[a7]">>></a> ServiceTime +<LI><a href="#[a5]">>></a> Latch_Event +<LI><a href="#[99]">>></a> init_Vibro +<LI><a href="#[90]">>></a> SystemCoreClockUpdate +<LI><a href="#[32]">>></a> SystemInit +</UL> +<BR>[Called By]<UL><LI><a href="#[3e]">>></a> __rt_entry_main +</UL> + +<P><STRONG><a name="[98]"></a>init_PLC</STRONG> (Thumb, 300 bytes, Stack size 72 bytes, plc_reg.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 352<LI>Call Chain = init_PLC ⇒ init_BandPass ⇒ cos ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[b1]">>></a> sin +<LI><a href="#[b3]">>></a> __aeabi_fmul +<LI><a href="#[af]">>></a> __aeabi_i2f +<LI><a href="#[b4]">>></a> __aeabi_f2iz +<LI><a href="#[88]">>></a> __aeabi_f2d +<LI><a href="#[b0]">>></a> __aeabi_dmul +<LI><a href="#[89]">>></a> __aeabi_ddiv +<LI><a href="#[b2]">>></a> __aeabi_d2f +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[b6]"></a>PLC_MeanderDelay</STRONG> (Thumb, 110 bytes, Stack size 0 bytes, plc_reg.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[aa]">>></a> clc_PLC +</UL> + +<P><STRONG><a name="[b7]"></a>WP_PhaseDetectorRate</STRONG> (Thumb, 42 bytes, Stack size 0 bytes, plc_reg.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[aa]">>></a> clc_PLC +</UL> + +<P><STRONG><a name="[aa]"></a>clc_PLC</STRONG> (Thumb, 1030 bytes, Stack size 40 bytes, plc_reg.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 60<LI>Call Chain = clc_PLC ⇒ PLC_PhaseDetFilt +</UL> +<BR>[Calls]<UL><LI><a href="#[b5]">>></a> PLC_PhaseDetFilt +<LI><a href="#[b7]">>></a> WP_PhaseDetectorRate +<LI><a href="#[b6]">>></a> PLC_MeanderDelay +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[14b]"></a>Signal_2_Oscill</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, plc_reg.o(.text), UNUSED) + +<P><STRONG><a name="[ab]"></a>clc_WP_sin</STRONG> (Thumb, 50 bytes, Stack size 8 bytes, plc_reg.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = clc_WP_sin +</UL> +<BR>[Calls]<UL><LI><a href="#[b8]">>></a> DAC_Output +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[a9]"></a>clc_HFO</STRONG> (Thumb, 368 bytes, Stack size 32 bytes, hfo_reg.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = clc_HFO ⇒ HFO_MovAverFilt +</UL> +<BR>[Calls]<UL><LI><a href="#[b9]">>></a> HFO_MovAverFilt +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[ba]"></a>StaticTermoCompens</STRONG> (Thumb, 102 bytes, Stack size 32 bytes, thermocalc.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = StaticTermoCompens ⇒ __aeabi_fmul +</UL> +<BR>[Calls]<UL><LI><a href="#[b3]">>></a> __aeabi_fmul +<LI><a href="#[af]">>></a> __aeabi_i2f +<LI><a href="#[b4]">>></a> __aeabi_f2iz +<LI><a href="#[bb]">>></a> __aeabi_frsub +</UL> +<BR>[Called By]<UL><LI><a href="#[a8]">>></a> clc_ThermoSensors +</UL> + +<P><STRONG><a name="[bc]"></a>DynamicDeltaCalc</STRONG> (Thumb, 212 bytes, Stack size 32 bytes, thermocalc.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = DynamicDeltaCalc ⇒ __aeabi_fmul +</UL> +<BR>[Calls]<UL><LI><a href="#[b3]">>></a> __aeabi_fmul +<LI><a href="#[af]">>></a> __aeabi_i2f +<LI><a href="#[b4]">>></a> __aeabi_f2iz +<LI><a href="#[bb]">>></a> __aeabi_frsub +</UL> +<BR>[Called By]<UL><LI><a href="#[a8]">>></a> clc_ThermoSensors +</UL> + +<P><STRONG><a name="[a8]"></a>clc_ThermoSensors</STRONG> (Thumb, 648 bytes, Stack size 24 bytes, thermocalc.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = clc_ThermoSensors ⇒ DynamicDeltaCalc ⇒ __aeabi_fmul +</UL> +<BR>[Calls]<UL><LI><a href="#[bc]">>></a> DynamicDeltaCalc +<LI><a href="#[ba]">>></a> StaticTermoCompens +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[bd]"></a>DithFreqRangeCalc</STRONG> (Thumb, 264 bytes, Stack size 32 bytes, thermocalc.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[be]">>></a> Max_Saturation +</UL> + +<P><STRONG><a name="[c0]"></a>GLD_Stop</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, cntrlgld.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[ac]">>></a> contrl_GLD +<LI><a href="#[bf]">>></a> GLD_Status +</UL> + +<P><STRONG><a name="[bf]"></a>GLD_Status</STRONG> (Thumb, 62 bytes, Stack size 8 bytes, cntrlgld.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = GLD_Status ⇒ SwitchMode ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[4b]">>></a> SwitchMode +<LI><a href="#[c0]">>></a> GLD_Stop +</UL> +<BR>[Called By]<UL><LI><a href="#[ac]">>></a> contrl_GLD +</UL> + +<P><STRONG><a name="[5]"></a>Sts_Pause</STRONG> (Thumb, 66 bytes, Stack size 0 bytes, cntrlgld.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> cntrlgld.o(.data) +</UL> +<P><STRONG><a name="[4]"></a>Sts_Pulse</STRONG> (Thumb, 78 bytes, Stack size 0 bytes, cntrlgld.o(.text)) +<BR>[Address Reference Count : 1]<UL><LI> cntrlgld.o(.data) +</UL> +<P><STRONG><a name="[6]"></a>Sts_Polling</STRONG> (Thumb, 266 bytes, Stack size 16 bytes, cntrlgld.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = Sts_Polling +</UL> +<BR>[Address Reference Count : 1]<UL><LI> cntrlgld.o(.data) +</UL> +<P><STRONG><a name="[c1]"></a>GLD_Start</STRONG> (Thumb, 80 bytes, Stack size 8 bytes, cntrlgld.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = GLD_Start +</UL> +<BR>[Called By]<UL><LI><a href="#[ac]">>></a> contrl_GLD +</UL> + +<P><STRONG><a name="[c2]"></a>GLD_Pulse</STRONG> (Thumb, 72 bytes, Stack size 8 bytes, cntrlgld.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = GLD_Pulse +</UL> +<BR>[Called By]<UL><LI><a href="#[ac]">>></a> contrl_GLD +</UL> + +<P><STRONG><a name="[ac]"></a>contrl_GLD</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, cntrlgld.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = contrl_GLD ⇒ GLD_Status ⇒ SwitchMode ⇒ UART_SwitchSpeed +</UL> +<BR>[Calls]<UL><LI><a href="#[54]">>></a> GLD_Output +<LI><a href="#[c2]">>></a> GLD_Pulse +<LI><a href="#[c1]">>></a> GLD_Start +<LI><a href="#[bf]">>></a> GLD_Status +<LI><a href="#[c0]">>></a> GLD_Stop +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[84]"></a>init_VibroReduce</STRONG> (Thumb, 202 bytes, Stack size 24 bytes, mathdsp.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = init_VibroReduce +</UL> +<BR>[Called By]<UL><LI><a href="#[83]">>></a> init_Dither_reg +</UL> + +<P><STRONG><a name="[ca]"></a>VibroReduce</STRONG> (Thumb, 242 bytes, Stack size 24 bytes, mathdsp.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = VibroReduce +</UL> +<BR>[Called By]<UL><LI><a href="#[a6]">>></a> clc_Pulses +</UL> + +<P><STRONG><a name="[7e]"></a>DUP_Filt</STRONG> (Thumb, 148 bytes, Stack size 20 bytes, mathdsp.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[7d]">>></a> clc_Dith_regulator +</UL> + +<P><STRONG><a name="[b5]"></a>PLC_PhaseDetFilt</STRONG> (Thumb, 220 bytes, Stack size 20 bytes, mathdsp.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = PLC_PhaseDetFilt +</UL> +<BR>[Called By]<UL><LI><a href="#[aa]">>></a> clc_PLC +</UL> + +<P><STRONG><a name="[8a]"></a>init_BandPass</STRONG> (Thumb, 686 bytes, Stack size 88 bytes, mathdsp.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 280<LI>Call Chain = init_BandPass ⇒ cos ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[c4]">>></a> cos +<LI><a href="#[b0]">>></a> __aeabi_dmul +<LI><a href="#[c7]">>></a> __aeabi_d2iz +<LI><a href="#[89]">>></a> __aeabi_ddiv +<LI><a href="#[c5]">>></a> __aeabi_dsub +<LI><a href="#[c3]">>></a> __aeabi_drsub +<LI><a href="#[c6]">>></a> __aeabi_dadd +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[83]">>></a> init_Dither_reg +</UL> + +<P><STRONG><a name="[b9]"></a>HFO_MovAverFilt</STRONG> (Thumb, 96 bytes, Stack size 8 bytes, mathdsp.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = HFO_MovAverFilt +</UL> +<BR>[Called By]<UL><LI><a href="#[a9]">>></a> clc_HFO +</UL> + +<P><STRONG><a name="[ad]"></a>G_Photo_Exchange</STRONG> (Thumb, 304 bytes, Stack size 0 bytes, inputoutput.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[14c]"></a>DAC_ADC_Exchange</STRONG> (Thumb, 98 bytes, Stack size 0 bytes, inputoutput.o(.text), UNUSED) + +<P><STRONG><a name="[14d]"></a>ADC_Input</STRONG> (Thumb, 96 bytes, Stack size 0 bytes, inputoutput.o(.text), UNUSED) + +<P><STRONG><a name="[b8]"></a>DAC_Output</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, inputoutput.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[ab]">>></a> clc_WP_sin +</UL> + +<P><STRONG><a name="[97]"></a>G_Photo_Init</STRONG> (Thumb, 76 bytes, Stack size 0 bytes, inputoutput.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[93]"></a>DAC_ADC_Exchange_Init</STRONG> (Thumb, 214 bytes, Stack size 0 bytes, inputoutput.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[94]"></a>DACInit</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, inputoutput.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[63]"></a>Out_G_photo</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, inputoutput.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +<LI><a href="#[62]">>></a> M_Gph_W +</UL> + +<P><STRONG><a name="[cb]"></a>ResetBitsOfWord</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, sip.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = ResetBitsOfWord +</UL> +<BR>[Called By]<UL><LI><a href="#[a6]">>></a> clc_Pulses +</UL> + +<P><STRONG><a name="[c8]"></a>interpolation</STRONG> (Thumb, 66 bytes, Stack size 32 bytes, sip.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = interpolation ⇒ __aeabi_ldivmod +</UL> +<BR>[Calls]<UL><LI><a href="#[c9]">>></a> __aeabi_ldivmod +</UL> +<BR>[Called By]<UL><LI><a href="#[a6]">>></a> clc_Pulses +</UL> + +<P><STRONG><a name="[a6]"></a>clc_Pulses</STRONG> (Thumb, 684 bytes, Stack size 8 bytes, sip.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = clc_Pulses ⇒ interpolation ⇒ __aeabi_ldivmod +</UL> +<BR>[Calls]<UL><LI><a href="#[c8]">>></a> interpolation +<LI><a href="#[cb]">>></a> ResetBitsOfWord +<LI><a href="#[ca]">>></a> VibroReduce +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[95]"></a>SOI_Init</STRONG> (Thumb, 154 bytes, Stack size 8 bytes, sip.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = SOI_Init +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[cc]"></a>init_DefaultParam</STRONG> (Thumb, 278 bytes, Stack size 0 bytes, parameters.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[68]">>></a> LoadFlashParam +</UL> + +<P><STRONG><a name="[8f]"></a>FlashDMA_Init</STRONG> (Thumb, 52 bytes, Stack size 0 bytes, parameters.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +<LI><a href="#[68]">>></a> LoadFlashParam +</UL> + +<P><STRONG><a name="[68]"></a>LoadFlashParam</STRONG> (Thumb, 114 bytes, Stack size 4 bytes, parameters.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = LoadFlashParam +</UL> +<BR>[Calls]<UL><LI><a href="#[8f]">>></a> FlashDMA_Init +<LI><a href="#[cc]">>></a> init_DefaultParam +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +<LI><a href="#[67]">>></a> M_LdPar_F +</UL> + +<P><STRONG><a name="[14e]"></a>UART0_Init_m</STRONG> (Thumb, 70 bytes, Stack size 0 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[14f]"></a>UART0_SendByte_m</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[150]"></a>ClearBuffout</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[151]"></a>SendToBuffByte</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[152]"></a>SendToBuff</STRONG> (Thumb, 48 bytes, Stack size 12 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[9e]"></a>SendToBuffStr</STRONG> (Thumb, 44 bytes, Stack size 0 bytes, console.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[a4]"></a>TakeFromBuff</STRONG> (Thumb, 56 bytes, Stack size 0 bytes, console.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[153]"></a>ClearBuffIn</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[154]"></a>BuffDataReady</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[155]"></a>ReadDataInBuff</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, console.o(.text), UNUSED) + +<P><STRONG><a name="[ce]"></a>D_QEI</STRONG> (Thumb, 666 bytes, Stack size 0 bytes, qei.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[13]">>></a> TIMER1_IRQHandler +</UL> + +<P><STRONG><a name="[49]"></a>VibroPush</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, global.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[48]">>></a> cheng +</UL> + +<P><STRONG><a name="[4a]"></a>VibroPull</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, global.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[48]">>></a> cheng +</UL> + +<P><STRONG><a name="[a3]"></a>ButtonLightUP</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, global.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[9a]"></a>init_timer</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, mtimer.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = init_timer +</UL> +<BR>[Calls]<UL><LI><a href="#[cd]">>></a> NVIC_EnableIRQ +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[9b]"></a>enable_timer1</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, mtimer.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[13]"></a>TIMER1_IRQHandler</STRONG> (Thumb, 112 bytes, Stack size 8 bytes, mtimer.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = TIMER1_IRQHandler ⇒ cheng ⇒ CalcAmpN ⇒ srand +</UL> +<BR>[Calls]<UL><LI><a href="#[48]">>></a> cheng +<LI><a href="#[cf]">>></a> SPI_Exchange +<LI><a href="#[ce]">>></a> D_QEI +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[9c]"></a>Init_TIM2</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, mtimer.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = Init_TIM2 +</UL> +<BR>[Calls]<UL><LI><a href="#[cd]">>></a> NVIC_EnableIRQ +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[9d]"></a>enable_timer2</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, mtimer.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[14]"></a>TIMER2_IRQHandler</STRONG> (Thumb, 54 bytes, Stack size 8 bytes, mtimer.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIMER2_IRQHandler +</UL> +<BR>[Calls]<UL><LI><a href="#[d0]">>></a> VibroOut +</UL> +<BR>[Address Reference Count : 1]<UL><LI> startup_lpc17xx.o(RESET) +</UL> +<P><STRONG><a name="[156]"></a>DACLInit</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, spi.o(.text), UNUSED) + +<P><STRONG><a name="[cf]"></a>SPI_Exchange</STRONG> (Thumb, 436 bytes, Stack size 0 bytes, spi.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[13]">>></a> TIMER1_IRQHandler +</UL> + +<P><STRONG><a name="[157]"></a>Init_SPI_Exchange</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, spi.o(.text), UNUSED) + +<P><STRONG><a name="[d2]"></a>Check</STRONG> (Thumb, 78 bytes, Stack size 16 bytes, command.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = Check +</UL> +<BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +<LI><a href="#[a2]">>></a> CMD_Rate +<LI><a href="#[d5]">>></a> CMD_M_Control_D9 +<LI><a href="#[d4]">>></a> CMD_M_Control_D8 +<LI><a href="#[d1]">>></a> CMD_Maintenance +</UL> + +<P><STRONG><a name="[d1]"></a>CMD_Maintenance</STRONG> (Thumb, 60 bytes, Stack size 8 bytes, command.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = CMD_Maintenance ⇒ Check +</UL> +<BR>[Calls]<UL><LI><a href="#[d3]">>></a> WriteConN +<LI><a href="#[d2]">>></a> Check +</UL> +<BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +</UL> + +<P><STRONG><a name="[a2]"></a>CMD_Rate</STRONG> (Thumb, 464 bytes, Stack size 112 bytes, command.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = CMD_Rate ⇒ Check +</UL> +<BR>[Calls]<UL><LI><a href="#[d3]">>></a> WriteConN +<LI><a href="#[d2]">>></a> Check +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[d4]"></a>CMD_M_Control_D8</STRONG> (Thumb, 342 bytes, Stack size 16 bytes, command.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = CMD_M_Control_D8 ⇒ Check +</UL> +<BR>[Calls]<UL><LI><a href="#[d3]">>></a> WriteConN +<LI><a href="#[d2]">>></a> Check +</UL> +<BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +</UL> + +<P><STRONG><a name="[d5]"></a>CMD_M_Control_D9</STRONG> (Thumb, 128 bytes, Stack size 8 bytes, command.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = CMD_M_Control_D9 ⇒ Check +</UL> +<BR>[Calls]<UL><LI><a href="#[d3]">>></a> WriteConN +<LI><a href="#[d2]">>></a> Check +</UL> +<BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +</UL> + +<P><STRONG><a name="[d6]"></a>CMD_M_Stymul</STRONG> (Thumb, 78 bytes, Stack size 32 bytes, command.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = CMD_M_Stymul ⇒ __aeabi_d2f +</UL> +<BR>[Calls]<UL><LI><a href="#[b3]">>></a> __aeabi_fmul +<LI><a href="#[af]">>></a> __aeabi_i2f +<LI><a href="#[d7]">>></a> __aeabi_f2uiz +<LI><a href="#[88]">>></a> __aeabi_f2d +<LI><a href="#[c6]">>></a> __aeabi_dadd +<LI><a href="#[b2]">>></a> __aeabi_d2f +</UL> +<BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +</UL> + +<P><STRONG><a name="[da]"></a>Getlengf</STRONG> (Thumb, 108 bytes, Stack size 0 bytes, command.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +</UL> + +<P><STRONG><a name="[a1]"></a>Read_CMD</STRONG> (Thumb, 352 bytes, Stack size 8 bytes, command.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = Read_CMD ⇒ CMD_M_Stymul ⇒ __aeabi_d2f +</UL> +<BR>[Calls]<UL><LI><a href="#[d9]">>></a> ReadCon +<LI><a href="#[d8]">>></a> ReadChekCon +<LI><a href="#[da]">>></a> Getlengf +<LI><a href="#[d6]">>></a> CMD_M_Stymul +<LI><a href="#[d5]">>></a> CMD_M_Control_D9 +<LI><a href="#[d4]">>></a> CMD_M_Control_D8 +<LI><a href="#[d1]">>></a> CMD_Maintenance +<LI><a href="#[d2]">>></a> Check +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[158]"></a>UART0_Init</STRONG> (Thumb, 80 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[159]"></a>UART1_Init_temp</STRONG> (Thumb, 80 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[15a]"></a>UART2_Init</STRONG> (Thumb, 86 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[15b]"></a>UART3_Init</STRONG> (Thumb, 98 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[15c]"></a>UART2_InitSet</STRONG> (Thumb, 98 bytes, Stack size 12 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[15d]"></a>UART3_InitSet</STRONG> (Thumb, 98 bytes, Stack size 12 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[15e]"></a>UART_InitSet</STRONG> (Thumb, 328 bytes, Stack size 16 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[dc]"></a>UART0_SendByte</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[dd]">>></a> UART0_SendChar +<LI><a href="#[db]">>></a> UART0_SendString +</UL> + +<P><STRONG><a name="[15f]"></a>UART0_GetChar</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[160]"></a>UART1_GetChar</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[161]"></a>UART2_GetChar</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[162]"></a>UART3_GetChar</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[163]"></a>UART0_Chek</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[164]"></a>UART1_Chek</STRONG> (Thumb, 66 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[165]"></a>UART2_Chek</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[166]"></a>UART3_Chek</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[db]"></a>UART0_SendString</STRONG> (Thumb, 22 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[dc]">>></a> UART0_SendByte +</UL> + +<P><STRONG><a name="[167]"></a>UART2_SendByte</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[dd]"></a>UART0_SendChar</STRONG> (Thumb, 124 bytes, Stack size 16 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[dc]">>></a> UART0_SendByte +</UL> + +<P><STRONG><a name="[df]"></a>Delay</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, uart_m.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[e8]">>></a> SetDeUART3 +<LI><a href="#[e7]">>></a> ClrDeUART3 +<LI><a href="#[e5]">>></a> SetDeUART2 +<LI><a href="#[e4]">>></a> ClrDeUART2 +<LI><a href="#[e2]">>></a> SetDeUART1 +<LI><a href="#[e1]">>></a> ClrDeUART1 +<LI><a href="#[e0]">>></a> SetDeUART0 +<LI><a href="#[de]">>></a> ClrDeUART0 +</UL> + +<P><STRONG><a name="[de]"></a>ClrDeUART0</STRONG> (Thumb, 36 bytes, Stack size 4 bytes, uart_m.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = ClrDeUART0 +</UL> +<BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[a0]">>></a> Concol +</UL> + +<P><STRONG><a name="[e0]"></a>SetDeUART0</STRONG> (Thumb, 36 bytes, Stack size 4 bytes, uart_m.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = SetDeUART0 +</UL> +<BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[a0]">>></a> Concol +</UL> + +<P><STRONG><a name="[a0]"></a>Concol</STRONG> (Thumb, 130 bytes, Stack size 4 bytes, uart_m.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = Concol ⇒ SetDeUART0 +</UL> +<BR>[Calls]<UL><LI><a href="#[e0]">>></a> SetDeUART0 +<LI><a href="#[de]">>></a> ClrDeUART0 +</UL> +<BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +</UL> + +<P><STRONG><a name="[168]"></a>Concol1</STRONG> (Thumb, 102 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[e1]"></a>ClrDeUART1</STRONG> (Thumb, 38 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[e3]">>></a> Concol1Fast +</UL> + +<P><STRONG><a name="[e2]"></a>SetDeUART1</STRONG> (Thumb, 38 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[e3]">>></a> Concol1Fast +</UL> + +<P><STRONG><a name="[e3]"></a>Concol1Fast</STRONG> (Thumb, 138 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[e2]">>></a> SetDeUART1 +<LI><a href="#[e1]">>></a> ClrDeUART1 +</UL> + +<P><STRONG><a name="[e4]"></a>ClrDeUART2</STRONG> (Thumb, 38 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[ea]">>></a> Concol2M +<LI><a href="#[e6]">>></a> Concol2 +</UL> + +<P><STRONG><a name="[e5]"></a>SetDeUART2</STRONG> (Thumb, 38 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[ea]">>></a> Concol2M +<LI><a href="#[e6]">>></a> Concol2 +</UL> + +<P><STRONG><a name="[e6]"></a>Concol2</STRONG> (Thumb, 130 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[e5]">>></a> SetDeUART2 +<LI><a href="#[e4]">>></a> ClrDeUART2 +</UL> + +<P><STRONG><a name="[e7]"></a>ClrDeUART3</STRONG> (Thumb, 38 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[e9]">>></a> Concol3 +</UL> + +<P><STRONG><a name="[e8]"></a>SetDeUART3</STRONG> (Thumb, 130 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[df]">>></a> Delay +</UL> +<BR>[Called By]<UL><LI><a href="#[e9]">>></a> Concol3 +</UL> + +<P><STRONG><a name="[e9]"></a>Concol3</STRONG> (Thumb, 130 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[e8]">>></a> SetDeUART3 +<LI><a href="#[e7]">>></a> ClrDeUART3 +</UL> + +<P><STRONG><a name="[ea]"></a>Concol2M</STRONG> (Thumb, 130 bytes, Stack size 4 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[e5]">>></a> SetDeUART2 +<LI><a href="#[e4]">>></a> ClrDeUART2 +</UL> + +<P><STRONG><a name="[9f]"></a>WriteCon</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, uart_m.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3f]">>></a> main +<LI><a href="#[eb]">>></a> WriteConF +</UL> + +<P><STRONG><a name="[ec]"></a>WriteCon1</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[eb]">>></a> WriteConF +</UL> + +<P><STRONG><a name="[d3]"></a>WriteConN</STRONG> (Thumb, 50 bytes, Stack size 8 bytes, uart_m.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = WriteConN +</UL> +<BR>[Called By]<UL><LI><a href="#[a2]">>></a> CMD_Rate +<LI><a href="#[d5]">>></a> CMD_M_Control_D9 +<LI><a href="#[d4]">>></a> CMD_M_Control_D8 +<LI><a href="#[d1]">>></a> CMD_Maintenance +</UL> + +<P><STRONG><a name="[ed]"></a>WriteCon2</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[eb]">>></a> WriteConF +</UL> + +<P><STRONG><a name="[ee]"></a>WriteCon3</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[eb]">>></a> WriteConF +</UL> + +<P><STRONG><a name="[eb]"></a>WriteConF</STRONG> (Thumb, 46 bytes, Stack size 12 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[9f]">>></a> WriteCon +<LI><a href="#[ee]">>></a> WriteCon3 +<LI><a href="#[ed]">>></a> WriteCon2 +<LI><a href="#[ec]">>></a> WriteCon1 +</UL> + +<P><STRONG><a name="[f0]"></a>WriteConByte</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[ef]">>></a> WriteConByteF +</UL> + +<P><STRONG><a name="[f1]"></a>WriteCon1Byte</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[ef]">>></a> WriteConByteF +</UL> + +<P><STRONG><a name="[f2]"></a>WriteCon2Byte</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[ef]">>></a> WriteConByteF +</UL> + +<P><STRONG><a name="[f3]"></a>WriteCon3Byte</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[ef]">>></a> WriteConByteF +</UL> + +<P><STRONG><a name="[ef]"></a>WriteConByteF</STRONG> (Thumb, 46 bytes, Stack size 12 bytes, uart_m.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[f3]">>></a> WriteCon3Byte +<LI><a href="#[f2]">>></a> WriteCon2Byte +<LI><a href="#[f1]">>></a> WriteCon1Byte +<LI><a href="#[f0]">>></a> WriteConByte +</UL> + +<P><STRONG><a name="[d9]"></a>ReadCon</STRONG> (Thumb, 58 bytes, Stack size 0 bytes, uart_m.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +</UL> + +<P><STRONG><a name="[169]"></a>ReadCon1</STRONG> (Thumb, 58 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[16a]"></a>ReadCon2</STRONG> (Thumb, 58 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[16b]"></a>ReadCon3</STRONG> (Thumb, 58 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[d8]"></a>ReadChekCon</STRONG> (Thumb, 162 bytes, Stack size 0 bytes, uart_m.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[a1]">>></a> Read_CMD +</UL> + +<P><STRONG><a name="[16c]"></a>ReadChekCon1</STRONG> (Thumb, 42 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[16d]"></a>ReadChekCon2</STRONG> (Thumb, 42 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[16e]"></a>ReadChekCon3</STRONG> (Thumb, 42 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[16f]"></a>ChekInCon</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[170]"></a>ChekInCon1</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[171]"></a>ChekInCon2</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[172]"></a>ChekInCon3</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[173]"></a>ChekOutCon</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[174]"></a>ChekOutCon1</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[175]"></a>ChekOutCon2</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[176]"></a>ChekOutCon3</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, uart_m.o(.text), UNUSED) + +<P><STRONG><a name="[c9]"></a>__aeabi_ldivmod</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, llsdiv.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_ldivmod +</UL> +<BR>[Called By]<UL><LI><a href="#[c8]">>></a> interpolation +</UL> + +<P><STRONG><a name="[f4]"></a>_ll_sdiv</STRONG> (Thumb, 72 bytes, Stack size 8 bytes, llsdiv.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[f5]">>></a> __aeabi_uldivmod +</UL> + +<P><STRONG><a name="[46]"></a>srand</STRONG> (Thumb, 42 bytes, Stack size 8 bytes, rand.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = srand +</UL> +<BR>[Called By]<UL><LI><a href="#[81]">>></a> clc_Noise_regulator +<LI><a href="#[45]">>></a> CalcAmpN +<LI><a href="#[39]">>></a> _rand_init +</UL> + +<P><STRONG><a name="[39]"></a>_rand_init</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, rand.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _rand_init ⇒ srand +</UL> +<BR>[Calls]<UL><LI><a href="#[46]">>></a> srand +</UL> +<BR>[Called By]<UL><LI><a href="#[38]">>></a> __rt_lib_init_rand_2 +</UL> + +<P><STRONG><a name="[7c]"></a>__aeabi_memcpy</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[7b]">>></a> decode_CMD +</UL> + +<P><STRONG><a name="[f6]"></a>__rt_memcpy</STRONG> (Thumb, 138 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[f7]">>></a> __aeabi_memcpy4 +</UL> + +<P><STRONG><a name="[177]"></a>_memcpy_lastbytes</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_v6.o(.text), UNUSED) + +<P><STRONG><a name="[178]"></a>__use_two_region_memory</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +<P><STRONG><a name="[179]"></a>__rt_heap_escrow$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +<P><STRONG><a name="[17a]"></a>__rt_heap_expand$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +<P><STRONG><a name="[f5]"></a>__aeabi_uldivmod</STRONG> (Thumb, 0 bytes, Stack size 48 bytes, lludivv7m.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[f4]">>></a> _ll_sdiv +</UL> + +<P><STRONG><a name="[17b]"></a>_ll_udiv</STRONG> (Thumb, 238 bytes, Stack size 48 bytes, lludivv7m.o(.text), UNUSED) + +<P><STRONG><a name="[f8]"></a>__read_errno</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, _rserrno.o(.text), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[f9]">>></a> __aeabi_errno_addr +</UL> + +<P><STRONG><a name="[fa]"></a>__set_errno</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, _rserrno.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __set_errno +</UL> +<BR>[Calls]<UL><LI><a href="#[f9]">>></a> __aeabi_errno_addr +</UL> +<BR>[Called By]<UL><LI><a href="#[b1]">>></a> sin +<LI><a href="#[c4]">>></a> cos +</UL> + +<P><STRONG><a name="[f7]"></a>__aeabi_memcpy4</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[f6]">>></a> __rt_memcpy +</UL> + +<P><STRONG><a name="[17c]"></a>__aeabi_memcpy8</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED) + +<P><STRONG><a name="[17d]"></a>__rt_memcpy_w</STRONG> (Thumb, 100 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED) + +<P><STRONG><a name="[17e]"></a>_memcpy_lastbytes_aligned</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_w.o(.text), UNUSED) + +<P><STRONG><a name="[f9]"></a>__aeabi_errno_addr</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[fa]">>></a> __set_errno +<LI><a href="#[f8]">>></a> __read_errno +</UL> + +<P><STRONG><a name="[17f]"></a>__errno$intlibspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text), UNUSED) + +<P><STRONG><a name="[180]"></a>__rt_errno_addr$intlibspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text), UNUSED) + +<P><STRONG><a name="[181]"></a>__user_libspace</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +<P><STRONG><a name="[fb]"></a>__user_perproc_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[3b]">>></a> __user_setup_stackheap +</UL> + +<P><STRONG><a name="[182]"></a>__user_perthread_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +<P><STRONG><a name="[3b]"></a>__user_setup_stackheap</STRONG> (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size +<LI>Call Chain = __user_setup_stackheap +</UL> +<BR>[Calls]<UL><LI><a href="#[fc]">>></a> __user_initial_stackheap +<LI><a href="#[fb]">>></a> __user_perproc_libspace +</UL> +<BR>[Called By]<UL><LI><a href="#[3a]">>></a> __rt_entry_sh +</UL> + +<P><STRONG><a name="[40]"></a>exit</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, exit.o(.text)) +<BR><BR>[Calls]<UL><LI><a href="#[fd]">>></a> __rt_exit +</UL> +<BR>[Called By]<UL><LI><a href="#[3e]">>></a> __rt_entry_main +</UL> + +<P><STRONG><a name="[183]"></a>__I$use$semihosting</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +<P><STRONG><a name="[184]"></a>__use_no_semihosting_swi</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +<P><STRONG><a name="[185]"></a>__semihosting_library_function</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, indicate_semi.o(.text), UNUSED) + +<P><STRONG><a name="[44]"></a>_sys_exit</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[43]">>></a> __rt_exit_exit +</UL> + +<P><STRONG><a name="[be]"></a>Max_Saturation</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, thermocalc.o(i.Max_Saturation), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[bd]">>></a> DithFreqRangeCalc +</UL> + +<P><STRONG><a name="[105]"></a>__ARM_fpclassify</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, fpclassify.o(i.__ARM_fpclassify)) +<BR><BR>[Called By]<UL><LI><a href="#[104]">>></a> __kernel_sin +</UL> + +<P><STRONG><a name="[fe]"></a>__ieee754_rem_pio2</STRONG> (Thumb, 828 bytes, Stack size 128 bytes, rred.o(i.__ieee754_rem_pio2)) +<BR><BR>[Stack]<UL><LI>Max Depth = 160<LI>Call Chain = __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[b0]">>></a> __aeabi_dmul +<LI><a href="#[c7]">>></a> __aeabi_d2iz +<LI><a href="#[c5]">>></a> __aeabi_dsub +<LI><a href="#[c3]">>></a> __aeabi_drsub +<LI><a href="#[c6]">>></a> __aeabi_dadd +<LI><a href="#[101]">>></a> __ARM_scalbn +<LI><a href="#[100]">>></a> __aeabi_ui2d +<LI><a href="#[ff]">>></a> __aeabi_i2d +</UL> +<BR>[Called By]<UL><LI><a href="#[b1]">>></a> sin +<LI><a href="#[c4]">>></a> cos +</UL> + +<P><STRONG><a name="[102]"></a>__kernel_cos</STRONG> (Thumb, 230 bytes, Stack size 48 bytes, cos_i.o(i.__kernel_cos)) +<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = __kernel_cos ⇒ __kernel_poly ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[b0]">>></a> __aeabi_dmul +<LI><a href="#[c7]">>></a> __aeabi_d2iz +<LI><a href="#[c5]">>></a> __aeabi_dsub +<LI><a href="#[c3]">>></a> __aeabi_drsub +<LI><a href="#[103]">>></a> __kernel_poly +<LI><a href="#[101]">>></a> __ARM_scalbn +</UL> +<BR>[Called By]<UL><LI><a href="#[b1]">>></a> sin +<LI><a href="#[c4]">>></a> cos +</UL> + +<P><STRONG><a name="[103]"></a>__kernel_poly</STRONG> (Thumb, 170 bytes, Stack size 24 bytes, poly.o(i.__kernel_poly)) +<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = __kernel_poly ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[b0]">>></a> __aeabi_dmul +<LI><a href="#[c6]">>></a> __aeabi_dadd +</UL> +<BR>[Called By]<UL><LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[104]">>></a> __kernel_sin +</UL> + +<P><STRONG><a name="[104]"></a>__kernel_sin</STRONG> (Thumb, 224 bytes, Stack size 64 bytes, sin_i.o(i.__kernel_sin)) +<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = __kernel_sin ⇒ __kernel_poly ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[b0]">>></a> __aeabi_dmul +<LI><a href="#[c5]">>></a> __aeabi_dsub +<LI><a href="#[c3]">>></a> __aeabi_drsub +<LI><a href="#[c6]">>></a> __aeabi_dadd +<LI><a href="#[103]">>></a> __kernel_poly +<LI><a href="#[105]">>></a> __ARM_fpclassify +<LI><a href="#[101]">>></a> __ARM_scalbn +<LI><a href="#[106]">>></a> __mathlib_dbl_underflow +</UL> +<BR>[Called By]<UL><LI><a href="#[b1]">>></a> sin +<LI><a href="#[c4]">>></a> cos +</UL> + +<P><STRONG><a name="[107]"></a>__mathlib_dbl_infnan</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, dunder.o(i.__mathlib_dbl_infnan)) +<BR><BR>[Calls]<UL><LI><a href="#[101]">>></a> __ARM_scalbn +</UL> +<BR>[Called By]<UL><LI><a href="#[b1]">>></a> sin +<LI><a href="#[c4]">>></a> cos +</UL> + +<P><STRONG><a name="[108]"></a>__mathlib_dbl_invalid</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, dunder.o(i.__mathlib_dbl_invalid)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __mathlib_dbl_invalid ⇒ __aeabi_ddiv +</UL> +<BR>[Calls]<UL><LI><a href="#[89]">>></a> __aeabi_ddiv +</UL> +<BR>[Called By]<UL><LI><a href="#[b1]">>></a> sin +<LI><a href="#[c4]">>></a> cos +</UL> + +<P><STRONG><a name="[106]"></a>__mathlib_dbl_underflow</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, dunder.o(i.__mathlib_dbl_underflow)) +<BR><BR>[Calls]<UL><LI><a href="#[101]">>></a> __ARM_scalbn +</UL> +<BR>[Called By]<UL><LI><a href="#[104]">>></a> __kernel_sin +</UL> + +<P><STRONG><a name="[c4]"></a>cos</STRONG> (Thumb, 148 bytes, Stack size 32 bytes, cos.o(i.cos)) +<BR><BR>[Stack]<UL><LI>Max Depth = 192<LI>Call Chain = cos ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[fa]">>></a> __set_errno +<LI><a href="#[104]">>></a> __kernel_sin +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +<LI><a href="#[108]">>></a> __mathlib_dbl_invalid +<LI><a href="#[107]">>></a> __mathlib_dbl_infnan +</UL> +<BR>[Called By]<UL><LI><a href="#[8a]">>></a> init_BandPass +</UL> + +<P><STRONG><a name="[b1]"></a>sin</STRONG> (Thumb, 150 bytes, Stack size 32 bytes, sin.o(i.sin)) +<BR><BR>[Stack]<UL><LI>Max Depth = 192<LI>Call Chain = sin ⇒ __ieee754_rem_pio2 ⇒ __aeabi_dmul +</UL> +<BR>[Calls]<UL><LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[fa]">>></a> __set_errno +<LI><a href="#[104]">>></a> __kernel_sin +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +<LI><a href="#[108]">>></a> __mathlib_dbl_invalid +<LI><a href="#[107]">>></a> __mathlib_dbl_infnan +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +</UL> + +<P><STRONG><a name="[b2]"></a>__aeabi_d2f</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, d2f.o(x$fpl$d2f)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __aeabi_d2f +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[d6]">>></a> CMD_M_Stymul +</UL> + +<P><STRONG><a name="[109]"></a>_d2f</STRONG> (Thumb, 98 bytes, Stack size 32 bytes, d2f.o(x$fpl$d2f), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10a]">>></a> __fpl_fretinf +<LI><a href="#[10b]">>></a> __fpl_dnaninf +</UL> + +<P><STRONG><a name="[c6]"></a>__aeabi_dadd</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, daddsub_clz.o(x$fpl$dadd)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_dadd +</UL> +<BR>[Called By]<UL><LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[d6]">>></a> CMD_M_Stymul +<LI><a href="#[103]">>></a> __kernel_poly +<LI><a href="#[104]">>></a> __kernel_sin +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +</UL> + +<P><STRONG><a name="[10c]"></a>_dadd</STRONG> (Thumb, 332 bytes, Stack size 16 bytes, daddsub_clz.o(x$fpl$dadd), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10e]">>></a> __fpl_dretinf +<LI><a href="#[10b]">>></a> __fpl_dnaninf +<LI><a href="#[10d]">>></a> _dsub1 +</UL> + +<P><STRONG><a name="[10f]"></a>__fpl_dcheck_NaN1</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, dcheck1.o(x$fpl$dcheck1)) +<BR><BR>[Calls]<UL><LI><a href="#[110]">>></a> __fpl_return_NaN +</UL> +<BR>[Called By]<UL><LI><a href="#[101]">>></a> __ARM_scalbn +</UL> + +<P><STRONG><a name="[89]"></a>__aeabi_ddiv</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, ddiv.o(x$fpl$ddiv)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __aeabi_ddiv +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[83]">>></a> init_Dither_reg +<LI><a href="#[108]">>></a> __mathlib_dbl_invalid +</UL> + +<P><STRONG><a name="[111]"></a>_ddiv</STRONG> (Thumb, 552 bytes, Stack size 32 bytes, ddiv.o(x$fpl$ddiv), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10e]">>></a> __fpl_dretinf +<LI><a href="#[10b]">>></a> __fpl_dnaninf +</UL> + +<P><STRONG><a name="[c7]"></a>__aeabi_d2iz</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, dfix.o(x$fpl$dfix)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __aeabi_d2iz +</UL> +<BR>[Called By]<UL><LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +</UL> + +<P><STRONG><a name="[112]"></a>_dfix</STRONG> (Thumb, 94 bytes, Stack size 32 bytes, dfix.o(x$fpl$dfix), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10b]">>></a> __fpl_dnaninf +</UL> + +<P><STRONG><a name="[ff]"></a>__aeabi_i2d</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dflt)) +<BR><BR>[Called By]<UL><LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +</UL> + +<P><STRONG><a name="[186]"></a>_dflt</STRONG> (Thumb, 46 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dflt), UNUSED) + +<P><STRONG><a name="[100]"></a>__aeabi_ui2d</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dfltu)) +<BR><BR>[Called By]<UL><LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +</UL> + +<P><STRONG><a name="[187]"></a>_dfltu</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dfltu), UNUSED) + +<P><STRONG><a name="[b0]"></a>__aeabi_dmul</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __aeabi_dmul +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[103]">>></a> __kernel_poly +<LI><a href="#[104]">>></a> __kernel_sin +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +</UL> + +<P><STRONG><a name="[113]"></a>_dmul</STRONG> (Thumb, 332 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10e]">>></a> __fpl_dretinf +<LI><a href="#[10b]">>></a> __fpl_dnaninf +</UL> + +<P><STRONG><a name="[10b]"></a>__fpl_dnaninf</STRONG> (Thumb, 156 bytes, Stack size 16 bytes, dnaninf.o(x$fpl$dnaninf), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[113]">>></a> _dmul +<LI><a href="#[112]">>></a> _dfix +<LI><a href="#[111]">>></a> _ddiv +<LI><a href="#[116]">>></a> _dsub +<LI><a href="#[10c]">>></a> _dadd +<LI><a href="#[109]">>></a> _d2f +</UL> + +<P><STRONG><a name="[10e]"></a>__fpl_dretinf</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, dretinf.o(x$fpl$dretinf), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[117]">>></a> _f2d +<LI><a href="#[113]">>></a> _dmul +<LI><a href="#[111]">>></a> _ddiv +<LI><a href="#[10c]">>></a> _dadd +</UL> + +<P><STRONG><a name="[c3]"></a>__aeabi_drsub</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, daddsub_clz.o(x$fpl$drsb)) +<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_drsub +</UL> +<BR>[Called By]<UL><LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[104]">>></a> __kernel_sin +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +</UL> + +<P><STRONG><a name="[114]"></a>_drsb</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, daddsub_clz.o(x$fpl$drsb), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10d]">>></a> _dsub1 +<LI><a href="#[115]">>></a> _dadd1 +</UL> + +<P><STRONG><a name="[c5]"></a>__aeabi_dsub</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, daddsub_clz.o(x$fpl$dsub)) +<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __aeabi_dsub +</UL> +<BR>[Called By]<UL><LI><a href="#[8a]">>></a> init_BandPass +<LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[104]">>></a> __kernel_sin +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +</UL> + +<P><STRONG><a name="[116]"></a>_dsub</STRONG> (Thumb, 464 bytes, Stack size 32 bytes, daddsub_clz.o(x$fpl$dsub), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10b]">>></a> __fpl_dnaninf +<LI><a href="#[115]">>></a> _dadd1 +</UL> + +<P><STRONG><a name="[88]"></a>__aeabi_f2d</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_f2d +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[83]">>></a> init_Dither_reg +<LI><a href="#[d6]">>></a> CMD_M_Stymul +</UL> + +<P><STRONG><a name="[117]"></a>_f2d</STRONG> (Thumb, 86 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[118]">>></a> __fpl_fnaninf +<LI><a href="#[10e]">>></a> __fpl_dretinf +</UL> + +<P><STRONG><a name="[188]"></a>__aeabi_fadd</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fadd), UNUSED) + +<P><STRONG><a name="[119]"></a>_fadd</STRONG> (Thumb, 196 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fadd), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10a]">>></a> __fpl_fretinf +<LI><a href="#[118]">>></a> __fpl_fnaninf +<LI><a href="#[11a]">>></a> _fsub1 +</UL> + +<P><STRONG><a name="[b4]"></a>__aeabi_f2iz</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, ffix.o(x$fpl$ffix)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_f2iz +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[bc]">>></a> DynamicDeltaCalc +<LI><a href="#[ba]">>></a> StaticTermoCompens +</UL> + +<P><STRONG><a name="[11b]"></a>_ffix</STRONG> (Thumb, 54 bytes, Stack size 16 bytes, ffix.o(x$fpl$ffix), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[118]">>></a> __fpl_fnaninf +</UL> + +<P><STRONG><a name="[d7]"></a>__aeabi_f2uiz</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, ffixu.o(x$fpl$ffixu)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_f2uiz +</UL> +<BR>[Called By]<UL><LI><a href="#[d6]">>></a> CMD_M_Stymul +</UL> + +<P><STRONG><a name="[11c]"></a>_ffixu</STRONG> (Thumb, 62 bytes, Stack size 16 bytes, ffixu.o(x$fpl$ffixu), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[118]">>></a> __fpl_fnaninf +</UL> + +<P><STRONG><a name="[af]"></a>__aeabi_i2f</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$fflt)) +<BR><BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[d6]">>></a> CMD_M_Stymul +<LI><a href="#[bc]">>></a> DynamicDeltaCalc +<LI><a href="#[ba]">>></a> StaticTermoCompens +</UL> + +<P><STRONG><a name="[189]"></a>_fflt</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$fflt), UNUSED) + +<P><STRONG><a name="[87]"></a>__aeabi_ui2f</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$ffltu)) +<BR><BR>[Called By]<UL><LI><a href="#[83]">>></a> init_Dither_reg +</UL> + +<P><STRONG><a name="[18a]"></a>_ffltu</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$ffltu), UNUSED) + +<P><STRONG><a name="[b3]"></a>__aeabi_fmul</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul)) +<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_fmul +</UL> +<BR>[Called By]<UL><LI><a href="#[98]">>></a> init_PLC +<LI><a href="#[d6]">>></a> CMD_M_Stymul +<LI><a href="#[bc]">>></a> DynamicDeltaCalc +<LI><a href="#[ba]">>></a> StaticTermoCompens +</UL> + +<P><STRONG><a name="[11d]"></a>_fmul</STRONG> (Thumb, 258 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[10a]">>></a> __fpl_fretinf +<LI><a href="#[118]">>></a> __fpl_fnaninf +</UL> + +<P><STRONG><a name="[118]"></a>__fpl_fnaninf</STRONG> (Thumb, 140 bytes, Stack size 8 bytes, fnaninf.o(x$fpl$fnaninf), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[11d]">>></a> _fmul +<LI><a href="#[11c]">>></a> _ffixu +<LI><a href="#[11b]">>></a> _ffix +<LI><a href="#[120]">>></a> _fsub +<LI><a href="#[119]">>></a> _fadd +<LI><a href="#[117]">>></a> _f2d +</UL> + +<P><STRONG><a name="[10a]"></a>__fpl_fretinf</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, fretinf.o(x$fpl$fretinf), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[11d]">>></a> _fmul +<LI><a href="#[119]">>></a> _fadd +<LI><a href="#[109]">>></a> _d2f +</UL> + +<P><STRONG><a name="[bb]"></a>__aeabi_frsub</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, faddsub_clz.o(x$fpl$frsb)) +<BR><BR>[Called By]<UL><LI><a href="#[bc]">>></a> DynamicDeltaCalc +<LI><a href="#[ba]">>></a> StaticTermoCompens +</UL> + +<P><STRONG><a name="[11e]"></a>_frsb</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, faddsub_clz.o(x$fpl$frsb), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[11a]">>></a> _fsub1 +<LI><a href="#[11f]">>></a> _fadd1 +</UL> + +<P><STRONG><a name="[18b]"></a>__aeabi_fsub</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fsub), UNUSED) + +<P><STRONG><a name="[120]"></a>_fsub</STRONG> (Thumb, 234 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fsub), UNUSED) +<BR><BR>[Calls]<UL><LI><a href="#[118]">>></a> __fpl_fnaninf +<LI><a href="#[11f]">>></a> _fadd1 +</UL> + +<P><STRONG><a name="[110]"></a>__fpl_return_NaN</STRONG> (Thumb, 100 bytes, Stack size 0 bytes, retnan.o(x$fpl$retnan)) +<BR><BR>[Calls]<UL><LI><a href="#[121]">>></a> __fpl_cmpreturn +</UL> +<BR>[Called By]<UL><LI><a href="#[10f]">>></a> __fpl_dcheck_NaN1 +</UL> + +<P><STRONG><a name="[101]"></a>__ARM_scalbn</STRONG> (Thumb, 92 bytes, Stack size 0 bytes, scalbn.o(x$fpl$scalbn)) +<BR><BR>[Calls]<UL><LI><a href="#[10f]">>></a> __fpl_dcheck_NaN1 +</UL> +<BR>[Called By]<UL><LI><a href="#[102]">>></a> __kernel_cos +<LI><a href="#[104]">>></a> __kernel_sin +<LI><a href="#[fe]">>></a> __ieee754_rem_pio2 +<LI><a href="#[106]">>></a> __mathlib_dbl_underflow +<LI><a href="#[107]">>></a> __mathlib_dbl_infnan +</UL> + +<P><STRONG><a name="[121]"></a>__fpl_cmpreturn</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, trapv.o(x$fpl$trapveneer)) +<BR><BR>[Called By]<UL><LI><a href="#[110]">>></a> __fpl_return_NaN +</UL> +<P> +<H3> +Local Symbols +</H3> +<P><STRONG><a name="[51]"></a>NVIC_EnableIRQ</STRONG> (Thumb, 140 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[52]">>></a> IntLatch_Init +<LI><a href="#[50]">>></a> ExtLatch_Init +</UL> + +<P><STRONG><a name="[4f]"></a>NVIC_DisableIRQ</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, cyclessync.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[53]">>></a> WDTInit +<LI><a href="#[50]">>></a> ExtLatch_Init +<LI><a href="#[4e]">>></a> CounterIquiryCycle_Init +</UL> + +<P><STRONG><a name="[cd]"></a>NVIC_EnableIRQ</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, mtimer.o(.text)) +<BR><BR>[Called By]<UL><LI><a href="#[9a]">>></a> init_timer +<LI><a href="#[9c]">>></a> Init_TIM2 +</UL> + +<P><STRONG><a name="[115]"></a>_dadd1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, daddsub_clz.o(x$fpl$dadd), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[116]">>></a> _dsub +<LI><a href="#[114]">>></a> _drsb +</UL> + +<P><STRONG><a name="[10d]"></a>_dsub1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, daddsub_clz.o(x$fpl$dsub), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[114]">>></a> _drsb +<LI><a href="#[10c]">>></a> _dadd +</UL> + +<P><STRONG><a name="[11f]"></a>_fadd1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, faddsub_clz.o(x$fpl$fadd), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[120]">>></a> _fsub +<LI><a href="#[11e]">>></a> _frsb +</UL> + +<P><STRONG><a name="[11a]"></a>_fsub1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, faddsub_clz.o(x$fpl$fsub), UNUSED) +<BR><BR>[Called By]<UL><LI><a href="#[11e]">>></a> _frsb +<LI><a href="#[119]">>></a> _fadd +</UL> +<P> +<H3> +Undefined Global Symbols +</H3><HR></body></html>
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/LandTiger_DMA.lnp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/LandTiger_DMA.lnp Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,29 @@ +--cpu Cortex-M3 +".\obj\startup_lpc17xx.o" +".\obj\core_cm3.o" +".\obj\system_lpc17xx.o" +".\obj\vibro.o" +".\obj\cyclessync.o" +".\obj\commandset.o" +".\obj\dither_reg.o" +".\obj\el_lin.o" +".\obj\main.o" +".\obj\plc_reg.o" +".\obj\hfo_reg.o" +".\obj\thermocalc.o" +".\obj\cntrlgld.o" +".\obj\mathdsp.o" +".\obj\inputoutput.o" +".\obj\sip.o" +".\obj\parameters.o" +".\obj\console.o" +".\obj\qei.o" +".\obj\global.o" +".\obj\mtimer.o" +".\obj\spi.o" +".\obj\command.o" +".\obj\uart_m.o" +--strict --scatter ".\Obj\LandTiger_DMA.sct" +--summary_stderr --info summarysizes --map --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\List\LandTiger_DMA.map" -o .\Obj\LandTiger_DMA.axf \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/LandTiger_DMA.sct --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/LandTiger_DMA.sct Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,18 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00027FFF { ; load region size_region + ER_IROM1 0x00000000 0x00027FFF { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x10000000 UNINIT 0x00008000 { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 0x2007C000 0x00008000 { + .ANY (+RW +ZI) + } +} +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/LandTiger_DMA_LandTiger_DMA.dep --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/LandTiger_DMA_LandTiger_DMA.dep Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,292 @@ +Dependencies for Project 'LandTiger_DMA', Target 'LandTiger_DMA': (DO NOT MODIFY !) +F (.\Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm\startup_LPC17xx.s)(0x512C9542)(--cpu Cortex-M3 -g --apcs=interwork -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx --pd "__UVISION_VERSION SETA 515" --pd "NO_CRP SETA 1" --list .\list\startup_lpc17xx.lst --xref -o .\obj\startup_lpc17xx.o --depend .\obj\startup_lpc17xx.d) +F (.\Source\CMSIS\CM3\CoreSupport\core_cm3.c)(0x4AEA5B64)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\core_cm3.o --omf_browse .\obj\core_cm3.crf --depend .\obj\core_cm3.d) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +F (.\Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.c)(0x56434A55)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\system_lpc17xx.o --omf_browse .\obj\system_lpc17xx.crf --depend .\obj\system_lpc17xx.d) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +I (Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\LPC17xx.h)(0x55C4BB90) +I (.\Source\App\core_cm3.h)(0x55B8D52D) +I (.\Source\App\core_cmInstr.h)(0x511A1EAD) +I (.\Source\App\core_cmFunc.h)(0x511A1EC3) +I (Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.h)(0x4BE3DD88) +F (.\Source\App\vibro.c)(0x5694F52C)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\vibro.o --omf_browse .\obj\vibro.crf --depend .\obj\vibro.d) +I (Source\App\vibro.h)(0x569659D7) +I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x5645EC7B) +I (Source\App\lpc17xx.h)(0x511A1E5E) +I (Source\App\core_cm3.h)(0x55B8D52D) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +I (Source\App\core_cmInstr.h)(0x511A1EAD) +I (Source\App\core_cmFunc.h)(0x511A1EC3) +I (Source\App\system_LPC17xx.h)(0x511A1EDB) +I (C:\Keil_v5\ARM\ARMCC\include\ctime)(0x54C28C08) +I (C:\Keil_v5\ARM\ARMCC\include\time.h)(0x54C28C08) +I (Source\App\InputOutput.h)(0x563B0E3F) +I (Source\App\stdint.h)(0x511A1E8B) +I (Source\App\Parameters.h)(0x561B6047) +I (Source\App\CntrlGLD.h)(0x561D13F5) +I (Source\App\CyclesSync.h)(0x512C89CD) +I (Source\App\SIP.h)(0x55BB6023) +I (Source\App\QEI.h)(0x5683964E) +I (Source\App\Global.h)(0x56A21870) +I (Source\App\MTimer.h)(0x56B0B806) +F (.\Source\App\CyclesSync.c)(0x563B0156)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\cyclessync.o --omf_browse .\obj\cyclessync.crf --depend .\obj\cyclessync.d) +I (Source\App\CyclesSync.h)(0x512C89CD) +I (Source\App\lpc17xx.h)(0x511A1E5E) +I (Source\App\core_cm3.h)(0x55B8D52D) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +I (Source\App\core_cmInstr.h)(0x511A1EAD) +I (Source\App\core_cmFunc.h)(0x511A1EC3) +I (Source\App\system_LPC17xx.h)(0x511A1EDB) +I (Source\App\CntrlGLD.h)(0x561D13F5) +I (Source\App\SIP.h)(0x55BB6023) +I (Source\App\el_lin.h)(0x561B8D45) +I (Source\App\inputOutput.h)(0x563B0E3F) +I (Source\App\stdint.h)(0x511A1E8B) +F (.\Source\App\commandset.c)(0x567D48D3)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\commandset.o --omf_browse .\obj\commandset.crf --depend .\obj\commandset.d) +I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x54C28C08) +I (Source\App\commandset.h)(0x4F4C80E2) +I (Source\App\stdint.h)(0x511A1E8B) +I (Source\App\el_lin.h)(0x561B8D45) +I (Source\App\CyclesSync.h)(0x512C89CD) +I (Source\App\lpc17xx.h)(0x511A1E5E) +I (Source\App\core_cm3.h)(0x55B8D52D) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +I (Source\App\core_cmInstr.h)(0x511A1EAD) +I (Source\App\core_cmFunc.h)(0x511A1EC3) +I (Source\App\system_LPC17xx.h)(0x511A1EDB) +I (Source\App\CntrlGLD.h)(0x561D13F5) +I (Source\App\InputOutput.h)(0x563B0E3F) +I (Source\App\Parameters.h)(0x561B6047) +F (.\Source\App\Dither_Reg.c)(0x561FA0BB)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\dither_reg.o --omf_browse .\obj\dither_reg.crf --depend .\obj\dither_reg.d) +I (Source\App\lpc17xx.h)(0x511A1E5E) +I (Source\App\core_cm3.h)(0x55B8D52D) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +I (Source\App\core_cmInstr.h)(0x511A1EAD) +I (Source\App\core_cmFunc.h)(0x511A1EC3) +I (Source\App\system_LPC17xx.h)(0x511A1EDB) +I (Source\App\mathDSP.h)(0x56091744) +I (C:\Keil_v5\ARM\ARMCC\include\dspfns.h)(0x55C318C4) +I (C:\Keil_v5\ARM\ARMCC\include\assert.h)(0x54C28C08) +I (Source\App\InputOutput.h)(0x563B0E3F) +I (Source\App\stdint.h)(0x511A1E8B) +I (Source\App\CyclesSync.h)(0x512C89CD) +I (Source\App\CntrlGLD.h)(0x561D13F5) +I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x5645EC7B) +I (Source\App\sip.h)(0x55BB6023) +I (Source\App\console.h)(0x5649AFF6) +F (.\Source\App\el_lin.c)(0x5680F878)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\el_lin.o --omf_browse .\obj\el_lin.crf --depend .\obj\el_lin.d) +I (Source\App\CyclesSync.h)(0x512C89CD) +I (Source\App\lpc17xx.h)(0x511A1E5E) +I (Source\App\core_cm3.h)(0x55B8D52D) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +I (Source\App\core_cmInstr.h)(0x511A1EAD) +I (Source\App\core_cmFunc.h)(0x511A1EC3) +I (Source\App\system_LPC17xx.h)(0x511A1EDB) +I (Source\App\CntrlGLD.h)(0x561D13F5) +I (Source\App\el_lin.h)(0x561B8D45) +F (.\Source\App\main.c)(0x56B1AEAB)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I C:\Keil_v5\ARM\CMSIS\Include -I C:\Keil_v5\ARM\Inc\NXP\LPC17xx -D__UVISION_VERSION="515" -o .\obj\main.o --omf_browse .\obj\main.crf --depend .\obj\main.d) +I (Source\App\SIP.h)(0x55BB6023) +I (Source\App\el_lin.h)(0x561B8D45) +I (Source\App\CyclesSync.h)(0x512C89CD) +I (Source\App\lpc17xx.h)(0x511A1E5E) +I (Source\App\core_cm3.h)(0x55B8D52D) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x54C28C08) +I (Source\App\core_cmInstr.h)(0x511A1EAD) +I (Source\App\core_cmFunc.h)(0x511A1EC3) +I (Source\App\system_LPC17xx.h)(0x511A1EDB) +I (Source\App\CntrlGLD.h)(0x561D13F5) +I (Source\App\Parameters.h)(0x561B6047) +I (Source\App\Dither_Reg.h)(0x56974547) +I (Source\App\commandset.h)(0x4F4C80E2) +I (Source\App\stdint.h)(0x511A1E8B) +I (Source\App\InputOutput.h)(0x563B0E3F) +I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x54C28C08) +I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x5645EC7B) +I (Source\App\console.h)(0x5649AFF6) +I (Source\App\vibro.h)(0x569659D7) +I (Source\App\QEI.h)(0x5683964E) +I (Source\App\MTimer.h)(0x56B0B806) +I (Source\App\Global.h)(0x56A21870) +I (Source\App\SPI.h)(0x567D148F) +I (Source\App\uart_m.h)(0x5680F70C) +I (Source\App\command.h)(0x5683979B) +F (.\Source\App\PLC_reg.c)(0x56092BD4)(-c --cpu Cortex-M3 -g -W -O0 --apcs=interwork -I.\Source -I.\Source\App -I.\Source\App -I C:\Keil_v5\ARM\RV31\INC -I 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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/cntrlgld.crf Binary file host/Obj/cntrlgld.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/cntrlgld.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/cntrlgld.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,15 @@ +.\obj\cntrlgld.o: Source\App\CntrlGLD.c +.\obj\cntrlgld.o: Source\App\commandset.h +.\obj\cntrlgld.o: Source\App\stdint.h +.\obj\cntrlgld.o: Source\App\CntrlGLD.h +.\obj\cntrlgld.o: Source\App\Cyclessync.h +.\obj\cntrlgld.o: Source\App\lpc17xx.h +.\obj\cntrlgld.o: Source\App\core_cm3.h +.\obj\cntrlgld.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\cntrlgld.o: Source\App\core_cmInstr.h +.\obj\cntrlgld.o: Source\App\core_cmFunc.h +.\obj\cntrlgld.o: Source\App\system_LPC17xx.h +.\obj\cntrlgld.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\dspfns.h +.\obj\cntrlgld.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h +.\obj\cntrlgld.o: Source\App\SIP.h +.\obj\cntrlgld.o: Source\App\el_lin.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/cntrlgld.o Binary file host/Obj/cntrlgld.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/command.crf Binary file host/Obj/command.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/command.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/command.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,18 @@ +.\obj\command.o: Source\App\Command.c +.\obj\command.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\command.o: Source\App\lpc17xx.h +.\obj\command.o: Source\App\core_cm3.h +.\obj\command.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\command.o: Source\App\core_cmInstr.h +.\obj\command.o: Source\App\core_cmFunc.h +.\obj\command.o: Source\App\system_LPC17xx.h +.\obj\command.o: Source\App\Command.h +.\obj\command.o: Source\App\el_lin.h +.\obj\command.o: Source\App\vibro.h +.\obj\command.o: Source\App\Global.h +.\obj\command.o: Source\App\uart_m.h +.\obj\command.o: Source\App\CntrlGLD.h +.\obj\command.o: Source\App\QEI.h +.\obj\command.o: Source\App\InputOutput.h +.\obj\command.o: Source\App\stdint.h +.\obj\command.o: Source\App\SPI.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/command.o Binary file host/Obj/command.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/commandset.crf Binary file host/Obj/commandset.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/commandset.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/commandset.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,15 @@ +.\obj\commandset.o: Source\App\commandset.c +.\obj\commandset.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h +.\obj\commandset.o: Source\App\commandset.h +.\obj\commandset.o: Source\App\stdint.h +.\obj\commandset.o: Source\App\el_lin.h +.\obj\commandset.o: Source\App\CyclesSync.h +.\obj\commandset.o: Source\App\lpc17xx.h +.\obj\commandset.o: Source\App\core_cm3.h +.\obj\commandset.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\commandset.o: Source\App\core_cmInstr.h +.\obj\commandset.o: Source\App\core_cmFunc.h +.\obj\commandset.o: Source\App\system_LPC17xx.h +.\obj\commandset.o: Source\App\CntrlGLD.h +.\obj\commandset.o: Source\App\InputOutput.h +.\obj\commandset.o: Source\App\Parameters.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/commandset.o Binary file host/Obj/commandset.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/console.crf Binary file host/Obj/console.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/console.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/console.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,10 @@ +.\obj\console.o: Source\App\console.c +.\obj\console.o: Source\App\console.h +.\obj\console.o: Source\App\lpc17xx.h +.\obj\console.o: Source\App\core_cm3.h +.\obj\console.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\console.o: Source\App\core_cmInstr.h +.\obj\console.o: Source\App\core_cmFunc.h +.\obj\console.o: Source\App\system_LPC17xx.h +.\obj\console.o: Source\App\CyclesSync.h +.\obj\console.o: Source\App\CntrlGLD.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/console.o Binary file host/Obj/console.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/core_cm3.crf Binary file host/Obj/core_cm3.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/core_cm3.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/core_cm3.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,2 @@ +.\obj\core_cm3.o: Source\CMSIS\CM3\CoreSupport\core_cm3.c +.\obj\core_cm3.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/core_cm3.o Binary file host/Obj/core_cm3.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/cyclessync.crf Binary file host/Obj/cyclessync.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/cyclessync.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/cyclessync.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,13 @@ +.\obj\cyclessync.o: Source\App\CyclesSync.c +.\obj\cyclessync.o: Source\App\CyclesSync.h +.\obj\cyclessync.o: Source\App\lpc17xx.h +.\obj\cyclessync.o: Source\App\core_cm3.h +.\obj\cyclessync.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\cyclessync.o: Source\App\core_cmInstr.h +.\obj\cyclessync.o: Source\App\core_cmFunc.h +.\obj\cyclessync.o: Source\App\system_LPC17xx.h +.\obj\cyclessync.o: Source\App\CntrlGLD.h +.\obj\cyclessync.o: Source\App\SIP.h +.\obj\cyclessync.o: Source\App\el_lin.h +.\obj\cyclessync.o: Source\App\inputOutput.h +.\obj\cyclessync.o: Source\App\stdint.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/cyclessync.o Binary file host/Obj/cyclessync.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/dither_reg.crf Binary file host/Obj/dither_reg.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/dither_reg.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/dither_reg.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,17 @@ +.\obj\dither_reg.o: Source\App\Dither_Reg.c +.\obj\dither_reg.o: Source\App\lpc17xx.h +.\obj\dither_reg.o: Source\App\core_cm3.h +.\obj\dither_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\dither_reg.o: Source\App\core_cmInstr.h +.\obj\dither_reg.o: Source\App\core_cmFunc.h +.\obj\dither_reg.o: Source\App\system_LPC17xx.h +.\obj\dither_reg.o: Source\App\mathDSP.h +.\obj\dither_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\dspfns.h +.\obj\dither_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h +.\obj\dither_reg.o: Source\App\InputOutput.h +.\obj\dither_reg.o: Source\App\stdint.h +.\obj\dither_reg.o: Source\App\CyclesSync.h +.\obj\dither_reg.o: Source\App\CntrlGLD.h +.\obj\dither_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\dither_reg.o: Source\App\sip.h +.\obj\dither_reg.o: Source\App\console.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/dither_reg.o Binary file host/Obj/dither_reg.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/el_lin.crf Binary file host/Obj/el_lin.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/el_lin.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/el_lin.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,10 @@ +.\obj\el_lin.o: Source\App\el_lin.c +.\obj\el_lin.o: Source\App\CyclesSync.h +.\obj\el_lin.o: Source\App\lpc17xx.h +.\obj\el_lin.o: Source\App\core_cm3.h +.\obj\el_lin.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\el_lin.o: Source\App\core_cmInstr.h +.\obj\el_lin.o: Source\App\core_cmFunc.h +.\obj\el_lin.o: Source\App\system_LPC17xx.h +.\obj\el_lin.o: Source\App\CntrlGLD.h +.\obj\el_lin.o: Source\App\el_lin.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/el_lin.o Binary file host/Obj/el_lin.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/global.crf Binary file host/Obj/global.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/global.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/global.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,3 @@ +.\obj\global.o: Source\App\Global.c +.\obj\global.o: Source\App\Global.h +.\obj\global.o: Source\App\CntrlGLD.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/global.o Binary file host/Obj/global.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/hfo_reg.crf Binary file host/Obj/hfo_reg.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/hfo_reg.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/hfo_reg.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,8 @@ +.\obj\hfo_reg.o: Source\App\HFO_Reg.c +.\obj\hfo_reg.o: Source\App\mathDSP.h +.\obj\hfo_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\dspfns.h +.\obj\hfo_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\hfo_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h +.\obj\hfo_reg.o: Source\App\InputOutput.h +.\obj\hfo_reg.o: Source\App\stdint.h +.\obj\hfo_reg.o: Source\App\CntrlGLD.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/hfo_reg.o Binary file host/Obj/hfo_reg.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/inputoutput.crf Binary file host/Obj/inputoutput.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/inputoutput.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/inputoutput.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,12 @@ +.\obj\inputoutput.o: Source\App\InputOutput.c +.\obj\inputoutput.o: Source\App\InputOutput.h +.\obj\inputoutput.o: Source\App\stdint.h +.\obj\inputoutput.o: Source\App\CyclesSync.h +.\obj\inputoutput.o: Source\App\lpc17xx.h +.\obj\inputoutput.o: Source\App\core_cm3.h +.\obj\inputoutput.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\inputoutput.o: Source\App\core_cmInstr.h +.\obj\inputoutput.o: Source\App\core_cmFunc.h +.\obj\inputoutput.o: Source\App\system_LPC17xx.h +.\obj\inputoutput.o: Source\App\CntrlGLD.h +.\obj\inputoutput.o: Source\App\el_lin.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/inputoutput.o Binary file host/Obj/inputoutput.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/main.crf Binary file host/Obj/main.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/main.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/main.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,27 @@ +.\obj\main.o: Source\App\main.c +.\obj\main.o: Source\App\SIP.h +.\obj\main.o: Source\App\el_lin.h +.\obj\main.o: Source\App\CyclesSync.h +.\obj\main.o: Source\App\lpc17xx.h +.\obj\main.o: Source\App\core_cm3.h +.\obj\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\main.o: Source\App\core_cmInstr.h +.\obj\main.o: Source\App\core_cmFunc.h +.\obj\main.o: Source\App\system_LPC17xx.h +.\obj\main.o: Source\App\CntrlGLD.h +.\obj\main.o: Source\App\Parameters.h +.\obj\main.o: Source\App\Dither_Reg.h +.\obj\main.o: Source\App\commandset.h +.\obj\main.o: Source\App\stdint.h +.\obj\main.o: Source\App\InputOutput.h +.\obj\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\obj\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\main.o: Source\App\console.h +.\obj\main.o: Source\App\vibro.h +.\obj\main.o: Source\App\QEI.h +.\obj\main.o: Source\App\MTimer.h +.\obj\main.o: Source\App\Global.h +.\obj\main.o: Source\App\SPI.h +.\obj\main.o: Source\App\uart_m.h +.\obj\main.o: Source\App\command.h +.\obj\main.o: Source\App\Global.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/main.o Binary file host/Obj/main.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/mathdsp.crf Binary file host/Obj/mathdsp.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/mathdsp.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/mathdsp.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,7 @@ +.\obj\mathdsp.o: Source\App\mathDSP.c +.\obj\mathdsp.o: Source\App\mathDSP.h +.\obj\mathdsp.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\dspfns.h +.\obj\mathdsp.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\mathdsp.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h +.\obj\mathdsp.o: Source\App\CntrlGLD.h +.\obj\mathdsp.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/mathdsp.o Binary file host/Obj/mathdsp.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/mtimer.crf Binary file host/Obj/mtimer.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/mtimer.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/mtimer.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,15 @@ +.\obj\mtimer.o: Source\App\MTimer.c +.\obj\mtimer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\Time.h +.\obj\mtimer.o: Source\App\lpc17xx.h +.\obj\mtimer.o: Source\App\core_cm3.h +.\obj\mtimer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\mtimer.o: Source\App\core_cmInstr.h +.\obj\mtimer.o: Source\App\core_cmFunc.h +.\obj\mtimer.o: Source\App\system_LPC17xx.h +.\obj\mtimer.o: Source\App\MTimer.h +.\obj\mtimer.o: Source\App\vibro.h +.\obj\mtimer.o: Source\App\QEI.h +.\obj\mtimer.o: Source\App\Global.h +.\obj\mtimer.o: Source\App\SPI.h +.\obj\mtimer.o: Source\App\InputOutput.h +.\obj\mtimer.o: Source\App\stdint.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/mtimer.o Binary file host/Obj/mtimer.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/parameters.crf Binary file host/Obj/parameters.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/parameters.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/parameters.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,10 @@ +.\obj\parameters.o: Source\App\Parameters.c +.\obj\parameters.o: Source\App\CntrlGLD.h +.\obj\parameters.o: Source\App\lpc17xx.h +.\obj\parameters.o: Source\App\core_cm3.h +.\obj\parameters.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\parameters.o: Source\App\core_cmInstr.h +.\obj\parameters.o: Source\App\core_cmFunc.h +.\obj\parameters.o: Source\App\system_LPC17xx.h +.\obj\parameters.o: Source\App\Parameters.h +.\obj\parameters.o: Source\App\el_lin.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/parameters.o Binary file host/Obj/parameters.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/plc_reg.crf Binary file host/Obj/plc_reg.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/plc_reg.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/plc_reg.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,17 @@ +.\obj\plc_reg.o: Source\App\PLC_reg.c +.\obj\plc_reg.o: Source\App\mathDSP.h +.\obj\plc_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\dspfns.h +.\obj\plc_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\plc_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h +.\obj\plc_reg.o: Source\App\CyclesSync.h +.\obj\plc_reg.o: Source\App\lpc17xx.h +.\obj\plc_reg.o: Source\App\core_cm3.h +.\obj\plc_reg.o: Source\App\core_cmInstr.h +.\obj\plc_reg.o: Source\App\core_cmFunc.h +.\obj\plc_reg.o: Source\App\system_LPC17xx.h +.\obj\plc_reg.o: Source\App\CntrlGLD.h +.\obj\plc_reg.o: Source\App\ThermoCalc.h +.\obj\plc_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\plc_reg.o: Source\App\InputOutput.h +.\obj\plc_reg.o: Source\App\stdint.h +.\obj\plc_reg.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/plc_reg.o Binary file host/Obj/plc_reg.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/qei.crf Binary file host/Obj/qei.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/qei.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/qei.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,10 @@ +.\obj\qei.o: Source\App\QEI.c +.\obj\qei.o: Source\App\lpc17xx.h +.\obj\qei.o: Source\App\core_cm3.h +.\obj\qei.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\qei.o: Source\App\core_cmInstr.h +.\obj\qei.o: Source\App\core_cmFunc.h +.\obj\qei.o: Source\App\system_LPC17xx.h +.\obj\qei.o: Source\App\QEI.h +.\obj\qei.o: Source\App\vibro.h +.\obj\qei.o: Source\App\MTimer.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/qei.o Binary file host/Obj/qei.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/sip.crf Binary file host/Obj/sip.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/sip.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/sip.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,18 @@ +.\obj\sip.o: Source\App\SIP.c +.\obj\sip.o: Source\App\mathDSP.h +.\obj\sip.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\dspfns.h +.\obj\sip.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\sip.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h +.\obj\sip.o: Source\App\SIP.h +.\obj\sip.o: Source\App\CyclesSync.h +.\obj\sip.o: Source\App\lpc17xx.h +.\obj\sip.o: Source\App\core_cm3.h +.\obj\sip.o: Source\App\core_cmInstr.h +.\obj\sip.o: Source\App\core_cmFunc.h +.\obj\sip.o: Source\App\system_LPC17xx.h +.\obj\sip.o: Source\App\CntrlGLD.h +.\obj\sip.o: Source\App\InputOutput.h +.\obj\sip.o: Source\App\stdint.h +.\obj\sip.o: Source\App\ThermoCalc.h +.\obj\sip.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\sip.o: Source\App\el_lin.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/sip.o Binary file host/Obj/sip.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/spi.crf Binary file host/Obj/spi.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/spi.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/spi.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,13 @@ +.\obj\spi.o: Source\App\SPI.c +.\obj\spi.o: Source\App\Global.h +.\obj\spi.o: Source\App\SPI.h +.\obj\spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\spi.o: Source\App\lpc17xx.h +.\obj\spi.o: Source\App\core_cm3.h +.\obj\spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\spi.o: Source\App\core_cmInstr.h +.\obj\spi.o: Source\App\core_cmFunc.h +.\obj\spi.o: Source\App\system_LPC17xx.h +.\obj\spi.o: Source\App\InputOutput.h +.\obj\spi.o: Source\App\stdint.h +.\obj\spi.o: Source\App\MTimer.h
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/spi.o Binary file host/Obj/spi.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/startup_lpc17xx.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/startup_lpc17xx.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1 @@ +.\obj\startup_lpc17xx.o: Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm\startup_LPC17xx.s
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/startup_lpc17xx.o Binary file host/Obj/startup_lpc17xx.o has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/system_lpc17xx.crf Binary file host/Obj/system_lpc17xx.crf has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/system_lpc17xx.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/system_lpc17xx.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,7 @@ +.\obj\system_lpc17xx.o: Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.c +.\obj\system_lpc17xx.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\system_lpc17xx.o: Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\LPC17xx.h +.\obj\system_lpc17xx.o: .\Source\App\core_cm3.h +.\obj\system_lpc17xx.o: .\Source\App\core_cmInstr.h +.\obj\system_lpc17xx.o: .\Source\App\core_cmFunc.h +.\obj\system_lpc17xx.o: Source\CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.h
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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/thermocalc.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/thermocalc.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,16 @@ +.\obj\thermocalc.o: Source\App\ThermoCalc.c +.\obj\thermocalc.o: Source\App\ThermoCalc.h +.\obj\thermocalc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\thermocalc.o: Source\App\CyclesSync.h +.\obj\thermocalc.o: Source\App\lpc17xx.h +.\obj\thermocalc.o: Source\App\core_cm3.h +.\obj\thermocalc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\thermocalc.o: Source\App\core_cmInstr.h +.\obj\thermocalc.o: Source\App\core_cmFunc.h +.\obj\thermocalc.o: Source\App\system_LPC17xx.h +.\obj\thermocalc.o: Source\App\CntrlGLD.h +.\obj\thermocalc.o: Source\App\InputOutput.h +.\obj\thermocalc.o: Source\App\stdint.h +.\obj\thermocalc.o: Source\App\mathDSp.h +.\obj\thermocalc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\dspfns.h +.\obj\thermocalc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h
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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/timer.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/timer.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,8 @@ +.\obj\timer.o: Source\App\Timer.c +.\obj\timer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\Time.h +.\obj\timer.o: Source\App\lpc17xx.h +.\obj\timer.o: Source\App\core_cm3.h +.\obj\timer.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\timer.o: Source\App\core_cmInstr.h +.\obj\timer.o: Source\App\core_cmFunc.h +.\obj\timer.o: Source\App\system_LPC17xx.h
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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/uart_m.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/uart_m.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,8 @@ +.\obj\uart_m.o: Source\App\uart_m.c +.\obj\uart_m.o: Source\App\lpc17xx.h +.\obj\uart_m.o: Source\App\core_cm3.h +.\obj\uart_m.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\uart_m.o: Source\App\core_cmInstr.h +.\obj\uart_m.o: Source\App\core_cmFunc.h +.\obj\uart_m.o: Source\App\system_LPC17xx.h +.\obj\uart_m.o: Source\App\uart_m.h
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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Obj/vibro.d --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Obj/vibro.d Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,20 @@ +.\obj\vibro.o: Source\App\vibro.c +.\obj\vibro.o: Source\App\vibro.h +.\obj\vibro.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\obj\vibro.o: Source\App\lpc17xx.h +.\obj\vibro.o: Source\App\core_cm3.h +.\obj\vibro.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\obj\vibro.o: Source\App\core_cmInstr.h +.\obj\vibro.o: Source\App\core_cmFunc.h +.\obj\vibro.o: Source\App\system_LPC17xx.h +.\obj\vibro.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\ctime +.\obj\vibro.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\time.h +.\obj\vibro.o: Source\App\InputOutput.h +.\obj\vibro.o: Source\App\stdint.h +.\obj\vibro.o: Source\App\Parameters.h +.\obj\vibro.o: Source\App\CntrlGLD.h +.\obj\vibro.o: Source\App\CyclesSync.h +.\obj\vibro.o: Source\App\SIP.h +.\obj\vibro.o: Source\App\QEI.h +.\obj\vibro.o: Source\App\Global.h +.\obj\vibro.o: Source\App\MTimer.h
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diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CntrlGLD.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CntrlGLD.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,265 @@ +#include "commandset.h" +#include "CntrlGLD.h" +#include "Cyclessync.h" +#include "dspfns.h" +#include "SIP.h" +#include "el_lin.h" + +#define COMMAND_DEBUG + +uint32_t SRgR; //r. ñèñòåìíûé ðåãèñòð ðåæèìà ïëàòû ADSP + +uint32_t RgConA; //r. îñíîâíîé ðåãèñòð óïðàâëåíèÿ óñòðîéñòâà +uint32_t RgConB; //r. äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ +//uint32_t Copy_e5_RgR; //r. êîïèÿ ðåãèñòðà ðåæèìà ïëàòû E5 +//uint32_t Copy_e5_RgRA; //r. êîïèÿ äîïîëíèòåëüíîãî ðåãèñòðà ðåæèìà E5 + +uint32_t Valid_Data; //r. áàéò-ïðèçíàê äîñòîâåðíûõ äàííûõ, íàêàïëèâàþùèé îøèáêè îò çàïðîñà äî çàïðîñà + +TDEVICE_BLK Device_blk; //e. union for device constants +uint32_t ser_num; //e. device serial number + +int Device_Mode = DM_INT_10KHZ_LATCH; //r. ðåæèì ðàáîòû ïðèáîðà (âíóòð.çàùåëêà, çíàêîâûé ìåàíäð èëè âíåøíÿÿ çàùåëêà) + +void Sts_Pulse(void); +void Sts_Pause(void); +void Sts_Polling(void); + + //r. òàáëèöà ñîñòîÿíèé ïðîöåäóðû çàïóñêà ïðèáîðà +void (* Tab_Gld_Start[3])(void) = {Sts_Pulse, Sts_Pause, Sts_Polling}; + //r. òàáëèöà ñîñòîÿíèé ïðîöåäóðû ïîäæèãà ëàçåðà +void (* Tab_Gld_Pulse[1])(void) = {Sts_Pulse}; + + //e. stack of states of the procedure of starting //r. ñòåê ïàðàìåòðîâ ñîñòîÿíèé ïðîöåäóðû çàïóñêà +uint32_t Stk_Gld_Start[3] = {LIGHT_UP_PULSE_WDTH, LIGHT_UP_PAUSE, LIGHT_UP_POLLING}; + +uint32_t gyro_Sts = 0; //r. ðåãèñòð ñîñòîÿíèÿ ïðèáîðà +uint32_t start_Rq = 1; //r. çàïðîñ íà çàïóñê ïðèáîðà +uint32_t start_Go = 0; //r. ïðîöåäóðà çàïóñêà àêòèâíà +uint32_t stop_Rq = 0; //r. çàïðîñ íà îñòàíîâ ïðèáîðà +uint32_t pulse_Rq = 0; //r. çàïðîñ íà ïîäæèã ëàçåðà +uint32_t pulse_Go = 0; //r. ïðîöåññ ïîäæèãà àêòèâåí + +uint32_t state_index; //r. èíäåêñ ñîñòîÿíèÿ ïðîöåäóðû (ñòàðòà) +uint32_t sts_work; //r. 1 - òåêóùåå ñîñòîÿíèå - â ðàáî÷åé ôàçå, 0 - èíèöèàëèçàöèè +uint32_t sts_time; //r. ñ÷åò÷èê âðåìåíè òåêóùåãî ñîñòîÿíèÿ +uint32_t attempt_Str; //r. ñ÷åò÷èê ïîïûòîê çàïóñêà ïðèáîðà + + +uint32_t BIT_number; +uint32_t Is_BIT = 0; + +void GLD_Stop(void) //e.---------- procedure of GLD stopping -------------------------------------- //r.---------- ïðîöåäóðà îñòàíîâà ÃËÄ -------------------------------------- +{ + if (!stop_Rq) //r. ïðîâåðèòü çàïðîñ íà âûêëþ÷åíèå ïðèáîðà + { + return; //r. åñëè íåò, âîçâðàò + } + + //r. ñáðîñèòü ôëàãè + start_Rq = 0; //r. çàïðîñà âêëþ÷åíèÿ, + start_Go = 0; //r. àêòèâíîñòè ïðîöåññà çàïóñêà ïðèáîðà, + stop_Rq = 0; //r. çàïðîñà îñòàíîâà + open_all_loops(); //r. âûêëþ÷èòü âñå êîíòóðà ðåãóëèðîâàíèÿ + + gyro_Sts = 0; //r. ñáðîñ ðåãèñòðà ñîñòîÿíèÿ àïïàðàòóðû ÃËÄ + + //r. óñòàíîâêà çíà÷åíèé ïîêîÿ âûõîäíûõ ïàðàìåòðîâ ðåãóëÿòîðîâ +#if !defined COMMAND_DEBUG + disable_DACs(); +#endif +} // GLD_Stop + +void GLD_Status(void) //r.---------- äîïóñêîâûé êîíòðîëü ïàðàìåòðîâ ÃËÄ -------------------------- +{ + static uint32_t Device_Mode_Old = DM_INT_10KHZ_LATCH/*DM_EXT_LATCH_DELTA_SF_PULSE*/; + + if ( loop_is_closed(GLD_ON) == 0 ) + { + open_all_loops(); + GLD_Stop(); + } + if (Device_Mode_Old != Device_Mode) //deviñe mode has been changed + { + if (SwitchMode()) //e. mode is changed successful + { + Device_Mode_Old = Device_Mode; //e. save current mode name + if (Device_Mode_Old == DM_INT_10KHZ_LATCH) + trm_ena = 1; //e. enable answer + } + } +} // GLD_Status + +void Sts_Pause(void) //r.------- ïðîöåäóðà ñîñòîÿíèÿ ïàóçû -------------------------------------- +{ + if (sts_work) //r. ñîñòîÿíèå â àêòèâíîé ôàçå? + { + sts_time--; //r. äåêðåìåíò ñ÷åò÷èêà âðåìåíè ñîñòîÿíèÿ + if (sts_time > 0) + { + return; //r. ïðîäîëæàòü ðàáîòó, ïîêà ñ÷åò÷èê ïîëîæèòåëåí + } + //r. âðåìÿ ñîñòîÿíèÿ êîí÷èëîñü + sts_work = 0; //r. ñáðîñèòü ôëàã àêòèâíîñòè + state_index++; //r. ïåðåäâèíóòü óêàçàòåëü íà ñëåäóþùåå ñîñòîÿíèå + } + else + { + sts_time = Stk_Gld_Start[state_index]; //r. âðåìÿ äàííîãî ñîñòîÿíèÿ + sts_work = 1; //r. óñòàíîâèòü ôëàã àêòèâíîé ôàçû + } +} // Sts_Pause + +void Sts_Pulse() //r. ------- ïðîöåäóðà ñîñòîÿíèÿ èìïóëüñà ïîäæèãà -------------------------- +{ + if (sts_work) //r. ñîñòîÿíèå â àêòèâíîé ôàçå? + { + sts_time--; //r. äåêðåìåíò ñ÷åò÷èêà âðåìåíè ñîñòîÿíèÿ + if (sts_time > 0) + { + return; //r. ïðîäîëæàòü ðàáîòó, ïîêà ñ÷åò÷èê ïîëîæèòåëåí + } + //r. âðåìÿ ñîñòîÿíèÿ êîí÷èëîñü + sts_work = 0; //r. ñáðîñèòü ôëàã àêòèâíîñòè + state_index++; //r. ïåðåäâèíóòü óêàçàòåëü íà ñëåäóþùåå ñîñòîÿíèå + + Set_LightUp; //r. ñíÿòü ñèãíàë ïîäæèãà ëàçåðà + + } + else + { + sts_time = Stk_Gld_Start[state_index]; //r. âðåìÿ äàííîãî ñîñòîÿíèÿ + sts_work = 1; //r. óñòàíîâèòü ôëàã àêòèâíîé ôàçû + + Reset_LightUp; //r. àêòèâèðîâàòü ñèãíàë ïîäæèãà ëàçåðà + + } +} // Sts_Pulse + +void Sts_Polling(void) //r.========== ïðîöåäóðà ñîñòîÿíèÿ èçìåðåíèÿ è ïðèíÿòèÿ ðåøåíèÿ î çàïóñêå +{ + static int32_t Sum_F_ras = 0; //r. èíòåãðàëüíàÿ ñóììà ðàñùåïëåíèÿ äëÿ ïðîöåäóðû ñòàðòà + + if (sts_work) //r. ñîñòîÿíèå â àêòèâíîé ôàçå? + { + if (Dif_Curr_Vib >0) + Sum_F_ras = L_add(Sum_F_ras, Dif_Curr_Vib); + else + Sum_F_ras = L_sub(Sum_F_ras, Dif_Curr_Vib); + +//r. íåò, ïðîïóñòèòü íàêîïëåíèå ñóììû ðàñùåïëåíèÿ + sts_time--; //r. äåêðåìåíò ñ÷åò÷èêà âðåìåíè ñîñòîÿíèÿ + if (sts_time > 0) + { + return; //r. ïðîäîëæàòü ðàáîòó, ïîêà ñ÷åò÷èê ïîëîæèòåëåí + } + //r. âðåìÿ ñîñòîÿíèÿ êîí÷èëîñü + sts_work = 0; //r. ñáðîñèòü ôëàã àêòèâíîñòè + state_index++; //r. ïåðåäâèíóòü óêàçàòåëü íà ñëåäóþùåå ñîñòîÿíèå + //r. ïðîâåðèòü íàëè÷èå ãåíåðàöèè + if ( Sum_F_ras >= F_RAS_MIN) //e. //r. F_RAS_MIN = 10000 ??? ÷òî ýòî çà åäèíèöû??? + { + gyro_Sts |= LASER_ON; //r. èíà÷å ñòàðò ñîñòîÿëñÿ, îòìåòèòü â ðåãèñòðå ñîñòîÿíèÿ + return; //r. ïðèáîðà è çàâåðøàòü ïðîöåññ + } + //r. åñëè îíà ìåíüøå, ãåíåðàöèè íåò + attempt_Str--; //r. äåêðåìåíò ñ÷åò÷èêà ïîïûòîê çàïóñêà ëàçåðà + if (attempt_Str <= 0) + { + return; //r. åñëè ïîïûòêè çàêîí÷åíû, çàâåðøèòü ïðîöåññ + } + //r. èíà÷å óñòàíîâèòü óêàçàòåëü ñîñòîÿíèé íà + state_index = 0; //r. íà÷àëî ïðîöåññà çàïóñêà äëÿ ïîâòîðíîé ïîïûòêè + } + else + { + sts_time = Stk_Gld_Start[state_index]; //r. âðåìÿ äàííîãî ñîñòîÿíèÿ + sts_work = 1; //r. óñòàíîâèòü ôëàã àêòèâíîé ôàçû + Sum_F_ras = 0; //r. ïðåäñáðîñ èíòåãðàëüíîé ñóììû ðàñùåïëåíèÿ + } + +} // Sts_Polling + + +//r.---------- ïðîöåññ çàïóñêà ïðèáîðà ------------------------------------- +void GLD_Start(void) +{ + if (!start_Rq) //r. ïðîâåðèòü ñîñòîÿíèå çàïðîñà íà çàïóñê ïðèáîðà + { + return; //r. çàïðîñà íåò, âîçâðàò + } + + if (!start_Go) //r. ïðîöåññ çàïóñêà åùå íå áûë àêòèâåí? + { + //r. ýòî íà÷àëî çàïóñêà + attempt_Str = N_START_MAX; //r. óñòàíîâèòü ìàêñèìàëüíîå ÷èñëî ïîïûòîê çàïóñêà + //r. ðàçîìêíóòü êîíòóðà ðåãóëÿòîðîâ + //open_loop(VB_FREQ_ON | VB_TAU_ON | WP_REG_ON | HF_REG_ON); // 0xff95 + //close_all_loops(); + + sts_work = 0; //r. ñáðîñèòü ôëàã àêòèâíîé ôàçû ñîñòîÿíèÿ + state_index= 0; //r. óñòàíîâèòü óêàçàòåëü ñîñòîÿíèé â íà÷àëüíîå ïîëîæåíèå + start_Go = 1; //r. ïðîöåññ ñòàðòà íà÷àëñÿ + } + + ( *Tab_Gld_Start[state_index] )(); //r. âûçîâ ïðîöåäóðû ñîñòîÿíèÿ ïî íîìåðó â ìàññèâå + + if (sts_work) //r. òåêóùåå ñîñòîÿíèå îêîí÷åíî? + { + return; //r. ïðîäîëæàòü îæèäàíèå + } + //r. ñîñòîÿíèå çàêîí÷èëîñü ïðîâåðèòü óêàçàòåëü ñîñòîÿíèé + if ( state_index >= 3 ) + { + //r. îêîí÷àíèå ïðîöåññà + //r. ñáðîñèòü ôëàãè + start_Rq = 0; //r. çàïðîñà + start_Go = 0; //r. è àêòèâíîñòè ïðîöåññà +#if !defined COMMAND_DEBUG + Out_G_photo(Device_blk.Str.Gain_Ph_A, Device_blk.Str.Gain_Ph_B); //r. ïîâòîðíî èíèöèàëèçèðîâàòü êîýô-òû ïåðåäà÷è ôîòîïðèåìíèêîâ +#endif + // close_all_loops(); + + } + +} // GLD_Start + +void GLD_Pulse(void) //r.---------- ïðîöåññ ïîäæèãà ëàçåðà -------------------------------------- +{ + if (!pulse_Rq) //r. ïðîâåðèòü ñîñòîÿíèå çàïðîñà íà ïîäæèã ëàçåðà + { + return; //r. çàïðîñà íåò, âîçâðàò + } + + if (!pulse_Go) //r. ïðîöåññ ïîäæèãà åùå íå áûë àêòèâåí? + { + sts_work = 0; //r. ñáðîñèòü ôëàã àêòèâíîé ôàçû ñîñòîÿíèÿ + state_index = 0; //r. óñòàíîâèòü óêàçàòåëü ñîñòîÿíèé â íà÷àëüíîå ïîëîæåíèå + pulse_Go = 1; //r. ïðîöåññ ñòàðòà íà÷àëñÿ + } + + ( *Tab_Gld_Pulse[state_index] )(); //r. âûçîâ ïðîöåäóðû ñîñòîÿíèÿ ïî íîìåðó â ìàññèâå + + if (sts_work) //r. òåêóùåå ñîñòîÿíèå îêîí÷åíî? + { + return; //r. ïðîäîëæàòü îæèäàíèå + } + + if ( state_index >= 1 ) + { + //r. ñáðîñèòü ôëàãè + pulse_Rq = 0; //r. çàïðîñà + pulse_Go = 0; //r. è àêòèâíîñòè ïðîöåññà + } + +} // GLD_Pulse + +void contrl_GLD(void) //r.========== ïðîöåäóðà óïðàâëåíèÿ ïðèáîðîì =============================== +{ + GLD_Start(); //r. çàïóñòèòü ïðèáîð, åñëè åñòü çàïðîñ + GLD_Status(); //r. ïðîâåðêà ñîñòîÿíèÿ ïðèáîðà + GLD_Stop(); //r. îñòàíîâèòü ïðèáîð, åñëè íåîáõîäèìî + GLD_Pulse(); //r. ãåíåðàöèÿ èìïóëüñà ïîäæèãà ïðè íàëè÷èè çàïðîñà + GLD_Output(); //r. ðåæèìû âûäà÷è äàííûõ èç ãèðîñêîïà +} // contrl_GLD +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CntrlGLD.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CntrlGLD.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,328 @@ + +#ifndef DEVICE +#define DEVICE + +//e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +typedef enum _TERMO_MODE //e. thermocompensation modes //r. ðåæèìû ðàáîòû òåðìîêîìïåíñàöèè +{ + TERMO_OFF, //e. thermocompensation is switched off //r. òåðìîêîìïåíñàöèÿ âûêëþ÷åíà + TERMO_ON, //e. thermocompensation is switched on //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà + TERMO_ON_NUMB_OFF, //e. thermocompensation is switched on, number resets (debug mode) //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_STATIC_ONLY, //e. only static thermocompensation is switched on //r. âêëþ÷åíà òîëüêî ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_DYNAMIC_ONLY, //e. only dynamic thermocompensation is switched on //r. âêëþ÷åíà òîëüêî äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_STATIC_ONLY_NUMB_OFF, //e. static thermocompensation is switched on, number resets (debug mode) //r. ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_DYNAMIC_ONLY_NUMB_OFF //e. dynamic thermocompensation is switched on, number resets (debug mode) //r. äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) +} TERMO_MODE; + +typedef enum _WATCH_MODE //e. variants of control points for scope //r. âàðèàíòû êîíòðîëüíûõ òî÷åê äëÿ îñöèëëîãðàôà +{ + VB_DELAY_MEANDER, //e. the delayed on the VB_phs meander //r. çàäåðæàííûé ìåàíäð íà âåëè÷èíó VB_phs + VB_PHASE_DETECTOR, //e. output of the PD of the dither drive //r. âûõîä ôàçîâîãî äåòåêòîðà âèþðîïðèâîäà + VB_PHASE_DETECTOR_1_SEC, //e. output of integral of the PD of the dither drive for 1 Sec //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 1 ñåê + VB_INTEGRATOR_40T, //e. output of integral of the PD of the dither drive for 40 periods //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 40 ïåðèîäîâ + WP_PHASE_DETECTOR //e. output of the PD of the CPLC regulator //r. âûõîä ôàçîâîãî äåòåêòîðà êîíòóðà ÑÐÏ +} WATCH_MODE; + +//e. ===== device operation modes ================================================================ //r. ===== ðåæèìû ðàáîòû ïðèáîðà ================================================================ +#define DM_INT_10KHZ_LATCH 1 //e. mode of internal latch 10 kHz //r. ðåæèì âíóòðåííåé çàùåëêè 10 êÃö +#define DM_INT_LATCH_DELTA_PS 2 +#define DM_INT_LATCH_DELTA_BINS 3 +#define DM_EXT_LATCH_DELTA_PS_PULSE 4 //e. mode of external latch with output of the Delta_PS command by pulse //r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_PS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_BINS_PULSE 6 //e. mode of external latch with output of the Delta_BINS command by pulse//r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_BINS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_SF_PULSE 7 //e. mode of Delta Scale factor //r. ðåæèì Delta_SF command + + //e. *** the BLOCK of VARIABLES, LOADED from FLASH-memory ********************** //r. *** ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè ********************** + //e. Address (parameter number in the block = 0..255 ) //r. Àäðåñ (Íîìåð ïàðàìåòðà â áëîêå = 0..255) +typedef union + { + int Array[171]; + struct + { // Device_blk + int My_Addres; //e. 0 - device own address //r.0 - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HFO regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + int HF_ref; //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + int HF_scl; //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int HF_min; //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + int HF_max; //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + + //e. =============== parameters of the regulator of the DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + int RI_ref; //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + int RI_scl; //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + int WP_ref; //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + int WP_scl; //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int WP_mdy; //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + int WP_rup; //e. 10 - upper value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + int WP_rdw; //e. 11 - lower value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + int VB_phs; //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + int VB_scl; //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà +unsigned int VB_N; //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ +unsigned int VB_Nmin; //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà +unsigned int VB_Nmax; //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + + int VB_Fdf_Hi; //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) +unsigned int VB_Fdf_Lo; //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + + int VB_Fsc; //e. 19 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmin; //e. 20 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmax; //e. 21 - maximum of the output value of the regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau +unsigned int VB_tau; //e. 22 - pulse width of the dither drive (without noise)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + int VBN_Tzd; //e. 23 - adjusted noise period //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ + int VBN_Ran; //e. 24 - range of the random component of noise //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + int VBN_k; //e. 25 - adjusted noise constant //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + int PI_Fsc; //_ //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + int PI_Fb0; //_ //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + int PI_scl; //_ //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + int PI_bia; //_ //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + int PI_a0; //_ // 30 + int PI_a1; //_ // 31 + int PI_a2; //_ // 32 + int PI_a3; //_ // 33 + int PI_a4; //_ // 34 + int PI_a5; //_ // 35 + int PI_a6; //_ // 36 + int PI_b1; //_ // 37 + int PI_b2; //_ // 38 + int PI_b3; //_ // 39 + int PI_b4; //_ // 40 + int PI_b5; //_ // 41 + int PI_b6; //_ // 42 + + //e. =============== parameters of normalization of the temperature sensors ============= //r. =============== ïàðàìåòðû íîðìèðîâêè äàò÷èêîâ òåìïåðàòóðû ============= + + int Tmp_bias[6]; //_ //e. 43 - an array of shifts of the 0..5 temperature sensors //r. 43 - ìàññèâ ñäâèãîâ òåìïåðàòóðíûõ äàò÷èêîâ 0..5 + int Tmp_scal[6]; //_ //e. 49 - an array of the scale coefficients of temperature sensors//r. 49 - ìàññèâ ìàñøòàáíûõ ê-òîâ òåìïåðàòóðíûõ äàò÷èêîâ + int WP_reset; //e. 55 - initial position of the CPLC regulator (after reset) //r. 55 - èñõîäíîå ïîëîæåíèå ðåãóëÿòîðà ÑÐÏ (ïîñëå ñáðîñà) + + //e. ================ gain factor of photodetector channels =========== //r. ================ ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== +unsigned int Gain_Ph_A; //e. 56 - initial gain factor of the A channel of photodetector //r. 56 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà À ôîòîïðèåìíèêà +unsigned int Gain_Ph_B; //e. 57 - initial gain factor of the B channel of photodetector //r. 57 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà B ôîòîïðèåìíèêà + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ (ãàëî÷êà â íàñòîðîå÷íîé ïðîãðàììå) + int Header_Word; //e. 58 - flash sector validity header //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + int LoadFlash_enable; //e. 59 - source loading flag: 1 - load from the flash //r. 59 - ïðèçíàê èñòî÷íèêà çàãðóçêè: 1 - ãðóçèòüñÿ èç flesh + //e. 0 - load default parameters (factory) //r. 0 - ãðóçèòü ïàðàìåòðû ïî óìîë÷àíèþ (çàâîäñêèå) +unsigned int Device_SerialNumber; //e. 60 - serial number of the device //r. 60 - ñåðèéíûé íîìåð ïðèáîðà + int Reserved0; //e. 61 - not used + TERMO_MODE TermoMode; //e 62 - device operation mode (with thermocompenstion, without it, debug )//r. 62 - ðåæèì ðàáîòû ïðèáîðà (ñ òåðìîêîìïåíñàöèåé, áåç íåå èëè îòëàäêà) +//e. addition for the piecewise-linear termocorrection //r. äîáàâëåíèå äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîððåêöèè + int TemperInt[TERMO_FUNC_SIZE]; //e. 63 + float TermoFunc[TERMO_FUNC_SIZE]; //e. 77 + int WP_reset2; //e. 91 - voltages of CPLC regulator reset at cooling //r. xx - íàïðÿæåíèÿ îáíóëåíèÿ êîíòóðà ÑÐÏ ïðè îõëàæäåíèè + //e. parameters setting termocompensation parameters in dynamics (at heating and cooling) //r. ïàðàìåòðû, çàäàþùèå ïàðàìåòðû òåðìîêîìïåíñàöèè â äèíàìèêå (ïðè íàãðåâå è îõëàæäåíèè) + float Reserved1; //e. 92 - not used + float Reserved2; //e. 93 - not used + int K_vb_tu; //e. 94 - slope of dependence of the VB_N division factor from temperature (as though Hz/degree, but in relative units ) //r. êðóòèçíà çàâèñèìîñòè êîýôôèöèåíòà äåëåíèÿ VB_N îò òåìïåðàòóðû (êàê áû Ãö/ãðàäóñ, íî â ó.å.) + int TemperNormal; //e. 95 -temperature for which the VB_N division factor of the dither drive is set //r. òåìïåðàòóðà, äëÿ êîòîðîé çàäàí êîýôôèöèåíò äåëåíèÿ âèáðîïðèâîäà VB_N + int K_WP_rst_heating; //r. 96 - êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè íàãðåâàíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int K_WP_rst_cooling; //e. 97 - slope of dependence of a reset voltage at cooling from temperature (as though Volt/degree, but in relative units of DAC and temperature sensors) //r. êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè îõëàæäåíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int WP_transition_step; //e. 98 - step of change of a heater voltage at resetting //r. øàã èçìåíåíèÿ íàïðÿæåíèÿ íàãðåâàòåëÿ ïðè âûïîëíåíèè îáíóëåíèÿ + int Reserved3; // e. 99 -not used + int HF_scl_2; //r. 100 - êîýôôèöèåíò ïåðåäà÷è (1.15) êîíòóðà ÃÂ× ïðè îáíóëåíèè + int TemperIntDyn[TERMO_FUNC_SIZE]; //e. 114 - + float ThermoHeatDelta[TERMO_FUNC_SIZE]; //e. 128 - + int DeltaTempRecalc; //r. 129 - òåìïåðàòóðíûé èíòåðâàë ïåðåñ÷åòà äèíàìè÷. êîìïåíñàöèè (â ó.å.) //e. temperature delta for dynamic thermocompensation recalculation(in relative units) + int TemperCoolIntDyn[TERMO_FUNC_SIZE]; // e. 143 - + float ThermoCoolDelta[TERMO_FUNC_SIZE]; //e. 157 - + } Str; +} TDEVICE_BLK; + + + + + + + + + + + +//e. ************ end of the BLOCK of VARIABLES, LOADED from FLASH-memory ************ //r. ************ êîíåö áëîêà çàãðóæàåìûõ èç ôëýø-ïàìÿòè ïàðàìåòðîâ ÃËÄ ************ +extern TDEVICE_BLK Device_blk; //e. the BLOCK of VARIABLES, LOADED from FLASH-memory //r. ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè + +extern int Device_Mode; +extern unsigned Valid_Data; + +extern unsigned ser_num; + +extern int VB_Nmin0; //r. ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal +extern int VB_Nmax0; //r. ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal + +extern unsigned BIT_number; +extern unsigned Is_BIT; + +extern unsigned start_Rq; //r. çàïðîñ íà çàïóñê ïðèáîðà +extern unsigned stop_Rq; //r. çàïðîñ íà îñòàíîâ ïðèáîðà +extern unsigned pulse_Rq; //r. çàïðîñ íà ïîäæèã ëàçåðà + + //r. *** Ïðèáîðíûå ïàðàìåòðû ïî óìîë÷àíèþ *** +#define DEVICE_SN 1 //r. ñåðèéíûé íîìåð ïðèáîðà = 01 +#define My_Addres_const 0 //r. - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //r. ====== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + + #define HF_REF_CONST 15080 //r. 1 - çíà÷åíèå îïîðû + #define HF_SCL_CONST 1 //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define HF_MIN_CONST -32668 //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + #define HF_MAX_CONST -17379 //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + #define HFO_SHIFT 16 //r. ÷èñëî ðàçðÿäîâ äðîáíîé ÷àñòè â 32-õáèòîâîé ïåðåìåííîé hf_reg32 + + //r. ====== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + + #define WP_REF_CONST 5 //r. 7 - çíà÷åíèå îïîðû + #define WP_SCL_CONST 5 //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define WP_MDY_CONST 30 //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + #define WP_RUP_CONST 31936 //r. 10 - íèæíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + #define WP_RDW_CONST 11801 //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + +//r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + + #define VB_PHS_CONST 4 //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + #define VB_SCL_CONST 1024 //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà + #define T_VIB_START 16600 //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ + //r. _VB_N íà÷àëüíûé ïåðèîä êîëåáàíèé âèáðîïðèâîäà (406Hz-18916, 17067 - 450Hz) + #define T_VIB_DELTA 1000 //r. äèàïàçîí èçìåíåíèÿ ïåðèîäà êîëåáàíèé âèáðîïðèâîäà (~ +/- 10 Hz) + + #define VB_NMIN_CONST 12080 //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_NMAX_CONST 64000 //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_FDF_HI_CONST 3 //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) + #define VB_FDF_LO_CONST 0 //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + #define VB_FSC_CONST -2000 //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ + #define VB_TMIN_CONST 100 //r. 20 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define VB_TMAX_CONST 10022 //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define L_VIB_START 5120 //r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + //r. _VB_tau íà÷àëüíàÿ äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà + + #define VBN_TZD_CONST 500 //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + #define VBN_RAN_CONST 400 //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + #define VBN_K_CONST 7000 //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + + //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + #define RI_REF_CONST 25600 //r. 5 - çíà÷åíèå îïîðû + #define RI_SCL_CONST 0 //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + + //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + #define PI_FSC_CONST 128 //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + #define PI_FB0_CONST 0 //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + #define PI_SCL_CONST 256 //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + #define PI_BIA_CONST 0 //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + #define PI_A0_CONST 0 // 30 + #define PI_A1_CONST 0 // 31 + #define PI_A2_CONST 0 // 32 + #define PI_A3_CONST 0 // 33 + #define PI_A4_CONST 0 // 34 + #define PI_A5_CONST 0 // 35 + #define PI_A6_CONST 0 // 36 + #define PI_B1_CONST 0 // 37 + #define PI_B2_CONST 0 // 38 + #define PI_B3_CONST 0 // 39 + #define PI_B4_CONST 0 // 40 + #define PI_B5_CONST 0 // 41 + #define PI_B6_CONST 0 // 42 + + #define TMP_SCALE 0x4000 // 43 - 54 Tmp_bias[6]; Tmp_scal[6] + #define TMP_BIAS 0 + #define WP_RESET_CONST 7360 // 55 + #define WP_RESET2_CONST 29216 + #define WP_TRANS_STEP 32767 +//r. ================ íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== + #define G_PHOTO_STRA 60 // 56 + #define G_PHOTO_STRB 60 // 57 + + //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ === + #define HEADER_WORD_CONST 0x55aa //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + +#define DITHER_REG_PERIOD 40 //r. ïåðèîä ðåãóëèðîâàíèÿ âèáðîïðèîäà (â ïåðèîäàõ âèáðîïðèâîäà) + +#define PLC_RESET_THRESHOLD (-3276) //r. ñîîòâåòñòâóåò íàïðÿæåíèþ +1.2 âîëüòà + +//r. ìèí.äîïóñòèìàÿ ÷àñòîòà ðàñùåïëåíèÿ, ïðè êîò. äàííûå ñ÷èòàþòñÿ äîñòîâåðíûìè +#define F_RAS_MIN 10000 //r. ìèíèìàëüíàÿ ÷àñòîòà ðàñùåïëåíèÿ ïðè ñòàðòå +#define F_OUT_MIN (5000>>4) // 5000 Ãö / 16 +#define F_OUT_NORM (70000>>4) // 90000 Ãö / 16 +#define F_OUT_MAX (300000>>4) // 300000 Ãö / 16 + +#define Set_LightUp LPC_GPIO0->FIOSET = (1<<4) //set light up signal +#define Reset_LightUp LPC_GPIO0->FIOCLR = (1<<4) //reset light up signal + + //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +#define VALID_START_4SEC 3 //r. âðåìÿ ïîñëå ñòàðòà, êîãäà òåìïåðàòóðà ñòàëà äîñòîâåðíîé + +#define N_START_MAX 1 // 4 //r. ÷èñëî ïîïûòîê çàïóñêà ïðèáîðà +#define LIGHT_UP_PULSE_WDTH 5000 //1000 //e. width of light-up pulse = 100 msec +#define LIGHT_UP_PAUSE 1000 //e. pause after light-up = 100 msec +#define LIGHT_UP_POLLING 10000 //e. time of waiting laser generation = 1 sec + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define TS_MIN -2500 // minimal temperature for our thermal sensors +#define TS_MAX +13000 // maximal temperature for our thermal sensors +#define TS_DIFF_MAX 1300 // maximal difference between 2 thermal sensors + +#define HFO_NEG_MIN 8738 // -4.5 V +#define HFO_NEG_MAX 25122 // -10.5 V +#define HFO_POZ_MIN -32221 // +10.5 V +#define HFO_POZ_MAX -15837 // +4.5 V + +//e. ================ bits of the main register (_RgConA) of GLD control ============== + //r. ================ áèòû îñíîâíîãî ðåãèñòðà óïðàâëåíèÿ GLD (_RgConA) =============== + //e. ================ (bits of the status register) ============================ + //r. ================ (îíè æå - áèòû ðåãèñòðà ñîñòîÿíèÿ) ============================ +#define LASER_ON 0x0001 //r. âêë./âûêë. ãåíåðàöèþ ëàçåðà +#define HF_REG_ON 0x0002 //r. âêë./âûêë. êîíòóð ÃÂ× +#define RI_REG_ON 0x0004 //r. âêë./âûêë. êîíòóð ìîùíîñòè ÄÓÏ +#define WP_REG_ON 0x0008 //r. ìàñêà âêë./âûêë. êîíòóðà ÑÐÏ +#define WP_SIN_ON 0x0010 //r. âêë./âûêë. ïîèñêîâûé ñèãíàë ÑÐÏ +#define VB_TAU_ON 0x0020 //r. âêë./âûêë. êîíòóð àìïëèòóäû âèáðîðèâîäà +#define VB_FREQ_ON 0x0040 //r. âêë./âûêë. êîíòóð ÷àñòîòû âèáðîïðèâîäà +#define GLD_ON 0x0080 //r. âêë./âûêë. âåñü ÃËÄ + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define loop_is_closed(loop_bit) ((RgConA & (loop_bit)) == loop_bit) +#define close_loop(loop_bit) RgConA |= loop_bit +#define open_loop(loop_bit) RgConA &= ~(loop_bit) + //r. âûêëþ÷èòü âñå êîíòóðà ðåãóëèðîâàíèÿ +#define open_all_loops() RgConA = 0 +#define close_all_loops() RgConA = 0xFFFF + +extern unsigned SRgR; //r.ñèñòåìíîãî ðåãèñòðà ðåæèìà ïëàòû ADSP + +extern unsigned RgConA; //r. îñíîâíîé ðåãèñòð óïðàâëåíèÿ óñòðîéñòâà +extern unsigned RgConB; //r. äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ +//extern unsigned Copy_e5_RgR; //r. êîïèÿ ðåãèñòðà ðåæèìà ïëàòû E5 +//extern unsigned Copy_e5_RgRA; //r. êîïèÿ äîïîëíèòåëüíîãî ðåãèñòðà ðåæèìà E5 + +void contrl_GLD(void); +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CntrlGLD.h~RF105d04e.TMP --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CntrlGLD.h~RF105d04e.TMP Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,325 @@ + +#ifndef DEVICE +#define DEVICE + +//e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +typedef enum _TERMO_MODE //e. thermocompensation modes //r. ðåæèìû ðàáîòû òåðìîêîìïåíñàöèè +{ + TERMO_OFF, //e. thermocompensation is switched off //r. òåðìîêîìïåíñàöèÿ âûêëþ÷åíà + TERMO_ON, //e. thermocompensation is switched on //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà + TERMO_ON_NUMB_OFF, //e. thermocompensation is switched on, number resets (debug mode) //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_STATIC_ONLY, //e. only static thermocompensation is switched on //r. âêëþ÷åíà òîëüêî ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_DYNAMIC_ONLY, //e. only dynamic thermocompensation is switched on //r. âêëþ÷åíà òîëüêî äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_STATIC_ONLY_NUMB_OFF, //e. static thermocompensation is switched on, number resets (debug mode) //r. ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_DYNAMIC_ONLY_NUMB_OFF //e. dynamic thermocompensation is switched on, number resets (debug mode) //r. äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) +} TERMO_MODE; + +typedef enum _WATCH_MODE //e. variants of control points for scope //r. âàðèàíòû êîíòðîëüíûõ òî÷åê äëÿ îñöèëëîãðàôà +{ + VB_DELAY_MEANDER, //e. the delayed on the VB_phs meander //r. çàäåðæàííûé ìåàíäð íà âåëè÷èíó VB_phs + VB_PHASE_DETECTOR, //e. output of the PD of the dither drive //r. âûõîä ôàçîâîãî äåòåêòîðà âèþðîïðèâîäà + VB_PHASE_DETECTOR_1_SEC, //e. output of integral of the PD of the dither drive for 1 Sec //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 1 ñåê + VB_INTEGRATOR_40T, //e. output of integral of the PD of the dither drive for 40 periods //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 40 ïåðèîäîâ + WP_PHASE_DETECTOR //e. output of the PD of the CPLC regulator //r. âûõîä ôàçîâîãî äåòåêòîðà êîíòóðà ÑÐÏ +} WATCH_MODE; + +//e. ===== device operation modes ================================================================ //r. ===== ðåæèìû ðàáîòû ïðèáîðà ================================================================ +#define DM_INT_10KHZ_LATCH 1 //e. mode of internal latch 10 kHz //r. ðåæèì âíóòðåííåé çàùåëêè 10 êÃö +#define DM_INT_LATCH_DELTA_PS 2 +#define DM_INT_LATCH_DELTA_BINS 3 +#define DM_EXT_LATCH_DELTA_PS_PULSE 4 //e. mode of external latch with output of the Delta_PS command by pulse //r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_PS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_BINS_PULSE 6 //e. mode of external latch with output of the Delta_BINS command by pulse//r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_BINS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_SF_PULSE 7 //e. mode of Delta Scale factor //r. ðåæèì Delta_SF command + + //e. *** the BLOCK of VARIABLES, LOADED from FLASH-memory ********************** //r. *** ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè ********************** + //e. Address (parameter number in the block = 0..255 ) //r. Àäðåñ (Íîìåð ïàðàìåòðà â áëîêå = 0..255) +typedef union + { + int Array[171]; + struct + { // Device_blk + int My_Addres; //e. 0 - device own address //r.0 - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HFO regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + int HF_ref; //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + int HF_scl; //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int HF_min; //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + int HF_max; //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + + //e. =============== parameters of the regulator of the DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + int RI_ref; //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + int RI_scl; //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + int WP_ref; //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + int WP_scl; //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int WP_mdy; //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + int WP_rup; //e. 10 - upper value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + int WP_rdw; //e. 11 - lower value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + int VB_phs; //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + int VB_scl; //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà +unsigned int VB_N; //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ +unsigned int VB_Nmin; //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà +unsigned int VB_Nmax; //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + + int VB_Fdf_Hi; //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) +unsigned int VB_Fdf_Lo; //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + + int VB_Fsc; //e. 19 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmin; //e. 20 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmax; //e. 21 - maximum of the output value of the regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau +unsigned int VB_tau; //e. 22 - pulse width of the dither drive (without noise)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + int VBN_Tzd; //e. 23 - adjusted noise period //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ + int VBN_Ran; //e. 24 - range of the random component of noise //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + int VBN_k; //e. 25 - adjusted noise constant //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + int PI_Fsc; //_ //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + int PI_Fb0; //_ //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + int PI_scl; //_ //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + int PI_bia; //_ //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + int PI_a0; //_ // 30 + int PI_a1; //_ // 31 + int PI_a2; //_ // 32 + int PI_a3; //_ // 33 + int PI_a4; //_ // 34 + int PI_a5; //_ // 35 + int PI_a6; //_ // 36 + int PI_b1; //_ // 37 + int PI_b2; //_ // 38 + int PI_b3; //_ // 39 + int PI_b4; //_ // 40 + int PI_b5; //_ // 41 + int PI_b6; //_ // 42 + + //e. =============== parameters of normalization of the temperature sensors ============= //r. =============== ïàðàìåòðû íîðìèðîâêè äàò÷èêîâ òåìïåðàòóðû ============= + + int Tmp_bias[6]; //_ //e. 43 - an array of shifts of the 0..5 temperature sensors //r. 43 - ìàññèâ ñäâèãîâ òåìïåðàòóðíûõ äàò÷èêîâ 0..5 + int Tmp_scal[6]; //_ //e. 49 - an array of the scale coefficients of temperature sensors//r. 49 - ìàññèâ ìàñøòàáíûõ ê-òîâ òåìïåðàòóðíûõ äàò÷èêîâ + int WP_reset; //e. 55 - initial position of the CPLC regulator (after reset) //r. 55 - èñõîäíîå ïîëîæåíèå ðåãóëÿòîðà ÑÐÏ (ïîñëå ñáðîñà) + + //e. ================ gain factor of photodetector channels =========== //r. ================ ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== +unsigned int Gain_Ph_A; //e. 56 - initial gain factor of the A channel of photodetector //r. 56 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà À ôîòîïðèåìíèêà +unsigned int Gain_Ph_B; //e. 57 - initial gain factor of the B channel of photodetector //r. 57 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà B ôîòîïðèåìíèêà + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ (ãàëî÷êà â íàñòîðîå÷íîé ïðîãðàììå) + int Header_Word; //e. 58 - flash sector validity header //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + int LoadFlash_enable; //e. 59 - source loading flag: 1 - load from the flash //r. 59 - ïðèçíàê èñòî÷íèêà çàãðóçêè: 1 - ãðóçèòüñÿ èç flesh + //e. 0 - load default parameters (factory) //r. 0 - ãðóçèòü ïàðàìåòðû ïî óìîë÷àíèþ (çàâîäñêèå) +unsigned int Device_SerialNumber; //e. 60 - serial number of the device //r. 60 - ñåðèéíûé íîìåð ïðèáîðà + int Reserved0; //e. 61 - not used + TERMO_MODE TermoMode; //e 62 - device operation mode (with thermocompenstion, without it, debug )//r. 62 - ðåæèì ðàáîòû ïðèáîðà (ñ òåðìîêîìïåíñàöèåé, áåç íåå èëè îòëàäêà) +//e. addition for the piecewise-linear termocorrection //r. äîáàâëåíèå äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîððåêöèè + int TemperInt[TERMO_FUNC_SIZE]; //e. 63 + float TermoFunc[TERMO_FUNC_SIZE]; //e. 77 + int WP_reset2; //e. 91 - voltages of CPLC regulator reset at cooling //r. xx - íàïðÿæåíèÿ îáíóëåíèÿ êîíòóðà ÑÐÏ ïðè îõëàæäåíèè + //e. parameters setting termocompensation parameters in dynamics (at heating and cooling) //r. ïàðàìåòðû, çàäàþùèå ïàðàìåòðû òåðìîêîìïåíñàöèè â äèíàìèêå (ïðè íàãðåâå è îõëàæäåíèè) + float Reserved1; //e. 92 - not used + float Reserved2; //e. 93 - not used + int K_vb_tu; //e. 94 - slope of dependence of the VB_N division factor from temperature (as though Hz/degree, but in relative units ) //r. êðóòèçíà çàâèñèìîñòè êîýôôèöèåíòà äåëåíèÿ VB_N îò òåìïåðàòóðû (êàê áû Ãö/ãðàäóñ, íî â ó.å.) + int TemperNormal; //e. 95 -temperature for which the VB_N division factor of the dither drive is set //r. òåìïåðàòóðà, äëÿ êîòîðîé çàäàí êîýôôèöèåíò äåëåíèÿ âèáðîïðèâîäà VB_N + int K_WP_rst_heating; //r. 96 - êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè íàãðåâàíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int K_WP_rst_cooling; //e. 97 - slope of dependence of a reset voltage at cooling from temperature (as though Volt/degree, but in relative units of DAC and temperature sensors) //r. êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè îõëàæäåíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int WP_transition_step; //e. 98 - step of change of a heater voltage at resetting //r. øàã èçìåíåíèÿ íàïðÿæåíèÿ íàãðåâàòåëÿ ïðè âûïîëíåíèè îáíóëåíèÿ + int Reserved3; // e. 99 -not used + int HF_scl_2; //r. 100 - êîýôôèöèåíò ïåðåäà÷è (1.15) êîíòóðà ÃÂ× ïðè îáíóëåíèè + int TemperIntDyn[TERMO_FUNC_SIZE]; //e. 114 - + float ThermoHeatDelta[TERMO_FUNC_SIZE]; //e. 128 - + int DeltaTempRecalc; //r. 129 - òåìïåðàòóðíûé èíòåðâàë ïåðåñ÷åòà äèíàìè÷. êîìïåíñàöèè (â ó.å.) //e. temperature delta for dynamic thermocompensation recalculation(in relative units) + int TemperCoolIntDyn[TERMO_FUNC_SIZE]; // e. 143 - + float ThermoCoolDelta[TERMO_FUNC_SIZE]; //e. 157 - + } Str; +} TDEVICE_BLK; + + + + + + + + + + + +//e. ************ end of the BLOCK of VARIABLES, LOADED from FLASH-memory ************ //r. ************ êîíåö áëîêà çàãðóæàåìûõ èç ôëýø-ïàìÿòè ïàðàìåòðîâ ÃËÄ ************ +extern TDEVICE_BLK Device_blk; //e. the BLOCK of VARIABLES, LOADED from FLASH-memory //r. ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè + +extern int Device_Mode; +extern unsigned Valid_Data; + +extern unsigned ser_num; + +extern int VB_Nmin0; //e. minimum of the output value of a regulator of the period for the Device_blk.TemperNormal temperature //r. ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal +extern int VB_Nmax0; //e. maximum of the output value of a regulator of the period for the Device_blk.TemperNormal //r. ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal + +extern unsigned BIT_number; +extern unsigned Is_BIT; + +extern unsigned start_Rq; //e. request for device starting //r. çàïðîñ íà çàïóñê ïðèáîðà +extern unsigned stop_Rq; //e. request for device stopping //r. çàïðîñ íà îñòàíîâ ïðèáîðà +extern unsigned pulse_Rq; //e. request for light-up of laser //r. çàïðîñ íà ïîäæèã ëàçåðà + + //e. *** Default device parameters ********************** //r. *** Ïðèáîðíûå ïàðàìåòðû ïî óìîë÷àíèþ ********************** +#define DEVICE_SN 1 //e. device serial number = 01 //r. ñåðèéíûé íîìåð ïðèáîðà = 01 +#define My_Addres_const 0 //e. - device own address //r. - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HF regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + #define HF_REF_CONST 15080 //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + #define HF_SCL_CONST 1 // 0x64 //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define HF_MIN_CONST -32668 //e. 3 - minimum of the output value on the regulator DAC (appropriate to maximal voltage on the HFO) //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + #define HF_MAX_CONST -17379 //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + #define HFO_SHIFT 16 //e. number of digits of fractional part in 32-bit variable of the hf_reg32 varaible //r. ÷èñëî ðàçðÿäîâ äðîáíîé ÷àñòè â 32-õáèòîâîé ïåðåìåííîé hf_reg32 + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + #define WP_REF_CONST 5 //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + #define WP_SCL_CONST 5 //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define WP_MDY_CONST 30 //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + #define WP_RUP_CONST 31936 //e. 10 - lower value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - íèæíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + #define WP_RDW_CONST 11801 //e. 11 - upper value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + #define VB_PHS_CONST 4 //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + #define VB_SCL_CONST 1024 //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà + #define T_VIB_START 16600 //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ + //e. _VB_N - the initial value of the oscillation period of the dither drive (406Hz-18916, 17067 - 450Hz) //r. _VB_N íà÷àëüíûé ïåðèîä êîëåáàíèé âèáðîïðèâîäà (406Hz-18916, 17067 - 450Hz) + #define T_VIB_DELTA 1000 //e. the range of the oscillation period of the dither drive (~ +/- 10 Hz) //r. äèàïàçîí èçìåíåíèÿ ïåðèîäà êîëåáàíèé âèáðîïðèâîäà (~ +/- 10 Hz) + + #define VB_NMIN_CONST 12080 //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_NMAX_CONST 64000 //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_FDF_HI_CONST 3 //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) + #define VB_FDF_LO_CONST 0 //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + #define VB_FSC_CONST -2000 //e. 19 - the gain factor of the output frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ + #define VB_TMIN_CONST 100 //e. 20 - minimum of the output value of the Tau regulator //r. 20 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define VB_TMAX_CONST 10022 //e. 21 - maximum of the output value of the Tau regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define L_VIB_START 5120 //e. 22 - pulse width of the dither drive (before noiseness)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + //e. _VB_tau - initial pulse width of the dither drive //r. _VB_tau íà÷àëüíàÿ äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà + + #define VBN_TZD_CONST 500 //e. 23 - adjusted noise[??] period (user`s constant) //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + #define VBN_RAN_CONST 400 //e. 24 - range of the random component of noiseness //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + #define VBN_K_CONST 7000 //e. 25 - adjusted noise constant (user`s constant) //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + + //e. =============== parameters of DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + #define RI_REF_CONST 25600 //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + #define RI_SCL_CONST 0 //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + #define PI_FSC_CONST 128 //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + #define PI_FB0_CONST 0 //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + #define PI_SCL_CONST 256 //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + #define PI_BIA_CONST 0 //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + #define PI_A0_CONST 0 // 30 + #define PI_A1_CONST 0 // 31 + #define PI_A2_CONST 0 // 32 + #define PI_A3_CONST 0 // 33 + #define PI_A4_CONST 0 // 34 + #define PI_A5_CONST 0 // 35 + #define PI_A6_CONST 0 // 36 + #define PI_B1_CONST 0 // 37 + #define PI_B2_CONST 0 // 38 + #define PI_B3_CONST 0 // 39 + #define PI_B4_CONST 0 // 40 + #define PI_B5_CONST 0 // 41 + #define PI_B6_CONST 0 // 42 + + #define TMP_SCALE 0x4000 // 43 - 54 Tmp_bias[6]; Tmp_scal[6] + #define TMP_BIAS 0 + #define WP_RESET_CONST 7360 // 55 + #define WP_RESET2_CONST 29216 + #define WP_TRANS_STEP 32767 + //e. ================ initial gain factor of photodetector channels =========== //r. ================ íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== + #define G_PHOTO_STRA 60 // 56 + #define G_PHOTO_STRB 60 // 57 + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ === + #define HEADER_WORD_CONST 0x55aa //e. 58 - magic number flash validity //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + +#define DITHER_REG_PERIOD 40 //e. period of dither regulator (in periods of dither frequency) //r. ïåðèîä ðåãóëèðîâàíèÿ âèáðîïðèîäà (â ïåðèîäàõ âèáðîïðèâîäà) + +#define PLC_RESET_THRESHOLD (-3276) //e. correspond to the voltage +1.2 Volts //r. ñîîòâåòñòâóåò íàïðÿæåíèþ +1.2 âîëüòà + + //e. minimal allowable output frequency, at which data are considered authentic //r. ìèí.äîïóñòèìàÿ ÷àñòîòà ðàñùåïëåíèÿ, ïðè êîò. äàííûå ñ÷èòàþòñÿ äîñòîâåðíûìè +#define F_RAS_MIN 10000 //e. minimal output frequency at start //r. ìèíèìàëüíàÿ ÷àñòîòà ðàñùåïëåíèÿ ïðè ñòàðòå +#define F_OUT_MIN (5000>>4) // 5000 Ãö / 16 +#define F_OUT_NORM (70000>>4) // 90000 Ãö / 16 +#define F_OUT_MAX (300000>>4) // 300000 Ãö / 16 + +#define Set_LightUp LPC_GPIO0->FIOSET = (1<<4) //set light up signal +#define Reset_LightUp LPC_GPIO0->FIOCLR = (1<<4) //reset light up signal + + //e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +#define VALID_START_4SEC 3 //e. time after start, when temperature came authentic //r. âðåìÿ ïîñëå ñòàðòà, êîãäà òåìïåðàòóðà ñòàëà äîñòîâåðíîé + +#define N_START_MAX 1 // 4 //e. count of attempts of device starting //r. ÷èñëî ïîïûòîê çàïóñêà ïðèáîðà +#define LIGHT_UP_PULSE_WDTH 5000 //1000 //e. width of light-up pulse = 100 msec +#define LIGHT_UP_PAUSE 1000 //e. pause after light-up = 100 msec +#define LIGHT_UP_POLLING 10000 //e. time of waiting laser generation = 1 sec + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define TS_MIN -2500 // minimal temperature for our thermal sensors +#define TS_MAX +13000 // maximal temperature for our thermal sensors +#define TS_DIFF_MAX 1300 // maximal difference between 2 thermal sensors + +#define HFO_NEG_MIN 8738 // -4.5 V +#define HFO_NEG_MAX 25122 // -10.5 V +#define HFO_POZ_MIN -32221 // +10.5 V +#define HFO_POZ_MAX -15837 // +4.5 V + +//e. ================ bits of the main register (_RgConA) of GLD control ============== + //r. ================ áèòû îñíîâíîãî ðåãèñòðà óïðàâëåíèÿ GLD (_RgConA) =============== + //e. ================ (bits of the status register) ============================ + //r. ================ (îíè æå - áèòû ðåãèñòðà ñîñòîÿíèÿ) ============================ +#define LASER_ON 0x0001 //e. switch on/off laser-up //r. âêë./âûêë. ãåíåðàöèþ ëàçåðà +#define HF_REG_ON 0x0002 //e. switch on/off the HFO regulator //r. âêë./âûêë. êîíòóð ÃÂ× +#define RI_REG_ON 0x0004 //e. switch on/off the DS power regulator //r. âêë./âûêë. êîíòóð ìîùíîñòè ÄÓÏ +#define WP_REG_ON 0x0008 //e. a mask of switch on/off of the CPLC regulator //r. ìàñêà âêë./âûêë. êîíòóðà ÑÐÏ +#define WP_SIN_ON 0x0010 //e. switch on/off search signal of the CPLC //r. âêë./âûêë. ïîèñêîâûé ñèãíàë ÑÐÏ +#define VB_TAU_ON 0x0020 //e. switch on/off amplitude regulator of the dither drive //r. âêë./âûêë. êîíòóð àìïëèòóäû âèáðîðèâîäà +#define VB_FREQ_ON 0x0040 //e. switch on/off frequency regulator of the dither drive //r. âêë./âûêë. êîíòóð ÷àñòîòû âèáðîïðèâîäà +#define GLD_ON 0x0080 //e. switch on/off all GLD //r. âêë./âûêë. âåñü ÃËÄ + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define loop_is_closed(loop_bit) ((RgConA & (loop_bit)) == loop_bit) +#define close_loop(loop_bit) RgConA |= loop_bit +#define open_loop(loop_bit) RgConA &= ~(loop_bit) + //e. switch off all regulators //r. âûêëþ÷èòü âñå êîíòóðà ðåãóëèðîâàíèÿ +#define open_all_loops() RgConA = 0 +#define close_all_loops() RgConA = 0xFFFF + +extern unsigned SRgR; //e. system register of the ADSP card //r.ñèñòåìíîãî ðåãèñòðà ðåæèìà ïëàòû ADSP + +extern unsigned RgConA; //e. main register of device control //r. îñíîâíîé ðåãèñòð óïðàâëåíèÿ óñòðîéñòâà +extern unsigned RgConB; //e. additional register of device control //r. äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ +//extern unsigned Copy_e5_RgR; //e. copy of the mode register of the E5 card //r. êîïèÿ ðåãèñòðà ðåæèìà ïëàòû E5 +//extern unsigned Copy_e5_RgRA; //e. copy of the additional mode register of the E5 card //r. êîïèÿ äîïîëíèòåëüíîãî ðåãèñòðà ðåæèìà E5 + +void contrl_GLD(void); +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CntrlGLD.h~RF1796de6.TMP --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CntrlGLD.h~RF1796de6.TMP Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,316 @@ + +#ifndef DEVICE +#define DEVICE + +//e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +typedef enum _TERMO_MODE //e. thermocompensation modes //r. ðåæèìû ðàáîòû òåðìîêîìïåíñàöèè +{ + TERMO_OFF, //e. thermocompensation is switched off //r. òåðìîêîìïåíñàöèÿ âûêëþ÷åíà + TERMO_ON, //e. thermocompensation is switched on //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà + TERMO_ON_NUMB_OFF, //e. thermocompensation is switched on, number resets (debug mode) //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_STATIC_ONLY, //e. only static thermocompensation is switched on //r. âêëþ÷åíà òîëüêî ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_DYNAMIC_ONLY, //e. only dynamic thermocompensation is switched on //r. âêëþ÷åíà òîëüêî äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_STATIC_ONLY_NUMB_OFF, //e. static thermocompensation is switched on, number resets (debug mode) //r. ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_DYNAMIC_ONLY_NUMB_OFF //e. dynamic thermocompensation is switched on, number resets (debug mode) //r. äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) +} TERMO_MODE; + +typedef enum _WATCH_MODE //e. variants of control points for scope //r. âàðèàíòû êîíòðîëüíûõ òî÷åê äëÿ îñöèëëîãðàôà +{ + VB_DELAY_MEANDER, //e. the delayed on the VB_phs meander //r. çàäåðæàííûé ìåàíäð íà âåëè÷èíó VB_phs + VB_PHASE_DETECTOR, //e. output of the PD of the dither drive //r. âûõîä ôàçîâîãî äåòåêòîðà âèþðîïðèâîäà + VB_PHASE_DETECTOR_1_SEC, //e. output of integral of the PD of the dither drive for 1 Sec //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 1 ñåê + VB_INTEGRATOR_40T, //e. output of integral of the PD of the dither drive for 40 periods //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 40 ïåðèîäîâ + WP_PHASE_DETECTOR //e. output of the PD of the CPLC regulator //r. âûõîä ôàçîâîãî äåòåêòîðà êîíòóðà ÑÐÏ +} WATCH_MODE; + +//e. ===== device operation modes ================================================================ //r. ===== ðåæèìû ðàáîòû ïðèáîðà ================================================================ +#define DM_INT_10KHZ_LATCH 1 //e. mode of internal latch 10 kHz //r. ðåæèì âíóòðåííåé çàùåëêè 10 êÃö +#define DM_INT_LATCH_DELTA_PS 2 +#define DM_INT_LATCH_DELTA_BINS 3 +#define DM_EXT_LATCH_DELTA_PS_PULSE 4 //e. mode of external latch with output of the Delta_PS command by pulse //r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_PS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_BINS_PULSE 6 //e. mode of external latch with output of the Delta_BINS command by pulse//r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_BINS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_SF_PULSE 7 //e. mode of Delta Scale factor //r. ðåæèì Delta_SF command + + //e. *** the BLOCK of VARIABLES, LOADED from FLASH-memory ********************** //r. *** ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè ********************** + //e. Address (parameter number in the block = 0..255 ) //r. Àäðåñ (Íîìåð ïàðàìåòðà â áëîêå = 0..255) +typedef union + { + int Array[171]; + struct + { // Device_blk + int My_Addres; //e. 0 - device own address //r.0 - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HFO regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + int HF_ref; //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + int HF_scl; //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int HF_min; //e. 3 - minimum of the output value on the regulator DAC (appropriate to maximal voltage on the HFO) //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + int HF_max; //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + + //e. =============== parameters of the regulator of the DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + int RI_ref; //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + int RI_scl; //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + int WP_ref; //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + int WP_scl; //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int WP_mdy; //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + int WP_rup; //e. 10 - upper value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + int WP_rdw; //e. 11 - lower value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + int VB_phs; //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + int VB_scl; //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà +unsigned int VB_N; //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ +unsigned int VB_Nmin; //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà +unsigned int VB_Nmax; //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + + int VB_Fdf_Hi; //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) +unsigned int VB_Fdf_Lo; //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + + int VB_Fsc; //e. 19 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmin; //e. 20 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmax; //e. 21 - maximum of the output value of the regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau +unsigned int VB_tau; //e. 22 - pulse width of the dither drive (without noise)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + int VBN_Tzd; //e. 23 - adjusted noise period //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ + int VBN_Ran; //e. 24 - range of the random component of noise //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + int VBN_k; //e. 25 - adjusted noise constant //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + int PI_Fsc; //_ //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + int PI_Fb0; //_ //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + int PI_scl; //_ //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + int PI_bia; //_ //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + int PI_a0; //_ // 30 + int PI_a1; //_ // 31 + int PI_a2; //_ // 32 + int PI_a3; //_ // 33 + int PI_a4; //_ // 34 + int PI_a5; //_ // 35 + int PI_a6; //_ // 36 + int PI_b1; //_ // 37 + int PI_b2; //_ // 38 + int PI_b3; //_ // 39 + int PI_b4; //_ // 40 + int PI_b5; //_ // 41 + int PI_b6; //_ // 42 + + //e. =============== parameters of normalization of the temperature sensors ============= //r. =============== ïàðàìåòðû íîðìèðîâêè äàò÷èêîâ òåìïåðàòóðû ============= + + int Tmp_bias[6]; //_ //e. 43 - an array of shifts of the 0..5 temperature sensors //r. 43 - ìàññèâ ñäâèãîâ òåìïåðàòóðíûõ äàò÷èêîâ 0..5 + int Tmp_scal[6]; //_ //e. 49 - an array of the scale coefficients of temperature sensors//r. 49 - ìàññèâ ìàñøòàáíûõ ê-òîâ òåìïåðàòóðíûõ äàò÷èêîâ + int WP_reset; //e. 55 - initial position of the CPLC regulator (after reset) //r. 55 - èñõîäíîå ïîëîæåíèå ðåãóëÿòîðà ÑÐÏ (ïîñëå ñáðîñà) + + //e. ================ gain factor of photodetector channels =========== //r. ================ ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== +unsigned int Gain_Ph_A; //e. 56 - initial gain factor of the A channel of photodetector //r. 56 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà À ôîòîïðèåìíèêà +unsigned int Gain_Ph_B; //e. 57 - initial gain factor of the B channel of photodetector //r. 57 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà B ôîòîïðèåìíèêà + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ (ãàëî÷êà â íàñòîðîå÷íîé ïðîãðàììå) + int Header_Word; //e. 58 - flash sector validity header //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + int LoadFlash_enable; //e. 59 - source loading flag: 1 - load from the flash //r. 59 - ïðèçíàê èñòî÷íèêà çàãðóçêè: 1 - ãðóçèòüñÿ èç flesh + //e. 0 - load default parameters (factory) //r. 0 - ãðóçèòü ïàðàìåòðû ïî óìîë÷àíèþ (çàâîäñêèå) +unsigned int Device_SerialNumber; //e. 60 - serial number of the device //r. 60 - ñåðèéíûé íîìåð ïðèáîðà + int Reserved0; //e. 61 - not used + TERMO_MODE TermoMode; //e 62 - device operation mode (with thermocompenstion, without it, debug )//r. 62 - ðåæèì ðàáîòû ïðèáîðà (ñ òåðìîêîìïåíñàöèåé, áåç íåå èëè îòëàäêà) +//e. addition for the piecewise-linear termocorrection //r. äîáàâëåíèå äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîððåêöèè + int TemperInt[TERMO_FUNC_SIZE]; //e. 63 + float TermoFunc[TERMO_FUNC_SIZE]; //e. 77 + int WP_reset2; //e. 91 - voltages of CPLC regulator reset at cooling //r. xx - íàïðÿæåíèÿ îáíóëåíèÿ êîíòóðà ÑÐÏ ïðè îõëàæäåíèè + //e. parameters setting termocompensation parameters in dynamics (at heating and cooling) //r. ïàðàìåòðû, çàäàþùèå ïàðàìåòðû òåðìîêîìïåíñàöèè â äèíàìèêå (ïðè íàãðåâå è îõëàæäåíèè) + float Reserved1; //e. 92 - not used + float Reserved2; //e. 93 - not used + int K_vb_tu; //e. 94 - slope of dependence of the VB_N division factor from temperature (as though Hz/degree, but in relative units ) //r. êðóòèçíà çàâèñèìîñòè êîýôôèöèåíòà äåëåíèÿ VB_N îò òåìïåðàòóðû (êàê áû Ãö/ãðàäóñ, íî â ó.å.) + int TemperNormal; //e. 95 -temperature for which the VB_N division factor of the dither drive is set //r. òåìïåðàòóðà, äëÿ êîòîðîé çàäàí êîýôôèöèåíò äåëåíèÿ âèáðîïðèâîäà VB_N + int K_WP_rst_heating; //r. 96 - êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè íàãðåâàíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int K_WP_rst_cooling; //e. 97 - slope of dependence of a reset voltage at cooling from temperature (as though Volt/degree, but in relative units of DAC and temperature sensors) //r. êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè îõëàæäåíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int WP_transition_step; //e. 98 - step of change of a heater voltage at resetting //r. øàã èçìåíåíèÿ íàïðÿæåíèÿ íàãðåâàòåëÿ ïðè âûïîëíåíèè îáíóëåíèÿ + int Reserved3; // e. 99 -not used + int HF_scl_2; //r. 100 - êîýôôèöèåíò ïåðåäà÷è (1.15) êîíòóðà ÃÂ× ïðè îáíóëåíèè + int TemperIntDyn[TERMO_FUNC_SIZE]; //e. 114 - + float ThermoHeatDelta[TERMO_FUNC_SIZE]; //e. 128 - + int DeltaTempRecalc; //r. 129 - òåìïåðàòóðíûé èíòåðâàë ïåðåñ÷åòà äèíàìè÷. êîìïåíñàöèè (â ó.å.) //e. temperature delta for dynamic thermocompensation recalculation(in relative units) + int TemperCoolIntDyn[TERMO_FUNC_SIZE]; // e. 143 - + float ThermoCoolDelta[TERMO_FUNC_SIZE]; //e. 157 - + } Str; +} TDEVICE_BLK; + + +//e. ************ end of the BLOCK of VARIABLES, LOADED from FLASH-memory ************ //r. ************ êîíåö áëîêà çàãðóæàåìûõ èç ôëýø-ïàìÿòè ïàðàìåòðîâ ÃËÄ ************ +extern TDEVICE_BLK Device_blk; //e. the BLOCK of VARIABLES, LOADED from FLASH-memory //r. ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè + +extern int Device_Mode; +extern unsigned Valid_Data; + +extern unsigned ser_num; + +extern int VB_Nmin0; //e. minimum of the output value of a regulator of the period for the Device_blk.TemperNormal temperature //r. ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal +extern int VB_Nmax0; //e. maximum of the output value of a regulator of the period for the Device_blk.TemperNormal //r. ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal + +extern unsigned BIT_number; +extern unsigned Is_BIT; + +extern unsigned start_Rq; //e. request for device starting //r. çàïðîñ íà çàïóñê ïðèáîðà +extern unsigned stop_Rq; //e. request for device stopping //r. çàïðîñ íà îñòàíîâ ïðèáîðà +extern unsigned pulse_Rq; //e. request for light-up of laser //r. çàïðîñ íà ïîäæèã ëàçåðà + + //e. *** Default device parameters ********************** //r. *** Ïðèáîðíûå ïàðàìåòðû ïî óìîë÷àíèþ ********************** +#define DEVICE_SN 1 //e. device serial number = 01 //r. ñåðèéíûé íîìåð ïðèáîðà = 01 +#define My_Addres_const 0 //e. - device own address //r. - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HF regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + #define HF_REF_CONST 15080 //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + #define HF_SCL_CONST 1 // 0x64 //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define HF_MIN_CONST -32668 //e. 3 - minimum of the output value on the regulator DAC (appropriate to maximal voltage on the HFO) //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + #define HF_MAX_CONST -17379 //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + #define HFO_SHIFT 16 //e. number of digits of fractional part in 32-bit variable of the hf_reg32 varaible //r. ÷èñëî ðàçðÿäîâ äðîáíîé ÷àñòè â 32-õáèòîâîé ïåðåìåííîé hf_reg32 + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + #define WP_REF_CONST 5 //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + #define WP_SCL_CONST 5 //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define WP_MDY_CONST 30 //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + #define WP_RUP_CONST 31936 //e. 10 - lower value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - íèæíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + #define WP_RDW_CONST 11801 //e. 11 - upper value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + #define VB_PHS_CONST 4 //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + #define VB_SCL_CONST 1024 //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà + #define T_VIB_START 16600 //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ + //e. _VB_N - the initial value of the oscillation period of the dither drive (406Hz-18916, 17067 - 450Hz) //r. _VB_N íà÷àëüíûé ïåðèîä êîëåáàíèé âèáðîïðèâîäà (406Hz-18916, 17067 - 450Hz) + #define T_VIB_DELTA 1000 //e. the range of the oscillation period of the dither drive (~ +/- 10 Hz) //r. äèàïàçîí èçìåíåíèÿ ïåðèîäà êîëåáàíèé âèáðîïðèâîäà (~ +/- 10 Hz) + + #define VB_NMIN_CONST 12080 //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_NMAX_CONST 64000 //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_FDF_HI_CONST 3 //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) + #define VB_FDF_LO_CONST 0 //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + #define VB_FSC_CONST -2000 //e. 19 - the gain factor of the output frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ + #define VB_TMIN_CONST 100 //e. 20 - minimum of the output value of the Tau regulator //r. 20 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define VB_TMAX_CONST 10022 //e. 21 - maximum of the output value of the Tau regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define L_VIB_START 5120 //e. 22 - pulse width of the dither drive (before noiseness)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + //e. _VB_tau - initial pulse width of the dither drive //r. _VB_tau íà÷àëüíàÿ äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà + + #define VBN_TZD_CONST 500 //e. 23 - adjusted noise[??] period (user`s constant) //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + #define VBN_RAN_CONST 400 //e. 24 - range of the random component of noiseness //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + #define VBN_K_CONST 7000 //e. 25 - adjusted noise constant (user`s constant) //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + + //e. =============== parameters of DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + #define RI_REF_CONST 25600 //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + #define RI_SCL_CONST 0 //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + #define PI_FSC_CONST 128 //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + #define PI_FB0_CONST 0 //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + #define PI_SCL_CONST 256 //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + #define PI_BIA_CONST 0 //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + #define PI_A0_CONST 0 // 30 + #define PI_A1_CONST 0 // 31 + #define PI_A2_CONST 0 // 32 + #define PI_A3_CONST 0 // 33 + #define PI_A4_CONST 0 // 34 + #define PI_A5_CONST 0 // 35 + #define PI_A6_CONST 0 // 36 + #define PI_B1_CONST 0 // 37 + #define PI_B2_CONST 0 // 38 + #define PI_B3_CONST 0 // 39 + #define PI_B4_CONST 0 // 40 + #define PI_B5_CONST 0 // 41 + #define PI_B6_CONST 0 // 42 + + #define TMP_SCALE 0x4000 // 43 - 54 Tmp_bias[6]; Tmp_scal[6] + #define TMP_BIAS 0 + #define WP_RESET_CONST 7360 // 55 + #define WP_RESET2_CONST 29216 + #define WP_TRANS_STEP 32767 + //e. ================ initial gain factor of photodetector channels =========== //r. ================ íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== + #define G_PHOTO_STRA 60 // 56 + #define G_PHOTO_STRB 60 // 57 + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ === + #define HEADER_WORD_CONST 0x55aa //e. 58 - magic number flash validity //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + +#define DITHER_REG_PERIOD 40 //e. period of dither regulator (in periods of dither frequency) //r. ïåðèîä ðåãóëèðîâàíèÿ âèáðîïðèîäà (â ïåðèîäàõ âèáðîïðèâîäà) + +#define PLC_RESET_THRESHOLD (-3276) //e. correspond to the voltage +1.2 Volts //r. ñîîòâåòñòâóåò íàïðÿæåíèþ +1.2 âîëüòà + + //e. minimal allowable output frequency, at which data are considered authentic //r. ìèí.äîïóñòèìàÿ ÷àñòîòà ðàñùåïëåíèÿ, ïðè êîò. äàííûå ñ÷èòàþòñÿ äîñòîâåðíûìè +#define F_RAS_MIN 10000 //e. minimal output frequency at start //r. ìèíèìàëüíàÿ ÷àñòîòà ðàñùåïëåíèÿ ïðè ñòàðòå +#define F_OUT_MIN (5000>>4) // 5000 Ãö / 16 +#define F_OUT_NORM (70000>>4) // 90000 Ãö / 16 +#define F_OUT_MAX (300000>>4) // 300000 Ãö / 16 + +#define Set_LightUp LPC_GPIO0->FIOSET = (1<<4) //set light up signal +#define Reset_LightUp LPC_GPIO0->FIOCLR = (1<<4) //reset light up signal + + //e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +#define VALID_START_4SEC 3 //e. time after start, when temperature came authentic //r. âðåìÿ ïîñëå ñòàðòà, êîãäà òåìïåðàòóðà ñòàëà äîñòîâåðíîé + +#define N_START_MAX 1 // 4 //e. count of attempts of device starting //r. ÷èñëî ïîïûòîê çàïóñêà ïðèáîðà +#define LIGHT_UP_PULSE_WDTH 5000 //1000 //e. width of light-up pulse = 100 msec +#define LIGHT_UP_PAUSE 1000 //e. pause after light-up = 100 msec +#define LIGHT_UP_POLLING 10000 //e. time of waiting laser generation = 1 sec + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define TS_MIN -2500 // minimal temperature for our thermal sensors +#define TS_MAX +13000 // maximal temperature for our thermal sensors +#define TS_DIFF_MAX 1300 // maximal difference between 2 thermal sensors + +#define HFO_NEG_MIN 8738 // -4.5 V +#define HFO_NEG_MAX 25122 // -10.5 V +#define HFO_POZ_MIN -32221 // +10.5 V +#define HFO_POZ_MAX -15837 // +4.5 V + +//e. ================ bits of the main register (_RgConA) of GLD control ============== + //r. ================ áèòû îñíîâíîãî ðåãèñòðà óïðàâëåíèÿ GLD (_RgConA) =============== + //e. ================ (bits of the status register) ============================ + //r. ================ (îíè æå - áèòû ðåãèñòðà ñîñòîÿíèÿ) ============================ +#define LASER_ON 0x0001 //e. switch on/off laser-up //r. âêë./âûêë. ãåíåðàöèþ ëàçåðà +#define HF_REG_ON 0x0002 //e. switch on/off the HFO regulator //r. âêë./âûêë. êîíòóð ÃÂ× +#define RI_REG_ON 0x0004 //e. switch on/off the DS power regulator //r. âêë./âûêë. êîíòóð ìîùíîñòè ÄÓÏ +#define WP_REG_ON 0x0008 //e. a mask of switch on/off of the CPLC regulator //r. ìàñêà âêë./âûêë. êîíòóðà ÑÐÏ +#define WP_SIN_ON 0x0010 //e. switch on/off search signal of the CPLC //r. âêë./âûêë. ïîèñêîâûé ñèãíàë ÑÐÏ +#define VB_TAU_ON 0x0020 //e. switch on/off amplitude regulator of the dither drive //r. âêë./âûêë. êîíòóð àìïëèòóäû âèáðîðèâîäà +#define VB_FREQ_ON 0x0040 //e. switch on/off frequency regulator of the dither drive //r. âêë./âûêë. êîíòóð ÷àñòîòû âèáðîïðèâîäà +#define GLD_ON 0x0080 //e. switch on/off all GLD //r. âêë./âûêë. âåñü ÃËÄ + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define loop_is_closed(loop_bit) ((RgConA & (loop_bit)) == loop_bit) +#define close_loop(loop_bit) RgConA |= loop_bit +#define open_loop(loop_bit) RgConA &= ~(loop_bit) + //e. switch off all regulators //r. âûêëþ÷èòü âñå êîíòóðà ðåãóëèðîâàíèÿ +#define open_all_loops() RgConA = 0 +#define close_all_loops() RgConA = 0xFFFF + +extern unsigned SRgR; //e. system register of the ADSP card //r.ñèñòåìíîãî ðåãèñòðà ðåæèìà ïëàòû ADSP + +extern unsigned RgConA; //e. main register of device control //r. îñíîâíîé ðåãèñòð óïðàâëåíèÿ óñòðîéñòâà +extern unsigned RgConB; //e. additional register of device control //r. äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ +//extern unsigned Copy_e5_RgR; //e. copy of the mode register of the E5 card //r. êîïèÿ ðåãèñòðà ðåæèìà ïëàòû E5 +//extern unsigned Copy_e5_RgRA; //e. copy of the additional mode register of the E5 card //r. êîïèÿ äîïîëíèòåëüíîãî ðåãèñòðà ðåæèìà E5 + +void contrl_GLD(void); +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CntrlGLD.h~RF1a0a05c.TMP --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CntrlGLD.h~RF1a0a05c.TMP Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,316 @@ + +#ifndef DEVICE +#define DEVICE + +//e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +typedef enum _TERMO_MODE //e. thermocompensation modes //r. ðåæèìû ðàáîòû òåðìîêîìïåíñàöèè +{ + TERMO_OFF, //e. thermocompensation is switched off //r. òåðìîêîìïåíñàöèÿ âûêëþ÷åíà + TERMO_ON, //e. thermocompensation is switched on //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà + TERMO_ON_NUMB_OFF, //e. thermocompensation is switched on, number resets (debug mode) //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_STATIC_ONLY, //e. only static thermocompensation is switched on //r. âêëþ÷åíà òîëüêî ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_DYNAMIC_ONLY, //e. only dynamic thermocompensation is switched on //r. âêëþ÷åíà òîëüêî äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_STATIC_ONLY_NUMB_OFF, //e. static thermocompensation is switched on, number resets (debug mode) //r. ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_DYNAMIC_ONLY_NUMB_OFF //e. dynamic thermocompensation is switched on, number resets (debug mode) //r. äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) +} TERMO_MODE; + +typedef enum _WATCH_MODE //e. variants of control points for scope //r. âàðèàíòû êîíòðîëüíûõ òî÷åê äëÿ îñöèëëîãðàôà +{ + VB_DELAY_MEANDER, //e. the delayed on the VB_phs meander //r. çàäåðæàííûé ìåàíäð íà âåëè÷èíó VB_phs + VB_PHASE_DETECTOR, //e. output of the PD of the dither drive //r. âûõîä ôàçîâîãî äåòåêòîðà âèþðîïðèâîäà + VB_PHASE_DETECTOR_1_SEC, //e. output of integral of the PD of the dither drive for 1 Sec //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 1 ñåê + VB_INTEGRATOR_40T, //e. output of integral of the PD of the dither drive for 40 periods //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 40 ïåðèîäîâ + WP_PHASE_DETECTOR //e. output of the PD of the CPLC regulator //r. âûõîä ôàçîâîãî äåòåêòîðà êîíòóðà ÑÐÏ +} WATCH_MODE; + +//e. ===== device operation modes ================================================================ //r. ===== ðåæèìû ðàáîòû ïðèáîðà ================================================================ +#define DM_INT_10KHZ_LATCH 1 //e. mode of internal latch 10 kHz //r. ðåæèì âíóòðåííåé çàùåëêè 10 êÃö +#define DM_INT_LATCH_DELTA_PS 2 +#define DM_INT_LATCH_DELTA_BINS 3 +#define DM_EXT_LATCH_DELTA_PS_PULSE 4 //e. mode of external latch with output of the Delta_PS command by pulse //r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_PS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_BINS_PULSE 6 //e. mode of external latch with output of the Delta_BINS command by pulse//r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_BINS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_SF_PULSE 7 //e. mode of Delta Scale factor //r. ðåæèì Delta_SF command + + //e. *** the BLOCK of VARIABLES, LOADED from FLASH-memory ********************** //r. *** ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè ********************** + //e. Address (parameter number in the block = 0..255 ) //r. Àäðåñ (Íîìåð ïàðàìåòðà â áëîêå = 0..255) +typedef union + { + int Array[171]; + struct + { // Device_blk + int My_Addres; //e. 0 - device own address //r.0 - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HFO regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + int HF_ref; //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + int HF_scl; //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int HF_min; //e. 3 - minimum of the output value on the regulator DAC (appropriate to maximal voltage on the HFO) //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + int HF_max; //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + + //e. =============== parameters of the regulator of the DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + int RI_ref; //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + int RI_scl; //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + int WP_ref; //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + int WP_scl; //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int WP_mdy; //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + int WP_rup; //e. 10 - upper value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + int WP_rdw; //e. 11 - lower value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + int VB_phs; //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + int VB_scl; //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà +unsigned int VB_N; //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ +unsigned int VB_Nmin; //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà +unsigned int VB_Nmax; //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + + int VB_Fdf_Hi; //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) +unsigned int VB_Fdf_Lo; //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + + int VB_Fsc; //e. 19 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmin; //e. 20 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmax; //e. 21 - maximum of the output value of the regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau +unsigned int VB_tau; //e. 22 - pulse width of the dither drive (without noise)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + int VBN_Tzd; //e. 23 - adjusted noise period //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ + int VBN_Ran; //e. 24 - range of the random component of noise //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + int VBN_k; //e. 25 - adjusted noise constant //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + int PI_Fsc; //_ //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + int PI_Fb0; //_ //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + int PI_scl; //_ //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + int PI_bia; //_ //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + int PI_a0; //_ // 30 + int PI_a1; //_ // 31 + int PI_a2; //_ // 32 + int PI_a3; //_ // 33 + int PI_a4; //_ // 34 + int PI_a5; //_ // 35 + int PI_a6; //_ // 36 + int PI_b1; //_ // 37 + int PI_b2; //_ // 38 + int PI_b3; //_ // 39 + int PI_b4; //_ // 40 + int PI_b5; //_ // 41 + int PI_b6; //_ // 42 + + //e. =============== parameters of normalization of the temperature sensors ============= //r. =============== ïàðàìåòðû íîðìèðîâêè äàò÷èêîâ òåìïåðàòóðû ============= + + int Tmp_bias[6]; //_ //e. 43 - an array of shifts of the 0..5 temperature sensors //r. 43 - ìàññèâ ñäâèãîâ òåìïåðàòóðíûõ äàò÷èêîâ 0..5 + int Tmp_scal[6]; //_ //e. 49 - an array of the scale coefficients of temperature sensors//r. 49 - ìàññèâ ìàñøòàáíûõ ê-òîâ òåìïåðàòóðíûõ äàò÷èêîâ + int WP_reset; //e. 55 - initial position of the CPLC regulator (after reset) //r. 55 - èñõîäíîå ïîëîæåíèå ðåãóëÿòîðà ÑÐÏ (ïîñëå ñáðîñà) + + //e. ================ gain factor of photodetector channels =========== //r. ================ ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== +unsigned int Gain_Ph_A; //e. 56 - initial gain factor of the A channel of photodetector //r. 56 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà À ôîòîïðèåìíèêà +unsigned int Gain_Ph_B; //e. 57 - initial gain factor of the B channel of photodetector //r. 57 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà B ôîòîïðèåìíèêà + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ (ãàëî÷êà â íàñòîðîå÷íîé ïðîãðàììå) + int Header_Word; //e. 58 - flash sector validity header //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + int LoadFlash_enable; //e. 59 - source loading flag: 1 - load from the flash //r. 59 - ïðèçíàê èñòî÷íèêà çàãðóçêè: 1 - ãðóçèòüñÿ èç flesh + //e. 0 - load default parameters (factory) //r. 0 - ãðóçèòü ïàðàìåòðû ïî óìîë÷àíèþ (çàâîäñêèå) +unsigned int Device_SerialNumber; //e. 60 - serial number of the device //r. 60 - ñåðèéíûé íîìåð ïðèáîðà + int Reserved0; //e. 61 - not used + TERMO_MODE TermoMode; //e 62 - device operation mode (with thermocompenstion, without it, debug )//r. 62 - ðåæèì ðàáîòû ïðèáîðà (ñ òåðìîêîìïåíñàöèåé, áåç íåå èëè îòëàäêà) +//e. addition for the piecewise-linear termocorrection //r. äîáàâëåíèå äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîððåêöèè + int TemperInt[TERMO_FUNC_SIZE]; //e. 63 + float TermoFunc[TERMO_FUNC_SIZE]; //e. 77 + int WP_reset2; //e. 91 - voltages of CPLC regulator reset at cooling //r. xx - íàïðÿæåíèÿ îáíóëåíèÿ êîíòóðà ÑÐÏ ïðè îõëàæäåíèè + //e. parameters setting termocompensation parameters in dynamics (at heating and cooling) //r. ïàðàìåòðû, çàäàþùèå ïàðàìåòðû òåðìîêîìïåíñàöèè â äèíàìèêå (ïðè íàãðåâå è îõëàæäåíèè) + float Reserved1; //e. 92 - not used + float Reserved2; //e. 93 - not used + int K_vb_tu; //e. 94 - slope of dependence of the VB_N division factor from temperature (as though Hz/degree, but in relative units ) //r. êðóòèçíà çàâèñèìîñòè êîýôôèöèåíòà äåëåíèÿ VB_N îò òåìïåðàòóðû (êàê áû Ãö/ãðàäóñ, íî â ó.å.) + int TemperNormal; //e. 95 -temperature for which the VB_N division factor of the dither drive is set //r. òåìïåðàòóðà, äëÿ êîòîðîé çàäàí êîýôôèöèåíò äåëåíèÿ âèáðîïðèâîäà VB_N + int K_WP_rst_heating; //r. 96 - êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè íàãðåâàíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int K_WP_rst_cooling; //e. 97 - slope of dependence of a reset voltage at cooling from temperature (as though Volt/degree, but in relative units of DAC and temperature sensors) //r. êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè îõëàæäåíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int WP_transition_step; //e. 98 - step of change of a heater voltage at resetting //r. øàã èçìåíåíèÿ íàïðÿæåíèÿ íàãðåâàòåëÿ ïðè âûïîëíåíèè îáíóëåíèÿ + int Reserved3; // e. 99 -not used + int HF_scl_2; //r. 100 - êîýôôèöèåíò ïåðåäà÷è (1.15) êîíòóðà ÃÂ× ïðè îáíóëåíèè + int TemperIntDyn[TERMO_FUNC_SIZE]; //e. 114 - + float ThermoHeatDelta[TERMO_FUNC_SIZE]; //e. 128 - + int DeltaTempRecalc; //r. 129 - òåìïåðàòóðíûé èíòåðâàë ïåðåñ÷åòà äèíàìè÷. êîìïåíñàöèè (â ó.å.) //e. temperature delta for dynamic thermocompensation recalculation(in relative units) + int TemperCoolIntDyn[TERMO_FUNC_SIZE]; // e. 143 - + float ThermoCoolDelta[TERMO_FUNC_SIZE]; //e. 157 - + } Str; +} TDEVICE_BLK; + + +//e. ************ end of the BLOCK of VARIABLES, LOADED from FLASH-memory ************ //r. ************ êîíåö áëîêà çàãðóæàåìûõ èç ôëýø-ïàìÿòè ïàðàìåòðîâ ÃËÄ ************ +extern TDEVICE_BLK Device_blk; //e. the BLOCK of VARIABLES, LOADED from FLASH-memory //r. ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè + +extern int Device_Mode; +extern unsigned Valid_Data; + +extern unsigned ser_num; + +extern int VB_Nmin0; //e. minimum of the output value of a regulator of the period for the Device_blk.TemperNormal temperature //r. ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal +extern int VB_Nmax0; //e. maximum of the output value of a regulator of the period for the Device_blk.TemperNormal //r. ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal + +extern unsigned BIT_number; +extern unsigned Is_BIT; + +extern unsigned start_Rq; //e. request for device starting //r. çàïðîñ íà çàïóñê ïðèáîðà +extern unsigned stop_Rq; //e. request for device stopping //r. çàïðîñ íà îñòàíîâ ïðèáîðà +extern unsigned pulse_Rq; //e. request for light-up of laser //r. çàïðîñ íà ïîäæèã ëàçåðà + + //e. *** Default device parameters ********************** //r. *** Ïðèáîðíûå ïàðàìåòðû ïî óìîë÷àíèþ ********************** +#define DEVICE_SN 1 //e. device serial number = 01 //r. ñåðèéíûé íîìåð ïðèáîðà = 01 +#define My_Addres_const 0 //e. - device own address //r. - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HF regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + #define HF_REF_CONST 15080 //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + #define HF_SCL_CONST 1 // 0x64 //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define HF_MIN_CONST -32668 //e. 3 - minimum of the output value on the regulator DAC (appropriate to maximal voltage on the HFO) //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + #define HF_MAX_CONST -17379 //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + #define HFO_SHIFT 16 //e. number of digits of fractional part in 32-bit variable of the hf_reg32 varaible //r. ÷èñëî ðàçðÿäîâ äðîáíîé ÷àñòè â 32-õáèòîâîé ïåðåìåííîé hf_reg32 + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + #define WP_REF_CONST 5 //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + #define WP_SCL_CONST 5 //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define WP_MDY_CONST 30 //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + #define WP_RUP_CONST 31936 //e. 10 - lower value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - íèæíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + #define WP_RDW_CONST 11801 //e. 11 - upper value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + #define VB_PHS_CONST 4 //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + #define VB_SCL_CONST 1024 //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà + #define T_VIB_START 16600 //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ + //e. _VB_N - the initial value of the oscillation period of the dither drive (406Hz-18916, 17067 - 450Hz) //r. _VB_N íà÷àëüíûé ïåðèîä êîëåáàíèé âèáðîïðèâîäà (406Hz-18916, 17067 - 450Hz) + #define T_VIB_DELTA 1000 //e. the range of the oscillation period of the dither drive (~ +/- 10 Hz) //r. äèàïàçîí èçìåíåíèÿ ïåðèîäà êîëåáàíèé âèáðîïðèâîäà (~ +/- 10 Hz) + + #define VB_NMIN_CONST 12080 //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_NMAX_CONST 64000 //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_FDF_HI_CONST 3 //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) + #define VB_FDF_LO_CONST 0 //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + #define VB_FSC_CONST -2000 //e. 19 - the gain factor of the output frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ + #define VB_TMIN_CONST 100 //e. 20 - minimum of the output value of the Tau regulator //r. 20 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define VB_TMAX_CONST 10022 //e. 21 - maximum of the output value of the Tau regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define L_VIB_START 5120 //e. 22 - pulse width of the dither drive (before noiseness)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + //e. _VB_tau - initial pulse width of the dither drive //r. _VB_tau íà÷àëüíàÿ äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà + + #define VBN_TZD_CONST 500 //e. 23 - adjusted noise[??] period (user`s constant) //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + #define VBN_RAN_CONST 400 //e. 24 - range of the random component of noiseness //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + #define VBN_K_CONST 7000 //e. 25 - adjusted noise constant (user`s constant) //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + + //e. =============== parameters of DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + #define RI_REF_CONST 25600 //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + #define RI_SCL_CONST 0 //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + #define PI_FSC_CONST 128 //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + #define PI_FB0_CONST 0 //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + #define PI_SCL_CONST 256 //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + #define PI_BIA_CONST 0 //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + #define PI_A0_CONST 0 // 30 + #define PI_A1_CONST 0 // 31 + #define PI_A2_CONST 0 // 32 + #define PI_A3_CONST 0 // 33 + #define PI_A4_CONST 0 // 34 + #define PI_A5_CONST 0 // 35 + #define PI_A6_CONST 0 // 36 + #define PI_B1_CONST 0 // 37 + #define PI_B2_CONST 0 // 38 + #define PI_B3_CONST 0 // 39 + #define PI_B4_CONST 0 // 40 + #define PI_B5_CONST 0 // 41 + #define PI_B6_CONST 0 // 42 + + #define TMP_SCALE 0x4000 // 43 - 54 Tmp_bias[6]; Tmp_scal[6] + #define TMP_BIAS 0 + #define WP_RESET_CONST 7360 // 55 + #define WP_RESET2_CONST 29216 + #define WP_TRANS_STEP 32767 + //e. ================ initial gain factor of photodetector channels =========== //r. ================ íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== + #define G_PHOTO_STRA 60 // 56 + #define G_PHOTO_STRB 60 // 57 + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ === + #define HEADER_WORD_CONST 0x55aa //e. 58 - magic number flash validity //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + +#define DITHER_REG_PERIOD 40 //e. period of dither regulator (in periods of dither frequency) //r. ïåðèîä ðåãóëèðîâàíèÿ âèáðîïðèîäà (â ïåðèîäàõ âèáðîïðèâîäà) + +#define PLC_RESET_THRESHOLD (-3276) //e. correspond to the voltage +1.2 Volts //r. ñîîòâåòñòâóåò íàïðÿæåíèþ +1.2 âîëüòà + + //e. minimal allowable output frequency, at which data are considered authentic //r. ìèí.äîïóñòèìàÿ ÷àñòîòà ðàñùåïëåíèÿ, ïðè êîò. äàííûå ñ÷èòàþòñÿ äîñòîâåðíûìè +#define F_RAS_MIN 10000 //e. minimal output frequency at start //r. ìèíèìàëüíàÿ ÷àñòîòà ðàñùåïëåíèÿ ïðè ñòàðòå +#define F_OUT_MIN (5000>>4) // 5000 Ãö / 16 +#define F_OUT_NORM (70000>>4) // 90000 Ãö / 16 +#define F_OUT_MAX (300000>>4) // 300000 Ãö / 16 + +#define Set_LightUp LPC_GPIO0->FIOSET = (1<<4) //set light up signal +#define Reset_LightUp LPC_GPIO0->FIOCLR = (1<<4) //reset light up signal + + //e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +#define VALID_START_4SEC 3 //e. time after start, when temperature came authentic //r. âðåìÿ ïîñëå ñòàðòà, êîãäà òåìïåðàòóðà ñòàëà äîñòîâåðíîé + +#define N_START_MAX 1 // 4 //e. count of attempts of device starting //r. ÷èñëî ïîïûòîê çàïóñêà ïðèáîðà +#define LIGHT_UP_PULSE_WDTH 5000 //1000 //e. width of light-up pulse = 100 msec +#define LIGHT_UP_PAUSE 1000 //e. pause after light-up = 100 msec +#define LIGHT_UP_POLLING 10000 //e. time of waiting laser generation = 1 sec + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define TS_MIN -2500 // minimal temperature for our thermal sensors +#define TS_MAX +13000 // maximal temperature for our thermal sensors +#define TS_DIFF_MAX 1300 // maximal difference between 2 thermal sensors + +#define HFO_NEG_MIN 8738 // -4.5 V +#define HFO_NEG_MAX 25122 // -10.5 V +#define HFO_POZ_MIN -32221 // +10.5 V +#define HFO_POZ_MAX -15837 // +4.5 V + +//e. ================ bits of the main register (_RgConA) of GLD control ============== + //r. ================ áèòû îñíîâíîãî ðåãèñòðà óïðàâëåíèÿ GLD (_RgConA) =============== + //e. ================ (bits of the status register) ============================ + //r. ================ (îíè æå - áèòû ðåãèñòðà ñîñòîÿíèÿ) ============================ +#define LASER_ON 0x0001 //e. switch on/off laser-up //r. âêë./âûêë. ãåíåðàöèþ ëàçåðà +#define HF_REG_ON 0x0002 //e. switch on/off the HFO regulator //r. âêë./âûêë. êîíòóð ÃÂ× +#define RI_REG_ON 0x0004 //e. switch on/off the DS power regulator //r. âêë./âûêë. êîíòóð ìîùíîñòè ÄÓÏ +#define WP_REG_ON 0x0008 //e. a mask of switch on/off of the CPLC regulator //r. ìàñêà âêë./âûêë. êîíòóðà ÑÐÏ +#define WP_SIN_ON 0x0010 //e. switch on/off search signal of the CPLC //r. âêë./âûêë. ïîèñêîâûé ñèãíàë ÑÐÏ +#define VB_TAU_ON 0x0020 //e. switch on/off amplitude regulator of the dither drive //r. âêë./âûêë. êîíòóð àìïëèòóäû âèáðîðèâîäà +#define VB_FREQ_ON 0x0040 //e. switch on/off frequency regulator of the dither drive //r. âêë./âûêë. êîíòóð ÷àñòîòû âèáðîïðèâîäà +#define GLD_ON 0x0080 //e. switch on/off all GLD //r. âêë./âûêë. âåñü ÃËÄ + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define loop_is_closed(loop_bit) ((RgConA & (loop_bit)) == loop_bit) +#define close_loop(loop_bit) RgConA |= loop_bit +#define open_loop(loop_bit) RgConA &= ~(loop_bit) + //e. switch off all regulators //r. âûêëþ÷èòü âñå êîíòóðà ðåãóëèðîâàíèÿ +#define open_all_loops() RgConA = 0 +#define close_all_loops() RgConA = 0xFFFF + +extern unsigned SRgR; //e. system register of the ADSP card //r.ñèñòåìíîãî ðåãèñòðà ðåæèìà ïëàòû ADSP + +extern unsigned RgConA; //e. main register of device control //r. îñíîâíîé ðåãèñòð óïðàâëåíèÿ óñòðîéñòâà +extern unsigned RgConB; //e. additional register of device control //r. äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ +//extern unsigned Copy_e5_RgR; //e. copy of the mode register of the E5 card //r. êîïèÿ ðåãèñòðà ðåæèìà ïëàòû E5 +//extern unsigned Copy_e5_RgRA; //e. copy of the additional mode register of the E5 card //r. êîïèÿ äîïîëíèòåëüíîãî ðåãèñòðà ðåæèìà E5 + +void contrl_GLD(void); +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CntrlGLD.h~RF1f7463d.TMP --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CntrlGLD.h~RF1f7463d.TMP Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,328 @@ + +#ifndef DEVICE +#define DEVICE + +//e. constants for the piecewise-linear thermocompensation //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //e. amount of the points of the table function of thermocompensation //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //e. maximal value of order for the thermocompensation coefficients //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //e. number of the temperature sensor used for the thermocompensation //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +typedef enum _TERMO_MODE //e. thermocompensation modes //r. ðåæèìû ðàáîòû òåðìîêîìïåíñàöèè +{ + TERMO_OFF, //e. thermocompensation is switched off //r. òåðìîêîìïåíñàöèÿ âûêëþ÷åíà + TERMO_ON, //e. thermocompensation is switched on //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà + TERMO_ON_NUMB_OFF, //e. thermocompensation is switched on, number resets (debug mode) //r. òåðìîêîìïåíñàöèÿ âêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_STATIC_ONLY, //e. only static thermocompensation is switched on //r. âêëþ÷åíà òîëüêî ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_DYNAMIC_ONLY, //e. only dynamic thermocompensation is switched on //r. âêëþ÷åíà òîëüêî äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿ + TERMO_ON_STATIC_ONLY_NUMB_OFF, //e. static thermocompensation is switched on, number resets (debug mode) //r. ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) + TERMO_ON_DYNAMIC_ONLY_NUMB_OFF //e. dynamic thermocompensation is switched on, number resets (debug mode) //r. äèíàìè÷åñêàÿ òåðìîêîìïåíñàöèÿâêëþ÷åíà, ÷èñëî çàíóëÿåòñÿ (îòëàäî÷íûé ðåæèì) +} TERMO_MODE; + +typedef enum _WATCH_MODE //e. variants of control points for scope //r. âàðèàíòû êîíòðîëüíûõ òî÷åê äëÿ îñöèëëîãðàôà +{ + VB_DELAY_MEANDER, //e. the delayed on the VB_phs meander //r. çàäåðæàííûé ìåàíäð íà âåëè÷èíó VB_phs + VB_PHASE_DETECTOR, //e. output of the PD of the dither drive //r. âûõîä ôàçîâîãî äåòåêòîðà âèþðîïðèâîäà + VB_PHASE_DETECTOR_1_SEC, //e. output of integral of the PD of the dither drive for 1 Sec //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 1 ñåê + VB_INTEGRATOR_40T, //e. output of integral of the PD of the dither drive for 40 periods //r. âûõîä èíòåãðàëà ÔÄ âèáðîïðèâîäà çà 40 ïåðèîäîâ + WP_PHASE_DETECTOR //e. output of the PD of the CPLC regulator //r. âûõîä ôàçîâîãî äåòåêòîðà êîíòóðà ÑÐÏ +} WATCH_MODE; + +//e. ===== device operation modes ================================================================ //r. ===== ðåæèìû ðàáîòû ïðèáîðà ================================================================ +#define DM_INT_10KHZ_LATCH 1 //e. mode of internal latch 10 kHz //r. ðåæèì âíóòðåííåé çàùåëêè 10 êÃö +#define DM_INT_LATCH_DELTA_PS 2 +#define DM_INT_LATCH_DELTA_BINS 3 +#define DM_EXT_LATCH_DELTA_PS_PULSE 4 //e. mode of external latch with output of the Delta_PS command by pulse //r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_PS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_BINS_PULSE 6 //e. mode of external latch with output of the Delta_BINS command by pulse//r. ðåæèì âíåøíåé çàùåëêè ñ âûäà÷åé êîìàíäû Delta_BINS ïî èìïóëüñó +#define DM_EXT_LATCH_DELTA_SF_PULSE 7 //e. mode of Delta Scale factor //r. ðåæèì Delta_SF command + + //e. *** the BLOCK of VARIABLES, LOADED from FLASH-memory ********************** //r. *** ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè ********************** + //e. Address (parameter number in the block = 0..255 ) //r. Àäðåñ (Íîìåð ïàðàìåòðà â áëîêå = 0..255) +typedef union + { + int Array[171]; + struct + { // Device_blk + int My_Addres; //e. 0 - device own address //r.0 - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //e. =============== parameters of HFO regulator =============== //r. =============== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + int HF_ref; //e. 1 - value of the reference //r. 1 - çíà÷åíèå îïîðû + int HF_scl; //e. 2 - the gain factor (1.15) //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int HF_min; //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + int HF_max; //e. 4 - maximum of the output value on the regulator DAC (appropriate to minimal voltage on the HFO) //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + + //e. =============== parameters of the regulator of the DS power regulator ========== //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + int RI_ref; //e. 5 - value of the reference //r. 5 - çíà÷åíèå îïîðû + int RI_scl; //e. 6 - the gain factor (1.15) //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + //e. =============== parameters of the CPLC regulator ===== //r. =============== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + int WP_ref; //e. 7 - value of the reference //r. 7 - çíà÷åíèå îïîðû + int WP_scl; //e. 8 - the gain factor (1.15) //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + int WP_mdy; //e. 9 - value of the reset delay //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + int WP_rup; //e. 10 - upper value of DAC adjustment (appropriate to minimal voltage on the heater) //r. 10 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + int WP_rdw; //e. 11 - lower value of the DAC adjustment (appropriate to maximal voltage on the heater) //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + //e. =============== parameters of the dither drive regulator of the GLD ==================== //r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + int VB_phs; //e. 12 - the phase delay parameter of the dither drive PLL //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + int VB_scl; //e. 13 - the gain factor (1.15) of the dither drive PLL //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà +unsigned int VB_N; //e. 14 - divider for dither drive period (defines dither period) //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ +unsigned int VB_Nmin; //e. 15 - minimum of the output value of the oscillation period regulator //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà +unsigned int VB_Nmax; //e. 16 - maximum of the output value of the oscillation period regulator //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + + int VB_Fdf_Hi; //e. 17 - adjusted output frequency (H) //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) +unsigned int VB_Fdf_Lo; //e. 18 - (L) (double precision) //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + + int VB_Fsc; //e. 19 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmin; //e. 20 - the gain factor of the frequency regulator //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ +unsigned int VB_Tmax; //e. 21 - maximum of the output value of the regulator //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau +unsigned int VB_tau; //e. 22 - pulse width of the dither drive (without noise)//r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + int VBN_Tzd; //e. 23 - adjusted noise period //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ + int VBN_Ran; //e. 24 - range of the random component of noise //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + int VBN_k; //e. 25 - adjusted noise constant //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ + + //e. =============== parameters of processing of accurate data ============= //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + int PI_Fsc; //_ //e. 26 - the S_ds scale parameter //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + int PI_Fb0; //_ //e. 27 - the B_ds zero shift of the DS //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + int PI_scl; //_ //e. 28 - the Scale scale coefficient of the gyro //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + int PI_bia; //_ //e. 29 - the Bias zero shift of the gyro //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //e. =============== coefficients of the temperature correction ================= //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + int PI_a0; //_ // 30 + int PI_a1; //_ // 31 + int PI_a2; //_ // 32 + int PI_a3; //_ // 33 + int PI_a4; //_ // 34 + int PI_a5; //_ // 35 + int PI_a6; //_ // 36 + int PI_b1; //_ // 37 + int PI_b2; //_ // 38 + int PI_b3; //_ // 39 + int PI_b4; //_ // 40 + int PI_b5; //_ // 41 + int PI_b6; //_ // 42 + + //e. =============== parameters of normalization of the temperature sensors ============= //r. =============== ïàðàìåòðû íîðìèðîâêè äàò÷èêîâ òåìïåðàòóðû ============= + + int Tmp_bias[6]; //_ //e. 43 - an array of shifts of the 0..5 temperature sensors //r. 43 - ìàññèâ ñäâèãîâ òåìïåðàòóðíûõ äàò÷èêîâ 0..5 + int Tmp_scal[6]; //_ //e. 49 - an array of the scale coefficients of temperature sensors//r. 49 - ìàññèâ ìàñøòàáíûõ ê-òîâ òåìïåðàòóðíûõ äàò÷èêîâ + int WP_reset; //e. 55 - initial position of the CPLC regulator (after reset) //r. 55 - èñõîäíîå ïîëîæåíèå ðåãóëÿòîðà ÑÐÏ (ïîñëå ñáðîñà) + + //e. ================ gain factor of photodetector channels =========== //r. ================ ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== +unsigned int Gain_Ph_A; //e. 56 - initial gain factor of the A channel of photodetector //r. 56 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà À ôîòîïðèåìíèêà +unsigned int Gain_Ph_B; //e. 57 - initial gain factor of the B channel of photodetector //r. 57 - íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëà B ôîòîïðèåìíèêà + + //e. =============== switch of the source of loading GLD variables block === //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ (ãàëî÷êà â íàñòîðîå÷íîé ïðîãðàììå) + int Header_Word; //e. 58 - flash sector validity header //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + int LoadFlash_enable; //e. 59 - source loading flag: 1 - load from the flash //r. 59 - ïðèçíàê èñòî÷íèêà çàãðóçêè: 1 - ãðóçèòüñÿ èç flesh + //e. 0 - load default parameters (factory) //r. 0 - ãðóçèòü ïàðàìåòðû ïî óìîë÷àíèþ (çàâîäñêèå) +unsigned int Device_SerialNumber; //e. 60 - serial number of the device //r. 60 - ñåðèéíûé íîìåð ïðèáîðà + int Reserved0; //e. 61 - not used + TERMO_MODE TermoMode; //e 62 - device operation mode (with thermocompenstion, without it, debug )//r. 62 - ðåæèì ðàáîòû ïðèáîðà (ñ òåðìîêîìïåíñàöèåé, áåç íåå èëè îòëàäêà) +//e. addition for the piecewise-linear termocorrection //r. äîáàâëåíèå äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîððåêöèè + int TemperInt[TERMO_FUNC_SIZE]; //e. 63 + float TermoFunc[TERMO_FUNC_SIZE]; //e. 77 + int WP_reset2; //e. 91 - voltages of CPLC regulator reset at cooling //r. xx - íàïðÿæåíèÿ îáíóëåíèÿ êîíòóðà ÑÐÏ ïðè îõëàæäåíèè + //e. parameters setting termocompensation parameters in dynamics (at heating and cooling) //r. ïàðàìåòðû, çàäàþùèå ïàðàìåòðû òåðìîêîìïåíñàöèè â äèíàìèêå (ïðè íàãðåâå è îõëàæäåíèè) + float Reserved1; //e. 92 - not used + float Reserved2; //e. 93 - not used + int K_vb_tu; //e. 94 - slope of dependence of the VB_N division factor from temperature (as though Hz/degree, but in relative units ) //r. êðóòèçíà çàâèñèìîñòè êîýôôèöèåíòà äåëåíèÿ VB_N îò òåìïåðàòóðû (êàê áû Ãö/ãðàäóñ, íî â ó.å.) + int TemperNormal; //e. 95 -temperature for which the VB_N division factor of the dither drive is set //r. òåìïåðàòóðà, äëÿ êîòîðîé çàäàí êîýôôèöèåíò äåëåíèÿ âèáðîïðèâîäà VB_N + int K_WP_rst_heating; //r. 96 - êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè íàãðåâàíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int K_WP_rst_cooling; //e. 97 - slope of dependence of a reset voltage at cooling from temperature (as though Volt/degree, but in relative units of DAC and temperature sensors) //r. êðóòèçíà çàâèñèìîñòè íàïðÿæåíèÿ îáíóëåíèÿ ïðè îõëàæäåíèè îò òåìïåðàòóðû (êàê áû âîëüò/ãðàäóñ, íî â ó.å. ÖÀÏ è òåðìîäàò÷èêîâ ) + int WP_transition_step; //e. 98 - step of change of a heater voltage at resetting //r. øàã èçìåíåíèÿ íàïðÿæåíèÿ íàãðåâàòåëÿ ïðè âûïîëíåíèè îáíóëåíèÿ + int Reserved3; // e. 99 -not used + int HF_scl_2; //r. 100 - êîýôôèöèåíò ïåðåäà÷è (1.15) êîíòóðà ÃÂ× ïðè îáíóëåíèè + int TemperIntDyn[TERMO_FUNC_SIZE]; //e. 114 - + float ThermoHeatDelta[TERMO_FUNC_SIZE]; //e. 128 - + int DeltaTempRecalc; //r. 129 - òåìïåðàòóðíûé èíòåðâàë ïåðåñ÷åòà äèíàìè÷. êîìïåíñàöèè (â ó.å.) //e. temperature delta for dynamic thermocompensation recalculation(in relative units) + int TemperCoolIntDyn[TERMO_FUNC_SIZE]; // e. 143 - + float ThermoCoolDelta[TERMO_FUNC_SIZE]; //e. 157 - + } Str; +} TDEVICE_BLK; + + + + + + + + + + + +//e. ************ end of the BLOCK of VARIABLES, LOADED from FLASH-memory ************ //r. ************ êîíåö áëîêà çàãðóæàåìûõ èç ôëýø-ïàìÿòè ïàðàìåòðîâ ÃËÄ ************ +extern TDEVICE_BLK Device_blk; //e. the BLOCK of VARIABLES, LOADED from FLASH-memory //r. ÁËÎÊ ÏÅÐÅÌÅÍÍÛÕ, ÇÀÃÐÓÆÀÅÌÛÕ èç FLASH-ïàìÿòè + +extern int Device_Mode; +extern unsigned Valid_Data; + +extern unsigned ser_num; + +extern int VB_Nmin0; //r. ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal +extern int VB_Nmax0; //r. ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.TemperNormal + +extern unsigned BIT_number; +extern unsigned Is_BIT; + +extern unsigned start_Rq; //r. çàïðîñ íà çàïóñê ïðèáîðà +extern unsigned stop_Rq; //r. çàïðîñ íà îñòàíîâ ïðèáîðà +extern unsigned pulse_Rq; //r. çàïðîñ íà ïîäæèã ëàçåðà + + //r. *** Ïðèáîðíûå ïàðàìåòðû ïî óìîë÷àíèþ *** +#define DEVICE_SN 1 //r. ñåðèéíûé íîìåð ïðèáîðà = 01 +#define My_Addres_const 0 //r. - ñîáñòâåííûé àäðåñ óñòðîéñòâà + + //r. ====== ïàðàìåòðû êîíòóðà Â× ãåíåðàòîðà íàêà÷êè =============== + + #define HF_REF_CONST 15080 //r. 1 - çíà÷åíèå îïîðû + #define HF_SCL_CONST 1 //r. 2 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define HF_MIN_CONST -32668 //r. 3 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà ÃÂ×) + #define HF_MAX_CONST -17379 //r. 4 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ íà ÖÀÏå ðåãóëÿòîðà (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà ÃÂ×) + #define HFO_SHIFT 16 //r. ÷èñëî ðàçðÿäîâ äðîáíîé ÷àñòè â 32-õáèòîâîé ïåðåìåííîé hf_reg32 + + //r. ====== ïàðàìåòðû êîíòóðà ñòàáèëèçàöèè ðàáî÷åãî ïåðèìåòðà (ÑÐÏ) ===== + + #define WP_REF_CONST 5 //r. 7 - çíà÷åíèå îïîðû + #define WP_SCL_CONST 5 //r. 8 - êîýôôèöèåíò ïåðåäà÷è (1.15) + #define WP_MDY_CONST 30 //r. 9 - çíà÷åíèå çàäåðæêè ñáðîñà + #define WP_RUP_CONST 31936 //r. 10 - íèæíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìèíèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + #define WP_RDW_CONST 11801 //r. 11 - âåðõíåå çíà÷åíèå ðåãóëèðîâêè ÖÀÏ (ñîîòâåòñòâóåò ìàêñèì. íàïðÿæåíèþ íà íàãðåâàòåëå) + + +//r. =============== ïàðàìåòðû êîíòóðà âèáðîïðèâîäà ÃËÄ ==================== + + #define VB_PHS_CONST 4 //r. 12 - ïàðàìåòð Phase_çàä. ÑÐ× âèáðîïðèâîäà + #define VB_SCL_CONST 1024 //r. 13 - êîýôôèöèåíò ïåðåäà÷è (1.15) ÑÐ× âèáðîïðèâîäà + #define T_VIB_START 16600 //r. 14 - êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ + //r. _VB_N íà÷àëüíûé ïåðèîä êîëåáàíèé âèáðîïðèâîäà (406Hz-18916, 17067 - 450Hz) + #define T_VIB_DELTA 1000 //r. äèàïàçîí èçìåíåíèÿ ïåðèîäà êîëåáàíèé âèáðîïðèâîäà (~ +/- 10 Hz) + + #define VB_NMIN_CONST 12080 //r. 15 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_NMAX_CONST 64000 //r. 16 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà + #define VB_FDF_HI_CONST 3 //r. 17 - çàäàííàÿ ÷àñòîòà ðàñùåïëåíèÿ (H) + #define VB_FDF_LO_CONST 0 //r. 18 - (L) (äâîéíàÿ òî÷íîñòü) + #define VB_FSC_CONST -2000 //r. 19 - êîýôôèöèåíò ïåðåäà÷è ðåãóëÿòîðà ÷àñòîòû ðàñùåïëåíèÿ + #define VB_TMIN_CONST 100 //r. 20 - ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define VB_TMAX_CONST 10022 //r. 21 - ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà Tau + #define L_VIB_START 5120 //r. 22 - äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà (äî îøóìëåíèÿ) + //r. _VB_tau íà÷àëüíàÿ äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà + + #define VBN_TZD_CONST 500 //r. 23 - çàäàííûé ïåðèîä îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + #define VBN_RAN_CONST 400 //r. 24 - äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé îøóìëåíèÿ VBN_Tsl + #define VBN_K_CONST 7000 //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ (êîíñòàíòà ïîëüçîâàòåëÿ) + + //r. =============== ïàðàìåòðû êîíòóðà ðåãóëèðîâàíèÿ ìîùíîñòè ÄÓÏ ========== + #define RI_REF_CONST 25600 //r. 5 - çíà÷åíèå îïîðû + #define RI_SCL_CONST 0 //r. 6 - êîýôôèöèåíò ïåðåäà÷è (1.15) + + + //r. =============== ïàðàìåòðû îáðàáîòêè òî÷íîñòíîé èíôîðìàöèè ============= + #define PI_FSC_CONST 128 //r. 26 - ìàñøòàáíûé êîýôôèöèåíò Säóï + #define PI_FB0_CONST 0 //r. 27 - ñìåùåíèå íóëÿ ÄÓÏà Bäóï + #define PI_SCL_CONST 256 //r. 28 - ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + #define PI_BIA_CONST 0 //r. 29 - ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + //r. =============== êîýôôèöèåíòû òåìïåðàòóðíîé êîððåêöèè ================= + #define PI_A0_CONST 0 // 30 + #define PI_A1_CONST 0 // 31 + #define PI_A2_CONST 0 // 32 + #define PI_A3_CONST 0 // 33 + #define PI_A4_CONST 0 // 34 + #define PI_A5_CONST 0 // 35 + #define PI_A6_CONST 0 // 36 + #define PI_B1_CONST 0 // 37 + #define PI_B2_CONST 0 // 38 + #define PI_B3_CONST 0 // 39 + #define PI_B4_CONST 0 // 40 + #define PI_B5_CONST 0 // 41 + #define PI_B6_CONST 0 // 42 + + #define TMP_SCALE 0x4000 // 43 - 54 Tmp_bias[6]; Tmp_scal[6] + #define TMP_BIAS 0 + #define WP_RESET_CONST 7360 // 55 + #define WP_RESET2_CONST 29216 + #define WP_TRANS_STEP 32767 +//r. ================ íà÷àëüíûé ê-ò óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà =========== + #define G_PHOTO_STRA 60 // 56 + #define G_PHOTO_STRB 60 // 57 + + //r. =============== ïåðåêëþ÷àòåëü èñòî÷íèêà çàãðóçêè áëîêà ïåðåìåííûõ ÃËÄ === + #define HEADER_WORD_CONST 0x55aa //r. 58 - çàãîëîâîê-êëþ÷ ê èíäèêàòîðó èñòî÷íèêà çàãðóçêè + +#define DITHER_REG_PERIOD 40 //r. ïåðèîä ðåãóëèðîâàíèÿ âèáðîïðèîäà (â ïåðèîäàõ âèáðîïðèâîäà) + +#define PLC_RESET_THRESHOLD (-3276) //r. ñîîòâåòñòâóåò íàïðÿæåíèþ +1.2 âîëüòà + +//r. ìèí.äîïóñòèìàÿ ÷àñòîòà ðàñùåïëåíèÿ, ïðè êîò. äàííûå ñ÷èòàþòñÿ äîñòîâåðíûìè +#define F_RAS_MIN 10000 //r. ìèíèìàëüíàÿ ÷àñòîòà ðàñùåïëåíèÿ ïðè ñòàðòå +#define F_OUT_MIN (5000>>4) // 5000 Ãö / 16 +#define F_OUT_NORM (70000>>4) // 90000 Ãö / 16 +#define F_OUT_MAX (300000>>4) // 300000 Ãö / 16 + +#define Set_LightUp LPC_GPIO0->FIOSET = (1<<4) //set light up signal +#define Reset_LightUp LPC_GPIO0->FIOCLR = (1<<4) //reset light up signal + + //r. êîíñòàíòû äëÿ êóñî÷íî-ëèíåéíîé òåðìîêîìïåíñàöèè +#define TERMO_FUNC_SIZE 14 //r. êîëè÷åñòâî òî÷åê òàáëè÷íîé ôóíêöèè òåðìîêîìïåíñàöèè +#define MAX_ORDER 9 //r. ìàêñèìàëüíàÿ âåëè÷èíà ïîðÿäêà äëÿ êîýôôèöèåíòîâ òåðìîêîìïåíñàöèè +#define TSENS_NUMB 4 //r. íîìåð òåðìîäàò÷èêà, èñïîëüçóåìîãî äëÿ êîìïåíñàöèè + +#define VALID_START_4SEC 3 //r. âðåìÿ ïîñëå ñòàðòà, êîãäà òåìïåðàòóðà ñòàëà äîñòîâåðíîé + +#define N_START_MAX 1 // 4 //r. ÷èñëî ïîïûòîê çàïóñêà ïðèáîðà +#define LIGHT_UP_PULSE_WDTH 5000 //1000 //e. width of light-up pulse = 100 msec +#define LIGHT_UP_PAUSE 1000 //e. pause after light-up = 100 msec +#define LIGHT_UP_POLLING 10000 //e. time of waiting laser generation = 1 sec + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define TS_MIN -2500 // minimal temperature for our thermal sensors +#define TS_MAX +13000 // maximal temperature for our thermal sensors +#define TS_DIFF_MAX 1300 // maximal difference between 2 thermal sensors + +#define HFO_NEG_MIN 8738 // -4.5 V +#define HFO_NEG_MAX 25122 // -10.5 V +#define HFO_POZ_MIN -32221 // +10.5 V +#define HFO_POZ_MAX -15837 // +4.5 V + +//e. ================ bits of the main register (_RgConA) of GLD control ============== + //r. ================ áèòû îñíîâíîãî ðåãèñòðà óïðàâëåíèÿ GLD (_RgConA) =============== + //e. ================ (bits of the status register) ============================ + //r. ================ (îíè æå - áèòû ðåãèñòðà ñîñòîÿíèÿ) ============================ +#define LASER_ON 0x0001 //r. âêë./âûêë. ãåíåðàöèþ ëàçåðà +#define HF_REG_ON 0x0002 //r. âêë./âûêë. êîíòóð ÃÂ× +#define RI_REG_ON 0x0004 //r. âêë./âûêë. êîíòóð ìîùíîñòè ÄÓÏ +#define WP_REG_ON 0x0008 //r. ìàñêà âêë./âûêë. êîíòóðà ÑÐÏ +#define WP_SIN_ON 0x0010 //r. âêë./âûêë. ïîèñêîâûé ñèãíàë ÑÐÏ +#define VB_TAU_ON 0x0020 //r. âêë./âûêë. êîíòóð àìïëèòóäû âèáðîðèâîäà +#define VB_FREQ_ON 0x0040 //r. âêë./âûêë. êîíòóð ÷àñòîòû âèáðîïðèâîäà +#define GLD_ON 0x0080 //r. âêë./âûêë. âåñü ÃËÄ + + // Status word errors bits +#define OUT_FREQ_ERROR 0x8000 +#define DITH_FREQ_ERROR 0x4000 +#define HFO_VOLT_ERROR 0x2000 +#define THERMO_RANGE_ERROR 0x1000 +#define THERMO_DIFF_ERROR 0x0800 + +#define loop_is_closed(loop_bit) ((RgConA & (loop_bit)) == loop_bit) +#define close_loop(loop_bit) RgConA |= loop_bit +#define open_loop(loop_bit) RgConA &= ~(loop_bit) + //r. âûêëþ÷èòü âñå êîíòóðà ðåãóëèðîâàíèÿ +#define open_all_loops() RgConA = 0 +#define close_all_loops() RgConA = 0xFFFF + +extern unsigned SRgR; //r.ñèñòåìíîãî ðåãèñòðà ðåæèìà ïëàòû ADSP + +extern unsigned RgConA; //r. îñíîâíîé ðåãèñòð óïðàâëåíèÿ óñòðîéñòâà +extern unsigned RgConB; //r. äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ +//extern unsigned Copy_e5_RgR; //r. êîïèÿ ðåãèñòðà ðåæèìà ïëàòû E5 +//extern unsigned Copy_e5_RgRA; //r. êîïèÿ äîïîëíèòåëüíîãî ðåãèñòðà ðåæèìà E5 + +void contrl_GLD(void); +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Command.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Command.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,461 @@ +#include "stdlib.h" +#include "lpc17xx.h" +#include "Command.h" +#include "el_lin.h" +#include "vibro.h" +#include "Global.h" +#include "uart_m.h" +#include "CntrlGLD.h" +#include "QEI.h" +#include "InputOutput.h" +#include "SPI.h" +unsigned int Rate_Flag; +unsigned int PC_Comand; +unsigned int n; +unsigned int CountBuFFIn; +unsigned int ParamIn; +unsigned int Err; + unsigned int N=0,CRC_N; + unsigned int Param1=0; + unsigned int Param2=0; + unsigned int Param3=0; + unsigned int Param4=0; + +/* +void exec_CMD(void) //r. === ïðîöåäóðà îêîí÷àòåëüíîé äåøèôðàöèè è èñïîëíåíèÿ êîìàíäû +{ + unsigned int Comand_code; + + //rx_buf_copy = 1; //r. ïðåäóñòàíîâ ôëàãà êîïèðîâàíèÿ ïðèåìíîãî áóôåðà + + Comand_code = (rcv_buf[2] & 0xFF) << 8; + PC_Comand = Comand_code | (rcv_buf[3] & 0xFF); //e. save it in the memory for echo-transmission //r. ñîõðàíèòü åãî â ïàìÿòè äëÿ îáðàòíîé ïåðåäà÷è +}*/ +void CMD_Maintenance(void) +{ + BuffTemp[0] = Main.SOC_Out; + BuffTemp[1] = Main.My_Addres; + BuffTemp[2] = Main.Firmware_Version; + BuffTemp[3] = Main.GLD_Serial; + BuffTemp[4]=0x00; + BuffTemp[5]=0x00; + Check(BuffTemp, 8); + WriteConN (BuffTemp,8); +} + +void CMD_Rate(void) +{ + + unsigned int T_VibH , T_VibL; // ×àñòîòà âèáðîïðèâîäà. + unsigned int Cnt_PlsL , Cnt_PlsH; // Ñ÷åò÷èê +. + unsigned int Cnt_MnsL , Cnt_MnsH; // Ñ÷åò÷èê -. + unsigned int Cnt_DifL , Cnt_DifH; // Ðàçíîñòü ñ÷åò÷èêîâ. + unsigned int F_rasL , F_rasH; // ×àñòîòà ðàñùåïëåíèÿ. + + unsigned int HF_regL , HF_regH; // Âûõîä ðåãóëÿòîðà ÃÂ×. ÍÅ ÑÄÅËÀÍÎ + unsigned int HF_difL , HF_difH; // Ñèãíàë îøèáêè ðåãóëÿ÷òîðà ÃÂ×. ÍÅ ÑÄÅËÀÍÎ + + unsigned int WP_regL , WP_regH; + + unsigned int ADC1L, ADC2L, ADC3L, ADC4L, ADC5L; + unsigned int ADC1H, ADC2H, ADC3H, ADC4H, ADC5H; + + + LoopOn +// Main.T_Vib=(unsigned int)((7680000*16/Main.Frq)*4096); + Main.T_Vib=(unsigned int)((7680000*16/(Main.Frq>>12))); + Main.Firmware_Version=0xff; /// ïðîìåæóòî÷íàÿ çàòû÷êà + + T_VibH = ( Main.T_Vib>>8 ) TakeByte; + T_VibL = ( Main.T_Vib ) TakeByte; + + Cnt_PlsH = ( Main.Cnt_Pls>>8) TakeByte; + Cnt_PlsL = ( Main.Cnt_Pls ) TakeByte; + + Cnt_MnsH = ( Main.Cnt_Mns>>8) TakeByte; + Cnt_MnsL = ( Main.Cnt_Mns ) TakeByte; + + Cnt_DifH = ( Main.Cnt_Dif>>8) TakeByte; + Cnt_DifL = ( Main.Cnt_Dif ) TakeByte; + + F_rasH = ( Main.F_ras>>8 ) TakeByte; + F_rasL = ( Main.F_ras ) TakeByte; + + ADC1H = ( Spi.ADC1>>8 ) TakeByte; + ADC1L = ( Spi.ADC1 ) TakeByte; + + ADC2H = ( Spi.ADC2>>8 ) TakeByte; + ADC2L = ( Spi.ADC2 ) TakeByte; + + ADC3H = ( Spi.ADC3>>8 ) TakeByte; + ADC3L = ( Spi.ADC3 ) TakeByte; + + ADC4H = ( Spi.ADC4>>8 ) TakeByte; + ADC4L = ( Spi.ADC4 ) TakeByte; + + ADC5H = ( Spi.ADC5>>8 ) TakeByte; + ADC5L = ( Spi.ADC5 ) TakeByte; + + WP_regH = ( Spi.DAC_B>>8 ) TakeByte; + WP_regL = ( Spi.DAC_B ) TakeByte; + + HF_regH=0xff; + HF_regL=0xff; + + HF_difH=0xff; + HF_difL=0xff; + + + BuffTemp[ 0] = Main.SOC_Out; + BuffTemp[ 1] = Main.My_Addres; + + BuffTemp[ 2] = Cnt_PlsH;//ñòàðøèé áàéò ñ÷åò÷èêà +. + BuffTemp[ 3] = Cnt_PlsL;//ìëàäøèé áàéò ñ÷åò÷èêà +. + + BuffTemp[ 4] = Cnt_MnsH;//ñòàðøèé áàéò ñ÷åò÷èêà -. + BuffTemp[ 5] = Cnt_MnsL;//ìëàäøèé áàéò ñ÷åò÷èêà -. + + BuffTemp[ 6] = Cnt_DifH;//ñòàðøèé áàéò ðàçíîñòè ñ÷åò÷èêîâ + BuffTemp[ 7] = Cnt_DifL;//ìëàäøèé áàéò ðàçíîñòè ñ÷åò÷èêîâ + + BuffTemp[ 8] = F_rasH; + BuffTemp[ 9] = F_rasL; + + BuffTemp[10] = HF_regH; + BuffTemp[11] = HF_regL; + + BuffTemp[12] = HF_difH; + BuffTemp[13] = HF_difL; + + BuffTemp[14] = T_VibH ;// + BuffTemp[15] = T_VibL; //? + + BuffTemp[16] = Main.Firmware_Version;//ÕÇ + BuffTemp[17] = Main.Firmware_Version;//ÕÇ + + BuffTemp[18] = T_VibH>>1; + BuffTemp[19] = T_VibL; + + BuffTemp[20] = Main.Firmware_Version;//ÕÇ + BuffTemp[21] = Main.Firmware_Version;//ÕÇ + + BuffTemp[22] = WP_regH; //ÑÐÏ Spi.DAC_B + BuffTemp[23] = WP_regL; //ÑÐÏ + + BuffTemp[24] = Main.Firmware_Version;// ÕÇ + BuffTemp[25] = Main.Firmware_Version;// ÕÇ + + BuffTemp[26] = ADC1H; + BuffTemp[27] = ADC1L; + + BuffTemp[28] = ADC1H; + BuffTemp[29] = ADC1L; + + BuffTemp[30] = ADC1H; + BuffTemp[31] = ADC1L; + + BuffTemp[32] = ADC1H; + BuffTemp[33] = ADC1L; + + BuffTemp[34] = ADC1H; + BuffTemp[35] = ADC1L; + + BuffTemp[36] = 0x00;//ADC6 + BuffTemp[37] = 0x00;//ADC6 + + BuffTemp[38] = Main.Firmware_Version; + BuffTemp[39] = Main.Firmware_Version; + BuffTemp[40] = Main.Firmware_Version; + BuffTemp[41] = Main.Firmware_Version; + + + Check(BuffTemp, 44); + WriteConN (BuffTemp,44); + LoopOff +} + +void CMD_M_Control_D8()///óñòàíîâêà\ñáðîñ ðåãèñòðîâ óïðàâëåíèÿ +{ + int bit,NReg; + BuffTemp[0] = Main.SOC_Out; //DD + BuffTemp[1] = Main.My_Addres; //00 + BuffTemp[2] = Main.CMD_In; //D8 + //10? + if((Param1&0x80)) + { + bit=1; + } + else + { + bit=0; + } + + if ((Param1 & 0x10) == 0) + { + NReg=0; + switch(Param1&0xf) // Main.RgConA + { + case 0x0: + Main.RgConA|=bit; + break; + + case 0x1: + Main.RgConA|=bit<<0x1; + break; + + case 0x2: + Main.RgConA|=bit<<0x2; + break; + + case 0x3: + Main.RgConA|=bit<<0x3; + break; + + case 0x4: + Main.RgConA|=bit<<0x4; + break; + + case 0x5: + Main.RgConA|=bit<<0x5; + break; + + case 0x6: + Main.RgConA|=bit<<0x6; + break; + + case 0x7: + Main.RgConA|=bit<<0x7; + break; + } + BuffTemp[3] = NReg<<4; + BuffTemp[4] = (Main.RgConA>>8 )& 0xff; + BuffTemp[5] = Main.RgConA & 0xff; + } + else + { + NReg=1; // Main.RgConB + switch(Param1&0xf) // Main.RgConB + { + case 0x0: + Main.RgConB|=bit; + break; + case 0x1: + Main.RgConB|=bit<1; + break; + case 0x2: + Main.RgConB|=bit<2; + break; + } + BuffTemp[3] = NReg<<4; + BuffTemp[4] = (Main.RgConB>>8 ) & 0xff; + BuffTemp[5] = Main.RgConB & 0xff; + } + + Check(BuffTemp, CRC_N); + WriteConN (BuffTemp,CRC_N); +} + + void CMD_M_Control_D9()///÷òåíèå ðåãèñòðîâ óïðàâëåíèÿ + { + int bit,NReg; + BuffTemp[0] = Main.SOC_Out; //DD + BuffTemp[1] = Main.My_Addres; //00 + BuffTemp[2] = Main.CMD_In; //D9 + if ((Param1 & 0x10) == 0) + { + BuffTemp[3]=0<<4; + BuffTemp[4] = (Main.RgConA>>8 )& 0xff; + BuffTemp[5] = Main.RgConA & 0xff; + } + else + { + BuffTemp[3]=1<<4; + BuffTemp[4] = (Main.RgConB>>8 ) & 0xff; + BuffTemp[5] = Main.RgConB & 0xff; + } + Check(BuffTemp, CRC_N); + WriteConN (BuffTemp,CRC_N); + } +// (íîìåð (êîä) ÖÀÏà 0...3, ñòàðøèé áàéò òðåáóåìîãî ÖÀÏà, ìëàäøèé áàéò òðåá ÖÀÏà) +void CMD_M_Stymul() +{ + int temp; + temp =((BuffTemp[4]<<8) | BuffTemp[5]); + // temp=0; + temp=temp&0xFFFF; + DACF =(temp*K_DAC)+deltaDAC; + Spi.DAC_B =(unsigned int)(DACF) /*(unsigned int)(temp*K_DAC+deltaDAC)*/; // K_DAC); + + //int temp; +// temp =((BuffTemp[4]<<8) | BuffTemp[5]); + //temp = 65535 - temp; + /*if(temp<1000) + { + temp=0; + } + else if(temp>60000) + { + temp=65535; + }*/ + //Spi.DAC_B =(((BuffTemp[4]<<8) | BuffTemp[5])*K_DAC+deltaDAC);/*((BuffTemp[4]<<8) | BuffTemp[5])-0xFFFF*///; //((rcv_buf[4] << 8) | (int)rcv_buf[5]);K_DAC+deltaDAC + //BuffTemp[0] = temp; //DD + //WriteConN (BuffTemp,1); +} + +unsigned int Check(char *c, unsigned int Count) +{ + int i=1; + unsigned int temp,CRC; + + + temp=1; + CRC=0; + + + for(;i<Count-2;i++) + { + CRC+=c[i]; + } + + if(c[Count-2]!=((CRC>>8)&0xFF)) + { + temp=0; + Main.RsErrLine = (Main.RsErrLine)&=0x2; + } + + if(c[Count-1]!=((CRC>>0)&0xFF)) + { + temp=0; +// Main.RsErrLine= (Main.RsErrLine)=0x2; + } + + c[Count-2]=(CRC>>8)&0xFF; + c[Count-1]=(CRC>>0)&0xFF; + + + + return temp; +} + +int Getlengf(void) +{ + unsigned int lengf=0; + switch(Main.CMD_In) + { + case 0x99://maintainance + lengf=6; + CRC_N=8; + break; + + case 0x0A: //m_stymul + lengf=8; + break; + + case 0xA5://DeviceMode + + lengf=6; + CRC_N=8; + break; + + case 0xDD://m_rate + + lengf=6; + CRC_N=44; + break; + + case 0xB0://DeviceMode + + lengf=6; + CRC_N=8; + break; + + case 0xD8://m_control + + lengf=6; + CRC_N=8; + break; + + case 0xD9://m_control + + lengf=6; + CRC_N=8; + break; + } + return lengf; +} + +void Read_CMD(void) +{ + Main.SOC_Out=0xDD; + Main.RsErrLine = (Main.RsErrLine)& 0xffff; + + + CountBuFFIn=ReadChekCon(BuffTemp); + if(CountBuFFIn==1) + { + if (BuffTemp[0] != SOC_In) + { + ReadCon(BuffTemp); + Main.RsErrLine += 0x100;//WriteCon("\n\r ...Error.... "); + BuffTemp[99]=Main.RsErrLine; + } + } + else if(CountBuFFIn==2) + { + if (BuffTemp[1] != Main.My_Addres) + { + ReadCon(BuffTemp); + Main.RsErrLine += 0x1;//WriteCon("\n\r ...Error_ADDRES.... "); + } + } + else if(CountBuFFIn==3) + { + Main.CMD_In=BuffTemp[2]; + N=Getlengf(); + } + + else if(CountBuFFIn==4 && N==6) + { + Param1=BuffTemp[3]; + } + else if((CountBuFFIn==5)&&(N==7)) + { + //LoopOn + Param1=BuffTemp[3]; + Param2=BuffTemp[4]; + + } + else if((CountBuFFIn==6)&&(N==8)) + { + Param1=BuffTemp[3]; + Param2=BuffTemp[4]; + Param3=BuffTemp[5]; + } + else if(CountBuFFIn > (N-1)) + { + ReadCon(BuffTemp); + if(Check(BuffTemp, CountBuFFIn)) + { + switch(Main.CMD_In) + { + case CMD_MAINT: + CMD_Maintenance(); + break; + case 0xD8: + CMD_M_Control_D8(); + case 0xD9: + CMD_M_Control_D9(); + break; + case 0x0A: + CMD_M_Stymul(Param1,Param2,Param3); + break; + case 0xDD: + Rate_Flag=1; + break; + Main.RsErrLine = 0; + } + + } + } +} +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Command.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Command.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,47 @@ + extern unsigned int Err; + extern unsigned int ParamIn; + extern unsigned int Rate_Flag; +#define SOC_In 0xCC //e. attribute of command //r. ïðèçíàê êîìàíäû +//#define SOC_Out 0xDD +#define BROADCAST_ADDRESS 0x1f //e. the broadcasting address ( shared for 3 GLD ) //r. øèðîêîâåùàòåëüíûé àäðåñ (îáùèé äëÿ 3-õ ÃËÄ) + + +#define CMD_DELTA_PS 0xa000 //e. the code of the B_DeltaPS command //r. êîä êîìàíäû B_DeltaPS +#define CMD_DELTA_BINS 0xb000 //e. the code of the B_DeltaBINS command //r. êîä êîìàíäû B_DeltaBINS +#define CMD_DELTA_SF 0xb200 //e. the code of the B_DeltaSF command //r. êîä êîìàíäû B_DeltaSF +#define CMD_DEV_MODE 0xA500 //e. the code of the Device_Mode command //r. êîä êîìàíäû Device_Mode +#define CMD_BIT_MODE 0xA700 //e. the code of the B.I.T. command //r. êîä êîìàíäû B.I.T.(âñòîðîåííîãî òåñòèðîâàíèÿ) +#define CMD_RATE 0x0000 //e. the code of the Rate command //r. êîä êîìàíäû Rate +#define CMD_DELTA 0x0f00 //e. the code of the Delta command //r. êîä êîìàíäû Delta +#define CMD_D_PERIOD_W 0xf000 //e. the code of the D_Period_W command //r. êîä êîìàíäû D_Period_W + +#define CMD_MAINT 0x99 //e. the code of the Maintenance mode command //r. êîä êîìàíäû Maintenance mode + +#define SUBCMD_M_STIMUL 0x0a00 //e. the code of the Stimul command //r. êîä êîìàíäû Stimul +#define SUBCMD_M_RESET 0x8000 //e. software device reset(restart) //r. ïðîãðàììíûé ñáðîñ (ðåñòàðò) ïðèáîðà +#define SUBCMD_M_CLEAR 0xda00 //e. reset of the register of errors of line 485 //r. î÷èñòêà ðåãèñòðà îøèáîê ëèíèè 485 +#define SUBCMD_M_MIRR 0xda01 //e. return previous contents of the receiver buffer //r. âîçâðàò ïðåäûäóùåãî ñîäåðæèìîãî áóôåðà ïðèåìíèêà +#define SUBCMD_M_LDPAR_F 0xda02 //e. load GLD parameters from Flash-memory //r. çàãðóçèòü ïàðàìåòðû ÃËÄ èç ôëýø-ïàìÿòè +#define SUBCMD_M_LDPAR_D 0xda03 //e. set GLD parameters by procedure of initialization //r. óñòàíîâèòü ïàðàìåòðû ÃËÄ ïðîöåäóðîé èíèöèàëèçàöèè +#define SUBCMD_M_START 0xda04 //e. switch on the GLD //r. âêëþ÷èòü ÃËÄ +#define SUBCMD_M_STOP 0xda40 //e. switch off the GLD //r. âûêëþ÷èòü ÃËÄ +#define SUBCMD_M_PULSE 0xda0a //e. generation of the light-up pulse //r. ãåíåðàöèÿ èìïóëüñà ïîäæèãà + +#define SUBCMD_M_CTL_R 0xd900 //e. reading the control register of the device //r. ÷òåíèå ðåãèñòðà óïðàâëåíèÿ óñòðîéñòâà +#define SUBCMD_M_CTL_M 0xd800 //e. modification of bit of the control register //r. ìîäèôèêàöèÿ áèòà ðåãèñòðà óïðàâëåíèÿ +#define SUBCMD_M_RATE 0xdd00 //e. delivery of a stack of parameters M_Rate (Rate2, Rate3) //r. âûäà÷à íàáîðà ïàðàìåòðîâ M_Rate (Rate2, Rate3) + +#define SUBCMD_M_TMP_W 0xe000 //e. writing to the AD7714 circuit (temperature sensors) //r. çàïèñü â ñõåìû AD7714 (èçìåðèòåëè òåìïåðàòóðû) +#define SUBCMD_M_TMP_R 0xe100 //e. reading from the AD7714 circuit (temperature sensors) //r. ÷òåíèå èç ñõåì AD7714 (èçìåðèòåëè òåìïåðàòóðû) +#define SUBCMD_M_E5R_W 0xe200 //e. writing to the register of a mode of the Elio5 card //r. çàïèñü â ðåãèñòð ðåæèìà ïëàòû Elio5 +#define SUBCMD_M_ADC_R 0xe300 //e. reading data from the ADC of the Elio5 card //r. ÷òåíèå äàííûõ èç ÀÖÏ ïëàòû Elio5 +#define SUBCMD_M_VIB_W 0xe400 //e. loading of the oscillation period of the dither drive //r. çàãðóçêà ïåðèîäà êîëåáàíèé âèáðîïðèâîäà +#define SUBCMD_M_CNT_R 0xe500 //e. reading data from the counters of the Elio5 card //r. ÷òåíèå äàííûõ èç ñ÷åò÷èêîâ ïëàòû Elio5 +#define SUBCMD_M_GPH_W 0xe600 //e. loading gain factors of photodetector channels //r. çàãðóçêà êîýôôèöèåíòîâ óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà +#define SUBCMD_M_FLG_R 0xe700 //e. reading data from the register of input flags //r. ÷òåíèå äàííûõ èç ðåãèñòðà âõîäíûõ ôëàãîâ +#define SUBCMD_M_PARAM_W 0xe800 //e. writing working parameter to the data memory //r. çàïèñü ðàáî÷åãî ïàðàìåòðà â ïàìÿòü äàííûõ +#define SUBCMD_M_PARAM_R 0xe900 //e. reading working parameter of the GLD from the data memory //r. ÷òåíèå ðàáî÷åãî ïàðàìåòðà GLD èç ïàìÿòè äàííûõ +#define SUBCMD_M_E5RA_W 0xea00 //e. writing in 1st additional (A) register of a mode of the Elio5 card //r. çàïèñü â 1-ûé äîïîëíèòåëüíûé (À) ðåãèñòð ðåæèìà ïëàòû Elio5 +void Read_CMD(void); +unsigned int Check(char *c, unsigned int Count); +void CMD_Rate(void); \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CyclesSync.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CyclesSync.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,424 @@ + +/**--------------File Info--------------------------------------------------------------------------------- +** File name: CycleSync.c +** Last modified Date: 2011-09-06 +** Last Version: V1.00 +** Descriptions: +** +**-------------------------------------------------------------------------------------------------------- +** Created by: Electrooptica Inc. +** Created date: 2011-09-06 +** Version: V1.00 +** Descriptions: There is the routines for device synchronization +** +**-------------------------------------------------------------------------------------------------------- +*********************************************************************************************************/ +#include "CyclesSync.h" +#include "CntrlGLD.h" +#include "SIP.h" +#include "el_lin.h" +#include "inputOutput.h" + +uint32_t Sys_Clock; //e. counter of system ticks //r. ñ÷åò÷èê âðåìåííîé ñåòêè ñèñòåìû +uint32_t Seconds = 0; //e. seconds from power on //r. ÷èñëî ñåêóíä îò ìîìåíòà âêëþ÷åíèÿ ïèòàíèÿ +int32_t time_1_Sec = DEVICE_SAMPLE_RATE_uks; //e. pseudosecond timer //r. ïñåâäîñåêóíäíûé òàéìåð +uint32_t trm_cycl; +uint32_t count; + int32_t PrevPeriod = 0; +uint32_t num; +volatile uint32_t Latch_Rdy = 0; + + int32_t LatchPhase = INT32_MAX; +uint32_t Ext_Latch_ResetEnable = 1; +volatile uint32_t data_Rdy = 0; + +uint32_t Delay_UART_Enbl = DELAY_UART_ENBL; +//uint32_t Delay_UART_Disbl = DELAY_UART_ENBL; + +uint32_t main_cycle_latch = 0; +uint32_t Out_main_cycle_latch; //e. counter of main cycles between external latch pulse appearence +uint32_t T_latch, Out_T_latch, temp_T_latch; + +/****************************************************************************** +** Function name: Latch_Event +** +** Descriptions: Routine for latch appearing +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void Latch_Event() +{ + static unsigned PreLatch = 0; +// static int cc = 0; + if (LatchPhase < INT32_MAX) //Åñëè LatchPhase(ôëàã çàùåëêè) < ìåíüøå ìàêñèìàëüíîãî 32-õ áèòíîãî èíòà (ïðè èíèöèàëèçàöèè int32_t LatchPhase = INT32_MAX;) òî: + { + Latch_Rdy = 1; //e. óñòàíîâèòü ôëàã äëÿ îáðàáîòêè íèæå + if (RgConB) //Åñëè RgConB (äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ, óñòàíîâëåí â åäåíèöó ïðè èíèöèàëèçàöèè â ìýéíå) óòàíîâëåí â åäåíèöó òî: + { + if (PreLatch) //e. åñëè ìû îòêëàäûâàåì çàùåëêó + PreLatch = 0; + + else if ((LatchPhase < LPC_PWM1->TC) && (num == Sys_Clock)) //e. latch have appeared in current cycle + { + Latch_Rdy = 0; //e. bring it to the next cycle + PreLatch = 1; + } + } + } + else + Latch_Rdy = 0; //e. latch is absent + //---------------------------temp------------------------------- + /* Latch_Rdy = 0; //e. latch is absent + if (cc++ == 19) + { + cc = 0; + Latch_Rdy = 1; + LatchPhase = 2500; + } */ + //----------------------temp-------------------------------- +} + +/****************************************************************************** +** Function name: QEI_IRQHandler +** +** Descriptions: Latch counters by reference meander +** +** parameters: None +** Returned value: None +** +******************************************************************************/ + __irq void QEI_IRQHandler (void) + { + static uint32_t halfQEIPeriod = 0; + + Cnt_curr = LPC_QEI->POS; //e. read accumulated value of counter + if (LPC_QEI->INTSTAT & 0x0008) + { + data_Rdy = 0x0004; //e. data for Cnt_Pls or Cnt_Mns calculation are ready + + if (++halfQEIPeriod & 0x0001) //e. period elapsed, we can calculate Cnt_Dif + { + data_Rdy = 0x000C; + } + } + LPC_QEI->CLR = 0x1fff; //e. reset interrupt request //r. ñáðîñèòü çàïðîñ ïðåðûâàíèÿ + } +/****************************************************************************** +** Function name: SetIntLatch +** +** Descriptions: Set timer for accumulation period +** +** parameters: Period of accumulation +** Returned value: None +** +******************************************************************************/ +void SetIntLatch(uint32_t cycle) +{ + LPC_TIM3->TCR = 0x2; //switch off and reset timer3 + if (cycle != 0) + { + LPC_TIM3->MR0 = (cycle<<2); //load new value + LPC_TIM3->TCR = 1; //switch on timer3 + } +} +/****************************************************************************** +** Function name: SwitchRefMeandInt +** +** Descriptions: Enable/disable interrupt from reference meander +** +** parameters: switcher +** Returned value: None +** +******************************************************************************/ +void SwitchRefMeandInt(uint32_t s) +{ + LPC_QEI->CLR = 0x1fff; //e. reset all interrupts //r. ñáðîñèòü âñå ïðåðûâàíèÿ + if (s) + LPC_QEI->IEC = 0x1fff; //e. disable direction changing interrupt //r. çàïðåòèòü ïðåðûâàíèå ïðè èçìåíåíèè íàïðàâëåíèÿ + else + LPC_QEI->IES = 0x0008; //e. enable direction changing interrupt //r. ðàçðåøèòü ïðåðûâàíèå ïðè èçìåíåíèè íàïðàâëåíèÿ +} +/****************************************************************************** +** Function name: ExtLatch_IRQHandler +** +** Descriptions: Routine for external latch appearence processing +** +** parameters: None +** Returned value: None +** +******************************************************************************/ + __irq void EINT3_IRQHandler (void) + { + //LPC_GPIO2->FIOSET = 0x00000020; //e. turn on the LED + LatchPhase = LPC_PWM1->TC; //e. read moment of latch + LPC_TIM0->TCR = 1; //e. start Mltdrop delay timer + LPC_GPIOINT->IO0IntClr |= 0x0000800;//e. clean interrupt request + //LPC_GPIO2->FIOCLR = 0x00000020; //e. turn off the LED + } + /****************************************************************************** +** Function name: IntLatch_IRQHandler +** +** Descriptions: Routine for Internal latch appearence processing +** +** parameters: None +** Returned value: None +** +******************************************************************************/ + __irq void IntLatch_IRQHandler (void) + { + //LPC_GPIO2->FIOSET |= 0x00000080; // turn on the LED + LatchPhase =(int)LPC_PWM1->TC; //e. read moment of latch + LPC_TIM3->IR = 0x0001; //e. clear interrupt flag + num = Sys_Clock; +// count++; + //LPC_GPIO2->FIOCLR |= 0x00000080; // turn off the LED + } + + /****************************************************************************** +** Function name: SwitchMode +** +** Descriptions: Switch mode of device functionality +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +int SwitchMode() +{ + //-----------------------disable latch sources --------------------- + SetIntLatch(0); //e. disable internal latch + LPC_TIM3->IR = 0x0001; //e. clear internal latch interrupt request + + LPC_GPIOINT->IO0IntEnR &= ~0x0000800; //e. disable external latch + LPC_GPIOINT->IO0IntClr |= 0x0000800; //e. clean external latch interrupt request + + LPC_TIM0->TCR = 2; //e. stop and reset the multidrop delay timer + LPC_TIM0->IR = 0x03F; //e. clear internal latch interrupt request +//----------------------wait while UART and DMA are active------------- + if ( LPC_GPDMACH1->CConfig & DMA_BUSY) //e. if DMA channel is busy, wait //r. åñëè êàíàë ïåðåäà÷è çàíÿò, æäàòü + return 0; + LPC_GPDMACH1->CConfig &= ~DMAChannelEn; //e. disable DMA for UART transmition + LPC_GPDMACH2->CConfig &= ~DMAChannelEn; + + if (!(LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //e. transmit buffer is not empty //r. ïåðåäàþùèé áóôåð íå ïóñò + return 0; + LPC_UART1->FCR |= 0x4; //e. reset TX FIFO + + LPC_TIM0->IR = 0x3F; //e. clear all interrupt flags +//---------------------configure a new exchanging parameters------------ + if (Device_Mode > 3) //e. external latch mode enabled + { + LPC_TIM0->MR0 = 10; + LPC_TIM0->MR1 = 50; //e. /10 = delay before enable signal (us) + // LPC_UART1->FCR &= ~0x08; //e. TX FIFO is not source for DMA request + +// LPC_SC->DMAREQSEL = 0xC; //e. external latch delay timer is source for DMA request +// LPC_GPIOINT->IO0IntEnR |= 0x0000800; //e. enable rising edge interrupt + } + else //e. internal latch mode enabled + { + LPC_TIM0->MR0 = 10; + LPC_TIM0->MR1 = 5000; //e. /10 = delay before enable signal (us) +// LPC_SC->DMAREQSEL = 0x3; //e. FIFO generate DMA request + +// LPC_SC->EXTINT = 0x8; //e. clean interrupt request + } + + UART_SwitchSpeed(SRgR & 0x0030); + + if (Device_Mode == DM_INT_LATCH_DELTA_PS) + SetIntLatch(50000); + return 1; +} + + /****************************************************************************** +** Function name: ServiceTime +** +** Descriptions: Routine for pseudoseconds counting +** +** parameters: None +** Returned value: None +** +******************************************************************************/ + void ServiceTime(void)// ïñåâäîñåêóíäíûé ñ÷åò÷èê. +{ + time_1_Sec -= PrevPeriod; + + if (time_1_Sec < (PrevPeriod>>1)) //1 sec elapsed with accurate 0.5 of main period + { + time_1_Sec = DEVICE_SAMPLE_RATE_uks; + Seconds++; + } + if (Seconds == 3) { Seconds++;close_all_loops();} + Sys_Clock++; //e. increment of the system clock register //r. èíêðåìåíò ðåãèñòðà âðåìåííîé ñåòêè ñèñòåìû + PrevPeriod = LPC_PWM1->MR0; +} // ServiceTime + +/****************************************************************************** +** Function name: WDTFeed +** +** Descriptions: Feed watchdog timer to prevent it from timeout +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void WDTFeed( void ) +{ + LPC_WDT->FEED = 0xAA; /* Feeding sequence */ + LPC_WDT->FEED = 0x55; + return; +} + +/****************************************************************************** +** Function name: CounterIquiryCycle_Init +** +** Descriptions: CounterIquiryCycle_Init setup demanded GPIOs for PWM1, +** reset counter, all latches are enabled, interrupt +** on PWMMR0, install PWM interrupt to the VIC table. +** +** parameters: +** Returned value: +** +******************************************************************************/ +void CounterIquiryCycle_Init(uint32_t cycle) +{ + //PWM1 enabled after reset by default + LPC_SC->PCLKSEL0 &= ~(3<<12); + LPC_SC->PCLKSEL0 |= (1<<12); //PWM1 is synchronized by CCLK (100 MHz)(CCLK) PCLKSEL0 - Peripheral Clock Selection registers. + + LPC_PWM1->TCR = TCR_RESET; /* Counter Reset */ //#define TCR_RESET 0x00000002 èíêðåìåíòèðîâàòü ñ÷åò÷èê ïðè ñïàäåíèè èìïóëüñà ÏÂÌ. + LPC_PWM1->MCR = PWMMR0I |PWMMR0R; //generate interrupt and reset timer counter ( PWMMR0I - ïðåðûâàíèå ãåíåðèðóåòñÿ êîãäà PWMMR0 ñîâïîäàåò ñî çíà÷åíèåì PWMTC. ) + // ( PWMMR0R - ñáðàñûâàåò PWMTC ïðè ñîâïîäåíèè PWMTC è PWMMR0. ) + + LPC_PWM1->CCR = 0x1; //ðàçðåøèòü ïðåðûâàíèå òîëüêî ïðè ñîâïàäåíèè PWMTC ñ PWMMR0 (åùå ÷òî òî ñâÿçàíî ñ çàãðóçêîé ÒÑ) + + + PrevPeriod = 10000; + LPC_PWM1->MR0 = PrevPeriod; /* set PWM cycle */// çàäàíèå ïåðèîäà ñáðîñà ñ÷åò÷èêà. + LPC_PWM1->PCR = PWMENA1; //e. single edge control mode, PWM1 out enabled only âêëþ÷åíèå âûõîäà ØÈÌ 1. + LPC_PWM1->LER = LER0_EN ; //e. enable updating of register + LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN; /* counter enable, PWM enable */ //âêëþ÷åíèå ñ÷åò÷èêà è ØÈÌ + + NVIC_DisableIRQ(PWM1_IRQn);//çàïðåòèòü ïðåðûâàíèå. + + + return ; +} + +__irq void TIMER0_IRQHandler() +{ + int val = LPC_TIM0->IR; + LPC_TIM0->IR |= 3; + + if (val & 1) //MAT 1.0 interrupt + { + LPC_GPIO2->FIOSET |= 1<<6; // turn on the LED + LPC_TIM0->IR |= 1; + return; + } + if (val & 2) //MAT 1.1 interrupt + { + LPC_GPIO2->FIOCLR |= 1<<6; // turn on the LED + LPC_TIM0->IR |= 2; + return; + } + if (val & 4) //MAT 0.2 interrupt + { +// LPC_GPIO0->FIOSET2 |= 0xFF; //set P0.23 +// LPC_GPIO2->FIOSET |= 0x00000040; // turn on the LED +// LPC_TIM0->IR |= 4; + return; + } + return; +} + +/****************************************************************************** +** Function name: ExtLatch_Init +** +** Descriptions: Initialization of external latch +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ExtLatch_Init() +{ + LPC_PINCON->PINSEL4 &= ~0xC000000; //e. èñïîëüçîâàòü P2.13 êàê GPIO. + LPC_PINCON->PINSEL0 &= ~0x0C00000; //e. èñïîëüçîâàòü P0.11 êàê GPIO. + LPC_GPIO0->FIODIR &= ~0x0000800; //e. èñïîëüçîâàòü P0.11 âõëîä. + LPC_GPIOINT->IO0IntEnR &= ~0x0000800; //e. îòêëþ÷èòü âíóòðåííþþ çàùåëêó. + LPC_GPIOINT->IO0IntClr |= 0x0000800; //e. ñáðîñèòü çàïðîñû íà ïðåðûâàíèÿ + + NVIC_EnableIRQ(EINT3_IRQn); // ðàçðåøèòü ïðåðûâàíèÿ. + +//+++++++ initialization of timer for multidrop delay generation+++++++++++++++++++++++ + //e. TIMER0 enabled by default + LPC_SC->PCLKSEL0 &= ~(3<<2); //e. ñáðîñèòü ÷àñòîòó òàéìåðà 0 + LPC_SC->PCLKSEL0 |= (3<<2); //e. óñòàíîâèòü ÷àñòîòó òàéìåðà 0 íà CLK/8. + LPC_TIM0->PR = 0; //e. óñòàíîâèòü äåëèòåëü ÷àñòîòû â 0. + LPC_TIM0->IR = 0x3F; //e. î÷èñòèòü ôëàãè ïðåðûâàíèé. + LPC_TIM0->MCR = 1 |(1<<3)|MR1_RESET |MR1_STOP; //e. ñáðîñèòü è îñòàíîâèòü òàéìåð ïîñëå ñîâïàäåíèÿ MR1 è TC. + LPC_TIM0->CCR = 0; //e. ñîäåðæèìîå òàéìåðà çàãðóæàåòñÿ ïðè ïîÿâëåíèè ïåðåäíåãî ôðîíòà çàùåëêè. + LPC_TIM0->CTCR = 0; //e. timer0 â ðåæèìå òàéìåðà. + + LPC_TIM0->MR0 = /*Device_blk.Address**/10; //e. delay before UART transmitter loading + LPC_TIM0->MR1 = /*Device_blk.Address**/5000; //e. delay before UART transmitter start + //e. set first empty) event of timer + NVIC_DisableIRQ(TIMER0_IRQn); +} +/****************************************************************************** +** Function name: IntLatch_Init +** +** Descriptions: Initialization of iternal latch cycle generation +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void IntLatch_Init() +{ + LPC_SC->PCONP |= (1<<23); //âêëþ÷èò TIME3(òàéìåð) + //e. by default timer3 mode is not counter (T3CTCR[1,0]=0) + + LPC_SC->PCLKSEL1 &= SYNC_CLCK4; // ÷àñòîòà âõîäíîãî ñèãíàëà ðàâíà CLCK/4 + LPC_SC->PCLKSEL1 |= (1<<14); // timer 3 input frequency equal to CLCK/4 + +// LPC_PINCON->PINSEL1 |= (3<<16); //e. CAP 3.1 is connected to P0.24 + //e. by default CAP3.0 is connected to timer3 + LPC_TIM3->PR = 0; //e. óñòàíîâèòü ïðåääåëèòåëü òàéìåðà3 íà 0. + LPC_TIM3->IR = 0x0001; //e. î÷èñòèòü ôëàãè ïðåðûâàíèé. + LPC_TIM3->MCR = MR0_RESET |MR0_INT_EN |MR0_NO_STOP; // óñòàíîâêà ôëàãîâ ïðåðûâàíèé êîòîðûå âûïîëíÿþòñÿ ïðè ñîâïàäåíèè òàéìåðà è ÌÑR. + LPC_TIM3->CCR = 0x0001; //ñîäåðæèìîå ñ÷åò÷èêà çàãðóæàåòñÿ ïî ïðèõîäó ïåðåäíåãî ôðîíòà çàùåëêè. + + NVIC_EnableIRQ(TIMER3_IRQn); //ðàçðåøèòü ïðåðûâàíèÿ. +} +/***************************************************************************** +** Function name: WDTInit +** +** Descriptions: Initialize watchdog timer, install the +** watchdog timer interrupt handler +** +** parameters: None +** Returned value: true or false, return false if the VIC table +** is full and WDT interrupt handler can be +** installed. +** +*****************************************************************************/ +uint32_t WDTInit( void ) +{ + NVIC_DisableIRQ(WDT_IRQn); + + LPC_WDT->TC = WDT_FEED_VALUE; // once WDEN is set, the WDT will start after feeding + LPC_WDT->MOD = WDEN; + + LPC_WDT->FEED = 0xAA; // Feeding sequence + LPC_WDT->FEED = 0x55; + + return 1; +} +/****************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/CyclesSync.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/CyclesSync.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,91 @@ +/**--------------File Info--------------------------------------------------------------------------------- +** File name: CycleSync.h +** Last modified Date: 2011-09-06 +** Last Version: V1.00 +** Descriptions: +** +**-------------------------------------------------------------------------------------------------------- +** Created by: Electrooptica Inc. +** Created date: 2011-09-06 +** Version: V1.00 +** Descriptions: There is the routines for device synchronization +** +**-------------------------------------------------------------------------------------------------------- +*********************************************************************************************************/ +#include "lpc17xx.h" +#include "CntrlGLD.h" + +//#define PERFOMANCE + +#define DEVICE_SAMPLE_RATE_HZ 10000 //e. sampling frequency 10 kHz //r. ÷àñòîòà äèñêðåòèçàöèè 10 êÃö +#define DEVICE_SAMPLE_RATE_uks 100000000 //e. sampling frequency 10 kHz //r. ÷àñòîòà äèñêðåòèçàöèè 10 êÃö +#define DELAY_UART_ENBL 4000 //e. delay = DELAY_UART_ENBL*8/CLCK +#define DELAY_UART_DISBL 2500 //e. delay = DELAY_UART_ENBL*8/CLCK +#define RATE_REPER_OR_REFMEANDR 0x0000 //e. difference of general counters (not dither counters), latched by Reper or by Sign Meander //r. ðàçíîñòü îáû÷íûõ ñ÷åò÷èêîâ (íå âèáðîñ÷), çàùåëêíóòûõ ïî Reper`ó èëè ïî RefMeandr`ó +#define RATE_VIBRO_1 0x0001 //e. difference of dither counters after the filter of moving average //r. ðàçíîñòü âèáðîñ÷åò÷èêîâ ïîñëå ôèëüòðà ñêîëüç.ñðåäíåãî + +#define HALF_PERIOD 0x00000004 +#define WHOLE_PERIOD 0x00000008 +#define RESET_PERIOD 0x0000000C +//-----------------------------PWM Registers---------------------------------------- + +#define TCR_CNT_EN 0x00000001 +#define TCR_RESET 0x00000002 +#define TCR_PWM_EN 0x00000008 + +#define PWMMR0I (1 << 0) +#define PWMMR0R (1 << 1) +#define PWMMR0S (1 << 2) +#define PWMENA1 (1 << 9) +#define LER0_EN (1 << 0) + +//-----------------------Drive cycle registers------------------------------------ +#define MR0_RESET 0x00000002 +#define MR1_RESET 0x00000010 +#define MR1_STOP 0x00000020 +#define MR0_STOP 0x00000004 +#define MR0_NO_STOP 0x00000000 +#define MR0_INT_EN 0x00000001 +#define SYNC_CLCK4 0xffff3fff +#define SYNC_CLCK 0xfffffff + +//------------------------WDT registers-------------------------------------------- +#define WDEN (0x1<<0) +#define WDRESET (0x1<<1) +#define WDTOF (0x1<<2) +#define WDINT (0x1<<3) +#define WDT_FEED_VALUE 0x003FFFFF + +extern uint32_t WDTInit( void ); +extern void WDTFeed( void ); +extern uint32_t Sys_Clock; +extern int32_t time_1_Sec; +extern uint32_t trm_cycl; +extern int32_t PrevPeriod; +extern uint32_t Ext_Latch_ResetEnable; +extern volatile uint32_t Latch_Rdy; +extern volatile uint32_t data_Rdy; +extern int32_t LatchPhase; +extern uint32_t PeriodElapsed; +extern uint32_t count; +extern uint32_t main_cycle_latch; +extern uint32_t Out_main_cycle_latch; //e. counter of main cycles between external latch pulse appearence +extern uint32_t T_latch, Out_T_latch, temp_T_latch; + +extern void CounterIquiryCycle_Init(uint32_t); +extern void ExtLatch_Init(void); +extern void IntLatch_Init(void); +extern void Latch_Event(void); +extern void SetIntLatch(uint32_t); +extern void SwitchRefMeandInt(uint32_t); +extern int SwitchMode(void); + +#if defined PERFOMANCE + void IntLatch(void); +#endif + +void ServiceTime(void); + +/***************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Dither_Reg.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Dither_Reg.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,440 @@ +#include "lpc17xx.h" +#include "mathDSP.h" +#include "InputOutput.h" +#include "CyclesSync.h" +#include "CntrlGLD.h" +#include "stdlib.h" +#include "sip.h" +#include "console.h" + + +#define SHIFT_7680_12500 15 //e. 14 digits for 7680 to 12500 clock converting and 1 division digit +#define SHIFT_C_7680_12500 11 // +#define DITH_VBN_SHIFT 2 //e. //r. îïðåäåëÿåò ñäâèã (äåëåíèå íà 4) êîýôôèöèåíòà äåëåíèÿ âèáðîïðèâîäà, ÷òîáû èìåòü çàïàñ íà ðåãóëèðîâàíèå +#define DITH_VB_TAU_SHIFT 2 + + + + int32_t RI_diff; //e.input signal of "recovery" APS //r. âõîäíîé ñèãíàë "âîññòàíîâëåííîãî" ÄÓÏ + int32_t MaxDelay; + int32_t VB_tau_Ins; //r. âíóòðåííåå çíà÷åíèå êîíòóðà ðåãóëèðîâàíèÿ Òàó + int32_t VB_Nmin0; //r. ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.Str.TemperNormal + int32_t VB_Nmax0; //r. ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.Str.TemperNormal + +uint32_t In_Flag = 0; +uint32_t SwitchCntInq = 0; + + int32_t accum_error = 0; + int32_t ph_error = 0; + int32_t accum_error_old = 0; + int32_t PhaseShift; + int32_t temp2; + int32_t temp3; + +#if defined DITHERSIM + int32_t timeDither = 0; + int32_t LIM0; +#endif +extern uint32_t Vibro_2_CountIn; +void clc_Noise_regulator(void); + +/****************************************************************************** +** Function name: VibroDither_Set +** +** Descriptions: Set period and pulse width for dither. +** +** parameters: duration of vibro pulses, period of dither +** Returned value: None +** +******************************************************************************/ +void VibroDither_Set() +{ +//êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ = T_Vibro äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà>> + + + Device_blk.Str.VB_N = Output.Str.T_Vibro; + LPC_MCPWM->LIM0 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500;//#define SHIFT_7680_12500 15 ñìåøåíèå äëÿ êîíâåðòàöèè ÷àñòîòû èç 7680 â 12500 +#if defined DITHERSIM + 6565 LIM0 = (Output.Str.T_Vibro*86)>>16; +#endif +#if !defined CONSTCYCLE + 5655 SwitchCntInq = 1; //to enable inquiry timer reloading +#endif +} +/****************************************************************************** +** Function name: VibroDither_SwitchOn +** +** Descriptions: VibroDither switching on. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void VibroDither_SwitchOn() +{ + LPC_MCPWM->CON_SET = 1<<8; //start vibro dither +} +/****************************************************************************** +** Function name: VibroDither_SwitchOff +** +** Descriptions: VibroDither switching off. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void VibroDither_SwitchOff() +{ + LPC_MCPWM->CON_CLR = 1<<8; //stop vibro dither +} + +/****************************************************************************** +** Function name: VB_MeanderDelay +** +** Descriptions: Routine for addition of delay to meander +** +** parameters: meander, delay magnitude, max delay +** Returned value: delayed meander +** +******************************************************************************/ +int VB_MeanderDelay(int VB_Meander, int Delay100uS, int MaxDly) +{ + static int poz_counter = 0, neg_counter = 0, flg_delay; + + if (Delay100uS == 0) + { + return (VB_Meander); + } + + if (Delay100uS > 0) + { + if (Delay100uS > MaxDly) { Delay100uS = MaxDly; } + if (VB_Meander) //e. outgoing WP_flg flag, which delayed by the WP_ref //r. ôîðìèðîâàíèå çàäåðæàííîãî íà âåëè÷èíó WP_ref ôëàãà poz_sin_flag + { + neg_counter = 0; + poz_counter++; + } + else + { + poz_counter = 0; + neg_counter++; + } + if (poz_counter == Delay100uS) { flg_delay = 1; } + if (neg_counter == Delay100uS) { flg_delay = 0; } + } + else + { + Delay100uS = -Delay100uS; + if (Delay100uS > MaxDly) { Delay100uS = MaxDly; } + if (VB_Meander) //e. outgoing WP_flg flag, which delayed by the WP_ref //r. ôîðìèðîâàíèå çàäåðæàííîãî íà âåëè÷èíó WP_ref ôëàãà poz_sin_flag + { + neg_counter = MaxDly + 1; + poz_counter--; + } + else + { + poz_counter = MaxDly + 1; + neg_counter--; + } + if (poz_counter == Delay100uS) { flg_delay = 0; } + if (neg_counter == Delay100uS) { flg_delay = 1; } + } + return (flg_delay); +} // VB_MeanderDelay +/****************************************************************************** +** Function name: VB_PhaseDetectorRate +** +** Descriptions: Routine for accumulation of dither error +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +int VB_PhaseDetectorRate(int PhaseDetInput, int IntegrateTime) +{ + + static int SampleAndHoldOut = 0, VB_PhasDet_integr = 0; + + if (IntegrateTime == DEVICE_SAMPLE_RATE_uks) + { + SampleAndHoldOut = VB_PhasDet_integr; + VB_PhasDet_integr = 0; + } + else + { + VB_PhasDet_integr += PhaseDetInput; + } + return (SampleAndHoldOut); +} // VB_PhaseDetectorRate + +/*r. + + DelayedDithMeander - çàäåðæàííûé ìåàíäð (íà âåëè÷èíó VB_phs) +Âûõîä + VB_N - êîýôôèöèåíò äåëåíèÿ +*/ +/****************************************************************************** +** Function name: clc_Dith_regulator +** +** Descriptions: Routine for dither frequency controller +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void clc_Dith_regulator(void) +{ +// static int smooth=0, buf[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, i = 0; +// int ph_error; + static int dith_period = 0;//, accum_error = 0; + + RI_diff = DUP_Filt(Dif_Curr_Vib<<2); + + if (RI_diff >= 0) + ph_error = 1; + else + ph_error = 0; + + if (LPC_MCPWM->INTF & 0x0001) //vibro pulse has been formed + { + LPC_MCPWM->INTF_CLR |= 0x0001; + if (LPC_MCPWM->MAT2 > LPC_MCPWM->MAT1) + { +// LPC_GPIO2->FIOSET = 0x000000FF; // turn on the LED + if (SwitchCntInq) //inquiry cycle duration must be changed + { + LPC_PWM1->MR0 = (Output.Str.T_Vibro*Vibro_2_CountIn)>>SHIFT_C_7680_12500; + LPC_PWM1->LER = LER0_EN ; //e. enable updating of register + SwitchCntInq = 0; + } + LPC_MCPWM->MAT1 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500; + LPC_MCPWM->MAT2 = ((Output.Str.T_Vibro - Output.Str.L_Vibro)*MULT_7680_12500)>>SHIFT_7680_12500; + In_Flag = 0; + } + else + { +// LPC_GPIO2->FIOCLR = 0x000000FF; // turn off the LED + LPC_MCPWM->MAT2 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500; + LPC_MCPWM->MAT1 = ((Output.Str.T_Vibro - Output.Str.L_Vibro)*MULT_7680_12500)>>SHIFT_7680_12500; + In_Flag = 1; + dith_period++; + } + } + + temp3 = VB_MeanderDelay(In_Flag, Device_blk.Str.VB_phs, MaxDelay); //r. ôîðìèðîâàíèå çàäåðæàííîãî ñèãíàëà ìåàíäð + temp2 = ( ( temp3 ^ ph_error ) << 1 ) - 1; //r. àíàëîãîâûé âûõîä XOR ÔÄ(-1..+1, ò.ê. const=1) + accum_error += temp2; + + Output.Str.T_VB_pll = VB_PhaseDetectorRate(temp2, time_1_Sec); //r. ôîðìèðîâàíèå ïðîèíòåãðèðîâàííîãî çà 1 ñåê àíàëîãîâîãî ñèãíàëà ÔÄ âèáðîïðèâîäà + if ( dith_period > DITHER_REG_PERIOD ) //r. ïðîâåðêà ñîñòîÿíèÿ ñ÷åò÷èêà dith_period + { + dith_period = 0; //r. 40 ïåðèîäîâ - îáíóëåíèå ñ÷åò÷èêà ïåðèîäîâ âèáðîïðèâîäà + //r. ìàñøòàáèðîâàíèå è ñóììèðîâàíèå ñ îêðóãëåíèåì è íàñûùåíèåì + if ( loop_is_closed(VB_FREQ_ON) ) + { + Device_blk.Str.VB_N = mac_r(Device_blk.Str.VB_N << (16 - DITH_VBN_SHIFT),-accum_error,Device_blk.Str.VB_scl) << DITH_VBN_SHIFT; + + Saturation(Device_blk.Str.VB_N, Device_blk.Str.VB_Nmax, Device_blk.Str.VB_Nmin); //r. ïðîâåðêà âåðõíåãî äèàïàçîíà ðåãóëèðîâàíèÿ + accum_error = 0; //r. îáíóëåíèå ñóììû _VB_Uab40 + } + } + + if ( loop_is_closed(VB_FREQ_ON) ) //r. ôðîíò áûë, ïðîâåðèòü âêëþ÷åí ëè êîíòóð ñòàáèëèçàöèè + { + Output.Str.T_Vibro = Device_blk.Str.VB_N; + LPC_MCPWM->LIM0 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500; //r. âêëþ÷åí, çàãðóçèòü âû÷èñëåííûå çíà÷åíèÿ ïåðèîäà + } + // cyclic built-in test + if ((Output.Str.T_Vibro > Device_blk.Str.VB_Nmax) || (Output.Str.T_Vibro < Device_blk.Str.VB_Nmin)) + { + Valid_Data |= DITH_FREQ_ERROR; + } +} // clc_Dith_regulator + +/****************************************************************************** +** Function name: clc_OutFreq_regulator +** +** Descriptions: Routine for output frequency controller +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void clc_OutFreq_regulator(void) +{ + static int out_freq_sum = 0; + static int temp; +/* + if (Dif_Curr_Vib > 0) //e. angular speed > 0 //r.ñêîðîñòü ïîëîæèòåëüíà + { + if (RI_diff > 0) + out_freq_sum += (Dif_Curr_Vib - (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + else + out_freq_sum -= (Dif_Curr_Vib - (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + } + else //e. angular speed < 0 //r.ñêîðîñòü îòðèöàòåëüíà + { + if (RI_diff < 0) + out_freq_sum += (Dif_Curr_Vib + (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + else + out_freq_sum -= (Dif_Curr_Vib + (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + } +*/ + if(Dif_Curr_Vib>0) + out_freq_sum += Dif_Curr_Vib; + else + out_freq_sum -= Dif_Curr_Vib; + + + if (time_1_Sec == DEVICE_SAMPLE_RATE_uks) //e. second has elapsed, fix the output frequency value //r. ñåêóíäà ïðîøëà, çàôèêñèðîâàòü çíà÷åíèå ÷àñòîòû ðàñùåïëåíèÿ + { + if (loop_is_closed(VB_TAU_ON)) //e. the regulator loop is closed //r. êîíòóð çàìêíóò + { + temp = Device_blk.Str.VB_Fdf_Hi << 16; + temp |= Device_blk.Str.VB_Fdf_Lo; + temp = L_sub(out_freq_sum, temp) >> 3; // (out_freq_sum - temp) with saturation, then >> 3 + Saturation(temp, 32767, -32768); // error saturation if error is out of range + //e. scaling and summing with rounding and saturation //r. ìàñøòàáèðîâàíèå è ñóììèðîâàíèå ñ îêðóãëåíèåì è íàñûùåíèåì + VB_tau_Ins = mac_r( VB_tau_Ins << (16 - DITH_VB_TAU_SHIFT), + temp, + Device_blk.Str.VB_Fsc ); // << DITH_VB_TAU_SHIFT; + //e. reduction the VB_Err value to 16 digits (arithmetic right shift to 3 digits) //r. ñâåäåíèå âåëè÷èíû VB_Err ê 16 ðàçðÿäàì (àðèôìåòè÷åñêèé ñäâèã âïðàâî íà 3 ðàçðÿäà) + + Saturation(VB_tau_Ins, \ + (int)Device_blk.Str.VB_Tmax >> DITH_VB_TAU_SHIFT, \ + (int)Device_blk.Str.VB_Tmin >> DITH_VB_TAU_SHIFT); //e. checking upper and lower levels in sign range + VB_tau_Ins <<= DITH_VB_TAU_SHIFT; + } + + Output.Str.F_ras = out_freq_sum >> 5; //e. once more divide output frequency by 2, in order to coincide with frequency meter //r. ïîäåëèòü ÷àñòîòó ðàñùåïëåíèÿ åùå íà 2, ÷òîáû ñîâïàëî ñ ÷àñòîòîìåðîì + out_freq_sum = 0; //e. reset accumulated values for next cycle of measurement //r. ñáðîñèòü íàêîïëåííûå çíà÷åíèÿ äëÿ ñëåäóþùåãî öèêëà èçìåðåíèÿ + + // cyclic built-in test + // if output frequency is less than 3/4 of nominal then data is invalid + if (Output.Str.F_ras < ((temp >> 7)*3)) + { + Valid_Data |= OUT_FREQ_ERROR; + } + else + { + Valid_Data &= ~OUT_FREQ_ERROR; + } + } + + clc_Noise_regulator(); + + if ( loop_is_closed(VB_TAU_ON) ) //r. êîíòóð ñòàáèëèçàöèè âêëþ÷åí? + { + Output.Str.L_Vibro = Device_blk.Str.VB_tau; //r. èíà÷å çàãðóçèòü íîâîå çíà÷åíèå + //r. äëèòåëüíîñòè èìïóëüñîâ âèáðîïðèâîäà + } + +} // clc_OutFreq_regulator + +//e. noise regulator //r. ñèñòåìà ýëåêòðîííîãî îøóìëåíèÿ âèáðîïðèâîäà +/*r. +PeriodCount (VBN_Cnt) - ñ÷åò÷èê ïåðèîäîâ ñèãíàëà Meander. +Tnoise (VBN_Per)- òåêóùèé ïåðèîä îøóìëåíèÿ. +PeriodNoise (VBN_Tzd) - ñðåäíèé ïåðèîä îøóìëåíèÿ, çàäàííûé ïîëüçîâàòåëåì. +AmpNoise(VBN_Ran) - ìàêñèìàëüíàÿ àìïëèòóäà ïåðèîäà îøóìëåíèÿ (çàäàåòñÿ ïîëüçîâàòåëåì). +Delta (VBN_k) - ãëóáèíà îøóìëåíèÿ (çàäàåòñÿ ïîëüçîâàòåëåì). +Flag(VBN_Mod) - ôëàã çíàêà èçìåíåíèÿ àìïëèòóäû. +Tu(VBN_Tau) - äëèòåëüíîñòü èìïóëüñà îäíîâèáðàòîðà. +Tp(VBN_tau_Ins) - äëèòåëüíîñòü èìïóëüñà îäíîâèáðàòîðà, çàäàâàåìàÿ ñèñòåìîé ðåãóëèðîâêè ÷àñòîòû ðàñùåïëåíèÿ. +*/ + +void clc_Noise_regulator(void) +{ + int temp; + static uint32_t Flag = 0; + static int PeriodCount = 0, Tnoise = 0; + + if ( PeriodCount >= Tnoise ) + { + PeriodCount = 0; + srand(Device_blk.Str.VB_N);// Srand(ïåðèîä êîëåáàíèé ÂÏ) -èíèöèàëèçàöèÿ ãåíåðàòîðà ñëó÷àéíûõ ÷èñåë ñ çåðíîì (VB_N) + //çàäàííûé ïåðèîä îøóìëåíèÿ + Tnoise = add( Device_blk.Str.VBN_Tzd, mult_r(Device_blk.Str.VBN_Ran, rand())); // Tnoise = Device_blk.Str.VBN_Tzd + MULT_RND_SAT( Device_blk.Str.VBN_Ran, rand() ); + if ( Flag ) //e. calculation +dF/-dF //r. ðàñ÷åò +dF/-dF + { + temp = Device_blk.Str.VBN_k; //r. 25 - çàäàííàÿ êîíñòàíòà îøóìëåíèÿ + } + else + { + temp = -Device_blk.Str.VBN_k; + } + ///Äëèòåëüíîñòü èìïóëüñà äî îøóìëåíèÿ + Device_blk.Str.VB_tau = add(VB_tau_Ins, (mult_r( VB_tau_Ins, temp ) << 1)); // VB_tau = VB_tau_Ins + VB_tau_Ins * temp; with saturation + Saturation(Device_blk.Str.VB_tau, Device_blk.Str.VB_Tmax, Device_blk.Str.VB_Tmin); //e. checking upper and lower levels of control range //r. ïðîâåðêà âåðõíåãî äèàïàçîíà ðåãóëèðîâàíèÿ + Flag = !Flag; + } + else + { + PeriodCount++; + } + +} // clc_Noise_regulator +/****************************************************************************** +** Function name: VibroDither_Init +** +** Descriptions: VibroDither initialization. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void VibroDither_Init() +{ + LPC_SC->PCONP |= 0x00020000; //âêëþ÷åíèå ØÈÌ. + LPC_SC->PCLKSEL1 |= 0xC0000000; //CLK=12.5MHz âûáîð ÷àñòîòû + + /* P1.25,1.26 as PhA_vibro; P1.28,1.29 as PhB_vibro*///âûáîð íîæåê äëÿ äâóõ (òðåõ) êàíàëîâ ØÈÌ(PhA è PhB). + // LPC_PINCON->PINSEL3 &= ~(0x3CF<<18); + // LPC_PINCON->PINSEL3 |= (0x145 << 18) |(1<<6)|(1<<12);//P1.19 - MCOA0; P1.22 - MCOB0; P1.25 - MCOA1; P1.26 - MCOB1; P1.28 - MCOA2; P1.29 - MCOB2; + //âûõîäû ØÈÌ (MCOA è MCOB) ðàçíîé ïîëÿðíîñòè. + + LPC_MCPWM->CON_SET |= 1<<30; //e. set AC mode (Pha, PhB periods are set by LIM0 ) + //ÀÑ ðåæèì (3-õ ôàçíûé ÀÑ ðåæèì) âñå ØÈÌ èñïîëüçóþò + //ñ÷åò÷èê âðåìåíè è ðåãèñòð ïåðèîä êàíàëà 0. + + LPC_MCPWM->TC0 = 0;// èíèöèàëèçàöèÿ (îáíóëåíèå) òàéìåðà 0; + LPC_MCPWM->LIM0 = (Device_blk.Str.VB_N*MULT_7680_12500)>>SHIFT_7680_12500; //ïåðèîä ØÈÌ(Âèðîïðèâîäà). + + LPC_MCPWM->MAT0 = (Device_blk.Str.VB_N*MULT_7680_12500)>>SHIFT_7680_12500; // set LPC_MCPWM->MAT0 for defineteness | óñòàíîâëåíèå âðåìåííûõ èíòåðâàëîâ + LPC_MCPWM->MAT2 = (Device_blk.Str.VB_tau*MULT_7680_12500)>>SHIFT_7680_12500; // pulse width of the PhA dither drive | (MAT) ïðè äîñòèæåíèè êîòîðûõ + LPC_MCPWM->MAT1 = ((Device_blk.Str.VB_N - Device_blk.Str.VB_tau)*MULT_7680_12500)>>SHIFT_7680_12500; // pulse width of the PhB dither drive at first time | òàéìåðîì, ÷òî òî ïðîèñõîäèò. + + LPC_MCPWM->DT &= ~0x3FF; //e. reset dead timer register + LPC_MCPWM->INTEN_SET = 1; //e. enable lim0 interrupt + + LPC_MCPWM->CON_SET |= (1<<8) |1 |(1<<16); //start PWM channel 0,1,2 + + VB_tau_Ins = Device_blk.Str.VB_tau; // VB_tau_Ins - âíóòðåííåå çíà÷åíèå êîíòóðà ðåãóëèðîâàíèÿ Òàó + + Output.Str.L_Vibro = Device_blk.Str.VB_tau; //to update the period and pulse duration for displaying + Output.Str.T_Vibro = Device_blk.Str.VB_N; //çàïèñü â âûõîäíîé ìàñèâ äëèòåëüíîñòè è ïåðèóäà èìïóëüñîâ äëÿ îòîáðàæåíèÿ + return; +} +/****************************************************************************** +** Function name: init_Dither_reg +** +** Descriptions: Initialization of dither regulator. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void init_Dither_reg() +{ + + init_VibroReduce(); // ðàñ÷åò êîýôèöèåíòîâ (âèáðî àïåðòóðû) + Device_blk.Str.VB_N = 29538; //êîýôô.äåëåíèÿ N âèáðîïðèâîäà (ïåðèîä êîëåáàíèé) ÂÏ (? çàäàåòñÿ òîëüêî ñäåñü íî èñïîëüçóåòñÿ óæå ïðè âû÷èñëåíèè Vibro_Filter_Aperture â ïðåäúèäóùåé ôóíêöèè) + VibroDither_Init();// Âûáîð íîæåê äëÿ äâóõ êàíàëîâ ØÈÌ(1-2(Êàíàë 0 òîæå îïðåäåëåí)),ïåðèîä ØÈÌ,ðåæèì è òä. + VibroDither_SwitchOn(); //LPC_MCPWM->CON_SET = 1<<8; ñòàðò òàéìåðà 1. âûñòàâëåíèå 8 áèòà mscon_set èçìåíÿåò 8 áèò â ðåãèñòðå mscon (PDF CTP. - 526) + init_BandPass(1.0/(float)Vibro_Filter_Aperture, 100.0/(float)DEVICE_SAMPLE_RATE_HZ, DUP); //ëèíåéíûé ôèëüòð (òî æå ñàìîå ÷òî è â ÑÐÏ)ïîëîñîôîé ôèëüòð äëÿ âûäåëåíèÿ ÷àñòîòû êîëåáàíèÿ. + MaxDelay = Vibro_Filter_Aperture >> 1; //r. ìàêñ. çàäåðæêà ìåàíäðà âèáðîïðèâîäà (Vibro_Filter_Aperture îïðåäåëÿåòñ â init_VibroReduce();) + CounterIquiryCycle_Init((Device_blk.Str.VB_N*Vibro_2_CountIn)>>SHIFT_C_7680_12500); //çàäàíèå ïåðèîäà ñáðîñà ñ÷åò÷èêà, çàïðåò ïðåðûâàíèÿ. +} +/****************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Dither_Reg.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Dither_Reg.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,12 @@ + + +extern uint32_t L_Vibro; +extern uint32_t T_Vibro; +extern int F_ras; //e. really output frequency, divided by 16 (for transmission) +extern int T_VB_pll; //e. PD output of the frequency regulator of the dither drive //r. âûõîä ÔÄ ðåãóëÿòîðà ÷àñòîòû âèáðîïðèâîäà + + +void init_Dither_reg(void); + +void clc_Dith_regulator(void); +void clc_OutFreq_regulator(void);
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Dither_Regh.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Dither_Regh.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,439 @@ +#include "lpc17xx.h" +#include "mathDSP.h" +#include "InputOutput.h" +#include "CyclesSync.h" +#include "CntrlGLD.h" +#include "stdlib.h" +#include "sip.h" + +//#define FREQ_NEW + +int out_freq_sum = 0; + +#define SHIFT_7680_12500 15 //e. 14 digits for 7680 to 12500 clock converting and 1 division digit +#define SHIFT_C_7680_12500 11 // +#define DITH_VBN_SHIFT 2 //e. //r. îïðåäåëÿåò ñäâèã (äåëåíèå íà 4) êîýôôèöèåíòà äåëåíèÿ âèáðîïðèâîäà, ÷òîáû èìåòü çàïàñ íà ðåãóëèðîâàíèå +#define DITH_VB_TAU_SHIFT 2 + + int32_t RI_diff; //e.input signal of "recovery" APS //r. âõîäíîé ñèãíàë "âîññòàíîâëåííîãî" ÄÓÏ + int32_t MaxDelay; + int32_t VB_tau_Ins; //e. local value of the Tau regulator //r. âíóòðåííåå çíà÷åíèå êîíòóðà ðåãóëèðîâàíèÿ Òàó + int32_t VB_Nmin0; //e. minimum of the output value of a regulator of the period for the Device_blk.Str.TemperNormal temperature //r. ìèíèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.Str.TemperNormal + int32_t VB_Nmax0; //e. maximum of the output value of a regulator of the period for the Device_blk.Str.TemperNormal //r. ìàêñèìóì âûõîäíîãî çíà÷åíèÿ ðåãóëÿòîðà ïåðèîäà äëÿ òåìïåðàòóðû Device_blk.Str.TemperNormal + +uint32_t In_Flag; +uint32_t SwitchCntInq = 0; + + int32_t accum_error = 0; + int32_t ph_error = 0; + int32_t accum_error_old = 0; + int32_t PhaseShift; + int32_t meandr1; + int32_t temp2; + int32_t temp3; + +extern uint32_t Vibro_2_CountIn; + +void clc_Noise_regulator(void); + +/****************************************************************************** +** Function name: VibroDither_Set +** +** Descriptions: Set period and pulse width for dither. +** +** parameters: duration of vibro pulses, period of dither +** Returned value: None +** +******************************************************************************/ +void VibroDither_Set() +{ + Device_blk.Str.VB_N = Output.Str.T_Vibro; + LPC_MCPWM->LIM0 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500; + SwitchCntInq = 1; +} +/****************************************************************************** +** Function name: VibroDither_SwitchOn +** +** Descriptions: VibroDither switching on. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void VibroDither_SwitchOn() +{ + LPC_MCPWM->CON_SET = 1<<8; //start vibro dither +} +/****************************************************************************** +** Function name: VibroDither_SwitchOff +** +** Descriptions: VibroDither switching off. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void VibroDither_SwitchOff() +{ + LPC_MCPWM->CON_CLR = 1<<8; //stop vibro dither +} + +/****************************************************************************** +** Function name: VB_MeanderDelay +** +** Descriptions: Routine for addition of delay to meander +** +** parameters: meander, delay magnitude, max delay +** Returned value: delayed meander +** +******************************************************************************/ +int VB_MeanderDelay(int VB_Meander, int Delay100uS, int MaxDly) +{ + static int poz_counter = 0, neg_counter = 0, flg_delay; + + if (Delay100uS == 0) + { + return (VB_Meander); + } + + if (Delay100uS > 0) + { + if (Delay100uS > MaxDly) { Delay100uS = MaxDly; } + if (VB_Meander) //e. outgoing WP_flg flag, which delayed by the WP_ref //r. ôîðìèðîâàíèå çàäåðæàííîãî íà âåëè÷èíó WP_ref ôëàãà poz_sin_flag + { + neg_counter = 0; + poz_counter++; + } + else + { + poz_counter = 0; + neg_counter++; + } + if (poz_counter == Delay100uS) { flg_delay = 1; } + if (neg_counter == Delay100uS) { flg_delay = 0; } + } + else + { + Delay100uS = -Delay100uS; + if (Delay100uS > MaxDly) { Delay100uS = MaxDly; } + if (VB_Meander) //e. outgoing WP_flg flag, which delayed by the WP_ref //r. ôîðìèðîâàíèå çàäåðæàííîãî íà âåëè÷èíó WP_ref ôëàãà poz_sin_flag + { + neg_counter = MaxDly + 1; + poz_counter--; + } + else + { + poz_counter = MaxDly + 1; + neg_counter--; + } + if (poz_counter == Delay100uS) { flg_delay = 0; } + if (neg_counter == Delay100uS) { flg_delay = 1; } + } + return (flg_delay); +} // VB_MeanderDelay +/****************************************************************************** +** Function name: VB_PhaseDetectorRate +** +** Descriptions: Routine for accumulation of dither error +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +int VB_PhaseDetectorRate(int PhaseDetInput, int IntegrateTime) +{ + + static int SampleAndHoldOut = 0, VB_PhasDet_integr = 0; + + if (IntegrateTime == 0) + { + SampleAndHoldOut = VB_PhasDet_integr; + VB_PhasDet_integr = 0; + } + else + { + VB_PhasDet_integr += PhaseDetInput; + } + return (SampleAndHoldOut); +} // VB_PhaseDetectorRate + +/*r. + + DelayedDithMeander - çàäåðæàííûé ìåàíäð (íà âåëè÷èíó VB_phs) +Âûõîä + VB_N - êîýôôèöèåíò äåëåíèÿ +*/ + +void clc_Dith_regulator(void) +{ +// static int smooth=0, buf[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, i = 0; +// int ph_error; + static int dith_period = 0;//, accum_error = 0; +#if defined FREQ_NEW + static int RI_diff_old = 0; + static int PhaseShift_Old = 0, accum_on = 0; +#endif + RI_diff = DUP_Filt(Dif_Curr_Vib<<2); + + if (RI_diff >= 0) + { + meandr1 = 1; +#if defined FREQ_NEW + if (RI_diff_old < 0) + if (ph_error !=1) + ph_error++; +#else + ph_error = 1; +#endif + } + else + { + meandr1 = 0; +#if !defined FREQ_NEW + ph_error = 0; +#endif + } + + if (LPC_MCPWM->INTF & 0x0001) + { + LPC_MCPWM->INTF_CLR |= 0x0001; + + if (LPC_MCPWM->MAT2 > LPC_MCPWM->MAT1) + { +// LPC_GPIO2->FIOSET = 0x000000FF; // turn on the LED + if (SwitchCntInq) + { + LPC_PWM1->MR0 = (Output.Str.T_Vibro*Vibro_2_CountIn)>>SHIFT_C_7680_12500; + LPC_PWM1->LER = LER0_EN ; //e. enable updating of register + SwitchCntInq = 0; + } + LPC_MCPWM->MAT1 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500; + LPC_MCPWM->MAT2 = ((Output.Str.T_Vibro - Output.Str.L_Vibro)*MULT_7680_12500)>>SHIFT_7680_12500; + In_Flag = 1; +#if defined FREQ_NEW + if (ph_error > (-1)) + ph_error--; +#endif + } + else + { +// LPC_GPIO2->FIOCLR = 0x000000FF; // turn off the LED + LPC_MCPWM->MAT2 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500; + LPC_MCPWM->MAT1 = ((Output.Str.T_Vibro - Output.Str.L_Vibro)*MULT_7680_12500)>>SHIFT_7680_12500; + In_Flag = 0; + dith_period++; + + } + } +#if !defined FREQ_NEW + temp3 = VB_MeanderDelay(In_Flag, Device_blk.Str.VB_phs, MaxDelay); //e. outgoing of the delayed menader signal //r. ôîðìèðîâàíèå çàäåðæàííîãî ñèãíàëà ìåàíäð + temp2 = ( ( temp3 ^ ph_error ) << 1 ) - 1; //e. the PD XOR analog out (-1..+1, since const=1) //r. àíàëîãîâûé âûõîä XOR ÔÄ(-1..+1, ò.ê. const=1) + accum_error += temp2; +#else + if ((ph_error !=0) && (accum_on == 0)) // + { + accum_on = 1; + PhaseShift += ph_error; + } + else if ((ph_error == 0) && (accum_on == 1)) + { + accum_on = 0; + accum_error += (PhaseShift - PhaseShift_Old); + PhaseShift_Old = PhaseShift; + PhaseShift = 0; + } + else + PhaseShift += ph_error; +#endif + Output.Str.T_VB_pll = VB_PhaseDetectorRate(temp2, time_1_Sec); //e. outgoing of the integrated for 1 Sec analog signal of the PD of the dither drive //r. ôîðìèðîâàíèå ïðîèíòåãðèðîâàííîãî çà 1 ñåê àíàëîãîâîãî ñèãíàëà ÔÄ âèáðîïðèâîäà + if ( dith_period > DITHER_REG_PERIOD ) //e. checking status of the dith_period counter //r. ïðîâåðêà ñîñòîÿíèÿ ñ÷åò÷èêà dith_period + { + dith_period = 0; //e. 40 periods - resetting the counter of dither drive periods //r. 40 ïåðèîäîâ - îáíóëåíèå ñ÷åò÷èêà ïåðèîäîâ âèáðîïðèâîäà + //e. scaling and summing with rounding and saturation //r. ìàñøòàáèðîâàíèå è ñóììèðîâàíèå ñ îêðóãëåíèåì è íàñûùåíèåì + Device_blk.Str.VB_N = mac_r(Device_blk.Str.VB_N << (16 - DITH_VBN_SHIFT), + -accum_error, + Device_blk.Str.VB_scl) << DITH_VBN_SHIFT; + + // Saturation(Device_blk.Str.VB_N, Device_blk.Str.VB_Nmax, Device_blk.Str.VB_Nmin); //e. checking upper and lower levels of control range //r. ïðîâåðêà âåðõíåãî äèàïàçîíà ðåãóëèðîâàíèÿ + accum_error = 0; //e. resetting the _VB_Uab40 sum //r. îáíóëåíèå ñóììû _VB_Uab40 + + } + if ( loop_is_closed(VB_FREQ_ON) ) //e. it was, check the activation of the stabilization regulator //r. ôðîíò áûë, ïðîâåðèòü âêëþ÷åí ëè êîíòóð ñòàáèëèçàöèè + { + Output.Str.T_Vibro = Device_blk.Str.VB_N; + LPC_MCPWM->LIM0 = (Output.Str.T_Vibro*MULT_7680_12500)>>SHIFT_7680_12500; //e. has switched on, load calculated values of period //r. âêëþ÷åí, çàãðóçèòü âû÷èñëåííûå çíà÷åíèÿ ïåðèîäà + SwitchCntInq = 1; //e. enable loading counter inquiry timer at the next vibro halfperiod + } + // cyclic built-in test + if ((Output.Str.T_Vibro > Device_blk.Str.VB_Nmax) || (Output.Str.T_Vibro < Device_blk.Str.VB_Nmin)) + { + Valid_Data |= DITH_FREQ_ERROR; + } +} // clc_Dith_regulator + +//e. dither drive output frequency stabilization //r. ñòàáèëèçàöèÿ ÷àñòîòû ðàñùåïëåíèÿ âèáðîïðèâîäà +void clc_OutFreq_regulator(void) +{ +// static int out_freq_sum = 0; + static int temp; + + /* if (Dif_Curr_Vib > 0) //e. angular speed > 0 //r.ñêîðîñòü ïîëîæèòåëüíà + { + if (RI_diff > 0) + out_freq_sum += (Dif_Curr_Vib - (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + else + out_freq_sum -= (Dif_Curr_Vib - (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + } + else //e. angular speed < 0 //r.ñêîðîñòü îòðèöàòåëüíà + { + if (RI_diff < 0) + out_freq_sum += (Dif_Curr_Vib + (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + else + out_freq_sum -= (Dif_Curr_Vib + (int)(Dif_Curr_32 >> SHIFT_TO_FRACT)); + } + */ + if(Dif_Curr_Vib>0) + out_freq_sum += Dif_Curr_Vib; + else + out_freq_sum -= Dif_Curr_Vib; + if (time_1_Sec == 0) //e. second has elapsed, fix the output frequency value //r. ñåêóíäà ïðîøëà, çàôèêñèðîâàòü çíà÷åíèå ÷àñòîòû ðàñùåïëåíèÿ + { + if (loop_is_closed(VB_TAU_ON)) //e. the regulator loop is closed //r. êîíòóð çàìêíóò + { + temp = Device_blk.Str.VB_Fdf_Hi << 16; + temp |= Device_blk.Str.VB_Fdf_Lo; + temp = L_sub(out_freq_sum, temp) >> 3; // (out_freq_sum - temp) with saturation, then >> 3 + Saturation(temp, 32767, -32768); // error saturation if error is out of range + //e. scaling and summing with rounding and saturation //r. ìàñøòàáèðîâàíèå è ñóììèðîâàíèå ñ îêðóãëåíèåì è íàñûùåíèåì + VB_tau_Ins = mac_r( VB_tau_Ins << (16 - DITH_VB_TAU_SHIFT), + temp, + Device_blk.Str.VB_Fsc ); // << DITH_VB_TAU_SHIFT; + //e. reduction the VB_Err value to 16 digits (arithmetic right shift to 3 digits) //r. ñâåäåíèå âåëè÷èíû VB_Err ê 16 ðàçðÿäàì (àðèôìåòè÷åñêèé ñäâèã âïðàâî íà 3 ðàçðÿäà) + + Saturation(VB_tau_Ins, \ + (int)Device_blk.Str.VB_Tmax >> DITH_VB_TAU_SHIFT, \ + (int)Device_blk.Str.VB_Tmin >> DITH_VB_TAU_SHIFT); //e. checking upper and lower levels in sign range + VB_tau_Ins <<= DITH_VB_TAU_SHIFT; + } + + Output.Str.F_ras = out_freq_sum >> 5; //e. once more divide output frequency by 2, in order to coincide with frequency meter //r. ïîäåëèòü ÷àñòîòó ðàñùåïëåíèÿ åùå íà 2, ÷òîáû ñîâïàëî ñ ÷àñòîòîìåðîì + out_freq_sum = 0; //e. reset accumulated values for next cycle of measurement //r. ñáðîñèòü íàêîïëåííûå çíà÷åíèÿ äëÿ ñëåäóþùåãî öèêëà èçìåðåíèÿ + + // cyclic built-in test + // if output frequency is less than 3/4 of nominal then data is invalid + if (Output.Str.F_ras < ((temp >> 7)*3)) + { + Valid_Data |= OUT_FREQ_ERROR; + } + else + { + Valid_Data &= ~OUT_FREQ_ERROR; + } + } + + clc_Noise_regulator(); + + if ( loop_is_closed(VB_TAU_ON) ) //e. is stabilization regulator switched on? //r. êîíòóð ñòàáèëèçàöèè âêëþ÷åí? + { + Output.Str.L_Vibro = Device_blk.Str.VB_tau; //e. otherwise, load new value of //r. èíà÷å çàãðóçèòü íîâîå çíà÷åíèå + //e. pulse width of the dither drive //r. äëèòåëüíîñòè èìïóëüñîâ âèáðîïðèâîäà + } + +} // clc_OutFreq_regulator + +//e. noise regulator //r. ñèñòåìà ýëåêòðîííîãî îøóìëåíèÿ âèáðîïðèâîäà +/*r. +PeriodCount (VBN_Cnt) - ñ÷åò÷èê ïåðèîäîâ ñèãíàëà Meander. +Tnoise (VBN_Per)- òåêóùèé ïåðèîä îøóìëåíèÿ. +PeriodNoise (VBN_Tzd) - ñðåäíèé ïåðèîä îøóìëåíèÿ, çàäàííûé ïîëüçîâàòåëåì. +AmpNoise(VBN_Ran) - ìàêñèìàëüíàÿ àìïëèòóäà ïåðèîäà îøóìëåíèÿ (çàäàåòñÿ ïîëüçîâàòåëåì). +Delta (VBN_k) - ãëóáèíà îøóìëåíèÿ (çàäàåòñÿ ïîëüçîâàòåëåì). +Flag(VBN_Mod) - ôëàã çíàêà èçìåíåíèÿ àìïëèòóäû. +Tu(VBN_Tau) - äëèòåëüíîñòü èìïóëüñà îäíîâèáðàòîðà. +Tp(VBN_tau_Ins) - äëèòåëüíîñòü èìïóëüñà îäíîâèáðàòîðà, çàäàâàåìàÿ ñèñòåìîé ðåãóëèðîâêè ÷àñòîòû ðàñùåïëåíèÿ. +*/ + +void clc_Noise_regulator(void) +{ + int temp; + static uint32_t Flag = 0; + static int PeriodCount = 0, Tnoise = 0; + + if ( PeriodCount >= Tnoise ) + { + PeriodCount = 0; + srand(Device_blk.Str.VB_N); + Tnoise = add( Device_blk.Str.VBN_Tzd, mult_r(Device_blk.Str.VBN_Ran, rand())); // Tnoise = Device_blk.Str.VBN_Tzd + MULT_RND_SAT( Device_blk.Str.VBN_Ran, rand() ); + if ( Flag ) //e. calculation +dF/-dF //r. ðàñ÷åò +dF/-dF + { + temp = Device_blk.Str.VBN_k; + } + else + { + temp = -Device_blk.Str.VBN_k; + } + + Device_blk.Str.VB_tau = add(VB_tau_Ins, (mult_r( VB_tau_Ins, temp ) << 1)); // VB_tau = VB_tau_Ins + VB_tau_Ins * temp; with saturation + Saturation(Device_blk.Str.VB_tau, Device_blk.Str.VB_Tmax, Device_blk.Str.VB_Tmin); //e. checking upper and lower levels of control range //r. ïðîâåðêà âåðõíåãî äèàïàçîíà ðåãóëèðîâàíèÿ + Flag = !Flag; + } + else + { + PeriodCount++; + } + +} // clc_Noise_regulator +/****************************************************************************** +** Function name: VibroDither_Init +** +** Descriptions: VibroDither initialization. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void VibroDither_Init() +{ + LPC_SC->PCONP |= 0x00020000; /* Turn On MCPWM PCLK */ + LPC_SC->PCLKSEL1 |= 0xC0000000; //CLK=12.5MHz + /* P1.25,1.26 as PhA_vibro; P1.28,1.29 as PhB_vibro*/ + LPC_PINCON->PINSEL3 &= ~(0x3CF<<18); + LPC_PINCON->PINSEL3 |= (0x145 << 18) |(1<<6)|(1<<12); + + LPC_MCPWM->CON_SET |= 1<<30; //e. set AC mode (Pha, PhB periods are set by LIM0 ) + + LPC_MCPWM->TC0 = 0; //e. initial time counter of channel 0 + LPC_MCPWM->LIM0 = (Device_blk.Str.VB_N*MULT_7680_12500)>>SHIFT_7680_12500; //e. period of the dither drive + LPC_MCPWM->MAT0 = (Device_blk.Str.VB_N*MULT_7680_12500)>>SHIFT_7680_12500; //e. set LPC_MCPWM->MAT0 for defineteness + LPC_MCPWM->MAT2 = (Device_blk.Str.VB_tau*MULT_7680_12500)>>SHIFT_7680_12500; //e. pulse width of the PhA dither drive + LPC_MCPWM->MAT1 = ((Device_blk.Str.VB_N - Device_blk.Str.VB_tau)*MULT_7680_12500)>>SHIFT_7680_12500; //e. pulse width of the PhB dither drive at first time + + LPC_MCPWM->DT &= ~0x3FF; //e. reset dead timer register + LPC_MCPWM->INTEN_SET = 1; //e. enable lim0 interrupt + + LPC_MCPWM->CON_SET |= (1<<8) |1 |(1<<16); //start PWM channel 0,1,2 + + VB_tau_Ins = Device_blk.Str.VB_tau; + return; +} +/****************************************************************************** +** Function name: init_Dither_reg +** +** Descriptions: Initialization of dither regulator. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void init_Dither_reg() +{ + init_VibroReduce(); + VibroDither_Init(); + VibroDither_SwitchOn(); + init_BandPass(1.0/(float)Vibro_Filter_Aperture, 100.0/(float)DEVICE_SAMPLE_RATE_HZ, DUP); + MaxDelay = Vibro_Filter_Aperture >> 1; //e. maximal delay of the meander of the dither drive //r. ìàêñ. çàäåðæêà ìåàíäðà âèáðîïðèâîäà + CounterIquiryCycle_Init((Device_blk.Str.VB_N*Vibro_2_CountIn)>>SHIFT_C_7680_12500); +} +/****************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Global.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Global.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,25 @@ +#include "Global.h" +#include "CntrlGLD.h" + + +unsigned int VibroReg = 0; //ðåãèñòð ñîñòàÿíèÿ âèáðîïðèâîäà. +unsigned long Global_Time=0, Time_UART=0,Time_Sec=0,Time_vibro=0,Time_1kHz=0; +unsigned long MaxAmp=0; +unsigned char BuffTemp[100]; + void VibroPush(void) + { + VibroReg |= 0x1; + } + void VibroPull(void) + { + VibroReg |= 0x0; + } +void ButtonLightUP(void) +{ + if ((secPuls>100)&&(pulse_Rq==1)) + { + pulse_Rq=0; + LightUpCount=3000; + BackLightCount=5000; + } +} \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Global.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Global.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,17 @@ +#define BackLightOFF LPC_GPIO2->FIOSET =(1<<12); +#define BackLightON LPC_GPIO2->FIOCLR =(1<<12); +#define LightUpON LPC_GPIO0->FIOSET = (1<<4); +#define LightUpOFF LPC_GPIO0->FIOCLR = (1<<4); + +#define TakeByte & 0xFF +#define deltaDAC 11400.857 //íîëü ÖÀÏà +//#define K_DAC 0.843 +extern float DACF, K_DAC; +extern unsigned int VibroReg; +extern void VibroPush(void); +extern void VibroPull(void); +extern void ButtonLightUP(void); +extern unsigned long Global_Time, Time_UART,Time_Sec,Time_vibro,Time_1kHz; +extern unsigned long MaxAmp; +extern unsigned int LightUpCount,BackLightCount,secPuls; +extern unsigned char BuffTemp[];
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/HFO_Reg.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/HFO_Reg.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,68 @@ +#include "mathDSP.h" +#include "InputOutput.h" +#include "CntrlGLD.h" + +#define HFO_NEG_MIN 8738 // -4.5 V +#define HFO_NEG_MAX 25122 // -10.5 V +#define HFO_POZ_MIN -32221 // +10.5 V +#define HFO_POZ_MAX -15837 // +4.5 V + +/****************************************************************************** +** Function name: clc_HFO +** +** Descriptions: Procedure of the HFO regulator +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void clc_HFO() // --- HFO regulator --- +{ + + static int hf_reg = 0; //r. çíà÷åíèå èíòåãðàòîðà â êîíòóðå ÃÂ× + + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + //r. ôèëüòðàöèÿ âûõîäà àìïë. äåòåêòîðà ïåðåä ïåðåäà÷åé â êîíòóð ÃÂ× + /*int HFO_MovAverFilt (int Input) +{ + static __int64 smooth_HF = 0; + + static int buffer_HF[BUF_SIZE]; + + static unsigned i_HF = 0; + + smooth_HF -= buffer_HF[i_HF]; + buffer_HF[i_HF] = Input; + smooth_HF += Input; + + i_HF++; + i_HF &= (BUF_SIZE-1); + + return (smooth_HF>>22); //shift on additional 6 bits for smoothing 2^6 = 64 +}*/ + + +// HFO_SHIFT - ÷èñëî ðàçðÿäîâ äðîáíîé ÷àñòè â 32-õáèòîâîé ïåðåìåííîé hf_reg32 +Input.StrIn.HF_out = HFO_MovAverFilt(Input.StrIn.HF_out<<HFO_SHIFT); +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +Output.Str.HF_dif = L_sub(Device_blk.Str.HF_ref, Input.StrIn.HF_out); // HF_dif = HF_out - Device_blk.Str.HF_ref; + + if ( loop_is_closed(HF_REG_ON) ) //e. the regulator loop is closed //r. êîíòóð çàìêíóò + {// êîýôôèöèåíò ïåðåäà÷è + hf_reg = L_mac( hf_reg, Output.Str.HF_dif, Device_blk.Str.HF_scl ); // hf_reg32 += HFO_error * Device_blk.Str.HF_scl; + Saturation(hf_reg, Device_blk.Str.HF_max << HFO_SHIFT, Device_blk.Str.HF_min << HFO_SHIFT); //e. checking range //r. ïðîâåðêà äèàïàçîíà if (Uin > UpSat) Uin = UpSat; if (Uin < DownSat) Uin = DownSat; + Output.Str.HF_reg = (hf_reg >> HFO_SHIFT); // Output.Str.HF_reg - HFO output voltage + } + else + { + hf_reg = Output.Str.HF_reg << HFO_SHIFT; //r. èíòåãðàòîðó ïðèñâàèâàåì ïðåäûäóùåå çíà÷åíèå HF_reg + } + + // cyclic built-in test + if (!(((Output.Str.HF_reg < HFO_NEG_MAX)&&(Output.Str.HF_reg > HFO_NEG_MIN))||((Output.Str.HF_reg < HFO_POZ_MAX) && (Output.Str.HF_reg > HFO_POZ_MIN)))) + { + Valid_Data |= HFO_VOLT_ERROR; + } +} // clc_HFO
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/InputOutput.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/InputOutput.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,316 @@ +#include "InputOutput.h" +#include "CyclesSync.h" +#include "lpc17xx.h" +//-------------------temp------- +#include "el_lin.h" +INPUT Input; +OUTPUT Output; + +volatile uint32_t I2CMasterState = I2C_IDLE; +volatile uint32_t I2CMasterBuffer[I2C_WRITELENGTH]; + +int ExchangeErr = 0; +//----------------------temp--------------------- +extern char test; +/****************************************************************************** +** Function name: G_Photo_Exchange +** +** Descriptions: Driver for I2C exchange +** +** parameters: None +** Returned value: None +** +******************************************************************************/ + +void G_Photo_Exchange(void) +{ + uint32_t StatValue; + static uint32_t WrIndex; + static int32_t time_out = TIMEOUT; + + if (I2CMasterState) + return; //e.transmitting is not active, go away + + if (--time_out < 0) //e. valid time period elapsed, go away + { + time_out = TIMEOUT; + I2CMasterState = I2C_IDLE; //e. timer elapsed, go away + LPC_I2C0->CONSET = I2CONSET_STO; //e. Set Stop flag + LPC_I2C0->CONCLR = I2CONCLR_AAC | I2CONCLR_SIC | I2CONCLR_STAC; + return; + } + else if (!(LPC_I2C0->CONSET & I2CONSET_SI)) //e. state of I2C bus has not been changed + return; + + StatValue = LPC_I2C0->STAT; + + switch ( StatValue ) + { + case 0x08: // A Start condition is issued (write data for the first potentiometer) + WrIndex = 0; + time_out = TIMEOUT; //e. enable countdown + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send address + LPC_I2C0->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); //e .clear interrupt bit and start bit + break; + + case 0x10: // A repeated started is issued (write data for the second potentiometer) + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send address + LPC_I2C0->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); //e .clear interrupt bit and start bit + break; + + case 0x18: //e. Regardless, it's a ACK after slave address reading + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send another byte + LPC_I2C0->CONCLR = I2CONCLR_SIC; //e. clear interrupt bit + break; + + case 0x28: //e. Regardless it's a ACK after data byte + if (WrIndex == I2C_WRITELENGTH) //e. we have transmitted the data for the B potentiometer + { + I2CMasterState = I2C_IDLE; + LPC_I2C0->CONSET = I2CONSET_STO; //e. Set Stop flag + Output.Str.Cnt_Dif = 300; + } + else if (WrIndex == 3) + { + LPC_I2C0->CONSET = I2CONSET_STA; + Output.Str.Cnt_Dif = 200; + } + else + { + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send another byte + Output.Str.Cnt_Dif = 100; + } + LPC_I2C0->CONCLR = I2CONCLR_SIC; //e. clear interrupt bit + break; + + case 0x20: //e. no aknowledgement after address transmitting + case 0x30: //e. no aknowledgement after data block transmitting + LPC_I2C0->CONSET = I2CONSET_STO; //e. Set Stop flag + LPC_I2C0->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); + I2CMasterState = I2C_IDLE; //e. fix new state + break; + } + return; +} +/****************************************************************************** +** Function name: DAC_ADC_Exchange +** +** Descriptions: Loading data to DACs and initialization of ADC reading +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void DAC_ADC_Exchange() +{ + //-------------------------loading data from ADC to buffer--------------------------------------- +//int x; + ExchangeErr &= ~ADC_ERR_MSK; //e. ñáðîñèòü ôëàã îøèáêè + if (LPC_SSP0->SR & SSP_BUSY) //e. åñëè áóôåð ïåðåäàò÷èêà íå ïîëîí + { + ExchangeErr |= ADC_ERR_MSK; //e. óñòàíîâèòü ôëàã îøèáêè + } + else + { + LPC_SSP0->DR = 0x8001; //çàïèñàòü 0x8001 â ðåãèñòð ïåðåäà÷è. + if (Sys_Clock & 1)//åñëè íå÷åòíûé òàêò òî + { + LPC_SSP0->DR = WRITE_DAC0; //e.êîìàíäà äëÿ ÖÀÏ_0 ïåðåäàâàòü. + LPC_SSP0->DR = (-Output.ArrayOut[3]+32767); //e. ïåðåäà÷à 12 áèò + } + else //åñëè òàêò ÷åòíûé. + { + LPC_SSP0->DR = WRITE_DAC1 ; //e.êîìàíäà äëÿ ÖÀÏ_1 ïåðåäàâàòü. + LPC_SSP0->DR = (Output.ArrayOut[0]<<1) & 0xFFF0; //e. ïåðåäà÷à 12 áèò + } + } +} +/****************************************************************************** +** Function name: ADC_Input +** +** Descriptions: Reading data from ADC +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ADC_Input() +{ + uint32_t Dummy; + + //---------------------read data from ADC buffer--------------------------------------------- + Dummy = Dummy; + ExchangeErr &= ~ADC_ERR_MSK; + + if (LPC_SSP0->SR & SSP_BUSY) //åñëè áóôåð ôèôî íå ïîëíûé(ïåðåäà÷à àòèâíà) + { ExchangeErr |= ADC_ERR_MSK; //óñòàíîâèòü ôëàã îøèáêè + + if (!(LPC_SSP0->SR & TX_SSP_EMPT)) //áóôåð ïåðåäà÷è íå ïóñò. + ExchangeErr |= ADC_ERR_MSK; //óñòàíîâèòü ôëàã îøèáêè + } + else //îáìåí çàêîí÷åí ïðî÷èòàòü áóôåð. + { + Input.ArrayIn[0] = LPC_SSP0->DR; //÷òåíèåThermo2 + Input.ArrayIn[1] = LPC_SSP0->DR; //÷òåíèå Thermo1 + Input.ArrayIn[2] = LPC_SSP0->DR; //÷òåíèå HF_out + + while (LPC_SSP0->SR & RX_SSP_notEMPT) //åñëè áóôåð SPI íå ïóñò. + Dummy = LPC_SSP0->DR; //î÷èñòèòü áóôåð. + } + + +} +/***************************************************************************** +** Function name: DAC_Output +** +** Descriptions: Output data to intrnal DAC +** +** parameters: output - code for output +** Returned value: None +** +*****************************************************************************/ +void DAC_Output(int output) +{ +// LPC_DAC->CR = (output<<6); + return; +} +/****************************************************************************** +** Function name: G_Photo_Init +** +** Descriptions: Initialization of exchange with digital potentiometers +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void G_Photo_Init(void ) +{ + LPC_SC->PCONP |= (1 << 19);//âêëþ÷åíèå èíòåðôåéñà I2C. + + /* set PIO0.27 and PIO0.28 to I2C0 SDA and SCK */ + /* function to 01 on both SDA and SCK. */ + LPC_PINCON->PINSEL1 &= ~0x03C00000; //P0.27 - SDA. + LPC_PINCON->PINSEL1 |= 0x01400000; //P0.28 - SCK. + + // ïîäòâåðæäåíèå Ôëàã ôëàã ðàçðåøåíèÿ + /*ñáðîñ ôëàãîô ôëàãà ïðåðûâàíèÿ I2C ñòàðòà èíòåðôåéñà I2C */ + LPC_I2C0->CONCLR = I2CONCLR_AAC | I2CONCLR_SIC | I2CONCLR_STAC | I2CONCLR_I2ENC; // óñòàíîâêà ìèêðîêîíòðîëëåðà â ðåæèì ìàñòåðà + + /*--- Reset registers ---*/ + LPC_I2C0->SCLL = I2SCLL_SCLL; // - ñ÷åò÷èê scl low time period + LPC_I2C0->SCLH = I2SCLH_SCLH; // - ñ÷åò÷èê scl high time period + + I2CMasterBuffer[0] = A_ADDRESS; //àðåñ ïîòåíöèîìåòðà êàíàëà À + I2CMasterBuffer[1] = WRITE_CMD; //Äàííûå + I2CMasterBuffer[3] = B_ADDRESS; //àðåñ ïîòåíöèîìåòðà êàíàëà  + I2CMasterBuffer[4] = WRITE_CMD; //Äàííûå + + LPC_I2C0->CONSET = I2CONSET_I2EN; //âêëþ÷åíèå èíòåðôåéñà I2C. + +} +/****************************************************************************** +** Function name: DAC_ADC_Exchange_Init +** +** Descriptions: Initialization of data exchange with DACs and ADCs +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void DAC_ADC_Exchange_Init() +{ + + int Dummy; // èíèöèàëèçàöèÿ ìóñîðêè äëÿ î÷èñòêè áóôåðà ïðèåìà. + Dummy = Dummy; + + /* Enable AHB clock to the SSP0, SSP1 */ + LPC_SC->PCONP |= (0x1<<21); // âêëþ÷åíèå SSP0. +// LPC_SC->PCONP |= (0x1<<10); + + /* âûáîð ÷àñòîòû äëÿ ïåðåôåðèè èñïîëüçóåì ïî óìîë÷àíèÿ ñ äåëèòåëåì îñíîâíîé íà 4 */ + LPC_SC->PCLKSEL1 &= ~(0x3<<10); //00 CLK/4; 1 CLK; 2 CLK/2; 3 CLK/8 + LPC_SC->PCLKSEL1 |= (0x0<<10); //00 CLK/4; 1 CLK; 2 CLK/2; 3 CLK/8 + // LPC_SC->PCLKSEL0 &= ~(0x3<<20); + + // P0.15~0.18 as SSP0 + LPC_PINCON->PINSEL0 &= ~(0x3UL<<30); //óñòàíîâèò Ð 0.15 + LPC_PINCON->PINSEL0 |= (0x2UL<<30); //êàê (???? SCK 0 ???). ÷àñòîòà äëÿ ñèíõðîíèçàöèèè Master - slave + + LPC_PINCON->PINSEL1 &= ~((0x3<<0)|(0x3<<2)|(0x3<<4)); // óñòàíèâîèòü Ð 0.17 è Ð 0.18 + LPC_PINCON->PINSEL1 |= ((0x2<<2)|(0x2<<4)); // êàê MISO0 è MOSI0 + + LPC_PINCON->PINMODE0 &= ~(0x3UL<<30);// ? óñòàíîâëåíèå íà Ð 0.15 ðåæèìà On-Chip pull-down resistor enabled + LPC_PINCON->PINMODE0 |= (0x3UL<<30);// ? óñòàíîâëåíèå íà Ð 0.15 ðåæèìà On-Chip pull-down resistor enabled + + LPC_PINCON->PINMODE1 &= ~((0x3<<2)|(0x3<<4));// ? óñòàíîâëåíèå íà Ð 0.17 è Ð 0.18 ðåæèìà On-Chip pull-down resistor enabled + LPC_PINCON->PINMODE1 |= ((0x3<<2)|(0x3<<4));// ? óñòàíîâëåíèå íà Ð 0.17 è Ð 0.18 ðåæèìà On-Chip pull-down resistor enabled + + /* P0.6~0.9 as SSP1 */ +/* LPC_PINCON->PINSEL0 &= ~((0x3<<12)|(0x3<<14)|(0x3<<16)|(0x3<<18)); + LPC_PINCON->PINSEL0 |= ((0x2<<12)|(0x2<<14)|(0x2<<16)|(0x2<<18)); + LPC_PINCON->PINMODE0 &= ~((0x3<<16)|(0x3<<12)|(0x3<<14)|(0x3<<18)); + LPC_PINCON->PINMODE0 |= ((0x3<<16)|(0x3<<14)|(0x3<<18)); */ + + /* Set DSS data to 16-bit, Frame format TI, SCR is 2 */ + LPC_SSP0->CR0 = ((3<<8)|(0<<7)|(0<<4) |0xF); // (0xF)-óñòàíîâëåíèå DSS(Data sise select) â 16-áèòíûé ôîðìàò, (3<<8 scr - âûáîð ÷àñòîòû), + // íèçêèé óðîâåíü ëèíèè òàêòèðîâàíèÿ ìåæäó êàäðàìè, ïðèêðåïëåíèå ïåðåäà÷è ê ïåðâîìó íàðàñòàíèþ òàêòîâîãî ìèãíàëà + // ôîðìàò êàäðà TI. + // LPC_SSP1->CR0 = 0x0207; + + /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */ + LPC_SSP0->CPSR = 0x2; // freq = CLK/(cpsdvr*(scr+1)) = 1.6 MHz + // LPC_SSP1->CPSR = 0x2; + +/*SSP enable, master mode */ + LPC_SSP0->CR1 = SSPCR1_SSE; +// LPC_SSP1->CR1 = SSPCR1_SSE; + + while (LPC_SSP0->SR & SSP_BUSY); +// while (LPC_SSP1->SR & SSP_BUSY); + + while (LPC_SSP0->SR & RX_SSP_notEMPT) /* clear the RxFIFO */ + Dummy = LPC_SSP0->DR; + //all pins after reset is in GPIO mode, so CS pins needn't to configure + LPC_GPIO0->FIODIR |= ADC; // P0.16 defined as CS for ADC + LPC_GPIO0->FIOSET |= ADC; // set CS for ADC + + LPC_GPIO0->FIODIR |= DAC; // P defined as CS for DAC + LPC_GPIO0->FIOCLR |= DAC; // set CS for DAC +/* while (LPC_SSP1->SR & RX_SSP_notEMPT) + Dummy = LPC_SSP1->DR;*/ /* clear the RxFIFO */ +} +/***************************************************************************** +** Function name: DACInit +** +** Descriptions: initialize DAC channel +** +** parameters: None +** Returned value: None +** +*****************************************************************************/ +void DACInit( void ) +{ + /* setup the related pin to DAC output */ + LPC_PINCON->PINSEL1 |= 0x00200000; /* óñòàíîâèòü p0.26 êàê âûõîä ÖÀÏ */ + // LPC_GPIO0->FIODIR |= (1<<26); + LPC_DAC->CNTVAL = 0; // êêàèåòî ïàðàìåòðû + LPC_DAC->CTRL = 0; // äëÿ ÄÌÀ + return; +} +/****************************************************************************** +** Function name: Out_G_photo +** +** Descriptions: Start of potentiometer data writing process +** +** parameters: pointer to gain factors +** Returned value: None +** +******************************************************************************/ +void Out_G_photo(uint32_t Ph_A, uint32_t Ph_B) +{ + I2CMasterBuffer[2] = Ph_A;// çàïèñü â áóôåð I2C ìàñòåðà äàííûõ ñ À êàíàëà ôîòî äàò÷èêà.(óòî÷íèòü) + I2CMasterBuffer[5] = Ph_B;// çàïèñü â áóôåð I2C ìàñòåðà äàííûõ ñ  êàíàëà ôîòî äàò÷èêà.(óòî÷íèòü) + + LPC_I2C0->CONSET = I2CONSET_STA; // óñòàíîâèòü ñòàðò ôëàã. + I2CMasterState = I2C_BUSY; // óñòàíîâèòü ôëàã çàíÿòîé øèíû. + }
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/InputOutput.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/InputOutput.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,127 @@ +#include "stdint.h" + +//******************************I2C************************************************* +#define I2C0 + +#define I2C_IDLE 1 +#define I2C_BUSY 0 + +#define I2CONSET_I2EN 0x0000040 /* I2C Control Set Register */ +#define I2CONSET_AA 0x0000004 +#define I2CONSET_SI 0x0000008 +#define I2CONSET_STO 0x0000010 +#define I2CONSET_STA 0x0000020 + +#define I2CONCLR_AAC 0x0000004 /* I2C Control clear Register */ +#define I2CONCLR_SIC 0x0000008 +#define I2CONCLR_STAC 0x0000020 +#define I2CONCLR_I2ENC 0x0000040 + +#define I2SCLH_SCLH 0x00000080 /* I2C SCL Duty Cycle High Reg */ +#define I2SCLL_SCLL 0x00000080 /* I2C SCL Duty Cycle Low Reg */ + +#define I2C_WRITELENGTH 0x00000006 /*Buffer length*/ +#define A_ADDRESS 0x0000005E /*address of slave potentiometer (table 6-2 of pot's manual)*/ +#define B_ADDRESS 0x0000005C /*address of slave potentiometer (table 6-2 of pot's manual)*/ +#define WRITE_CMD 0x00000000 /*address of wiper0 register in memory map*/ + +//********************************SPI************************************************ +#define HALFWORDS_FOR_ADCs 3 + +#define WRITE_DAC0 0x00000030 //write data to DAC 0 +#define WRITE_DAC1 0x00000031 //write data to DAC 1 + +#define DAC (1<<23) //DAC identifer +#define ADC (1<<16) //ADC identifer + +#define SetCS(a) LPC_GPIO0->FIOSET = a //set CS signal for ADC or DAC +#define ResetCS(a) LPC_GPIO0->FIOCLR = a //reset CS signal for ADC or DAC +#define SetDAC(a) LPC_GPIO0->FIOSET = a //set CS signal for ADC or DAC +#define ResetDAC(a) LPC_GPIO0->FIOCLR = a //reset CS signal for ADC or DAC + + + +#define SSPCR1_SSE 0x00000002 + +#define TX_SSP_EMPT 0x00000001 +#define RX_SSP_notEMPT 0x00000004 +#define TX_SSP_notFULL 0x00000002 +#define RX_SSP_FULL 0x00000008 +#define SSP_BUSY 0x00000010 + +#define ADC_ERR_MSK 0x00000001 +#define DAC_ERR_MSK 0x00000002 + +#define TIMEOUT 1000 + +typedef union + { + int ArrayOut[31]; + struct { + int WP_reg; //e. PLC output voltage + int WP_sin; //r. ñèãíàë ïîèñêà ÑÐÏ - ñèíóñ 250 Ãö + int WP_pll; //r. âûõîä XOR ÔÄ êîíòóðà ÑÐÏ + int HF_reg; //e. HFO output voltage + + int HF_dif; + + int WP_Phase_Det_Array[8]; //e. arrays for "worms" output //r. ìàññèâû äëÿ âûâîäà "÷åðâÿ÷êîâ" + int WP_sin_Array[8]; + int WP_scope1, WP_scope2; //e. temporary variables for Rate3 monitoring //r. âðåìåííûå ïåðåìåííûå äëÿ íàáëþäåíèÿ â Rate3 + + uint32_t F_ras; //e. really output frequency, divided by 16 (for transmission) + uint32_t L_Vibro; //e. period of oscillation of the dither drive //r. ïåðèîä êîëåáàíèÿ âèáðîïðèâîäà + uint32_t T_Vibro; //e. pulse width of the dither drive //r. äëèòåëüíîñòü èìïóëüñà âèáðîïðèâîäà + uint32_t T_VB_pll; //e. PD output of the frequency regulator of the dither drive //r. âûõîä ÔÄ ðåãóëÿòîðà ÷àñòîòû âèáðîïðèâîäà + + int PS_dif; + int BINS_dif; + int Cnt_Dif; + int Cnt_Pls; + int Cnt_Mns; + int Tmp_Out[6]; + + __int64 SF_dif; + + } Str; + } OUTPUT; + + +typedef union + { + int ArrayIn[3]; + struct { + int Tmp_in[2]; + int HF_out; + int WP_sel; + }StrIn; + } INPUT; + +extern INPUT Input; +extern OUTPUT Output; + +void DAC_ADC_Exchange_Init(void); +void DAC_ADC_Exchange(void); +void ADC_Input(void); + +void clc_HFO(void); + +int clc_WP_sin(void); +void clc_PLC(void); +void init_PLC(void); + +void clc_Pulses(void); +void SOI_Init(void); + +void VibroDither_SwitchOn(void); +void VibroDither_SwitchOff(void); +void VibroDither_Set(void); +void DACInit(void); +void DAC_Output(int); +void clc_ThermoSensors(void); + +void Out_G_photo(unsigned, unsigned); +void G_Photo_Init( void ); +void G_Photo_Exchange(void); + +//endof file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/InputOutput_oldSPI.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/InputOutput_oldSPI.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,429 @@ +#include "InputOutput.h" +#include "lpc17xx.h" + +INPUT Input; +OUTPUT Output; + +volatile uint32_t I2CMasterState = I2C_IDLE; +volatile uint32_t I2CMasterBuffer[I2C_WRITELENGTH]; + +int ExchangeErr = 0; + +/****************************************************************************** +** Function name: G_Photo_Exchange +** +** Descriptions: Driver for I2C exchange +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +#if defined I2C0 +void G_Photo_Exchange(void) +{ + uint32_t StatValue; + static uint32_t WrIndex; + static int32_t time_out = TIMEOUT; + + if (I2CMasterState) + return; //e.transmitting is not active, go away + + if (--time_out < 0) //e. valid time period elapsed, go away + { + time_out = TIMEOUT; + I2CMasterState = I2C_IDLE; //e. timer elapsed, go away + LPC_I2C0->CONSET = I2CONSET_STO; //e. Set Stop flag + LPC_I2C0->CONCLR = I2CONCLR_AAC | I2CONCLR_SIC | I2CONCLR_STAC; + return; + } + else if (!(LPC_I2C0->CONSET & I2CONSET_SI)) //e. state of I2C bus has not been changed + return; + + StatValue = LPC_I2C0->STAT; + + switch ( StatValue ) + { + case 0x08: // A Start condition is issued (write data for the first potentiometer) + WrIndex = 0; + time_out = TIMEOUT; //e. enable countdown + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send address + LPC_I2C0->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); //e .clear interrupt bit and start bit + break; + + case 0x10: // A repeated started is issued (write data for the second potentiometer) + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send address + LPC_I2C0->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); //e .clear interrupt bit and start bit + break; + + case 0x18: //e. Regardless, it's a ACK after slave address reading + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send another byte + LPC_I2C0->CONCLR = I2CONCLR_SIC; //e. clear interrupt bit + break; + + case 0x28: //e. Regardless it's a ACK after data byte + if (WrIndex == I2C_WRITELENGTH) //e. we have transmitted the data for the B potentiometer + { + I2CMasterState = I2C_IDLE; + LPC_I2C0->CONSET = I2CONSET_STO; //e. Set Stop flag + } + else if (WrIndex == 3) + { + LPC_I2C0->CONSET = I2CONSET_STA; + } + else + { + LPC_I2C0->DAT = I2CMasterBuffer[WrIndex++]; //e. send another byte + } + LPC_I2C0->CONCLR = I2CONCLR_SIC; //e. clear interrupt bit + break; + + case 0x20: //e. no aknowledgement after address transmitting + case 0x30: //e. no aknowledgement after data block transmitting + LPC_I2C0->CONSET = I2CONSET_STO; //e. Set Stop flag + LPC_I2C0->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); + I2CMasterState = I2C_IDLE; //e. fix new state + break; + } + return; +} +#else +void G_Photo_Exchange(void) +{ + static uint32_t WrIndex; + uint32_t StatValue; + static int time_out = TIMEOUT; + + if (I2CMasterState) + return; //e.transmitting is not active, go away + + if (--time_out < 0) //e. valid time period elapsed, go away + { + time_out = TIMEOUT; + I2CMasterState = I2C_TIME_OUT; //e. timer elapsed, go away + LPC_I2C2->CONSET = I2CONSET_STO; //e. Set Stop flag + LPC_I2C2->CONCLR = I2CONCLR_AAC | I2CONCLR_SIC | I2CONCLR_STAC; + return; + } + else if (!(LPC_I2C2->CONSET & I2CONSET_SI)) //e. state of I2C bus has not been changed + return; + + StatValue = LPC_I2C2->STAT; + + switch ( StatValue ) + { + case 0x08: // A Start condition is issued (write data for the first potentiometer) + WrIndex = 0; + time_out = TIMEOUT; //e. enable countdown + LPC_I2C2->DAT = I2CMasterBuffer[WrIndex++]; //e. send address + LPC_I2C2->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); //e .clear interrupt bit and start bit + break; + + case 0x10: // A repeated started is issued (write data for the second potentiometer) + LPC_I2C2->DAT = I2CMasterBuffer[WrIndex++]; //e. send address + LPC_I2C2->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); //e .clear interrupt bit and start bit + break; + + case 0x18: //e. Regardless, it's a ACK after slave address reading + LPC_I2C2->DAT = I2CMasterBuffer[WrIndex++]; //e. send another byte + LPC_I2C2->CONCLR = I2CONCLR_SIC; //e. clear interrupt bit + break; + + case 0x28: //e. Regardless it's a ACK after data byte + if (WrIndex == I2C_WRITELENGTH) //e. we have transmitted the data for the B potentiometer + { + I2CMasterState = I2C_IDLE; //e. fix new state (release bus) + LPC_I2C2->CONSET = I2CONSET_STO; //e. Set Stop flag + } + else if (WrIndex == 3) + { + LPC_I2C2->CONSET = I2CONSET_STA; + } + else + { + LPC_I2C2->DAT = I2CMasterBuffer[WrIndex++]; //e. send another byte + } + LPC_I2C2->CONCLR = I2CONCLR_SIC; //e. clear interrupt bit + break; + + case 0x20: //e. no aknowledgement after address transmitting + case 0x30: //e. no aknowledgement after data block transmitting + LPC_I2C2->CONSET = I2CONSET_STO; //e. Set Stop flag + LPC_I2C2->CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC); + I2CMasterState = I2C_IDLE; //e. fix new state (release) + break; + } + return; +} +#endif +/****************************************************************************** +** Function name: DAC_Out_ADC_Input +** +** Descriptions: Loading data to DACs and initialization of ADC reading +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void DAC_Out_ADC_Input() +{ + int i, Dummy = Dummy; + + //-------------------------loading data from ADC to buffer--------------------------------------- + i = BYTES_FOR_ADCs; + ExchangeErr &= ~ADC_ERR_MSK; //reset ADC bit of error register; + + if (LPC_SSP0->SR & SSP_BUSY) //if exchanging is activing, error + { + ExchangeErr |= ADC_ERR_MSK; //reset DAC bit of error register; + } + else + + while ((i-- > 0) && (LPC_SSP0->SR & TX_SSP_notFULL)) //receiving has finished, initiate a new one + LPC_SSP0->DR = 0xFF; + /* +{ LPC_SSP0->DR = 0x80; + LPC_SSP0->DR = 0x01; + LPC_SSP0->DR = 0xC0; + LPC_SSP0->DR = 0x03; + LPC_SSP0->DR = 0xE0; + LPC_SSP0->DR = 0x07; + LPC_SSP0->DR = 0xF0; + LPC_SSP0->DR = 0x0F; }*/ +// ------------------------loading data to DACs-------------------------------------------------- + ExchangeErr &= ~DAC_ERR_MSK; //reset DAC bit of error register; + i= BYTEs_FOR_DACs >> 1; + if (LPC_SSP1->SR & SSP_BUSY) //if exchanging is activing, error + { + ExchangeErr |= DAC_ERR_MSK; + } + else + while ((i-->0) && (LPC_SSP1->SR & TX_SSP_notFULL)) //load new data to DAC + { + LPC_SSP1->DR = (Output.ArrayOut[i]>>8)& 0xFF; + if (LPC_SSP1->SR & TX_SSP_notFULL) + LPC_SSP1->DR = Output.ArrayOut[i] & 0xFF; + } + +/* { LPC_SSP1->DR = 0x80; + LPC_SSP1->DR = 0x01; + LPC_SSP1->DR = 0xC0; + LPC_SSP1->DR = 0x03; + LPC_SSP1->DR = 0xE0; + LPC_SSP1->DR = 0x07; + LPC_SSP1->DR = 0xF0; + LPC_SSP1->DR = 0x0F; } */ + + if (i != 0xFFFFFFFF) + { + ExchangeErr |= DAC_ERR_MSK; + } +} +/****************************************************************************** +** Function name: ADC_Out_DAC_Input +** +** Descriptions: Reading data from ADC and initialization of DAC writing +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ADC_Out_DAC_Input() +{ + int i = 0, Dummy; + static int timeDither = 0; + Dummy = Dummy; + + //++++++++++++++++++++++++++ Dither_simulation ++++++++++++++++++++++++++++++++++++++++++++++++ + + if (++timeDither>(LPC_MCPWM->LIM0/50)) + { + LPC_MCPWM->INTF_SET |= 1; + timeDither = 0; + } + //----------------------read receiver buffer of DAC-------------------------------------------- + ExchangeErr &= ~DAC_ERR_MSK; + + if (LPC_SSP1->SR & SSP_BUSY) //if exchanging is active, error + { + ExchangeErr |= DAC_ERR_MSK; + } + else //exchanging has finished, read buffer + { + while (LPC_SSP1->SR & RX_SSP_notEMPT) + { + Dummy = LPC_SSP1->DR; + i++; + } + + if (i != BYTEs_FOR_DACs) + { + ExchangeErr |= DAC_ERR_MSK; + } + } + + //---------------------read data from ADC buffer--------------------------------------------- + i = BYTES_FOR_ADCs >> 1; + ExchangeErr &= ~ADC_ERR_MSK; + + if (LPC_SSP0->SR & SSP_BUSY) //if exchanging is active, error + { + if ((LPC_SSP0->SR & TX_SSP_EMPT)==0) + ExchangeErr |= ADC_ERR_MSK; + } + else //exchanging has finished, read buffer + { + while ((i-- > 0)&& (LPC_SSP0->SR & RX_SSP_notEMPT) ) //read buffer while data present + { + Input.ArrayIn[i] = ((LPC_SSP0->DR & 0xFF) << 8); + if (LPC_SSP0->SR & RX_SSP_notEMPT) + Input.ArrayIn[i] |= (LPC_SSP0->DR & 0xFF); + else + break; + } + if (i != 0xFFFFFFFF) + ExchangeErr |= ADC_ERR_MSK; + } +} +/****************************************************************************** +** Function name: G_Photo_Init +** +** Descriptions: Initialization of exchange with digital potentiometers +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +#if !defined I2C0 +void G_Photo_Init( void ) +{ + LPC_SC->PCONP |= (1 << 26); //e. enable I2C interface + //e. by default sync frequency is CCLK/4 (see PCLKSEL1[21:20]) + + //e. set P0.10 and P0.11 to I2C2 SDA and SCL + LPC_PINCON->PINSEL0 &= ~((0x03<<20)|(0x03<<22)); //e. clear + LPC_PINCON->PINSEL0 |= ((0x02<<20)|(0x02<<22)); //e. set SDA2, SCL2 + LPC_PINCON->PINMODE0 &= ~((0x03<<20)|(0x03<<22)); //e. clear + LPC_PINCON->PINMODE0 |= ((0x02<<20)|(0x2<<22)); //e. No pull-up no pull-down + LPC_PINCON->PINMODE_OD0 |= ((0x01<<10)|(0x1<<11));//e. switch SDA2, SCL2 to open drain mode + + //--- Clear flags --- + LPC_I2C2->CONCLR = I2CONCLR_AAC | I2CONCLR_SIC | I2CONCLR_STAC | I2CONCLR_I2ENC; + + //--- Set registers for transmition rate = PCLK/(I2SCLL_SCLL+I2SCLH_SCLH)--- + LPC_I2C2->SCLL = I2SCLL_SCLL; + LPC_I2C2->SCLH = I2SCLH_SCLH; + + I2CMasterBuffer[0] = A_ADDRESS; + I2CMasterBuffer[1] = WRITE_CMD; + I2CMasterBuffer[3] = B_ADDRESS; + I2CMasterBuffer[4] = WRITE_CMD; + + LPC_I2C2->CONSET = I2CONSET_I2EN; + return; +} +#else +void G_Photo_Init(void ) +{ + LPC_SC->PCONP |= (1 << 19); + + /* set PIO0.27 and PIO0.28 to I2C0 SDA and SCK */ + /* function to 01 on both SDA and SCK. */ + LPC_PINCON->PINSEL1 &= ~0x03C00000; + LPC_PINCON->PINSEL1 |= 0x01400000; + + /*--- Clear flags ---*/ + LPC_I2C0->CONCLR = I2CONCLR_AAC | I2CONCLR_SIC | I2CONCLR_STAC | I2CONCLR_I2ENC; + + /*--- Reset registers ---*/ + LPC_I2C0->SCLL = I2SCLL_SCLL; + LPC_I2C0->SCLH = I2SCLH_SCLH; + + I2CMasterBuffer[0] = A_ADDRESS; + I2CMasterBuffer[1] = WRITE_CMD; + I2CMasterBuffer[3] = B_ADDRESS; + I2CMasterBuffer[4] = WRITE_CMD; + + LPC_I2C0->CONSET = I2CONSET_I2EN; + +} +#endif +/****************************************************************************** +** Function name: DAC_ADC_Exchange_Init +** +** Descriptions: Initialization of data exchange with DACs and ADCs +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void DAC_ADC_Exchange_Init() +{ + int Dummy; + + Dummy = Dummy; + + /* Enable AHB clock to the SSP0, SSP1 */ + // LPC_SC->PCONP |= (0x1<<21); + // LPC_SC->PCONP |= (0x1<<10); + + /* Further divider is needed on SSP0,SSP1 clock. Using default divided by 4 */ + LPC_SC->PCLKSEL1 &= ~(0x3<<10); + LPC_SC->PCLKSEL0 &= ~(0x3<<20); + + /* P0.15~0.18 as SSP0 */ + LPC_PINCON->PINSEL0 &= ~(0x3UL<<30); + LPC_PINCON->PINSEL0 |= (0x2UL<<30); + LPC_PINCON->PINSEL1 &= ~((0x3<<0)|(0x3<<2)|(0x3<<4)); + LPC_PINCON->PINSEL1 |= ((0x2<<0)|(0x2<<2)|(0x2<<4)); + + LPC_PINCON->PINMODE0 &= ~(0x3UL<<30); + LPC_PINCON->PINMODE0 |= (0x3UL<<30); + LPC_PINCON->PINMODE1 &= ~((0x3<<2)|(0x3<<4)); + LPC_PINCON->PINMODE1 |= ((0x3<<2)|(0x3<<4)); + + /* P0.6~0.9 as SSP1 */ + LPC_PINCON->PINSEL0 &= ~((0x3<<12)|(0x3<<14)|(0x3<<16)|(0x3<<18)); + LPC_PINCON->PINSEL0 |= ((0x2<<12)|(0x2<<14)|(0x2<<16)|(0x2<<18)); + LPC_PINCON->PINMODE0 &= ~((0x3<<16)|(0x3<<12)|(0x3<<14)|(0x3<<18)); + LPC_PINCON->PINMODE0 |= ((0x3<<16)|(0x3<<14)|(0x3<<18)); + + /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 2*/ + LPC_SSP0->CR0 = 0x0207; + LPC_SSP1->CR0 = 0x0207; + + /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */ + LPC_SSP0->CPSR = 0x2; + LPC_SSP1->CPSR = 0x2; //so, SSPfreq = PCLK/(2*(2+1)) = 4.13 MHz + + LPC_SSP0->CR1 = SSPCR1_SSE; + LPC_SSP1->CR1 = SSPCR1_SSE; + + while (LPC_SSP0->SR & SSP_BUSY); + while (LPC_SSP1->SR & SSP_BUSY); + + while (LPC_SSP0->SR & RX_SSP_notEMPT) /* clear the RxFIFO */ + Dummy = LPC_SSP0->DR; + + while (LPC_SSP1->SR & RX_SSP_notEMPT) + Dummy = LPC_SSP1->DR; /* clear the RxFIFO */ +} +/****************************************************************************** +** Function name: Out_G_photo +** +** Descriptions: Start of potentiometer data writing process +** +** parameters: pointer to gain factors +** Returned value: None +** +******************************************************************************/ +void Out_G_photo(uint32_t Ph_A, uint32_t Ph_B) +{ + I2CMasterBuffer[2] = Ph_A; + I2CMasterBuffer[5] = Ph_B; +#if defined I2C0 + LPC_I2C0->CONSET = I2CONSET_STA; // Set Start flag +#else + LPC_I2C2->CONSET = I2CONSET_STA; // Set Start flag +#endif + I2CMasterState = I2C_BUSY; + }
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/LPC17xx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/LPC17xx.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1007 @@ +/****************************************************************************** + * @file: LPC17xx.h + * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version: V1.10 + * @date: 24. September 2010 + *---------------------------------------------------------------------------- + * + * @note + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +/** @addtogroup LPC17xx_System + * @{ + */ + #define rISER0 (*(volatile unsigned *)0xE000E100) + #define rICER0 (*(volatile unsigned *)0xE000E180) + #define rISPR0 (*(volatile unsigned *)0xE000E200) + #define rICPR0 (*(volatile unsigned *)0xE000E280) + #define rIABR0 (*(volatile unsigned *)0xE000E300) + + +/** @brief IRQ interrupt source definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ + USBActivity_IRQn = 33, /*!< USB Activity Interrupt(For wakeup only) */ + CANActivity_IRQn = 34 /*!< CAN Activity Interrupt(For wakeup only) */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC17xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SC) ------------------------------------------*/ +/** @brief System Control (SC) register structure definition */ +typedef struct +{ + __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ + __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ + __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ + __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ + __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ + __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ + __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ + uint32_t RESERVED2[4]; + __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ + __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; /*!< Offset: 0x104 (R/W) CPU Clock Configure Register */ + __IO uint32_t USBCLKCFG; /*!< Offset: 0x108 (R/W) USB Clock Configure Register */ + __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ + __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ + __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ + uint32_t RESERVED4[10]; + __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ + uint32_t RESERVED5[1]; + __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ + __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Select 0 Register */ + __IO uint32_t PCLKSEL1; /*!< Offset: 0x1AC (R/W) Peripheral Clock Select 1 Register */ + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ + __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ + __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ + + } LPC_SC_TypeDef; + + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +/** @brief Pin Connect Block (PINCON) register structure definition */ +typedef struct +{ + __IO uint32_t PINSEL0; /* !< Offset: 0x000 PIN Select0 (R/W) */ + __IO uint32_t PINSEL1; /* !< Offset: 0x004 PIN Select1 (R/W) */ + __IO uint32_t PINSEL2; /* !< Offset: 0x008 PIN Select2 (R/W) */ + __IO uint32_t PINSEL3; /* !< Offset: 0x00C PIN Select3 (R/W) */ + __IO uint32_t PINSEL4; /* !< Offset: 0x010 PIN Select4 (R/W) */ + __IO uint32_t PINSEL5; /* !< Offset: 0x014 PIN Select5 (R/W) */ + __IO uint32_t PINSEL6; /* !< Offset: 0x018 PIN Select6 (R/W) */ + __IO uint32_t PINSEL7; /* !< Offset: 0x01C PIN Select7 (R/W) */ + __IO uint32_t PINSEL8; /* !< Offset: 0x020 PIN Select8 (R/W) */ + __IO uint32_t PINSEL9; /* !< Offset: 0x024 PIN Select9 (R/W) */ + __IO uint32_t PINSEL10; /* !< Offset: 0x028 PIN Select20 (R/W) */ + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; /* !< Offset: 0x040 PIN Mode0 (R/W) */ + __IO uint32_t PINMODE1; /* !< Offset: 0x044 PIN Mode1 (R/W) */ + __IO uint32_t PINMODE2; /* !< Offset: 0x048 PIN Mode2 (R/W) */ + __IO uint32_t PINMODE3; /* !< Offset: 0x04C PIN Mode3 (R/W) */ + __IO uint32_t PINMODE4; /* !< Offset: 0x050 PIN Mode4 (R/W) */ + __IO uint32_t PINMODE5; /* !< Offset: 0x054 PIN Mode5 (R/W) */ + __IO uint32_t PINMODE6; /* !< Offset: 0x058 PIN Mode6 (R/W) */ + __IO uint32_t PINMODE7; /* !< Offset: 0x05C PIN Mode7 (R/W) */ + __IO uint32_t PINMODE8; /* !< Offset: 0x060 PIN Mode8 (R/W) */ + __IO uint32_t PINMODE9; /* !< Offset: 0x064 PIN Mode9 (R/W) */ + __IO uint32_t PINMODE_OD0; /* !< Offset: 0x068 Open Drain PIN Mode0 (R/W) */ + __IO uint32_t PINMODE_OD1; /* !< Offset: 0x06C Open Drain PIN Mode1 (R/W) */ + __IO uint32_t PINMODE_OD2; /* !< Offset: 0x070 Open Drain PIN Mode2 (R/W) */ + __IO uint32_t PINMODE_OD3; /* !< Offset: 0x074 Open Drain PIN Mode3 (R/W) */ + __IO uint32_t PINMODE_OD4; /* !< Offset: 0x078 Open Drain PIN Mode4 (R/W) */ + __IO uint32_t I2CPADCFG; /* !< Offset: 0x07C I2C Pad Configure (R/W) */ +} LPC_PINCON_TypeDef; + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +/** @brief General Purpose Input/Output (GPIO) register structure definition */ +typedef struct +{ + union { + __IO uint32_t FIODIR; /* !< Offset: 0x00 Port direction (R/W) */ + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; /* !< Offset: 0x10 Port mask (R/W) */ + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; /* !< Offset: 0x14 Port value (R/W) */ + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; /* !< Offset: 0x18 Port output set (R/W) */ + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; /* !< Offset: 0x1C Port output clear (R/W) */ + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; + +/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */ +typedef struct +{ + __I uint32_t IntStatus; /*!< Offset: 0x000 (R/ ) GPIO overall Interrupt Status Register */ + __I uint32_t IO0IntStatR; /*!< Offset: 0x004 (R/ ) GPIO Interrupt Status Register 0 for Rising edge */ + __I uint32_t IO0IntStatF; /*!< Offset: 0x008 (R/ ) GPIO Interrupt Status Register 0 for Falling edge */ + __O uint32_t IO0IntClr; /*!< Offset: 0x00C (R/W) GPIO Interrupt Clear Register 0 */ + __IO uint32_t IO0IntEnR; /*!< Offset: 0x010 ( /W) GPIO Interrupt Enable Register 0 for Rising edge */ + __IO uint32_t IO0IntEnF; /*!< Offset: 0x014 (R/W) GPIO Interrupt Enable Register 0 for Falling edge */ + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Rising edge */ + __I uint32_t IO2IntStatF; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Falling edge */ + __O uint32_t IO2IntClr; /*!< Offset: 0x000 ( /W) GPIO Interrupt Clear Register 2 */ + __IO uint32_t IO2IntEnR; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Rising edge */ + __IO uint32_t IO2IntEnF; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Falling edge */ +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +/** @brief Timer (TIM) register structure definition */ +typedef struct +{ + __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */ + __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */ + __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */ + __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */ + __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */ + __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */ + __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */ + __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */ + __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */ + __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */ + __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */ + __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */ + __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register */ + uint32_t RESERVED0[2]; + __IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */ + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */ +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +/** @brief Pulse-Width Modulation (PWM) register structure definition */ +typedef struct +{ + __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */ + __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register. Register */ + __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */ + __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */ + __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */ + __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */ + __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */ + __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */ + __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */ + __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */ + __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */ + __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */ + __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register 1 */ + __I uint32_t CR2; /*!< Offset: 0x034 (R/ ) Capture Register 2 */ + __I uint32_t CR3; /*!< Offset: 0x038 (R/ ) Capture Register 3 */ + uint32_t RESERVED0; + __IO uint32_t MR4; /*!< Offset: 0x040 (R/W) Match Register 4 */ + __IO uint32_t MR5; /*!< Offset: 0x044 (R/W) Match Register 5 */ + __IO uint32_t MR6; /*!< Offset: 0x048 (R/W) Match Register 6 */ + __IO uint32_t PCR; /*!< Offset: 0x04C (R/W) PWM Control Register */ + __IO uint32_t LER; /*!< Offset: 0x050 (R/W) Load Enable Register */ + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */ +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ + __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ + }; + union { + __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ + __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register (R/W) */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ + __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ + uint32_t RESERVED0; + __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ + uint32_t RESERVED1; + __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ + __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ + __IO uint32_t ICR; /*!< Offset: 0x024 IrDA Control Register (R/W) */ + __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ + uint32_t RESERVED2; + __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ +} LPC_UART_TypeDef; + +/** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ + __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ + }; + union { + __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ + __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ + __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ + __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ + __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ + __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ + __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ + uint32_t RESERVED0; + __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ + uint32_t RESERVED1; + __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ + uint32_t RESERVED2[6]; + __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ + __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ + __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +/** @brief Serial Peripheral Interface (SPI) register structure definition */ +typedef struct +{ + __IO uint32_t SPCR; /*!< Offset: 0x000 SPI Control Register (R/W) */ + __I uint32_t SPSR; /*!< Offset: 0x004 SPI Status Register (R/) */ + __IO uint32_t SPDR; /*!< Offset: 0x008 SPI Data Register (R/W) */ + __IO uint32_t SPCCR; /*!< Offset: 0x00C SPI Clock Counter Register (R/W) */ + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; /*!< Offset: 0x01C SPI Interrupt Flag Register (R/W) */ +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +/** @brief Synchronous Serial Communication (SSP) register structure definition */ +typedef struct +{ + __IO uint32_t CR0; /*!< Offset: 0x000 (R/W) Control Register 0 */ + __IO uint32_t CR1; /*!< Offset: 0x004 (R/W) Control Register 1 */ + __IO uint32_t DR; /*!< Offset: 0x008 (R/W) Data Register */ + __I uint32_t SR; /*!< Offset: 0x00C (R/ ) Status Register */ + __IO uint32_t CPSR; /*!< Offset: 0x010 (R/W) Clock Prescale Register */ + __IO uint32_t IMSC; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */ + __IO uint32_t RIS; /*!< Offset: 0x018 (R/W) Raw Interrupt Status Register */ + __IO uint32_t MIS; /*!< Offset: 0x01C (R/W) Masked Interrupt Status Register */ + __IO uint32_t ICR; /*!< Offset: 0x020 (R/W) SSPICR Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< Offset: 0x024 (R/W) DMA Control Register */ +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** @brief Inter-Integrated Circuit (I2C) register structure definition */ +typedef struct +{ + __IO uint32_t CONSET; /*!< Offset: 0x000 (R/W) I2C Control Set Register */ + __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) I2C Status Register */ + __IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C Data Register */ + __IO uint32_t ADR0; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */ + __IO uint32_t SCLH; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */ + __IO uint32_t SCLL; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */ + __O uint32_t CONCLR; /*!< Offset: 0x018 (R/W) I2C Control Clear Register */ + __IO uint32_t MMCTRL; /*!< Offset: 0x01C (R/W) Monitor mode control register */ + __IO uint32_t ADR1; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */ + __IO uint32_t ADR2; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */ + __IO uint32_t ADR3; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */ + __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C (R/ ) Data buffer Register */ + __IO uint32_t MASK0; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */ + __IO uint32_t MASK2; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */ + __IO uint32_t MASK3; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */ +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +/** @brief Inter IC Sound (I2S) register structure definition */ +typedef struct +{ + __IO uint32_t DAO; /*!< Offset: 0x000 (R/W) Digital Audio Output Register */ + __IO uint32_t DAI; /*!< Offset: 0x004 (R/W) Digital Audio Input Register */ + __O uint32_t TXFIFO; /*!< Offset: 0x008 ( /W) Transmit FIFO */ + __I uint32_t RXFIFO; /*!< Offset: 0x00C (R/ ) Receive FIFO */ + __I uint32_t STATE; /*!< Offset: 0x010 (R/W) Status Feedback Register */ + __IO uint32_t DMA1; /*!< Offset: 0x014 (R/W) DMA Configuration Register 1 */ + __IO uint32_t DMA2; /*!< Offset: 0x018 (R/W) DMA Configuration Register 2 */ + __IO uint32_t IRQ; /*!< Offset: 0x01C (R/W) Interrupt Request Control Register */ + __IO uint32_t TXRATE; /*!< Offset: 0x020 (R/W) Transmit reference clock divider Register */ + __IO uint32_t RXRATE; /*!< Offset: 0x024 (R/W) Receive reference clock divider Register */ + __IO uint32_t TXBITRATE; /*!< Offset: 0x028 (R/W) Transmit bit rate divider Register */ + __IO uint32_t RXBITRATE; /*!< Offset: 0x02C (R/W) Receive bit rate divider Register */ + __IO uint32_t TXMODE; /*!< Offset: 0x030 (R/W) Transmit mode control Register */ + __IO uint32_t RXMODE; /*!< Offset: 0x034 (R/W) Receive mode control Register */ +} LPC_I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +/** @brief Repetitive Interrupt Timer (RIT) register structure definition */ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint32_t RICTRL; + __IO uint32_t RICOUNTER; +} LPC_RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +/** @brief Real-Time Clock (RTC) register structure definition */ +typedef struct +{ + __IO uint32_t ILR; /*!< Offset: 0x000 (R/W) Interrupt Location Register */ + uint32_t RESERVED0; + __IO uint32_t CCR; /*!< Offset: 0x008 (R/W) Clock Control Register */ + __IO uint32_t CIIR; /*!< Offset: 0x00C (R/W) Counter Increment Interrupt Register */ + __IO uint32_t AMR; /*!< Offset: 0x010 (R/W) Alarm Mask Register */ + __I uint32_t CTIME0; /*!< Offset: 0x014 (R/ ) Consolidated Time Register 0 */ + __I uint32_t CTIME1; /*!< Offset: 0x018 (R/ ) Consolidated Time Register 1 */ + __I uint32_t CTIME2; /*!< Offset: 0x01C (R/ ) Consolidated Time Register 2 */ + __IO uint32_t SEC; /*!< Offset: 0x020 (R/W) Seconds Counter Register */ + __IO uint32_t MIN; /*!< Offset: 0x024 (R/W) Minutes Register */ + __IO uint32_t HOUR; /*!< Offset: 0x028 (R/W) Hours Register */ + __IO uint32_t DOM; /*!< Offset: 0x02C (R/W) Day of Month Register */ + __IO uint32_t DOW; /*!< Offset: 0x030 (R/W) Day of Week Register */ + __IO uint32_t DOY; /*!< Offset: 0x034 (R/W) Day of Year Register */ + __IO uint32_t MONTH; /*!< Offset: 0x038 (R/W) Months Register */ + __IO uint32_t YEAR; /*!< Offset: 0x03C (R/W) Years Register */ + __IO uint32_t CALIBRATION; /*!< Offset: 0x040 (R/W) Calibration Value Register */ + __IO uint32_t GPREG0; /*!< Offset: 0x044 (R/W) General Purpose Register 0 */ + __IO uint32_t GPREG1; /*!< Offset: 0x048 (R/W) General Purpose Register 1 */ + __IO uint32_t GPREG2; /*!< Offset: 0x04C (R/W) General Purpose Register 2 */ + __IO uint32_t GPREG3; /*!< Offset: 0x050 (R/W) General Purpose Register 3 */ + __IO uint32_t GPREG4; /*!< Offset: 0x054 (R/W) General Purpose Register 4 */ + __IO uint32_t RTC_AUXEN; /*!< Offset: 0x058 (R/W) RTC Auxiliary Enable Register */ + __IO uint32_t RTC_AUX; /*!< Offset: 0x05C (R/W) RTC Auxiliary Control Register */ + __IO uint32_t ALSEC; /*!< Offset: 0x060 (R/W) Alarm value for Seconds */ + __IO uint32_t ALMIN; /*!< Offset: 0x064 (R/W) Alarm value for Minutes */ + __IO uint32_t ALHOUR; /*!< Offset: 0x068 (R/W) Alarm value for Hours */ + __IO uint32_t ALDOM; /*!< Offset: 0x06C (R/W) Alarm value for Day of Month */ + __IO uint32_t ALDOW; /*!< Offset: 0x070 (R/W) Alarm value for Day of Week */ + __IO uint32_t ALDOY; /*!< Offset: 0x074 (R/W) Alarm value for Day of Year */ + __IO uint32_t ALMON; /*!< Offset: 0x078 (R/W) Alarm value for Months */ + __IO uint32_t ALYEAR; /*!< Offset: 0x07C (R/W) Alarm value for Year */ +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +/** @brief Watchdog Timer (WDT) register structure definition */ +typedef struct +{ + __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) Watchdog mode Register */ + __IO uint32_t TC; /*!< Offset: 0x004 (R/W) Watchdog timer constant Register */ + __O uint32_t FEED; /*!< Offset: 0x008 ( /W) Watchdog feed sequence Register */ + __I uint32_t TV; /*!< Offset: 0x00C (R/ ) Watchdog timer value Register */ + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +/** @brief Analog-to-Digital Converter (ADC) register structure definition */ +typedef struct +{ + __IO uint32_t CR; /*!< Offset: 0x000 (R/W) A/D Control Register */ + __IO uint32_t GDR; /*!< Offset: 0x004 (R/W) A/D Global Data Register */ + uint32_t RESERVED0; + __IO uint32_t INTEN; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */ + __I uint32_t DR[8]; /*!< Offset: 0x010 (R/ ) A/D Channel # Data Register */ + __I uint32_t STAT; /*!< Offset: 0x030 (R/ ) A/D Status Register */ + __IO uint32_t ADTRM; /*!< Offset: 0x034 (R/W) ADC trim Register */ +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +/** @brief Digital-to-Analog Converter (DAC) register structure definition */ +typedef struct +{ + __IO uint32_t CR; /*!< Offset: 0x000 (R/W) D/A Converter Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) DAC Control register */ + __IO uint32_t CNTVAL; /*!< Offset: 0x008 (R/W) DAC Counter Value Register */ +} LPC_DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +/** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */ +typedef struct +{ + __I uint32_t CON; /*!< Offset: 0x000 (R/ ) PWM Control read address Register */ + __O uint32_t CON_SET; /*!< Offset: 0x004 ( /W) PWM Control set address Register */ + __O uint32_t CON_CLR; /*!< Offset: 0x008 ( /W) PWM Control clear address Register */ + __I uint32_t CAPCON; /*!< Offset: 0x00C (R/ ) Capture Control read address Register */ + __O uint32_t CAPCON_SET; /*!< Offset: 0x010 ( /W) Capture Control set address Register */ + __O uint32_t CAPCON_CLR; /*!< Offset: 0x014 ( /W) Event Control clear address Register */ + __IO uint32_t TC0; /*!< Offset: 0x018 (R/W) Timer Counter Register, channel 0 */ + __IO uint32_t TC1; /*!< Offset: 0x01C (R/W) Timer Counter Register, channel 1 */ + __IO uint32_t TC2; /*!< Offset: 0x020 (R/W) Timer Counter Register, channel 2 */ + __IO uint32_t LIM0; /*!< Offset: 0x024 (R/W) Limit Register, channel 0 */ + __IO uint32_t LIM1; /*!< Offset: 0x028 (R/W) Limit Register, channel 1 */ + __IO uint32_t LIM2; /*!< Offset: 0x02C (R/W) Limit Register, channel 2 */ + __IO uint32_t MAT0; /*!< Offset: 0x030 (R/W) Match Register, channel 0 */ + __IO uint32_t MAT1; /*!< Offset: 0x034 (R/W) Match Register, channel 1 */ + __IO uint32_t MAT2; /*!< Offset: 0x038 (R/W) Match Register, channel 2 */ + __IO uint32_t DT; /*!< Offset: 0x03C (R/W) Dead time Register */ + __IO uint32_t CP; /*!< Offset: 0x040 (R/W) Commutation Pattern Register */ + __IO uint32_t CAP0; /*!< Offset: 0x044 (R/W) Capture Register, channel 0 */ + __IO uint32_t CAP1; /*!< Offset: 0x048 (R/W) Capture Register, channel 1 */ + __IO uint32_t CAP2; /*!< Offset: 0x04C (R/W) Capture Register, channel 2 */ + __I uint32_t INTEN; /*!< Offset: 0x050 (R/ ) Interrupt Enable read Register */ + __O uint32_t INTEN_SET; /*!< Offset: 0x054 ( /W) Interrupt Enable set address Register */ + __O uint32_t INTEN_CLR; /*!< Offset: 0x058 ( /W) Interrupt Enable clear address Register */ + __I uint32_t CNTCON; /*!< Offset: 0x05C (R/ ) Count Control read address Register */ + __O uint32_t CNTCON_SET; /*!< Offset: 0x060 ( /W) Count Control set address Register */ + __O uint32_t CNTCON_CLR; /*!< Offset: 0x064 ( /W) Count Control clear address Register */ + __I uint32_t INTF; /*!< Offset: 0x068 (R/ ) Interrupt flags read address Register */ + __O uint32_t INTF_SET; /*!< Offset: 0x06C ( /W) Interrupt flags set address Register */ + __O uint32_t INTF_CLR; /*!< Offset: 0x070 ( /W) Interrupt flags clear address Register */ + __O uint32_t CAP_CLR; /*!< Offset: 0x074 ( /W) Capture clear address Register */ +} LPC_MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +/** @brief Quadrature Encoder Interface (QEI) register structure definition */ +typedef struct +{ + __O uint32_t CON; /*!< Offset: 0x000 ( /W) Control Register */ + __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) Encoder Status Register */ + __IO uint32_t CONF; /*!< Offset: 0x008 (R/W) Configuration Register */ + __I uint32_t POS; /*!< Offset: 0x00C (R/ ) Position Register */ + __IO uint32_t MAXPOS; /*!< Offset: 0x010 (R/W) Maximum position Register */ + __IO uint32_t CMPOS0; /*!< Offset: 0x014 (R/W) Position compare Register 0 */ + __IO uint32_t CMPOS1; /*!< Offset: 0x018 (R/W) Position compare Register 1 */ + __IO uint32_t CMPOS2; /*!< Offset: 0x01C (R/W) Position compare Register 2 */ + __I uint32_t INXCNT; /*!< Offset: 0x020 (R/ ) Index count Register */ + __IO uint32_t INXCMP0; /*!< Offset: 0x024 (R/W) Index compare Register 0 */ + __IO uint32_t LOAD; /*!< Offset: 0x028 (R/W) Velocity timer reload Register */ + __I uint32_t TIME; /*!< Offset: 0x02C (R/ ) Velocity timer Register */ + __I uint32_t VEL; /*!< Offset: 0x030 (R/ ) Velocity counter Register */ + __I uint32_t CAP; /*!< Offset: 0x034 (R/ ) Velocity capture Register */ + __IO uint32_t VELCOMP; /*!< Offset: 0x038 (R/W) Velocity compare Register */ + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t IEC; /*!< Offset: 0xFD8 ( /W) Interrupt enable clear Register */ + __O uint32_t IES; /*!< Offset: 0xFDC ( /W) Interrupt enable set Register */ + __I uint32_t INTSTAT; /*!< Offset: 0xFE0 (R/ ) Interrupt status Register */ + __I uint32_t IE; /*!< Offset: 0xFE4 (R/ ) Interrupt enable Register */ + __O uint32_t CLR; /*!< Offset: 0xFE8 ( /W) Interrupt status clear Register */ + __O uint32_t SET; /*!< Offset: 0xFEC ( /W) Interrupt status set Register */ +} LPC_QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +/** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */ +typedef struct +{ + __IO uint32_t mask[512]; /*!< Offset: 0x000 (R/W) Acceptance Filter RAM */ +} LPC_CANAF_RAM_TypeDef; + +/** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */ +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; /*!< Offset: 0x000 (R/W) Acceptance Filter Register */ + __IO uint32_t SFF_sa; /*!< Offset: 0x004 (R/W) Standard Frame Individual Start Address Register */ + __IO uint32_t SFF_GRP_sa; /*!< Offset: 0x008 (R/W) Standard Frame Group Start Address Register */ + __IO uint32_t EFF_sa; /*!< Offset: 0x00C (R/W) Extended Frame Start Address Register */ + __IO uint32_t EFF_GRP_sa; /*!< Offset: 0x010 (R/W) Extended Frame Group Start Address Register */ + __IO uint32_t ENDofTable; /*!< Offset: 0x014 (R/W) End of AF Tables Register */ + __I uint32_t LUTerrAd; /*!< Offset: 0x018 (R/ ) LUT Error Address Register */ + __I uint32_t LUTerr; /*!< Offset: 0x01C (R/ ) LUT Error Register */ + __IO uint32_t FCANIE; /*!< Offset: 0x020 (R/W) Global FullCANInterrupt Enable Register */ + __IO uint32_t FCANIC0; /*!< Offset: 0x024 (R/W) FullCAN Interrupt and Capture Register 0 */ + __IO uint32_t FCANIC1; /*!< Offset: 0x028 (R/W) FullCAN Interrupt and Capture Register 1 */ +} LPC_CANAF_TypeDef; + +/** @brief Controller Area Network Central (CANCR) register structure definition */ +typedef struct /* Central Registers */ +{ + __I uint32_t TxSR; /*!< Offset: 0x000 (R/ ) CAN Central Transmit Status Register */ + __I uint32_t RxSR; /*!< Offset: 0x004 (R/ ) CAN Central Receive Status Register */ + __I uint32_t MSR; /*!< Offset: 0x008 (R/ ) CAN Central Miscellaneous Register */ +} LPC_CANCR_TypeDef; + +/** @brief Controller Area Network Controller (CAN) register structure definition */ +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) CAN Mode Register */ + __O uint32_t CMR; /*!< Offset: 0x004 ( /W) CAN Command Register */ + __IO uint32_t GSR; /*!< Offset: 0x008 (R/W) CAN Global Status Register */ + __I uint32_t ICR; /*!< Offset: 0x00C (R/ ) CAN Interrupt and Capture Register */ + __IO uint32_t IER; /*!< Offset: 0x010 (R/W) CAN Interrupt Enable Register */ + __IO uint32_t BTR; /*!< Offset: 0x014 (R/W) CAN Bus Timing Register */ + __IO uint32_t EWL; /*!< Offset: 0x018 (R/W) CAN Error Warning Limit Register */ + __I uint32_t SR; /*!< Offset: 0x01C (R/ ) CAN Status Register */ + __IO uint32_t RFS; /*!< Offset: 0x020 (R/W) CAN Receive Frame Status Register */ + __IO uint32_t RID; /*!< Offset: 0x024 (R/W) CAN Receive Identifier Register */ + __IO uint32_t RDA; /*!< Offset: 0x028 (R/W) CAN Receive Data Register A */ + __IO uint32_t RDB; /*!< Offset: 0x02C (R/W) CAN Receive Data Register B */ + __IO uint32_t TFI1; /*!< Offset: 0x030 (R/W) CAN Transmit Frame Information Register 1 */ + __IO uint32_t TID1; /*!< Offset: 0x034 (R/W) CAN Transmit Identifier Register 1 */ + __IO uint32_t TDA1; /*!< Offset: 0x038 (R/W) CAN Transmit Data Register A 1 */ + __IO uint32_t TDB1; /*!< Offset: 0x03C (R/W) CAN Transmit Data Register B 1 */ + __IO uint32_t TFI2; /*!< Offset: 0x040 (R/W) CAN Transmit Frame Information Register 2 */ + __IO uint32_t TID2; /*!< Offset: 0x044 (R/W) CAN Transmit Identifier Register 2 */ + __IO uint32_t TDA2; /*!< Offset: 0x048 (R/W) CAN Transmit Data Register A 2 */ + __IO uint32_t TDB2; /*!< Offset: 0x04C (R/W) CAN Transmit Data Register B 2 */ + __IO uint32_t TFI3; /*!< Offset: 0x050 (R/W) CAN Transmit Frame Information Register 3 */ + __IO uint32_t TID3; /*!< Offset: 0x054 (R/W) CAN Transmit Identifier Register 3 */ + __IO uint32_t TDA3; /*!< Offset: 0x058 (R/W) CAN Transmit Data Register A 3 */ + __IO uint32_t TDB3; /*!< Offset: 0x05C (R/W) CAN Transmit Data Register B 3 */ +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +/** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */ +typedef struct /* Common Registers */ +{ + __I uint32_t IntStat; /*!< Offset: 0x000 (R/ ) DMA Interrupt Status Register */ + __I uint32_t IntTCStat; /*!< Offset: 0x004 (R/ ) DMA Interrupt Terminal Count Request Status Register */ + __O uint32_t IntTCClear; /*!< Offset: 0x008 ( /W) DMA Interrupt Terminal Count Request Clear Register */ + __I uint32_t IntErrStat; /*!< Offset: 0x00C (R/ ) DMA Interrupt Error Status Register */ + __O uint32_t IntErrClr; /*!< Offset: 0x010 ( /W) DMA Interrupt Error Clear Register */ + __I uint32_t RawIntTCStat; /*!< Offset: 0x014 (R/ ) DMA Raw Interrupt Terminal Count Status Register */ + __I uint32_t RawIntErrStat; /*!< Offset: 0x018 (R/ ) DMA Raw Error Interrupt Status Register */ + __I uint32_t EnbldChns; /*!< Offset: 0x01C (R/ ) DMA Enabled Channel Register */ + __IO uint32_t SoftBReq; /*!< Offset: 0x020 (R/W) DMA Software Burst Request Register */ + __IO uint32_t SoftSReq; /*!< Offset: 0x024 (R/W) DMA Software Single Request Register */ + __IO uint32_t SoftLBReq; /*!< Offset: 0x028 (R/W) DMA Software Last Burst Request Register */ + __IO uint32_t SoftLSReq; /*!< Offset: 0x02C (R/W) DMA Software Last Single Request Register */ + __IO uint32_t Config; /*!< Offset: 0x030 (R/W) DMA Configuration Register */ + __IO uint32_t Sync; /*!< Offset: 0x034 (R/W) DMA Synchronization Register */ +} LPC_GPDMA_TypeDef; + +/** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */ +typedef struct /* Channel Registers */ +{ + __IO uint32_t CSrcAddr; /*!< Offset: 0x000 (R/W) DMA Channel # Source Address Register */ + __IO uint32_t CDestAddr; /*!< Offset: 0x004 (R/W) DMA Channel # Destination Address Register */ + __IO uint32_t CLLI; /*!< Offset: 0x008 (R/W) DMA Channel # Linked List Item Register */ + __IO uint32_t CControl; /*!< Offset: 0x00C (R/W) DMA Channel # Control Register */ + __IO uint32_t CConfig; /*!< Offset: 0x010 (R/W) DMA Channel # Configuration Register */ +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +/** @brief Universal Serial Bus (USB) register structure definition */ +typedef struct +{ + __I uint32_t Revision; /*!< Offset: 0x000 (R/ ) Revision Register */ + __IO uint32_t Control; /*!< Offset: 0x004 (R/W) Control Register */ + __IO uint32_t CommandStatus; /*!< Offset: 0x008 (R/W) Command / Status Register */ + __IO uint32_t InterruptStatus; /*!< Offset: 0x00C (R/W) Interrupt Status Register */ + __IO uint32_t InterruptEnable; /*!< Offset: 0x010 (R/W) Interrupt Enable Register */ + __IO uint32_t InterruptDisable; /*!< Offset: 0x014 (R/W) Interrupt Disable Register */ + __IO uint32_t HCCA; /*!< Offset: 0x018 (R/W) Host Controller communication Area Register */ + __I uint32_t PeriodCurrentED; /*!< Offset: 0x01C (R/ ) Register */ + __IO uint32_t ControlHeadED; /*!< Offset: 0x020 (R/W) Register */ + __IO uint32_t ControlCurrentED; /*!< Offset: 0x024 (R/W) Register */ + __IO uint32_t BulkHeadED; /*!< Offset: 0x028 (R/W) Register */ + __IO uint32_t BulkCurrentED; /*!< Offset: 0x02C (R/W) Register */ + __I uint32_t DoneHead; /*!< Offset: 0x030 (R/ ) Register */ + __IO uint32_t FmInterval; /*!< Offset: 0x034 (R/W) Register */ + __I uint32_t FmRemaining; /*!< Offset: 0x038 (R/ ) Register */ + __I uint32_t FmNumber; /*!< Offset: 0x03C (R/ ) Register */ + __IO uint32_t PeriodicStart; /*!< Offset: 0x040 (R/W) Register */ + __IO uint32_t LSTreshold; /*!< Offset: 0x044 (R/W) Register */ + __IO uint32_t RhDescriptorA; /*!< Offset: 0x048 (R/W) Register */ + __IO uint32_t RhDescriptorB; /*!< Offset: 0x04C (R/W) Register */ + __IO uint32_t RhStatus; /*!< Offset: 0x050 (R/W) Register */ + __IO uint32_t RhPortStatus1; /*!< Offset: 0x054 (R/W) Register */ + __IO uint32_t RhPortStatus2; /*!< Offset: 0x05C (R/W) Register */ + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; /*!< Offset: 0x0FC (R/ ) Module ID / Version Reverence ID Register */ + /* USB On-The-Go Registers */ + __I uint32_t IntSt; /*!< Offset: 0x100 (R/ ) OTG Interrupt Status Register */ + __IO uint32_t IntEn; /*!< Offset: 0x104 (R/W) OTG Interrupt Enable Register */ + __O uint32_t IntSet; /*!< Offset: 0x108 ( /W) OTG Interrupt Set Register */ + __O uint32_t IntClr; /*!< Offset: 0x10C ( /W) OTG Interrupt Clear Register */ + __IO uint32_t StCtrl; /*!< Offset: 0x110 (R/W) OTG Status and Control Register */ + __IO uint32_t Tmr; /*!< Offset: 0x114 (R/W) OTG Timer Register */ + uint32_t RESERVED1[58]; + /* USB Device Interrupt Registers */ + __I uint32_t DevIntSt; /*!< Offset: 0x200 (R/ ) USB Device Interrupt Status Register */ + __IO uint32_t DevIntEn; /*!< Offset: 0x204 (R/W) USB Device Interrupt Enable Register */ + __O uint32_t DevIntClr; /*!< Offset: 0x208 ( /W) USB Device Interrupt Clear Register */ + __O uint32_t DevIntSet; /*!< Offset: 0x20C ( /W) USB Device Interrupt Set Register */ + /* USB Device SIE Command Registers */ + __O uint32_t CmdCode; /*!< Offset: 0x210 (R/W) USB Command Code Register */ + __I uint32_t CmdData; /*!< Offset: 0x214 (R/W) USB Command Data Register */ + /* USB Device Transfer Registers */ + __I uint32_t RxData; /*!< Offset: 0x218 (R/ ) USB Receive Data Register */ + __O uint32_t TxData; /*!< Offset: 0x21C ( /W) USB Transmit Data Register */ + __I uint32_t RxPLen; /*!< Offset: 0x220 (R/ ) USB Receive Packet Length Register */ + __O uint32_t TxPLen; /*!< Offset: 0x224 ( /W) USB Transmit Packet Length Register */ + __IO uint32_t Ctrl; /*!< Offset: 0x228 (R/W) USB Control Register */ + __O uint32_t DevIntPri; /*!< Offset: 0x22C (R/W) USB Device Interrupt Priority Register */ + /* USB Device Endpoint Interrupt Regs */ + __I uint32_t EpIntSt; /*!< Offset: 0x230 (R/ ) USB Endpoint Interrupt Status Register */ + __IO uint32_t EpIntEn; /*!< Offset: 0x234 (R/W) USB Endpoint Interrupt Enable Register */ + __O uint32_t EpIntClr; /*!< Offset: 0x238 ( /W) USB Endpoint Interrupt Clear Register */ + __O uint32_t EpIntSet; /*!< Offset: 0x23C ( /W) USB Endpoint Interrupt Set Register */ + __O uint32_t EpIntPri; /*!< Offset: 0x240 ( /W) USB Endpoint Interrupt Priority Register */ + /* USB Device Endpoint Realization Reg*/ + __IO uint32_t ReEp; /*!< Offset: 0x244 (R/W) USB Realize Endpoint Register */ + __O uint32_t EpInd; /*!< Offset: 0x248 ( /W) USB Endpoint Index Register */ + __IO uint32_t MaxPSize; /*!< Offset: 0x24C (R/W) USB MaxPacketSize Register */ + /* USB Device DMA Registers */ + __I uint32_t DMARSt; /*!< Offset: 0x250 (R/ ) USB DMA Request Status Register */ + __O uint32_t DMARClr; /*!< Offset: 0x254 ( /W) USB DMA Request Clear Register */ + __O uint32_t DMARSet; /*!< Offset: 0x258 ( /W) USB DMA Request Set Register */ + uint32_t RESERVED2[9]; + __IO uint32_t UDCAH; /*!< Offset: 0x280 (R/W) USB UDCA Head Register */ + __I uint32_t EpDMASt; /*!< Offset: 0x284 (R/ ) USB EP DMA Status Register */ + __O uint32_t EpDMAEn; /*!< Offset: 0x288 ( /W) USB EP DMA Enable Register */ + __O uint32_t EpDMADis; /*!< Offset: 0x28C ( /W) USB EP DMA Disable Register */ + __I uint32_t DMAIntSt; /*!< Offset: 0x290 (R/ ) USB DMA Interrupt Status Register */ + __IO uint32_t DMAIntEn; /*!< Offset: 0x294 (R/W) USB DMA Interrupt Enable Register */ + uint32_t RESERVED3[2]; + __I uint32_t EoTIntSt; /*!< Offset: 0x2A0 (R/ ) USB End of Transfer Interrupt Status Register */ + __O uint32_t EoTIntClr; /*!< Offset: 0x2A4 ( /W) USB End of Transfer Interrupt Clear Register */ + __O uint32_t EoTIntSet; /*!< Offset: 0x2A8 ( /W) USB End of Transfer Interrupt Set Register */ + __I uint32_t NDDRIntSt; /*!< Offset: 0x2AC (R/ ) USB New DD Request Interrupt Status Register */ + __O uint32_t NDDRIntClr; /*!< Offset: 0x2B0 ( /W) USB New DD Request Interrupt Clear Register */ + __O uint32_t NDDRIntSet; /*!< Offset: 0x2B4 ( /W) USB New DD Request Interrupt Set Register */ + __I uint32_t SysErrIntSt; /*!< Offset: 0x2B8 (R/ ) USB System Error Interrupt Status Register */ + __O uint32_t SysErrIntClr; /*!< Offset: 0x2BC ( /W) USB System Error Interrupt Clear Register */ + __O uint32_t SysErrIntSet; /*!< Offset: 0x2C0 ( /W) USB System Error Interrupt Set Register */ + uint32_t RESERVED4[15]; + /* USB OTG I2C Registers */ + union { + __I uint32_t I2C_RX; /*!< Offset: 0x300 (R/ ) OTG I2C Receive Register */ + __O uint32_t I2C_TX; /*!< Offset: 0x300 ( /W) OTG I2C Transmit Register */ + }; + __I uint32_t I2C_STS; /*!< Offset: 0x304 (R/ ) OTG I2C Status Register */ + __IO uint32_t I2C_CTL; /*!< Offset: 0x308 (R/W) OTG I2C Control Register */ + __IO uint32_t I2C_CLKHI; /*!< Offset: 0x30C (R/W) OTG I2C Clock High Register */ + __O uint32_t I2C_CLKLO; /*!< Offset: 0x310 ( /W) OTG I2C Clock Low Register */ + uint32_t RESERVED5[824]; + /* USB Clock Control Registers */ + union { + __IO uint32_t USBClkCtrl; /*!< Offset: 0xFF4 (R/W) OTG clock controller Register */ + __IO uint32_t OTGClkCtrl; /*!< Offset: 0xFF4 (R/W) USB clock controller Register */ + }; + union { + __I uint32_t USBClkSt; /*!< Offset: 0xFF8 (R/ ) OTG clock status Register */ + __I uint32_t OTGClkSt; /*!< Offset: 0xFF8 (R/ ) USB clock status Register */ + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +/** @brief Ethernet Media Access Controller (EMAC) register structure definition */ +typedef struct +{ + __IO uint32_t MAC1; /*!< Offset: 0x000 (R/W) MAC Configuration Register 1 */ + __IO uint32_t MAC2; /*!< Offset: 0x004 (R/W) MAC Configuration Register 2 */ + __IO uint32_t IPGT; /*!< Offset: 0x008 (R/W) Back-to-Back Inter-Packet-Gap Register */ + __IO uint32_t IPGR; /*!< Offset: 0x00C (R/W) Non Back-to-Back Inter-Packet-Gap Register */ + __IO uint32_t CLRT; /*!< Offset: 0x010 (R/W) Collision Window / Retry Register */ + __IO uint32_t MAXF; /*!< Offset: 0x014 (R/W) Maximum Frame Register */ + __IO uint32_t SUPP; /*!< Offset: 0x018 (R/W) PHY Support Register */ + __IO uint32_t TEST; /*!< Offset: 0x01C (R/W) Test Register */ + __IO uint32_t MCFG; /*!< Offset: 0x020 (R/W) MII Mgmt Configuration Register */ + __IO uint32_t MCMD; /*!< Offset: 0x024 (R/W) MII Mgmt Command Register */ + __IO uint32_t MADR; /*!< Offset: 0x028 (R/W) MII Mgmt Address Register */ + __O uint32_t MWTD; /*!< Offset: 0x02C ( /W) MII Mgmt Write Data Register */ + __I uint32_t MRDD; /*!< Offset: 0x030 (R/ ) MII Mgmt Read Data Register */ + __I uint32_t MIND; /*!< Offset: 0x034 (R/ ) MII Mgmt Indicators Register */ + uint32_t RESERVED0[2]; + __IO uint32_t SA0; /*!< Offset: 0x040 (R/W) Station Address 0 Register */ + __IO uint32_t SA1; /*!< Offset: 0x044 (R/W) Station Address 1 Register */ + __IO uint32_t SA2; /*!< Offset: 0x048 (R/W) Station Address 2 Register */ + uint32_t RESERVED1[45]; + __IO uint32_t Command; /*!< Offset: 0x100 (R/W) Command Register */ + __I uint32_t Status; /*!< Offset: 0x104 (R/ ) Status Register */ + __IO uint32_t RxDescriptor; /*!< Offset: 0x108 (R/W) Receive Descriptor Base Address Register */ + __IO uint32_t RxStatus; /*!< Offset: 0x10C (R/W) Receive Status Base Address Register */ + __IO uint32_t RxDescriptorNumber; /*!< Offset: 0x110 (R/W) Receive Number of Descriptors Register */ + __I uint32_t RxProduceIndex; /*!< Offset: 0x114 (R/ ) Receive Produce Index Register */ + __IO uint32_t RxConsumeIndex; /*!< Offset: 0x118 (R/W) Receive Consume Index Register */ + __IO uint32_t TxDescriptor; /*!< Offset: 0x11C (R/W) Transmit Descriptor Base Address Register */ + __IO uint32_t TxStatus; /*!< Offset: 0x120 (R/W) Transmit Status Base Address Register */ + __IO uint32_t TxDescriptorNumber; /*!< Offset: 0x124 (R/W) Transmit Number of Descriptors Register */ + __IO uint32_t TxProduceIndex; /*!< Offset: 0x128 (R/W) Transmit Produce Index Register */ + __I uint32_t TxConsumeIndex; /*!< Offset: 0x12C (R/ ) Transmit Consume Index Register */ + uint32_t RESERVED2[10]; + __I uint32_t TSV0; /*!< Offset: 0x158 (R/ ) Transmit Status Vector 0 Register */ + __I uint32_t TSV1; /*!< Offset: 0x15C (R/ ) Transmit Status Vector 1 Register */ + __I uint32_t RSV; /*!< Offset: 0x160 (R/ ) Receive Status Vector Register */ + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; /*!< Offset: 0x170 (R/W) Flow Control Counter Register */ + __I uint32_t FlowControlStatus; /*!< Offset: 0x174 (R/ ) Flow Control Status egister */ + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /*!< Offset: 0x200 (R/W) Receive Filter Control Register */ + __I uint32_t RxFilterWoLStatus; /*!< Offset: 0x204 (R/ ) Receive Filter WoL Status Register */ + __O uint32_t RxFilterWoLClear; /*!< Offset: 0x208 ( /W) Receive Filter WoL Clear Register */ + uint32_t RESERVED5; + __IO uint32_t HashFilterL; /*!< Offset: 0x210 (R/W) Hash Filter Table LSBs Register */ + __IO uint32_t HashFilterH; /*!< Offset: 0x214 (R/W) Hash Filter Table MSBs Register */ + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /*!< Offset: 0xFE0 (R/ ) Interrupt Status Register */ + __IO uint32_t IntEnable; /*!< Offset: 0xFE4 (R/W) Interrupt Enable Register */ + __O uint32_t IntClear; /*!< Offset: 0xFE8 ( /W) Interrupt Clear Register */ + __O uint32_t IntSet; /*!< Offset: 0xFEC ( /W) Interrupt Set Register */ + uint32_t RESERVED7; + __IO uint32_t PowerDown; /*!< Offset: 0xFF4 (R/W) Power-Down Register */ +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#ifdef __LPC17XX_REV00 +#define LPC_AHBRAM0_BASE (0x20000000UL) +#define LPC_AHBRAM1_BASE (0x20004000UL) +#else +#define LPC_AHBRAM0_BASE (0x2007C000UL) +#define LPC_AHBRAM1_BASE (0x20080000UL) +#endif +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) + +/* APB0 peripherals */ +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) + + +/** + * @} + */ + +#endif // __LPC17xx_H__
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/MTimer.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/MTimer.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,122 @@ +#include "Time.h" +#include "lpc17xx.h" +#include "MTimer.h" +#include "vibro.h" +#include "QEI.h" +#include "Global.h" +#include "SPI.h" +#include "InputOutput.h" + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////TIMER1//////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////// +/////////////////////èíèöèàëèçàöèÿ òàéìåðà 1 ///////////////////////// +////////////////////////////////////////////////////////////////////// +//unsigned int CountV=0; +//unsigned int CountVf=0 ; +unsigned int CountV31=0; +unsigned int CountV255=0 ; +unsigned int CountV64 = 0; + unsigned int init_timer (unsigned int TimerInterval ) + { + //start DAC prepearing for writing + LPC_TIM1->MR0 = TimerInterval; + LPC_TIM1->MCR = 3; /* Interrupt and Reset on MR1 */ + NVIC_EnableIRQ(TIMER1_IRQn); + //LPC_GPIO0->FIOSET |= (1<<5); + + return 0; + } + + +////////////////////////////////////////////////////////////////////// +/////////////////////////âêëþ÷åíèå òàéìåðà 1////////////////////////// +////////////////////////////////////////////////////////////////////// + void enable_timer1( void ) + { + LPC_TIM1->TCR = 1; + return; + } + + +////////////////////////////////////////////////////////////////////// +/////////////////////////ïðåðûâàíèå òàéìåðà 1////////////////////////// +////////////////////////////////////////////////////////////////////// + __irq void TIMER1_IRQHandler (void) + { +//LoopOn + + + // Init_SPI_Exchange();// CS + ResetCS(ADC); //prepare ADC for sampling + SetDAC(DAC); + + CountV255++; + CountV255 &= 0xff; + CountV31 =CountV255 & 0x1f; + CountV64 = CountV255 & 0x3f; + SetCS(ADC); //start ADC sampling + ResetDAC(DAC); + D_QEI(); + + cheng(); + +// CuruAngle = CuruAngle + Buff_32Point [CountVf] - 0xffff; + CuruAngle = CuruAngle + Buff_32Point [CountV255] - 0xffff; + + SPI_Exchange(); //×òåíèå ADS_SPI + + LPC_TIM1->IR = 1; + + } + + +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////TIMER2////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////// +/////////////////////èíèöèàëèçàöèÿ òàéìåðà 2 ///////////////////////// +////////////////////////////////////////////////////////////////////// + unsigned int Init_TIM2 (void) + { + LPC_TIM2->MR0 = 250; + LPC_TIM2->MCR = 3; /* Interrupt and Reset on MR0 */ + NVIC_EnableIRQ(TIMER2_IRQn); + return 1; + } + + + +////////////////////////////////////////////////////////////////////// +/////////////////////////âêëþ÷åíèå òàéìåðà 2////////////////////////// +////////////////////////////////////////////////////////////////////// + void enable_timer2(void) + { + LPC_TIM2->TCR = 1; + LPC_TIM2->TCR = 0x01; + } + + + +/////////////////////////////////////////////////////////////////////// +/////////////////////////ïðåðûâàíèå òàéìåðà 2////////////////////////// +/////////////////////////////////////////////////////////////////////// + __irq void TIMER2_IRQHandler (void) + { + LPC_TIM2->IR = 1; + + Global_Time++; + + Time_UART++; + + Time_vibro++; + + Time_1kHz++; + + VibroOut(); + + + } \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/MTimer.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/MTimer.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,8 @@ + +extern unsigned int init_timer (unsigned int TimerInterval ); +extern void enable_timer1( void ); +extern unsigned int Init_TIM2 (void); +extern void enable_timer2(void); +extern unsigned int CountV31; +extern unsigned int CountV255; +extern unsigned int CountV64 ; \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/PLC_reg.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/PLC_reg.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,353 @@ +/****************************************Copyright (c)**************************************************** +**--------------File Info--------------------------------------------------------------------------------- +** File name: PLC_reg.c +** Last modified Date: 2011-09-26 +** Last Version: V1.00 +** Descriptions: Routines for system of perimeter regulating unit +** +**-------------------------------------------------------------------------------------------------------- +** Created by: Electrooptica Incorp. +** Created date: 2011-09-26 +** Version: V1.00 +** Descriptions: +** +**-------------------------------------------------------------------------------------------------------- +*********************************************************************************************************/ +#include "mathDSP.h" +#include "CyclesSync.h" +#include "ThermoCalc.h" +#include "CntrlGLD.h" +#include "InputOutput.h" +#include <math.h> + +#define CONFIG_HFO_REG //r. èçìåíÿåì êîýôôèöèåíò ïåðåäà÷è êîíòóðà ÃÂ× îò íîìèíàëüíîãî íà âðåìÿ îáíóëåíèÿ +#define WP_TRANSITION_ENA // + + //e.--- constants for the CPLC regulator ------------------------------------------------------- //r.--- êîíñòàíòû äëÿ êîíòóðà ÑÐÏ ------------------------------------------------------- + +#define PLC_SHIFT (6) +#define PLC_PHASE_DET_SHIFT (18) //e. 18 - for analog output //r. 18 - äëÿ àíàëîãîâîãî + +#define PLC_RESET_THRESHOLD (-3276) //e. correspond to the voltage +1.2 Volts //r. ñîîòâåòñòâóåò íàïðÿæåíèþ +1.2 âîëüòà +#define WP_REG32MAX_SATURATION (32767 << PLC_SHIFT) +#define WP_REG32MIN_NEW_SATURATION (PLC_RESET_THRESHOLD << PLC_SHIFT) +#define WP_TMP_THRESHOLD (7) //e. temperature threshold, defining heats up or cool down the device //r. òåìïåðàòóðíûé ïîðîã, îïðåäåëÿþùèé íàãðåâàåòñÿ èëè îõëàæäàåòñÿ ïðèáîð + + +#define debugPLC + + int WP_reg32; + int WP_Phase_Det; //e. output of the phase detector of the CPLC (in a digital kind)//r. âûõîä ôàçîâîãî äåòåêòîðà ÑÐÏ (â öèôðîâîì âèäå) + int WP_reset_heating; //e. voltage of reset at heating //r. íàïðÿæåíèå ñáðîñà ïðè íàãðåâàíèè + int WP_reset_cooling; //e. voltage of reset at cooling //r. íàïðÿæåíèå ñáðîñà ïðè îõëàæäåíèè + int MaxDelayPLC; + int sin_func[100]; + +int phase_Digital; + +int WP_PhaseDetectorRate(int PhaseDetInput, int IntegrateTime); + +/****************************************************************************** +** Function name: init_PLC +** +** Descriptions: Initialization procedure for PLC regulator +** +** Parameters: None +** Returned value: None +** +******************************************************************************/ +void init_PLC(void) +{ + int i; + //( 1,2 âîëüòà) + if (Device_blk.Str.WP_reset < PLC_RESET_THRESHOLD) //e. íàïðÿæåíèå ïîñëå ñáðîñà íà íàãðåâàòåëå íå äîëæíî ïðåâûøàòü 1,2 âîëüòà. + //(èñõîäíîå çíà÷åíèå ðåãóëÿòîðà ÑÐÏ (ïîñëå ñáðîñà)) < (-3276). + { + Device_blk.Str.WP_reset = PLC_RESET_THRESHOLD + 1;//(-3275) + } +//íàïðÿæåíèå íà ÑÐÏ = (ìèí. çíà÷åíèå íà íàãðåâàòåëå + ìàõ. çíà÷åíèå íà íàãðåâàòåëå)/2 + Output.Str.WP_reg = (Device_blk.Str.WP_rup + Device_blk.Str.WP_rdw) >> 1; //e. WP_reg start voltage is (WP_rup - WP_rdw)/2 + + // íàïðÿæåíèå íà ÑÐÏ << 6 + WP_reg32 = Output.Str.WP_reg<<PLC_SHIFT; + + if ((Device_blk.Str.PI_b3>100)||(Device_blk.Str.PI_b3<10)) //e. Åñëè òðåáóåìàÿ ÷àñòîòà ìîäóëÿòîðà ÑÐÏ áîëüøå 1kHz èëè ìåíüøå 100Hz + Device_blk.Str.PI_b3 = 40; //e. Óñòàíîâèòü ÷àñòîòó â 250Hz (÷àñòîòà äðåáåçäåíèÿ) + + for (i = 0; i<Device_blk.Str.PI_b3; i++) //e. Ñêàíèðîâàíèå ÑÐÏ ñèãíàëà + { + float temp = sin((float)i*2.0*PI/(float)Device_blk.Str.PI_b3); /// âû÷èñëåíèå çíà÷åíèé ñèíóñà + /// äëÿ ÷àñòîòû ìîäóëÿòîðà ñðï (PI_b3), + sin_func[i] = (int)(temp*32767); /// è êàëèáðîâêà ýòèõ çíà÷åíèé äëÿ ÀÖÏ. + if (sin_func[i] < 0) + sin_func[i] += 65536; + } + + //e. calculation of filter coefficients for PLC +// 250 Hz 10 KHz + init_BandPass( 1.0/(float)Device_blk.Str.PI_b3, 10.0/(float)(DEVICE_SAMPLE_RATE_HZ), PLC); //ïîëîñîôîé ôèëüòð äëÿ âûäåëåíèÿ ÷àñòîòû êîëåáàíèÿ ìîäóëÿòîðà + //è îïðåäåëåíèå êîýôèöèåíòîâ(aPLC[0-2] è bPLC[0-2]) + //(äðåáåçäåíèå ñðï äëÿ îïðåäåëåíèÿ ãðåòü èëè îõëîæäàòü îñíîâíîé ýëåìåíò óïðàâëåíèÿ.) + + Device_blk.Str.WP_scl <<= 1; //e. during fist 10 seconds after start we state Device_blk.Str.WP_scl = 2*Device_blk.Str.WP_scl + // ïåðâûå 10 ñåêóíä ðàáîòàòü ñ êîýôèöèåíòîì ïåðåäà÷è * 2 + + MaxDelayPLC = Device_blk.Str.PI_b3>>1; //e. max expected delay for phase detector output +} // init_PLC + +/****************************************************************************** +** Function name: PLC_MeanderDelay +** +** Descriptions: Outgoing of the delayed meander signal for the PLC regulator +** +** parameters: Input value +** Returned value: Delayed value +** +******************************************************************************/ +int PLC_MeanderDelay(int flag) +{ + static int poz_counter = 0, neg_counter = 0, flg_delay; + + if (Device_blk.Str.WP_ref == 0) + { + return (flag); + } + + //e. check whether delay exceeds the greatest possible value //r. ïðîâåðêà íå ïðåâîñõîäèò ëè çàäåðæêà ìàêñèìàëüíî âîçìîæíóþ + if (Device_blk.Str.WP_ref > MaxDelayPLC) { Device_blk.Str.WP_ref = MaxDelayPLC; } + + if (flag) //e. outgoing poz_sin_flag flag, which delayed by the WP_ref //r. ôîðìèðîâàíèå çàäåðæàííîãî íà âåëè÷èíó WP_ref ôëàãà poz_sin_flag + { + neg_counter = 0; + poz_counter++; + } + else + { + poz_counter = 0; + neg_counter++; + } + if (poz_counter == Device_blk.Str.WP_ref) { flg_delay = 0; } + if (neg_counter == Device_blk.Str.WP_ref) { flg_delay = 1; } + return (flg_delay); +} +/****************************************************************************** +** Function name: clc_PLC +** +** Descriptions: Procedure of initial processing for the CPLC regulator +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void clc_PLC(void) +{ + static int is_zeroing = 0; + static int zero_delay = 0; +// static int WP_DelaySin_Array[21] = {0}; +// int phase_Digital; + int poz_sin_flag; + int poz_sin_flag_delayed; + + + static int plc_reset32; + static enum + { //r. ñîñòîÿíèå ëèíåéíîãî ïåðåõîäà ïðè îáíóëåíèè ÑÐÏ + FINISHED, //r. ëèíåéíûé ïåðåõîä çàâåðøåí + TRANS_HEATING, //r. ïåðåõîä âûïîëíÿåòñÿ ïðè íàãðåâàíèè + TRANS_COOLING //r. ïåðåõîä âûïîëíÿåòñÿ ïðè îõëàæäåíèè + } plc_transiton = FINISHED; + +// int i; + + if (Output.Str.WP_sin >= 32768) + { + poz_sin_flag = 0; + } + else + { + poz_sin_flag = 1; + } + + //r. ïîëîñîâîé ôèëüòð äëÿ êîíòóðà ÑÐÏ + WP_Phase_Det = PLC_PhaseDetFilt(/*Output.Str.WP_sin*/Input.StrIn.WP_sel); + + + if (WP_Phase_Det >0) + { //r. WP_sel>0 + phase_Digital = 1; + } + else + { + phase_Digital = -1; + } + // from this WP_Phase_Det - modulated signal like LIM_DIG + + poz_sin_flag_delayed = PLC_MeanderDelay(poz_sin_flag); + + if(poz_sin_flag_delayed) + { + WP_Phase_Det = -WP_Phase_Det; + phase_Digital = -phase_Digital; + } + // from this WP_Phase_Det - demodulated signal like LIDEM_DIG + + if (!is_zeroing) //r. Íå ïîðà âûïîëíÿòü îáíóëåíèå + { //r. íåò îáíóëåíèÿ + if ((WP_reg32 > (Device_blk.Str.WP_rup << PLC_SHIFT)) && IsHeating) //r. ïðîèñõîäèò íàãðåâàíèå + { + is_zeroing = 1; + //r. íàïðÿæåíèå ñáðîñà ïðè íàãðåâàíèè + WP_reset_heating = CPL_reset_calc(Device_blk.Str.WP_reset, Device_blk.Str.K_WP_rst_heating, Temp_Aver, Device_blk.Str.TemperNormal); + plc_transiton = TRANS_HEATING; + plc_reset32 = WP_reset_heating << PLC_SHIFT;; + + Device_blk.Str.HF_scl = Device_blk.Str.HF_scl_2; //r. èçìåíÿåì êîýôôèöèåíò ïåðåäà÷è êîíòóðà ÃÂ× îò íîìèíàëüíîãî íà âðåìÿ îáíóëåíèÿ + } + else if ((WP_reg32 < (Device_blk.Str.WP_rdw << PLC_SHIFT)) && !IsHeating) //r. îõëàæäåíèå + { + is_zeroing = 1; + //r. íàïðÿæåíèå ñáðîñà ïðè îõëàæäåíèè + WP_reset_cooling = CPL_reset_calc(Device_blk.Str.WP_reset2, Device_blk.Str.K_WP_rst_cooling, Temp_Aver, Device_blk.Str.TemperNormal); + + plc_transiton = TRANS_COOLING; + plc_reset32 = WP_reset_cooling << PLC_SHIFT; + + Device_blk.Str.HF_scl = Device_blk.Str.HF_scl_2; //r. èçìåíÿåì êîýôôèöèåíò ïåðåäà÷è êîíòóðà ÃÂ× îò íîìèíàëüíîãî íà âðåìÿ îáíóëåíèÿ + } + else //r. ïîðîãè íå ïðåâûøåíû, îáû÷íàÿ ðàáîòà êîíòóðà + WP_reg32 = L_mac(WP_reg32, phase_Digital, Device_blk.Str.WP_scl ); // WP_reg32 += phase_Digital * Device_blk.Str.WP_scl; + + } + else //r. ôëàã óñòàíîâëåí (1) - ðåæèì îáíóëåíèÿ + { + + if (plc_transiton != FINISHED) + { + if (plc_transiton == TRANS_HEATING) + { + + WP_reg32 = L_sub(WP_reg32, Device_blk.Str.WP_transition_step); // WP_reg32 -= Device_blk.Str.WP_transition_step; + if (WP_reg32 < plc_reset32) + { + zero_delay = 0; + plc_transiton = FINISHED; //r.false; + WP_reg32 = plc_reset32; + } + } + else // plc_transiton == TRANS_COOLING + { + WP_reg32 = L_add(WP_reg32, Device_blk.Str.WP_transition_step); // WP_reg32 += Device_blk.Str.WP_transition_step; + if (WP_reg32 > plc_reset32) + { + zero_delay = 0; + plc_transiton = FINISHED; //r.false; + WP_reg32 = plc_reset32; + } + } + } + else + + if (zero_delay < Device_blk.Str.WP_mdy) + { + zero_delay++; + } + else //e. resetting was completed //r. îáíóëåíèå çàêîí÷èëîñü + { + is_zeroing = 0; + //e. save the temperature for further comparison //r. çàïîìèíàåì òåìïåðàòóðó äëÿ äàëüíåéøåãî ñðàâíåíèÿ + // TempOfReset = Temp_Aver; //r.x. Temp5_Aver; //r. Tmp_Out[TSENS_NUMB]; // T4; + //r.x Zero_Numb_dbg++; // òàê ìîæíî ïîäñ÷èòûâàòü ÷èñëî îáíóëåíèé + + // DithFreqRangeCalc(); //e. calculation of range of the division factor for the dither drive frequency, depending on current temperature //r. ðàñ÷åò ãðàíèö êîýôôèöèåíòà äåëåíèÿ äëÿ ÷àñòîòû âèáðîïðèâîäà, çàâèñÿùèõ îò òåêóùåé òåìïåðàòóðû + } + } + + Saturation(WP_reg32, WP_REG32MAX_SATURATION, WP_REG32MIN_NEW_SATURATION); //e. the minimum corresponds to a small negative number, appropriate to PLC_RESET_THRESHOLD //r. ìèíèìóì ñîîòâåòñòâóåò íåáîëüøîìó îòðèöàòåëüíîìó ÷èñëó, ñîîòâ-ìó PLC_RESET_THRESHOLD + + + if ( loop_is_closed(WP_REG_ON) ) //e. the regulator loop is closed //r. êîíòóð çàìêíóò + { + Output.Str.WP_reg = (int)(WP_reg32 >> PLC_SHIFT); //e. we use as controlling - voltages of the integrator //r. èñïîëüçóåì êàê óïðàâëÿþùåå - íàïðÿæåíèÿ èíòåãðàòîðà + + } + else //e. the regulator loop is open //r. êîíòóð ðàçîìêíóò + { + WP_reg32 = Output.Str.WP_reg << PLC_SHIFT; //e. set the previous value of the WP_reg //r. ïðèñâàèâàåì ïðåäûäóùåå çíà÷åíèå WP_reg + + } + + //e. integartion of output of the PD of the CPLC regulator for the technological output on the Rate command //r. èíòåãðèðîâàíèå âûõîäà ÔÄ êîíòóðà ÑÐÏ äëÿ òåõíîëîãè÷åñêîãî âûâîäà ïî êîìàíäå Rate + + Output.Str.WP_pll = WP_PhaseDetectorRate( WP_Phase_Det, time_1_Sec); + +} // clc_PLC + +/****************************************************************************** +** Function name: Signal_2_Oscill +** +** Descriptions: Procedure of analog worm output +** +** parameters: Type of output +** Returned value: code to DAC +** +******************************************************************************/ +int Signal_2_Oscill() //e. the signal for the control by scope on DAC output (was DS) //r. ñèãíàë äëÿ êîíòðîëÿ îñöèëëîãðàôîì íà âûõîäå ÖÀÏ (áûâøèé ÄÓÏ) +{ + // Scope_Mode var not used now, reserved for future applications + return (-WP_Phase_Det << 2); +} // Signal_2_Oscill + +/****************************************************************************** +** Function name: clc_WP_sin +** +** Descriptions: Procedure of scan signal generating +** +** parameters: None +** Returned value: Current code for scan signal DAC of PLC +** +******************************************************************************/ +int clc_WP_sin(void) +{ + static int index = 0; + index++; + + if (index >= 40/*Device_blk.Str.PI_b3*/) + index = 0; +/* if (index > 20) + LPC_GPIO0->FIOSET = (1<<26); + else + LPC_GPIO0->FIOCLR = (1<<26); */ + DAC_Output(sin_func[index]); //output to DAC + + return (sin_func[index]); +} // clc_WP_sin + +/****************************************************************************** +** Function name: WP_PhaseDetectorRate +** +** Descriptions: Integartion of output of the PD of the CPLC regulator + for the technological output on the Rate command +** +** Parameters: Current PD magnitude, period of integration +** Returned value: Integrated magnitude of PD +** +******************************************************************************/ +int WP_PhaseDetectorRate(int PhaseDetInput, int IntegrateTime) +{ + + static int SampleAndHoldOut = 0; + static int WP_PhasDet_integr = 0;//, WP_PhasDetector = 0; + + if (IntegrateTime == DEVICE_SAMPLE_RATE_uks) + { + SampleAndHoldOut = (int)(WP_PhasDet_integr >> PLC_PHASE_DET_SHIFT); + WP_PhasDet_integr = 0; + } + else + { + WP_PhasDet_integr += PhaseDetInput; + } + return (SampleAndHoldOut); +} // WP_PhaseDetectorRate + +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Parameters.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Parameters.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,149 @@ +#include "CntrlGLD.h" +#include "lpc17xx.h" +#include "Parameters.h" +#include "el_lin.h" + +/****************************************************************************** +** Function name: LoadFlashParam +** +** Descriptions: Load of the parameters from the flash memory +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LoadFlashParam(unsigned source) +{ + if (source == FromFLASH) + { + while (LPC_GPDMACH3->CConfig & (1<<17)); //e. wait while DMA channel3 is busy + + if (LPC_GPDMA->RawIntErrStat & INT_ERR_TC) + LPC_GPDMA->IntErrClr |= INT_ERR_TC; //e. an errors found, reset interrupt + + else if (LPC_GPDMA->RawIntTCStat & INT_ERR_TC) + { //e. successful loading complete + LPC_GPDMA->IntTCClear |= INT_ERR_TC; + if (Device_blk.Str.Header_Word == HEADER_WORD_CONST) //e. flash contain valid data + return; + } + else + { //e. transfer was not started, start it immediatly + FlashDMA_Init(); + return; + } + init_DefaultParam(); //e. load parameters by default + } + else //e. source == ByDefault + init_DefaultParam(); //e. load parameters by default + + blt_in_test = ((uint32_t)FIRMWARE_VER << 8) | (Device_blk.Str.Device_SerialNumber & 0x00FF); +} +/****************************************************************************** +** Function name: init_DefaultParam +** +** Descriptions: Initialization of variables of computing procedures +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void init_DefaultParam(void) +{ + int i; + + Device_blk.Str.My_Addres = My_Addres_const; //r. 0x00; //e. direct set of the main device address //r. ïðÿìîå íàçíà÷åíèå îñíîâíîãî àäðåñà ó-âà + + Device_blk.Str.HF_ref = HF_REF_CONST; //e. set the reference voltage of the HFO //r. óñòàíîâèòü îïîðíîå íàïðÿæåíèå ÃÂ× + Device_blk.Str.HF_scl = HF_SCL_CONST; //e. set the gain factor of HFO integrator to ~ 0.001 //r. óñòàíîâèòü ê-ò ïåðåäà÷è èíòåãðàòîðà ÃÂ× ~ 0.001 + Device_blk.Str.HF_scl_2 = Device_blk.Str.HF_scl; + Device_blk.Str.HF_max = HF_MAX_CONST; //e. maximal value of the regulator //r. ìàêñèìàëüíîå çíà÷åíèå ðåãóëÿòîðà + + Device_blk.Str.HF_min = HF_MIN_CONST; //e. minimal value //r. ìèíèìàëüíîå çíà÷åíèå + Device_blk.Str.RI_ref= RI_REF_CONST; //e. set the reference voltage of DS to (=) 1,5 V //r. óñòàíîâèòü îïîðíîå íàïðÿæåíèå ÄÓÏ = 1,5  + Device_blk.Str.RI_scl= RI_SCL_CONST; //e. set the gain factor of DS integrator to ~ 0.01 //r. óñòàíîâèòü ê-ò ïåðåäà÷è èíòåãðàòîðà ÄÓÏ ~ 0.01 + + Device_blk.Str.WP_ref = WP_REF_CONST; //e. set the reference signal of CPLC to ~ 0,01 of maximal input value //r. óñòàíîâèòü îïîðíûé ñèãíàë ÑÐÏ ~ 0,01 âõîäíîãî ìàêñ. + Device_blk.Str.WP_scl = WP_SCL_CONST; //e. the gain factor of the CPLC regulator ~ 0,001 //r. ê-ò ïåðåäà÷è êîíòóðà ÑÐÏ ~ 0,001 + Device_blk.Str.WP_rup = WP_RUP_CONST; //e. upper value of the heater current //r. âåðõíåå çíà÷åíèå òîêà íàãðåâàòåëÿ + Device_blk.Str.WP_rdw = WP_RDW_CONST; //e. lower value of the heater current //r. íèæíåå çíà÷åíèå òîêà íàãðåâàòåëÿ + Device_blk.Str.WP_mdy = WP_MDY_CONST; //e. maximal delay of the reset //r. ìàêñèìàëüíàÿ çàäåðæêà îáíóëåíèÿ + + Device_blk.Str.VB_phs = VB_PHS_CONST; //e. the phase delay parameter of the PLL //r. ïàðàìåòð Phase_çàä. + Device_blk.Str.VB_scl = VB_SCL_CONST; //e. set the gain factor of the PLL of the dither drive //r. óñòàíîâèòü êîýôôèöèåíò ïåðåäà÷è ÑÐ× âèáðîïðèâîäà + Device_blk.Str.VB_Fdf_Lo = VB_FDF_LO_CONST; //e. set the F_del parameter //r. óñòàíîâèòü ïàðàìåòð Fçàä + Device_blk.Str.VB_Fdf_Hi = VB_FDF_HI_CONST; //e. set the F_del parameter (120000) //r. óñòàíîâèòü ïàðàìåòð Fçàä (120000) + Device_blk.Str.VB_Fsc = VB_FSC_CONST; //e. set the ScaleTau parameter //r. óñòàíîâèòü ïàðàìåòð ScaleTau + Device_blk.Str.VB_Tmin = VB_TMIN_CONST; //e. set minimal value of the Tau regulator //r. ìèíèìàëüíîå çíà÷åíèå ðåãóëÿòîðà Tau + Device_blk.Str.VB_Tmax = VB_TMAX_CONST; //e. set maximal value of the Tau reulator //r. ìàêñèìàëüíîå çíà÷åíèå ðåãóëÿòîðà Tau + + Device_blk.Str.VB_N = T_VIB_START; //e. ... dither drive //r. âèáðîïðèâîäà + Device_blk.Str.VB_Nmin = T_VIB_START - T_VIB_DELTA; //e. minimal value of the N regulator //r. ìèíèìàëüíîå çíà÷åíèå ðåãóëÿòîðà N + Device_blk.Str.VB_Nmax = T_VIB_START + T_VIB_DELTA; //e. maximal value of the N regulator //r. ìàêñèìàëüíîå çíà÷åíèå ðåãóëÿòîðà N + Device_blk.Str.VB_tau = L_VIB_START; //e. similarly load th pulse width of the dither drive //r. àíàëîãè÷íî çàãðóçèòü äëèòåëüíîñòü èìïóëüñîâ âèáðîïðèâîäà + + Device_blk.Str.VBN_Tzd = VBN_TZD_CONST; //e. adjusted period of {noise}[??] //r. çàäàííûé ïåðèîä îøóìëåíèÿ + Device_blk.Str.VBN_Ran = VBN_RAN_CONST; //e. the range of the random component //r. äèàïàçîí ñëó÷àéíîé ñîñòàâëÿþùåé + Device_blk.Str.VBN_k = VBN_K_CONST; //e. ajusted of the {noise}[??] constant //r. çàäàííàÿ êîíñòàíòà îøóìëåíèÿ + + Device_blk.Str.PI_a0 = PI_A0_CONST; //e. a0 coefficient of the temperature correction //r. êîýôôèöèåíò a0 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_a1 = PI_A1_CONST; //e. a1 coefficient of the temperature correction //r. êîýôôèöèåíò a1 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_a2 = PI_A2_CONST; //e. a2 coefficient of the temperature correction //r. êîýôôèöèåíò a2 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_a3 = PI_A3_CONST; //e. a3 coefficient of the temperature correction //r. êîýôôèöèåíò a3 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_a4 = PI_A4_CONST; //e. a4 coefficient of the temperature correction //r. êîýôôèöèåíò a4 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_a5 = PI_A5_CONST; //e. a5 coefficient of the temperature correction //r. êîýôôèöèåíò a5 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_a6 = PI_A6_CONST; //e. a6 coefficient of the temperature correction //r. êîýôôèöèåíò a6 òåìïåðàòóðíîé êîððåêöèè + + Device_blk.Str.PI_b1 = PI_B1_CONST; //e. b1 coefficient of the temperature correction //r. êîýôôèöèåíò b1 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_b2 = PI_B2_CONST; //e. b2 coefficient of the temperature correction //r. êîýôôèöèåíò b2 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_b3 = PI_B3_CONST; //e. b3 coefficient of the temperature correction //r. êîýôôèöèåíò b3 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_b4 = PI_B4_CONST; //e. b4 coefficient of the temperature correction //r. êîýôôèöèåíò b4 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_b5 = PI_B5_CONST; //e. b5 coefficient of the temperature correction //r. êîýôôèöèåíò b5 òåìïåðàòóðíîé êîððåêöèè + Device_blk.Str.PI_b6 = PI_B6_CONST; //e. b6 coefficient of the temperature correction //r. êîýôôèöèåíò b6 òåìïåðàòóðíîé êîððåêöèè + + Device_blk.Str.PI_Fsc = PI_FSC_CONST; //e. the S_ds scale parameter //r. ìàñøòàáíûé êîýôôèöèåíò Säóï + Device_blk.Str.PI_Fb0 = PI_FB0_CONST; //e. the B_ds zero shift of the DS //r. ñìåùåíèå íóëÿ ÄÓÏà Bäóï + Device_blk.Str.PI_scl = PI_SCL_CONST; //e. the Scale scale coefficient of the gyro //r. ìàñøòàáíûé êîýôô. ãèðîñêîïà Scale + Device_blk.Str.PI_bia = PI_BIA_CONST; //e. the Bias zero shift of the gyro //r. ñìåùåíèå íóëÿ ãèðîñêîïà Bias + + for (i = 0; i <6 ; i++) + { + Device_blk.Str.Tmp_scal[i] = TMP_SCALE; + Device_blk.Str.Tmp_bias[i] = TMP_BIAS; + } + Device_blk.Str.WP_transition_step = WP_TRANS_STEP; + Device_blk.Str.WP_reset = WP_RESET_CONST; //e. default initial position = 0 //r. èñõîäíîå ïîëîæåíèå ïî óìîë÷àíèþ = 0 + Device_blk.Str.WP_reset2 = WP_RESET2_CONST; + Device_blk.Str.Gain_Ph_A = G_PHOTO_STRA; //e. load the initial value of the gain factor of photodetectors channels//r. çàãðóçèòü íà÷àëüíîå çíà÷åíèå ê-òà óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêîâ + Device_blk.Str.Gain_Ph_B = G_PHOTO_STRB; + + Device_blk.Str.Device_SerialNumber = DEVICE_SN; //e. serial number of the device is by default written down in the register of self-testing //r. ñåðèéíûé íîìåð ïðèáîðà ïî óìîë÷àíèþ çàïèñûâàåì â ðåãèñòð ñàìîòåñòèðîâàíèÿ + +} // init_DefaultParam +/****************************************************************************** +** Function name: FlashDMA_Init +** +** Descriptions: Initialisation of DMA channel for flash reading +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void FlashDMA_Init() +{ + LPC_GPDMACH3->CConfig &= ~DMAChannelEn; + + LPC_GPDMA->IntTCClear = DMA3_IntTCClear; + LPC_GPDMA->IntErrClr = DMA3_IntTCClear; + + /* Ch3 set for M2M transfer from Flash to RAM. */ + LPC_GPDMACH3->CSrcAddr = 0x40000; //e. address of device parameter block in flash memory (22 sec) + LPC_GPDMACH3->CDestAddr = (uint32_t)&(Device_blk.Array);//e. address of device parameter block in RAM + + LPC_GPDMACH3->CControl = ((sizeof(Device_blk.Array))>>2)|SrcBSize_1 |DstBSize_1 + |SrcWidth_32b |DstWidth_32b |SrcInc |DstInc |TCIntEnabl; + + LPC_GPDMACH3->CConfig = MaskTCInt |MaskErrInt|DMA_MEMORY |DMA_MEMORY |(M2M << 11)| DMAChannelEn; + + return; +}
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/Parameters.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/Parameters.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,57 @@ +#ifndef UHOST +#define UHOST +/*e.**************************************************** +* Constants for the uHost card * +********************************************************/ +/*r.**************************************************** +* Êîíñòàíòû äëÿ ïëàòû uHost * +********************************************************/ +/*e. file for the C code */ +/*r. ôàéë äëÿ êîäà íà Ñ */ + +#define FIRMWARE_VER 0x00 //e. firmware version number //r. íîìåð âåðñèè ìèêðîïðîãðàììû + + //e. ====================== registers of the system controller of the DSP card ================ //r. ====================== ðåãèñòðû ñèñòåìíîãî êîíòðîëëåðà ïëàòû DSP ================ +#define Sys_RgE 0x07fb //e. the line1_err register of line errors //r. ðåãèñòð îøèáîê ëèíèè line1_err +#define Sys_RgR 0x07fc //e. the register of a mode of the system (only write) //r. ðåãèñòð ðåæèìà ñèñòåìû (òîëüêî çàïèñü) +#define Sys_RgS 0x07fc //e. the register of a status of the system (only read) //r. ðåãèñòð ñòàòóñà ñèñòåìû (òîëüêî ÷òåíèå) +#define Trm_data 0x07fd //e. the data stack of the transmitter //r. ñòåê äàííûõ ïåðåäàò÷èêà +#define Rcv_data 0x07fd //e. the data stack of the receiver //r. ñòåê äàííûõ ïðèåìíèêà +#define Rcv_cntr 0x07fe //e. the counter of the received bytes //r. ñ÷åò÷èê ïðèíÿòûõ áàéò ïðèåìíèêà + + //e. ====================== bits of the Sys_RgS status register ========================= //r. ====================== áèòû ðåãèñòðà ñîñòîÿíèÿ Sys_RgS ========================= +#define RCV_RDY_MASK 0x0040 //e. a mask of the readiness bit of the receiver //r. ìàñêà áèòà ãîòîâíîñòè ïðèåìíèêà +#define RCV_FERR_MASK 0x0020 //e. a mask of the "format error" bit //r. ìàñêà áèòà "îøèáêà ôîðìàòà" +#define RCV_TOUT_MASK 0x0010 //e. a mask of the "time-out" bit //r. ìàñêà áèòà "òàéì-àóò" +#define RCV_RFUL_MASK 0x0008 //e. a mask of the "stack is full" bit//r. ìàñêà áèòà "ñòåê ïîëîí" +#define RCV_FERR 0x0020 //e. a mask of the "format error" bit //r. ìàñêà áèòà "îøèáêà ôîðìàòà" +#define RCV_TOUT 0x0010 //e. a mask of the "time-out" bit //r. ìàñêà áèòà "òàéì-àóò" +#define RCV_RFUL 0x0008 //e. a mask of the "stack is full" bit//r. ìàñêà áèòà "ñòåê ïîëîí" + +#define INT_ERR_TC 0x00000008 + +#define FromFLASH 0x00003 +#define ByDefault 0x00001 + + + + +#define SetV1 LPC_GPIO1->FIOSET=(1<<25); +#define ClrV1 LPC_GPIO1->FIOCLR = (1<<25); +#define SetV2 LPC_GPIO1->FIOSET = (1<<28); +#define ClrV2 LPC_GPIO1->FIOCLR = (1<<28); +#define LoopOn LPC_GPIO1->FIOSET = (1<<30); +#define LoopOff LPC_GPIO1->FIOCLR = (1<<30); +#define StartV1 0 +#define StartV2 15 +#define TIME_INTERVAL (7812) + + + +extern uint32_t blt_in_test; + +void LoadFlashParam(unsigned ); +void FlashDMA_Init(void); +void init_DefaultParam(void); +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/QEI.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/QEI.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,117 @@ +#include "lpc17xx.h" +#include "QEI.h" +#include "vibro.h" +#include "MTimer.h" + + int Pulse_midl = 0; + int PulseHalf = 0; + int CuruAngle = 0; + int Dif_QEI; +int FFF=0;//äëÿ çàïëàòêè + + int Pulse_8Point = 0; + int Pulse_16Point = 0; + int Pulse_32Point = 0; + int Pulse_16PointD = 0; + unsigned int Iras=0,Temp_F_ras=0; + int yy = 0; + + + unsigned int Buff_32Point [256]; + unsigned int Buff_16Point [256]; + unsigned int Buff_16PointD [256]; + unsigned int Buff_8Point [256]; + unsigned int Buff_1Point [256]; + unsigned int Buff_Restored_sin [256]; + int unsigned Cur_QEI = 0, Last_QEI=0; + + + void D_QEI(void) + { + Dif_QEI=0; + + + Cur_QEI = LPC_QEI->POS & 0xFFFF; // ñ÷èòûâàíèå òåêóùåãî çíà÷åíèÿ ýíêîäåðà. + Dif_QEI = (Cur_QEI - Last_QEI); // ïîëó÷åíèå ïðèðàùåíèÿ.() + Last_QEI = Cur_QEI; // çàïèñü òåêóùåãî çíà÷åíèÿ ýíêîäåðà â ðåãèñòð ïðåäûäóùåãî çíà÷åíèÿ. + + + if (Dif_QEI < -0xfff) Dif_QEI += 0x10000; // îáðàáîòêà ïðîõîäà çíà÷åíèÿ ÷åðåç íîëü + if (Dif_QEI > 0xfff) Dif_QEI -= 0x10000; // îáðàáîòêà ïðîõîäà çíà÷åíèÿ ÷åðåç íîëü + + + Buff_1Point[CountV255] = (unsigned int) (Dif_QEI + 0xffff);// íàêîïëåíèå â áóôåð åäåíè÷íûõ çíà÷åíèé ïðèðàùåíèÿ ïî êàæäîìó òàêòó. + + //////////////////////////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////////////////// + + if (LPC_QEI->STAT) //e. "+" direction //r. ñòàëè âðàùàòüñÿ â "+" ñòîðîíó + { + Main.Cnt_Mns = Dif_QEI; + } + else + { + Main.Cnt_Pls = -Dif_QEI; + } + ////////// ???? Çàïëàòêà + ////////// ???? Ïðîáëåìà íà÷àëüíîãî çàïîëíåíèÿ áóôåðîâ + ////////////////////////////////////////////////////////////////////////////////////////////// + if(FFF==1) // åñëè ïðîøëî 32 òàêòà âèáðî ïîäâåñà íà÷àòü çàïîëíÿòü îñòàëüíûå áóâåðû. + { + Pulse_8Point += Buff_1Point[CountV255]; + Pulse_8Point -= Buff_1Point[(CountV255-8) & 0xff]; // çàïîëíåíèå áóôåðà íàêîïëåíûõ ïðèðàùåíèé çà 8 òàêòîâ + Buff_8Point[CountV255] = (unsigned int) (Pulse_8Point + 0xffff); + + Pulse_16Point += Buff_1Point[CountV255]; + Pulse_16Point -= Buff_1Point[(CountV255-16) & 0xff]; // çàïîëíåíèå áóôåðà íàêîïëåíûõ ïðèðàùåíèé çà 16 òàêòîâ + Buff_16Point[CountV255] = (unsigned int) (Pulse_16Point + 0xffff); + + Pulse_32Point += Buff_1Point[CountV255]; + Pulse_32Point -= Buff_1Point[(CountV255-32) & 0xff]; // çàïîëíåíèå áóôåðà íàêîïëåíûõ ïðèðàùåíèé çà 32 òàêòîâ + Main.Cnt_Dif = (Pulse_32Point+ 0xffff); + Buff_32Point[CountV255] = (unsigned int) (Pulse_32Point + 0xffff); + + Pulse_16PointD += Buff_1Point[CountV255]; + Pulse_16PointD -= Buff_1Point[(CountV255-16) & 0xff]; // çàïîëíåíèå áóôåðà íàêîïëåíûõ ïðèðàùåíèé çà 16 òàêòîâ Äâîéíûç + Pulse_16PointD += Buff_1Point[(CountV255-32) & 0xff]; // + Pulse_16PointD -= Buff_1Point[(CountV255-48) & 0xff]; // ç + + Buff_16PointD[CountV255] = (unsigned int) (Pulse_16PointD + 0xffff); + + +// Buff_Restored_sin [CountVf]= (unsigned int)( ((Buff_16Point[CountVf]*2)) - Buff_32Point[CountVf] ); + + Buff_Restored_sin [CountV255]= (unsigned int)( Buff_16PointD [ CountV255] + 65536 - Buff_32Point[CountV255] ); + + + + if(Buff_32Point[CountV255]>0) + { + Temp_F_ras += Buff_32Point[CountV255]; + } + else if ((CountV255 & 0x1f)==0) + { + Main.F_ras=Temp_F_ras; + Temp_F_ras=0; + } + else + { + Temp_F_ras -= Buff_32Point[CountV255]; + } + + //unsigned int T_Vib; + + } + else if(CountV255 == 255) + { + FFF=1;//âðåìåííàÿ çàïëàòêà äëÿ ïàóçû ïåðåä çàïîëíåíèåì îñòàëüíûõ áóôåðîâ + for (yy = 0; yy < 256; yy++ ) + { + Buff_1Point [yy] = 0xffff; + Buff_16Point [yy] = 0xffff; + Buff_32Point [yy] = 0xffff; + Buff_16PointD [yy] = 0xffff; + } + + } + }
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/QEI.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/QEI.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,23 @@ +#ifndef QEI_H +#define QEI_H + +extern int Pulse_midl; +extern int PulseHalf; +extern int PulseQuad; +extern int CuruAngle; + +extern unsigned int Cur_QEI; +extern int Dif_QEI; +extern int Pulse_8Point ; +extern int Pulse_16Point ; +extern int Pulse_32Point ; + + +extern unsigned int Buff_32Point[]; +extern unsigned int Buff_16Point[]; +extern unsigned int Buff_16PointD[]; +extern unsigned int Buff_8Point[]; +extern unsigned int Buff_1Point[]; +extern unsigned int Buff_Restored_sin[]; +extern void D_QEI(void); +#endif
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/SIP.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/SIP.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,262 @@ +#include "mathDSP.h" +#include "SIP.h" +#include "CyclesSync.h" +#include "CntrlGLD.h" +#include "InputOutput.h" +#include "ThermoCalc.h" +#include "el_lin.h" + + + uint32_t Old_Cnt_Vib = 0; + uint32_t Old_Cnt = 0; + int32_t RefMeand_Cnt_Dif; + int32_t PSdif_sum_Vib_32 = 0; + __int64 PSdif_sum_Vib_64 = 0; + int32_t dif_Curr_32_Ext; //r. ðàçíîñòü (÷èñëî) äëÿ ðåæèìà âíåøíåé çàùåëêè + int32_t dif_Curr_32_previous; //e. Previous (in comparison with Dif_Curr_32) number //r. ïðåäûäóùåå (ïî ñðàâíåíèþ ñ Dif_Curr_32) ÷èñëî + int32_t temp22=0; +//+++++++++++++++++++++++++++++++INPUT DATA++++++++++++++++++++++++++++++++++++++++++++++++ +uint32_t Curr_Cnt_Vib; +uint32_t Cnt_curr; + +//+++++++++++++++++++++++++++++++variables for output++++++++++++++++++++++++++++++++++++++ +int32_t Dif_Curr_Vib; //e. current difference output for dithering control in LightUp mode and Dither regulator +int32_t Dif_Curr_32; //e. current difference without dithering for dithering control + +#if (defined GLOBALRATE)//íå âõîäèò + +//variables for rate mode + int32_t cntPls_sum_32; + ñññ int32_t last_Cnt_Plus; + int32_t dif_sum_32; + int32_t Cnt_Pls; + int32_t Cnt_Mns; + int32_t preLast_Cnt_Plus; + // uint32_t sumCnt_Mns = 0; + //uint32_t sumCnt_Pls = 0; + extern int32_t dif_cur_test[30]; + extern unsigned ii; + uint32_t halfPeriod = 0; +#endif + +void ResetBitsOfWord(int * x32, int truncate_bits) +{ + int hi_part; + + hi_part = *x32 >> truncate_bits; + *x32 -= hi_part << truncate_bits; //r. îñòàâëÿåì ìëàäøèå 16 áèò +} +/****************************************************************************** +** Function name: interpolation +** +** Descriptions: êîëè÷åñòâî èòåðïîëÿöèé äî ïîÿâëåíèÿ âíåøíåé çàùåëêè +** +** Returned value: Number in moment of external latch appearing +** parameters: y_curr - current number, y_prev - number at one cycle before time +** x_interp - moment of external latch appearing, + +** Precision of interpolation is 1/8 of impulse (3 digits after point in 14.18 format) +******************************************************************************/ +int interpolation(int y_curr, int x_interp) +{ + __int64 temp,temp3; + + temp = (__int64)y_curr *(__int64)x_interp; + temp /= PrevPeriod; // void ServiceTime(void) ||| PrevPeriod = LPC_PWM1->MR0; ||| (CyclesSync.c) + + temp3 = (__int64)y_curr *(__int64)(x_interp+1); + temp3 /= PrevPeriod; + temp22 = (int)temp3; + + return ((int)temp); +} // interpolation +/****************************************************************************** +** Function name: clc_Pulses +** +** Descriptions: Processing of information from SPOI +** +** parameters: None +** Returned value: None +** +******************************************************************************/ + +void clc_Pulses() +{ + +#if (!defined GLOBALRATE) + static int32_t cntPls_sum_32; + static int32_t last_Cnt_Plus; + static int32_t dif_sum_32; + static int32_t Cnt_Pls; + static int32_t Cnt_Mns; + static int32_t preLast_Cnt_Plus; +#endif + + Dif_Curr_Vib = Curr_Cnt_Vib - Old_Cnt_Vib; //Âû÷èñëåíèå ïðèðàùåíèÿ òåêóùåãî ñ÷åò÷èêà èìïóëüñîâ. + + Old_Cnt_Vib = Curr_Cnt_Vib; //ñîõðàíåíèå òåêóùåãî ñ÷åò÷èêà èìïóëüñîâ äëÿ ñëåäóþùåãî öèêëà èçìåðåíèé + + + Cnt_Overload(Dif_Curr_Vib, INT32MAX_DIV2, INT32MIN_DIV2); //ïðîâåðêà íà ïåðåïîëíåíèå (Dif_Curr_Vib). + // Uin UpSat DwnSat + + //#define Cnt_Overload(Uin, UpSat, DwnSat) +/* if (Uin > UpSat) + + { + Uin -= INT32_MAX; + } + if (Uin < DwnSat) + { + Uin += INT32_MAX; + } */ + + + Dif_Curr_32 = VibroReduce(Dif_Curr_Vib << SHIFT_TO_FRACT); // Òî÷íîñòü ôèëüòðàöèè 1/(2^18) + + + + + switch (RgConB) //r. äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ + { + case RATE_VIBRO_1: //r. ðàçíîñòü âèáðîñ÷åò÷èêîâ ïîñëå ôèëüòðà ñêîëüçÿùíãî ñðåäíåãî + + if (Latch_Rdy) //e. latch has arrived + { + //dif_Curr_32_Ext ðàçíîñòü (÷èñëî) äëÿ ðåæèìà âíåøíåé çàùåëêè + dif_Curr_32_Ext = interpolation(Dif_Curr_32, LatchPhase ); //èíòåðïîëÿöèÿ + Output.Str.Tmp_Out[2] = (int)((Curr_Cnt_Vib>>16)& 0xffff); + Output.Str.Tmp_Out[3] = (int)(Curr_Cnt_Vib & 0xffff); + //r. äîáàâëÿåì ê íàêîïëåííîé ñóììå èíòåðïîëèðîâàííûé îòñ÷åò âíåøíåé çàùåëêè + PSdif_sum_Vib_32 += dif_Curr_32_Ext; + PSdif_sum_Vib_64 += dif_Curr_32_Ext; //e. receive last data + //count--; + + //r. ïîäãîòîâèòü ÷èñëî äëÿ âûäà÷è + Output.Str.BINS_dif = PSdif_sum_Vib_32 - TermoCompens_Sum; //r. èç íàêîïëåííîãî ÷èñëà âû÷èòàåì íàêîïëåííóþ òåðìîêîìïåíñàöèîííóþ ñîñòàâëÿþùóþ + Output.Str.PS_dif = Output.Str.BINS_dif >> 16; + LatchPhase = INT32_MAX; //INT32_MAX=2147483647 //in Latch_Event it's indicator of latch appearing + Output.Str.SF_dif = PSdif_sum_Vib_64; + TermoCompens_Sum = 0; //r. îáíóëÿåì íàêîïëåííóþ òåðìîêîìïåíñàöèþ äëÿ íà÷àëà íîâîãî öèêëà íàêîïëåíèÿ + + if ((Device_Mode == DM_EXT_LATCH_DELTA_BINS_PULSE)||((Device_Mode == DM_EXT_LATCH_DELTA_SF_PULSE) && Ext_Latch_ResetEnable)) + { + PSdif_sum_Vib_32 = 0; //r. èíèöèàëèçèðîâàòü íîâûé öèêë èçìåðåíèÿ ïî çàùåëêå + PSdif_sum_Vib_64 = 0; + } + else + ResetBitsOfWord(&PSdif_sum_Vib_32, 16); + + dif_Curr_32_Ext = Dif_Curr_32 - temp22;//dif_Curr_32_Ext; + + PSdif_sum_Vib_32 += dif_Curr_32_Ext; // preserve rest of counters difference for next measure cycle: PSdif_sum_Vib_32 += Dif_Curr_32 - dif_Curr_32_Ext; + PSdif_sum_Vib_64 += dif_Curr_32_Ext; //ñîõðàíèòü îñòàëüíûå ñ÷åò÷èêè ðàçíèöû äëÿ ñëåäóþùåãî òàêòà öèêëà + + } + else //r. çàùåëêè íà íàñòîÿùèé ìîìåíò íå áûëî + { + //r. ïðîäîëæàåì íàêàïëèâàòü ñóììó èç âíóòðåííèõ îòñ÷åòîâ + PSdif_sum_Vib_32 += Dif_Curr_32; // PSdif_sum_Vib_32 += Dif_Curr_32 ; + PSdif_sum_Vib_64 += Dif_Curr_32; //e. sum for scale factor measurement mode + } + + dif_Curr_32_previous = Dif_Curr_32; //r. çàïîìèíàåì ïðåäûäóùåå ÷èñëî + break; + + case RATE_REPER_OR_REFMEANDR: + + if (data_Rdy & HALF_PERIOD) //e. calculate Cnt_Mns or Cnt_Pls + { + RefMeand_Cnt_Dif = Cnt_curr - Old_Cnt; + Old_Cnt = Cnt_curr; + // LPC_GPIO2->FIOCLR = 0x10; + Cnt_Overload(RefMeand_Cnt_Dif, INT32MAX_DIV2, INT32MIN_DIV2); + + if (LPC_QEI->STAT) //e. "+" direction //r. ñòàëè âðàùàòüñÿ â "+" ñòîðîíó + { + //sumCnt_Mns += -RefMeand_Cnt_Dif; //e. accumulation during 1 sec + Cnt_Mns = RefMeand_Cnt_Dif; + } + else + { + //r. ñòàëè âðàùàòüñÿ â "-" ñòîðîíó + //sumCnt_Pls += RefMeand_Cnt_Dif; //e. accumulation during 1 sec + Cnt_Pls = -RefMeand_Cnt_Dif; + } + + // UART1_SendByte((dif_sum_32>>8) & 0xff); + // UART1_SendByte((dif_sum_32) & 0xff); + + if (data_Rdy & WHOLE_PERIOD) //e. period of vibro elapsed + { + // LPC_GPIO2->FIOSET = 0x10; + last_Cnt_Plus = Cnt_Pls; + dif_sum_32 += Cnt_Pls - Cnt_Mns; + } + data_Rdy &= ~RESET_PERIOD; + } + if (Latch_Rdy) //e it's time for output + { + LatchPhase = INT32_MAX; + + Output.Str.Tmp_Out[2] = (int)((Curr_Cnt_Vib>>16)& 0xffff); + Output.Str.Tmp_Out[3] = (int)(Curr_Cnt_Vib & 0xffff); + + cntPls_sum_32 += last_Cnt_Plus - preLast_Cnt_Plus; + + Output.Str.Cnt_Dif = dif_sum_32; + Output.Str.Cnt_Dif += cntPls_sum_32 >> 1; + + dif_sum_32 = 0; //r. è ñáðîñèòü ðåãèñòðû íàêîïëåíèÿ + ResetBitsOfWord(&cntPls_sum_32, 1); //r. îñòàâëÿåì ìëàäøèé ðàçðÿä, ÷òîáû íå òåðÿëàñü òî÷íîñòü ïðè ñóììèðîâàíèè + preLast_Cnt_Plus = last_Cnt_Plus; //r. òåêóùèé ïîñëåäíèé îòñ÷åò ñòàë ïðåäûäóùèì + + Output.Str.Cnt_Mns = Cnt_Mns;//sumCnt_Mns; //e. rewrite accumulated data to output + Output.Str.Cnt_Pls = Cnt_Pls;//sumCnt_Pls; + + //sumCnt_Mns = 0; //e. prepare for new accumulation + //sumCnt_Pls = 0; + } + break; // RATE_REPER_OR_REFMEANDR + } + //e. WP_scope1, WP_scope2 - variables for control in the Rate3 mode //r. WP_scope1, WP_scope2 - ïåðåìåííûå äëÿ êîíòðîëÿ â ðåæèìå rate3 + Output.Str.WP_scope1 = Dif_Curr_Vib; + Output.Str.WP_scope2 = (Dif_Curr_32 >> (SHIFT_TO_FRACT-2)); //r. 2 äðîáíûõ ðàçðÿäà îñòàâëÿåì äëÿ áîëüøåé íàãëÿäíîñòè ïðè àíàëèçå ñèãíàëà rate3 +} + // clc_Pulses + + + /****************************************************************************** +** Function name: SOI_Init +** +** Descriptions: Quadrature encoder initialization. +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void SOI_Init(void) +{ + LPC_SC->PCONP |= (1<<18);//0x00040000; âêëþ÷åíèå êâàäðàòóðíîãî ýíêîäåðà. + LPC_SC->PCLKSEL1 |= 0x00000001; // âûáîð ÷àñòîòû äëÿ êâ.ý. CLK=100MHz + LPC_PINCON->PINSEL3 &= ~0x4100; + LPC_PINCON->PINSEL3 |= 0x4100; //P1.20, p1.23 óñòàíîâèòü êàê âõîäû êâ.ý + LPC_PINCON->PINMODE3 |= 0x3C300; //P1.20, p1.23, p1.24 ??are pulled-down??(ïðèòÿíóòü ê ïèòàíèþ)???? + + LPC_QEI->MAXPOS = MAX_QEI_CNT; //LPC_QEI->"ðåãèñòîð ìàêñèìàëüíîãî ïîëîæåíèÿ" = 2147483646 + LPC_QEI->FILTER = 2; // ôèëüòð( ?? ) + LPC_QEI->CON = 0xF; //ñáðîñèòü â íîëü âñå ñ÷åò÷èêè êâ.ý. (ñêîðîñòü, íàïðàâëåíèå, ïîçèöèþ è òä) + LPC_QEI->CONF = (0<<2) |(0<<1); //Quadrature inputs, no inverting,only A pulses are counted + + LPC_QEI->CLR = 0x1fff; //r. ñáðîñèòü âñå ïðåðûâàíèÿ + LPC_QEI->IEC = 0x1fff; //r. çàïðåòèòü ïðåðûâàíèå ïðè èçìåíåíèè íàïðàâëåíèÿ + + NVIC_SetPriority(QEI_IRQn, 0); + NVIC_EnableIRQ(QEI_IRQn); + return; + } + + +/****************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/SIP.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/SIP.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,26 @@ + +#define MAX_QEI_CNT 2147483646 //e .limit of input counter (INT32_MAX - 1) +#define INT32MAX_DIV2 1073741823 //e. 0.5*MAX_QEI_CNT +#define INT32MIN_DIV2 -1073741823 //e. -0.5*MAX_QEI_CNT + +#define SHIFT_TO_FRACT (18) //e. shift for converting integer to float (14.18) format //r. ñäâèã äëÿ ïðåîáðàçîâàíèÿ öåëîãî ÷èñëà ê äðîáíîìó ôîðìàòó 14.18 + +//#define OUTFREQ +//#define RATESIM +//#define GLOBALRATE +#define CONSTCYCLE +//#define DITHERSIM + +extern unsigned Cnt_curr; +extern unsigned Curr_Cnt_Vib; +extern int Dif_Curr_Vib; +extern int Dif_RG_vib_32; +extern int Dif_Curr_32; +extern __int64 Dif_RG_vib_64; + +extern int WP_scope3, WP_scope4; +/* +extern int Dif_Curr_Array[8]; +extern int Dif_Filt_Array[8]; +*/ +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/SPI.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/SPI.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,101 @@ +#include "Global.h" +#include "SPI.h" +#include "stdlib.h" +#include "lpc17xx.h" +#include "InputOutput.h" +#include "MTimer.h" +struct SPI Spi; + unsigned int Temp_AMP=0; + + unsigned int Temp_ADC_2=0; + unsigned int Temp_ADC_3=0; + unsigned int Temp_ADC_4=0; + unsigned int Temp_ADC_5=0; + + + unsigned int Buff_ADC_1 [256]; + unsigned int Buff_ADC_2 [256]; + unsigned int Buff_ADC_3 [256]; + unsigned int Buff_ADC_4 [256]; + unsigned int Buff_ADC_5 [256]; + + unsigned int Buff_AMP [256]; + + unsigned int SinPLC[64]={1023, 1016, 1006, 993, 976, 954, 904, 874, 841, 806, 768, 728, + 687, 645, 601, 557, 500, 379, 337, 296, 256, 219, 183, 150, + 120, 93, 69, 48, 31, 18, 8, 0, 8, 18, 31, 48, + 69, 93, 120, 150, 183, 219, 256, 296, 337, 379, 468, 512, 557, + 601, 645, 687, 728, 768, 806, 841, 874, 904, 954, 976, 993, 1006, + 1016, 1023}; + void DACLInit( void ) +{ + /* setup the related pin to DAC output */ + LPC_PINCON->PINSEL1 = 0x00200000; /* set p0.26 to DAC output */ + return; +} +void SPI_Exchange() +{ + unsigned int Dummy; + + Spi.ADC5 = LPC_SSP0->DR; + Spi.ADC4 = LPC_SSP0->DR; + Spi.ADC3 = LPC_SSP0->DR; + Spi.ADC2 = LPC_SSP0->DR; + Spi.ADC1 = LPC_SSP0->DR; + + Input.ArrayIn[2]= Spi.ADC5; + + LPC_SSP0->DR=0x5555; + LPC_SSP0->DR=0x5555; + LPC_SSP0->DR=0x5555; + + if (CountV31 & 1) //åñëè íå÷åòíûé òàêò òî + { + LPC_SSP0->DR = WRITE_DAC0; //e.êîìàíäà äëÿ ÖÀÏ_0 ïåðåäàâàòü. + LPC_SSP0->DR = (Spi.DAC_A); //e. ïåðåäà÷à 12 áèò + } + else //åñëè òàêò ÷åòíûé. + { + LPC_SSP0->DR = WRITE_DAC1 ; //e.êîìàíäà äëÿ ÖÀÏ_1 ïåðåäàâàòü. + LPC_SSP0->DR = (Spi.DAC_B); //e. ïåðåäà÷à 12 áèò + } + + LPC_DAC->CR = (((SinPLC[CountV64]*35)+21300)); + while (LPC_SSP0->SR & RX_SSP_notEMPT) //åñëè áóôåð SPI íå ïóñò. + Dummy = LPC_SSP0->DR; //î÷èñòèòü áóôåð. + + + Buff_ADC_1 [CountV255] = Spi.ADC1; // àìïë àöï. + Buff_ADC_2 [CountV255] = Spi.ADC2; + Buff_ADC_3 [CountV255] = Spi.ADC3; + Buff_ADC_4 [CountV255] = Spi.ADC4; + Buff_ADC_5 [CountV255] = Spi.ADC5; + + + + Temp_AMP += Buff_ADC_5[CountV255]; + Temp_AMP -= Buff_ADC_5[(CountV255-32) & 0xff]; // çàïîëíåíèå áóôåðà íàêîïëåíûõ ïðèðàùåíèé çà 8 òàêòîâ + Buff_AMP[CountV255] = (unsigned int) (Temp_AMP); + + Temp_ADC_2 += Buff_ADC_2[CountV255]; + Temp_ADC_2 -= Buff_ADC_2[(CountV255-32) & 0xff]; + + Temp_ADC_3 += Buff_ADC_3[CountV255]; + Temp_ADC_3 -= Buff_ADC_3[(CountV255-32) & 0xff]; + + Temp_ADC_4 += Buff_ADC_4[CountV255]; + Temp_ADC_4 -= Buff_ADC_4[(CountV255-32) & 0xff]; + + Temp_ADC_5 += Buff_ADC_1[CountV255]; + Temp_ADC_5 -= Buff_ADC_1[(CountV255-32) & 0xff]; +} +void Init_SPI_Exchange() +{ + ResetCS(ADC); //prepare ADC for sampling + SetDAC(DAC); + LPC_GPIO2->FIOSET |= 0x0000004; // turn on the LED +//LPC_GPIO2->FIOSET |= 0x0000004; // turn on the LED +//LPC_GPIO2->FIOSET |= 0x0000004; // turn on the LED + SetCS(ADC); //start ADC sampling + ResetDAC(DAC); +} \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/SPI.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/SPI.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,34 @@ +#define RX_SSP_notEMPT 0x00000004 + +extern unsigned int Temp_AMP; + +extern unsigned int Temp_ADC_2; +extern unsigned int Temp_ADC_3; +extern unsigned int Temp_ADC_4; +extern unsigned int Temp_ADC_5; + + + + +struct SPI { + unsigned int ADC1; + unsigned int ADC2; + unsigned int ADC3; + unsigned int ADC4; + unsigned int ADC5; + + unsigned int DAC_A; + unsigned int DAC_B; + unsigned int DAC_L; +}; + + extern unsigned int Buff_ADC_1 []; + extern unsigned int Buff_ADC_2 []; + extern unsigned int Buff_ADC_3 []; + extern unsigned int Buff_ADC_4 []; + extern unsigned int Buff_ADC_5 []; + extern unsigned int Buff_AMP []; + +extern struct SPI Spi; +extern void SPI_Exchange(); +extern void Init_SPI_Exchange(); \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/ThermoCalc.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/ThermoCalc.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,296 @@ + #include "ThermoCalc.h" + #include "CyclesSync.h" + #include "CntrlGLD.h" + #include "InputOutput.h" + #include "mathDSp.h" + +#define debug +#define TEMP_AVER_PERIOD 4 // e. number of seconds for average + int TermoCompens_Sum = 0; +unsigned int IsHeating; + //int Tmp_Out[NUM_OF_THERMOSENS]; + int dThermoHeatDeltaPer_dTermo[TERMO_FUNC_SIZE]; + int dThermoCoolDeltaPer_dTermo[TERMO_FUNC_SIZE]; + int dFuncPer_dTermo[TERMO_FUNC_SIZE]; + int TermoCompDelta; + int Temp_Aver; //e. the mean temperature for 1 Sec for T4 sensor //r. ñðåäíÿÿ òåìïåðàòóðà çà 1 ñåêóíäó äëÿ äàò÷èêà T4 + int TempEvolution = 0; + int StartTermoCompens = 0; //e. initial thermocompensation (in XXX seconds after start ) //r. íà÷àëüíàÿ òåðìîêîìïåíñàöèÿ (÷åðåç ÕÕÕ ñåêóíä ïîñëå ñòàðòà) + +extern int WP_reset_heating; //e. voltage of reset at heating //r. íàïðÿæåíèå ñáðîñà ïðè íàãðåâàíèè +extern int WP_reset_cooling; //e. voltage of reset at cooling //r. íàïðÿæåíèå ñáðîñà ïðè îõëàæäåíèè + +__inline Max_Saturation(unsigned *lvl, unsigned limit) +{ + if (*lvl>limit) *lvl = limit; +} + +/*{ + switch (Device_blk.Str.TermoMode) //e. selecting thermocompensation mode //r. âûáîð ðåæèìà òåðìîêîìïåíñàöèè + { + case TERMO_ON: + case TERMO_ON_NUMB_OFF: + + TermoCompens_Sum += StartTermoCompens + DynamicDeltaCalc(); //e. accumulation of the value of thermocompensation from request to request //r. íàêîïëåíèå âåëè÷èíû òåðìîêîìïåíñàöèè îò çàïðîñà äî çàïðîñà + + break; + + case TERMO_ON_STATIC_ONLY: + case TERMO_ON_STATIC_ONLY_NUMB_OFF: +#if !defined debug_SOI + TermoCompens_Sum += StartTermoCompens; //e. accumulation of the value of thermocompensation from request to request //r. íàêîïëåíèå âåëè÷èíû òåðìîêîìïåíñàöèè îò çàïðîñà äî çàïðîñà +#endif + break; + + case TERMO_ON_DYNAMIC_ONLY: + case TERMO_ON_DYNAMIC_ONLY_NUMB_OFF: +#if !defined debug_SOI + TermoCompens_Sum += DynamicTermoCompens(); //e. accumulation of the value of thermocompensation from request to request //r. íàêîïëåíèå âåëè÷èíû òåðìîêîìïåíñàöèè îò çàïðîñà äî çàïðîñà +#endif + break; + + case TERMO_OFF: + default: + TermoCompens_Sum = 0; //e. thermocompensation is disable, therefore its part is equal to zero //r. òåðìîêîìïåíñàöèÿ âûêëþ÷åíà, ïîýòîìó åå âêëàä ðàâåí íóëþ + + } //of thermomode switch +} */ +/****************************************************************************** +** Function name: StaticTermoCompens +** +** Descriptions: Procedure of +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +int StaticTermoCompens(int temperature) //r. ðàñ÷åò ñòàòè÷åñêîé ñîñòàâëÿþùåé òåðìîêîìïåíñàöèè çà îäèí ïåðèîä ïðèáîðà (100 ìêñ) +{ + + float TermoCompens_Curr; //r. âåëè÷èíà òåðìîêîìïåíñàöèè çà îäèí ïåðèîä ïðèáîðà (100 ìêñ) + + int i, t; + + //r. èñïîëüçóåì òîëüêî òåðìîäàò÷èê TSENS_NUMB + //r. äëÿ íîâûõ òåðìîäàò÷èêîâ: T4, äëÿ ñòàðûõ: T1 + //r. è èñïîëüçóåì êóñî÷íî-íåïðåðûâíóþ òåðìîêîìïåíñàöèþ + + //r. Tmp_Out[TSENS_NUMB] = 8960; //-2560; //5120; //8000; // -2600; //-5000; + + t = temperature; + if(t > Device_blk.Str.TemperInt[TERMO_FUNC_SIZE - 1]) + { + t = Device_blk.Str.TemperInt[TERMO_FUNC_SIZE - 1]; + } + + i = 0; + while( t > Device_blk.Str.TemperInt[i] ) i++; + + //r. Tmp_Out[5] = i; + TermoCompens_Curr = Device_blk.Str.TermoFunc[i] - dFuncPer_dTermo[i] * (float)( Device_blk.Str.TemperInt[i] - t ); + + //r. Îòëàäêà + //r. TermoCompens_Curr = 1.111111125; // îòëàäêà + //r.TermoCompens_Curr = // 0.25; // çà 1 ñåê íàêàïëèâàåòñÿ 2500 èìïóëüñîâ + /*r. + //0.000100; // êîýôô., ïðè êîòîðîì çà 1 ñåê íàêàïëèâàåòñÿ 1 èìïóëüñ + //1.0001; // êîýôô., ïðè êîòîðîì çà 1 ñåê íàêàïëèâàåòñÿ 10001 èìïóëüñ + // 0.000125; // êîýôô., ïðè êîòîðîì çà 1 ñåê íàêàïëèâàåòñÿ 1.25 èìïóëüñà (çà 100 âûâîäèòñÿ 122 èìï.???) + // 0.000105; // çà 100 ñåê ä.íàêàïëèâàòüñÿ 105 èìï., íàêàïë. 103??? + */ + + // TermoCompens_Curr = LONG_2_FRACT_14_18(TermoCompens_Curr); //r. TermoCompens_Curr ïåðåâîäèì â ôîðìàò 14.18 + + return TermoCompens_Curr; +} // StaticTermoCompens + +/****************************************************************************** +** Function name: DynamicDeltaCalc +** +** Descriptions: Procedure of +** +** parameters: None +** Returned value: Thermocompensation addition +** +******************************************************************************/ +int DynamicDeltaCalc() //e. calculation the addition termocompensation for 1 reset //r. ðàñ÷åò äîáàâêè òåðìîêîìïåíñàöèè íà îäíî îáíóëåíèå +{ + + int i, t; + + t = Temp_Aver; + + if (IsHeating) + { + if(t > Device_blk.Str.TemperIntDyn[TERMO_FUNC_SIZE - 1]) + { + t = Device_blk.Str.TemperIntDyn[TERMO_FUNC_SIZE - 1]; + } + + i = 0; + while( t > Device_blk.Str.TemperIntDyn[i] ) i++; + + TermoCompDelta = ( Device_blk.Str.ThermoHeatDelta[i] - dThermoHeatDeltaPer_dTermo[i] * (float)( Device_blk.Str.TemperIntDyn[i] - t ) ); + } + else + { + if(t > Device_blk.Str.TemperCoolIntDyn[TERMO_FUNC_SIZE - 1]) + { + t = Device_blk.Str.TemperCoolIntDyn[TERMO_FUNC_SIZE - 1]; + } + + i = 0; + while( t > Device_blk.Str.TemperCoolIntDyn[i] ) i++; + + TermoCompDelta = ( Device_blk.Str.ThermoCoolDelta[i] - dThermoCoolDeltaPer_dTermo[i] * (float)( Device_blk.Str.TemperCoolIntDyn[i] - t ) ); + } + return TermoCompDelta; + +} // DynamicDeltaCalc + +/****************************************************************************** +** Function name: clc_ThermoSensors +** +** Descriptions: Procedure of calculating of the normalized temperaturre vector +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void clc_ThermoSensors(void) +{ + unsigned i; + static int TS_sum = 0; + static int seconds_aver = 0, TenSeconds = 0; + static int Temp_AverPrevDynCalc = -7000; + static int StartRdy = 1; + static int PrevTemp = -7000; + + for (i=0; i<2; i++) + { + //e. conversion of temperature values on ADC output //r. ïðåîáðàçîâàíèå çíà÷åíèé òåìïåðàòóðû íà âûõîäå ÀÖÏ + //e. to range -32768 .. +32767 ( additional code; format 1.15 ) //r. ê äèàïàçîíó -32768 .. +32767 (äîïîëíèò. êîä; ôîðìàò 1.15) + /* Output.Str.Tmp_Out[i] = mac_r(Device_blk.Str.Tmp_bias[i] << 16, + (Input.StrIn.Tmp_in[i] - 0x8000), + Device_blk.Str.Tmp_scal[i]);*/ + Output.Str.Tmp_Out[i+4] = Input.StrIn.Tmp_in[i]; + } + + if (time_1_Sec == DEVICE_SAMPLE_RATE_uks) //r. èñòåêëà 1 ñåêóíäà + { + seconds_aver++; + } + + if (seconds_aver > TEMP_AVER_PERIOD) //r. èñòåêëè TEMP_AVER_PERIOD(4 ñåêóíäû) ñåêóíä + { + seconds_aver = 0; + TenSeconds++; + PrevTemp = Temp_Aver; //e. save the previous mean temperature for 1 Sec //r. çàïîìèíàåì ïðåäûäóùóþ ñðåäíþþ òåìïåðàòóðó çà ñåêóíäó + Temp_Aver = TS_sum / (DEVICE_SAMPLE_RATE_HZ * TEMP_AVER_PERIOD); //e. calculating mean temperature for 1 Sec //r. âû÷èñëÿåì ñðåäíþþ òåìïåðàòóðó çà ñåêóíäó + + if (Temp_Aver > PrevTemp) + { + TempEvolution++; + } + if (Temp_Aver < PrevTemp) + { + TempEvolution--; + } + + TS_sum = 0; //e. reset the sum for calculation of an mean //r. îáíóëÿåì ñóììó äëÿ âû÷èñëåíèÿ ñðåäíåãî + } + else + { + TS_sum += Output.Str.Tmp_Out[TSENS_NUMB]; + } + + if (TenSeconds == 10) // 10 * TEMP_AVER_PERIOD = 40 + { + TenSeconds = 0; + if (TempEvolution > 0) + { + IsHeating = 1; + } + + if (TempEvolution < 0) + { + IsHeating = 0; + } + TempEvolution = 0; + } + + //e. single calculaiton of some device parameters (measurement on the VALID_START_SEC second after start) //r. îäíîêðàòíûé ðàñ÷åò íåêîòîðûõ ïàðàìåòðîâ ïðèáîðà (èçìåðåíèå íà VALID_START_SEC ñåêóíäå ïîñëå ñòàðòà) + if (StartRdy) + { + if (TenSeconds > VALID_START_4SEC) + { + + StartRdy = 0; //r. ñàìîáëîêèðîâêà, ïîýòîìó áîëüøå ñþäà íå çàõîäèì + + if ((Device_blk.Str.TermoMode != TERMO_OFF) && \ + (Device_blk.Str.TermoMode != TERMO_ON_DYNAMIC_ONLY) && \ + (Device_blk.Str.TermoMode != TERMO_ON_DYNAMIC_ONLY_NUMB_OFF)) //r. ñòàòè÷åñêàÿ òåðìîêîìïåíñàöèÿ âêëþ÷åíà + { + //r. ðàñ÷åò ñòàòè÷åñêîé òåðìîêîìïåíñàöèè ÷èñëà + StartTermoCompens = StaticTermoCompens(Temp_Aver); //r. ñòàðòîâàÿ òåìïåðàòóðû ïðèáîðà + } + DynamicDeltaCalc(); + + //r. ðàñ÷åò ãðàíèö äëÿ ÷àñòîòû âèáðîïðèâîäà, çàâèñÿùåãî îò ñòàðòîâîé òåìïåðàòóðû + // DithFreqRangeCalc(); + + //r. êîýôôèöèåíòû äëÿ ïîëîñîâîãî ôèëüòðà êâàçè ÄÓÏ íå ïåðåñ÷èòûâàåì: ñ÷èòàåì, ÷òî ïîëîñà ôèëüòðà çàâåäîìî øèðå + + + //r. íàïðÿæåíèå ñáðîñà ïðè íàãðåâàíèè + WP_reset_heating = CPL_reset_calc(Device_blk.Str.WP_reset, Device_blk.Str.K_WP_rst_heating, Temp_Aver, Device_blk.Str.TemperNormal); + //e. voltage of reset at cooling //r. íàïðÿæåíèå ñáðîñà ïðè îõëàæäåíèè + WP_reset_cooling = CPL_reset_calc(Device_blk.Str.WP_reset2, Device_blk.Str.K_WP_rst_cooling, Temp_Aver, Device_blk.Str.TemperNormal); + } + } + + if ( abs(Temp_Aver - Temp_AverPrevDynCalc) > Device_blk.Str.DeltaTempRecalc) + { + Temp_AverPrevDynCalc = Temp_Aver; + DynamicDeltaCalc(); + }//r. ðàñ÷åò ñðåäíåé çà 1 ñåêóíäó òåìïåðàòóðû äàò÷èêîâ T4, T5 + + // cyclic built-in test + if ( (Output.Str.Tmp_Out[4] < TS_MIN) || (Output.Str.Tmp_Out[4] > TS_MAX) || (Output.Str.Tmp_Out[5] < TS_MIN) || (Output.Str.Tmp_Out[5] > TS_MAX) ) + { + Valid_Data |= THERMO_RANGE_ERROR; + } + + if ( abs( Output.Str.Tmp_Out[4] - Output.Str.Tmp_Out[5]) > TS_DIFF_MAX) + { + Valid_Data |= THERMO_DIFF_ERROR; + } +} // clc_ThermoSensors + + +/****************************************************************************** +** Function name: clc_PLC +** +** Descriptions: Procedure of initial processing for the CPLC regulator +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void DithFreqRangeCalc(void) //r. ðàñ÷åò ãðàíèö êîýôôèöèåíòà äåëåíèÿ äëÿ ÷àñòîòû âèáðîïðèâîäà, çàâèñÿùèõ îò òåêóùåé òåìïåðàòóðû +{ + + unsigned int min_level, max_level; + int delta_VB_N; + + delta_VB_N = mult_r(Device_blk.Str.K_vb_tu >> DITH_VBN_SHIFT, (Temp_Aver - Device_blk.Str.TemperNormal)); //r.200; + //r. !!! ñäåëàòü ñóììèðîâàíèå ñ íàñûùåíèåì, à çàòåì ñäâèã + min_level = VB_Nmin0 + delta_VB_N; + max_level = VB_Nmax0 + delta_VB_N; + // maximum saturation for unsigned levels + Max_Saturation(&min_level, ((unsigned int)0xFFFF >> DITH_VBN_SHIFT)-1); // min should be always less then max_level by 1 + Max_Saturation(&max_level, ((unsigned int)0xFFFF >> DITH_VBN_SHIFT)); + Device_blk.Str.VB_Nmin = min_level << DITH_VBN_SHIFT; + Device_blk.Str.VB_Nmax = max_level << DITH_VBN_SHIFT; + +} // DithFreqRange_calc
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/ThermoCalc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/ThermoCalc.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,15 @@ +#include "stdlib.h" + +#define NUM_OF_THERMOSENS 6 +#define DITH_VBN_SHIFT 2 //e. //r. îïðåäåëÿåò ñäâèã (äåëåíèå íà 4) êîýôôèöèåíòà äåëåíèÿ âèáðîïðèâîäà, ÷òîáû èìåòü çàïàñ íà ðåãóëèðîâàíèå + +#define DEBUG +extern unsigned int IsHeating; +extern int Temp_Aver; //e. the mean temperature for 1 Sec for T4 sensor +extern int Tmp_Out[NUM_OF_THERMOSENS]; +extern int StartTermoCompens; +extern int TermoCompens_Sum; + +void DithFreqRangeCalc(void); +void ThermoAverage(void); +int DynamicDeltaCalc(void);
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/commandset.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/commandset.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,915 @@ +#include <string.h> +#include "commandset.h" +#include "el_lin.h" +#include "CyclesSync.h" +#include "CntrlGLD.h" +#include "InputOutput.h" +#include "Parameters.h" + +#define COMMAND_DEBUG + +//++++++++++++++++debug++++++++++++++++ +extern uint32_t In_Flag; +unsigned char BuffTemp1[100]; +//e. +++++++++++++++++++ variables +++++++++++++++++++++++++++++++++++++++++++ //r. +++++++++++++++++++ ïåðåìåííûå +++++++++++++++++++++++++++++++++++++++++++ +uint32_t CMD_Mode = 0; //e. operation mode of the device //r. ðåæèì ðàáîòû óñòðîéñòâà +uint32_t CMD_Code; //e. full code of the last recieved command //r. ïîëíûé êîä ïîñëåäíåé ïðèíÿòîé êîìàíäû +uint32_t wrk_period; //e. run period in cycles //r. ðàáî÷èé ïåðèîä â öèêëàõ +uint32_t blt_in_test; + + int32_t ScopeMode; //e. mode of display for a control point of an scope //r. ðåæèì îòîáðàæåíèÿ äëÿ êîíòðîëüíîé òî÷êè îñöèëëîãðàôà + + +void SetSpeedPeriod(void) //e.============ procedure of set of rate and periodicity of answer ======== //r.============ ïðîöåäóðà óñòàíîâêè ñêîðîñòè è ïåðèîäè÷íîñòè îòâåòà ======== +{ + if ((rcv_buf[3] & 0x0080) != 0) //e. is periodic data transmission needed? //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à òðóáóåòñÿ? + { + trm_cycl = 1; //e. yes, set present flag //r. äà, óñòàíîâèòü äàííûé ôëàã + } + else + { + trm_cycl = 0; //e. no, reset present flag //r. íåò, ñáðîñèòü äàííûé ôëàã + } + + SRgR &= 0xffcf; //e. clear the bit of transfer rate //r. î÷èñòêà áèò ñêîðîñòè ïåðåäà÷è + trm_rate = (rcv_buf[3] >> 1) & 0x0030; + SRgR |= trm_rate; //e. set present transfer rate //r. óñòàíîâèòü äàííóþ ñêîðîñòü ïåðåäà÷è +} // SetSpeedPeriod + + +void B_Delta_BINS(void) //r.===ïðîöåäóðà âûäà÷è íàêîïëåííûõ ðàçíîñòåé ñ÷åò÷èêîâ èìïóëüñîâ â ÈÍÑ â ôîðìàòå 14.18 +{ + Valid_Data = 0; // reset all bits of status word + + num_of_par = 2; //e. 2 parameters output //r. âûâîäèòü 2 ïàðàìåòðà + addr_param[0] = &Output.Str.BINS_dif; //e. set the first parameter address //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà + addr_param[1] = &Valid_Data; //e. set the second paremeter address //r. çàäàòü àäðåñ âòîðîãî ïàðàìåòðà + size_param[0] = 4; //e. the length of the 1st parameter is 4 bytes //r. ïàðàìåòð 1 èìåeò äëèíó 4 áàéòà + size_param[1] = 1; //e. the length of the 2nd parameter is 1 byte (!! - the high byte, instead of low is transmitted) //r. ïàðàìåòð 2 èìååò äëèíó 1 áàéò (!!! ïåðåäàåòñÿ ñòàðøèé áàéò, à íå ìëàäøèé) + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + +} // B_Delta_BINS + +void B_Delta_SF(void) //r.=== ïðîöåäóðà äëÿ èçìåðåíèÿ ìàñøòàáíîãî ìíîæèòåëÿ +{ + //e. time for data transfer has come, we work only with dither counters //r. ïðèøëî âðåìÿ ïåðåäàâàòü äàííûå, ðàáîòàåì òîëüêî ñ âèáðî-ñ÷åò÷èêàìè + RgConB = RATE_VIBRO_1; //e. set in the additional register of device control the mode of work with dither counters and the filter of moving average //r. óñòàíàâëèâàåì â äîïîëíèòåëüíîì ðåãèñòðå óïðàâëåíèÿ ðåæèì ðàáîòû ñ âèáðîñ÷åò÷èêàìè è ôèëüòðîì ñêîëüçÿùåãî ñðåäíåãî + + Valid_Data = 0; // reset all bits of status word + + num_of_par = 5;//8; //e. 8 parameters output //r. âûâîäèòü 8 ïàðàìåòðà + addr_param[0] = &Output.Str.SF_dif; //e. set the first parameter address //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà + addr_param[1] = &Out_main_cycle_latch; //e. set the second paremeter address //r. çàäàòü àäðåñ âòîðîãî ïàðàìåòðà + addr_param[2] = &Out_T_latch;//F_ras; + addr_param[3] = &Output.Str.WP_reg; + addr_param[4] = &Output.Str.Tmp_Out; + size_param[0] = 8; //e. the length of the 1st parameter is 4 bytes //r. ïàðàìåòð 1 èìåeò äëèíó 4 áàéòà + size_param[1] = 4; //e. the length of the 2nd parameter is 1 byte (!! - the high byte, instead of low is transmitted) //r. ïàðàìåòð 2 èìååò äëèíó 1 áàéò (!!! ïåðåäàåòñÿ ñòàðøèé áàéò, à íå ìëàäøèé) + size_param[2] = 2; + size_param[3] = 2; + size_param[4] = 12; + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà +} // B_Delta_SF + +void B_Delta_PS_execution(void) +{ + static void * paramTable[11] = {&(Output.Str.F_ras) , &(Output.Str.HF_reg), &(Output.Str.T_Vibro), &(Output.Str.L_Vibro), &(Output.Str.WP_reg), &(Output.Str.Tmp_Out[0]), &(Output.Str.Tmp_Out[1]), &(Output.Str.Tmp_Out[2]), &(Output.Str.Tmp_Out[3]), &(Output.Str.Tmp_Out[4]), &(Output.Str.Tmp_Out[5])}; + static uint32_t val, paramTmpWord; + static uint32_t * ptr; + static uint32_t index = 0; + + if ((index & 1) == 0) // high byte + { + ptr = (uint32_t*)paramTable[index >> 1]; + val = *ptr; + paramTmpWord = val >> 8; // move it to low byte of word + } + else + { + paramTmpWord = val; + } + paramTmpWord &= 0xFF; + paramTmpWord |= index << 8; + + Valid_Data = 0; // reset all bits of status word + + + num_of_par = 2; //e. 2 parameters output //r. âûâîäèòü 2 ïàðàìåòðà + addr_param[0] = &Output.Str.PS_dif; //e. set the first parameter address //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà + addr_param[1] = ¶mTmpWord; + size_param[0] = 2; //e. the 1st parameter has 2 bytes length //r. ïàðàìåòð 1 èìåeò äëèíó 2 áàéò + size_param[1] = 2; //e. the 2nd and 3rd parameters have 1 bytes length//r. ïàðàìåòðû 2,3 èìåþò äëèíó 1 áàéò + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + + index++; + if (index > 21) + { + index = 0; + } +} // B_Delta_PS_execution + +void M_Mirror(void) //e.---------------- prepare to transmission of the copy of receiving buffer ------------- //r.---------------- ïîäãîòîâêà ïåðåäà÷è êîïèè ïðèåìíîãî áóôåðà ------------- +{ + num_of_par = 1; //e. 1 parameter output //r. âûâîäèòü 1 ïàðàìåòð + + addr_param[0] = &rcv_copy; //e. set the address of the receiving buffer //r. óñòàíîâêà àäðåñà ïðèåìíîãî áóôåðà + + //e. multiply the number of copied words on 2, since each //r. óìíîæèòü ÷èñëî ñêîïèðîâàííûõ ñëîâ íà 2, ò.ê. êàæäîå + //e. will be trasferred in two steps: first zero, and then //r. áóäåò ïåðåäàâàòüñ÷ â äâà ïðèåìà: ñíà÷àëà íóëåâîé, à çàòåì + size_param[0] = rcv_byt_copy << 1; // multiplay by 2 + if (size_param[0] >= 64) + { + size_param[0] = 64; //e. maximal amount - no more than double length of the copy buffer //r. ìàêñèìàëüíîå êîëè÷åñòâî - íå áîëåå äâîéíîé äëèíû áóôåðà-êîïèè + } + trm_rate = 0; //e. set the transfer rate to the 38400 bauds //r. óñòàíîâèòü ñêîðîñòü ïåðåäà÷è 38400 áîä + trm_cycl = 0; //e. forbid cyclic transmission of the parameter //r. çàïðåòèòü ïåðåäà÷ó ïàðàìåòðà â öèêëå + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà +} // M_Mirror + +void Mk_Ask1(void) //r.----------------- prepare of the standart answer 1 ---------------------- //r.----------------- ïîäãîòîâêà ñòàíäàðòíîãî îòâåòà 1 ---------------------- +{ + CMD_Code &= 0xff00; //e. clear bits of errors //r. î÷èñòèòü â íåì ïîëå îøèáîê + num_of_par = 1; //e. total amount parameters in aswer - 1 //r. âñåãî ïàðàìåòðîâ â îòâåòå - 1 + addr_param[0] = &CMD_Code; //e. and this parameter - returnable command code //r. è ýòîò ïàðàìåòð - âîçâðàùàåìûé êîä êîìàíäû + size_param[0] = 2; //e. and both its bytes //r. ïðè÷åì îáà åãî áàéòà + trm_ena = 1; //e. allow operation of the transmitter of the device //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà óñòðîéñòâà +} // Mk_Ask1 + +void Mk_AskDev(void) //r.----------------- answer on a command for device mode set ------------ //r.----------------- Îòâåò íà êîìàíäó óñòàíîâêè ðåæèìà ïðèáîðà ------------ +{ + num_of_par = 2; //e. 2 parameters output //r. âûâîäèòü äâà ïàðàìåòðà + addr_param[0] = &Device_Mode; //e. address of the counter mode register (intenal latch, external latch, etc.) //r. àäðåñ ðåãèñòðà ðåæèìà ñ÷åò÷èêîâ (âíóòð., âíåøíÿÿ çàùåëêà è ò.ä.) + addr_param[1] = &SRgR; //e. address of the mode register of the processor card //r. àäðåñ ðåãèñòðà ðåæèìà ïëàòû ïðîöåññîðà + size_param[0] = 2; //e. size of the counter mode register - 2 bytes //r. ðàçìåð ðåãèñòðà ðåæèìà ñ÷åò÷èêîâ - 2 áàéòà + size_param[1] = 2; //e. size of the mode register of the processor card //r. ðàçìåð ðåãèñòðà ðåæèìà ïëàòû ïðîöåññîðà + trm_cycl = 0; //e. forbid cyclic transmission of the parameter //r. çàïðåòèòü ïåðåäà÷ó ïàðàìåòðà â öèêëå + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà +} // Mk_AskDev + +void GLD_Output(void) //e. ----------- Output modes --------- //r. --------- Ðåæèìû âûâîäà --------- +{ +if (Latch_Rdy) //latch appeared + { + if (trm_cycl) + trm_ena = 1; //enable packet generation + + switch (CMD_Mode) + { + case 1: //e. Delta _PS mode + B_Delta_PS_execution(); + break; + + case 5: + CMD_Code &= 0xff1f; //e. reset bits of current command code settings of periodicity and transfer rate //r. ñáðîñèòü â òåêóùåì êîäå êîìàíäû áèòû óñòàíîâêè ïåðèîäè÷íîñòè è ñêîðîñòè ïåðåäà÷è + if (CMD_Code == 0xdd02) //e. is it the Rate2 mode? //r. ýòî ðåæèì Rate2? + { + if (data_Rdy & WHOLE_PERIOD) + { + trm_ena = 1; + } + else + trm_ena = 0; + } + break; + } + } +} // GLD_Delta + + + +///// -------- commands ------------------------------------------------------------- +//e. set main device operation modes: //r. Óñòàíîâêà îñíîâíûõ ðåæèìîâ ðàáîòû ïðèáîðà: +//e. 1. acions with counters (internal latch, external latch with request over line, //r. 1. ðàáîòà ñî ñ÷åò÷èêàìè (âíóòðåííÿÿ çàùåëêà, âíåøíÿÿ çàùåëêè ñ çàïðîñîì ïî ëèíèè, +//e. external latch without request over line (instant answer after receiving of external latch pulse)) //r. âíåøíÿÿ çàùåëêà áåç çàïðîñà ïî ëèíèè (îòâåò ñðàçó ïîñëå ïðèõîäà èìïóëüñà âíåøí. çàùåëêè)) +//e. 2. line receiving/transmission rate //r. 2. ñêîðîñòü ïðèåìà/ïåðåäà÷è ïî ëèíèè +void B_Dev_Mode(void) +{ + Device_Mode = rcv_buf[3] & 0x00ff; //e. read the byte of command parameter from the receiver buffer //r. ñ÷èòàòü èç áóôåðà ïðèåìíèêà áàéò ïàðàìåòðà êîìàíäû + //e. and write it to the counter mode register //r. è çàïèñûâàåì â ðåãèñòð ðåæèìà ñ÷åò÷èêîâ + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_AskDev(); +} // B_Dev_Mode + +void B_BIT_Mode(void) +{ + uint8_t temp; + + temp = rcv_buf[3] & 0x000f & (~((rcv_buf[3] & 0x00f0) >> 4)); + if (temp == 1) // 1 - const test + { + Is_BIT = 1; + BIT_number = (long)(rcv_buf[4] & 0x00FF) << 24; + BIT_number |= (long)(rcv_buf[5] & 0x00FF) << 16; + BIT_number |= (long)(rcv_buf[6] & 0x00FF) << 8; + BIT_number |= (long)(rcv_buf[7] & 0x00FF); + } + else + { + Is_BIT = 0; + } + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_AskDev(); +} // B_BIT_Mode + +void M_Stimul(void) //e. === procedure of output of analog (DAC) and digital (flags) stimuluses //r. === ïðîöåäóðà âûâîäà àíàëîãîâûõ (ÖÀÏ) è äèñêðåòíûõ (ôëàãè) ñòèìóëîâ +{ + uint32_t chan; + + ScopeMode = 4; //e. WP_PHASE_DETECTOR allocate a mode of display for a control point of an scope //r. WP_PHASE_DETECTOR íàçíà÷èòü ðåæèì îòîáðàæåíèÿ äëÿ êîíòðîëüíîé òî÷êè îñöèëëîãðàôà + + chan = CMD_Code & 0x0007; //e. extracting the number of stimulus //r. âûäåëåíèå íîìåðà ñòèìóëà + + Output.ArrayOut[chan] = (((int)rcv_buf[4] << 8) | (int)rcv_buf[5])-0x8000; + + if ((CMD_Code & (1 << 7)) == 0) //e. to estimate: whether the answer is required //r. îöåíèòü: òðåáóåòñÿ ëè îòâåò + { + return; //e. if no - return //r. åñëè íåò - âîçâðàò + } + Mk_Ask1(); //e. otherwise - answer output //r. èíà÷å - âûäàòü îòâåò +} // M_Stymul + +void M_Status(void) //e. === procedure of initialization of transmission of the device status //r. === ïðîöåäóðà èíèöèàëèçàöèè ïåðåäà÷è ñòàòóñà óñòðîéñòâà +{ + SetSpeedPeriod(); //e. and set the answer transfer rate and its periodicity //r. è óñòàíîâèòü ñêîðîñòü ïåðåäà÷è îòâåòà è åãî ïåðèîäè÷íîñòü + + num_of_par = 2; //e. 2 parameters output //r. âûâîäèòü äâà ïàðàìåòðà + addr_param[0] = &blt_in_test; //e. the register address of the self-testing result //r. àäðåñ ðåãèñòðà ðåçóëüòàòà ñàìîòåñòèðîâàíèÿ + addr_param[1] = &ser_num; //e. address of the register of errors of line //r. àäðåñ ðåãèñòðà îøèáîê ëèíèè + size_param[0] = 2; //e. size of the self-test register - 2 bytes //r. ðàçìåð ðåãèñòðà ñàìîòåñòèðîâàíèÿ - 2 áàéòà + size_param[1] = 2; //e. size of the register of errors of line //r. ðàçìåð ðåãèñòðà îøèáîê ëèíèè + + trm_rate = 0; //e. set the transfer rate to the 38400 bauds //r. óñòàíîâèòü ñêîðîñòü ïåðåäà÷è 38400 áîä + trm_cycl = 0; //e. forbid cyclic transmission of the parameter //r. çàïðåòèòü ïåðåäà÷ó ïàðàìåòðà â öèêëå + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà +} // M_Status + +void M_Clear(void) //e.---------------- cleaning of the register of errors of line -------------------------- //r.---------------- î÷èñòêà ðåãèñòðà îøèáîê ëèíèè -------------------------- +{ + line_err = 0; +} // M_Clear + +void M_Tmp_W(void) //e.----------------- write the command to the AD7714 IC ------------------------- //r.----------------- çàïèñü êîìàíäû â ñõåìû AD7714 ------------------------- +{ + + Mk_Ask1(); +} + +void M_Tmp_R(void) //e.----------------- read the data from the AD7714 IC -------------------------- //r.----------------- ÷òåíèå äàííûõ èç ñõåì AD7714 -------------------------- +{ + +} // M_Tmp_R + +void M_ADC_R(void) //e.----------------- read the data from the ADCs ADS1250, ADS8321 --------- //r.----------------- ÷òåíèå äàííûõ èç êàíàëîâ ÀÖÏ ADS1250, ADS8321 --------- +{ + SetSpeedPeriod(); //e. set the answer transfer rate and its periodicity //r. óñòàíîâèòü ñêîðîñòü ïåðåäà÷è îòâåòà è åãî ïåðèîäè÷íîñòü + UART_SwitchSpeed(trm_rate); + + num_of_par = 4; //e. 4 parameters output //r. âûâîäèòü ÷åòûðå ïàðàìåòðà + addr_param[0] = 0; //e. //r. <!-- èñïîëüçîâàëèñü äëÿ ÄÓÏ, òåïåðü íå èñïîëüçóþòñÿ + addr_param[1] = 0; //e. //r. --> + addr_param[2] = 0; + addr_param[3] = &(Input.StrIn.HF_out); //e. set the 4th parameter address _HF_out //r. çàäàòü àäðåñ ÷åòâåðòîãî ïàðàìåòðà _HF_out + size_param[0] = 2; //e. size of the parameters - 2 bytes //r. ðàçìåð ïàðàìåòðîâ - 2 áàéòà + size_param[1] = 2; + size_param[2] = 2; + size_param[3] = 2; + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà +} // M_ADC_R + +void M_Cnt_R(void) //r.----------------- read the counters of the Elio5 card -------------------------- //r.----------------- ÷òåíèå ñ÷åò÷èêîâ ïëàòû Elio5 -------------------------- +{ + SetSpeedPeriod(); //e. set the answer transfer rate and its periodicity //r. óñòàíîâèòü ñêîðîñòü ïåðåäà÷è îòâåòà è åãî ïåðèîäè÷íîñòü + UART_SwitchSpeed(trm_rate); + num_of_par = 2; //e. 2 parameters output //r. âûâîäèòü äâà ïàðàìåòðà + + addr_param[0] = &(Output.Str.Cnt_Pls); //e. set the first parameter address //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà + addr_param[1] = &(Output.Str.Cnt_Mns); //e. set the second paremeter address //r. çàäàòü àäðåñ âòîðîãî ïàðàìåòðà + size_param[0] = 2; //e. size of the parameters - 2 bytes //r. ðàçìåð ïàðàìåòðîâ - 2 áàéòà + size_param[1] = 2; + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà +} // M_Cnt_R + +/*void M_e5r_W(void) //r.----------------- write to the mode register of the Elio5 card ------------------ //r.----------------- çàïèñü â ðåãèñòð ðåæèìà ïëàòû Elio5 ------------------ +{ + //e. read the byte of command parameter from the receiver buffer //r. ñ÷èòàòü èç áóôåðà ïðèåìíèêà áàéò ïàðàìåòðà êîìàíäû + //e. and write it to the card mode register and its copy //r. è çàïèñàòü åãî â ðåãèñòð ðåæèìà ïëàòû è â åãî êîïèþ +#if !defined COMMAND_DEBUG + Copy_e5_RgR = rcv_buf[3]; + io_space_write(E5_RGR, Copy_e5_RgR); +#endif + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_e5r_W */ +/* +void M_e5rA_W(void) //e.----- write to the 1st additional mode register of the Elio5 card ---------- //r.----- çàïèñü â 1-ûé äîïîëíèòåëüíûé ðåãèñòð ðåæèìà ïëàòû Elio5 ---------- +{ + //e. this command is used for switching a signal on which data counters are latched: //r. ýòà êîìàíäà èñïîëüçóåòñÿ äëÿ ïåðåêëþ÷åíèÿ ñèãíàëà, ïî êîòîðîìó çàùåëêèâàþòñÿ + //e. on the Reper signal or on Sign Meander //r. èíôîðìàöèîííûå ñ÷åò÷èêè: ëèáî ïî Reper`ó ëèáî ïî RefMeandr`ó + + //e. read the byte of command parameter from the receiver buffer //r. ñ÷èòàòü èç áóôåðà ïðèåìíèêà áàéò ïàðàìåòðà êîìàíäû + //e. and write it to the card mode register and its copy //r. è çàïèñàòü åãî â ðåãèñòð ðåæèìà ïëàòû è â åãî êîïèþ + Copy_e5_RgRA = rcv_buf[3]; +//??? Device_Mode = Copy_e5_RgRA; //e. and write it to the counter mode register //r. è çàïèñûâàåì â ðåãèñòð ðåæèìà ñ÷åò÷èêîâ +#if !defined COMMAND_DEBUG + io_space_write(E5_RGRA, Copy_e5_RgRA); +#endif + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_e5rA_W */ + +void M_Ctl_R(void) //r.----------------- reading the control register of the device ----------------- //r.----------------- ÷òåíèå ðåãèñòðà óïðàâëåíèÿ óñòðîéñòâà ----------------- +{ + num_of_par = 2; //e. 2 parameters transfer //r. ïåðåäàâàòü 2 ïàðàìåòðà + addr_param[0] = &CMD_Code; //e. the first parameter in answer - returned command code //r. ïåðâûé ïàðàìåòð â îòâåòå - âîçâðàùàåìûé êîä êîìàíäû + size_param[0] = 2; + size_param[1] = 2; //e. two bytes also have control registers //r. äâà áàéòà èìåþò òàêæå è ðåãèñòðû óïðàâëåíèÿ + if ((rcv_buf[3] & (1 << 4)) == 0) //e. is main control register needed? //r. òðåáóåòñÿ îñíîâíîé ðåãèñòð óïðàâëåíèÿ? + { + addr_param[1] = &RgConA; //e. yes //r. äà + } + else + { + addr_param[1] = &RgConB; //e. otherwise - load the address of the addititonal register //r. èíà÷å - çàãðóçèòü àäðåñ äîïîëíèòåëüíîãî ðåãèñòðà + } + CMD_Code &= 0xff10; //e. clear in it bit of errors and byte number //r. ñáðîñèòü â íåì ïîëÿ îøèáîê è íîìåðà áèòà + trm_ena = 1; //e. allow operation of the transmitter of line //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà ëèíèè +} // M_Ctl_R + +void M_Ctl_M(void) //r.----------------- modification of the control register of the device ------------ //r.----------------- ìîäèôèêàöèÿ ðåãèñòðà óïðàâëåíèÿ óñòðîéñòâà ------------ +{ + uint32_t * ptr; + uint32_t bit_numb; + + num_of_par = 2; //e. 2 parameters transfer //r. ïåðåäàâàòü 2 ïàðàìåòðà + addr_param[0] = &CMD_Code; //e. the first parameter in answer - returned command code //r. ïåðâûé ïàðàìåòð â îòâåòå - âîçâðàùàåìûé êîä êîìàíäû + size_param[0] = 2; + size_param[1] = 2; //e. two bytes also have control registers //r. äâà áàéòà èìåþò òàêæå è ðåãèñòðû óïðàâëåíèÿ + if ((CMD_Code & (1 << 4)) == 0) //e. is main control register needed? //r. òðåáóåòñÿ îñíîâíîé ðåãèñòð óïðàâëåíèÿ? + { + ptr = &RgConA; //e. yes //r. äà + } + else + { + ptr = &RgConB; //e. otherwise - load the address of the addititonal register //r. èíà÷å - çàãðóçèòü àäðåñ äîïîëíèòåëüíîãî ðåãèñòðà + } + addr_param[1] = ptr; //e. the second parameter in answer - modified register //r. âòîðîé ïàðàìåòð â îòâåòå - ìîäèôèöèðîâàííûé ðåãèñòð + + bit_numb = CMD_Code & 0x000f; //e. extract the number of the changeable bit //r. âûäåëèòü íîìåð èçìåíÿåìîãî áèòà + if ((CMD_Code & (1 << 7)) == 0) // Is clear bit + { + *ptr &= ~(1 << bit_numb); // yes, clear bit + } + else + { + *ptr |= 1 << bit_numb; // no, set bit + } + + CMD_Code &= 0xff10; //e. clear in command bit of errors and byte number //r. ñáðîñèòü â êîìàíäå ïîëÿ îøèáîê è íîìåðà áèòà + trm_cycl = 0; //e. forbid cyclic transmission of the parameter //r. çàïðåòèòü ïåðåäà÷ó ïàðàìåòðà â öèêëå + trm_ena = 1; //e. allow operation of the transmitter of line //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà ëèíèè +} // M_Ctl_M + +void M_Flg_R(void) //e.------------ reading the register of input flags --------------------------- //r.------------ ÷òåíèå ðåãèñòðà âõîäíûõ ôëàãîâ --------------------------- +{ + + num_of_par = 1; //e. 1 parameter output //r. âûâîäèòü îäèí ïàðàìåòð + addr_param[0] = &In_Flag; //e. the address of the flag register copy //r. àäðåñ êîïèè ðåãèñòðà ôëàãîâ + size_param[0] = 2; //e. size of the buffer - 2 bytes //r. ðàçìåð áóôåðà - 2 áàéòà + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + +} // M_Flg_R + +void M_Vib_W(void) //r.------------ set the oscillation period of the dither drive ----------------- //r.------------ óñòàíîâêà ïåðèîäà êîëåáàíèé âèáðîïðèâîäà ----------------- +{ + ScopeMode = 1; //e. VB_PHASE_DETECTOR allocate a mode of display for a control point of an scope //r. VB_PHASE_DETECTOR íàçíà÷èòü ðåæèì îòîáðàæåíèÿ äëÿ êîíòðîëüíîé òî÷êè îñöèëëîãðàôà + + Output.Str.T_Vibro = (rcv_buf[4] << 8) | (rcv_buf[5] & 0xFF); //e. new variable of the period //r. íîâàÿ ïåðåìåííàÿ ïåðèîäà +/* sprintf(BuffTemp1, "\n\r F = %d ", Output.Str.T_Vibro); + SendToBuff(BuffTemp1,15);*/ + Output.Str.L_Vibro= (rcv_buf[6] << 8) | (rcv_buf[7] & 0xFF); //e. new variable of the pulse width //r. íîâàÿ ïåðåìåííàÿ äëèòåëüíîñòè èìïóëüñîâ + /*sprintf(BuffTemp1, "\n\r L = %d ", Output.Str.L_Vibro); + SendToBuff(BuffTemp1,15);*/ + VibroDither_Set(); //e. and output its value to period registers on card //r. âûâåñòè åå çíà÷åíèå â ðåãèñòðû ïåðèîäà íà ïëàòå + + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_Vib_W + +void M_Gph_W(void) //e.------------ set the gain factor of photodetector channels ------------------- //r.------------ óñòàíîâêà óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà ------------------- +{ + Device_blk.Str.Gain_Ph_A = rcv_buf[4]; //e. read from the receiver buffer the value of the gain factor of the A channel //r. ñ÷èòàòü èç áóôåðà ïðèåìíèêà çíà÷åíèå óñèëåíèÿ êàíàëà À + Device_blk.Str.Gain_Ph_B = rcv_buf[5]; //e. read from the receiver buffer the value of the gain factor of the B channel //r. ñ÷èòàòü èç áóôåðà ïðèåìíèêà çíà÷åíèå óñèëåíèÿ êàíàëà  + + Out_G_photo(Device_blk.Str.Gain_Ph_A, Device_blk.Str.Gain_Ph_B); //e. display these values to digital potentiometers //r. âûâåñòè ýòè çíà÷åíèÿ â öèôðîâûå ïîòåíöèîìåòðû + + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_Gph_W + +void M_Rate(void) //e.------------ start of transfer of the M_Rate parameters stack ------------------- //r.------------ çàïóñê ïåðåäà÷è íàáîðà ïàðàìåòðîâ M_Rate ------------------- +{ + uint8_t mode; + + SetSpeedPeriod(); //e. set the answer transfer rate and its periodicity //r. óñòàíîâèòü ñêîðîñòü ïåðåäà÷è îòâåòà è åãî ïåðèîäè÷íîñòü + UART_SwitchSpeed(trm_rate); + + mode = rcv_buf[3] & 0x001f; //e. extract number of the parameters stack in the command //r. âûäåëèòü íîìåð íàáîðà ïàðàìåòðîâ â êîìàíäå + + switch (mode) { + case 1: //e. it is the Rate stack //r. ýòî íàáîð Rate + RgConB = RATE_REPER_OR_REFMEANDR; //e. counter latch every vibro period + SwitchRefMeandInt(RATE_REPER_OR_REFMEANDR); //e. enable reference meander interrupt + + wrk_period = 12500000; //e. load needed length of working period 1 ñ.//r. çàãðóçèòü òðåáóåìóþ äëèòåëüíîñòü ðàáî÷åãî ïåðèîäà 1 ñ. + num_of_par = 14; //e. 9 parameters or groups of parameters output //r. âûâîäèòü 9 ïàðàìåòðîâ èëè ãðóïï ïàðàìåòðîâ + + Valid_Data = 0; // reset all bits of status word + + addr_param[0] = &(Output.Str.Cnt_Pls); //e. set the address of the 1st parameter in the 1st group //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà â 1-îé ãðóïïå + addr_param[1] = &(Output.Str.Cnt_Mns); //e. set the address of the 1st parameter in the 2nd group //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà â 2-îé ãðóïïå + addr_param[2] = &(Output.Str.Cnt_Dif); //e. set the address of the 1st parameter in the 3rd group //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà â 3-îé ãðóïïå + addr_param[3] = &(Output.Str.F_ras); //e. set the address of the _F_ras parameter in the 4th group //r. çàäàòü àäðåñ ïàðàìåòðà _F_ras âî 4-îé ãðóïïå + addr_param[4] = &(Output.Str.HF_reg); //e. set the address of the _HF_reg parameter in the 5th group //r. çàäàòü àäðåñ ïàðàìåòðà _HF_reg â 5-åé ãðóïïå + addr_param[5] = &(Output.Str.HF_dif); //e. set the address of the _HF_dif parameter in the 6th group //r. çàäàòü àäðåñ ïàðàìåòðà _HF_dif â 6-îé ãðóïïå + addr_param[6] = &(Output.Str.T_Vibro); //e. parameter _T_Vibro //r. ïàðàìåòð _T_Vibro + addr_param[7] = &(Output.Str.T_VB_pll); //e. parameter _T_VB_pll //r.ïàðàìåòðâ _T_VB_pll + addr_param[8] = &(Output.Str.L_Vibro); //e. parameter _L_Vibro //r. ïàðàìåòð _L_Vibro + addr_param[9] = &(Input.StrIn.HF_out); //e. set the address of the _RI_reg parameter in the 8th group //r. çàäàòü àäðåñ ïàðàìåòðà _RI_reg â 8-îé ãðóïïå + addr_param[10] = &(Output.Str.WP_reg); //e. parameters: _WP_reg, _WP_pll //r. ïàðàìåòðîâ _WP_reg, _WP_pll + addr_param[11] = &(Output.Str.WP_pll); //e. parameters: _WP_reg, _WP_pll //r. ïàðàìåòðîâ _WP_reg, _WP_pll + addr_param[12] = &(Output.Str.Tmp_Out); //e. set the address of the temperature sensors array //r. çàäàòü àäðåñ ìàññèâà äàò÷èêîâ òåìïåðàòóðû + addr_param[13] = &(Output.Str.WP_scope1); //e. reserved //r. çàðåçåðâèðîâàíî äëÿ äàëüíåéøèõ ïðèìåíåíèé + + size_param[0] = 2; //e. groups 1-6, 8-10 consists of one parameter ... //r. ãðóïïû 1-6, 8-10 ñîäåðæàò ïî îäíîìó ïàðàìåòðó + size_param[1] = 2; //e. and have 2 bytes length each //r. è èìåþò äëèíó 2 áàéòà êàæäàÿ + size_param[2] = 2; + size_param[3] = 2; + size_param[4] = 2; + size_param[5] = 2; + size_param[6] = 2; + size_param[7] = 2; + size_param[8] = 2; + size_param[9] = 2; + size_param[10] = 2; + size_param[11] = 2; + + size_param[13] = 4; //e. the 11th group parameters has length of 4 bytes //r. 11-z ãðóïïà ïàðàìåòðîâ èìååò äëèíó 4 áàéòà + + size_param[12] = 12; //e. format o the GLD array of temperatures - 12 bytes //r. ôîðìàò ìàññèâà òåìïåðàòóð ÃËÄ - 12 áàéò + + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + break; + + case 2: //e. it is the Rate2 stack //r. ýòî íàáîð Rate2 + RgConB = RATE_REPER_OR_REFMEANDR; + SwitchRefMeandInt(RATE_REPER_OR_REFMEANDR); //e. enable interrupt from ref. meander + wrk_period = 0; //e. frequency of output = fvibro //r. ÷àñòîòà âûâîäà ðàâíà ÷àñòîòå ÂÏ + + num_of_par = 2; //e. 2 parameters output //r. âûâîäèòü 2 ïàðàìåòðà + + addr_param[0] = &(Output.Str.Cnt_Pls); //e. set the first parameter address //r. çàäàòü àäðåñ ïåðâîãî ïàðàìåòðà + addr_param[1] = &(Output.Str.Cnt_Mns); //e. and the 2nd //r. è âòîðîãî + size_param[0] = 2; //e. parameters has 2 bytes length //r. ïàðàìåòðû èìååò äëèíó 2 áàéòà + size_param[1] = 2; + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + break; + + case 3: //e. it is the Rate3 stack //r. ýòî íàáîð Rate3 + + wrk_period = 2500; //e. frequency of output = 10000 Hz //r. n=1, ÷àñòîòà âûâîäà = 10000 Hz + num_of_par = 2; //e. 2 parameters output //r. âûâîäèòü 2 ïàðàìåòðà + + addr_param[0] = &(Output.Str.WP_scope1); //e. set the addresses of output parameters //r. çàäàòü àäðåñà âûâîäèìûõ ïàðàìåòðîâ + addr_param[1] = &(Output.Str.WP_scope2); + size_param[0] = 2; //e. all parameters has 2 bytes length //r. âñå ïàðàìåòðû èìåþò äëèíó 2 áàéòà + size_param[1] = 2; + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + break; + + case 4: //e. it is the Rate4 stack //r. ýòî íàáîð Rate4 + wrk_period = 20000; //e. correspond to output frequency 1.25 kHz //r. ñîîòâåñòâóåò ÷àñòîòå âûâîäà 1.25 kHz + num_of_par = 4; //e. 4 parameters output //r. âûâîäèòü 4 ïàðàìåòðà + + //e. set the addresses of output parameters //r. çàäàòü àäðåñà âûâîäèìûõ ïàðàìåòðîâ + // --- raw data array of numbers --- + // addr_param[0] = &Dif_Curr_Array; + // --- filtered array of numbers --- + // addr_param[1] = &Dif_Filt_Array; + // --------------------------------- + addr_param[2] = &(Output.Str.HF_reg); //e. HFO regulator //r. íàïðÿæåíèå ÃÂ× + addr_param[3] = &(Output.Str.WP_reg); //e. CPLC heater regulator //r. íàïðÿæåíèå íàãðåâàòåëÿ + size_param[0] = 16; + size_param[1] = 32; + size_param[2] = 2; + size_param[3] = 2; + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + break; + case 7: + wrk_period = 20000; //e. correspond to output frequency 1250 Hz //r. ñîîòâåñòâóåò ÷àñòîòå âûâîäà 1.25 kHz + num_of_par = 5; //e. 4 parameters output //r. âûâîäèòü 5 ïàðàìåòðà + + //e. set the addresses of output parameters //r. çàäàòü àäðåñà âûâîäèìûõ ïàðàìåòðîâ + // --- raw data array of PLC phase --- + addr_param[0] = &(Output.Str.WP_Phase_Det_Array); + // --- filtered array of reference sin--- + addr_param[1] = &(Output.Str.WP_sin_Array); + // --------------------------------- + addr_param[2] = &(Output.Str.WP_reg); //e. CPLC heater regulator //r. íàïðÿæåíèå íàãðåâàòåëÿ + addr_param[3] = &(Output.Str.WP_pll); //e. CPLC phase //r. ôàçà + addr_param[4] = &(Output.Str.HF_reg); //e. set the address of the _HF_reg parameter in the 5th group //r. çàäàòü àäðåñ ïàðàìåòðà _HF_reg â 5-åé ãðóïïå + size_param[0] = 16; + size_param[1] = 16; + size_param[2] = 2; + size_param[3] = 2; + size_param[4] = 2; + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà + break; + } + SetIntLatch(wrk_period); +} // M_Rate + +void M_Reset(void) +{ + while(1); +} // will not achieve + +void M_Param_R(void) //e. ------------ read the parameter of the GLD from the data memory ---------------------- //r.------------ ÷òåíèå ïàðàìåòðà GLD èç ïàìÿòè äàííûõ ---------------------- +{ + num_of_par = 1; //e. 1 parameter output //r. âûâîäèòü îäèí ïàðàìåòð + addr_param[0] = (void *)(&Device_blk.Str.My_Addres + rcv_buf[3]); //e. address of the needed parameter in the block //r. àäðåñ òðåáóåìîãî ïàðàìåòðà â áëîêå + size_param[0] = 2; //e. size of the buffer - 2 bytes //r. ðàçìåð áóôåðà - 2 áàéòà + + trm_ena = 1; //e. allow operation of the transmitter //r. ðàçðåøèòü ðàáîòó ïåðåäàò÷èêà +} // M_Param_R + +void M_Param_W(void) //e.------------ write the parameter of the GLD from the data memory ----------------------- //r.------------ çàïèñü ïàðàìåòðà GLD â ïàìÿòü äàííûõ ----------------------- +{ + int * ptr; + + ScopeMode = 0; //e. VB_DELAY_MEANDER allocate a mode of display for a control point of an scope //r. VB_DELAY_MEANDER íàçíà÷èòü ðåæèì îòîáðàæåíèÿ äëÿ êîíòðîëüíîé òî÷êè îñöèëëîãðàôà + + ptr = (int *)&Device_blk.Str.My_Addres; // pointer to Parameters block + ptr += rcv_buf[3]; // calculate offset + *ptr = (rcv_buf[4] << 8) | (rcv_buf[5] & 0xFF); // write new parameter value + + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_Param_W + +void M_LdPar_F() //e.============ procedure for load the GLD parameters from the flash-memory =========== //r.============ ïðîöåäóðà çàãðóçêè ïàðàìåòðîâ ÃËÄ èç ôëýø-ïàìÿòè =========== +{ + + LoadFlashParam(FromFLASH); //e. load the GLD parameters from the flash-memory //r. çàãðóçèòü ïàðàìåòðû ÃËÄ èç ôäýø-ïàìÿòè + blt_in_test = ((uint32_t)FIRMWARE_VER << 8) | (Device_blk.Str.Device_SerialNumber & 0x00FF); +// Init_software(); + + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_LdPar_F + +void M_LdPar_D(void) //e.============ procedure for set parameters of the GLD by default ============ //r.============ ïðîöåäóðà óñòàíîâêè ïàðàìåòðîâ ÃËÄ ïî óìîë÷àíèþ ============ +{ +#if !defined COMMAND_DEBUG + LoadFlashParam(ByDefault); //e. define parameters of the GLD by default //r. îïðåäåëèòü ïàðàìåòðû ÃËÄ ïî óìîë÷àíèþ (default) + Init_software(); +#endif + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_LdPar_D + +void M_Start(void) //e.============ initialization of the GLD switch on ================================= //r.============ èíèöèàëèçàöèÿ çàïóñêà ÃËÄ ================================= +{ + start_Rq = 1; //e. set the flag of the GLD switch on request //r. óñòàíîâèòü ôëàã çàïðîñà ñòàðòà ÃËÄ + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_Start + +void M_Stop(void) //e.============ initialization of the GLD switch off ============================== //r.============ èíèöèàëèçàöèÿ âûêëþ÷åíèÿ ÃËÄ ============================== +{ + stop_Rq = 1; //e. set the flag of the GLD switch off request //r. óñòàíîâèòü ôëàã çàïðîñà âûêëþ÷åíèÿ ÃËÄ + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_Stop + +void M_Pulse(void) //e.============ generetion of the light-up pulse ========================= //r.============ ãåíåðàöèÿ èìïóëüñà çàïóñêà ëàçåðà ========================= +{ + pulse_Rq = 1; //e. set the flag of the GLD switch on request //r. óñòàíîâèòü ôëàã çàïðîñà ñòàðòà ÃËÄ + trm_cycl = 0; //e. periodic data transmission is not needed //r. ïåðèîäè÷åñêàÿ ïåðåäà÷à îòâåòà íå òðåáóåòñÿ + Mk_Ask1(); +} // M_Pulse + +void B_Rate(void) //e. === procedure of device operation in a mode of continuous output of raw data //r. === ïðîöåäóðà ðàáîòû ïðèáîðà â ðåæèìå íåïðåðûâíîé âûäà÷è "ñûðûõ" äàííûõ +{ +} // B_Rate + +void B_Delta(void) //e. === procedure not used //r. === ïðîöåäóðà íå èñïîëüçóåòñÿ +{ +} // B_Delta + +void D_Period_W(void) //e. === set the period of the angle increase output //r. === óñòàíîâêà ïåðèîäà âûäà÷è ïðèðàùåíèÿ óãëà +{ +} // D_Period_W + + // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +void exec_CMD(void) //e. === the final decoding and command execution procedure //r. === ïðîöåäóðà îêîí÷àòåëüíîé äåøèôðàöèè è èñïîëíåíèÿ êîìàíäû +{ + uint32_t wcode; + + rx_buf_copy = 1; //e. initialization of the flag of copying of receiving buffer //r. ïðåäóñòàíîâ ôëàãà êîïèðîâàíèÿ ïðèåìíîãî áóôåðà + + wcode = (rcv_buf[2] & 0xFF) << 8; + CMD_Code = wcode | (rcv_buf[3] & 0xFF); //e. save it in the memory for echo-transmission //r. ñîõðàíèòü åãî â ïàìÿòè äëÿ îáðàòíîé ïåðåäà÷è + + if (wcode == CMD_RATE) //e. is it Rate command? //r. ýòî êîìàíäà Rate? + { + B_Rate(); + return; + } + else if (wcode == CMD_DEV_MODE) //e. is it the Device_Mode command? //r. ýòî êîìàíäà óñòàíîâêè ðåæèìà ïðèáîðà? + { + CMD_Mode = 3; + B_Dev_Mode(); + return; + } + else if (wcode == CMD_DELTA_BINS) //e. is it the B_DeltaBINS command (command of request for data transfer to the navigation system)? //r. ýòî êîìàíäà çàïðîñà ïåðåäà÷è äàííûõ â íàâèã.ñèñòåìó? + { + RgConB = RATE_VIBRO_1; //e. set in the additional register of device control the mode of work with dither counters and the filter of moving average //r. óñòàíàâëèâàåì â äîïîëíèòåëüíîì ðåãèñòðå óïðàâëåíèÿ ðåæèì ðàáîòû ñ âèáðîñ÷åò÷èêàìè è ôèëüòðîì ñêîëüçÿùåãî ñðåäíåãî + SetSpeedPeriod(); + UART_SwitchSpeed(trm_rate); + CMD_Mode = 4; + B_Delta_BINS(); + return; + } + else if (wcode == CMD_DELTA_PS) //e. is it the B_DeltaPS command (command of request for data transfer to the uPC)? //r. ýòî êîìàíäà çàïðîñà ïåðåäà÷è äàííûõ â MkPC? + { + SetSpeedPeriod(); //e. and set the answer transfer rate and its periodicity //r. è óñòàíîâèòü ñêîðîñòü ïåðåäà÷è îòâåòà è åãî ïåðèîäè÷íîñòü (_trm_cycl) + UART_SwitchSpeed(trm_rate); + if (Device_Mode < 4) //e. work with internal latch + Device_Mode = DM_INT_LATCH_DELTA_PS; + else + Device_Mode = DM_EXT_LATCH_DELTA_PS_PULSE; + CMD_Mode = 1; + // B_Delta_PS(); + return; + } + else if (wcode == CMD_DELTA_SF) // is it the B_DeltaSF command? + { + SetSpeedPeriod(); //e. and set the answer transfer rate and its periodicity //r. è óñòàíîâèòü ñêîðîñòü ïåðåäà÷è îòâåòà è åãî ïåðèîäè÷íîñòü (_trm_cycl) + CMD_Mode = 7; + if ((rcv_buf[3] & 0x0001) != 0) //e.reset of accumulated number is disabled //r. ñáðîñ íàêîïëåííîãî ìåæäó çàùåëêàìè ÷èñëà çàïðåùåí + Ext_Latch_ResetEnable = 0; + else + Ext_Latch_ResetEnable = 1; + B_Delta_SF(); + return; + } + else if (wcode == CMD_BIT_MODE) //e. is this the BIT mode command? //r. ýòî êîìàíäà òåñòèðîâàíèÿ? + { + CMD_Mode = 6; //e. set the value of the Delta mode//r. óñòàíîâèòü çíà÷åíèå ðåæèìà Delta + B_BIT_Mode(); + return; + } + else if (wcode == CMD_DELTA) //e. is this the B_Delta command? //r. ýòî êîìàíäà B_Delta? + { + CMD_Mode = 2; //e. set the value of the Delta mode//r. óñòàíîâèòü çíà÷åíèå ðåæèìà Delta + B_Delta(); //e. output calculated value of angle increase //r. âûâîäèòü âû÷èñëåííîå çíà÷åíèå ïðèðàùåíèÿ óãëà + return; + } + else if (CMD_Code == CMD_MAINT) //e. is this the Maintenance mode command? //r. ýòî êîìàíäà Maintenance mode? + { + if (!RgConB) + { + RgConB = RATE_VIBRO_1; + SwitchRefMeandInt(RATE_VIBRO_1); //e. disable interrupt from referense meander + } + CMD_Mode = 5; //e. yes, switch on present mode //r. äà, âêëþ÷èòü äàííûé ðåæèì + M_Status(); //e. output the status stack of registers //r. âûâåñòè ñòàòóñíûé íàáîð ðåãèñòðîâ + if (Device_Mode != DM_INT_10KHZ_LATCH) //e. mode of internal latch 10 kHz //r. ðåæèì âíóòðåííåé çàùåëêè 10 êÃö + { + Device_Mode = DM_INT_10KHZ_LATCH; + trm_ena = 0; + } + else + UART_SwitchSpeed(trm_rate); + return; + } + else if (wcode == SUBCMD_M_RESET) //e. is this subcommand for modification of the device control register? //r. ýòî ïîäêîìàíäà ìîäèôèêàöèè ðåãèñòðà óïðàâëåíèÿ ó-âà? + { +// Mk_AskDev(); + M_Reset(); + return; + } + else // subcommand analyse + { + if (CMD_Mode == 2) //e. is this the 2(Delta) mode? //r. ýòî ðåæèì 2? (Delta) + { + if (CMD_Code == CMD_D_PERIOD_W) //e. the Delta mode, check the subcommand ... //r. ðåæèì DElta, ïðîâåðèòü ïîäêîìàíäó çàãðóçêè ïåðèîäà + { + D_Period_W(); //e. otherwise - set the data transfer period //r. èíà÷å óñòàíîâèòèü ïåðèîä âûäà÷è äàííûõ + return; + } + else + { + line_sts = line_sts | CODE_ERR; // invalid command code + return; + } + } + else if (CMD_Mode == 5) //e. check the 5 mode (Maintenance) //r. ïðîâåðêà ðåæèìà 5 (Maintenance) + { + if (CMD_Code == SUBCMD_M_CLEAR) //e. is this subcommand of cleaning of the error register? //r. ýòî ïîäêîìàíäà î÷èñòêè ðåãèñòðà îøèáîê ëèíèè? + { + M_Clear(); //e. yes, cleaning the error register //r. äà, î÷èñòêà ðåãèñòðà îøèáîê + M_Status(); //e. preparing for trabsfer of the device status //r. ïîäãîòîâêà ïåðåäà÷è ñòàòóñà óñòðîéñòâà + UART_SwitchSpeed(trm_rate); + return; + } + else if (CMD_Code == SUBCMD_M_MIRR) //e. is this subcommand of return of previous command? //r. ýòî ïîäêîìàíäà âîçâðàòà ïðåäûäóùåé êîìàíäû? + { + rx_buf_copy = 0; //e. yes, forbid copying of command on saving previous //r. äà, çàïðåòèòü êîïèðîâàíèå êîìàíäû äëÿ ñîõðàíåíèÿ ïðåäûäóùåé + M_Mirror(); //e. prepare transfer of the receiving buffer copy //r. ïîäãîòîâèòü ïåðåäà÷ó êîïèè ïðèåìíîãî áóôåðà + return; + } + /* else if (wcode == SUBCMD_M_TMP_W) //e. is this subcommand for writing instructions to the AD7714? //r. ýòî ïîäêîìàíäà çàïèñè èíñòðóêöèé â AD7714? + { + // M_Tmp_W(); //e. yes, procedure call of write of the command //r. äà, âûçîâ ïðîöåäóðû çàïèñè êîìàíäû + return; + } */ + else if (wcode == SUBCMD_M_TMP_R) //e. is this subcommand for data read from the AD7714? //r. ýòî ïîäêîìàíäà ÷òåíèÿ äàííûõ èç AD7714? + { + M_Tmp_R(); //r. yes, call the procedure for data read //e. äà, âûçîâ ïðîöåäóðû ÷òåíèÿ äàííûõ + return; + } + /* else if (wcode == SUBCMD_M_E5R_W) //e. is this subcommand for write to the mode register? //r. ýòî ïîäêîìàíäà çàïèñè â ðåãèñòð ðåæèìà? + { + M_e5r_W(); //e. yes, write data to the mode register of the Elio5 card //r. äà, çàïèñàòü äàííûå â ðåãèñòð ðåæèìà ïëàòû Elio5 + return; + } + else if (wcode == SUBCMD_M_E5RA_W) //e. is this subcommand for write to the mode register? //r. ýòî ïîäêîìàíäà çàïèñè â ðåãèñòð ðåæèìà? + { + M_e5rA_W(); //e. yes, write data to the mode register of the Elio5 card //r. äà, çàïèñàòü äàííûå â ðåãèñòð ðåæèìà ïëàòû Elio5 + return; + } */ + else if (wcode == SUBCMD_M_ADC_R) //e. is t the subcommand for data read from ADCs ADS1250 and ADS8321 ? //r. ýòî ïîäêîìàíäà ÷òåíèÿ äàííûõ èç ÀÖÏ ADS1250 è ADS8321? + { + M_ADC_R(); //e. read of ADC channels //r. ÷òåíèå êàíàëîâ ÀÖÏ + return; + } + else if (wcode == SUBCMD_M_CNT_R) //e. is this subcommand of data read from pulse counters? //r. ýòî ïîäêîìàíäà ÷òåíèÿ äàííûõ èç ñ÷åò÷èêîâ èìïóëüñîâ? + { + M_Cnt_R(); //e. read of counters //r. ÷òåíèå ñ÷åò÷èêîâ + return; + } + else if (wcode == SUBCMD_M_FLG_R) //e. is it the command of data read about input flags? //r. ýòî ïîäêîìàíäà ÷òåíèÿ äàííûõ î âõîäíûõ ôëàãàõ? + { + M_Flg_R(); //e. read the input flags //r. ÷èòàòü âõîäíûå ôëàãè + return; + } + else if (wcode == SUBCMD_M_VIB_W) //e. is this subcommand for load the dither drive period? //r. ýòî ïîäêîìàíäà çàãðóçêè ïåðèîäà âèáðîïðèâîäà? + { + M_Vib_W(); //e. set the new value of the period //r. óñòàíîâèòü íîâîå çíà÷åíèå ïåðèîäà + return; + } + else if (wcode == SUBCMD_M_GPH_W) //e. is this subcommand for set the gain factor of photodetector channels? //r. ýòî ïîäêîìàíäà óñòàíîâêè óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà ? + { + M_Gph_W(); //e. set the new values of gain factor //r. óñòàíîâèòü íîâûå çíà÷åíèÿ óñèëåíèÿ + return; + } + else if (wcode == SUBCMD_M_STIMUL) //e. is this subcommand for set the values of the DACs and flags? //r. ýòî ïîäêîìàíäà óñòàíîâêè çíà÷åíèÿ ÖÀÏîâ è ôäàãîâ ? + { + M_Stimul(); //e. set the new values //r. óñòàíîâèòü íîâûå çíà÷åíèÿ + return; + } + else if (wcode == SUBCMD_M_RATE) //e. is this subcommand for set the M_Rate output stack //r. ýòî ïîäêîìàíäà óñòàíîâêè âûäà÷è íàáîðà M_Rate ? + { + M_Rate(); //e. switch on the M_Rate data transfer //r. âêëþ÷èòü ïåðåäà÷ó äàííûõ M_Rate + return; + } + else if (wcode == SUBCMD_M_PARAM_W) //e. is this subcommand for write the new value of the GLD parameter ... //r. ýòî ïîäêîìàíäà çàïèñè íîâîãî çíà÷åíèÿ ïàðàìåòðà GLD + { + M_Param_W(); //e. write the new value of the parameter //r. çàïèñàòü íîâîå çíà÷åíèå ïàðàìåòðà + return; + } + else if (wcode == SUBCMD_M_PARAM_R) //e. is this subcommand for read the value of the GLD parameter? //r. ýòî ïîäêîìàíäà ÷òåíèÿ çíà÷åíèÿ ïàðàìåòðà GLD? + { + M_Param_R(); //e. read the value from the data memory //r. ñ÷èòàòü çíà÷åíèå ïàðàìåòðà èç ïàìÿòè äàíûõ + return; + } + else if (CMD_Code == SUBCMD_M_LDPAR_F) //e. is this subcommand for load GLD parameters ... //r. ýòî ïîäêîìàíäà çàãðóçêè ïàðàìåòðîâ GLD + { + M_LdPar_F(); //e. start the loading of parameters //r. çàïóñòèòü çàãðóçêó ïàðàìåòðîâ + return; + } + else if (CMD_Code == SUBCMD_M_LDPAR_D) //e. is this subcommand for direct setting of the GLD parameters ... //r. ýòî ïîäêîìàíäà ïðÿìîãî íàçíà÷åíèÿ ïàðàìåòðîâ GLD + { + M_LdPar_D(); //e. read the value of the parameter from the data memory //r. ñ÷èòàòü çíà÷åíèå ïàðàìåòðà èç ïàìÿòè äàíûõ + return; + } + else if (CMD_Code == SUBCMD_M_START) //e. is this subcommand for GLD starting? //r. ýòî ïîäêîìàíäà çàïóñêà GLD? + { + M_Start(); //e. call the procedure of start //r. çàïóñòèòü ïðîöåäóðó ñòàðòà + return; + } + else if (CMD_Code == SUBCMD_M_PULSE) //e. is this subcommand for GLD starting? //r. ýòî ïîäêîìàíäà çàïóñêà GLD? + { + M_Pulse(); //e. call light-up function //r. âûäàòü èìïóëüñ ïîäæèãà + return; + } + else if (CMD_Code == SUBCMD_M_STOP) //e. is this subcommand for GLD switch off? //r. ýòî ïîäêîìàíäà âûêëþ÷åíèÿ GLD? + { + M_Stop(); //e. otherwise- switch off all regulators and stop device //r. âûêëþ÷èòü âñå êîíòóðû è îñòàíîâèòü ïðèáîð + return; + } + else if (wcode == SUBCMD_M_CTL_R) //e. is this subcommand for read the device control register? //r. ýòî ïîäêîìàíäà ÷òåíèÿ ðåãèñòðà óïðàâëåíèÿ ó-âà? + { + M_Ctl_R(); + return; + } + else if (wcode == SUBCMD_M_CTL_M) //e. is this subcommand for modification of the device control register? //r. ýòî ïîäêîìàíäà ìîäèôèêàöèè ðåãèñòðà óïðàâëåíèÿ ó-âà? + { + M_Ctl_M(); + return; + } +/* else if (wcode == SUBCMD_M_RESET) //e. is this subcommand for modification of the device control register? //r. ýòî ïîäêîìàíäà ìîäèôèêàöèè ðåãèñòðà óïðàâëåíèÿ ó-âà? + { + M_Reset(); + return; + }*/ + else + { + line_sts = line_sts | MODE_ERR; // mode error + return; + } + } + } +} // exec_CMD + +void decode_CMD(void) +{ + int size; + + if (!rcv_Rdy) //e. is data in receive buffer? //r. â ïðèåìíîì áóôåðå åñòü èíôîðìàöèÿ? + { + return; //e. if no, stop processing //r. åñëè íåò, çàêîí÷èòü îáðàáîòêó + } + + if (!line_sts) //e. Whether there were errors of receiving of start-bit? //r. áûëè ëè îøèáêè ïðèåìà ñòàðò-áèòà ? + { + //e. there were not errors of receiving of bytes, check the device address //r. îøèáîê ïðèåìà áàéòîâ íå áûëî, ïðîâåðèòü àäðåñ îáðàùåíèÿ + //Is_Brodcast_Req = 0; //e. reset the flag of broadcasting request //r. ñáðîñèòü ôëàã øèðîêîâåùàòåëüíîãî çàïðîñà + if (rcv_buf[1] != Device_blk.Str.My_Addres) + { + if (rcv_buf[1] != BROADCAST_ADDRESS) + { + goto end; + } + } + + if (rcv_buf[0] == COMMAND_PREFIX) + { //e. there is new command in the receiver buffer, stop the transfer //r. â áóôåðå ïðèåìíèêà åñòü íîâàÿ êîìàíäà, ïðåêðàòèòü ïåðåäà÷ó + trm_ena = 0; //e. reset the flag of transmission allowing //r. ñáðîñèòü ôëàã ðàçðåøåíèÿ ïåðåäà÷è + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + exec_CMD(); // øåé êîìàíäû + + ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + + //e. check up presence of errors in operation of this procedure //r. ïðîâåðèòü, íàëè÷èå îøèáîê â ðàáîòå äàííîé ïîöåäóðû + //e. did is the "unknown code of a command" or "parameters were set incorrectly" error? //r. áûëà îøèáêà "íåèçâåñòíûé êîä êîìàíäû" èëè "íåâåðíî çàäàííûå ïàðàìåòðû"? + if ( ((line_sts & CODE_ERR) == CODE_ERR) || ((line_sts & PARAM_ERR) == PARAM_ERR) ) + { + line_err = line_sts; //e. set error bits in the error register of the line //r. óñòàíîâèòü áèòû îøèáîê â ðåãèñòðå îøèáîê ëèíèè + } + } + else + { + line_err = line_sts | NO_CMD_ERR; // äîáàâëåíèå îøèáêè â ðåãèñòð îøèáîê + } + + } + else + { + line_err = line_sts; + } +end: + if (rx_buf_copy) //e. is copying of present received packet needed? //r. òðåáóåòñÿ êîïèðîâàíèå äàííîãî ïðèíÿòîãî ïàêåòà? + { + size = rcv_num_byt; + rcv_byt_copy = rcv_num_byt; //e. save the size of copy //r. çàïîìíèòü ðàçìåð êîïèè + if (rcv_num_byt > sizeof(rcv_buf)) //e. compare the size of receiving buffer with amount of received bytes //r. êîïèðîâàíèå òðåáóåòñÿ, ñðàâíèòü ðàçìåð ïðèåìíîãî áóôåðà ñ ÷èñëîì ïðèíÿòûõ áàéò + { + size = sizeof(rcv_buf); + } + memcpy(rcv_copy, rcv_buf, size); //e. copy of received amount of bytes, but no more than buffer size //r. êîïèðîâàòü ïðèíÿòîå ÷èñëî áàéò, íî íå áîëåå ðàçìåðà áóôåðà + } + rx_buf_copy = 0; //e. reset the flag of necessity of copying of receiving buffer //r. ñáðîñèòü ôëàã íåîáõîäèìîñòè êîïèðîâàíèÿ ïðèåìíîãî áóôåðà + + do + rcv_buf[--rcv_num_byt] = 0; + while(rcv_num_byt); + rcv_num_byt_old = rcv_num_byt; + line_sts = 0; //e. reset the line status register //r. ñáðîñèòü ðåãèñòð ñòàòóñà ëèíèè + rcv_Rdy = 0; //e. allow further data reception //r. ðàçðåøèòü äàëüíåéøèé ïðèåì äàííûõ +} // decode_CMD +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/commandset.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/commandset.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,59 @@ +//e. procedures, which are used in el_gld.asm //r. ïðîöåäóðû, èñïîëüçóåìûå â el_gld.asm +#ifndef COMMANDSET +#define COMMANDSET + +#include "stdint.h" + + //e. ===== command codes, received from a line ========== //r. ===== êîäû êîìàíä, ïðèíèìàåìûõ ñ ëèíèè ========== +#define COMMAND_PREFIX 0xCC //e. attribute of command //r. ïðèçíàê êîìàíäû +#define BROADCAST_ADDRESS 0x1f //e. the broadcasting address ( shared for 3 GLD ) //r. øèðîêîâåùàòåëüíûé àäðåñ (îáùèé äëÿ 3-õ ÃËÄ) + + +#define CMD_DELTA_PS 0xa000 //e. the code of the B_DeltaPS command //r. êîä êîìàíäû B_DeltaPS +#define CMD_DELTA_BINS 0xb000 //e. the code of the B_DeltaBINS command //r. êîä êîìàíäû B_DeltaBINS +#define CMD_DELTA_SF 0xb200 //e. the code of the B_DeltaSF command //r. êîä êîìàíäû B_DeltaSF +#define CMD_DEV_MODE 0xA500 //e. the code of the Device_Mode command //r. êîä êîìàíäû Device_Mode +#define CMD_BIT_MODE 0xA700 //e. the code of the B.I.T. command //r. êîä êîìàíäû B.I.T.(âñòîðîåííîãî òåñòèðîâàíèÿ) +#define CMD_RATE 0x0000 //e. the code of the Rate command //r. êîä êîìàíäû Rate +#define CMD_DELTA 0x0f00 //e. the code of the Delta command //r. êîä êîìàíäû Delta +#define CMD_D_PERIOD_W 0xf000 //e. the code of the D_Period_W command //r. êîä êîìàíäû D_Period_W + +#define CMD_MAINT 0x9999 //e. the code of the Maintenance mode command //r. êîä êîìàíäû Maintenance mode + +#define SUBCMD_M_STIMUL 0x0a00 //e. the code of the Stimul command //r. êîä êîìàíäû Stimul +#define SUBCMD_M_RESET 0x8000 //e. software device reset(restart) //r. ïðîãðàììíûé ñáðîñ (ðåñòàðò) ïðèáîðà +#define SUBCMD_M_CLEAR 0xda00 //e. reset of the register of errors of line 485 //r. î÷èñòêà ðåãèñòðà îøèáîê ëèíèè 485 +#define SUBCMD_M_MIRR 0xda01 //e. return previous contents of the receiver buffer //r. âîçâðàò ïðåäûäóùåãî ñîäåðæèìîãî áóôåðà ïðèåìíèêà +#define SUBCMD_M_LDPAR_F 0xda02 //e. load GLD parameters from Flash-memory //r. çàãðóçèòü ïàðàìåòðû ÃËÄ èç ôëýø-ïàìÿòè +#define SUBCMD_M_LDPAR_D 0xda03 //e. set GLD parameters by procedure of initialization //r. óñòàíîâèòü ïàðàìåòðû ÃËÄ ïðîöåäóðîé èíèöèàëèçàöèè +#define SUBCMD_M_START 0xda04 //e. switch on the GLD //r. âêëþ÷èòü ÃËÄ +#define SUBCMD_M_STOP 0xda40 //e. switch off the GLD //r. âûêëþ÷èòü ÃËÄ +#define SUBCMD_M_PULSE 0xda0a //e. generation of the light-up pulse //r. ãåíåðàöèÿ èìïóëüñà ïîäæèãà + +#define SUBCMD_M_CTL_R 0xd900 //e. reading the control register of the device //r. ÷òåíèå ðåãèñòðà óïðàâëåíèÿ óñòðîéñòâà +#define SUBCMD_M_CTL_M 0xd800 //e. modification of bit of the control register //r. ìîäèôèêàöèÿ áèòà ðåãèñòðà óïðàâëåíèÿ +#define SUBCMD_M_RATE 0xdd00 //e. delivery of a stack of parameters M_Rate (Rate2, Rate3) //r. âûäà÷à íàáîðà ïàðàìåòðîâ M_Rate (Rate2, Rate3) + +#define SUBCMD_M_TMP_W 0xe000 //e. writing to the AD7714 circuit (temperature sensors) //r. çàïèñü â ñõåìû AD7714 (èçìåðèòåëè òåìïåðàòóðû) +#define SUBCMD_M_TMP_R 0xe100 //e. reading from the AD7714 circuit (temperature sensors) //r. ÷òåíèå èç ñõåì AD7714 (èçìåðèòåëè òåìïåðàòóðû) +#define SUBCMD_M_E5R_W 0xe200 //e. writing to the register of a mode of the Elio5 card //r. çàïèñü â ðåãèñòð ðåæèìà ïëàòû Elio5 +#define SUBCMD_M_ADC_R 0xe300 //e. reading data from the ADC of the Elio5 card //r. ÷òåíèå äàííûõ èç ÀÖÏ ïëàòû Elio5 +#define SUBCMD_M_VIB_W 0xe400 //e. loading of the oscillation period of the dither drive //r. çàãðóçêà ïåðèîäà êîëåáàíèé âèáðîïðèâîäà +#define SUBCMD_M_CNT_R 0xe500 //e. reading data from the counters of the Elio5 card //r. ÷òåíèå äàííûõ èç ñ÷åò÷èêîâ ïëàòû Elio5 +#define SUBCMD_M_GPH_W 0xe600 //e. loading gain factors of photodetector channels //r. çàãðóçêà êîýôôèöèåíòîâ óñèëåíèÿ êàíàëîâ ôîòîïðèåìíèêà +#define SUBCMD_M_FLG_R 0xe700 //e. reading data from the register of input flags //r. ÷òåíèå äàííûõ èç ðåãèñòðà âõîäíûõ ôëàãîâ +#define SUBCMD_M_PARAM_W 0xe800 //e. writing working parameter to the data memory //r. çàïèñü ðàáî÷åãî ïàðàìåòðà â ïàìÿòü äàííûõ +#define SUBCMD_M_PARAM_R 0xe900 //e. reading working parameter of the GLD from the data memory //r. ÷òåíèå ðàáî÷åãî ïàðàìåòðà GLD èç ïàìÿòè äàííûõ +#define SUBCMD_M_E5RA_W 0xea00 //e. writing in 1st additional (A) register of a mode of the Elio5 card //r. çàïèñü â 1-ûé äîïîëíèòåëüíûé (À) ðåãèñòð ðåæèìà ïëàòû Elio5 + + //e. system global variables //r. ñèñòåìíûå ãëîáàëüíûå ïåðåìåííûå + +extern uint32_t blt_in_test; //e. self-test register //r. ðåãèñòð ñàìîòåñòèðîâàíèÿ +extern uint32_t BIT_number; +extern uint32_t Is_BIT; + +void decode_CMD(void); +void GLD_Output(void); + +#endif // EL_GLD +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/config.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/config.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,98 @@ +#ifndef CONFIG +#define CONFIG + + +#define DEBUG + +//========== device selection ========================== +#define GLD_DEVICE +//#define OID_DEVICE +//#define OID_RF_DEVICE +//====================================================== +#define COMMAND_DEBUG + +#if defined(GLD_DEVICE) + #define FIRMWARE_VER 0xD // 9.13 - firmware version + #define NEW_THERMO_ADC + #define CONFIG_HFO_REG +// #define DELTA_SF_DELAY + #define CONFIG_PLC_SINUS +// #define CONFIG_HW_PLC + //#define CONFIG_SIMUL_HW_PLC // simulation of part of PLC regulator in FPGA + #define CONFIG_PLC_LIDEM // PLC reg. works with demodulated LI signal (demodulation in analog IC) +// #define CONFIG_PLC_LIM // PLC reg. works with modulated LI signal (demodulation inside FPGA) + #define WP_TRANSITION_ENA //e. allow the linear transition process for PLC reset //r. ðàçðåøåí ëèíåéíûé ïåðåõîäíîé ïðîöåññ ïðè îáíóëåíèè ÑÐÏ + + #define CONFIG_HFO_MOV_AVER_FILTER + + #define CONFIG_SIX_THERMO_SENSORS + + #define DEBUG_EXT_LAT_CNTR + + //#warning "=== GLD_DEVICE configuration selected ===" + +#elif defined(OID_DEVICE) + #define FIRMWARE_VER 0x1C // 1.12 - firmware version + + #define CONFIG_CURRENT_REG +// #define CONFIG_IA_STABILIZING + #define CONFIG_LI_STABILIZING +// #define CONFIG_IB_EQUAL_IA + #define CONFIG_IB_IA_BALANCE + + #define CONFIG_HW_PLC +// #define CONFIG_PLC_LIDEM // PLC reg. works with demodulated LI signal (demodulation in analog IC) + #define CONFIG_PLC_LIM // PLC reg. works with modulated LI signal (demodulation inside FPGA) + //#define CONFIG_SIMUL_HW_PLC // simulation of part of PLC regulator in FPGA + #define WP_TRANSITION_ENA //e. allow the linear transition process for PLC reset //r. ðàçðåøåí ëèíåéíûé ïåðåõîäíîé ïðîöåññ ïðè îáíóëåíèè ÑÐÏ + + //#warning "=== OID_DEVICE configuration selected ===" + +#elif defined(OID_RF_DEVICE) + #define FIRMWARE_VER 0x1C // 1.12 - firmware version + + #define CONFIG_HFO_REG + + #define CONFIG_HW_PLC +// #define CONFIG_PLC_LIDEM // PLC reg. works with demodulated LI signal (demodulation in analog IC) + #define CONFIG_PLC_LIM // PLC reg. works with modulated LI signal (demodulation inside FPGA) + + //#warning "=== OID_RF_DEVICE configuration selected ===" + +#else + #error "Not defined Device type" +#endif + +// -------- conditional compiles errors messages --------------------------- +#if !(defined(GLD_DEVICE) ^ defined(OID_DEVICE) ^ defined(OID_RF_DEVICE)) + #error "Should be defined only one device, not several" +#endif + +#if defined(CONFIG_PLC_LIDEM) & defined(CONFIG_PLC_LIM) + #error "Should be defined CONFIG_PLC_LIDEM or CONFIG_PLC_LIM, not both" +#endif + +#if !( defined(CONFIG_PLC_LIDEM) | defined(CONFIG_PLC_LIM) ) + #error "Not defined PLC mode: modulated / demodulated" +#endif + +#if defined(OID_DEVICE) +#if defined(CONFIG_IA_STABILIZING) & defined(CONFIG_LI_STABILIZING) + #error "Should be defined CONFIG_IA_STABILIZING or CONFIG_LI_STABILIZING, not both" +#endif + +#if !( defined(CONFIG_IA_STABILIZING) | defined(CONFIG_LI_STABILIZING) ) + #error "Not defined IA regulator mode: select CONFIG_IA_STABILIZING or CONFIG_LI_STABILIZING" +#endif + +#if defined(CONFIG_IB_EQUAL_IA) & defined(CONFIG_IB_IA_BALANCE) + #error "Should be defined CONFIG_IB_EQUAL_IA or CONFIG_IB_IA_BALANCE, not both" +#endif + +#if !( defined(CONFIG_IB_EQUAL_IA) | defined(CONFIG_IB_IA_BALANCE) ) + #error "Not defined IB regulator mode: select CONFIG_IB_EQUAL_IA or CONFIG_IB_IA_BALANCE" +#endif +#endif // OID_DEVICE + +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/console.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/console.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,145 @@ +#include "console.h" +#include "lpc17xx.h" +#include "CyclesSync.h" +#define FOSC 12000000 + +#define FCCLK (FOSC * 8) + +#define FCCO (FCCLK * 3) + +#define FPCLK (FCCLK / 4) + +#define UART0_BPS 38400 + + + +unsigned int BuffOut[1024]; + +unsigned int InputIndexBO; +unsigned int OutputIndexBO; + + + +unsigned int BuffIn[1024]; + +unsigned int InputIndexBI; +unsigned int OutputIndexBI; + +//unsigned int OLD_OutputIndex; + +void UART0_Init_m (void)///èíèéöèàëèçàöèÿ íóëåâîãî óàðòà +{ + uint16_t usFdiv; + /* UART0 */ + LPC_PINCON->PINSEL0 |= (1 << 4); /* Pin P0.2 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL0 |= (1 << 6); /* Pin P0.3 used as RXD0 (Com0) */ + + LPC_UART0->LCR = 0x83; + usFdiv = (FPCLK / 16) / UART0_BPS; + LPC_UART0->DLM = usFdiv / 256; + LPC_UART0->DLL = usFdiv % 256; + LPC_UART0->LCR = 0x03; + LPC_UART0->FCR = 0x06; +} + +int UART0_SendByte_m (int ucData) +{ + //while (!(LPC_UART0->LSR & 0x20)){}; + + return (LPC_UART0->THR = ucData); +} +void ClearBuffout(void) //î÷èñòêà áóôåðà íà âûäà÷ó(ñáðîñ óêàçàòåëåé) +{ + InputIndexBO=0; + OutputIndexBO=0; +} +void SendToBuffByte(unsigned int *input) // çàïèñü â áóôåð íà âûäà÷ó îäíîãî çíà÷åíèÿ èíò(áåççíàêîâîãî) +{ + InputIndexBO++; + InputIndexBO &= 0x3ff; + BuffOut[InputIndexBO]=*input; +} +void SendToBuff(unsigned char *input, unsigned int size)//çàïèñü íåñêîëüêèõ çíà÷åíèé ñ óêàçàíèåì ðàçìåðíîñòè çàïèñè â áóôåð íà âûäà÷ó. +{ + unsigned int i; + for(i=0;i<size;i++) + { + InputIndexBO++; + InputIndexBO &= 0x3ff; + BuffOut[InputIndexBO]=*input++; + } +} + + +void SendToBuffStr(char *s)//çàïèñü ñòðîêè (êîíåö îòñëåæèâàåòñÿ ïî íóëþ) â áóôåð íà âûäà÷ó. +{ + while (*s != 0) + { + InputIndexBO++; + InputIndexBO &= 0x3ff; + BuffOut[InputIndexBO]=*s++; + } +} + + +void TakeFromBuff(void)//ïåðåäà÷à èç áóôåðà íà âûäà÷ó. +{ + if((OutputIndexBO != InputIndexBO) && (LPC_UART0 -> LSR & 0x20)) + { + OutputIndexBO++; + OutputIndexBO &= 0x3ff; + LPC_UART0->THR = BuffOut[OutputIndexBO]; + } +} + + + +/* +void UART0_SendString (char *s) +{ + while (*s != 0) + { + InputIndex++; + InputIndex &= 0x3ff; + BuffOut[InputIndex]=*s++; + } +} +*/ + +void ClearBuffIn(void) +{ + InputIndexBI=0; + OutputIndexBI=0; +} + +void BuffDataReady(void) +{ + if((OutputIndexBI != InputIndexBI) && (!(LPC_UART0 -> LSR & 0x01))) + { + + } +} +void ReadDataInBuff(void) +{ + while (LPC_UART0->LSR & 0x01) + { + BuffIn[InputIndexBI] = LPC_UART0->RBR; + InputIndexBI++; + } +} + + + + + + + + + + + + + + + +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/console.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/console.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,20 @@ + +extern void UART0_Init (void); +extern int UART0_SendByte (int ucData); +extern void ClearBuFF(void); +extern void SendToBuff(unsigned char *input, unsigned int size); +extern void SendToBuffStr( char *s); +extern void TakeFromBuff(void); +extern void ClearBuffIn(void); + +extern void BuffDataReady(void); + + +extern unsigned int BuffOut[]; +extern unsigned int BuffIn[]; +extern unsigned int InputIndexBO; +extern unsigned int OutputIndexBO; +extern unsigned int InputIndexBI; +extern unsigned int OutputIndexBI; +extern unsigned int OLD_OutputIndex; +extern void UART0_SendString (char *s);
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/core_cm3.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/core_cm3.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1240 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration + List of Lint messages which will be suppressed and not shown: + - not yet checked + . + Note: To re-enable a Message, insert a space before 'lint' * + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +#include <stdint.h> /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_InterruptType CMSIS Interrupt Type + Type definitions for the Cortex-M Interrupt Type Register + @{ + */ + +/** \brief Structure type to access the Interrupt Type Register. + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ + +/*@}*/ /* end of group CMSIS_InterruptType */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) + { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else + { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + +/*lint -restore */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/core_cm3.h~RF1c0a0ba.TMP --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/core_cm3.h~RF1c0a0ba.TMP Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1236 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + + +/** \mainpage CMSIS Cortex-M3 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration + List of Lint messages which will be suppressed and not shown: + - not yet checked + . + Note: To re-enable a Message, insert a space before 'lint' * + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +#include <stdint.h> /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM CMSIS ITM + Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_InterruptType CMSIS Interrupt Type + Type definitions for the Cortex-M Interrupt Type Register + @{ + */ + +/** \brief Structure type to access the Interrupt Type Register. + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ + +/*@}*/ /* end of group CMSIS_InterruptType */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU CMSIS MPU + Type definitions for the Cortex-M Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Type definitions for the Cortex-M Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/** \brief Set Priority Grouping + + This function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + This function gets the priority grouping from NVIC Interrupt Controller. + Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + + \return Priority grouping field + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + This function enables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + This function reads the active register in NVIC and returns the active bit. + \param [in] IRQn Number of the interrupt for get active + \return 0 Interrupt status is not active + \return 1 Interrupt status is active + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + This function encodes the priority for an interrupt with the given priority group, + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The returned priority value can be used for NVIC_SetPriority(...) function + + \param [in] PriorityGroup Used priority group + \param [in] PreemptPriority Preemptive priority value (starting from 0) + \param [in] SubPriority Sub priority value (starting from 0) + \return Encoded priority for the interrupt + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + This function decodes an interrupt priority value with the given priority group to + preemptive priority value and sub priority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + The priority value can be retrieved with NVIC_GetPriority(...) function + + \param [in] Priority Priority value + \param [in] PriorityGroup Used priority group + \param [out] pPreemptPriority Preemptive priority value (starting from 0) + \param [out] pSubPriority Sub priority value (starting from 0) + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** \brief ITM Send Character + + This function transmits a character via the ITM channel 0. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \param [in] ch Character to transmit + \return Character to transmit + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + This function inputs a character via external variable ITM_RxBuffer. + It just returns when no debugger is connected that has booked the output. + It is blocking when a debugger is connected, but the previous character send is not transmitted. + + \return Received character + \return -1 No character received + */ +static __INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + This function checks external variable ITM_RxBuffer whether a character is available or not. + It returns '1' if a character is available and '0' if no character is available. + + \return 0 No character available + \return 1 Character available + */ +static __INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif + +/*lint -restore */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/core_cmFunc.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/core_cmFunc.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,844 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H__ +#define __CORE_CMFUNC_H__ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_CONTROL(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_CONTROL(uint32_t control); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_IPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_APSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_xPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PSP(uint32_t topOfProcStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_MSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_MSP(uint32_t topOfMainStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PRIMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PRIMASK(uint32_t priMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_BASEPRI(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_BASEPRI(uint32_t basePri); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_FAULTMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_FAULTMASK(uint32_t faultMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + + #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ + +#if defined (__ICCARM__) + #include <intrinsics.h> /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_irq __enable_interrupt + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_irq __disable_interrupt + + +/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ +/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static uint32_t __get_IPSR(void) +{ + __ASM("mrs r0, ipsr"); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static uint32_t __get_APSR(void) +{ + __ASM("mrs r0, apsr"); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static uint32_t __get_xPSR(void) +{ + __ASM("mrs r0, psr"); // assembler does not know "xpsr" +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); +} + + +/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ +/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq(void) +{ + __ASM ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq(void) +{ + __ASM ("cpsid f"); +} + + +/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ +/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ +/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ +/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + __ASM("vmrs r0, fpscr"); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM("vmsr fpscr, r0"); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + + __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H__ */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/core_cmInstr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/core_cmInstr.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,775 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.01 + * @date 06. December 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H__ +#define __CORE_CMINSTR_H__ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +extern uint32_t __REV16(uint32_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__ARMCC_VERSION < 400677) +extern int32_t __REVSH(int32_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#if (__ARMCC_VERSION < 400000) +extern void __CLREX(void); +#else /* (__ARMCC_VERSION >= 400000) */ +#define __CLREX __clrex +#endif /* __ARMCC_VERSION */ + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ + +#include <intrinsics.h> /* IAR Intrinsics */ + +#pragma diag_suppress=Pe940 + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __no_operation + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +static __INLINE void __WFI(void) +{ + __ASM ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE(void) +{ + __ASM ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +static __INLINE void __SEV(void) +{ + __ASM ("sev"); +} + + +/* intrinsic void __ISB(void) (see intrinsics.h) */ +/* intrinsic void __DSB(void) (see intrinsics.h) */ +/* intrinsic void __DMB(void) (see intrinsics.h) */ +/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */ +/* intrinsic __SSAT (see intrinsics.h) */ +/* intrinsic __USAT (see intrinsics.h) */ + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static uint32_t __REV16(uint32_t value) +{ + __ASM("rev16 r0, r0"); +} + + +/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +static uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +static uint8_t __LDREXB(volatile uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +static uint16_t __LDREXH(volatile uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */ +static uint32_t __LDREXW(volatile uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/ +static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +static __INLINE void __CLREX(void) +{ + __ASM ("clrex"); +} + +/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + +#pragma diag_default=Pe940 + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H__ */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/el_lin.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/el_lin.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,551 @@ + +/**--------------File Info--------------------------------------------------------------------------------- +** File name: el_lin.c +** Last modified Date: 2011-08-22 +** Last Version: V1.00 +**-------------------------------------------------------------------------------------------------------- +** Created by: Electrooptica Incor. +** Created date: 2011-08-22 +** Version: V1.00 +**-------------------------------------------------------------------------------------------------------- +*********************************************************************************************************/ +#include "CyclesSync.h" +#include "CntrlGLD.h" +#include "el_lin.h" + +#define UART1TEST +#define UART1REC +/* +struct { + uint32_t rcv_num_byt; + uint32_t rcv_num_byt_old; + uint32_t rcv_Rdy; + char rcv_copy[64]; + char rcv_buf[64]; + int32_t rx_buf_copy; + int32_t rcv_byt_copy; + }RECIEVER; + +struct { + uint32_t trm_num_byt; + uint32_t trm_rate; + uint32_t trm_cycl; + uint32_t num_of_par; + char trm_buf[64]; + void* addr_param[16]; + uint32_t size_param[16]; + uint32_t trm_ena; + }TRANSMITTER; +*/ + uint32_t rcv_num_byt; + uint32_t rcv_num_byt_old; + uint32_t rcv_Rdy; + char rcv_copy[64]; + char rcv_buf[64]; + int32_t rx_buf_copy; + int32_t rcv_byt_copy; + + uint32_t trm_num_byt; + uint32_t trm_rate; + uint32_t num_of_par; + char trm_buf[64]; + void* addr_param[16]; + uint32_t size_param[16]; + uint32_t trm_ena; + + uint32_t line_err; + uint32_t line_sts; + + uint32_t EnablLength = 12; + uint32_t LLI0_TypeDef[4]; + uint32_t LLI1_TypeDef[4]; + uint32_t EnablTx = 0x80; + uint32_t EnablDMA = 0; +/****************************************************************************** +** Function name: DMA_IRQHandler +** +** Descriptions: DMA interrupt handler +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +int check_lcc(void) //e. CRC checking //r.ïðîâåðêà êîíòðîëüíîé ñóììû +{ + int iCRC_calc, CRC_calc = 0, CRC_real; + + for (iCRC_calc = 1; iCRC_calc < (rcv_num_byt-2); iCRC_calc++) + CRC_calc += rcv_buf[iCRC_calc]; + + CRC_real = (rcv_buf[rcv_num_byt-2] << 8) | rcv_buf[rcv_num_byt-1]; + + return (CRC_real - CRC_calc); +} + void PacketSafing(void) + { + /* int j; static char rcv_buf_copy[16]; + for (j=2; j<rcv_num_byt; j++) + { + if (rcv_buf[j] == 0xCC); + rcv_buf_copy[0] = 0xCC; + // if ((rcv_buf[j] < 3) || (rcv_buf[j] == 0x1F)) + } */ + } + +/****************************************************************************** +** Function name: Line_1_Rcv +** +** Descriptions: receive process preparation +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void Line_1_Rcv(void) +{ + static int ToWaitEnd, ErrReg ; + + + + + while ((LPC_UART1->LSR & RecievBufEmpty) != 0) //e. reciever contain some information + rcv_buf[rcv_num_byt++] = LPC_UART1->RBR;//÷òåíèå èíôîðìàöèè èç áóôåðà. + + + + + if (( ToWaitEnd > 25000)) //e. end part of packet is absent //r. íå äîæäàëèñü êîíöà ïàêåòà + { + do + rcv_buf[--rcv_num_byt] = 0; + while(rcv_num_byt); + rcv_num_byt_old = rcv_num_byt; +#if defined UART1REC + LPC_UART1->FCR |= RX_FIFO_Reset; +#else + LPC_UART0->FCR |= RX_FIFO_Reset; +#endif + // L1_Rc_err (TIMEOUT_ERR); + ToWaitEnd = 0; + return; + } + if (rcv_num_byt_old == rcv_num_byt) //e. we have not received any new bytes + { + if (ToWaitEnd) ToWaitEnd++; + return; + } + rcv_num_byt_old = rcv_num_byt; + + if ((rcv_num_byt < 6) || ((rcv_num_byt & 0x0001) == 1)) + { + ToWaitEnd++; + return; + } + + if ((!ToWaitEnd) && (rcv_num_byt > 1)) //e. the header of packet has not recieved //r. îæèäàåì íà÷àëî ïàêåòà + if ((rcv_buf[0] != 0xCC) || (( rcv_buf[1] > 2) && ( rcv_buf[1] != 0x1F))) + { + // L1_Rc_err (HEADER_ERR); + ErrReg |= 5; + ToWaitEnd++; + return; + } + // if (ErrReg != 0) //e. trying of recovering of packet //r. ñïàñåíèå ñëåäóþùåãî ïàêåòà + // PacketSafing(); + + + if (rcv_num_byt == 6) + { + if ((rcv_buf[2] == 0x0A) || (rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4) || (rcv_buf[2] == 0xE6) || (rcv_buf[2] == 0xE8)) + { //e. packet length is not valid, so we have the error //r. îøèáêà ðàçìåðà ïàêåòà + ToWaitEnd++; + return; + } + + } + else if (rcv_num_byt == 8) + { + if ((rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4)) + { + ToWaitEnd++; + return; + } + } + if (check_lcc() != 0) //e. checksum is bad //r.êîíòðîëüíûå ñóììû íå ðàâíû + { + + return; + } + else //e. cheksum is not bad //r.êîíòðîëüíûå ñóììû ðàâíû + { + rcv_Rdy = 1; + } + ToWaitEnd = 0; + + return; + +} +/* +void L1_Rc_err (int Error) //e. error fixing and reciever restart //r. ìîäóëü ôèêñàöèè îøèáêè è ïåðåçàïóñêà ïðèåìíèêà +{ + int temp; + line_sts |= Error; + temp = Copy_SRgR & (~Rcv_Rdy); + io_space_write(Sys_RgR, temp); + temp |= Rcv_Rdy; + asm("nop;"); + io_space_write(Sys_RgR, temp); + return; +} +*/ + +/****************************************************************************** +** Function name: transm_DAT +** +** Descriptions: transmit process preparation +** +** parameters: None +** Returned value: None +** +******************************************************************************/ + + +void transm_DAT(void) +{ + uint32_t param, param_byte, CRC; + int32_t *trans_param; + + if ((LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. ïåðåäàþùèé áóôåð ïóñò + if (!( LPC_GPDMACH1->CConfig & (1<<17))) + LPC_GPIO2->FIOCLR |= 8; //switch off UART1 driver + + if (trm_ena == 0) + { +// LPC_GPIO1->FIOCLR = (0x01<<30); //r.ïåðåäà÷à òðåáóåòñÿ? + return; //r. åñëè íåò, âîçâðàò + } + + if (!(LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. ïåðåäàþùèé áóôåð ïóñò + return; + + if ( LPC_GPDMACH1->CConfig & (1<<17)) //r. åñëè êàíàë ïåðåäà÷è çàíÿò, æäàòü + return; + +//#if defined UART1TEST +// if (LPC_SC->DMAREQSEL == 0x8) //e. DMA request from UART +// LPC_GPIO2->FIOSET |= (1<<3); //e. set enable UART bit +//#endif + + trm_ena = 0; //r. ñáðîñèòü ôëàã ðàçðåøåíèÿ ïåðåäà÷è + + trm_num_byt = 2; + + trm_buf[0] = 0x00dd; //r. çàãîëîâîê ïàêåòà + trm_buf[1] = Device_blk.Str.My_Addres; //r. àäðåñ ïðèáîðà + + CRC = trm_buf[1]; //r.èíèöèàëèçàöèÿ ñ÷åò÷èêà êîíòðîëüíîé ñóììû + for ( param = 0; param < num_of_par; param++) //r.öèêë ôîðìèðîâàíèÿ áëîêà äàííûõ ïàêåòà + { + trans_param = (int32_t *)addr_param[param]; //r. ÷òåíèå àäðåñà îäíîãî èç âûäàâàåìûõ â ïàêåòå ïàðàìåòðîâ + + for (param_byte = 0; param_byte < size_param[param]; param_byte++) + { + if ( (param_byte & 0x0001) == 0 ) //r. ñ÷èòûâàåì ñòàðøèé áàéò + trm_buf[trm_num_byt] = (*trans_param >> (8/**(size_param[param]-param_byte-1)*/)) & 0x00ff; //r.ðàçìåùåíèå ïåðåäàâàåìîãî ïàðàìåòðà â ïàêåòå + else + { + trm_buf[trm_num_byt] = *trans_param & 0x00ff; + trans_param ++; //r.ïåðåõîäèì ê ñëåäóþùåé ÿ÷åéêå ïàìÿòè + } + CRC += trm_buf[trm_num_byt]; //r. âû÷èñëåíèå òåêóùåé êîíòðîëüíîé ñóììû + trm_num_byt++; //r. êîëè÷åñòâî áèò, îòïðàâëåííûõ â ïàêåò + } + } + trm_buf[trm_num_byt] = CRC >> 8; //r. çàïèñü êîíòðîëüíîé ñóììû â ïàêåò + trm_buf[trm_num_byt+1] = CRC & 0x00ff; + + trm_num_byt += 2; + + LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf; + + LPC_GPDMACH1->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting + LPC_GPDMACH2->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting + + LPC_GPDMACH1->CLLI = 0; //e. linked list is empty + + if (trm_num_byt > 16) //e. a packet is too long for FIFO + { + LPC_GPDMACH1->CControl |= 16; //e. set length of first packet part + LPC_GPDMACH1->CLLI = (uint32_t)&LLI0_TypeDef; //e. initialize chain for other parts transmitting + } + else + LPC_GPDMACH1->CControl |= trm_num_byt; + + LPC_GPDMACH2->CControl |= 1; //e. set 1 transfert for enable signal +#if defined UART1TEST + LPC_UART1->TER = 0; //e. disable data output to UART1 +#endif + if (Device_Mode < 4) //e. work with internal latch + { + LPC_TIM0->TCR = 1; //e. start timer +//-------------------debug----------------------------------------- + LPC_GPIO2->FIOSET |= 8; //turn on RS-422 driver +//-------------------debug----------------------------------------- + + LPC_GPDMACH1->CConfig |= DMAChannelEn; //e. DMA for UART transmition + //LPC_GPIO1->FIOSET = (0x1<<30); + + } + + LPC_GPDMACH2->CConfig |= DMAChannelEn; //e. DMA for enable signal + return; +} +/****************************************************************************** +** Function name: DMA_Init +** +** Descriptions: +** +** parameters: +** Returned value: +** +******************************************************************************/ +void DMA_Init( void ) +{ + /* Enable CLOCK into GPDMA controller */ + LPC_SC->PCONP |= GPDMA_POWER_ON; + + /* Select primary function(UART0/1/2/3) in DMA channels, + secondary is timer 0/1/2/3. */ +#if defined UART1TEST + LPC_SC->DMAREQSEL = 3; +#endif + //LPC_GPDMA->Sync = (0x1<<DMA_UART0_RX)|(0x1<<DMA_UART1_TX); //synchronization logic is enabled by default + LPC_GPDMA->Config = DMA_ControllerEn | DMA_AHB_Little; + while ( !(LPC_GPDMA->Config & DMA_ControllerEn) ); //wait until DMA_Controller switched on + + NVIC_DisableIRQ(DMA_IRQn); + return; +} + +/****************************************************************************** +** Function name: UARTInit +** +** Descriptions: Initialisation of UART on 38400 baud +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void UARTInit(void) +{ + uint32_t Fdiv; + uint32_t pclk; +#if !defined UART1TEST + uint32_t baudrate = 38400; +#else + uint32_t baudrate = 38400; +#endif + LPC_SC->PCONP |= (1<<3); + + LPC_PINCON->PINSEL0 |= 0x00000050; + + pclk = SystemCoreClock/4; + + LPC_UART0->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access; + Fdiv = (pclk / 16) / baudrate; + LPC_UART0->DLM = Fdiv / 256; + LPC_UART0->DLL = Fdiv % 256; + LPC_UART0->LCR &= ~DLAB_access; + LPC_UART0->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06; + LPC_UART0->IER = 0;//RBR_IntEnabl; + + LPC_UART0->FCR |= 0x08; //e. DMA mode select + //+++++++++++++++++++++++enable signal initialization++++++++++++++++++++++++++ + LPC_PINCON->PINSEL1 &= ~0x0000C000; //e. select P0.23 as general purpose + LPC_GPIO0->FIODIR |= 0x00800000; //e. P0.23 is output +// LPC_GPIO0->FIOMASK |= 0x007F0000; //e. P0.16..P0.22 is not changed by FIOSET writing + LPC_GPIO0->FIOCLR |= 0x00800000; // e. clear P0.23 + + return; +} + +void UART1_Init(void) +{ + uint32_t Fdiv; + uint32_t pclk; +#if !defined UART1TEST + uint32_t baudrate = 256000; + #else + uint32_t baudrate = 38400; +#endif + LPC_SC->PCONP |= (1<<4); //switch on UART1 + + LPC_PINCON->PINSEL4 |= (2<<0)|(2<<2)|(2<<10)|(2<<14); //P2.0, P2.1, P2.5, P2.7 + + pclk = SystemCoreClock/4; + + LPC_UART1->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access; + Fdiv = (pclk / 16) / baudrate; + LPC_UART1->DLM = Fdiv / 256; + LPC_UART1->DLL = Fdiv % 256; + LPC_UART1->LCR &= ~DLAB_access; + LPC_UART1->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06; + + LPC_UART1->RS485CTRL = (1<<5); //(1<<4); + + LPC_UART1->IER = 0;//RBR_IntEnabl; + + LPC_UART1->FCR |= 0x08; //e. DMA mode select + return; +} +//----------------------temp---------------------------- +/*int UART0_SendByte (int ucData) +{ +// while (!(LPC_UART1->LSR & 0x20)); + return (LPC_UART0->THR = ucData); +}*/ +//----------------------temp---------------------------- +int UART1_SendByte (int ucData) +{ +// while (!(LPC_UART1->LSR & 0x20)); + return (LPC_UART1->THR = ucData); +} +/****************************************************************************** +** Function name: UART_SwitchSpeed +** +** Descriptions: Change UART speed +** +** parameters: Demanded speed +** Returned value: None +** +******************************************************************************/ +void UART_SwitchSpeed(unsigned Speed) +{ + uint32_t Fdiv; + uint32_t pclk; + + pclk = SystemCoreClock/4; +#if defined UART1REC + LPC_UART1->LCR |= DLAB_access; +#else + LPC_UART0->LCR |= DLAB_access; +#endif + switch (Speed) + { + case Sp38400: + Fdiv = (pclk / 16) / 38400; + EnablLength = 3240; + break; + + case Sp115200: + Fdiv = (pclk / 16) /115200; + EnablLength = 1090; + break; + + case Sp460800: + Fdiv = (pclk / 16) / 460800; + break; + + case Sp921600: + Fdiv = (pclk / 16) / 921600; + EnablLength = 140; + break; + + } +#if defined UART1REC + LPC_UART1->DLM = Fdiv / 256; + LPC_UART1->DLL = Fdiv % 256; + LPC_UART1->LCR &= ~DLAB_access; +#else + LPC_UART0->DLM = Fdiv / 256; + LPC_UART0->DLL = Fdiv % 256; + LPC_UART0->LCR &= ~DLAB_access; +#endif +} +/****************************************************************************** +** Function name: UART_DMA_Init +** +** Descriptions: Initialisation of DMA channel for UART transmitter +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void UART_DMA_Init() +{ +//+++++++++++++++++config channel for UART0+++++++++++++++++++++++++++++++++++++++++++++++ + LPC_GPDMACH1->CConfig &= ~DMAChannelEn; + + LPC_GPDMA->IntTCClear = DMA1_IntTCClear; + LPC_GPDMA->IntErrClr = DMA1_IntErrClear; + + LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf; + LPC_GPDMACH1->CDestAddr = UART1_DMA_TX_DST; + LPC_GPDMACH1->CControl = SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; +#if defined UART1TEST + LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART1_TX |(M2P << 11); +#else + g LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART0_TX |(M2P << 11); +#endif + + EnablDMA = (LPC_GPDMACH1->CConfig)|DMAChannelEn; //save register content for DMA starting in multidrop mode +//**********for Rate mode output***************************** + #if defined UART1TEST + LLI1_TypeDef[0] = (uint32_t)&trm_buf[32]; + LLI1_TypeDef[1] = UART1_DMA_TX_DST; + LLI1_TypeDef[2] = 0; + LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; + + LLI0_TypeDef[0] = (uint32_t)&trm_buf[16]; + LLI0_TypeDef[1] = UART1_DMA_TX_DST; + LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef; + LLI0_TypeDef[3] = (16 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; +#else + LLI1_TypeDef[0] = (uint32_t)&trm_buf[32]; + LLI1_TypeDef[1] = UART0_DMA_TX_DST; + LLI1_TypeDef[2] = 0; + LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl; + + LLI0_TypeDef[0] = (uint32_t)&trm_buf[16]; + LLI0_TypeDef[1] = UART0_DMA_TX_DST; + LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef; + LLI0_TypeDef[3] = (16 & 0x0FFF)|SrcBSize_1 |DstBSize_1 |SrcWidth_8b + |DstWidth_8b|SrcInc |DstFixed |TCIntDisabl; +#endif +//++++++++++++++++++++++++++config channel for transmit enable signal+++++++++++++++++++ + LPC_GPDMACH2->CConfig &= ~DMAChannelEn; + + LPC_GPDMA->IntTCClear = DMA2_IntTCClear; + LPC_GPDMA->IntErrClr = DMA2_IntErrClear; + + LPC_GPDMACH2->CSrcAddr = (uint32_t)&EnablTx; //e. content of TX UART1 enable register + LPC_GPDMACH2->CDestAddr = 0x40010030; //e. address of TX UART1 enable register (U1TER) + + LPC_GPDMACH2->CControl = SrcBSize_4 |DstBSize_4 + |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl; + + LPC_GPDMACH2->CConfig |= MaskTCInt |MaskErrInt + |SrcDMA_UART0_RX |DstDMA_UART0_RX|(M2P << 11); + LPC_GPDMACH2->CLLI = 0; //e. linked list is empty + +//++++++++++++++++++++++++++config channel for DMA1 enable signal+++++++++++++++++++ +#if defined UART1TEST + LPC_GPDMACH4->CConfig &= ~DMAChannelEn; + + LPC_GPDMA->IntTCClear = DMA4_IntTCClear; + LPC_GPDMA->IntErrClr = DMA4_IntErrClear; + + LPC_GPDMACH4->CSrcAddr = (uint32_t)&EnablDMA; //e. content of TX UART1 enable register + LPC_GPDMACH4->CDestAddr = 0x50004130; //e. address of DMA1CConfig register + + LPC_GPDMACH4->CControl = SrcBSize_4 |DstBSize_4 + |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl; + + LPC_GPDMACH4->CConfig |= MaskTCInt |MaskErrInt + |SrcDMA_UART0_TX |DstDMA_UART0_TX|(M2P << 11); + LPC_GPDMACH4->CLLI = 0; //e. linked list is empty +#endif +} +/****************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/el_lin.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/el_lin.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,216 @@ + +/**--------------File Info--------------------------------------------------------------------------------- +** File name: el_lin.h +** Last modified Date: 2011-08-22 +** Last Version: V1.00 +** Descriptions: +** +**-------------------------------------------------------------------------------------------------------- +** Created by: Electrooptika incor. +** Created date: 2011-08-22 +** Version: V1.00 +** +**-------------------------------------------------------------------------------------------------------- +*********************************************************************************************************/ +#ifndef __DMA_H +#define __DMA_H + + + +#define STRT_ERR 0x0080 //e. error of the start bit //r. îøèáêà ñòàðò-áèòà +#define STOP_ERR 0x0040 //e. error of the stop bit //r. îøèáêà ñòîï-áèòà +#define SIZE_ERR 0x0004 //e. size of the received data packet mismatches the agreement //r. ðàçìåð ïðèíÿòîãî ïàêåòà íå ñîîòâåòñòâóåò ñîãëàøåíèþ +#define LCC_ERR 0x0002 //e. checksum has not coincided //r. íå ñîâïàëà êîíòðîëüíàÿ ñóììà +#define NO_CMD_ERR 0x0100 //e. in the received packet there is no attribute of command //r. â ïðèíÿòîì ïàêåòå íåò ïðèçíàêà êîìàíäû +#define CODE_ERR 0x0200 //e. unknown code of a command //r. íåèçâåñòíûé êîä êîìàíäû +#define MODE_ERR 0x0400 //e. code of a command mismatches a current mode //r. êîä êîìàíäû íå ñîîòâåòñòâóåò òåêóùåìó ðåæèìó +#define PARAM_ERR 0x0800 //e. parameters of a command was set incorrectly //r. íåâåðíî çàäàííûå ïàðàìåòðû êîìàíäû +#define MAXSIZE_ERR 0x1000 //e. receiver buffer overflow //r. ïåðåïîëíåíèå áóôåðà ïðèåìíèêà +#define ADDR_ERR 0x2000 //e. incorrect address of the device //r. íåâåðíûé àäðåñ óñòðîéñòâà +#define READ_ERR 0x4000 //e. stop of link because of untimely data read //r. îñòàíîâ ñâÿçè íåñâîåâðåìåííûì ÷òåíèåì äàííûõ +#define WASQ_ERR 0x8000 //e. error of waiting of authentic answer //r. îøèáêà îæèäàíèÿ äîñòîâåðíîãî îòâåòà + +#define Trm_En_Rd 0x0080 //e. a mask of permission/readiness of transmitter of the 2 line //r. ìàñêà ðàçðåøåíèÿ/ãîòîâíîñòè ïåðåäàò÷èêà ëèíèè 2 +#define Rcv_Rdy 0x0040 //e. a mask of the readiness bit of the receiver //r. ìàñêà áèòà ãîòîâíîñòè ïðèåìíèêà +#define Rcv_Ferr 0x0020 //e. a mask of the "format error" bit //r. ìàñêà áèòà "îøèáêà ôîðìàòà" +#define Rcv_Tout 0x0010 //e. a mask of the "time-out" bit //r. ìàñêà áèòà "òàéì-àóò" +#define Rcv_Rful 0x0008 //e. a mask of the "stack is full" bit //r. ìàñêà áèòà "ñòåê ïîëîí" + + +#define FIFOs_En 0x00000001 +#define RX_FIFO_Reset 0x00000002 +#define TX_FIFO_Reset 0x00000004 +#define DMA_Mode_UART 0x00000008 +#define RX_TrigLvl_1 0x00000000 +#define RX_TrigLvl_4 0x00000040 +#define RX_TrigLvl_8 0x00000080 +#define RX_TrigLvl_14 0x000000C0 + +#define word_length_8 0x00000003 + +#define one_stop_bit 0x00000000 + +#define no_parity 0x00000000 + +#define back_trans_dis 0x00000000 + +#define DLAB_access 0x00000080 + +#define TRANS_SHIFT_BUF_EMPTY 0x00000040 +#define DMA_BUSY 0x00020000 +#define RecievBufEmpty 0x00000001 +#define DIS_ALL_INT 0x00000000 +#define RBR_IntEnabl 0x00000001 +/* Second half of the second RAM is used for GPDMA operation. */ + +#define DMA_UART0_TX 8 +#define DMA_UART0_RX 9 +#define DMA_UART1_TX 10 +#define DMA_UART1_RX 11 +#define DMA_UART2_TX 12 +#define DMA_UART2_RX 13 +#define DMA_UART3_TX 14 +#define DMA_UART3_RX 15 + +#define DMA_MEMORY 0 +#define SrcDMA_UART0_RX DMA_UART0_RX << 1 +#define SrcDMA_UART0_TX DMA_UART0_TX << 1 +#define SrcDMA_UART1_TX DMA_UART1_TX << 1 +#define DstDMA_UART0_TX DMA_UART0_TX << 6 +#define DstDMA_UART1_TX DMA_UART1_TX << 6 +#define DstDMA_UART0_RX DMA_UART0_RX << 6 +#define SrcDMA_UART1_RX DMA_UART1_RX << 1 +#define DstDMA_UART1_RX DMA_UART1_RX << 6 + +/* UART0 TX and RX */ +#define UART0_DMA_TX_SRC 0x2007C800 /* starting addr of DATA register in UART0 */ +#define UART0_DMA_TX_DST LPC_UART0_BASE +#define UART0_DMA_RX_SRC LPC_UART0_BASE +#define UART0_DMA_RX_DST 0x2007C900 + +#define UART2_DMA_TX_DST LPC_UART2_BASE +#define UART1_DMA_TX_DST LPC_UART1_BASE + +#define GPDMA_POWER_ON 0x20000000 + +#define UART_REQ 0x00000000 + +//To clear particular DMA TC-interrupts +#define DMA0_IntTCClear 0x00000001 +#define DMA1_IntTCClear 0x00000002 +#define DMA2_IntTCClear 0x00000004 +#define DMA3_IntTCClear 0x00000008 +#define DMA4_IntTCClear 0x00000010 +#define DMA5_IntTCClear 0x00000020 +#define DMA6_IntTCClear 0x00000040 +#define DMA7_IntTCClear 0x00000080 + +//To clear particular DMA Error-interrupts +#define DMA0_IntErrClear 0x00000001 +#define DMA1_IntErrClear 0x00000002 +#define DMA2_IntErrClear 0x00000004 +#define DMA3_IntErrClear 0x00000008 +#define DMA4_IntErrClear 0x00000010 +#define DMA5_IntErrClear 0x00000020 +#define DMA6_IntErrClear 0x00000040 +#define DMA7_IntErrClear 0x00000080 +#define DMACH1_IntTCPend 0x00000002 + +#define DMA_ControllerEn 0x00000001 + +#define DMA_AHB_Little 0x00000000 +#define DMA_AHB_Big 0x00000002 + +#define SrcBSize_1 0x00000000 +#define SrcBSize_4 0x00001000 +#define SrcBSize_8 0x00002000 +#define SrcBSize_16 0x00003000 +#define SrcBSize_32 0x00004000 +#define SrcBSize_64 0x00005000 +#define SrcBSize_128 0x00006000 +#define SrcBSize_256 0x00007000 + +#define DstBSize_1 0x00000000 +#define DstBSize_4 0x00008000 +#define DstBSize_8 0x00010000 +#define DstBSize_16 0x00018000 +#define DstBSize_32 0x00020000 +#define DstBSize_64 0x00028000 +#define DstBSize_128 0x00030000 +#define DstBSize_256 0x00038000 + +#define SrcWidth_8b 0x00000000 +#define SrcWidth_16b 0x00020000 +#define SrcWidth_32b 0x00040000 + +#define DstWidth_8b 0x00000000 +#define DstWidth_16b 0x00200000 +#define DstWidth_32b 0x00400000 + +#define SrcInc 0x04000000 +#define SrcFixed 0x00000000 + +#define DstInc 0x08000000 +#define DstFixed 0x00000000 + +#define TCIntEnabl 0x80000000 +#define TCIntDisabl 0x00000000 + +#define DMAChannelEn 0x00000001 +#define DMAChannelDis 0x00000000 + +#define CH2_ENABLED 0x00000004 + +#define DONtMaskTCInt 0x00008000 +#define MaskTCInt 0x00000000 +#define DONtMaskErrInt 0x00004000 +#define MaskErrInt 0x00000000 + +#define INT_DMA_Disabl 0x04000000 +/* DMA mode */ +#define M2M 0x00 +#define M2P 0x01 +#define P2M 0x02 +#define P2P 0x03 + +#define Sp38400 0x00000 +#define Sp115200 0x00010 +#define Sp460800 0x00020 +#define Sp921600 0x00030 + +extern unsigned int trm_num_byt; +extern unsigned int rcv_num_byt; +extern unsigned int rcv_Rdy; +extern char trm_buf[64]; +extern char rcv_buf[64]; +extern char rcv_copy[64]; +extern unsigned int trm_cycl; +extern unsigned int num_of_par; +extern void* addr_param[16]; +extern unsigned int size_param[16]; +extern unsigned int trm_rate; +extern unsigned int trm_cycl; +extern unsigned int rcv_num_byt_old; +extern int rcv_byt_copy; +extern unsigned int trm_ena; +extern int cycl_phase; +extern unsigned int line_err; +extern unsigned int line_sts; +extern int rx_buf_copy; +extern char zeros; +extern unsigned int SystemCoreClock; + +extern void DMA_Init(void); +extern void transm_DAT(void); +extern void Line_1_Rcv(void); + +extern void UARTInit(void); +extern void UART1_Init(void); +//extern int UART0_SendByte(int); +extern int UART1_SendByte(int); +extern void UART_SwitchSpeed(unsigned); +extern void UART_DMA_Init(void); +extern void SystemCoreClockUpdate (void); + +#endif /* end __DMA_H */ +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/main.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/main.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,415 @@ +/****************************************Copyright (c)**************************************************** +**--------------File Info--------------------------------------------------------------------------------- +** File name: main.c +** Last modified Date: 2011-10-24 +** Last Version: V1.00 +** Descriptions: The main() function +** +**-------------------------------------------------------------------------------------------------------- +** Created by: Electrooptica Incorp. +** Created date: 2011-08-22 +** Version: V1.00 +** Descriptions: +**-------------------------------------------------------------------------------------------------------- +*********************************************************************************************************/ +#include "SIP.h" +#include "el_lin.h" +#include "CyclesSync.h" +#include "Parameters.h" +#include "Dither_Reg.h" +#include "commandset.h" +#include "CntrlGLD.h" +#include "InputOutput.h" +#include <math.h> +#include "stdlib.h" +#include "console.h" +#include "vibro.h" +#include "QEI.h" +#include "MTimer.h" +#include "Global.h" +#include "SPI.h" +#include "uart_m.h" +#include "command.h" +#include "Global.h" + +///ÕÅÐÍß + +/****************************************************************************** +** Main Function main() +******************************************************************************/ +extern uint32_t CMD_Mode; +////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////// + + int i1 =0; +//extern unsigned int Buff_QEI[256]; +volatile unsigned int IRQ_Counter=0; +volatile uint32_t timer1_counter = 0; +int temp111=0,temp=0; +int y = 0; +int CuruAngleOld=0; +unsigned int LightUpCount,BackLightCount,secPuls,CountBI,CmmandIn,tt,th; + + +unsigned int paramV; + + + + +void Led_init() +{ + LPC_PINCON->PINSEL0 = (0x00<<28); + LPC_GPIO1->FIODIR = (0x1<<30); + LPC_PINCON->PINMODE0 = (0x3<<28); + // LPC_GPIO1->FIOSET = (0x0<<30); + // LPC_GPIO0->FIOSET = (1<<4); +} +int flag=0, TIME=0,t=0, Sec=0,tmpSec=0,SEC=0, mSec=0; +int tempsec=0; +float DACF, K_DAC; +void Led_Blink() +{ + + if (flag == 0) + { + LPC_GPIO1->FIOSET = (0x1<<30); + flag=1; + } + else + { + flag =0; + LPC_GPIO1->FIOCLR = (0x01<<30); + } +} + +long LED_TEMP=0; + + + +int main (void) +{ + +{ + K_DAC=65535.0/(65535.0+(deltaDAC+deltaDAC/2)); + K_DAC=0.8; + Main.Firmware_Version=0x15; + Main.GLD_Serial = 0x20; + Main.My_Addres=0; + LightUpCount=1000; + BackLightCount=5000; + secPuls=0; + Pulse_midl = 0; + PulseHalf = 0; + CuruAngle = 0; + Spi.DAC_A=0x7fff; + Spi.DAC_B=0x7fff; + //èíèöèàëèçàöèÿ + SystemInit(); // Èíèöèàëèçàöèÿ ñèñòåìû + Led_init(); + + ///* + //êîíôèãóðèðîâàíèå ñèãíàëà ïîäæèãà + LPC_PINCON->PINSEL0 &= ~(3<<8); //e. P0.4 is GPIO pin (çàïèñü ( 00 ) â 9:8 áèò PISEL0 âûáîð P0.4 êàê GPIO) + LPC_PINCON->PINMODE0 |= (3<<8); //e. P0.4 is GPIO pin (çàïèñü ( 11 ) â 9:8 áèò PINMODE0 "äëÿ âêëþ÷åíèÿ ïîäòÿãèâàþùåãî ðåçèñòîðà") + LPC_GPIO0->FIODIR |= (1<<4); //e. P0.4 is output (çàïèñü ( 1 ) â 5 áèò FIODIR âûáîð P0.4 êàê âûõîä) + LightUpON //e. P0.4 is output (çàïèñü ( 1 ) â 5 áèò CLR óñòàíàâëèâàåì íà P0.4 íèçêèé óðîâåíü ñèãíàëà) + /* + LPC_PINCON->PINSEL0 &= ~(3<<10); //e. P0.4 is GPIO pin (çàïèñü ( 00 ) â 9:8 áèò PISEL0 âûáîð P0.4 êàê GPIO) + LPC_PINCON->PINMODE0 |= (3<<10); //e. P0.4 is GPIO pin (çàïèñü ( 11 ) â 9:8 áèò PINMODE0 "äëÿ âêëþ÷åíèÿ ïîäòÿãèâàþùåãî ðåçèñòîðà") + LPC_GPIO0->FIODIR |= (1<<5); //e. P0.4 is output (çàïèñü ( 1 ) â 5 áèò FIODIR âûáîð P0.4 êàê âûõîä) + LPC_GPIO0->FIOCLR |= (1<<5); //e. P0.4 is output (çàïèñü ( 1 ) â 5 áèò CLR óñòàíàâëèâàåì íà P0.4 íèçêèé óðîâåíü ñèãíàëà)*/ +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + LPC_PINCON->PINSEL3 = (0x00<<18); //e. P1.25 is GPIO pin + LPC_PINCON->PINMODE3 |= (3<<18); //e. P1.25 (âêëþ÷åíèe ïîäòÿãèâàþùåãî ðåçèñòîðà") + LPC_GPIO1->FIODIR |= (1<<25); //e. P0.5 is output (çàïèñü ( 1 ) â 5 áèò FIODIR âûáîð P0.5 êàê âûõîä) + LPC_GPIO1->FIOCLR |= (1<<25); + + +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + LPC_PINCON->PINSEL3 = (0x00<<24); //e. P1.28 is GPIO pin + LPC_PINCON->PINMODE3 |= (3<<24); //e. P1.28 is GPIO pin (çàïèñü ( 11 ) â áèò PINMODE0 "äëÿ âêëþ÷åíèÿ ïîäòÿãèâàþùåãî ðåçèñòîðà") + LPC_GPIO1->FIODIR |= (1<<28); //e. P1.28 is output (çàïèñü ( 1 ) â 5 áèò FIODIR âûáîð P0.5 êàê âûõîä) + LPC_GPIO1->FIOCLR |= (1<<28); +// init_timer(TIME_INTERVAL ); // 10ms + // enable_timer1(); +///èÍÈöèàëèçàöèÿ ïîäñâåòêè + LPC_PINCON->PINSEL2 = (0x00<<24); //e. P2.12 is GPIO pin + LPC_PINCON->PINMODE3 |= (3<<24); //e. P1.28 is GPIO pin (çàïèñü ( 11 ) â áèò PINMODE0 "äëÿ âêëþ÷åíèÿ ïîäòÿãèâàþùåãî ðåçèñòîðà") + LPC_GPIO2->FIODIR |= (1<<12); //e. P1.28 is output (çàïèñü ( 1 ) â 5 áèò FIODIR âûáîð P0.5 êàê âûõîä) + LPC_GPIO2->FIOCLR |= (1<<12); + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* + //êîíôèãóðèðîâàíèå ñèãíàëà ïîäæèãà îòîðâàíàÿ íîãà (ïîäæèã íà 80 íîãå âìåñòî 81) + LPC_PINCON->PINSEL0 = (0x00<<10); //e. P0.5 is GPIO pin (çàïèñü ( 00 ) â 11:10 áèò PISEL0 âûáîð P0.5 êàê GPIO) + LPC_PINCON->PINMODE0 |= (3<<10); //e. P0.5 is GPIO pin (çàïèñü ( 11 ) â 11:10 áèò PINMODE0 "äëÿ âêëþ÷åíèÿ ïîäòÿãèâàþùåãî ðåçèñòîðà") + LPC_GPIO0->FIODIR |= (1<<5); //e. P0.5 is output (çàïèñü ( 1 ) â 5 áèò FIODIR âûáîð P0.5 êàê âûõîä) + LPC_GPIO0->FIOCLR |= (1<<5); //e. P0.5 is output (çàïèñü ( 1 ) â 5 áèò CLR óñòàíàâëèâàåì íà P0.5 íèçêèé óðîâåíü ñèãíàëà) + */ + DMA_Init(); // Èíèöèàëèçàöèÿ DMA + FlashDMA_Init(); // Çàãðóçêà ïàðàìåòðîâ ñ ôëýø + + SystemCoreClockUpdate(); // ðàñ÷åò ñèñòåìíîé ÷àñòîòû äëÿ UART. + UARTInit(); // èíèöèàëèçàöèÿ UART0 íà ñêîðîñòü 38400. + UART1_Init(); // èíèöèàëèçàöèÿ UART1 íà ñêîðîñòü 38400. + + + DAC_ADC_Exchange_Init(); // èíèöèàëèçàöèÿ îáìåíà ÀÖÏ è ÖÀÏ. + DACInit(); // èíèöèàëèçàöèÿ ÖÀÏ. + SOI_Init(); // Èíèöèàëèçàöèÿ êâàäðàòóðíîãî ýíêîäåðà. + + IntLatch_Init(); // èíèöèàëèçàöèÿ âíóòðåííåé çàùåëêè. + ExtLatch_Init(); // èíèöèàëèçàöèÿ âíåøíåé çàùåëêè. + +//----------------debug------------------------- + //LPC_GPIO2->FIODIR = 0x5C; // P2.0...P2.7 defined as Outputs + //LPC_GPIO2->FIOCLR = 0x5C; // turn off all the LEDs +//----------------debug------------------------- + + + LoadFlashParam(FromFLASH); //çàãðóçêà ïàðàìåòðîâ. + UART_DMA_Init(); //èíèöèàëèçàöèÿ DMA äëÿ UART. + G_Photo_Init(); //èíèöèàëèçàöèÿ èíòåðôåéñà I2C äëÿ ôîòîäåòåêòîðà. + Out_G_photo(60, 60); //çàïèñü â áóôåð ìàñòåðà ïðèíÿòûå îò ôóíêöèè äàííûå (60,60) è óñòàíîâêà ôëàãà ñòàðòà ïåðåäà÷è è çàíÿòîé øèíû. +// WDTInit(); + + + open_all_loops(); //#define open_all_loops() RgConA = 0 (Îñíîâíîé ðåãèñòð óïðàâëåíèÿ óñòðîéñòâà (0 - âêëþ÷èòü, 1 - îòêëþ÷èòü)). + Output.Str.HF_reg = Device_blk.Str.HF_min; //HFO output voltage = ìàêñèâàëüíîå íàïðÿæåíèå íà ÃÂ×. + init_PLC(); //Èíèöèàëèçàöèÿ ÑÐÏ(ðåãóëèðîâêà ïåðèìåòðà) + init_Dither_reg(); //èíèöèàëèçàöèÿ âèáðîïðèâîäà + RgConB = RATE_VIBRO_1; // äîïîëíèòåëüíûé ðåãèñòð óïðàâëåíèÿ = ðàçíîñòü âèáðîñ÷åò÷èêîâ ïîñëå ôèëüòðà ñêîëüç.ñðåäíåãî(#define RATE_VIBRO_1 0x0001) + init_Vibro(); + init_timer(TIME_INTERVAL ); // 10ms + enable_timer1(); + Init_TIM2(); + enable_timer2(); + close_all_loops(); + + LPC_GPIO0->FIOCLR = (1<<5); + } + + + Pulse_8Point = 0; + Pulse_16Point = 0; + Pulse_32Point = 0; + + Temp_AMP=0; + Temp_ADC_2=0; + Temp_ADC_3=0; + Temp_ADC_4=0; + Temp_ADC_5=0; + + + +for (y = 0; y < 256; y++ ) + { + Buff_16Point [y] = 0xffff; + Buff_8Point [y] = 0xffff; + Buff_32Point [y] = 0xffff; + Buff_ADC_1 [y] = 0;// àìïë àöï. + Buff_ADC_2 [y] = 0; + Buff_ADC_3 [y] = 0; + Buff_ADC_4 [y] = 0; + Buff_ADC_5 [y] = 0; + + } + + + +SendToBuffStr ("\n\r ....... "); +OutBufConCount =0; + WriteCon("\n\r ...WriteCon1.... "); + do //îñíîâíîé öèêë. + { + + + if (OutBufConCount) OutBufConCount--; + Concol (); + // Concol1 (); + Read_CMD(); + + // VibroOut(); + + + if(Time_1kHz>100) + { + + SEC++; + if(Rate_Flag==1&&SEC>500) + { + SEC-=500; + CMD_Rate(); + } + + Time_1kHz-=100; + if(LightUpCount){LightUpCount--;LightUpON} + + else + { + LightUpOFF; + } + if(BackLightCount){BackLightCount--;BackLightON} + else + { + BackLightOFF; + } + } + ButtonLightUP(); + //Device_blk.Str. + TakeFromBuff(); + + //îòêëþ÷åíèå ïîäæèãà. + + // paramV=TakeParam(1); + + + + + + if (LPC_PWM1->IR & 0x0001) // Åñëè â ðåãèñòðå ïðåðûâàíèé ØÈÌ1 (ðåãèñòð PWM1IR) åñòü âëàã ïðåðûâàíèÿ ñîâïàäåíèÿ ñ÷åò÷èêà ñ ÌÀÒÑÍ (lim0 ?) òî: + { + /* ResetCS(ADC); //prepare ADC for sampling + SetDAC(DAC); + LPC_GPIO2->FIOSET |= 0x0000004; // turn on the LED + LPC_GPIO2->FIOSET |= 0x0000004; // turn on the LED + LPC_GPIO2->FIOSET |= 0x0000004; // turn on the LED + SetCS(ADC); //start ADC sampling + ResetDAC(DAC); //start DAC prepearing for writing + +*/ +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + + secPuls++; + tmpSec++; + mSec++; + + i1++; + if(i1>10000) + //if(CountV31>30) + { + i1=0; + /* + SendToBuffStr("\n\r"); + // if (Buff_ADC_1 [y] > 65535)SendToBuffStr(" 0 "); else SendToBuffStr(" 1 "); + sprintf (BuffTemp,"<%05d> <%05d> <%05d> <%05d> <%05d>", Temp_AMP>>5,Temp_ADC_2>>5,Temp_ADC_3>>5,Temp_ADC_4>>5,Temp_ADC_5>>5); + // sprintf (BuffTemp,"<%07d> <%07d> <%07d> <%07d> <%07d>", Spi.ADC1,Spi.ADC2,Spi.ADC3,Spi.ADC4,Spi.ADC5); + SendToBuffStr(BuffTemp); + */ + /* + WriteConByte (Main.T_Vib&0xff00); + WriteConByte (Main.T_Vib&0x00ff); + WriteConByte (Main.T_Vib); + */ + /* + + for (y = 0; y < 32; y++ ) + { + + WriteCon(BuffTemp); + } WriteCon("\n\r"); + + */ +/* +Main.T_Vib=((7680000*16/Main.Frq)*4096); + th= Main.T_Vib&0xff00; + tt= Main.T_Vib&0x00ff; + sprintf(BuffTemp,"<%07d >",( (Main.T_Vib&0xff00))); + SendToBuffStr(BuffTemp); + + sprintf(BuffTemp,"<%07d >",( ( Main.T_Vib&0x00ff))); + SendToBuffStr(BuffTemp); + /* + CuruAngleOld=CuruAngle;*/ + // Spi.ADC1=Spi.ADC1*0.000061; + + + + + /* + + sprintf(BuffTemp,"\n\r<%05d><%05d><%05d><%05d><%05d>",Spi.ADC1,Spi.ADC2,Spi.ADC3,Spi.ADC4,Spi.ADC5); + SendToBuffStr(BuffTemp); + + */ + + /* sprintf(BuffTemp,"<%d>",(FrecTemp)); + SendToBuffStr(BuffTemp); + for (y = 0; y < 32; y++ ) + { + sprintf(BuffTemp," <%07d>", (Buff_16PointD [y]-65535)); + SendToBuffStr(BuffTemp); + } */ + } + + + + + + + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + + + + LPC_GPIO2->FIOSET |= 0x0000004; // turn on the LED + + + Curr_Cnt_Vib = LPC_QEI->POS; // çàïèñàòü â ïåðåìåííóþ Curr_Cnt_Vib òåêóùåå ïîëîæåíèå Ýíêîäåðà. (òåêóùåå êîëè÷åñòâî èìïóëüñîâ) + Latch_Event(); //îïðåäåëåíèå çàùåëêè + + clc_Pulses(); // ñ÷åò÷èê èìïóëüñîâ. RATE_REPER_OR_REFMEANDR èëè RATE_VIBRO_1 + + + //ADC_Input(); // ïðîâåðêà ôëàãîâ çàïîëíåíèÿ áóôåðà è ÷åòåíèå Thermo1, Thermo2, HF_out â ìàñèâ Input.ArrayIn[n]. + //DAC_ADC_Exchange();// ïðîâåðêà ôëàãîâ çàïîëíåíèÿ áóôåðà è çïèñü â ÖÀÏû. + ServiceTime();//ñåêóíäíûé òàéìåð. + clc_ThermoSensors();//ðàñ÷åò ñðåäíåé òåìïåðàòóðû çà ñåêóíäó + clc_HFO(); //ðàñ÷åò çíà÷åíèÿ äëÿ ïåðåäà÷è â êîíòóð ÃÂ×(íà öàï). + clc_PLC(); + // clc_Dith_regulator(); + clc_OutFreq_regulator(); + Output.Str.WP_sin = clc_WP_sin(); + contrl_GLD(); + G_Photo_Exchange(); + // Output.Str.T_Vibro = paramV*48; + + + Line_1_Rcv(); + decode_CMD(); + transm_DAT(); + + +// data_Rdy &= ~RESET_PERIOD; + + +LPC_PWM1->IR = 0x0001; //e. clear interrupt flag + + + +LPC_GPIO2->FIOCLR |= 0x0000004; // turn off the LED +// WDTFeed(); + + +//SPI_Exchange(); + + } + + } while ( 1 ); // main infinie loop +} + +/****************************************************************************** +** End Of File +******************************************************************************/ +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/mathDSP.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/mathDSP.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,264 @@ +#include "mathDSP.h" +#include "CntrlGLD.h" +#include <math.h> + +BAND_PASS_TYPE BandPassType; + + +#define L_PLC 3 +#define L_DUP 3 +#define DIV_CONST 768 +#define DIV_CONST2 384 +#define BUF_SIZE 64 +#define HALFINT 16384 + + int highPls = 0; + int lowPls = 0; + int BufInMovAverPls [67]; + int BufInMovAverMns [67]; + int BufInMovAverPls_2 [67]; + int BufInMovAverMns_2 [67]; + int hMovAver [67]; + + int aPLC[L_PLC], bPLC[L_PLC], aDUP[L_DUP], bDUP[L_DUP]; + int aDUP_2[L_DUP] = {A0_HP, A1_HP, 0}, bDUP_2[L_DUP] = {0, B1_HP, 0}; + +unsigned int Vibro_Filter_Aperture; +unsigned int Vibro_2_CountIn; +/****************************************************************************** +** Function name: init_VibroReduce +** +** Descriptions: Prepare coefficiennts and delay +** line for vibro reduce filter +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void init_VibroReduce() +{ + unsigned int i; + __int64 coeff; +// ~22.9 ~17600 768 | 10000Hz = 10 KHz |*| ????? |/|768000| + Vibro_Filter_Aperture = Device_blk.Str.VB_N/DIV_CONST; //e. real expression is DEVICE_SAMPLE_RATE_HZ*Device_blk.Str.VB_N/7680000 +//8832 îïðåäåëÿåòñÿ âûøå 384 + i = L_mult(Vibro_Filter_Aperture,DIV_CONST2); //e. i äî áëèæàéøåãî öåëîãî.//óìíîæåíèå 2 16-òè ðàçðÿäíûõ çíàêîâûõ ÷èñåë è ïîëó÷åíèå 32-õ ðàçðÿäíîãî ÷èñëà + // ? + if ((Device_blk.Str.VB_N - i)>DIV_CONST2) Vibro_Filter_Aperture++; //ïðîâåðêà íà ïåðåïîëíåíèå L_mult() + + coeff = 0x7FFFFFFF/Vibro_Filter_Aperture;//íàñûùåíèå ïðè ïåðåïîëíåíèè + + for ( i=0; i < Vibro_Filter_Aperture; i++) /// íå ïîíÿòíûé öèêë çàïîëíÿþùèé òðè áóôåðà çàâåäåííûõ âûøå... + { + BufInMovAverPls[i] = 0; + BufInMovAverMns[i] = 0; + hMovAver[i]= coeff; + } + Vibro_2_CountIn = MULT_7680_12500/Vibro_Filter_Aperture; + Vibro_2_CountIn++; //êàêîéòî ñ÷åò÷èê +} + +/****************************************************************************** +** Function name: VibroReduce +** +** Descriptions: Routine for reduce of vibro +** +** parameters: +** Returned value: Filtered magnitude +** +******************************************************************************/ +int VibroReduce (int input) +{ + static unsigned kIn = 0; + unsigned s; + __int64 outMns = 0; + __int64 outPls = 0; + BufInMovAverPls[kIn] = input; + BufInMovAverMns[kIn] = -input; + for (s=0; s<Vibro_Filter_Aperture; s++) + { + outPls += (__int64)hMovAver[s]*(__int64)BufInMovAverPls[s]; + outMns += (__int64)hMovAver[s]*(__int64)BufInMovAverMns[s]; + } + highPls = (int)(outPls>>32); + lowPls = (int)outPls; + + BufInMovAverPls_2[kIn] = (int)(outPls-(outMns>>32)); + BufInMovAverMns_2[kIn] = -BufInMovAverPls_2[kIn]; + outPls = 0; + outMns = 0; + for (s=0; s<Vibro_Filter_Aperture; s++) + { + outPls += (__int64)hMovAver[s]*(__int64)BufInMovAverPls_2[s]; + outMns += (__int64)hMovAver[s]*(__int64)BufInMovAverMns_2[s]; + } + kIn++; + if (kIn>(Vibro_Filter_Aperture-1)) kIn = 0; + + + return (int)(outPls-(outMns>>32)); +} +/*#endif +int VibroReduce (int input) +{ + static unsigned k = 0; + static __int64 out = 0, buf[67]; + + out -= buf[k]; + buf[k] = (__int64)hMovAver[k] * (__int64)input; + out += buf[k]; + + if (k++ > (Vibro_Filter_Aperture-1)) k = 0; + +// if ((int)out >> 16) +// return (int)(out>>31)+1; +// else + return (int)(out>>31); +}*/ +/****************************************************************************** +** Function name: DUP_Filt +** +** Descriptions: Filter for dither frequency regulator +** +** parameters: +** Returned value: Filtered magnitude +** +******************************************************************************/ +int DUP_Filt (int input) +{ +static unsigned int kIn = 0; + int ind; + __int64 temp = 0; + unsigned int i; +static int BufInDUP_1 [L_DUP] = {0,0,0}; +static int BufInDUP_2 [L_DUP] = {0,0,0}; +//static __int64 BufOutDUP[L_DUP] = {0,0,0}; + + if (kIn>(L_DUP-1)) kIn = 0; + + BufInDUP_1[kIn] = input; + ind = kIn; + BufInDUP_2[kIn] = 0; + for (i=0; i<L_DUP; i++) + { + temp += aDUP[i]*BufInDUP_1[ind]; + temp += bDUP[i]*BufInDUP_2[ind]; + if ((--ind) < 0) ind = L_DUP-1; + } + BufInDUP_2[kIn] =(int)(temp>>14); //e.-----16----------- take into account that filter coefficients are divided on 2 + +//-----------------------------2 section (HF-filtration)---------------------------------- + /* BufOutDUP[kIn] = 0; + for (i=0; i<L_DUP; i++) + { + BufOutDUP[kIn] += (__int64)aDUP_2[i]*BufInDUP_2[ind] + (__int64)bDUP_2[i]*BufOutDUP[ind]; + if ((--ind) < 0) ind = L_DUP-1; + } + BufOutDUP[kIn] >>= 30; */ + + return (BufInDUP_2[kIn++]); +} + + + + +//-------------------------PLC phase detector---------------------------------- +int PLC_PhaseDetFilt (int input) +{ +static unsigned kIn = 0; + int ind; + __int64 temp = 0; + unsigned i; +static int BufInPLC_1 [L_PLC] = {0,0,0}; +static int BufInPLC_2 [L_PLC] = {0,0,0}; +static int BufOutPLC [L_PLC] = {0,0,0}; + + if (kIn>(L_PLC-1)) kIn = 0; + + BufInPLC_1[kIn] = input; + ind = kIn; + // BufInPLC_2[kIn] = 0; + + for (i=0; i<L_PLC; i++) + { + temp += aPLC[i]*BufInPLC_1[ind]; + temp += bPLC[i]*BufInPLC_2[ind]; + if ((--ind) < 0) ind = L_PLC-1; + } + BufInPLC_2[kIn] =(int)(temp>>14); +//-----------------------------2 section---------------------------------------- +// BufOutPLC[kIn] = 0; + temp = 0; + for (i=0; i<L_PLC; i++) + { + temp += aPLC[i]*BufInPLC_2[ind]; + temp += bPLC[i]*BufOutPLC[ind]; + if ((--ind) < 0) ind = L_PLC-1; + } + BufOutPLC[kIn] =(int)(temp>>14); + + return (BufOutPLC[kIn++]); +} +/****************************************************************************** +** Function name: init_BandPass +** +** Descriptions: Initialization of IIR filters for PLC and DUP signals +** +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void init_BandPass(double CenterFreq, double BandWidth, BAND_PASS_TYPE FiltType) +{ + double K, R, Cos_x_2, R_x_R; + + R = 1.0 - 3.0 * BandWidth; + R_x_R = R * R; + Cos_x_2 = cos(2.0 * PI * CenterFreq) * 2.0; + K = (1.0 - R * Cos_x_2 + R_x_R)/(2.0 - Cos_x_2); + switch (FiltType) + { + case PLC: + aPLC[0] = (int)((1.0 - K)*HALFINT); + aPLC[1] = (int)(((K - R) * Cos_x_2)*HALFINT); + aPLC[2] = (int)((R_x_R - K)*HALFINT); + bPLC[0] = 0; + bPLC[1] = (int)((R * Cos_x_2)*HALFINT); + bPLC[2] = (int)((- R_x_R)*HALFINT); + break; + case DUP: + aDUP[0] = (int)((1.0 - K)*HALFINT); + aDUP[1] = (int)(((K - R) * Cos_x_2)*HALFINT); + aDUP[2] = (int)((R_x_R - K)*HALFINT); + bDUP[0] = 0; + bDUP[1] = (int)((R * Cos_x_2)*HALFINT); + bDUP[2] = (int)((- R_x_R)*HALFINT); + break; + } +} +/****************************************************************************** +** Function name: HFO_MovAverFilt +** +** Descriptions: Moving average filter for ammplitude signal filtration +** +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +int HFO_MovAverFilt (int Input) +{ + static __int64 smooth_HF = 0; + static int buffer_HF[BUF_SIZE]; + static unsigned i_HF = 0; + + smooth_HF -= buffer_HF[i_HF]; + buffer_HF[i_HF] = Input; + smooth_HF += Input; + + i_HF++; + i_HF &= (BUF_SIZE-1); + + return (smooth_HF>>22); //shift on additional 6 bits for smoothing 2^6 = 64 +}
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/mathDSP.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/mathDSP.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,42 @@ +#include "dspfns.h" + + +typedef enum BAND_PASS_TYPE_{PLC, DUP} BAND_PASS_TYPE; + +extern BAND_PASS_TYPE BandPassType; +extern unsigned int Vibro_Filter_Aperture; + +#define PI 3.14159265 + + //e. constants for the filter in the CPLC regulator //r. êîíñòàíòû äëÿ ôèëüòðà â êîíòóðå ÑÐÏ +#define NUMB_OF_BIQUADS_PLC 2 +#define TAPS_PLC 5*NUMB_OF_BIQUADS_PLC +#define DELAY_LEN_PLC (2*NUMB_OF_BIQUADS_PLC+2) + + //e. constants for the filter in the APS regulator //r. êîíñòàíòû äëÿ ôèëüòðà â êîíòóðå ÄÓÏ +#define NUM_OF_BIQUADS_DUP 2 +#define TAPS_DUP 5*NUM_OF_BIQUADS_DUP +#define DELAY_LEN_DUP (2*NUM_OF_BIQUADS_DUP+2) + +#define X 0.98 //0.96 //0.86 +#define A0_HP ((1 + X)/2) * 0x40000000 +#define A1_HP (-(1 + X)/2) * 0x40000000 +#define B1_HP (X * 0x80000000)/2 + +#define MULT_7680_12500 26667 + +#define Saturation(Uin, UpSat, DownSat) if (Uin > UpSat) Uin = UpSat; \ + if (Uin < DownSat) Uin = DownSat; + +#define Cnt_Overload(Uin, UpSat, DwnSat) if (Uin > UpSat) Uin -= INT32_MAX; if (Uin < DwnSat) Uin += INT32_MAX; + +#define CPL_reset_calc(U0, Kgrad, Ti, T0) U0 + L_mult( Kgrad, (Ti - T0) ) + +int HFO_MovAverFilt (int ); + +int VibroReduce (int input); +void init_VibroReduce(void); +int PLC_PhaseDetFilt (int input); +int DUP_Filt (int input); +void init_BandPass(double CenterFreq, double BandWidth, BAND_PASS_TYPE ); +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/stdint.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/stdint.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,265 @@ +/* Copyright (C) ARM Ltd., 1999 */ +/* All rights reserved */ + +/* + * RCS $Revision: 137748 $ + * Checkin $Date: 2008-09-11 17:34:24 +0100 (Thu, 11 Sep 2008) $ + * Revising $Author: agrant $ + */ + +#ifndef __stdint_h +#define __stdint_h + + #ifndef __STDINT_DECLS + #define __STDINT_DECLS + + #undef __CLIBNS + + #ifdef __cplusplus + namespace std { + #define __CLIBNS std:: + extern "C" { + #else + #define __CLIBNS + #endif /* __cplusplus */ + + +/* + * 'signed' is redundant below, except for 'signed char' and if + * the typedef is used to declare a bitfield. + * '__int64' is used instead of 'long long' so that this header + * can be used in --strict mode. + */ + + /* 7.18.1.1 */ + + /* exact-width signed integer types */ +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef signed __int64 int64_t; + + /* exact-width unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned __int64 uint64_t; + + /* 7.18.1.2 */ + + /* smallest type of at least n bits */ + /* minimum-width signed integer types */ +typedef signed char int_least8_t; +typedef signed short int int_least16_t; +typedef signed int int_least32_t; +typedef signed __int64 int_least64_t; + + /* minimum-width unsigned integer types */ +typedef unsigned char uint_least8_t; +typedef unsigned short int uint_least16_t; +typedef unsigned int uint_least32_t; +typedef unsigned __int64 uint_least64_t; + + /* 7.18.1.3 */ + + /* fastest minimum-width signed integer types */ +typedef signed int int_fast8_t; +typedef signed int int_fast16_t; +typedef signed int int_fast32_t; +typedef signed __int64 int_fast64_t; + + /* fastest minimum-width unsigned integer types */ +typedef unsigned int uint_fast8_t; +typedef unsigned int uint_fast16_t; +typedef unsigned int uint_fast32_t; +typedef unsigned __int64 uint_fast64_t; + + /* 7.18.1.4 integer types capable of holding object pointers */ +typedef signed int intptr_t; +typedef unsigned int uintptr_t; + + /* 7.18.1.5 greatest-width integer types */ +typedef signed __int64 intmax_t; +typedef unsigned __int64 uintmax_t; + + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + + /* 7.18.2.1 */ + + /* minimum values of exact-width signed integer types */ +#define INT8_MIN -128 +#define INT16_MIN -32768 +#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */ +#define INT64_MIN __ESCAPE__(~0x7fffffffffffffffll) /* -9223372036854775808 is unsigned */ + + /* maximum values of exact-width signed integer types */ +#define INT8_MAX 127 +#define INT16_MAX 32767 +#define INT32_MAX 2147483647 +#define INT64_MAX __ESCAPE__(9223372036854775807ll) + + /* maximum values of exact-width unsigned integer types */ +#define UINT8_MAX 255 +#define UINT16_MAX 65535 +#define UINT32_MAX 4294967295u +#define UINT64_MAX __ESCAPE__(18446744073709551615ull) + + /* 7.18.2.2 */ + + /* minimum values of minimum-width signed integer types */ +#define INT_LEAST8_MIN -128 +#define INT_LEAST16_MIN -32768 +#define INT_LEAST32_MIN (~0x7fffffff) +#define INT_LEAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) + + /* maximum values of minimum-width signed integer types */ +#define INT_LEAST8_MAX 127 +#define INT_LEAST16_MAX 32767 +#define INT_LEAST32_MAX 2147483647 +#define INT_LEAST64_MAX __ESCAPE__(9223372036854775807ll) + + /* maximum values of minimum-width unsigned integer types */ +#define UINT_LEAST8_MAX 255 +#define UINT_LEAST16_MAX 65535 +#define UINT_LEAST32_MAX 4294967295u +#define UINT_LEAST64_MAX __ESCAPE__(18446744073709551615ull) + + /* 7.18.2.3 */ + + /* minimum values of fastest minimum-width signed integer types */ +#define INT_FAST8_MIN (~0x7fffffff) +#define INT_FAST16_MIN (~0x7fffffff) +#define INT_FAST32_MIN (~0x7fffffff) +#define INT_FAST64_MIN __ESCAPE__(~0x7fffffffffffffffll) + + /* maximum values of fastest minimum-width signed integer types */ +#define INT_FAST8_MAX 2147483647 +#define INT_FAST16_MAX 2147483647 +#define INT_FAST32_MAX 2147483647 +#define INT_FAST64_MAX __ESCAPE__(9223372036854775807ll) + + /* maximum values of fastest minimum-width unsigned integer types */ +#define UINT_FAST8_MAX 4294967295u +#define UINT_FAST16_MAX 4294967295u +#define UINT_FAST32_MAX 4294967295u +#define UINT_FAST64_MAX __ESCAPE__(18446744073709551615ull) + + /* 7.18.2.4 */ + + /* minimum value of pointer-holding signed integer type */ +#define INTPTR_MIN (~0x7fffffff) + + /* maximum value of pointer-holding signed integer type */ +#define INTPTR_MAX 2147483647 + + /* maximum value of pointer-holding unsigned integer type */ +#define UINTPTR_MAX 4294967295u + + /* 7.18.2.5 */ + + /* minimum value of greatest-width signed integer type */ +#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) + + /* maximum value of greatest-width signed integer type */ +#define INTMAX_MAX __ESCAPE__(9223372036854775807ll) + + /* maximum value of greatest-width unsigned integer type */ +#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) + + /* 7.18.3 */ + + /* limits of ptrdiff_t */ +#define PTRDIFF_MIN (~0x7fffffff) +#define PTRDIFF_MAX 2147483647 + + /* limits of sig_atomic_t */ +#define SIG_ATOMIC_MIN (~0x7fffffff) +#define SIG_ATOMIC_MAX 2147483647 + + /* limit of size_t */ +#define SIZE_MAX 4294967295u + + /* limits of wchar_t */ + /* NB we have to undef and redef because they're defined in both + * stdint.h and wchar.h */ +#undef WCHAR_MIN +#undef WCHAR_MAX + +#if defined(__WCHAR32) + #define WCHAR_MIN 0 + #define WCHAR_MAX 0xffffffffU +#else + #define WCHAR_MIN 0 + #define WCHAR_MAX 65535 +#endif + + /* limits of wint_t */ +#define WINT_MIN (~0x7fffffff) +#define WINT_MAX 2147483647 + +#endif /* __STDC_LIMIT_MACROS */ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + + /* 7.18.4.1 macros for minimum-width integer constants */ +#define INT8_C(x) (x) +#define INT16_C(x) (x) +#define INT32_C(x) (x) +#define INT64_C(x) __ESCAPE__(x ## ll) + +#define UINT8_C(x) (x ## u) +#define UINT16_C(x) (x ## u) +#define UINT32_C(x) (x ## u) +#define UINT64_C(x) __ESCAPE__(x ## ull) + + /* 7.18.4.2 macros for greatest-width integer constants */ +#define INTMAX_C(x) __ESCAPE__(x ## ll) +#define UINTMAX_C(x) __ESCAPE__(x ## ull) + +#endif /* __STDC_CONSTANT_MACROS */ + + #ifdef __cplusplus + } /* extern "C" */ + } /* namespace std */ + #endif /* __cplusplus */ + #endif /* __STDINT_DECLS */ + + #ifdef __cplusplus + #ifndef __STDINT_NO_EXPORTS + using ::std::int8_t; + using ::std::int16_t; + using ::std::int32_t; + using ::std::int64_t; + using ::std::uint8_t; + using ::std::uint16_t; + using ::std::uint32_t; + using ::std::uint64_t; + using ::std::int_least8_t; + using ::std::int_least16_t; + using ::std::int_least32_t; + using ::std::int_least64_t; + using ::std::uint_least8_t; + using ::std::uint_least16_t; + using ::std::uint_least32_t; + using ::std::uint_least64_t; + using ::std::int_fast8_t; + using ::std::int_fast16_t; + using ::std::int_fast32_t; + using ::std::int_fast64_t; + using ::std::uint_fast8_t; + using ::std::uint_fast16_t; + using ::std::uint_fast32_t; + using ::std::uint_fast64_t; + using ::std::intptr_t; + using ::std::uintptr_t; + using ::std::intmax_t; + using ::std::uintmax_t; + #endif + #endif /* __cplusplus */ + +#endif /* __stdint_h */ + +/* end of stdint.h */ + +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/system_LPC17xx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/system_LPC17xx.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,49 @@ +/****************************************************************************** + * @file: system_LPC17xx.h + * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC17xx Device Series + * @version: V1.01 + * @date: 22. Jul. 2009 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC17xx_H +#define __SYSTEM_LPC17xx_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +extern void SystemInit (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC17xx_H */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/uart.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/uart.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,65 @@ +/**************************************************************************** + * $Id:: uart.c 5751 2010-11-30 23:56:11Z usb00423 $ + * Project: NXP LPC17xx UART example + * + * Description: + * This file contains UART code example which include UART initialization, + * UART interrupt handler, and APIs for UART access. + * +****************************************************************************/ +#include "lpc17xx.h" +#include "uart.h" + +#define FOSC 12000000 /* Õñµ´Æ÷ƵÂÊ */ + +#define FCCLK (FOSC * 8) /* Ö÷ʱÖÓƵÂÊ<=100Mhz */ + /* FOSCµÄÕûÊý±¶ */ +#define FCCO (FCCLK * 3) /* PLLƵÂÊ(275Mhz~550Mhz) */ + /* ÓëFCCLKÏàͬ£¬»òÊÇÆäµÄżÊý±¶ */ +#define FPCLK (FCCLK / 4) /* ÍâÉèʱÖÓƵÂÊ,FCCLKµÄ1/2¡¢1/4*/ + /* »òÓëFCCLKÏàͬ */ +/***************************************************************************** +** Function name: UARTInit +** +** Descriptions: Initialize UART port, setup pin select, +** clock, parity, stop bits, FIFO, etc. +** +** parameters: portNum(0 or 1) and UART baudrate +** Returned value: true or false, return false only if the +** interrupt handler can't be installed to the +** VIC table +** +*****************************************************************************/ +void UART2_Init (void) +{ + uint16_t usFdiv; + /* UART2 */ + LPC_PINCON->PINSEL0 |= (1 << 20); /* Pin P0.10 used as TXD2 (Com2) */ + LPC_PINCON->PINSEL0 |= (1 << 22); /* Pin P0.11 used as RXD2 (Com2) */ + + LPC_SC->PCONP = LPC_SC->PCONP|(1<<24); /*´ò¿ªUART2µçÔ´¿ØÖÆλ */ + + LPC_UART2->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + usFdiv = (FPCLK / 16) / 115200; /* ÉèÖò¨ÌØÂÊ */ + LPC_UART2->DLM = usFdiv / 256; + LPC_UART2->DLL = usFdiv % 256; + LPC_UART2->LCR = 0x03; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART2->FCR = 0x06; +} + +/********************************************************************************************************* +** Function name: UART2_SendByte +** Descriptions: ´Ó´®¿Ú2·¢ËÍÊý¾Ý +** input parameters: data: ·¢Ë͵ÄÊý¾Ý +** output parameters: ÎÞ +** Returned value: ÎÞ +*********************************************************************************************************/ +int UART2_SendByte (int ucData) +{ + while (!(LPC_UART2->LSR & 0x20)); + return (LPC_UART2->THR = ucData); +} + +/****************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/uart.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/uart.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,88 @@ +/**************************************************************************** + * $Id:: uart.h 5751 2010-11-30 23:56:11Z usb00423 $ + * Project: NXP LPC17xx UART example + * + * Description: + * This file contains UART code header definition. + * + **************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. +****************************************************************************/ +#ifndef __UART_H +#define __UART_H + +#define SIMPLEUARTRX + +/* State-machine variable to control application functionality */ +enum state_machine { + UNKNOWN_COMMAND, + WRITE4SECTOR = 101, // actions with flash: erase + WAIT_ENTRANCE, // waiting for bootloader entrance + WAIT_FLASHACTION = 113, // waiting for an action with flash + READ_FLASH = 114, // actions with flash: read + WRITE_FLASH = 119 // actions with flash: write + +}; +#define IER_RBR 0x01 +#define IER_THRE 0x02 +#define IER_RLS 0x04 + +#define IIR_PEND 0x01 +#define IIR_RLS 0x03 +#define IIR_RDA 0x02 +#define IIR_CTI 0x06 +#define IIR_THRE 0x01 + +#define LSR_RDR 0x01 +#define LSR_OE 0x02 +#define LSR_PE 0x04 +#define LSR_FE 0x08 +#define LSR_BI 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define BUFSIZE 0x40 +#define FIFOs_En 0x00000001 +#define RX_FIFO_Reset 0x00000002 +#define TX_FIFO_Reset 0x00000004 +#define DMA_Mode_UART 0x00000008 +#define RX_TrigLvl_1 0x00000000 +#define RX_TrigLvl_4 0x00000040 +#define RX_TrigLvl_8 0x00000080 +#define RX_TrigLvl_14 0x000000C0 + +#define word_length_8 0x00000003 + +#define one_stop_bit 0x00000000 + +#define no_parity 0x00000000 + +#define back_trans_dis 0x00000000 + +#define DLAB_access 0x00000080 + +#define TRANS_SHIFT_BUF_EMPTY 0x00000040 +#define RecievBufNOTEmpty 0x00000001 +#define DIS_ALL_INT 0x00000000 +#define RBR_IntEnabl 0x00000001 + +void UART2_Init(void); + +int UART2_SendByte (int ucData); + + + +#endif /* end __UART_H */ +/***************************************************************************** +** End Of File +******************************************************************************/
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/uart_m.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/uart_m.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,850 @@ +/****************************************Copyright (c)**************************************************** +** http://www.PowerAVR.com +** http://www.PowerMCU.com +**--------------File Info--------------------------------------------------------------------------------- +** File name: uart.c +** Last modified Date: 2010-05-12 +** Last Version: V1.00 +** Descriptions: +** +**-------------------------------------------------------------------------------------------------------- +** Created by: PowerAVR +** Created date: 2010-05-10 +** Version: V1.00 +** Descriptions: ±àдʾÀý´úÂë +** +*-------------------------------------------------------------------------------------------------------- YJVTHF + +*********************************************************************************************************/ + +#include "lpc17xx.h" /* LPC17xx definitions */ +#include "uart_m.h" +//#include "global.h" + + +//#define FPCLK (100000000) //ñ pll +//#define FPCLK (12000000) //ñ pll +#define FOSC 12000000 /* Õñµ´Æ÷ƵÂÊ */ +#define FCCLK (FOSC * 8) /* Ö÷ʱÖÓƵÂÊ<=100Mhz */ + /* FOSCµÄÕûÊý±¶ */ +#define FCCO (FCCLK * 3) /* PLLƵÂÊ(275Mhz~550Mhz) */ + +//#define FPCLK (FCCLK / 4) //ñ pll + + +#define FPCLK (100000000 / 4) //ñ pll + +//#define FPCLK (25000000) //ñ pll + + + + +int UART0_BPS = 9600 ; /* ´®¿Ú0ͨÐŲ¨ÌØÂÊ */ +int UART1_BPS = 4800; /* ´®¿Ú0ͨÐŲ¨ÌØÂÊ */ +int UART2_BPS = 9600 ; /* ´®¿Ú0ͨÐŲ¨ÌØÂÊ */ +int UART3_BPS = 19200 ; /* ´®¿Ú0ͨÐŲ¨ÌØÂÊ */ + +#define UART_LCR_ODD 0x0b +#define UART_LCR_EVEN 0x1b + +int UART_LCR = UART_LCR_EVEN ; + +char InCon[1024]; +char OutCon[1024]; + +unsigned int ConInPnt = 0; +unsigned int ConInCur = 0; +unsigned int ConOutPnt = 0; +unsigned int ConOutCur = 0; + + +char InCon1[1024]; +char OutCon1[1024]; + +unsigned int ConInPnt1 = 0; +unsigned int ConInCur1 = 0; +unsigned int ConOutPnt1 = 0; +unsigned int ConOutCur1 = 0; + + +char InCon2[1024]; +char OutCon2[1024]; + +unsigned int ConInPnt2 = 0; +unsigned int ConInCur2 = 0; +unsigned int ConOutPnt2 = 0; +unsigned int ConOutCur2 = 0; + +char InCon3[1024]; +char OutCon3[1024]; + +unsigned int ConInPnt3 = 0; +unsigned int ConInCur3 = 0; +unsigned int ConOutPnt3 = 0; +unsigned int ConOutCur3 = 0; + + + +unsigned int InCon2M[16]; +unsigned int OutCon2M[16]; + +unsigned int ConInPnt2M = 0; +unsigned int ConInCur2M = 0; +unsigned int ConOutPnt2M = 0; +unsigned int ConOutCur2M = 0; + +unsigned int InCon3M[16]; +unsigned int OutCon3M[16]; + +unsigned int ConInPnt3M = 0; +unsigned int ConInCur3M = 0; +unsigned int ConOutPnt3M = 0; +unsigned int ConOutCur3M = 0; + + + + + +unsigned int OutBufConCount = 0; +unsigned int OutBufCon1Count = 0; +unsigned int OutBufCon2Count = 0; +unsigned int OutBufCon3Count = 0; + + + +/********************************************************************************************************* +** Function name: UART0_Init +** Descriptions: °´Ä¬ÈÏÖµ³õʼ»¯´®¿Ú0µÄÒý½ÅºÍͨѶ²ÎÊý¡£ÉèÖÃΪ8λÊý¾Ý룬1λֹͣ룬ÎÞÆæżУÑé +** input parameters: ÎÞ +** output parameters: ÎÞ +** Returned value: ÎÞ +*********************************************************************************************************/ +void UART0_Init (void) +{ + uint16_t usFdiv; + LPC_PINCON->PINSEL0 |= (1 << 4); /* Pin P0.2 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL0 |= (1 << 6); /* Pin P0.3 used as RXD0 (Com0) */ + LPC_UART0->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + + // LPC_UART0->FDR = 0x00000085; // cñì ïäô LPC17xx-User-Manual_0[1].05 íà ñòð 311 + //óìíîæèòåëü íà 8 äåëèòåëü íà 5 +// usFdiv = 4; + usFdiv = (FPCLK / 16) / UART0_BPS; /* ÉèÖò¨ÌØÂÊ */ + LPC_UART0->DLM = usFdiv / 256; + LPC_UART0->DLL = usFdiv % 256; + LPC_UART0->LCR = 0x03; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART0->FCR = 0x07; +} +void UART1_Init_temp (void) +{ + uint16_t usFdiv; + LPC_PINCON->PINSEL4 |= (2 << 0); /* Pin P2.0 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL4 |= (2 << 2); /* Pin P2.1 used as RXD0 (Com0) */ + LPC_UART1->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + usFdiv = (FPCLK / 16) / UART1_BPS; /* ÉèÖò¨ÌØÂÊ */ + LPC_UART1->DLM = usFdiv / 256; + LPC_UART1->DLL = usFdiv % 256; + LPC_UART1->LCR = 0x03; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART1->FCR = 0x07; +} + +void UART2_Init (void) +{ + uint16_t usFdiv; + LPC_PINCON->PINSEL0 |= (1 << 20); /* Pin P0.10 used as TXD2 (Com2) */ + LPC_PINCON->PINSEL0 |= (1 << 22); /* Pin P0.11 used as RXD2 (Com2) */ + LPC_SC->PCONP = LPC_SC->PCONP|(1<<24); /*´ò¿ªUART2µçÔ´¿ØÖÆλ */ + + LPC_UART2->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + usFdiv = (FPCLK / 16) / 9600; /* ÉèÖò¨ÌØÂÊ */ + LPC_UART2->DLM = usFdiv / 256; + LPC_UART2->DLL = usFdiv % 256; + LPC_UART2->LCR = 0x03; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART2->FCR = 0x07; +} + + +void UART3_Init (void) +{ + uint16_t usFdiv; + /* UART0 */ + LPC_PINCON->PINSEL1 |= (3 << 18); /* Pin P0.25 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL1 |= (3 << 20); /* Pin P0.26 used as RXD0 (Com0) */ + LPC_SC->PCONP = LPC_SC->PCONP|(1<<25); /*´ò¿ªUART2µçÔ´¿ØÖÆλ */ + + LPC_UART3->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + usFdiv = (FPCLK / 16) / UART3_BPS; /* ÉèÖò¨ÌØÂÊ */ + LPC_UART3->DLM = usFdiv / 256; + LPC_UART3->DLL = usFdiv % 256; + LPC_UART3->LCR = UART_LCR; + LPC_UART3->FCR = 0x07; +} + +void UART2_InitSet (unsigned int speed, unsigned int SetLsr) +{ + uint16_t usFdiv; + + LPC_PINCON->PINSEL0 |= (1 << 20); /* Pin P0.10 used as TXD2 (Com2) */ + LPC_PINCON->PINSEL0 |= (1 << 22); /* Pin P0.11 used as RXD2 (Com2) */ + + LPC_SC->PCONP = LPC_SC->PCONP|(1<<24); /*´ò¿ªUART2µçÔ´¿ØÖÆλ */ + + LPC_UART2->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + usFdiv = (FPCLK / 16) / speed; /* ÉèÖò¨ÌØÂÊ */ + LPC_UART2->DLM = usFdiv / 256; + LPC_UART2->DLL = usFdiv % 256; + LPC_UART2->LCR = SetLsr; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART2->FCR = 0x07; + +} + + +void UART3_InitSet (unsigned int speed, unsigned int SetLsr) +{ + uint16_t usFdiv; + /* UART0 */ + LPC_PINCON->PINSEL1 |= (3 << 18); /* Pin P0.25 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL1 |= (3 << 20); /* Pin P0.26 used as RXD0 (Com0) */ + + LPC_SC->PCONP = LPC_SC->PCONP|(1<<25); /*´ò¿ªUART2µçÔ´¿ØÖÆλ */ + LPC_UART3->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + usFdiv = (FPCLK / 16) / speed; /* ÉèÖò¨ÌØÂÊ */ + LPC_UART3->DLM = usFdiv / 256; + LPC_UART3->DLL = usFdiv % 256; + LPC_UART3->LCR = SetLsr; + LPC_UART3->FCR = 0x07; +} + +void UART_InitSet (unsigned int Num,unsigned int Speed, unsigned int SetLsr) +{ + uint16_t usFdiv; + +// usFdiv = ((FPCLK / 16) / Speed) +1; + usFdiv = ((FPCLK / 4) / Speed) + 1 ; + + if (Num == 0) + { + LPC_PINCON->PINSEL0 |= (1 << 4); /* Pin P0.2 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL0 |= (1 << 6); /* Pin P0.3 used as RXD0 (Com0) */ + LPC_UART0->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + // LPC_UART0->FDR = 0x00000085; // cñì ïäô LPC17xx-User-Manual_0[1].05 íà ñòð 311 + //óìíîæèòåëü íà 8 äåëèòåëü íà 5 + // usFdiv = 4; + LPC_UART0->DLM = usFdiv / 256; + LPC_UART0->DLL = usFdiv % 256; + LPC_UART0->LCR = SetLsr; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART0->FCR = 0x07; + } + if (Num == 1) + { + LPC_PINCON->PINSEL4 |= (2 << 0); /* Pin P2.0 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL4 |= (2 << 2); /* Pin P2.1 used as RXD0 (Com0) */ + + LPC_UART1->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + LPC_UART1->DLM = usFdiv / 256; + LPC_UART1->DLL = usFdiv % 256; + LPC_UART1->LCR = SetLsr; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART1->FCR = 0x07; + } + if (Num == 2) + { + LPC_PINCON->PINSEL0 |= (1 << 20); /* Pin P0.10 used as TXD2 (Com2) */ + LPC_PINCON->PINSEL0 |= (1 << 22); /* Pin P0.11 used as RXD2 (Com2) */ + LPC_SC->PCONP = LPC_SC->PCONP|(1<<24); /*´ò¿ªUART2µçÔ´¿ØÖÆλ */ + LPC_UART2->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + LPC_UART2->DLM = usFdiv / 256; + LPC_UART2->DLL = usFdiv % 256; + LPC_UART2->LCR = SetLsr; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART2->FCR = 0x07; + } + if (Num == 3) + { + LPC_PINCON->PINSEL1 |= (3 << 18); /* Pin P0.25 used as TXD0 (Com0) */ + LPC_PINCON->PINSEL1 |= (3 << 20); /* Pin P0.26 used as RXD0 (Com0) */ + LPC_SC->PCONP = LPC_SC->PCONP|(1<<25); /*´ò¿ªUART2µçÔ´¿ØÖÆλ */ + LPC_UART3->LCR = 0x83; /* ÔÊÐíÉèÖò¨ÌØÂÊ */ + LPC_UART3->DLM = usFdiv / 256; + LPC_UART3->DLL = usFdiv % 256; + LPC_UART3->LCR = SetLsr; /* Ëø¶¨²¨ÌØÂÊ */ + LPC_UART3->FCR = 0x07; + } +} + + + + + + + + + + + + + + + + + + + + + + + + +/********************************************************************************************************* +** Function name: UART0_SendByte +** Descriptions: ´Ó´®¿Ú0·¢ËÍÊý¾Ý +** input parameters: data: ·¢Ë͵ÄÊý¾Ý +** output parameters: ÎÞ +** Returned value: ÎÞ +*********************************************************************************************************/ +int UART0_SendByte (int ucData) +{ + while (!(LPC_UART0->LSR & 0x20)); + return (LPC_UART0->THR = ucData); + +} + + + + + + +/*---------------------------------------------------------------------------- + Read character from Serial Port (blocking read) + *----------------------------------------------------------------------------*/ +int UART0_GetChar (void) +{ + while (!(LPC_UART0->LSR & 0x01)); + return (LPC_UART0->RBR); +} +/*---------------------------------------------------------------------------- + Read character from Serial Port (blocking read) + *----------------------------------------------------------------------------*/ +int UART1_GetChar (void) +{ + while (!(LPC_UART1->LSR & 0x01)); + return (LPC_UART1->RBR); +} + +/*---------------------------------------------------------------------------- + Read character from Serial Port (blocking read) + *----------------------------------------------------------------------------*/ +int UART2_GetChar (void) +{ + while (!(LPC_UART2->LSR & 0x01)); + return (LPC_UART2->RBR); +} +/*---------------------------------------------------------------------------- + Read character from Serial Port (blocking read) + *----------------------------------------------------------------------------*/ +int UART3_GetChar (void) +{ + while (!(LPC_UART3->LSR & 0x01)); + return (LPC_UART3->RBR); +} + +int UART0_Chek (void) +{ + if (LPC_UART0->LSR & 0x01) return 1; else return 0; +} + +int UART1_Chek (void) +{ + if (LPC_UART1->LSR & 0x01)return 1; else return 0; +} + + +int UART2_Chek (void) +{ + + if (LPC_UART2->LSR & 0x01)return 1; else return 0; +} + +int UART3_Chek (void) +{ + if (LPC_UART3->LSR & 0x01)return 1; else return 0; + +} + + + + + + +void UART0_SendString (char *s) +{ + while (*s != 0) + { + UART0_SendByte(*s++); + } +} + + + + + +int UART2_SendByte (int ucData) +{ + while (!(LPC_UART2->LSR & 0x20)); + return (LPC_UART2->THR = ucData); +} + + + +void UART0_SendChar(uint16_t disp) +{ + uint16_t dispbuf[4]; + uint8_t i; + + dispbuf[3] = disp%10 + '0'; + dispbuf[2] = disp/10%10 + '0'; + dispbuf[1] = disp/10/10%10 + '0'; + dispbuf[0] = disp/10/10/10%10 + '0'; + for(i=0;i<4;i++) + UART0_SendByte(dispbuf[i]); +} + + + +void Concol (void ) +{ + if (OutBufConCount == 0) + { + + if (ConOutPnt != ConOutCur) + if (LPC_UART0->LSR & 0x20) + { + ConOutCur++; + ConOutCur = ConOutCur & 0x3ff; + SetDeUART0 (); + LPC_UART0->THR = OutCon[ConOutCur]; + } + } + if (LPC_UART0->LSR & 0x01) + { + ConInCur++; + ConInCur = ConInCur & 0x3ff; + InCon[ConInCur] = (LPC_UART0->RBR); + } + + if (!(LPC_UART0->LSR & 0x40)) SetDeUART0 (); else ClrDeUART0() ; //óïðàâëåíèå 485 + +} + + +void Concol1 (void ) +{ + if (OutBufCon1Count == 0) + { + if (ConOutPnt1 != ConOutCur1) + if (LPC_UART1->LSR & 0x20) + { + ConOutCur1++; + ConOutCur1 = ConOutCur1 & 0x3ff; + LPC_UART1->THR = OutCon1[ConOutCur1]; + } + } + if (LPC_UART1->LSR & 0x01) + { + ConInCur1++; + ConInCur1 = ConInCur1 & 0x3ff; + InCon1[ConInCur1] = (LPC_UART1->RBR); + } + + //if (!(LPC_UART1->LSR & 0x40)) SetDeUART1 (); else ClrDeUART1() ; //óïðàâëåíèå 485 +} + +void Concol1Fast (void ) +{ + if (OutBufCon1Count == 0) + { + while((ConOutPnt1 != ConOutCur1) && (LPC_UART1->LSR & 0x20)) + { + ConOutCur1++; + ConOutCur1 = ConOutCur1 & 0x3ff; + SetDeUART1 (); + LPC_UART1->THR = OutCon1[ConOutCur1]; + } + } + while (LPC_UART1->LSR & 0x01) + { + ConInCur1++; + ConInCur1 = ConInCur1 & 0x3ff; + InCon1[ConInCur1] = (LPC_UART1->RBR); + } + if (!(LPC_UART1->LSR & 0x40)) SetDeUART1 (); else ClrDeUART1() ; //óïðàâëåíèå 485 +} + + + + +void Concol2 (void ) +{ + if (OutBufCon2Count == 0) + { + if (ConOutPnt2 != ConOutCur2) + if (LPC_UART2->LSR & 0x20) + { + ConOutCur2++; + ConOutCur2 = ConOutCur2 & 0x3ff; + SetDeUART2 (); + LPC_UART2->THR = OutCon2[ConOutCur2]; + } + } + if (LPC_UART2->LSR & 0x01) + { + ConInCur2++; + ConInCur2 = ConInCur2 & 0x3ff; + InCon2[ConInCur2] = (LPC_UART2->RBR); + } + if (!(LPC_UART2->LSR & 0x40)) SetDeUART2 (); else ClrDeUART2() ; //óïðàâëåíèå 485 +} + + + + + +void Concol3 (void ) +{ + if (OutBufCon3Count == 0) + { + if (ConOutPnt3 != ConOutCur3) + if (LPC_UART3->LSR & 0x20) + { + ConOutCur3++; + ConOutCur3 = ConOutCur3 & 0x3ff; + SetDeUART3 (); + LPC_UART3->THR = OutCon3[ConOutCur3]; + } + } + if (LPC_UART3->LSR & 0x01) + { + ConInCur3++; + ConInCur3 = ConInCur3 & 0x3ff; + InCon3[ConInCur3] = (LPC_UART3->RBR); + } + + if (!(LPC_UART3->LSR & 0x40)) SetDeUART3 (); else ClrDeUART3() ; //óïðàâëåíèå 485 +} + + + +void Concol2M (void ) +{ + if (OutBufCon2Count == 0) + { + if (ConOutPnt2M != ConOutCur2M) + if (LPC_UART2->LSR & 0x20) + { + ConOutCur2++; + ConOutCur2 = ConOutCur2 & 0x3ff; + SetDeUART2 (); + LPC_UART2->THR = OutCon2[ConOutCur2]; + } + } + if (LPC_UART2->LSR & 0x01) + { + ConInCur2++; + ConInCur2 = ConInCur2 & 0x3ff; + InCon2[ConInCur2] = (LPC_UART2->RBR); + } + if (!(LPC_UART2->LSR & 0x40)) SetDeUART2 (); else ClrDeUART2() ; //óïðàâëåíèå 485 +} + + + + + + +void WriteCon (char *s) +{ + OutBufConCount = 0; + while (*s != 0) + { + ConOutPnt++; + ConOutPnt = ConOutPnt & 0x3ff; + OutCon[ConOutPnt] = (*s++); + } +} + +void WriteCon1 (char *s) +{ + OutBufCon1Count = 0; + while (*s != 0) + { + ConOutPnt1++; + ConOutPnt1 = ConOutPnt1 & 0x3ff; + OutCon1[ConOutPnt1] = (*s++); + } +} + +void WriteConN (char *s, unsigned int N) +{ + OutBufConCount = 0; + while (N != 0) + { + N--; + ConOutPnt++; + ConOutPnt = ConOutPnt & 0x3ff; + OutCon[ConOutPnt] = (*s++); + } +} + + +void WriteCon2 (char *s) +{ + OutBufCon2Count = 0; + while (*s != 0) + { + ConOutPnt2++; + ConOutPnt2 = ConOutPnt2 & 0x3ff; + OutCon2[ConOutPnt2] = (*s++); + } +} +void WriteCon3 (char *s) +{ + OutBufCon3Count = 0; + while (*s != 0) + { + ConOutPnt3++; + ConOutPnt3 = ConOutPnt3 & 0x3ff; + OutCon3[ConOutPnt3] = (*s++); + } +} + + + + +void WriteConF (char *s, unsigned int Num) +{ + if (Num == 0) WriteCon(s); + if (Num == 1) WriteCon1(s); + if (Num == 2) WriteCon2(s); + if (Num == 2) WriteCon3(s); + +} + + + + +void WriteConByte (unsigned int In) +{ + ConOutPnt++; + ConOutPnt = ConOutPnt & 0x3ff; + OutCon[ConOutPnt] = In; +} + +void WriteCon1Byte (unsigned int In) +{ + ConOutPnt1++; + ConOutPnt1 = ConOutPnt1 & 0x3ff; + OutCon1[ConOutPnt1] = In; +} + + +void WriteCon2Byte (unsigned int temp) +{ + ConOutPnt2++; + ConOutPnt2 = ConOutPnt2 & 0x3ff; + OutCon2[ConOutPnt2] = temp; +} + +void WriteCon3Byte (unsigned int temp) +{ + ConOutPnt3++; + ConOutPnt3 = ConOutPnt3 & 0x3ff; + OutCon3[ConOutPnt3] = temp; +} + + + + + +void WriteConByteF (unsigned int In,unsigned int Num ) +{ + if (Num == 0) WriteConByte(In); + if (Num == 1) WriteCon1Byte(In); + if (Num == 2) WriteCon2Byte(In); + if (Num == 3) WriteCon3Byte(In); + +} + + + + + + + + + +int ReadCon (char *s) +{ + int i = 0; + while (ConInPnt != ConInCur) + { + i++; + ConInPnt++; + ConInPnt = ConInPnt & 0x3ff; + (*s++) = InCon[ConInPnt] ; + } + (*s++) = 0; + return i; +} + +int ReadCon1 (char *s) +{ + int i = 0; + while (ConInPnt1 != ConInCur1) + { + i++; + ConInPnt1++; + ConInPnt1 = ConInPnt1 & 0x3ff; + (*s++) = InCon1[ConInPnt1] ; + } + (*s++) = 0; + return i; +} + +int ReadCon2 (char *s) +{ + int i = 0; + while (ConInPnt2 != ConInCur2) + { + i++; + ConInPnt2++; + ConInPnt2 = ConInPnt2 & 0x3ff; + (*s++) = InCon2[ConInPnt2] ; + } + (*s++) = 0; + return i; + +} + + +int ReadCon3 (char *s) +{ + int i = 0; + while (ConInPnt3 != ConInCur3) + { + i++; + ConInPnt3++; + ConInPnt3 = ConInPnt3 & 0x3ff; + (*s++) = InCon3[ConInPnt3] ; + } + (*s++) = 0; + return i; + +} + + + + + +int ReadChekCon (char *s) +{ + int i = 0; + int ConInPntTemp = ConInPnt; + while (ConInPntTemp != ConInCur) + { + i++; + ConInPntTemp++; + ConInPntTemp = ConInPntTemp & 0x3ff; + (*s++) = InCon[ConInPntTemp] ; + } + (*s++) = 0; + return i; +} + +int ReadChekCon1 (char *s) +{ + int i = 0; + int ConInPntTemp = ConInPnt1; + while (ConInPntTemp != ConInCur1) + { + i++; + ConInPntTemp++; + ConInPntTemp = ConInPntTemp & 0x3ff; + (*s++) = InCon1[ConInPntTemp] ; + } + (*s++) = 0; + return i; +} + + + + +int ReadChekCon2 (char *s) +{ + int i = 0; + int ConInPntTemp = ConInPnt2; + while (ConInPntTemp != ConInCur2) + { + i++; + ConInPntTemp++; + ConInPntTemp = ConInPntTemp & 0x3ff; + (*s++) = InCon2[ConInPntTemp] ; + } + (*s++) = 0; + return i; +} + + +int ReadChekCon3 (char *s) +{ + int i = 0; + int ConInPntTemp = ConInPnt3; + while (ConInPntTemp != ConInCur3) + { + i++; + ConInPntTemp++; + ConInPntTemp = ConInPntTemp & 0x3ff; + (*s++) = InCon3[ConInPntTemp] ; + } + (*s++) = 0; + return i; +} + + + + + + +int ChekInCon ( void ) {if (ConInPnt != ConInCur) return 1; else return 0;} +int ChekInCon1 ( void ) {if (ConInPnt1 != ConInCur1) return 1; else return 0;} +int ChekInCon2 ( void ) {if (ConInPnt2 != ConInCur2) return 1; else return 0;} +int ChekInCon3 ( void ) {if (ConInPnt3 != ConInCur3) return 1; else return 0;} + +int ChekOutCon ( void ) {if (!(LPC_UART0->LSR & 0x40)) return 1; else return 0;} +int ChekOutCon1 ( void ) {if (!(LPC_UART1->LSR & 0x40)) return 1; else return 0;} +int ChekOutCon2 ( void ) {if (!(LPC_UART2->LSR & 0x40)) return 1; else return 0;} +int ChekOutCon3 ( void ) {if (!(LPC_UART3->LSR & 0x40)) return 1; else return 0;} + + + + +void Delay(int t) +{ +} + + +void SetDeUART0 (void) {if ((PortEUART0 & (PinEUART0)) == 0) {PortEUART0 |= (PinEUART0); Delay(10);} } +void ClrDeUART0 (void) {if ((PortEUART0 & (PinEUART0))) { Delay(10); PortEUART0 &= (~(PinEUART0));}} + +void SetDeUART1 (void) {if ((PortEUART1 & (PinEUART1)) == 0) {PortEUART1 |= (PinEUART1); Delay(10);} } +void ClrDeUART1 (void) {if ((PortEUART1 & (PinEUART1))) { Delay(10); PortEUART1 &= (~(PinEUART1));}} + + + +void SetDeUART2 (void) {if ((PortEUART2 & (PinEUART2)) == 0) {PortEUART2 |= (PinEUART2); Delay(10);}} +void ClrDeUART2 (void) {if ((PortEUART2 & (PinEUART2))) {Delay(10); PortEUART2 &= (~(PinEUART2));}} + + +void SetDeUART3 (void) {if ((PortEUART3 & (PinEUART3)) == 0) {PortEUART3 |= (PinEUART3); Delay(10);}} +void ClrDeUART3 (void) {if ((PortEUART3 & (PinEUART3))) {Delay(10);PortEUART3 &= (~(PinEUART3));}} + + + +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/uart_m.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/uart_m.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,122 @@ +#ifndef __UART_H +#define __UART_H + +#define PortEUART0 LPC_GPIO4->FIOPIN +#define PortDirEUART0 LPC_GPIO4->FIODIR +#define PinEUART0 1UL << 29 + +#define PortEUART1 LPC_GPIO2->FIOPIN +#define PortDirEUART1 LPC_GPIO2->FIODIR +#define PinEUART1 1UL << 2 + + +#define PortEUART2 LPC_GPIO2->FIOPIN +#define PortDirEUART2 LPC_GPIO2->FIODIR +#define PinEUART2 1UL << 13 + +#define PortEUART3 LPC_GPIO0->FIOPIN +#define PortDirEUART3 LPC_GPIO0->FIODIR +#define PinEUART3 1UL << 24 + + + + + + + + + +void UART0_Init (void); +void UART1_Init_temp (void); +void UART2_Init (void); +void UART3_Init (void); + +void UART2_InitSet (unsigned int speed, unsigned int SetLsr); +void UART3_InitSet (unsigned int speed, unsigned int SetLsr); +void UART_InitSet (unsigned int Num,unsigned int Speed, unsigned int SetLsr); + + + +int UART0_SendByte (int ucData); + +int UART0_GetChar (void); +int UART1_GetChar (void); +int UART2_GetChar (void); +int UART3_GetChar (void); + + +int UART0_Chek (void); +int UART1_Chek (void); +int UART2_Chek (void); +int UART3_Chek (void); + +void UART0_SendString (char *s); +void UART2_SendString (char *s); + + +int UART2_SendByte (int ucData); +int UART2_SendByte_i (int ucData); +int UART2_GetChar (void); +int UART2_Chek (void); + +void Concol ( void); +void Concol1 ( void); +void Concol2 ( void); +void Concol3 ( void); + +void WriteCon (char *s); +void WriteCon1 (char *s); +void WriteCon2 (char *s); +void WriteConF (char *s, unsigned int Num); + +void WriteConN (char *s, unsigned int N); + +void WriteConByte (unsigned int In) ; +void WriteCon2Byte (unsigned int In) ; +void WriteCon3Byte (unsigned int In) ; + + +void WriteConByteF (unsigned int In,unsigned int Num ); + + +int ReadCon (char *s); +int ReadCon1 (char *s); +int ReadCon2 (char *s); +int ReadCon3 (char *s); + +int ReadChekCon (char *s); +int ReadChekCon2 (char *s); +int ReadChekCon3 (char *s); + +int ChekInCon ( void); +int ChekInCon1 ( void); +int ChekInCon2 ( void); +int ChekInCon3 ( void); + +int ChekOutCon ( void); +int ChekOutCon1 ( void); +int ChekOutCon2 ( void); +int ChekOutCon3 ( void); + + + +void SetDeUART0 (void); +void ClrDeUART0 (void); +void SetDeUART1 (void); +void ClrDeUART1 (void); +void SetDeUART2 (void); +void ClrDeUART2 (void); +void SetDeUART3 (void); +void ClrDeUART3 (void); + + + + +extern unsigned int OutBufConCount ; +extern unsigned int OutBufCon1Count; +extern unsigned int OutBufCon2Count; +extern unsigned int OutBufCon3Count; + + + +#endif
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/vibro.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/vibro.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,221 @@ +#include "vibro.h" +#include "stdlib.h" +#include "lpc17xx.h" +#include "ctime" +#include "InputOutput.h" +#include "Parameters.h" +#include "CntrlGLD.h" +#include "CyclesSync.h" +#include "SIP.h" +//extern OUTPUT Output; +#include "QEI.h" +#include "Global.h" +#include "MTimer.h" + +struct MAIN Main; + + +volatile int V1 = 0 ; +volatile int Temp = 0 ; +volatile unsigned int Flag=0; + +unsigned int FrecTemp=0; +///////////////////////////////////////////////////////////////////////////// +/////////////////////////èíèöèàëèçàöèÿ âèáðîïðèâîäà////////////////////////// +///////////////////////////////////////////////////////////////////////////// + unsigned int init_Vibro () + { + Main.FrqRate=40; + Main.FrqMin=380; + Main.FrqHZ=449; + Main.Frq = Main.FrqHZ<<16; + + Main.AmpPer=20; + Main.AmpPerDel=10; + Main.Amp = 10*65535; + Main.AmpL = 20*650; +/* + Vib.AmpH=50*650; + // Vib.AmpT=600; + // Output.Str.T_Vibro=40; + //LPC_GPIO0->FIOSET |= (1<<5); +*/ + return 0; + } + + +void VibroOut(void) +{ + + + if(CountV31>=16) + { + if((Time_vibro>Main.AmpN1) && (Time_vibro<Main.AmpN2)) {ClrV2 /*LoopOn*/} + else{ SetV2 } + } + else + { + if((Time_vibro>Main.AmpN1)&&(Time_vibro<Main.AmpN2)) {ClrV1 /*LoopOff*/} + else{ SetV1 } + } + + + +} + +void CalcAmpN(void) +{ + static int PeriodCount = 0,Tnoise; + + + + unsigned int Nmax=0; + + + if(PeriodCount>= Tnoise)//åñëè êîëè÷åñòâî çàõîäîâ â ïðåðûâàíèå áîëüøå ëèáî ðàâíî ÷àñòîòå îøóìëåíèÿ. + { + if (Flag==0)//ñåé÷àñ ìàëàÿ àìïëèòóäà? + { + + if(Main.AmpPer>90){Main.AmpPer=90;} + Nmax =(unsigned int)((100000/(Main.Frq>>16))-1); + Main.AmpN1=(unsigned int)((Nmax*(100-Main.AmpPer))/400); + Main.AmpN2=(unsigned int)((Nmax/2)-Main.AmpN1); + Flag=1; + + } + + else + { + if((Main.AmpPer+Main.AmpPerDel)>90){Main.AmpPer=90-Main.AmpPerDel;} + + Nmax =(unsigned int)((100000/(Main.Frq>>16))-1); + Main.AmpN1=(unsigned int)((Nmax*(100-Main.AmpPer+Main.AmpPerDel))/400); + Main.AmpN2=(unsigned int)((Nmax/2)-Main.AmpN1); + Flag=0; + } + Main.AmpMin =10; + Main.AmpTD =30; + //Tnoise=55; + srand(Global_Time); + Main.AmpT = (rand() % Main.AmpTD+Main.AmpMin);// ÎØÓÌËÅÍÈÅ amp + Tnoise=Main.AmpT; + //èçìåíåíèå ôëàãà ïðåäèäóùåé àìïëèòóäû + PeriodCount=0; + } + else{PeriodCount++;} + + + +} + +////////////////////////////////////////////////////////////////////////////// +/////////////////////////ôóíêöèÿ ðàáîòû âèáðîïðèâîäà////////////////////////// +////////////////////////////////////////////////////////////////////////////// +void cheng(void) +{ + static int TempFaza, CountFaza; + + + //Noise(); + + //Vib.Frq = ((unsigned int) ((7680000*16/Output.Str.T_Vibro)))*16*16*16; +/* +// CountV++; +// CountV &= 0x1f; +*/ + if (Buff_Restored_sin [CountV255] > MaxAmp) + { + MaxAmp=Buff_Restored_sin [CountV255]; + } + + + + + + switch(CountV31) + { + case 0: + CalcAmpN(); + //Vib.Frq = ((unsigned int) ((7680000*16/Output.Str.T_Vibro)))*16*16*16; + LPC_TIM1->MR0 =(unsigned int)(100000000/(Main.Frq>>11)); + Output.Str.T_Vibro=(unsigned int)((7680000*16/Main.Frq)*4096); + VibroPush(); + // LoopOn + // LPC_TIM1->MR0 =(unsigned int)(204800000000/Vib.Frq); + Time_vibro=0; + break; + case 10: + +// if (MaxAmp>(65535+400)) +// { +// Vib.Amp-=1000;// +// } +// else +// { +// Vib.Amp+=1000; +// } + + + + + Main.Amp -= (MaxAmp - 65536 - 300)*4; // ðàñ÷åò àìïëèòóäâ ñ ó÷åòîì ðàçíèöè + /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + if(Main.Amp>2500000){Main.Amp=1200000;}// âðåìåííîå îãðàíè÷åíèå ðîñòà àìïëèòóäû â ñëó÷àå íåïîäîæåííîãî ãèðîñêîïà////////// + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + + Main.AmpPer = Main.Amp>>16; + MaxAmp=0; + FrecTemp=Main.AmpPer;//äëÿ âûâîäà â òåðìèíàë + break; + case 16: + VibroPull(); + //SetV2 + // LoopOff + Time_vibro=0; + + + + + + +// ðàñ÷åò Ôàçû ñ ó÷åòîð ðàçíèöè + TempFaza = -4; + for (CountFaza = 0; CountFaza < 8; CountFaza++ ) + { + if (Buff_Restored_sin [(CountV255- 12 + CountFaza) & 0xff] > 65535) TempFaza++; + } // ðàñ÷åò Ôàçû ñ ó÷åòîð ðàçíèöè + Main.Frq -=TempFaza*1000; + + + + +// if (Buff_Restored_sin [(CountVf-8) & 0xff] > 65535) +// { +// Vib.Frq=Vib.Frq-10000; +// } + +// else +// { +// Vib.Frq=Vib.Frq+1000; +// } + break; + } + + + + + /* + if((CountV & 0x0f) == V1) + { + ClrV1 + ClrV2 + }*/ +} \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/App/vibro.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/App/vibro.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,72 @@ +#ifndef VIBRO_H +#define VIBRO_H + +/* +#define SetV1 LPC_GPIO1->FIOSET=(1<<25); +#define ClrV1 LPC_GPIO1->FIOCLR = (1<<25); +#define SetV2 LPC_GPIO1->FIOSET = (1<<28); +#define ClrV2 LPC_GPIO1->FIOCLR = (1<<28); +*/ +#define ClrV1 LPC_GPIO1->FIOSET=(1<<25); +#define SetV1 LPC_GPIO1->FIOCLR = (1<<25); + +#define ClrV2 LPC_GPIO1->FIOSET = (1<<28); +#define SetV2 LPC_GPIO1->FIOCLR = (1<<28); + +#define LoopOn LPC_GPIO1->FIOSET = (1<<30); +#define LoopOff LPC_GPIO1->FIOCLR = (1<<30); +#define StartV1 0 +#define StartV2 15 +#define TIME_INTERVAL (7812) + + + struct MAIN { + + unsigned int RgConA; + unsigned int RgConB; + + + unsigned int Frq; // Íåïîñðåäñòâåííîå çíà÷åíèå ÷àñòîòû äëÿ òàéìåðà. + unsigned int FrqHZ; // ×àñòîòà â Ãö. + unsigned int FrqRate; // Ðàçáðîñ ÷àñòîò ïðè îøóìëåíèè. + unsigned int FrqMin; // Ìèíèìàëüíîå çíà÷åíèå îøóìëåííîé ÷àñòîòû. + unsigned int FrqOld; // Çíà÷åíèå ÷àñòîòû çà ïðîøëûé òàêò. + + unsigned int Amp; + unsigned int AmpL; + unsigned int AmpT; + unsigned int AmpPer; + unsigned int AmpPerDel;//0-100% + unsigned int AmpN1; + unsigned int AmpN2; + unsigned int AmpMin; + unsigned int AmpTD; + + unsigned int CMD_In; + unsigned int SOC_Out; + unsigned int My_Addres; + unsigned int GLD_Serial; + unsigned int CRC; + unsigned int Firmware_Version; + unsigned int RsErrLine; + + unsigned int Cnt_Pls; + unsigned int Cnt_Mns; + unsigned int Cnt_Dif; + unsigned int T_Vib; + unsigned int F_ras; +}; +extern struct MAIN Main; + +extern unsigned int init_Vibro (); +extern void cheng(void); +extern void Noise(void); +extern void VibroOut(void); + +extern int Pulse_midl ; +extern struct VIBRO Vib; +extern int PulseHalf; +extern int CuruAngle; +extern unsigned int FrecTemp; +#endif +
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/CoreSupport/core_cm3.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/CoreSupport/core_cm3.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include <stdint.h> + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/CoreSupport/core_cm3.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/CoreSupport/core_cm3.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include <stdint.h> /* Include standard types */ + +#if defined (__ICCARM__) + #include <intrinsics.h> /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/LPC13xx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/LPC13xx.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,493 @@ +/**************************************************************************//** + * @file LPC13xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC13xx_H__ +#define __LPC13xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC13xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + WAKEUP13_IRQn = 13, + WAKEUP14_IRQn = 14, + WAKEUP15_IRQn = 15, + WAKEUP16_IRQn = 16, + WAKEUP17_IRQn = 17, + WAKEUP18_IRQn = 18, + WAKEUP19_IRQn = 19, + WAKEUP20_IRQn = 20, + WAKEUP21_IRQn = 21, + WAKEUP22_IRQn = 22, + WAKEUP23_IRQn = 23, + WAKEUP24_IRQn = 24, + WAKEUP25_IRQn = 25, + WAKEUP26_IRQn = 26, + WAKEUP27_IRQn = 27, + WAKEUP28_IRQn = 28, + WAKEUP29_IRQn = 29, + WAKEUP30_IRQn = 30, + WAKEUP31_IRQn = 31, + WAKEUP32_IRQn = 32, + WAKEUP33_IRQn = 33, + WAKEUP34_IRQn = 34, + WAKEUP35_IRQn = 35, + WAKEUP36_IRQn = 36, + WAKEUP37_IRQn = 37, + WAKEUP38_IRQn = 38, + WAKEUP39_IRQn = 39, + I2C_IRQn = 40, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ + SSP_IRQn = 45, /*!< SSP Interrupt */ + UART_IRQn = 46, /*!< UART Interrupt */ + USB_IRQn = 47, /*!< USB Regular Interrupt */ + USB_FIQn = 48, /*!< USB Fast Interrupt */ + ADC_IRQn = 49, /*!< A/D Converter Interrupt */ + WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ + EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC13xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ + __IO uint32_t PRESETCTRL; + __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ + __IO uint32_t SYSPLLSTAT; + __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ + __IO uint32_t USBPLLSTAT; + uint32_t RESERVED0[2]; + + __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ + __IO uint32_t WDTOSCCTRL; + __IO uint32_t IRCCTRL; + uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ + __IO uint32_t SYSPLLCLKUEN; + __IO uint32_t USBPLLCLKSEL; + __IO uint32_t USBPLLCLKUEN; + uint32_t RESERVED3[8]; + + __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ + __IO uint32_t MAINCLKUEN; + __IO uint32_t SYSAHBCLKDIV; + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ + uint32_t RESERVED5[4]; + __IO uint32_t SSPCLKDIV; + __IO uint32_t UARTCLKDIV; + uint32_t RESERVED6[4]; + __IO uint32_t TRACECLKDIV; + + __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ + uint32_t RESERVED7[3]; + + __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ + __IO uint32_t USBCLKUEN; + __IO uint32_t USBCLKDIV; + uint32_t RESERVED8[1]; + __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ + __IO uint32_t WDTCLKUEN; + __IO uint32_t WDTCLKDIV; + uint32_t RESERVED9[1]; + __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ + __IO uint32_t CLKOUTUEN; + __IO uint32_t CLKOUTDIV; + uint32_t RESERVED10[5]; + + __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ + __IO uint32_t PIOPORCAP1; + uint32_t RESERVED11[18]; + + __IO uint32_t BODCTRL; /* Offset 0x150 */ + uint32_t RESERVED12[1]; + __IO uint32_t SYSTCKCAL; + uint32_t RESERVED13[41]; + + __IO uint32_t STARTAPRP0; /* Offset 0x200 */ + __IO uint32_t STARTERP0; + __IO uint32_t STARTRSRP0CLR; + __IO uint32_t STARTSRP0; + __IO uint32_t STARTAPRP1; + __IO uint32_t STARTERP1; + __IO uint32_t STARTRSRP1CLR; + __IO uint32_t STARTSRP1; + uint32_t RESERVED14[4]; + + __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ + __IO uint32_t PDAWAKECFG; + __IO uint32_t PDRUNCFG; + uint32_t RESERVED15[110]; + __I uint32_t DEVICE_ID; +} LPC_SYSCON_TypeDef; + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +typedef struct +{ + __IO uint32_t PIO2_6; + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; + __IO uint32_t RESET_PIO0_0; + __IO uint32_t PIO0_1; + __IO uint32_t PIO1_8; + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; + + __IO uint32_t PIO2_7; + __IO uint32_t PIO2_8; + __IO uint32_t PIO2_1; + __IO uint32_t PIO0_3; + __IO uint32_t PIO0_4; + __IO uint32_t PIO0_5; + __IO uint32_t PIO1_9; + __IO uint32_t PIO3_4; + + __IO uint32_t PIO2_4; + __IO uint32_t PIO2_5; + __IO uint32_t PIO3_5; + __IO uint32_t PIO0_6; + __IO uint32_t PIO0_7; + __IO uint32_t PIO2_9; + __IO uint32_t PIO2_10; + __IO uint32_t PIO2_2; + + __IO uint32_t PIO0_8; + __IO uint32_t PIO0_9; + __IO uint32_t JTAG_TCK_PIO0_10; + __IO uint32_t PIO1_10; + __IO uint32_t PIO2_11; + __IO uint32_t JTAG_TDI_PIO0_11; + __IO uint32_t JTAG_TMS_PIO1_0; + __IO uint32_t JTAG_TDO_PIO1_1; + + __IO uint32_t JTAG_nTRST_PIO1_2; + __IO uint32_t PIO3_0; + __IO uint32_t PIO3_1; + __IO uint32_t PIO2_3; + __IO uint32_t ARM_SWDIO_PIO1_3; + __IO uint32_t PIO1_4; + __IO uint32_t PIO1_11; + __IO uint32_t PIO3_2; + + __IO uint32_t PIO1_5; + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO3_3; + __IO uint32_t SCKLOC; /* For HB1 only, new feature */ +} LPC_IOCON_TypeDef; + + +/*------------- Power Management Unit (PMU) --------------------------*/ +typedef struct +{ + __IO uint32_t PCON; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; +} LPC_PMU_TypeDef; + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; + __IO uint32_t IS; + __IO uint32_t IBE; + __IO uint32_t IEV; + __IO uint32_t IE; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t IC; +} LPC_GPIO_TypeDef; + + +/*------------- Timer (TMR) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + uint32_t RESERVED1[3]; + __IO uint32_t EMR; + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; + __IO uint32_t PWMC; +} LPC_TMR_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint32_t RBR; + __O uint32_t THR; + __IO uint32_t DLL; + }; + union { + __IO uint32_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint32_t FCR; + }; + __IO uint32_t LCR; + __IO uint32_t MCR; + __I uint32_t LSR; + __I uint32_t MSR; + __IO uint32_t SCR; + __IO uint32_t ACR; + __IO uint32_t ICR; + __IO uint32_t FDR; + uint32_t RESERVED0; + __IO uint32_t TER; + uint32_t RESERVED1[6]; + __IO uint32_t RS485CTRL; + __IO uint32_t ADRMATCH; + __IO uint32_t RS485DLY; + __I uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t CONSET; + __I uint32_t STAT; + __IO uint32_t DAT; + __IO uint32_t ADR0; + __IO uint32_t SCLH; + __IO uint32_t SCLL; + __O uint32_t CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t ADR1; + __IO uint32_t ADR2; + __IO uint32_t ADR3; + __I uint32_t DATA_BUFFER; + __IO uint32_t MASK0; + __IO uint32_t MASK1; + __IO uint32_t MASK2; + __IO uint32_t MASK3; +} LPC_I2C_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t TC; + __O uint32_t FEED; + __I uint32_t TV; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t GDR; + uint32_t RESERVED0; + __IO uint32_t INTEN; + __I uint32_t DR0; + __I uint32_t DR1; + __I uint32_t DR2; + __I uint32_t DR3; + __I uint32_t DR4; + __I uint32_t DR5; + __I uint32_t DR6; + __I uint32_t DR7; + __I uint32_t STAT; +} LPC_ADC_TypeDef; + + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t DevIntEn; + __O uint32_t DevIntClr; + __O uint32_t DevIntSet; + + __O uint32_t CmdCode; /* USB Device SIE Command Registers */ + __I uint32_t CmdData; + + __I uint32_t RxData; /* USB Device Transfer Registers */ + __O uint32_t TxData; + __I uint32_t RxPLen; + __O uint32_t TxPLen; + __IO uint32_t Ctrl; + __O uint32_t DevFIQSel; +} LPC_USB_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#endif // __LPC13xx_H__
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/startup/arm/startup_LPC13xx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/startup/arm/startup_LPC13xx.s Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,271 @@ +;/***************************************************************************** +; * @file: startup_LPC13xx.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the NXP LPC13xx Device Series +; * @version: V1.0 +; * @date: 27. Aug. 2009 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WAKEUP_IRQHandler ; 16+ 0: Wakeup PIO0.0 + DCD WAKEUP_IRQHandler ; 16+ 1: Wakeup PIO0.1 + DCD WAKEUP_IRQHandler ; 16+ 2: Wakeup PIO0.2 + DCD WAKEUP_IRQHandler ; 16+ 3: Wakeup PIO0.3 + DCD WAKEUP_IRQHandler ; 16+ 4: Wakeup PIO0.4 + DCD WAKEUP_IRQHandler ; 16+ 5: Wakeup PIO0.5 + DCD WAKEUP_IRQHandler ; 16+ 6: Wakeup PIO0.6 + DCD WAKEUP_IRQHandler ; 16+ 7: Wakeup PIO0.7 + DCD WAKEUP_IRQHandler ; 16+ 8: Wakeup PIO0.8 + DCD WAKEUP_IRQHandler ; 16+ 9: Wakeup PIO0.9 + DCD WAKEUP_IRQHandler ; 16+10: Wakeup PIO0.10 + DCD WAKEUP_IRQHandler ; 16+11: Wakeup PIO0.11 + DCD WAKEUP_IRQHandler ; 16+12: Wakeup PIO1.0 + DCD WAKEUP_IRQHandler ; 16+13: Wakeup PIO1.1 + DCD WAKEUP_IRQHandler ; 16+14: Wakeup PIO1.2 + DCD WAKEUP_IRQHandler ; 16+15: Wakeup PIO1.3 + DCD WAKEUP_IRQHandler ; 16+16: Wakeup PIO1.4 + DCD WAKEUP_IRQHandler ; 16+17: Wakeup PIO1.5 + DCD WAKEUP_IRQHandler ; 16+18: Wakeup PIO1.6 + DCD WAKEUP_IRQHandler ; 16+19: Wakeup PIO1.7 + DCD WAKEUP_IRQHandler ; 16+20: Wakeup PIO1.8 + DCD WAKEUP_IRQHandler ; 16+21: Wakeup PIO1.9 + DCD WAKEUP_IRQHandler ; 16+22: Wakeup PIO1.10 + DCD WAKEUP_IRQHandler ; 16+23: Wakeup PIO1.11 + DCD WAKEUP_IRQHandler ; 16+24: Wakeup PIO2.0 + DCD WAKEUP_IRQHandler ; 16+25: Wakeup PIO2.1 + DCD WAKEUP_IRQHandler ; 16+26: Wakeup PIO2.2 + DCD WAKEUP_IRQHandler ; 16+27: Wakeup PIO2.3 + DCD WAKEUP_IRQHandler ; 16+28: Wakeup PIO2.4 + DCD WAKEUP_IRQHandler ; 16+29: Wakeup PIO2.5 + DCD WAKEUP_IRQHandler ; 16+30: Wakeup PIO2.6 + DCD WAKEUP_IRQHandler ; 16+31: Wakeup PIO2.7 + DCD WAKEUP_IRQHandler ; 16+32: Wakeup PIO2.8 + DCD WAKEUP_IRQHandler ; 16+33: Wakeup PIO2.9 + DCD WAKEUP_IRQHandler ; 16+34: Wakeup PIO2.10 + DCD WAKEUP_IRQHandler ; 16+35: Wakeup PIO2.11 + DCD WAKEUP_IRQHandler ; 16+36: Wakeup PIO3.0 + DCD WAKEUP_IRQHandler ; 16+37: Wakeup PIO3.1 + DCD WAKEUP_IRQHandler ; 16+38: Wakeup PIO3.2 + DCD WAKEUP_IRQHandler ; 16+39: Wakeup PIO3.3 + DCD I2C_IRQHandler ; 16+40: I2C + DCD TIMER16_0_IRQHandler ; 16+41: 16-bit Counter-Timer 0 + DCD TIMER16_1_IRQHandler ; 16+42: 16-bit Counter-Timer 1 + DCD TIMER32_0_IRQHandler ; 16+43: 32-bit Counter-Timer 0 + DCD TIMER32_1_IRQHandler ; 16+44: 32-bit Counter-Timer 1 + DCD SSP_IRQHandler ; 16+45: SSP + DCD UART_IRQHandler ; 16+46: UART + DCD USB_IRQHandler ; 16+47: USB IRQ + DCD USB_FIQHandler ; 16+48: USB FIQ + DCD ADC_IRQHandler ; 16+49: A/D Converter + DCD WDT_IRQHandler ; 16+50: Watchdog Timer + DCD BOD_IRQHandler ; 16+51: Brown Out Detect + DCD FMC_IRQHandler ; 16+52: IP2111 Flash Memory Controller + DCD PIOINT3_IRQHandler ; 16+53: PIO INT3 + DCD PIOINT2_IRQHandler ; 16+54: PIO INT2 + DCD PIOINT1_IRQHandler ; 16+55: PIO INT1 + DCD PIOINT0_IRQHandler ; 16+56: PIO INT0 + + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WAKEUP_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT PIOINT3_IRQHandler [WEAK] + EXPORT PIOINT2_IRQHandler [WEAK] + EXPORT PIOINT1_IRQHandler [WEAK] + EXPORT PIOINT0_IRQHandler [WEAK] + +WAKEUP_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +PIOINT3_IRQHandler +PIOINT2_IRQHandler +PIOINT1_IRQHandler +PIOINT0_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/startup/gcc/startup_LPC13xx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/startup/gcc/startup_LPC13xx.s Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,248 @@ +/*****************************************************************************/ +/* startup_LPC13xx.s: Startup file for LPC13xx device series */ +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +//*** <<< Use Configuration Wizard in Context Menu >>> *** +*/ + + +/* +// <h> Stack Configuration +// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// <h> Heap Configuration +// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long WAKEUP_IRQHandler /* 16+ 0: Wakeup PIO0.0 */ + .long WAKEUP_IRQHandler /* 16+ 1: Wakeup PIO0.1 */ + .long WAKEUP_IRQHandler /* 16+ 2: Wakeup PIO0.2 */ + .long WAKEUP_IRQHandler /* 16+ 3: Wakeup PIO0.3 */ + .long WAKEUP_IRQHandler /* 16+ 4: Wakeup PIO0.4 */ + .long WAKEUP_IRQHandler /* 16+ 5: Wakeup PIO0.5 */ + .long WAKEUP_IRQHandler /* 16+ 6: Wakeup PIO0.6 */ + .long WAKEUP_IRQHandler /* 16+ 7: Wakeup PIO0.7 */ + .long WAKEUP_IRQHandler /* 16+ 8: Wakeup PIO0.8 */ + .long WAKEUP_IRQHandler /* 16+ 9: Wakeup PIO0.9 */ + .long WAKEUP_IRQHandler /* 16+10: Wakeup PIO0.10 */ + .long WAKEUP_IRQHandler /* 16+11: Wakeup PIO0.11 */ + .long WAKEUP_IRQHandler /* 16+12: Wakeup PIO1.0 */ + .long WAKEUP_IRQHandler /* 16+13: Wakeup PIO1.1 */ + .long WAKEUP_IRQHandler /* 16+14: Wakeup PIO1.2 */ + .long WAKEUP_IRQHandler /* 16+15: Wakeup PIO1.3 */ + .long WAKEUP_IRQHandler /* 16+16: Wakeup PIO1.4 */ + .long WAKEUP_IRQHandler /* 16+17: Wakeup PIO1.5 */ + .long WAKEUP_IRQHandler /* 16+18: Wakeup PIO1.6 */ + .long WAKEUP_IRQHandler /* 16+19: Wakeup PIO1.7 */ + .long WAKEUP_IRQHandler /* 16+20: Wakeup PIO1.8 */ + .long WAKEUP_IRQHandler /* 16+21: Wakeup PIO1.9 */ + .long WAKEUP_IRQHandler /* 16+22: Wakeup PIO1.10 */ + .long WAKEUP_IRQHandler /* 16+23: Wakeup PIO1.11 */ + .long WAKEUP_IRQHandler /* 16+24: Wakeup PIO2.0 */ + .long WAKEUP_IRQHandler /* 16+25: Wakeup PIO2.1 */ + .long WAKEUP_IRQHandler /* 16+26: Wakeup PIO2.2 */ + .long WAKEUP_IRQHandler /* 16+27: Wakeup PIO2.3 */ + .long WAKEUP_IRQHandler /* 16+28: Wakeup PIO2.4 */ + .long WAKEUP_IRQHandler /* 16+29: Wakeup PIO2.5 */ + .long WAKEUP_IRQHandler /* 16+30: Wakeup PIO2.6 */ + .long WAKEUP_IRQHandler /* 16+31: Wakeup PIO2.7 */ + .long WAKEUP_IRQHandler /* 16+32: Wakeup PIO2.8 */ + .long WAKEUP_IRQHandler /* 16+33: Wakeup PIO2.9 */ + .long WAKEUP_IRQHandler /* 16+34: Wakeup PIO2.10 */ + .long WAKEUP_IRQHandler /* 16+35: Wakeup PIO2.11 */ + .long WAKEUP_IRQHandler /* 16+36: Wakeup PIO3.0 */ + .long WAKEUP_IRQHandler /* 16+37: Wakeup PIO3.1 */ + .long WAKEUP_IRQHandler /* 16+38: Wakeup PIO3.2 */ + .long WAKEUP_IRQHandler /* 16+39: Wakeup PIO3.3 */ + .long I2C_IRQHandler /* 16+40: I2C */ + .long TIMER16_0_IRQHandler /* 16+41: 16-bit Counter-Timer 0 */ + .long TIMER16_1_IRQHandler /* 16+42: 16-bit Counter-Timer 1 */ + .long TIMER32_0_IRQHandler /* 16+43: 32-bit Counter-Timer 0 */ + .long TIMER32_1_IRQHandler /* 16+44: 32-bit Counter-Timer 1 */ + .long SSP_IRQHandler /* 16+45: SSP */ + .long UART_IRQHandler /* 16+46: UART */ + .long USB_IRQHandler /* 16+47: USB IRQ */ + .long USB_FIQHandler /* 16+48: USB FIQ */ + .long ADC_IRQHandler /* 16+49: A/D Converter */ + .long WDT_IRQHandler /* 16+50: Watchdog Timer */ + .long BOD_IRQHandler /* 16+51: Brown Out Detect */ + .long FMC_IRQHandler /* 16+52: IP2111 Flash Memory */ + .long PIOINT3_IRQHandler /* 16+53: PIO INT3 */ + .long PIOINT2_IRQHandler /* 16+54: PIO INT2 */ + .long PIOINT1_IRQHandler /* 16+55: PIO INT1 */ + .long PIOINT0_IRQHandler /* 16+56: PIO INT0 */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ WAKEUP_IRQHandler + IRQ I2C_IRQHandler + IRQ TIMER16_0_IRQHandler + IRQ TIMER16_1_IRQHandler + IRQ TIMER32_0_IRQHandler + IRQ TIMER32_1_IRQHandler + IRQ SSP_IRQHandler + IRQ UART_IRQHandler + IRQ USB_IRQHandler + IRQ USB_FIQHandler + IRQ ADC_IRQHandler + IRQ WDT_IRQHandler + IRQ BOD_IRQHandler + IRQ FMC_IRQHandler + IRQ PIOINT3_IRQHandler + IRQ PIOINT2_IRQHandler + IRQ PIOINT1_IRQHandler + IRQ PIOINT0_IRQHandler + + .end
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/startup/iar/startup_LPC13xx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/startup/iar/startup_LPC13xx.s Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,291 @@ +;/***************************************************************************** +; * @file: startup_LPC13xx.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the NXP LPC13xx Device Series +; * @version: V1.00 +; * @date: 19. October 2009 +; *---------------------------------------------------------------------------- +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * +; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WAKEUP_IRQHandler ; 16+ 0: Wakeup PIO0.0 + DCD WAKEUP_IRQHandler ; 16+ 1: Wakeup PIO0.1 + DCD WAKEUP_IRQHandler ; 16+ 2: Wakeup PIO0.2 + DCD WAKEUP_IRQHandler ; 16+ 3: Wakeup PIO0.3 + DCD WAKEUP_IRQHandler ; 16+ 4: Wakeup PIO0.4 + DCD WAKEUP_IRQHandler ; 16+ 5: Wakeup PIO0.5 + DCD WAKEUP_IRQHandler ; 16+ 6: Wakeup PIO0.6 + DCD WAKEUP_IRQHandler ; 16+ 7: Wakeup PIO0.7 + DCD WAKEUP_IRQHandler ; 16+ 8: Wakeup PIO0.8 + DCD WAKEUP_IRQHandler ; 16+ 9: Wakeup PIO0.9 + DCD WAKEUP_IRQHandler ; 16+10: Wakeup PIO0.10 + DCD WAKEUP_IRQHandler ; 16+11: Wakeup PIO0.11 + DCD WAKEUP_IRQHandler ; 16+12: Wakeup PIO1.0 + DCD WAKEUP_IRQHandler ; 16+13: Wakeup PIO1.1 + DCD WAKEUP_IRQHandler ; 16+14: Wakeup PIO1.2 + DCD WAKEUP_IRQHandler ; 16+15: Wakeup PIO1.3 + DCD WAKEUP_IRQHandler ; 16+16: Wakeup PIO1.4 + DCD WAKEUP_IRQHandler ; 16+17: Wakeup PIO1.5 + DCD WAKEUP_IRQHandler ; 16+18: Wakeup PIO1.6 + DCD WAKEUP_IRQHandler ; 16+19: Wakeup PIO1.7 + DCD WAKEUP_IRQHandler ; 16+20: Wakeup PIO1.8 + DCD WAKEUP_IRQHandler ; 16+21: Wakeup PIO1.9 + DCD WAKEUP_IRQHandler ; 16+22: Wakeup PIO1.10 + DCD WAKEUP_IRQHandler ; 16+23: Wakeup PIO1.11 + DCD WAKEUP_IRQHandler ; 16+24: Wakeup PIO2.0 + DCD WAKEUP_IRQHandler ; 16+25: Wakeup PIO2.1 + DCD WAKEUP_IRQHandler ; 16+26: Wakeup PIO2.2 + DCD WAKEUP_IRQHandler ; 16+27: Wakeup PIO2.3 + DCD WAKEUP_IRQHandler ; 16+28: Wakeup PIO2.4 + DCD WAKEUP_IRQHandler ; 16+29: Wakeup PIO2.5 + DCD WAKEUP_IRQHandler ; 16+30: Wakeup PIO2.6 + DCD WAKEUP_IRQHandler ; 16+31: Wakeup PIO2.7 + DCD WAKEUP_IRQHandler ; 16+32: Wakeup PIO2.8 + DCD WAKEUP_IRQHandler ; 16+33: Wakeup PIO2.9 + DCD WAKEUP_IRQHandler ; 16+34: Wakeup PIO2.10 + DCD WAKEUP_IRQHandler ; 16+35: Wakeup PIO2.11 + DCD WAKEUP_IRQHandler ; 16+36: Wakeup PIO3.0 + DCD WAKEUP_IRQHandler ; 16+37: Wakeup PIO3.1 + DCD WAKEUP_IRQHandler ; 16+38: Wakeup PIO3.2 + DCD WAKEUP_IRQHandler ; 16+39: Wakeup PIO3.3 + DCD I2C_IRQHandler ; 16+40: I2C + DCD TIMER16_0_IRQHandler ; 16+41: 16-bit Counter-Timer 0 + DCD TIMER16_1_IRQHandler ; 16+42: 16-bit Counter-Timer 1 + DCD TIMER32_0_IRQHandler ; 16+43: 32-bit Counter-Timer 0 + DCD TIMER32_1_IRQHandler ; 16+44: 32-bit Counter-Timer 1 + DCD SSP_IRQHandler ; 16+45: SSP + DCD UART_IRQHandler ; 16+46: UART + DCD USB_IRQHandler ; 16+47: USB IRQ + DCD USB_FIQHandler ; 16+48: USB FIQ + DCD ADC_IRQHandler ; 16+49: A/D Converter + DCD WDT_IRQHandler ; 16+50: Watchdog Timer + DCD BOD_IRQHandler ; 16+51: Brown Out Detect + DCD FMC_IRQHandler ; 16+52: IP2111 Flash Memory Controller + DCD PIOINT3_IRQHandler ; 16+53: PIO INT3 + DCD PIOINT2_IRQHandler ; 16+54: PIO INT2 + DCD PIOINT1_IRQHandler ; 16+55: PIO INT1 + DCD PIOINT0_IRQHandler ; 16+56: PIO INT0 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WAKEUP_IRQHandler + SECTION .text:CODE:REORDER(1) +WAKEUP_IRQHandler + B WAKEUP_IRQHandler + + PUBWEAK I2C_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C_IRQHandler + B I2C_IRQHandler + + PUBWEAK TIMER16_0_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER16_0_IRQHandler + B TIMER16_0_IRQHandler + + PUBWEAK TIMER16_1_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER16_1_IRQHandler + B TIMER16_1_IRQHandler + + PUBWEAK TIMER32_0_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER32_0_IRQHandler + B TIMER32_0_IRQHandler + + PUBWEAK TIMER32_1_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER32_1_IRQHandler + B TIMER32_1_IRQHandler + + PUBWEAK SSP_IRQHandler + SECTION .text:CODE:REORDER(1) +SSP_IRQHandler + B SSP_IRQHandler + + PUBWEAK UART_IRQHandler + SECTION .text:CODE:REORDER(1) +UART_IRQHandler + B UART_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK USB_FIQHandler + SECTION .text:CODE:REORDER(1) +USB_FIQHandler + B USB_FIQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + PUBWEAK BOD_IRQHandler + SECTION .text:CODE:REORDER(1) +BOD_IRQHandler + B BOD_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK PIOINT3_IRQHandler + SECTION .text:CODE:REORDER(1) +PIOINT3_IRQHandler + B PIOINT3_IRQHandler + + PUBWEAK PIOINT2_IRQHandler + SECTION .text:CODE:REORDER(1) +PIOINT2_IRQHandler + B PIOINT2_IRQHandler + + PUBWEAK PIOINT1_IRQHandler + SECTION .text:CODE:REORDER(1) +PIOINT1_IRQHandler + B PIOINT1_IRQHandler + + PUBWEAK PIOINT0_IRQHandler + SECTION .text:CODE:REORDER(1) +PIOINT0_IRQHandler + B PIOINT0_IRQHandler + + + END
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/system_LPC13xx.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/system_LPC13xx.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,479 @@ +/**************************************************************************//** + * @file system_LPC13xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the NXP LPC13xx Device Series + * @version V1.02 + * @date 21. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include <stdint.h> +#include "LPC13xx.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// <e> Clock Configuration +// <e1> System Clock Setup +// <e2> System Oscillator Enable +// <o3.1> Select System Oscillator Frequency Range +// <0=> 1 - 20 MHz +// <1=> 15 - 25 MHz +// </e2> +// <e4> Watchdog Oscillator Enable +// <o5.0..4> Select Divider for Fclkana +// <0=> 2 <1=> 4 <2=> 6 <3=> 8 +// <4=> 10 <5=> 12 <6=> 14 <7=> 16 +// <8=> 18 <9=> 20 <10=> 22 <11=> 24 +// <12=> 26 <13=> 28 <14=> 30 <15=> 32 +// <16=> 34 <17=> 36 <18=> 38 <19=> 40 +// <20=> 42 <21=> 44 <22=> 46 <23=> 48 +// <24=> 50 <25=> 52 <26=> 54 <27=> 56 +// <28=> 58 <29=> 60 <30=> 62 <31=> 64 +// <o5.5..8> Select Watchdog Oscillator Analog Frequency (Fclkana) +// <0=> Disabled +// <1=> 0.5 MHz +// <2=> 0.8 MHz +// <3=> 1.1 MHz +// <4=> 1.4 MHz +// <5=> 1.6 MHz +// <6=> 1.8 MHz +// <7=> 2.0 MHz +// <8=> 2.2 MHz +// <9=> 2.4 MHz +// <10=> 2.6 MHz +// <11=> 2.7 MHz +// <12=> 2.9 MHz +// <13=> 3.1 MHz +// <14=> 3.2 MHz +// <15=> 3.4 MHz +// </e4> +// <o6> Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL) +// <0=> IRC Oscillator +// <1=> System Oscillator +// <2=> WDT Oscillator +// <3=> Invalid +// <e7> Use System PLL +// <i> F_pll = M * F_in +// <i> F_in must be in the range of 10 MHz to 25 MHz +// <o8.0..4> M: PLL Multiplier Selection +// <1-32><#-1> +// <o8.5..6> P: PLL Divider Selection +// <0=> 2 +// <1=> 4 +// <2=> 8 +// <3=> 16 +// <o8.7> DIRECT: Direct CCO Clock Output Enable +// <o8.8> BYPASS: PLL Bypass Enable +// </e7> +// <o9> Select Input Clock for Main clock (Register: MAINCLKSEL) +// <0=> IRC Oscillator +// <1=> Input Clock to System PLL +// <2=> WDT Oscillator +// <3=> System PLL Clock Out +// </e1> +// <e10> USB Clock Setup +// <e11> Use USB PLL +// <i> F_pll = M * F_in +// <i> F_in must be in the range of 10 MHz to 25 MHz +// <o12.0..1> Select Input Clock for usb_pllclkin (Register: USBPLLCLKSEL) +// <0=> IRC Oscillator +// <1=> System Oscillator +// <o13.0..4> M: PLL Multiplier Selection +// <1-32><#-1> +// <o13.5..6> P: PLL Divider Selection +// <0=> 2 +// <1=> 4 +// <2=> 8 +// <3=> 16 +// <o13.7> DIRECT: Direct CCO Clock Output Enable +// <o13.8> BYPASS: PLL Bypass Enable +// </e11> +// </e10> +// <o14.0..7> System AHB Divider <0-255> +// <i> 0 = is disabled +// <o15.0> SYS Clock Enable +// <o15.1> ROM Clock Enable +// <o15.2> RAM Clock Enable +// <o15.3> FLASH1 Clock Enable +// <o15.4> FLASH2 Clock Enable +// <o15.5> I2C Clock Enable +// <o15.6> GPIO Clock Enable +// <o15.7> CT16B0 Clock Enable +// <o15.8> CT16B1 Clock Enable +// <o15.9> CT32B0 Clock Enable +// <o15.10> CT32B1 Clock Enable +// <o15.11> SSP Clock Enable +// <o15.12> UART Clock Enable +// <o15.13> ADC Clock Enable +// <o15.14> USB_REG Clock Enable +// <o15.15> SWDT Clock Enable +// <o15.16> IOCON Clock Enable +// </e> +*/ +#define CLOCK_SETUP 1 +#define SYSCLK_SETUP 1 +#define SYSOSC_SETUP 1 +#define SYSOSCCTRL_Val 0x00000000 +#define WDTOSC_SETUP 0 +#define WDTOSCCTRL_Val 0x000000A0 +#define SYSPLLCLKSEL_Val 0x00000001 +#define SYSPLL_SETUP 1 +#define SYSPLLCTRL_Val 0x00000005 +#define MAINCLKSEL_Val 0x00000003 +#define USBCLK_SETUP 0 +#define USBPLL_SETUP 1 +#define USBPLLCLKSEL_Val 0x00000001 +#define USBPLLCTRL_Val 0x00000003 +#define SYSAHBCLKDIV_Val 0x00000001 +#define AHBCLKCTRL_Val 0x0001005F + +/*--------------------- Memory Mapping Configuration ------------------------- +// +// <e> Memory Mapping +// <o1.0..1> System Memory Remap (Register: SYSMEMREMAP) +// <0=> Bootloader mapped to address 0 +// <1=> RAM mapped to address 0 +// <2=> Flash mapped to address 0 +// <3=> Flash mapped to address 0 +// </e> +*/ +#define MEMMAP_SETUP 0 +#define SYSMEMREMAP_Val 0x00000001 + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) + #error "SYSOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) + #error "WDTOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2)) + #error "SYSPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) + #error "SYSPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) + #error "MAINCLKSEL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) + #error "USBPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF)) + #error "USBPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((USBPLLUEN_Val), ~0x00000001)) + #error "USBPLLUEN: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) + #error "SYSAHBCLKDIV: Value out of range!" +#endif + +#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF)) + #error "AHBCLKCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003)) + #error "SYSMEMREMAP: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (12000000UL) /* Oscillator frequency */ +#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ +#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ + + +#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) +#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) + +#if (CLOCK_SETUP) /* Clock Setup */ + #if (SYSCLK_SETUP) /* System Clock Setup */ + #if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/ + #if (__FREQSEL == 0) + #define __WDT_OSC_CLK ( 400000 / __DIVSEL) + #elif (__FREQSEL == 1) + #define __WDT_OSC_CLK ( 500000 / __DIVSEL) + #elif (__FREQSEL == 2) + #define __WDT_OSC_CLK ( 800000 / __DIVSEL) + #elif (__FREQSEL == 3) + #define __WDT_OSC_CLK (1100000 / __DIVSEL) + #elif (__FREQSEL == 4) + #define __WDT_OSC_CLK (1400000 / __DIVSEL) + #elif (__FREQSEL == 5) + #define __WDT_OSC_CLK (1600000 / __DIVSEL) + #elif (__FREQSEL == 6) + #define __WDT_OSC_CLK (1800000 / __DIVSEL) + #elif (__FREQSEL == 7) + #define __WDT_OSC_CLK (2000000 / __DIVSEL) + #elif (__FREQSEL == 8) + #define __WDT_OSC_CLK (2200000 / __DIVSEL) + #elif (__FREQSEL == 9) + #define __WDT_OSC_CLK (2400000 / __DIVSEL) + #elif (__FREQSEL == 10) + #define __WDT_OSC_CLK (2600000 / __DIVSEL) + #elif (__FREQSEL == 11) + #define __WDT_OSC_CLK (2700000 / __DIVSEL) + #elif (__FREQSEL == 12) + #define __WDT_OSC_CLK (2900000 / __DIVSEL) + #elif (__FREQSEL == 13) + #define __WDT_OSC_CLK (3100000 / __DIVSEL) + #elif (__FREQSEL == 14) + #define __WDT_OSC_CLK (3200000 / __DIVSEL) + #else + #define __WDT_OSC_CLK (3400000 / __DIVSEL) + #endif + #else + #define __WDT_OSC_CLK (1600000 / 2) + #endif // WDTOSC_SETUP + + /* sys_pllclkin calculation */ + #if ((SYSPLLCLKSEL_Val & 0x03) == 0) + #define __SYS_PLLCLKIN (__IRC_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) + #define __SYS_PLLCLKIN (__SYS_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 2) + #define __SYS_PLLCLKIN (__WDT_OSC_CLK) + #else + #define __SYS_PLLCLKIN (0) + #endif + + #if (SYSPLL_SETUP) /* System PLL Setup */ + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) + #else + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1)) + #endif // SYSPLL_SETUP + + /* main clock calculation */ + #if ((MAINCLKSEL_Val & 0x03) == 0) + #define __MAIN_CLOCK (__IRC_OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 1) + #define __MAIN_CLOCK (__SYS_PLLCLKIN) + #elif ((MAINCLKSEL_Val & 0x03) == 2) + #define __MAIN_CLOCK (__WDT_OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 3) + #define __MAIN_CLOCK (__SYS_PLLCLKOUT) + #else + #define __MAIN_CLOCK (0) + #endif + + #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) + + #else // SYSCLK_SETUP + #if (SYSAHBCLKDIV_Val == 0) + #define __SYSTEM_CLOCK (0) + #else + #define __SYSTEM_CLOCK (__XTAL / SYSAHBCLKDIV_Val) + #endif + #endif // SYSCLK_SETUP + +#else + #define __SYSTEM_CLOCK (__XTAL) +#endif // CLOCK_SETUP + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t wdt_osc = 0; + + /* Determine clock frequency according to clock register values */ + switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { + case 0: wdt_osc = 400000; break; + case 1: wdt_osc = 500000; break; + case 2: wdt_osc = 800000; break; + case 3: wdt_osc = 1100000; break; + case 4: wdt_osc = 1400000; break; + case 5: wdt_osc = 1600000; break; + case 6: wdt_osc = 1800000; break; + case 7: wdt_osc = 2000000; break; + case 8: wdt_osc = 2200000; break; + case 9: wdt_osc = 2400000; break; + case 10: wdt_osc = 2600000; break; + case 11: wdt_osc = 2700000; break; + case 12: wdt_osc = 2900000; break; + case 13: wdt_osc = 3100000; break; + case 14: wdt_osc = 3200000; break; + case 15: wdt_osc = 3400000; break; + } + wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; + + switch (LPC_SYSCON->MAINCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* Input Clock to System PLL */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK; + break; + case 2: /* WDT Oscillator */ + SystemCoreClock = wdt_osc; + break; + case 3: /* Reserved */ + SystemCoreClock = 0; + break; + } + break; + case 2: /* WDT Oscillator */ + SystemCoreClock = wdt_osc; + break; + case 3: /* System PLL Clock Out */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = __IRC_OSC_CLK; + } else { + SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 1: /* System oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = __SYS_OSC_CLK; + } else { + SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 2: /* WDT Oscillator */ + if (LPC_SYSCON->SYSPLLCTRL & 0x180) { + SystemCoreClock = wdt_osc; + } else { + SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + } + break; + case 3: /* Reserved */ + SystemCoreClock = 0; + break; + } + break; + } + + SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (CLOCK_SETUP) /* Clock Setup */ +#if (SYSCLK_SETUP) /* System Clock Setup */ +#if (SYSOSC_SETUP) /* System Oscillator Setup */ + uint32_t i; + + LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */ + LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; + for (i = 0; i < 200; i++) __NOP(); + LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ + LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ + LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->SYSPLLCLKUEN = 0x01; + while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ +#if (SYSPLL_SETUP) /* System PLL Setup */ + LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */ + while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ +#endif +#endif +#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/ + LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */ +#endif + LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ + LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ + LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->MAINCLKUEN = 0x01; + while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ +#endif + +#if (USBCLK_SETUP) /* USB Clock Setup */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */ +#if (USBPLL_SETUP) /* USB PLL Setup */ + LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */ + LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ + LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */ + LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */ + LPC_SYSCON->USBPLLCLKUEN = 0x01; + while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */ + LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; + while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ + LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */ +#else + LPC_SYSCON->USBCLKSEL = 0x01; /* Select Main Clock */ +#endif +#else + LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */ + LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */ +#endif + + LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; + LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val; +#endif + + +#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */ + LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val; +#endif +}
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/system_LPC13xx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/system_LPC13xx.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC13xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC13xx_H +#define __SYSTEM_LPC13xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC13x_H */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/LPC17xx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/LPC17xx.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1028 @@ +/**************************************************************************//** + * @file LPC17xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version V1.07 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC17xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SC) ------------------------------------------*/ +typedef struct +{ + __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /* Clocking and Power Control */ + __IO uint32_t PLL0CFG; + __I uint32_t PLL0STAT; + __O uint32_t PLL0FEED; + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; + __IO uint32_t PLL1CFG; + __I uint32_t PLL1STAT; + __O uint32_t PLL1FEED; + uint32_t RESERVED2[4]; + __IO uint32_t PCON; + __IO uint32_t PCONP; + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; + __IO uint32_t USBCLKCFG; + __IO uint32_t CLKSRCSEL; + uint32_t RESERVED4[12]; + __IO uint32_t EXTINT; /* External Interrupts */ + uint32_t RESERVED5; + __IO uint32_t EXTMODE; + __IO uint32_t EXTPOLAR; + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /* Reset */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; + __IO uint32_t PCLKSEL1; + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ + __IO uint32_t DMAREQSEL; + __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ + } LPC_SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +typedef struct +{ + __IO uint32_t PINSEL0; + __IO uint32_t PINSEL1; + __IO uint32_t PINSEL2; + __IO uint32_t PINSEL3; + __IO uint32_t PINSEL4; + __IO uint32_t PINSEL5; + __IO uint32_t PINSEL6; + __IO uint32_t PINSEL7; + __IO uint32_t PINSEL8; + __IO uint32_t PINSEL9; + __IO uint32_t PINSEL10; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; + __IO uint32_t PINMODE1; + __IO uint32_t PINMODE2; + __IO uint32_t PINMODE3; + __IO uint32_t PINMODE4; + __IO uint32_t PINMODE5; + __IO uint32_t PINMODE6; + __IO uint32_t PINMODE7; + __IO uint32_t PINMODE8; + __IO uint32_t PINMODE9; + __IO uint32_t PINMODE_OD0; + __IO uint32_t PINMODE_OD1; + __IO uint32_t PINMODE_OD2; + __IO uint32_t PINMODE_OD3; + __IO uint32_t PINMODE_OD4; + __IO uint32_t I2CPADCFG; +} LPC_PINCON_TypeDef; + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t FIODIR; + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; + +typedef struct +{ + __I uint32_t IntStatus; + __I uint32_t IO0IntStatR; + __I uint32_t IO0IntStatF; + __O uint32_t IO0IntClr; + __IO uint32_t IO0IntEnR; + __IO uint32_t IO0IntEnF; + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; + __I uint32_t IO2IntStatF; + __O uint32_t IO2IntClr; + __IO uint32_t IO2IntEnR; + __IO uint32_t IO2IntEnF; +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + uint32_t RESERVED0[2]; + __IO uint32_t EMR; + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + __I uint32_t CR2; + __I uint32_t CR3; + uint32_t RESERVED0; + __IO uint32_t MR4; + __IO uint32_t MR5; + __IO uint32_t MR6; + __IO uint32_t PCR; + __IO uint32_t LER; + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __I uint8_t FIFOLVL; +} LPC_UART_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint8_t ICR; + uint8_t RESERVED4[3]; + __IO uint8_t FDR; + uint8_t RESERVED5[7]; + __IO uint8_t TER; + uint8_t RESERVED6[39]; + __I uint8_t FIFOLVL; +} LPC_UART0_TypeDef; + +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[3]; + __IO uint8_t MCR; + uint8_t RESERVED2[3]; + __I uint8_t LSR; + uint8_t RESERVED3[3]; + __I uint8_t MSR; + uint8_t RESERVED4[3]; + __IO uint8_t SCR; + uint8_t RESERVED5[3]; + __IO uint32_t ACR; + uint32_t RESERVED6; + __IO uint32_t FDR; + uint32_t RESERVED7; + __IO uint8_t TER; + uint8_t RESERVED8[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED9[3]; + __IO uint8_t ADRMATCH; + uint8_t RESERVED10[3]; + __IO uint8_t RS485DLY; + uint8_t RESERVED11[3]; + __I uint8_t FIFOLVL; +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +typedef struct +{ + __IO uint32_t SPCR; + __I uint32_t SPSR; + __IO uint32_t SPDR; + __IO uint32_t SPCCR; + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t I2CONSET; + __I uint32_t I2STAT; + __IO uint32_t I2DAT; + __IO uint32_t I2ADR0; + __IO uint32_t I2SCLH; + __IO uint32_t I2SCLL; + __O uint32_t I2CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t I2ADR1; + __IO uint32_t I2ADR2; + __IO uint32_t I2ADR3; + __I uint32_t I2DATA_BUFFER; + __IO uint32_t I2MASK0; + __IO uint32_t I2MASK1; + __IO uint32_t I2MASK2; + __IO uint32_t I2MASK3; +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t I2SDAO; + __IO uint32_t I2SDAI; + __O uint32_t I2STXFIFO; + __I uint32_t I2SRXFIFO; + __I uint32_t I2SSTATE; + __IO uint32_t I2SDMA1; + __IO uint32_t I2SDMA2; + __IO uint32_t I2SIRQ; + __IO uint32_t I2STXRATE; + __IO uint32_t I2SRXRATE; + __IO uint32_t I2STXBITRATE; + __IO uint32_t I2SRXBITRATE; + __IO uint32_t I2STXMODE; + __IO uint32_t I2SRXMODE; +} LPC_I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint8_t RICTRL; + uint8_t RESERVED0[3]; + __IO uint32_t RICOUNTER; +} LPC_RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +typedef struct +{ + __IO uint8_t ILR; + uint8_t RESERVED0[7]; + __IO uint8_t CCR; + uint8_t RESERVED1[3]; + __IO uint8_t CIIR; + uint8_t RESERVED2[3]; + __IO uint8_t AMR; + uint8_t RESERVED3[3]; + __I uint32_t CTIME0; + __I uint32_t CTIME1; + __I uint32_t CTIME2; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t DOM; + uint8_t RESERVED7[3]; + __IO uint8_t DOW; + uint8_t RESERVED8[3]; + __IO uint16_t DOY; + uint16_t RESERVED9; + __IO uint8_t MONTH; + uint8_t RESERVED10[3]; + __IO uint16_t YEAR; + uint16_t RESERVED11; + __IO uint32_t CALIBRATION; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; + __IO uint8_t RTC_AUXEN; + uint8_t RESERVED12[3]; + __IO uint8_t RTC_AUX; + uint8_t RESERVED13[3]; + __IO uint8_t ALSEC; + uint8_t RESERVED14[3]; + __IO uint8_t ALMIN; + uint8_t RESERVED15[3]; + __IO uint8_t ALHOUR; + uint8_t RESERVED16[3]; + __IO uint8_t ALDOM; + uint8_t RESERVED17[3]; + __IO uint8_t ALDOW; + uint8_t RESERVED18[3]; + __IO uint16_t ALDOY; + uint16_t RESERVED19; + __IO uint8_t ALMON; + uint8_t RESERVED20[3]; + __IO uint16_t ALYEAR; + uint16_t RESERVED21; +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint8_t WDMOD; + uint8_t RESERVED0[3]; + __IO uint32_t WDTC; + __O uint8_t WDFEED; + uint8_t RESERVED1[3]; + __I uint32_t WDTV; + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t ADCR; + __IO uint32_t ADGDR; + uint32_t RESERVED0; + __IO uint32_t ADINTEN; + __I uint32_t ADDR0; + __I uint32_t ADDR1; + __I uint32_t ADDR2; + __I uint32_t ADDR3; + __I uint32_t ADDR4; + __I uint32_t ADDR5; + __I uint32_t ADDR6; + __I uint32_t ADDR7; + __I uint32_t ADSTAT; + __IO uint32_t ADTRM; +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +typedef struct +{ + __IO uint32_t DACR; + __IO uint32_t DACCTRL; + __IO uint16_t DACCNTVAL; +} LPC_DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +typedef struct +{ + __I uint32_t MCCON; + __O uint32_t MCCON_SET; + __O uint32_t MCCON_CLR; + __I uint32_t MCCAPCON; + __O uint32_t MCCAPCON_SET; + __O uint32_t MCCAPCON_CLR; + __IO uint32_t MCTIM0; + __IO uint32_t MCTIM1; + __IO uint32_t MCTIM2; + __IO uint32_t MCPER0; + __IO uint32_t MCPER1; + __IO uint32_t MCPER2; + __IO uint32_t MCPW0; + __IO uint32_t MCPW1; + __IO uint32_t MCPW2; + __IO uint32_t MCDEADTIME; + __IO uint32_t MCCCP; + __IO uint32_t MCCR0; + __IO uint32_t MCCR1; + __IO uint32_t MCCR2; + __I uint32_t MCINTEN; + __O uint32_t MCINTEN_SET; + __O uint32_t MCINTEN_CLR; + __I uint32_t MCCNTCON; + __O uint32_t MCCNTCON_SET; + __O uint32_t MCCNTCON_CLR; + __I uint32_t MCINTFLAG; + __O uint32_t MCINTFLAG_SET; + __O uint32_t MCINTFLAG_CLR; + __O uint32_t MCCAP_CLR; +} LPC_MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +typedef struct +{ + __O uint32_t QEICON; + __I uint32_t QEISTAT; + __IO uint32_t QEICONF; + __I uint32_t QEIPOS; + __IO uint32_t QEIMAXPOS; + __IO uint32_t CMPOS0; + __IO uint32_t CMPOS1; + __IO uint32_t CMPOS2; + __I uint32_t INXCNT; + __IO uint32_t INXCMP; + __IO uint32_t QEILOAD; + __I uint32_t QEITIME; + __I uint32_t QEIVEL; + __I uint32_t QEICAP; + __IO uint32_t VELCOMP; + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t QEIIEC; + __O uint32_t QEIIES; + __I uint32_t QEIINTSTAT; + __I uint32_t QEIIE; + __O uint32_t QEICLR; + __O uint32_t QEISET; +} LPC_QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +typedef struct +{ + __IO uint32_t mask[512]; /* ID Masks */ +} LPC_CANAF_RAM_TypeDef; + +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; + __IO uint32_t SFF_sa; + __IO uint32_t SFF_GRP_sa; + __IO uint32_t EFF_sa; + __IO uint32_t EFF_GRP_sa; + __IO uint32_t ENDofTable; + __I uint32_t LUTerrAd; + __I uint32_t LUTerr; + __IO uint32_t FCANIE; + __IO uint32_t FCANIC0; + __IO uint32_t FCANIC1; +} LPC_CANAF_TypeDef; + +typedef struct /* Central Registers */ +{ + __I uint32_t CANTxSR; + __I uint32_t CANRxSR; + __I uint32_t CANMSR; +} LPC_CANCR_TypeDef; + +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; + __O uint32_t CMR; + __IO uint32_t GSR; + __I uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t BTR; + __IO uint32_t EWL; + __I uint32_t SR; + __IO uint32_t RFS; + __IO uint32_t RID; + __IO uint32_t RDA; + __IO uint32_t RDB; + __IO uint32_t TFI1; + __IO uint32_t TID1; + __IO uint32_t TDA1; + __IO uint32_t TDB1; + __IO uint32_t TFI2; + __IO uint32_t TID2; + __IO uint32_t TDA2; + __IO uint32_t TDB2; + __IO uint32_t TFI3; + __IO uint32_t TID3; + __IO uint32_t TDA3; + __IO uint32_t TDB3; +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +typedef struct /* Common Registers */ +{ + __I uint32_t DMACIntStat; + __I uint32_t DMACIntTCStat; + __O uint32_t DMACIntTCClear; + __I uint32_t DMACIntErrStat; + __O uint32_t DMACIntErrClr; + __I uint32_t DMACRawIntTCStat; + __I uint32_t DMACRawIntErrStat; + __I uint32_t DMACEnbldChns; + __IO uint32_t DMACSoftBReq; + __IO uint32_t DMACSoftSReq; + __IO uint32_t DMACSoftLBReq; + __IO uint32_t DMACSoftLSReq; + __IO uint32_t DMACConfig; + __IO uint32_t DMACSync; +} LPC_GPDMA_TypeDef; + +typedef struct /* Channel Registers */ +{ + __IO uint32_t DMACCSrcAddr; + __IO uint32_t DMACCDestAddr; + __IO uint32_t DMACCLLI; + __IO uint32_t DMACCControl; + __IO uint32_t DMACCConfig; +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t HcRevision; /* USB Host Registers */ + __IO uint32_t HcControl; + __IO uint32_t HcCommandStatus; + __IO uint32_t HcInterruptStatus; + __IO uint32_t HcInterruptEnable; + __IO uint32_t HcInterruptDisable; + __IO uint32_t HcHCCA; + __I uint32_t HcPeriodCurrentED; + __IO uint32_t HcControlHeadED; + __IO uint32_t HcControlCurrentED; + __IO uint32_t HcBulkHeadED; + __IO uint32_t HcBulkCurrentED; + __I uint32_t HcDoneHead; + __IO uint32_t HcFmInterval; + __I uint32_t HcFmRemaining; + __I uint32_t HcFmNumber; + __IO uint32_t HcPeriodicStart; + __IO uint32_t HcLSTreshold; + __IO uint32_t HcRhDescriptorA; + __IO uint32_t HcRhDescriptorB; + __IO uint32_t HcRhStatus; + __IO uint32_t HcRhPortStatus1; + __IO uint32_t HcRhPortStatus2; + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; + + __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ + __IO uint32_t OTGIntEn; + __O uint32_t OTGIntSet; + __O uint32_t OTGIntClr; + __IO uint32_t OTGStCtrl; + __IO uint32_t OTGTmr; + uint32_t RESERVED1[58]; + + __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t USBDevIntEn; + __O uint32_t USBDevIntClr; + __O uint32_t USBDevIntSet; + + __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ + __I uint32_t USBCmdData; + + __I uint32_t USBRxData; /* USB Device Transfer Registers */ + __O uint32_t USBTxData; + __I uint32_t USBRxPLen; + __O uint32_t USBTxPLen; + __IO uint32_t USBCtrl; + __O uint32_t USBDevIntPri; + + __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ + __IO uint32_t USBEpIntEn; + __O uint32_t USBEpIntClr; + __O uint32_t USBEpIntSet; + __O uint32_t USBEpIntPri; + + __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ + __O uint32_t USBEpInd; + __IO uint32_t USBMaxPSize; + + __I uint32_t USBDMARSt; /* USB Device DMA Registers */ + __O uint32_t USBDMARClr; + __O uint32_t USBDMARSet; + uint32_t RESERVED2[9]; + __IO uint32_t USBUDCAH; + __I uint32_t USBEpDMASt; + __O uint32_t USBEpDMAEn; + __O uint32_t USBEpDMADis; + __I uint32_t USBDMAIntSt; + __IO uint32_t USBDMAIntEn; + uint32_t RESERVED3[2]; + __I uint32_t USBEoTIntSt; + __O uint32_t USBEoTIntClr; + __O uint32_t USBEoTIntSet; + __I uint32_t USBNDDRIntSt; + __O uint32_t USBNDDRIntClr; + __O uint32_t USBNDDRIntSet; + __I uint32_t USBSysErrIntSt; + __O uint32_t USBSysErrIntClr; + __O uint32_t USBSysErrIntSet; + uint32_t RESERVED4[15]; + + __I uint32_t I2C_RX; /* USB OTG I2C Registers */ + __O uint32_t I2C_WO; + __I uint32_t I2C_STS; + __IO uint32_t I2C_CTL; + __IO uint32_t I2C_CLKHI; + __O uint32_t I2C_CLKLO; + uint32_t RESERVED5[823]; + + union { + __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ + __IO uint32_t OTGClkCtrl; + }; + union { + __I uint32_t USBClkSt; + __I uint32_t OTGClkSt; + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +typedef struct +{ + __IO uint32_t MAC1; /* MAC Registers */ + __IO uint32_t MAC2; + __IO uint32_t IPGT; + __IO uint32_t IPGR; + __IO uint32_t CLRT; + __IO uint32_t MAXF; + __IO uint32_t SUPP; + __IO uint32_t TEST; + __IO uint32_t MCFG; + __IO uint32_t MCMD; + __IO uint32_t MADR; + __O uint32_t MWTD; + __I uint32_t MRDD; + __I uint32_t MIND; + uint32_t RESERVED0[2]; + __IO uint32_t SA0; + __IO uint32_t SA1; + __IO uint32_t SA2; + uint32_t RESERVED1[45]; + __IO uint32_t Command; /* Control Registers */ + __I uint32_t Status; + __IO uint32_t RxDescriptor; + __IO uint32_t RxStatus; + __IO uint32_t RxDescriptorNumber; + __I uint32_t RxProduceIndex; + __IO uint32_t RxConsumeIndex; + __IO uint32_t TxDescriptor; + __IO uint32_t TxStatus; + __IO uint32_t TxDescriptorNumber; + __IO uint32_t TxProduceIndex; + __I uint32_t TxConsumeIndex; + uint32_t RESERVED2[10]; + __I uint32_t TSV0; + __I uint32_t TSV1; + __I uint32_t RSV; + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; + __I uint32_t FlowControlStatus; + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ + __IO uint32_t RxFilterWoLStatus; + __IO uint32_t RxFilterWoLClear; + uint32_t RESERVED5; + __IO uint32_t HashFilterL; + __IO uint32_t HashFilterH; + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /* Module Control Registers */ + __IO uint32_t IntEnable; + __O uint32_t IntClear; + __O uint32_t IntSet; + uint32_t RESERVED7; + __IO uint32_t PowerDown; + uint32_t RESERVED8; + __IO uint32_t Module_ID; +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) + +/* APB0 peripherals */ +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) + +#endif // __LPC17xx_H__
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,277 @@ +;/***************************************************************************** +; * @file: startup_LPC17xx.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the NXP LPC17xx Device Series +; * @version: V1.02 +; * @date: 27. July 2009 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 16: Watchdog Timer + DCD TIMER0_IRQHandler ; 17: Timer0 + DCD TIMER1_IRQHandler ; 18: Timer1 + DCD TIMER2_IRQHandler ; 19: Timer2 + DCD IntLatch_IRQHandler ; 20: Timer3 + DCD UART0_IRQHandler ; 21: UART0 + DCD UART1_IRQHandler ; 22: UART1 + DCD UART2_IRQHandler ; 23: UART2 + DCD UART3_IRQHandler ; 24: UART3 + DCD PWM1_IRQHandler ; 25: PWM1 + DCD I2C0_IRQHandler ; 26: I2C0 + DCD I2C1_IRQHandler ; 27: I2C1 + DCD I2C2_IRQHandler ; 28: I2C2 + DCD SPI_IRQHandler ; 29: SPI + DCD SSP0_IRQHandler ; 30: SSP0 + DCD SSP1_IRQHandler ; 31: SSP1 + DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) + DCD RTC_IRQHandler ; 33: Real Time Clock + DCD EINT0_IRQHandler ; 34: External Interrupt 0 + DCD EINT1_IRQHandler ; 35: External Interrupt 1 + DCD EINT2_IRQHandler ; 36: External Interrupt 2 + DCD EINT3_IRQHandler ; 37: External Interrupt 3 + DCD ADC_IRQHandler ; 38: A/D Converter + DCD BOD_IRQHandler ; 39: Brown-Out Detect + DCD USB_IRQHandler ; 40: USB + DCD CAN_IRQHandler ; 41: CAN + DCD DMA_IRQHandler ; 42: General Purpose DMA + DCD I2S_IRQHandler ; 43: I2S + DCD ENET_IRQHandler ; 44: Ethernet + DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer + DCD MCPWM_IRQHandler ; 46: Motor Control PWM + DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface + DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) + + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT IntLatch_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT PLL0_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT RIT_IRQHandler [WEAK] + EXPORT MCPWM_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] + EXPORT PLL1_IRQHandler [WEAK] + +WDT_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +IntLatch_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PWM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI_IRQHandler +SSP0_IRQHandler +SSP1_IRQHandler +PLL0_IRQHandler +RTC_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +ADC_IRQHandler +BOD_IRQHandler +USB_IRQHandler +CAN_IRQHandler +DMA_IRQHandler +I2S_IRQHandler +ENET_IRQHandler +RIT_IRQHandler +MCPWM_IRQHandler +QEI_IRQHandler +PLL1_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,239 @@ +/*****************************************************************************/ +/* startup_LPC17xx.s: Startup file for LPC17xx device series */ +/*****************************************************************************/ +/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */ +/*****************************************************************************/ + + +/* +//*** <<< Use Configuration Wizard in Context Menu >>> *** +*/ + + +/* +// <h> Stack Configuration +// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + + .equ Stack_Size, 0x00000100 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// <h> Heap Configuration +// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + + .equ Heap_Size, 0x00001000 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long WDT_IRQHandler /* 16: Watchdog Timer */ + .long TIMER0_IRQHandler /* 17: Timer0 */ + .long TIMER1_IRQHandler /* 18: Timer1 */ + .long TIMER2_IRQHandler /* 19: Timer2 */ + .long TIMER3_IRQHandler /* 20: Timer3 */ + .long UART0_IRQHandler /* 21: UART0 */ + .long UART1_IRQHandler /* 22: UART1 */ + .long UART2_IRQHandler /* 23: UART2 */ + .long UART3_IRQHandler /* 24: UART3 */ + .long PWM1_IRQHandler /* 25: PWM1 */ + .long I2C0_IRQHandler /* 26: I2C0 */ + .long I2C1_IRQHandler /* 27: I2C1 */ + .long I2C2_IRQHandler /* 28: I2C2 */ + .long SPI_IRQHandler /* 29: SPI */ + .long SSP0_IRQHandler /* 30: SSP0 */ + .long SSP1_IRQHandler /* 31: SSP1 */ + .long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */ + .long RTC_IRQHandler /* 33: Real Time Clock */ + .long EINT0_IRQHandler /* 34: External Interrupt 0 */ + .long EINT1_IRQHandler /* 35: External Interrupt 1 */ + .long EINT2_IRQHandler /* 36: External Interrupt 2 */ + .long EINT3_IRQHandler /* 37: External Interrupt 3 */ + .long ADC_IRQHandler /* 38: A/D Converter */ + .long BOD_IRQHandler /* 39: Brown-Out Detect */ + .long USB_IRQHandler /* 40: USB */ + .long CAN_IRQHandler /* 41: CAN */ + .long DMA_IRQHandler /* 42: General Purpose DMA */ + .long I2S_IRQHandler /* 43: I2S */ + .long ENET_IRQHandler /* 44: Ethernet */ + .long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */ + .long MCPWM_IRQHandler /* 46: Motor Control PWM */ + .long QEI_IRQHandler /* 47: Quadrature Encoder Interface */ + .long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ WDT_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER3_IRQHandler + IRQ UART0_IRQHandler + IRQ UART1_IRQHandler + IRQ UART2_IRQHandler + IRQ UART3_IRQHandler + IRQ PWM1_IRQHandler + IRQ I2C0_IRQHandler + IRQ I2C1_IRQHandler + IRQ I2C2_IRQHandler + IRQ SPI_IRQHandler + IRQ SSP0_IRQHandler + IRQ SSP1_IRQHandler + IRQ PLL0_IRQHandler + IRQ RTC_IRQHandler + IRQ EINT0_IRQHandler + IRQ EINT1_IRQHandler + IRQ EINT2_IRQHandler + IRQ EINT3_IRQHandler + IRQ ADC_IRQHandler + IRQ BOD_IRQHandler + IRQ USB_IRQHandler + IRQ CAN_IRQHandler + IRQ DMA_IRQHandler + IRQ I2S_IRQHandler + IRQ ENET_IRQHandler + IRQ RIT_IRQHandler + IRQ MCPWM_IRQHandler + IRQ QEI_IRQHandler + IRQ PLL1_IRQHandler + + .end
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,341 @@ +;/***************************************************************************** +; * @file: startup_LPC17xx.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the NXP LPC17xx Device Series +; * @version: V1.02 +; * @date: 31. July 2009 +; *---------------------------------------------------------------------------- +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * +; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 16: Watchdog Timer + DCD TIMER0_IRQHandler ; 17: Timer0 + DCD TIMER1_IRQHandler ; 18: Timer1 + DCD TIMER2_IRQHandler ; 19: Timer2 + DCD TIMER3_IRQHandler ; 20: Timer3 + DCD UART0_IRQHandler ; 21: UART0 + DCD UART1_IRQHandler ; 22: UART1 + DCD UART2_IRQHandler ; 23: UART2 + DCD UART3_IRQHandler ; 24: UART3 + DCD PWM1_IRQHandler ; 25: PWM1 + DCD I2C0_IRQHandler ; 26: I2C0 + DCD I2C1_IRQHandler ; 27: I2C1 + DCD I2C2_IRQHandler ; 28: I2C2 + DCD SPI_IRQHandler ; 29: SPI + DCD SSP0_IRQHandler ; 30: SSP0 + DCD SSP1_IRQHandler ; 31: SSP1 + DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) + DCD RTC_IRQHandler ; 33: Real Time Clock + DCD EINT0_IRQHandler ; 34: External Interrupt 0 + DCD EINT1_IRQHandler ; 35: External Interrupt 1 + DCD EINT2_IRQHandler ; 36: External Interrupt 2 + DCD EINT3_IRQHandler ; 37: External Interrupt 3 + DCD ADC_IRQHandler ; 38: A/D Converter + DCD BOD_IRQHandler ; 39: Brown-Out Detect + DCD USB_IRQHandler ; 40: USB + DCD CAN_IRQHandler ; 41: CAN + DCD DMA_IRQHandler ; 42: General Purpose DMA + DCD I2S_IRQHandler ; 43: I2S + DCD ENET_IRQHandler ; 44: Ethernet + DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer + DCD MCPWM_IRQHandler ; 46: Motor Control PWM + DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface + DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK PWM1_IRQHandler + SECTION .text:CODE:REORDER(1) +PWM1_IRQHandler + B PWM1_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI_IRQHandler + SECTION .text:CODE:REORDER(1) +SPI_IRQHandler + B SPI_IRQHandler + + PUBWEAK SSP0_IRQHandler + SECTION .text:CODE:REORDER(1) +SSP0_IRQHandler + B SSP0_IRQHandler + + PUBWEAK SSP1_IRQHandler + SECTION .text:CODE:REORDER(1) +SSP1_IRQHandler + B SSP1_IRQHandler + + PUBWEAK PLL0_IRQHandler + SECTION .text:CODE:REORDER(1) +PLL0_IRQHandler + B PLL0_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK EINT0_IRQHandler + SECTION .text:CODE:REORDER(1) +EINT0_IRQHandler + B EINT0_IRQHandler + + PUBWEAK EINT1_IRQHandler + SECTION .text:CODE:REORDER(1) +EINT1_IRQHandler + B EINT1_IRQHandler + + PUBWEAK EINT2_IRQHandler + SECTION .text:CODE:REORDER(1) +EINT2_IRQHandler + B EINT2_IRQHandler + + PUBWEAK EINT3_IRQHandler + SECTION .text:CODE:REORDER(1) +EINT3_IRQHandler + B EINT3_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK BOD_IRQHandler + SECTION .text:CODE:REORDER(1) +BOD_IRQHandler + B BOD_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK CAN_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN_IRQHandler + B CAN_IRQHandler + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK I2S_IRQHandler + SECTION .text:CODE:REORDER(1) +I2S_IRQHandler + B I2S_IRQHandler + + PUBWEAK ENET_IRQHandler + SECTION .text:CODE:REORDER(1) +ENET_IRQHandler + B ENET_IRQHandler + + PUBWEAK RIT_IRQHandler + SECTION .text:CODE:REORDER(1) +RIT_IRQHandler + B RIT_IRQHandler + + PUBWEAK MCPWM_IRQHandler + SECTION .text:CODE:REORDER(1) +MCPWM_IRQHandler + B MCPWM_IRQHandler + + PUBWEAK QEI_IRQHandler + SECTION .text:CODE:REORDER(1) +QEI_IRQHandler + B QEI_IRQHandler + + PUBWEAK PLL1_IRQHandler + SECTION .text:CODE:REORDER(1) +PLL1_IRQHandler + B PLL1_IRQHandler + + END
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,539 @@ +/**************************************************************************//** + * @file system_LPC17xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the NXP LPC17xx Device Series + * @version V1.03 + * @date 07. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include <stdint.h> +#include "LPC17xx.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ---------------------------------- +// +// <e> Clock Configuration +// <h> System Controls and Status Register (SCS) +// <o1.4> OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 24 MHz +// <e1.5> OSCEN: Main Oscillator Enable +// </e> +// </h> +// +// <h> Clock Source Select Register (CLKSRCSEL) +// <o2.0..1> CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// </h> +// +// <e3> PLL0 Configuration (Main PLL) +// <h> PLL0 Configuration Register (PLL0CFG) +// <i> F_cco0 = (2 * M * F_in) / N +// <i> F_in must be in the range of 32 kHz to 50 MHz +// <i> F_cco0 must be in the range of 275 MHz to 550 MHz +// <o4.0..14> MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// <i> M Value +// <o4.16..23> NSEL: PLL Divider Selection +// <1-256><#-1> +// <i> N Value +// </h> +// </e> +// +// <e5> PLL1 Configuration (USB PLL) +// <h> PLL1 Configuration Register (PLL1CFG) +// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// <i> F_cco1 = F_osc * M * 2 * P +// <i> F_cco1 must be in the range of 156 MHz to 320 MHz +// <o6.0..4> MSEL: PLL Multiplier Selection +// <1-32><#-1> +// <i> M Value (for USB maximum value is 4) +// <o6.5..6> PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <i> P Value +// </h> +// </e> +// +// <h> CPU Clock Configuration Register (CCLKCFG) +// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 +// <3-256><#-1> +// </h> +// +// <h> USB Clock Configuration Register (USBCLKCFG) +// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 +// <0-15> +// <i> Divide is USBSEL + 1 +// </h> +// +// <h> Peripheral Clock Selection Register 0 (PCLKSEL0) +// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// </h> +// +// <h> Peripheral Clock Selection Register 1 (PCLKSEL1) +// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// </h> +// +// <h> Power Control for Peripherals Register (PCONP) +// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable +// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable +// <o11.3> PCUART0: UART 0 power/clock enable +// <o11.4> PCUART1: UART 1 power/clock enable +// <o11.6> PCPWM1: PWM 1 power/clock enable +// <o11.7> PCI2C0: I2C interface 0 power/clock enable +// <o11.8> PCSPI: SPI interface power/clock enable +// <o11.9> PCRTC: RTC power/clock enable +// <o11.10> PCSSP1: SSP interface 1 power/clock enable +// <o11.12> PCAD: A/D converter power/clock enable +// <o11.13> PCCAN1: CAN controller 1 power/clock enable +// <o11.14> PCCAN2: CAN controller 2 power/clock enable +// <o11.15> PCGPIO: GPIOs power/clock enable +// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable +// <o11.17> PCMC: Motor control PWM power/clock enable +// <o11.18> PCQEI: Quadrature encoder interface power/clock enable +// <o11.19> PCI2C1: I2C interface 1 power/clock enable +// <o11.21> PCSSP0: SSP interface 0 power/clock enable +// <o11.22> PCTIM2: Timer 2 power/clock enable +// <o11.23> PCTIM3: Timer 3 power/clock enable +// <o11.24> PCUART2: UART 2 power/clock enable +// <o11.25> PCUART3: UART 3 power/clock enable +// <o11.26> PCI2C2: I2C interface 2 power/clock enable +// <o11.27> PCI2S: I2S interface power/clock enable +// <o11.29> PCGPDMA: GP DMA function power/clock enable +// <o11.30> PCENET: Ethernet block power/clock enable +// <o11.31> PCUSB: USB interface power/clock enable +// </h> +// +// <h> Clock Output Configuration Register (CLKOUTCFG) +// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT +// <0=> CPU clock +// <1=> Main oscillator +// <2=> Internal RC oscillator +// <3=> USB clock +// <4=> RTC oscillator +// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT +// <1-16><#-1> +// <o12.8> CLKOUT_EN: CLKOUT enable control +// </h> +// +// </e> +*/ +#define CLOCK_SETUP 1 +#define SCS_Val 0x00000020 +#define CLKSRCSEL_Val 0x00000001 +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x00050063 +#define PLL1_SETUP 1 +#define PLL1CFG_Val 0x00000023 +#define CCLKCFG_Val 0x00000003 +#define USBCLKCFG_Val 0x00000000 +#define PCLKSEL0_Val 0x00000010 +#define PCLKSEL1_Val 0x00000000 +#define PCONP_Val 0x046887DE +#define CLKOUTCFG_Val 0x00000000 + + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// <e> Flash Accelerator Configuration +// <o1.0..1> FETCHCFG: Fetch Configuration +// <0=> Instruction fetches from flash are not buffered +// <1=> One buffer is used for all instruction fetch buffering +// <2=> All buffers may be used for instruction fetch buffering +// <3=> Reserved (do not use this setting) +// <o1.2..3> DATACFG: Data Configuration +// <0=> Data accesses from flash are not buffered +// <1=> One buffer is used for all data access buffering +// <2=> All buffers may be used for data access buffering +// <3=> Reserved (do not use this setting) +// <o1.4> ACCEL: Acceleration Enable +// <o1.5> PREFEN: Prefetch Enable +// <o1.6> PREFOVR: Prefetch Override +// <o1.12..15> FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// </e> +*/ +#define FLASH_SETUP 1 +#define FLASHCFG_Val 0x0000303A + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SCS_Val), ~0x00000030)) + #error "SCS: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) + #error "CLKSRCSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) + #error "PLL0CFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) + #error "PLL1CFG: Invalid values of reserved bits!" +#endif + +#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) + #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" +#endif + +#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) + #error "USBCLKCFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) + #error "PCLKSEL0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) + #error "PCLKSEL1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCONP_Val), 0x10100821)) + #error "PCONP: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) + #error "CLKOUTCFG: Invalid values of reserved bits!" +#endif + +/* Flash Accelerator Configuration -------------------------------------------*/ +#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) + #error "FLASHCFG: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + + +/* F_cco0 = (2 * M * F_in) / N */ +#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) +#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) +#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) +#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) + +/* Determine core clock frequency according to settings */ + #if (PLL0_SETUP) + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) + #else + #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) + #endif + #else + #if ((CLKSRCSEL_Val & 0x03) == 1) + #define __CORE_CLK (OSC_CLK / __CCLK_DIV) + #elif ((CLKSRCSEL_Val & 0x03) == 2) + #define __CORE_CLK (RTC_CLK / __CCLK_DIV) + #else + #define __CORE_CLK (IRC_OSC / __CCLK_DIV) + #endif + #endif + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = (IRC_OSC * + ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = (OSC_CLK * //it is our case osc_clk = 12 MHz + ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / //PLL0 multiplier value + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / //PLL0 pre-divider + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); //divider for CCLK (SystemCoreClock) + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = (RTC_CLK * + ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + break; + } + } else { + switch (LPC_SC->CLKSRCSEL & 0x03) { + case 0: /* Int. RC oscillator => PLL0 */ + case 3: /* Reserved, default to Int. RC */ + SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 1: /* Main oscillator => PLL0 */ + SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + case 2: /* RTC oscillator => PLL0 */ + SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); + break; + } + } + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if (CLOCK_SETUP) /* Clock Setup */ + LPC_SC->SCS = SCS_Val; + if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ + } + + LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + +#if (PLL0_SETUP) + LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ + + LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + + LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ + + LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ + LPC_SC->PLL0FEED = 0xAA; + LPC_SC->PLL0FEED = 0x55; + while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ +#endif + +#if (PLL1_SETUP) + LPC_SC->PLL1CFG = PLL1CFG_Val; + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + + LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ + + LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ + LPC_SC->PLL1FEED = 0xAA; + LPC_SC->PLL1FEED = 0x55; + while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ +#else + LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ +#endif + + LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ + LPC_SC->PCLKSEL1 = PCLKSEL1_Val; + + LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ + + LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ +#endif + +#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ + LPC_SC->FLASHCFG = FLASHCFG_Val; +#endif +}
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_LPC17xx.h + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the NXP LPC17xx Device Series + * @version V1.02 + * @date 08. September 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC17xx_H +#define __SYSTEM_LPC17xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC17xx_H */
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CMSIS changes.htm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CMSIS changes.htm Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,320 @@ +<html> + +<head> +<title>CMSIS Changes</title> +<meta http-equiv="Content-Type" content="text/html; charset=windows-1252"> +<meta name="GENERATOR" content="Microsoft FrontPage 6.0"> +<meta name="ProgId" content="FrontPage.Editor.Document"> +<style> +<!-- +/*----------------------------------------------------------- +Keil Software CHM Style Sheet +-----------------------------------------------------------*/ +body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: + Verdana, Arial, 'Sans Serif' } +a:link { color: #0000FF; text-decoration: underline } +a:visited { color: #0000FF; text-decoration: underline } +a:active { color: #FF0000; text-decoration: underline } +a:hover { color: #FF0000; text-decoration: underline } +h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; + text-align: Center; margin-right: 3 } +h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; + background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; + padding: 6 } +h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: + #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 } +pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; + margin-left: 24; margin-right: 24 } +ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 } +ol { margin-top: 6pt; margin-bottom: 0 } +li { clear: both; margin-bottom: 6pt } +table { font-size: 100%; border-width: 0; padding: 0 } +th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: + bottom; padding-right: 6pt } +tr { text-align: left; vertical-align: top } +td { text-align: left; vertical-align: top; padding-right: 6pt } +.ToolT { font-size: 8pt; color: #808080 } +.TinyT { font-size: 8pt; text-align: Center } +code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; + line-height: 120%; font-style: normal } +/*----------------------------------------------------------- +Notes +-----------------------------------------------------------*/ +p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt } +/*----------------------------------------------------------- +Expanding/Contracting Divisions +-----------------------------------------------------------*/ +#expand { text-decoration: none; margin-bottom: 3pt } +img.expand { border-style: none; border-width: medium } +div.expand { display: none; margin-left: 9pt; margin-top: 0 } +/*----------------------------------------------------------- +Where List Tags +-----------------------------------------------------------*/ +p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt } +table.wh { width: 100% } +td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: + 6pt } +td.whDesc { padding-bottom: 6pt } +/*----------------------------------------------------------- +Keil Table Tags +-----------------------------------------------------------*/ +table.kt { border: 1pt solid #000000 } +th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; + padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt } +tr.kt { } +td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; + padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; + padding-bottom: 2pt } +/*----------------------------------------------------------- +-----------------------------------------------------------*/ +--> + +</style> +</head> + +<body> + +<h1>Changes to CMSIS version V1.20</h1> + +<hr> + +<h2>1. Removed CMSIS Middelware packages</h2> +<p> + CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. +</p> + +<h2>2. SystemFrequency renamed to SystemCoreClock</h2> +<p> + The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong> + because the variable holds the clock value at which the core is running. +</p> + +<h2>3. Changed startup concept</h2> +<p> + The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit + from main) has the weakness that it does not work for controllers which need a already + configuerd clock system to configure the external memory controller. +</p> + +<h3>Changed startup concept</h3> +<ul> + <li> + SystemInit() is called from startup file before <strong>premain</strong>. + </li> + <li> + <strong>SystemInit()</strong> configures the clock system and also configures + an existing external memory controller. + </li> + <li> + <strong>SystemInit()</strong> must not use global variables. + </li> + <li> + <strong>SystemCoreClock</strong> is initialized with a correct predefined value. + </li> + <li> + Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br> + <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong> + and must be called whenever the core clock is changed.<br> + <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates + the current core clock. + </li> +</ul> + + +<h2>4. Advanced Debug Functions</h2> +<p> + ITM communication channel is only capable for OUT direction. To allow also communication for + IN direction a simple concept is provided. +</p> +<ul> + <li> + Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data. + </li> + <li> + Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available. + </li> + <li> + Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character. + </li> +</ul> + +<p> + For detailed explanation see file <strong>CMSIS debug support.htm</strong>. +</p> + + +<h2>5. Core Register Bit Definitions</h2> +<p> + Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the + defines correspond with the Cortex-M Technical Reference Manual. +</p> +<p> + e.g. SysTick structure with bit definitions +</p> +<pre> +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre> + +<h2>7. DoxyGen Tags</h2> +<p> + DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation + using DoxyGen. +</p> + +<h2>8. Folder Structure</h2> +<p> + The folder structure is changed to differentiate the single support packages. +</p> + + <ul> + <li>CM0</li> + <li>CM3 + <ul> + <li>CoreSupport</li> + <li>DeviceSupport</li> + <ul> + <li>Vendor + <ul> + <li>Device + <ul> + <li>Startup + <ul> + <li>Toolchain</li> + <li>Toolchain</li> + <li>...</li> + </ul> + </li> + </ul> + </li> + <li>Device</li> + <li>...</li> + </ul> + </li> + <li>Vendor</li> + <li>...</li> + </ul> + </li> + <li>Example + <ul> + <li>Toolchain + <ul> + <li>Device</li> + <li>Device</li> + <li>...</li> + </ul> + </li> + <li>Toolchain</li> + <li>...</li> + </ul> + </li> + </ul> + </li> + + <li>Documentation</li> + </ul> + +<h2>9. Open Points</h2> +<p> + Following points need to be clarified and solved: +</p> +<ul> + <li> + <p> + Equivalent C and Assembler startup files. + </p> + <p> + Is there a need for having C startup files although assembler startup files are + very efficient and do not need to be changed? + <p/> + </li> + <li> + <p> + Placing of HEAP in external RAM. + </p> + <p> + It must be possible to place HEAP in external RAM if the device supports an + external memory controller. + </p> + </li> + <li> + <p> + Placing of STACK /HEAP. + </p> + <p> + STACK should always be placed at the end of internal RAM. + </p> + <p> + If HEAP is placed in internal RAM than it should be placed after RW ZI section. + </p> + </li> + <li> + <p> + Removing core_cm3.c and core_cm0.c. + </p> + <p> + On a long term the functions in core_cm3.c and core_cm0.c must be replaced with + appropriate compiler intrinsics. + </p> + </li> +</ul> + + +<h2>10. Limitations</h2> +<p> + The following limitations are not covered with the current CMSIS version: +</p> +<ul> + <li> + No <strong>C startup files</strong> for ARM toolchain are provided. + </li> + <li> + No <strong>C startup files</strong> for GNU toolchain are provided. + </li> + <li> + No <strong>C startup files</strong> for IAR toolchain are provided. + </li> + <li> + No <strong>Tasking</strong> projects are provided yet. + </li> +</ul>
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/CMSIS debug support.htm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/CMSIS debug support.htm Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,243 @@ +<html> + +<head> +<title>CMSIS Debug Support</title> +<meta http-equiv="Content-Type" content="text/html; charset=windows-1252"> +<meta name="GENERATOR" content="Microsoft FrontPage 6.0"> +<meta name="ProgId" content="FrontPage.Editor.Document"> +<style> +<!-- +/*----------------------------------------------------------- +Keil Software CHM Style Sheet +-----------------------------------------------------------*/ +body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: + Verdana, Arial, 'Sans Serif' } +a:link { color: #0000FF; text-decoration: underline } +a:visited { color: #0000FF; text-decoration: underline } +a:active { color: #FF0000; text-decoration: underline } +a:hover { color: #FF0000; text-decoration: underline } +h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; + text-align: Center; margin-right: 3 } +h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; + background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; + padding: 6 } +h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: + #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 } +pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; + margin-left: 24; margin-right: 24 } +ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 } +ol { margin-top: 6pt; margin-bottom: 0 } +li { clear: both; margin-bottom: 6pt } +table { font-size: 100%; border-width: 0; padding: 0 } +th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: + bottom; padding-right: 6pt } +tr { text-align: left; vertical-align: top } +td { text-align: left; vertical-align: top; padding-right: 6pt } +.ToolT { font-size: 8pt; color: #808080 } +.TinyT { font-size: 8pt; text-align: Center } +code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; + line-height: 120%; font-style: normal } +/*----------------------------------------------------------- +Notes +-----------------------------------------------------------*/ +p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt } +/*----------------------------------------------------------- +Expanding/Contracting Divisions +-----------------------------------------------------------*/ +#expand { text-decoration: none; margin-bottom: 3pt } +img.expand { border-style: none; border-width: medium } +div.expand { display: none; margin-left: 9pt; margin-top: 0 } +/*----------------------------------------------------------- +Where List Tags +-----------------------------------------------------------*/ +p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt } +table.wh { width: 100% } +td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: + 6pt } +td.whDesc { padding-bottom: 6pt } +/*----------------------------------------------------------- +Keil Table Tags +-----------------------------------------------------------*/ +table.kt { border: 1pt solid #000000 } +th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; + padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt } +tr.kt { } +td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; + padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; + padding-bottom: 2pt } +/*----------------------------------------------------------- +-----------------------------------------------------------*/ +--> + +</style> +</head> + +<body> + +<h1>CMSIS Debug Support</h1> + +<hr> + +<h2>Cortex-M3 ITM Debug Access</h2> +<p> + The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with + the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has + 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM + communication channels are used by CMSIS to output the following information: +</p> +<ul> + <li>ITM Channel 0: used for printf-style output via the debug interface.</li> + <li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li> +</ul> + +<h2>Debug IN / OUT functions</h2> +<p>CMSIS provides following debug functions:</p> +<ul> + <li>ITM_SendChar (uses ITM channel 0)</li> + <li>ITM_ReceiveChar (uses global variable)</li> + <li>ITM_CheckChar (uses global variable)</li> +</ul> + +<h3>ITM_SendChar</h3> +<p> + <strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from + the microcontroller system to the debug system. <br> + Only a 8 bit value is transmitted. +</p> +<pre> +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + /* check if debugger connected and ITM channel enabled for tracing */ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && + (ITM->TCR & ITM_TCR_ITMENA) && + (ITM->TER & (1UL << 0)) ) + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +}</pre> + +<h3>ITM_ReceiveChar</h3> +<p> + ITM communication channel is only capable for OUT direction. For IN direction + a globel variable is used. A simple mechansim detects if a character is received. + The project to test need to be build with debug information. +</p> + +<p> + The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system + to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake. +</p> +<pre> +extern volatile int ITM_RxBuffer; /* variable to receive characters */ +</pre> +<p> + A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty + or contains a valid value. +</p> +<pre> +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */ +</pre> +<p> + <strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking. + It returns the received character or '-1' if no character was available. +</p> +<pre> +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} +</pre> + +<h3>ITM_CheckChar</h3> +<p> + <strong>ITM_CheckChar</strong> is used to check if a character is received. +</p> +<pre> +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +}</pre> + + +<h2>ITM Debug Support in uVision</h2> +<p> + uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to + display the debug data. +</p> +<p>Direction microcontroller system -> uVision:</p> +<ul> + <li> + Characters received via ITM communication channel 0 are written in a printf style + to <strong>Debug (printf) Viewer</strong> window. + </li> +</ul> + +<p>Direction uVision -> microcontroller system:</p> +<ul> + <li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li> + <li>Read character from <strong>Debug (printf) Viewer</strong> window.</li> + <li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li> +</ul> + +<p class="Note">Note</p> +<ul> + <li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p> + </li> +</ul> + +<h2>RTX Kernel awareness in uVision</h2> +<p> + uVision / RTX are using a simple and efficient solution for RTX Kernel awareness. + No format overhead is necessary.<br> + uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access + to ITM communication channel 31. +</p> + +<p>Following RTX events are traced:</p> +<ul> + <li>Task Create / Delete event + <ol> + <li>32 bit access. Task start address is transmitted</li> + <li>16 bit access. Task ID and Create/Delete flag are transmitted<br> + High byte holds Create/Delete flag, Low byte holds TASK ID. + </li> + </ol> + </li> + <li>Task switch event + <ol> + <li>8 bit access. Task ID of current task is transmitted</li> + </ol> + </li> +</ul> + +<p class="Note">Note</p> +<ul> + <li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p> + </li> +</ul> + + +<p class="MsoNormal"><span lang="EN-GB"> </span></p> + +<hr> + +<p class="TinyT">Copyright © KEIL - An ARM Company.<br> +All rights reserved.<br> +Visit our web site at <a href="http://www.keil.com">www.keil.com</a>. +</p> + +</body> + +</html> \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/Documentation/CMSIS_Core.htm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/CMSIS/Documentation/CMSIS_Core.htm Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,1337 @@ +<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> +<html xmlns:p="urn:schemas-microsoft-com:office:powerpoint" xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office"><head> + + <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252"> + <meta name="ProgId" content="FrontPage.Editor.Document"> + <style> +<!-- +/*-----------------------------------------------------------Keil Software CHM Style Sheet +-----------------------------------------------------------*/ +body { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: Verdana, Arial, 'Sans Serif' } +a:link { color: #0000FF; text-decoration: underline } +a:visited { color: #0000FF; text-decoration: underline } +a:active { color: #FF0000; text-decoration: underline } +a:hover { color: #FF0000; text-decoration: underline } +h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; text-align: Center; margin-right: 3 } +h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 } +h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 } +pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; margin-left: 24; margin-right: 24 } +ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 } +ol { margin-top: 6pt; margin-bottom: 0 } +li { clear: both; margin-bottom: 6pt } +table { font-size: 100%; border-width: 0; padding: 0 } +th { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: bottom; padding-right: 6pt } +tr { text-align: left; vertical-align: top } +td { text-align: left; vertical-align: top; padding-right: 6pt } +.ToolT { font-size: 8pt; color: #808080 } +.TinyT { font-size: 8pt; text-align: Center } +code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; line-height: 120%; font-style: normal } +/*-----------------------------------------------------------Notes +-----------------------------------------------------------*/ +p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt } +/*-----------------------------------------------------------Expanding/Contracting Divisions +-----------------------------------------------------------*/ +#expand { text-decoration: none; margin-bottom: 3pt } +img.expand { border-style: none; border-width: medium } +div.expand { display: none; margin-left: 9pt; margin-top: 0 } +/*-----------------------------------------------------------Where List Tags +-----------------------------------------------------------*/ +p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt } +table.wh { width: 100% } +td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: 6pt } +td.whDesc { padding-bottom: 6pt } +/*-----------------------------------------------------------Keil Table Tags +-----------------------------------------------------------*/ +table.kt { width: 100%; border: 1pt solid #000000 } +th.kt { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt } +tr.kt { } +td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; padding-bottom: 2pt } +/*----------------------------------------------------------------------------------------------------------------------*/ + .style1 { + background-color: #E0E0E0; +} +.O + {color:#1D315B; + font-size:149%;} + --> + </style></head> +<body> +<h1>Cortex Microcontroller Software Interface Standard</h1> + +<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p> +<p align="center">Version: 1.30 - 30. October 2009</p> + +<p class="TinyT">Information in this file, the accompany manuals, and software is<br> + Copyright © ARM Ltd.<br>All rights reserved. +</p> + +<hr> + +<p><span style="FONT-WEIGHT: bold">Revision History</span></p> +<ul> + <li>Version 1.00: initial release. </li> + <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li> + <li>Version 1.02: added Cortex-M0. </li> + <li>Version 1.10: second review. </li> + <li>Version 1.20: third review. </li> + <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li> + <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li> + <li>Version 1.30: updated Device Support Packages.</li> +</ul> + +<hr> + +<h2>Contents</h2> + +<ol> + <li class="LI2"><a href="#1">About</a></li> + <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li> + <li class="LI2"><a href="#3">CMSIS Files</a></li> + <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li> + <li class="LI2"><a href="#5">CMSIS Example</a></li> +</ol> + +<h2><a name="1"></a>About</h2> + +<p> + The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges + that are faced when software components are deployed to physical microcontroller devices based on a + Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M + processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation + with various silicon and software vendors and provides a common approach to interface to peripherals, + real-time operating systems, and middleware components. +</p> + +<p>ARM provides as part of the CMSIS the following software layers that are +available for various compiler implementations:</p> +<ul> + <li><strong>Core Peripheral Access Layer</strong>: contains name definitions, + address definitions and helper functions to + access core registers and peripherals. It defines also a device + independent interface for RTOS Kernels that includes debug channel + definitions.</li> +</ul> + +<p>These software layers are expanded by Silicon partners with:</p> +<ul> + <li><strong>Device Peripheral Access Layer</strong>: provides definitions + for all device peripherals</li> + <li><strong>Access Functions for Peripherals (optional)</strong>: provides + additional helper functions for peripherals</li> +</ul> + +<p>CMSIS defines for a Cortex-M Microcontroller System:</p> +<ul> + <li style="text-align: left;">A common way to access peripheral registers + and a common way to define exception vectors.</li> + <li style="text-align: left;">The register names of the <strong>Core + Peripherals</strong> and<strong> </strong>the names of the <strong>Core + Exception Vectors</strong>.</li> + <li>An device independent interface for RTOS Kernels including a debug + channel.</li> +</ul> + +<p> + By using CMSIS compliant software components, the user can easier re-use template code. + CMSIS is intended to enable the combination of software components from multiple middleware vendors. +</p> + +<h2><a name="2"></a>Coding Rules and Conventions</h2> + +<p> + The following section describes the coding rules and conventions used in the CMSIS + implementation. It contains also information about data types and version number information. +</p> + +<h3>Essentials</h3> +<ul> + <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, + there are disable and enable sequences for PC-LINT inserted.</li> + <li>ANSI standard data types defined in the ANSI C header file + <strong><stdint.h></strong> are used.</li> + <li>#define constants that include expressions must be enclosed by + parenthesis.</li> + <li>Variables and parameters have a complete data type.</li> + <li>All functions in the <strong>Core Peripheral Access Layer</strong> are + re-entrant.</li> + <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code + (which means that wait/query loops are done at other software layers).</li> + <li>For each exception/interrupt there is definition for: + <ul> + <li>an exception/interrupt handler with the postfix <strong>_Handler </strong> + (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li> + <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li> + <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li> + </ul></li> +</ul> + +<h3>Recommendations</h3> + +<p>The CMSIS recommends the following conventions for identifiers.</p> +<ul> + <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li> + <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li> + <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li> + <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li> +</ul> + +<b>Comments</b> + +<ul> + <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style + (<em>// comment</em>). It is assumed that the programming tools support today + consistently the C++ comment style.</li> + <li><strong>Function Comments</strong> provide for each function the following information: + <ul> + <li>one-line brief function overview.</li> + <li>detailed parameter explanation.</li> + <li>detailed information about return values.</li> + <li>detailed description of the actual function.</li> + </ul> + <p><b>Doxygen Example:</b></p> + <pre> +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * @param IRQn interrupt number that specifies the interrupt + * @return none. + * Enable the specified interrupt in the NVIC Interrupt Controller. + * Other settings of the interrupt such as priority are not affected. + */</pre> + </li> +</ul> + +<h3>Data Types and IO Type Qualifiers</h3> + +<p> + The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file + <strong><stdint.h></strong>. <strong>IO Type Qualifiers</strong> are used to specify the access + to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of + debug information of peripheral registers. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">IO Type Qualifier</th> + <th class="kt">#define</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">__I</td> + <td class="kt">volatile const</td> + <td class="kt">Read access only</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">__O</td> + <td class="kt">volatile</td> + <td class="kt">Write access only</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">__IO</td> + <td class="kt">volatile</td> + <td class="kt">Read and write access</td> + </tr> + </tbody> +</table> + +<h3>CMSIS Version Number</h3> +<p> + File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define: +</p> + +<pre> +#define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)</pre> + +<p> + File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define: +</p> + +<pre> +#define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */ +#define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)</pre> + + +<h3>CMSIS Cortex Core</h3> +<p> + File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define: +</p> + +<pre> +#define __CORTEX_M (0x03)</pre> + +<p> + File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define: +</p> + +<pre> +#define __CORTEX_M (0x00)</pre> + + +<h2><a name="3"></a>CMSIS Files</h2> +<p> + This section describes the Files provided in context with the CMSIS to access the Cortex-M + hardware and peripherals. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">File</th> + <th class="kt">Provider</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap"><i>device.h</i></td> + <td class="kt">Device specific (provided by silicon partner)</td> + <td class="kt">Defines the peripherals for the actual device. The file may use + several other include files to define the peripherals of the actual device.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">core_cm0.h</td> + <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> + <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">core_cm3.h</td> + <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> + <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">core_cm0.c</td> + <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> + <td class="kt">Provides helper functions that access core registers.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">core_cm3.c</td> + <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td> + <td class="kt">Provides helper functions that access core registers.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">startup<i>_device</i></td> + <td class="kt">ARM (adapted by compiler partner / silicon partner)</td> + <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">system<i>_device</i></td> + <td class="kt">ARM (adapted by silicon partner)</td> + <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes + typically the oscillator (PLL) that is part of the microcontroller device</td> + </tr> + </tbody> +</table> + +<h3><em>device.h</em></h3> + +<p> + The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the + <u><strong>central include file</strong></u> that the application programmer is using in + the C source code. This file contains: +</p> +<ul> + <li> + <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers + (IRQn) for all core and device specific exceptions and interrupts.</p> + </li> + <li> + <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the + actual configuration of the Cortex-M processor that is part of the actual + device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that + implements access to processor registers and core peripherals. </p> + </li> + <li> + <p><strong>Device Peripheral Access Layer</strong>: provides definitions + for all device peripherals. It contains all data structures and the address + mapping for the device specific peripherals. </p> + </li> + <li><strong>Access Functions for Peripherals (optional)</strong>: provides + additional helper functions for peripherals that are useful for programming + of these peripherals. Access Functions may be provided as inline functions + or can be extern references to a device specific library provided by the + silicon vendor.</li> +</ul> + + +<h4><strong>Interrupt Number Definition</strong></h4> + +<p>To access the device specific interrupts the device.h file defines IRQn +numbers for the complete device using a enum typedef as shown below:</p> +<pre> +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ****************************************************************/ + WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + : + : + } IRQn_Type;</pre> + + +<h4>Configuration for core_cm0.h / core_cm3.h</h4> +<p> + The Cortex-M core configuration options which are defined for each device implementation. Some + configuration options are reflected in the CMSIS layer using the #define settings described below. +</p> +<p> + To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>. + Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be + defined before <strong>#include <core_cm0.h></strong> / <strong>#include <core_cm3.h></strong> + preprocessor command. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">#define</th> + <th class="kt" nowrap="nowrap">File</th> + <th class="kt" nowrap="nowrap">Value</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td> + <td class="kt">core_cm0.h</td> + <td class="kt" nowrap="nowrap">(2)</td> + <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td> + <td class="kt">core_cm3.h</td> + <td class="kt" nowrap="nowrap">(2 ... 8)</td> + <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">__MPU_PRESENT</td> + <td class="kt">core_cm0.h, core_cm3.h</td> + <td class="kt" nowrap="nowrap">(0, 1)</td> + <td class="kt">Defines if an MPU is present or not</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td> + <td class="kt">core_cm0.h, core_cm3.h</td> + <td class="kt" nowrap="nowrap">(1)</td> + <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function + in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em> + file must contain a vendor specific implementation of this function.</td> + </tr> + </tbody> +</table> + + +<h4>Device Peripheral Access Layer</h4> +<p> + Each peripheral uses a prefix which consists of <strong><device abbreviation>_</strong> + and <strong><peripheral name>_</strong> to identify peripheral registers that access this + specific peripheral. The intention of this is to avoid name collisions caused + due to short names. If more than one peripheral of the same type exists, + identifiers have a postfix (digit or letter). For example: +</p> +<ul> + <li><device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device. + <pre> +typedef struct +{ + union { + __I uint8_t RBR; /*!< Offset: 0x000 Receiver Buffer Register */ + __O uint8_t THR; /*!< Offset: 0x000 Transmit Holding Register */ + __IO uint8_t DLL; /*!< Offset: 0x000 Divisor Latch LSB */ + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; /*!< Offset: 0x004 Divisor Latch MSB */ + __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register */ + __O uint8_t FCR; /*!< Offset: 0x008 FIFO Control Register */ + }; + __IO uint8_t LCR; /*!< Offset: 0x00C Line Control Register */ + uint8_t RESERVED1[7]; + __I uint8_t LSR; /*!< Offset: 0x014 Line Status Register */ + uint8_t RESERVED2[7]; + __IO uint8_t SCR; /*!< Offset: 0x01C Scratch Pad Register */ + uint8_t RESERVED3[3]; + __IO uint32_t ACR; /*!< Offset: 0x020 Autobaud Control Register */ + __IO uint8_t ICR; /*!< Offset: 0x024 IrDA Control Register */ + uint8_t RESERVED4[3]; + __IO uint8_t FDR; /*!< Offset: 0x028 Fractional Divider Register */ + uint8_t RESERVED5[7]; + __IO uint8_t TER; /*!< Offset: 0x030 Transmit Enable Register */ + uint8_t RESERVED6[39]; + __I uint8_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register */ +} LPC_UART_TypeDef;</pre> + </li> + <li><device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. + For example UART1->DR is the data register of UART1. + <pre> +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</pre> + </li> +</ul> + +<h5>Minimal Requiements</h5> +<p> + To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong> + and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum: +</p> +<ul> + <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names. + Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of + the peripheral registers. For example: + <pre> +typedef struct { + __IO uint32_t CTRL; /* SysTick Control and Status Register */ + __IO uint32_t LOAD; /* SysTick Reload Value Register */ + __IO uint32_t VAL; /* SysTick Current Value Register */ + __I uint32_t CALIB; /* SysTick Calibration Register */ + } SysTick_Type;</pre> + </li> + + <li> + <strong>Base Address</strong> for each peripheral (in case of multiple peripherals + that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example: + <pre> +#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre> + </li> + + <li> + <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use + the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0, + LPC_UART2). For Example: + <pre> +#define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre> + </li> +</ul> + +<p> + These definitions allow to access the peripheral registers from user code with simple assignments like: +</p> +<pre>SysTick->CTRL = 0;</pre> + +<h5>Optional Features</h5> +<p>In addition the <em> <strong>device.h </strong></em>file may define:</p> +<ul> + <li> + #define constants that simplify access to the peripheral registers. + These constant define bit-positions or other specific patterns are that required for the + programming of the peripheral registers. The identifiers used start with + <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>. + It is recommended to use CAPITAL letters for such #define constants. + </li> + <li> + Functions that perform more complex functions with the peripheral (i.e. status query before + a sending register is accessed). Again these function start with + <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>. + </li> +</ul> + +<h3>core_cm0.h and core_cm0.c</h3> +<p> + File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers + and core peripherals with efficient functions (defined as <strong>static inline</strong>). +</p> +<p> + File <b>core_cm0.c</b> defines several helper functions that access processor registers. +</p> +<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p> + +<h3>core_cm3.h and core_cm3.c</h3> +<p> + File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers + and core peripherals with efficient functions (defined as <strong>static inline</strong>). +</p> +<p> + File <b>core_cm3.c</b> defines several helper functions that access processor registers. +</p> +<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p> + +<h3>startup_<em>device</em></h3> +<p> + A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported + compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific + interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function + to an dummy handler. Therefore the interrupt handler can be directly used in application software + without any requirements to adapt the <strong>startup_<em>device</em></strong> file. +</p> +<p> + The following exception names are fixed and define the start of the vector table for a Cortex-M0: +</p> +<pre> +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler</pre> + +<p> + The following exception names are fixed and define the start of the vector table for a Cortex-M3: +</p> +<pre> +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler</pre> + +<p> + In the following examples for device specific interrupts are shown: +</p> +<pre> +; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper</pre> + +<p> + Device specific interrupts must have a dummy function that can be overwritten in user code. + Below is an example for this dummy function. +</p> +<pre> +Default_Handler PROC + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + : + : + WWDG_IRQHandler + PVD_IRQHandler + TAMPER_IRQHandler + : + : + B . + ENDP</pre> + +<p> + The user application may simply define an interrupt handler function by using the handler name + as shown below. +</p> +<pre> +void WWDG_IRQHandler(void) +{ + : + : +}</pre> + + +<h3><a name="4"></a>system_<em>device</em>.c</h3> +<p> + A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by + the silicon vendor to match their actual device. As a <strong>minimum requirement</strong> + this file must provide a device specific system configuration function and a global variable + that contains the system frequency. It configures the device and initializes typically the + oscillator (PLL) that is part of the microcontroller device. +</p> +<p> + The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide + as a minimum requirement the SystemInit function as shown below. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt">Function Definition</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void SystemInit (void)</td> + <td class="kt">Setup the microcontroller system. Typically this function configures the + oscillator (PLL) that is part of the microcontroller device. For systems + with variable clock speed it also updates the variable SystemCoreClock.<br> + SystemInit is called from startup<i>_device</i> file.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td> + <td class="kt">Updates the variable SystemCoreClock and must be called whenever the + core clock is changed during program execution. SystemCoreClockUpdate() + evaluates the clock register settings and calculates the current core clock. +</td> + </tr> + </tbody> +</table> + +<p> + Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> + is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt">Variable Definition</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td> + <td class="kt">Contains the system core clock (which is the system clock frequency supplied + to the SysTick timer and the processor core clock). This variable can be + used by the user application to setup the SysTick timer or configure other + parameters. It may also be used by debugger to query the frequency of the + debug timer or configure the trace clock speed.<br> + SystemCoreClock is initialized with a correct predefined value.<br><br> + The compiler must be configured to avoid the removal of this variable in + case that the application program is not using it. It is important for + debug systems that the variable is physically present in memory so that + it can be examined to configure the debugger.</td> + </tr> + </tbody> +</table> + +<p class="Note">Note</p> +<ul> + <li><p>The above definitions are the minimum requirements for the file <strong> + system_</strong><em><strong>device</strong></em><strong>.c</strong>. This + file may export more functions or variables that provide a more flexible + configuration of the microcontroller system.</p> + </li> +</ul> + + +<h2>Core Peripheral Access Layer</h2> + +<h3>Cortex-M Core Register Access</h3> +<p> + The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> + and provide access to Cortex-M core registers. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt">Function Definition</th> + <th class="kt">Core</th> + <th class="kt">Core Register</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __enable_irq (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">PRIMASK = 0</td> + <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE + i</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __disable_irq (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">PRIMASK = 1</td> + <td class="kt">Global Interrupt disable (using the instruction <strong> + CPSID i</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td> + <td class="kt">M0, M3</td> + <td class="kt">PRIMASK = value</td> + <td class="kt">Assign value to Priority Mask Register (using the instruction + <strong>MSR</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">return PRIMASK</td> + <td class="kt">Return Priority Mask Register (using the instruction + <strong>MRS</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td> + <td class="kt">M3</td> + <td class="kt">FAULTMASK = 0</td> + <td class="kt">Global Fault exception and Interrupt enable (using the + instruction <strong>CPSIE + f</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td> + <td class="kt">M3</td> + <td class="kt">FAULTMASK = 1</td> + <td class="kt">Global Fault exception and Interrupt disable (using the + instruction <strong>CPSID f</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td> + <td class="kt">M3</td> + <td class="kt">FAULTMASK = value</td> + <td class="kt">Assign value to Fault Mask Register (using the instruction + <strong>MSR</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td> + <td class="kt">M3</td> + <td class="kt">return FAULTMASK</td> + <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td> + <td class="kt">M3</td> + <td class="kt">BASEPRI = value</td> + <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td> + <td class="kt">M3</td> + <td class="kt">return BASEPRI</td> + <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td> + <td class="kt">M0, M3</td> + <td class="kt">CONTROL = value</td> + <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">return CONTROL</td> + <td class="kt">Return Control Register Value (using the instruction + <strong>MRS</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td> + <td class="kt">M0, M3</td> + <td class="kt">PSP = TopOfProcStack</td> + <td class="kt">Set Process Stack Pointer value (using the instruction + <strong>MSR</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">return PSP</td> + <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td> + <td class="kt">M0, M3</td> + <td class="kt">MSP = TopOfMainStack</td> + <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">return MSP</td> + <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td> + </tr> + </tbody> +</table> + +<h3>Cortex-M Instruction Access</h3> +<p> + The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and + generate specific Cortex-M instructions. The functions are implemented in the file + <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt">Name</th> + <th class="kt">Core</th> + <th class="kt">Generated CPU Instruction</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __NOP (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">NOP</td> + <td class="kt">No Operation</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __WFI (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">WFI</td> + <td class="kt">Wait for Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __WFE (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">WFE</td> + <td class="kt">Wait for Event</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __SEV (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">SEV</td> + <td class="kt">Set Event</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __ISB (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">ISB</td> + <td class="kt">Instruction Synchronization Barrier</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __DSB (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">DSB</td> + <td class="kt">Data Synchronization Barrier</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __DMB (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">DMB</td> + <td class="kt">Data Memory Barrier</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td> + <td class="kt">M0, M3</td> + <td class="kt">REV</td> + <td class="kt">Reverse byte order in integer value.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td> + <td class="kt">M0, M3</td> + <td class="kt">REV16</td> + <td class="kt">Reverse byte order in unsigned short value. </td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td> + <td class="kt">M0, M3</td> + <td class="kt">REVSH</td> + <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td> + <td class="kt">M3</td> + <td class="kt">RBIT</td> + <td class="kt">Reverse bit order of value</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td> + <td class="kt">M3</td> + <td class="kt">LDREXB</td> + <td class="kt">Load exclusive byte</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td> + <td class="kt">M3</td> + <td class="kt">LDREXH</td> + <td class="kt">Load exclusive half-word</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td> + <td class="kt">M3</td> + <td class="kt">LDREXW</td> + <td class="kt">Load exclusive word</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td> + <td class="kt">M3</td> + <td class="kt">STREXB</td> + <td class="kt">Store exclusive byte</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td> + <td class="kt">M3</td> + <td class="kt">STREXH</td> + <td class="kt">Store exclusive half-word</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td> + <td class="kt">M3</td> + <td class="kt">STREXW</td> + <td class="kt">Store exclusive word</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void __CLREX (void)</td> + <td class="kt">M3</td> + <td class="kt">CLREX</td> + <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td> + </tr> + </tbody> +</table> + + +<h3>NVIC Access Functions</h3> +<p> + The CMSIS provides access to the NVIC via the register interface structure and several helper + functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to + identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative + IRQn values are used for processor core exceptions. +</p> +<p> + For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides + the following enum names. +</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">Core Exception enum Value</th> + <th class="kt">Core</th> + <th class="kt">IRQn</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td> + <td class="kt">M0, M3</td> + <td class="kt">-14</td> + <td class="kt">Cortex-M Non Maskable Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">HardFault_IRQn</td> + <td class="kt">M0, M3</td> + <td class="kt">-13</td> + <td class="kt">Cortex-M Hard Fault Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td> + <td class="kt">M3</td> + <td class="kt">-12</td> + <td class="kt">Cortex-M Memory Management Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">BusFault_IRQn</td> + <td class="kt">M3</td> + <td class="kt">-11</td> + <td class="kt">Cortex-M Bus Fault Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">UsageFault_IRQn</td> + <td class="kt">M3</td> + <td class="kt">-10</td> + <td class="kt">Cortex-M Usage Fault Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">SVCall_IRQn</td> + <td class="kt">M0, M3</td> + <td class="kt">-5</td> + <td class="kt">Cortex-M SV Call Interrupt </td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td> + <td class="kt">M3</td> + <td class="kt">-4</td> + <td class="kt">Cortex-M Debug Monitor Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">PendSV_IRQn</td> + <td class="kt">M0, M3</td> + <td class="kt">-2</td> + <td class="kt">Cortex-M Pend SV Interrupt</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">SysTick_IRQn</td> + <td class="kt">M0, M3</td> + <td class="kt">-1</td> + <td class="kt">Cortex-M System Tick Interrupt</td> + </tr> + </tbody> +</table> + +<p>The following functions simplify the setup of the NVIC. +The functions are defined as <strong>static inline</strong>.</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">Name</th> + <th class="kt">Core</th> + <th class="kt">Parameter</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td> + <td class="kt">M3</td> + <td class="kt">Priority Grouping Value</td> + <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td> + <td class="kt">M3</td> + <td class="kt">(void)</td> + <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td> + <td class="kt">M0, M3</td> + <td class="kt">IRQ Number</td> + <td class="kt">Enable IRQn</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td> + <td class="kt">M0, M3</td> + <td class="kt">IRQ Number</td> + <td class="kt">Disable IRQn</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td> + <td class="kt">M0, M3</td> + <td class="kt">IRQ Number</td> + <td class="kt">Return 1 if IRQn is pending else 0</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td> + <td class="kt">M0, M3</td> + <td class="kt">IRQ Number</td> + <td class="kt">Set IRQn Pending</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td> + <td class="kt">M0, M3</td> + <td class="kt">IRQ Number</td> + <td class="kt">Clear IRQn Pending Status</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td> + <td class="kt">M3</td> + <td class="kt">IRQ Number</td> + <td class="kt">Return 1 if IRQn is active else 0</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td> + <td class="kt">M0, M3</td> + <td class="kt">IRQ Number, Priority</td> + <td class="kt">Set Priority for IRQn<br> + (not threadsafe for Cortex-M0)</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td> + <td class="kt">M0, M3</td> + <td class="kt">IRQ Number</td> + <td class="kt">Get Priority for IRQn</td> + </tr> + <tr> +<!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> --> + <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> + <td class="kt">M3</td> + <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td> + <td class="kt">Encode priority for given group, preemptive and sub priority</td> + </tr> +<!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> --> + <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> + <td class="kt">M3</td> + <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td> + <td class="kt">Deccode given priority to group, preemptive and sub priority</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td> + <td class="kt">M0, M3</td> + <td class="kt">(void)</td> + <td class="kt">Resets the System</td> + </tr> + </tbody> +</table> +<p class="Note">Note</p> +<ul> + <li><p>The processor exceptions have negative enum values. Device specific interrupts + have positive enum values and start with 0. The values are defined in + <b><em>device.h</em></b> file. + </p> + </li> + <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b> + used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b> + depend on the available __NVIC_PRIO_BITS implemented in the NVIC. + </p> + </li> +</ul> + + +<h3>SysTick Configuration Function</h3> + +<p>The following function is used to configure the SysTick timer and start the +SysTick interrupt.</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">Name</th> + <th class="kt">Parameter</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig + (uint32_t ticks)</span></td> + <td class="kt">ticks is SysTick counter reload value</td> + <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this + call the SysTick timer creates interrupts with the specified time + interval. <br> + <br> + Return: 0 when successful, 1 on failure.<br> + </td> + </tr> + </tbody> +</table> + + +<h3>Cortex-M3 ITM Debug Access</h3> + +<p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that +provides together with the Serial Viewer Output trace capabilities for the +microcontroller system. The ITM has 32 communication channels; two ITM +communication channels are used by CMSIS to output the following information:</p> +<ul> + <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function + which can be used for printf-style output via the debug interface.</li> + <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for + kernel awareness debugging.</li> +</ul> +<p class="Note">Note</p> +<ul> + <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels + may use the Privileged level for program execution. ITM + channels have 4 groups with 8 channels each, whereby each group can be + configured for access rights in the Unprivileged level. The ITM channel 0 + may be therefore enabled for the user task whereas ITM channel 31 may be + accessible only in Privileged level from the RTOS kernel itself.</p> + </li> +</ul> + +<p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the +table below.</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">Name</th> + <th class="kt">Parameter</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td> + <td class="kt">character to output</td> + <td class="kt">The function outputs a character via the ITM channel 0. The + function returns when no debugger is connected that has booked the + output. It is blocking when a debugger is connected, but the + previous character send is not transmitted. <br><br> + Return: the input character 'chr'.</td> + </tr> + </tbody> +</table> + +<p> + Example for the usage of the ITM Channel 31 for RTOS Kernels: +</p> +<pre> + // check if debugger connected and ITM channel enabled for tracing + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && + (ITM->TCR & ITM_TCR_ITMENA) && + (ITM->TER & (1UL << 31))) { + // transmit trace data + while (ITM->PORT31_U32 == 0); + ITM->PORT[31].u8 = task_id; // id of next task + while (ITM->PORT[31].u32 == 0); + ITM->PORT[31].u32 = task_status; // status information + }</pre> + + +<h3>Cortex-M3 additional Debug Access</h3> + +<p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access. +Data can be transmitted via a certain global buffer variable towards the target system.</p> + +<p>The buffer variable and the prototypes of the additional functions are shown in the +table below.</p> + +<table class="kt" border="0" cellpadding="0" cellspacing="0"> + <tbody> + <tr> + <th class="kt" nowrap="nowrap">Name</th> + <th class="kt">Parameter</th> + <th class="kt">Description</th> + </tr> + <tr> + <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td> + <td class="kt"> </td> + <td class="kt">Buffer to transmit data towards debug system. <br><br> + Value 0x5AA55AA5 indicates that buffer is empty.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td> + <td class="kt">none</td> + <td class="kt">The nonblocking functions returns the character stored in + ITM_RxBuffer. <br><br> + Return: -1 indicates that no character was received.</td> + </tr> + <tr> + <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td> + <td class="kt">none</td> + <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br> + Return: 1 indicates that a character is available, 0 indicates that + no character is available.</td> + </tr> + </tbody> +</table> + + +<h2><a name="5"></a>CMSIS Example</h2> +<p> + The following section shows a typical example for using the CMSIS layer in user applications. + The example is based on a STM32F10x Device. +</p> +<pre> +#include "stm32f10x.h" + +volatile uint32_t msTicks; /* timeTicks counter */ + +void SysTick_Handler(void) { + msTicks++; /* increment timeTicks counter */ +} + +__INLINE static void Delay (uint32_t dlyTicks) { + uint32_t curTicks = msTicks; + + while ((msTicks - curTicks) < dlyTicks); +} + +__INLINE static void LED_Config(void) { + ; /* Configure the LEDs */ +} + +__INLINE static void LED_On (uint32_t led) { + ; /* Turn On LED */ +} + +__INLINE static void LED_Off (uint32_t led) { + ; /* Turn Off LED */ +} + +int main (void) { + if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */ + ; /* Handle Error */ + while (1); + } + + LED_Config(); /* configure the LEDs */ + + while(1) { + LED_On (0x100); /* Turn on the LED */ + Delay (100); /* delay 100 Msec */ + LED_Off (0x100); /* Turn off the LED */ + Delay (100); /* delay 100 Msec */ + } +}</pre> + + +</body></html> \ No newline at end of file
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/CMSIS/License.doc Binary file host/Source/CMSIS/License.doc has changed
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/Source/LPC17xx.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/host/Source/LPC17xx.h Wed Feb 03 10:44:42 2016 +0300 @@ -0,0 +1,999 @@ +/****************************************************************************** + * @file: LPC17xx.h + * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version: V1.10 + * @date: 24. September 2010 + *---------------------------------------------------------------------------- + * + * @note + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +/** @addtogroup LPC17xx_System + * @{ + */ + +/** @brief IRQ interrupt source definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ + USBActivity_IRQn = 33, /*!< USB Activity Interrupt(For wakeup only) */ + CANActivity_IRQn = 34 /*!< CAN Activity Interrupt(For wakeup only) */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +#include "system_LPC17xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SC) ------------------------------------------*/ +/** @brief System Control (SC) register structure definition */ +typedef struct +{ + __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ + __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ + __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ + __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ + __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ + __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ + __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ + uint32_t RESERVED2[4]; + __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ + __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; /*!< Offset: 0x104 (R/W) CPU Clock Configure Register */ + __IO uint32_t USBCLKCFG; /*!< Offset: 0x108 (R/W) USB Clock Configure Register */ + __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ + __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ + __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ + uint32_t RESERVED4[10]; + __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ + uint32_t RESERVED5[1]; + __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ + __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Select 0 Register */ + __IO uint32_t PCLKSEL1; /*!< Offset: 0x1AC (R/W) Peripheral Clock Select 1 Register */ + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ + __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ + __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ + + } LPC_SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +/** @brief Pin Connect Block (PINCON) register structure definition */ +typedef struct +{ + __IO uint32_t PINSEL0; /* !< Offset: 0x000 PIN Select0 (R/W) */ + __IO uint32_t PINSEL1; /* !< Offset: 0x004 PIN Select1 (R/W) */ + __IO uint32_t PINSEL2; /* !< Offset: 0x008 PIN Select2 (R/W) */ + __IO uint32_t PINSEL3; /* !< Offset: 0x00C PIN Select3 (R/W) */ + __IO uint32_t PINSEL4; /* !< Offset: 0x010 PIN Select4 (R/W) */ + __IO uint32_t PINSEL5; /* !< Offset: 0x014 PIN Select5 (R/W) */ + __IO uint32_t PINSEL6; /* !< Offset: 0x018 PIN Select6 (R/W) */ + __IO uint32_t PINSEL7; /* !< Offset: 0x01C PIN Select7 (R/W) */ + __IO uint32_t PINSEL8; /* !< Offset: 0x020 PIN Select8 (R/W) */ + __IO uint32_t PINSEL9; /* !< Offset: 0x024 PIN Select9 (R/W) */ + __IO uint32_t PINSEL10; /* !< Offset: 0x028 PIN Select20 (R/W) */ + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; /* !< Offset: 0x040 PIN Mode0 (R/W) */ + __IO uint32_t PINMODE1; /* !< Offset: 0x044 PIN Mode1 (R/W) */ + __IO uint32_t PINMODE2; /* !< Offset: 0x048 PIN Mode2 (R/W) */ + __IO uint32_t PINMODE3; /* !< Offset: 0x04C PIN Mode3 (R/W) */ + __IO uint32_t PINMODE4; /* !< Offset: 0x050 PIN Mode4 (R/W) */ + __IO uint32_t PINMODE5; /* !< Offset: 0x054 PIN Mode5 (R/W) */ + __IO uint32_t PINMODE6; /* !< Offset: 0x058 PIN Mode6 (R/W) */ + __IO uint32_t PINMODE7; /* !< Offset: 0x05C PIN Mode7 (R/W) */ + __IO uint32_t PINMODE8; /* !< Offset: 0x060 PIN Mode8 (R/W) */ + __IO uint32_t PINMODE9; /* !< Offset: 0x064 PIN Mode9 (R/W) */ + __IO uint32_t PINMODE_OD0; /* !< Offset: 0x068 Open Drain PIN Mode0 (R/W) */ + __IO uint32_t PINMODE_OD1; /* !< Offset: 0x06C Open Drain PIN Mode1 (R/W) */ + __IO uint32_t PINMODE_OD2; /* !< Offset: 0x070 Open Drain PIN Mode2 (R/W) */ + __IO uint32_t PINMODE_OD3; /* !< Offset: 0x074 Open Drain PIN Mode3 (R/W) */ + __IO uint32_t PINMODE_OD4; /* !< Offset: 0x078 Open Drain PIN Mode4 (R/W) */ + __IO uint32_t I2CPADCFG; /* !< Offset: 0x07C I2C Pad Configure (R/W) */ +} LPC_PINCON_TypeDef; + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +/** @brief General Purpose Input/Output (GPIO) register structure definition */ +typedef struct +{ + union { + __IO uint32_t FIODIR; /* !< Offset: 0x00 Port direction (R/W) */ + struct { + __IO uint16_t FIODIRL; + __IO uint16_t FIODIRH; + }; + struct { + __IO uint8_t FIODIR0; + __IO uint8_t FIODIR1; + __IO uint8_t FIODIR2; + __IO uint8_t FIODIR3; + }; + }; + uint32_t RESERVED0[3]; + union { + __IO uint32_t FIOMASK; /* !< Offset: 0x10 Port mask (R/W) */ + struct { + __IO uint16_t FIOMASKL; + __IO uint16_t FIOMASKH; + }; + struct { + __IO uint8_t FIOMASK0; + __IO uint8_t FIOMASK1; + __IO uint8_t FIOMASK2; + __IO uint8_t FIOMASK3; + }; + }; + union { + __IO uint32_t FIOPIN; /* !< Offset: 0x14 Port value (R/W) */ + struct { + __IO uint16_t FIOPINL; + __IO uint16_t FIOPINH; + }; + struct { + __IO uint8_t FIOPIN0; + __IO uint8_t FIOPIN1; + __IO uint8_t FIOPIN2; + __IO uint8_t FIOPIN3; + }; + }; + union { + __IO uint32_t FIOSET; /* !< Offset: 0x18 Port output set (R/W) */ + struct { + __IO uint16_t FIOSETL; + __IO uint16_t FIOSETH; + }; + struct { + __IO uint8_t FIOSET0; + __IO uint8_t FIOSET1; + __IO uint8_t FIOSET2; + __IO uint8_t FIOSET3; + }; + }; + union { + __O uint32_t FIOCLR; /* !< Offset: 0x1C Port output clear (R/W) */ + struct { + __O uint16_t FIOCLRL; + __O uint16_t FIOCLRH; + }; + struct { + __O uint8_t FIOCLR0; + __O uint8_t FIOCLR1; + __O uint8_t FIOCLR2; + __O uint8_t FIOCLR3; + }; + }; +} LPC_GPIO_TypeDef; + +/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */ +typedef struct +{ + __I uint32_t IntStatus; /*!< Offset: 0x000 (R/ ) GPIO overall Interrupt Status Register */ + __I uint32_t IO0IntStatR; /*!< Offset: 0x004 (R/ ) GPIO Interrupt Status Register 0 for Rising edge */ + __I uint32_t IO0IntStatF; /*!< Offset: 0x008 (R/ ) GPIO Interrupt Status Register 0 for Falling edge */ + __O uint32_t IO0IntClr; /*!< Offset: 0x00C (R/W) GPIO Interrupt Clear Register 0 */ + __IO uint32_t IO0IntEnR; /*!< Offset: 0x010 ( /W) GPIO Interrupt Enable Register 0 for Rising edge */ + __IO uint32_t IO0IntEnF; /*!< Offset: 0x014 (R/W) GPIO Interrupt Enable Register 0 for Falling edge */ + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Rising edge */ + __I uint32_t IO2IntStatF; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Falling edge */ + __O uint32_t IO2IntClr; /*!< Offset: 0x000 ( /W) GPIO Interrupt Clear Register 2 */ + __IO uint32_t IO2IntEnR; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Rising edge */ + __IO uint32_t IO2IntEnF; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Falling edge */ +} LPC_GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +/** @brief Timer (TIM) register structure definition */ +typedef struct +{ + __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */ + __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */ + __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */ + __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */ + __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */ + __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */ + __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */ + __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */ + __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */ + __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */ + __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */ + __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */ + __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register */ + uint32_t RESERVED0[2]; + __IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */ + uint32_t RESERVED1[12]; + __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */ +} LPC_TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +/** @brief Pulse-Width Modulation (PWM) register structure definition */ +typedef struct +{ + __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */ + __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register. Register */ + __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */ + __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */ + __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */ + __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */ + __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */ + __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */ + __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */ + __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */ + __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */ + __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */ + __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register 1 */ + __I uint32_t CR2; /*!< Offset: 0x034 (R/ ) Capture Register 2 */ + __I uint32_t CR3; /*!< Offset: 0x038 (R/ ) Capture Register 3 */ + uint32_t RESERVED0; + __IO uint32_t MR4; /*!< Offset: 0x040 (R/W) Match Register 4 */ + __IO uint32_t MR5; /*!< Offset: 0x044 (R/W) Match Register 5 */ + __IO uint32_t MR6; /*!< Offset: 0x048 (R/W) Match Register 6 */ + __IO uint32_t PCR; /*!< Offset: 0x04C (R/W) PWM Control Register */ + __IO uint32_t LER; /*!< Offset: 0x050 (R/W) Load Enable Register */ + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */ +} LPC_PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ + __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ + }; + union { + __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ + __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register (R/W) */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ + __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ + uint32_t RESERVED0; + __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ + uint32_t RESERVED1; + __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ + __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ + __IO uint32_t ICR; /*!< Offset: 0x024 IrDA Control Register (R/W) */ + __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ + uint32_t RESERVED2; + __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ +} LPC_UART_TypeDef; + +/** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ + __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ + }; + union { + __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ + __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ + }; + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ + __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ + __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ + __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ + __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ + __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ + uint32_t RESERVED0; + __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ + uint32_t RESERVED1; + __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ + uint32_t RESERVED2[6]; + __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ + __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ + __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ +} LPC_UART1_TypeDef; + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +/** @brief Serial Peripheral Interface (SPI) register structure definition */ +typedef struct +{ + __IO uint32_t SPCR; /*!< Offset: 0x000 SPI Control Register (R/W) */ + __I uint32_t SPSR; /*!< Offset: 0x004 SPI Status Register (R/) */ + __IO uint32_t SPDR; /*!< Offset: 0x008 SPI Data Register (R/W) */ + __IO uint32_t SPCCR; /*!< Offset: 0x00C SPI Clock Counter Register (R/W) */ + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; /*!< Offset: 0x01C SPI Interrupt Flag Register (R/W) */ +} LPC_SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +/** @brief Synchronous Serial Communication (SSP) register structure definition */ +typedef struct +{ + __IO uint32_t CR0; /*!< Offset: 0x000 (R/W) Control Register 0 */ + __IO uint32_t CR1; /*!< Offset: 0x004 (R/W) Control Register 1 */ + __IO uint32_t DR; /*!< Offset: 0x008 (R/W) Data Register */ + __I uint32_t SR; /*!< Offset: 0x00C (R/ ) Status Register */ + __IO uint32_t CPSR; /*!< Offset: 0x010 (R/W) Clock Prescale Register */ + __IO uint32_t IMSC; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */ + __IO uint32_t RIS; /*!< Offset: 0x018 (R/W) Raw Interrupt Status Register */ + __IO uint32_t MIS; /*!< Offset: 0x01C (R/W) Masked Interrupt Status Register */ + __IO uint32_t ICR; /*!< Offset: 0x020 (R/W) SSPICR Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< Offset: 0x024 (R/W) DMA Control Register */ +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** @brief Inter-Integrated Circuit (I2C) register structure definition */ +typedef struct +{ + __IO uint32_t CONSET; /*!< Offset: 0x000 (R/W) I2C Control Set Register */ + __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) I2C Status Register */ + __IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C Data Register */ + __IO uint32_t ADR0; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */ + __IO uint32_t SCLH; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */ + __IO uint32_t SCLL; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */ + __O uint32_t CONCLR; /*!< Offset: 0x018 (R/W) I2C Control Clear Register */ + __IO uint32_t MMCTRL; /*!< Offset: 0x01C (R/W) Monitor mode control register */ + __IO uint32_t ADR1; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */ + __IO uint32_t ADR2; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */ + __IO uint32_t ADR3; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */ + __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C (R/ ) Data buffer Register */ + __IO uint32_t MASK0; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */ + __IO uint32_t MASK2; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */ + __IO uint32_t MASK3; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */ +} LPC_I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +/** @brief Inter IC Sound (I2S) register structure definition */ +typedef struct +{ + __IO uint32_t DAO; /*!< Offset: 0x000 (R/W) Digital Audio Output Register */ + __IO uint32_t DAI; /*!< Offset: 0x004 (R/W) Digital Audio Input Register */ + __O uint32_t TXFIFO; /*!< Offset: 0x008 ( /W) Transmit FIFO */ + __I uint32_t RXFIFO; /*!< Offset: 0x00C (R/ ) Receive FIFO */ + __I uint32_t STATE; /*!< Offset: 0x010 (R/W) Status Feedback Register */ + __IO uint32_t DMA1; /*!< Offset: 0x014 (R/W) DMA Configuration Register 1 */ + __IO uint32_t DMA2; /*!< Offset: 0x018 (R/W) DMA Configuration Register 2 */ + __IO uint32_t IRQ; /*!< Offset: 0x01C (R/W) Interrupt Request Control Register */ + __IO uint32_t TXRATE; /*!< Offset: 0x020 (R/W) Transmit reference clock divider Register */ + __IO uint32_t RXRATE; /*!< Offset: 0x024 (R/W) Receive reference clock divider Register */ + __IO uint32_t TXBITRATE; /*!< Offset: 0x028 (R/W) Transmit bit rate divider Register */ + __IO uint32_t RXBITRATE; /*!< Offset: 0x02C (R/W) Receive bit rate divider Register */ + __IO uint32_t TXMODE; /*!< Offset: 0x030 (R/W) Transmit mode control Register */ + __IO uint32_t RXMODE; /*!< Offset: 0x034 (R/W) Receive mode control Register */ +} LPC_I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +/** @brief Repetitive Interrupt Timer (RIT) register structure definition */ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint32_t RICTRL; + __IO uint32_t RICOUNTER; +} LPC_RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +/** @brief Real-Time Clock (RTC) register structure definition */ +typedef struct +{ + __IO uint32_t ILR; /*!< Offset: 0x000 (R/W) Interrupt Location Register */ + uint32_t RESERVED0; + __IO uint32_t CCR; /*!< Offset: 0x008 (R/W) Clock Control Register */ + __IO uint32_t CIIR; /*!< Offset: 0x00C (R/W) Counter Increment Interrupt Register */ + __IO uint32_t AMR; /*!< Offset: 0x010 (R/W) Alarm Mask Register */ + __I uint32_t CTIME0; /*!< Offset: 0x014 (R/ ) Consolidated Time Register 0 */ + __I uint32_t CTIME1; /*!< Offset: 0x018 (R/ ) Consolidated Time Register 1 */ + __I uint32_t CTIME2; /*!< Offset: 0x01C (R/ ) Consolidated Time Register 2 */ + __IO uint32_t SEC; /*!< Offset: 0x020 (R/W) Seconds Counter Register */ + __IO uint32_t MIN; /*!< Offset: 0x024 (R/W) Minutes Register */ + __IO uint32_t HOUR; /*!< Offset: 0x028 (R/W) Hours Register */ + __IO uint32_t DOM; /*!< Offset: 0x02C (R/W) Day of Month Register */ + __IO uint32_t DOW; /*!< Offset: 0x030 (R/W) Day of Week Register */ + __IO uint32_t DOY; /*!< Offset: 0x034 (R/W) Day of Year Register */ + __IO uint32_t MONTH; /*!< Offset: 0x038 (R/W) Months Register */ + __IO uint32_t YEAR; /*!< Offset: 0x03C (R/W) Years Register */ + __IO uint32_t CALIBRATION; /*!< Offset: 0x040 (R/W) Calibration Value Register */ + __IO uint32_t GPREG0; /*!< Offset: 0x044 (R/W) General Purpose Register 0 */ + __IO uint32_t GPREG1; /*!< Offset: 0x048 (R/W) General Purpose Register 1 */ + __IO uint32_t GPREG2; /*!< Offset: 0x04C (R/W) General Purpose Register 2 */ + __IO uint32_t GPREG3; /*!< Offset: 0x050 (R/W) General Purpose Register 3 */ + __IO uint32_t GPREG4; /*!< Offset: 0x054 (R/W) General Purpose Register 4 */ + __IO uint32_t RTC_AUXEN; /*!< Offset: 0x058 (R/W) RTC Auxiliary Enable Register */ + __IO uint32_t RTC_AUX; /*!< Offset: 0x05C (R/W) RTC Auxiliary Control Register */ + __IO uint32_t ALSEC; /*!< Offset: 0x060 (R/W) Alarm value for Seconds */ + __IO uint32_t ALMIN; /*!< Offset: 0x064 (R/W) Alarm value for Minutes */ + __IO uint32_t ALHOUR; /*!< Offset: 0x068 (R/W) Alarm value for Hours */ + __IO uint32_t ALDOM; /*!< Offset: 0x06C (R/W) Alarm value for Day of Month */ + __IO uint32_t ALDOW; /*!< Offset: 0x070 (R/W) Alarm value for Day of Week */ + __IO uint32_t ALDOY; /*!< Offset: 0x074 (R/W) Alarm value for Day of Year */ + __IO uint32_t ALMON; /*!< Offset: 0x078 (R/W) Alarm value for Months */ + __IO uint32_t ALYEAR; /*!< Offset: 0x07C (R/W) Alarm value for Year */ +} LPC_RTC_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +/** @brief Watchdog Timer (WDT) register structure definition */ +typedef struct +{ + __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) Watchdog mode Register */ + __IO uint32_t TC; /*!< Offset: 0x004 (R/W) Watchdog timer constant Register */ + __O uint32_t FEED; /*!< Offset: 0x008 ( /W) Watchdog feed sequence Register */ + __I uint32_t TV; /*!< Offset: 0x00C (R/ ) Watchdog timer value Register */ + __IO uint32_t WDCLKSEL; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +/** @brief Analog-to-Digital Converter (ADC) register structure definition */ +typedef struct +{ + __IO uint32_t CR; /*!< Offset: 0x000 (R/W) A/D Control Register */ + __IO uint32_t GDR; /*!< Offset: 0x004 (R/W) A/D Global Data Register */ + uint32_t RESERVED0; + __IO uint32_t INTEN; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */ + __I uint32_t DR[8]; /*!< Offset: 0x010 (R/ ) A/D Channel # Data Register */ + __I uint32_t STAT; /*!< Offset: 0x030 (R/ ) A/D Status Register */ + __IO uint32_t ADTRM; /*!< Offset: 0x034 (R/W) ADC trim Register */ +} LPC_ADC_TypeDef; + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +/** @brief Digital-to-Analog Converter (DAC) register structure definition */ +typedef struct +{ + __IO uint32_t CR; /*!< Offset: 0x000 (R/W) D/A Converter Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) DAC Control register */ + __IO uint32_t CNTVAL; /*!< Offset: 0x008 (R/W) DAC Counter Value Register */ +} LPC_DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +/** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */ +typedef struct +{ + __I uint32_t CON; /*!< Offset: 0x000 (R/ ) PWM Control read address Register */ + __O uint32_t CON_SET; /*!< Offset: 0x004 ( /W) PWM Control set address Register */ + __O uint32_t CON_CLR; /*!< Offset: 0x008 ( /W) PWM Control clear address Register */ + __I uint32_t CAPCON; /*!< Offset: 0x00C (R/ ) Capture Control read address Register */ + __O uint32_t CAPCON_SET; /*!< Offset: 0x010 ( /W) Capture Control set address Register */ + __O uint32_t CAPCON_CLR; /*!< Offset: 0x014 ( /W) Event Control clear address Register */ + __IO uint32_t TC0; /*!< Offset: 0x018 (R/W) Timer Counter Register, channel 0 */ + __IO uint32_t TC1; /*!< Offset: 0x01C (R/W) Timer Counter Register, channel 1 */ + __IO uint32_t TC2; /*!< Offset: 0x020 (R/W) Timer Counter Register, channel 2 */ + __IO uint32_t LIM0; /*!< Offset: 0x024 (R/W) Limit Register, channel 0 */ + __IO uint32_t LIM1; /*!< Offset: 0x028 (R/W) Limit Register, channel 1 */ + __IO uint32_t LIM2; /*!< Offset: 0x02C (R/W) Limit Register, channel 2 */ + __IO uint32_t MAT0; /*!< Offset: 0x030 (R/W) Match Register, channel 0 */ + __IO uint32_t MAT1; /*!< Offset: 0x034 (R/W) Match Register, channel 1 */ + __IO uint32_t MAT2; /*!< Offset: 0x038 (R/W) Match Register, channel 2 */ + __IO uint32_t DT; /*!< Offset: 0x03C (R/W) Dead time Register */ + __IO uint32_t CP; /*!< Offset: 0x040 (R/W) Commutation Pattern Register */ + __IO uint32_t CAP0; /*!< Offset: 0x044 (R/W) Capture Register, channel 0 */ + __IO uint32_t CAP1; /*!< Offset: 0x048 (R/W) Capture Register, channel 1 */ + __IO uint32_t CAP2; /*!< Offset: 0x04C (R/W) Capture Register, channel 2 */ + __I uint32_t INTEN; /*!< Offset: 0x050 (R/ ) Interrupt Enable read Register */ + __O uint32_t INTEN_SET; /*!< Offset: 0x054 ( /W) Interrupt Enable set address Register */ + __O uint32_t INTEN_CLR; /*!< Offset: 0x058 ( /W) Interrupt Enable clear address Register */ + __I uint32_t CNTCON; /*!< Offset: 0x05C (R/ ) Count Control read address Register */ + __O uint32_t CNTCON_SET; /*!< Offset: 0x060 ( /W) Count Control set address Register */ + __O uint32_t CNTCON_CLR; /*!< Offset: 0x064 ( /W) Count Control clear address Register */ + __I uint32_t INTF; /*!< Offset: 0x068 (R/ ) Interrupt flags read address Register */ + __O uint32_t INTF_SET; /*!< Offset: 0x06C ( /W) Interrupt flags set address Register */ + __O uint32_t INTF_CLR; /*!< Offset: 0x070 ( /W) Interrupt flags clear address Register */ + __O uint32_t CAP_CLR; /*!< Offset: 0x074 ( /W) Capture clear address Register */ +} LPC_MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +/** @brief Quadrature Encoder Interface (QEI) register structure definition */ +typedef struct +{ + __O uint32_t CON; /*!< Offset: 0x000 ( /W) Control Register */ + __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) Encoder Status Register */ + __IO uint32_t CONF; /*!< Offset: 0x008 (R/W) Configuration Register */ + __I uint32_t POS; /*!< Offset: 0x00C (R/ ) Position Register */ + __IO uint32_t MAXPOS; /*!< Offset: 0x010 (R/W) Maximum position Register */ + __IO uint32_t CMPOS0; /*!< Offset: 0x014 (R/W) Position compare Register 0 */ + __IO uint32_t CMPOS1; /*!< Offset: 0x018 (R/W) Position compare Register 1 */ + __IO uint32_t CMPOS2; /*!< Offset: 0x01C (R/W) Position compare Register 2 */ + __I uint32_t INXCNT; /*!< Offset: 0x020 (R/ ) Index count Register */ + __IO uint32_t INXCMP0; /*!< Offset: 0x024 (R/W) Index compare Register 0 */ + __IO uint32_t LOAD; /*!< Offset: 0x028 (R/W) Velocity timer reload Register */ + __I uint32_t TIME; /*!< Offset: 0x02C (R/ ) Velocity timer Register */ + __I uint32_t VEL; /*!< Offset: 0x030 (R/ ) Velocity counter Register */ + __I uint32_t CAP; /*!< Offset: 0x034 (R/ ) Velocity capture Register */ + __IO uint32_t VELCOMP; /*!< Offset: 0x038 (R/W) Velocity compare Register */ + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t IEC; /*!< Offset: 0xFD8 ( /W) Interrupt enable clear Register */ + __O uint32_t IES; /*!< Offset: 0xFDC ( /W) Interrupt enable set Register */ + __I uint32_t INTSTAT; /*!< Offset: 0xFE0 (R/ ) Interrupt status Register */ + __I uint32_t IE; /*!< Offset: 0xFE4 (R/ ) Interrupt enable Register */ + __O uint32_t CLR; /*!< Offset: 0xFE8 ( /W) Interrupt status clear Register */ + __O uint32_t SET; /*!< Offset: 0xFEC ( /W) Interrupt status set Register */ +} LPC_QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +/** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */ +typedef struct +{ + __IO uint32_t mask[512]; /*!< Offset: 0x000 (R/W) Acceptance Filter RAM */ +} LPC_CANAF_RAM_TypeDef; + +/** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */ +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; /*!< Offset: 0x000 (R/W) Acceptance Filter Register */ + __IO uint32_t SFF_sa; /*!< Offset: 0x004 (R/W) Standard Frame Individual Start Address Register */ + __IO uint32_t SFF_GRP_sa; /*!< Offset: 0x008 (R/W) Standard Frame Group Start Address Register */ + __IO uint32_t EFF_sa; /*!< Offset: 0x00C (R/W) Extended Frame Start Address Register */ + __IO uint32_t EFF_GRP_sa; /*!< Offset: 0x010 (R/W) Extended Frame Group Start Address Register */ + __IO uint32_t ENDofTable; /*!< Offset: 0x014 (R/W) End of AF Tables Register */ + __I uint32_t LUTerrAd; /*!< Offset: 0x018 (R/ ) LUT Error Address Register */ + __I uint32_t LUTerr; /*!< Offset: 0x01C (R/ ) LUT Error Register */ + __IO uint32_t FCANIE; /*!< Offset: 0x020 (R/W) Global FullCANInterrupt Enable Register */ + __IO uint32_t FCANIC0; /*!< Offset: 0x024 (R/W) FullCAN Interrupt and Capture Register 0 */ + __IO uint32_t FCANIC1; /*!< Offset: 0x028 (R/W) FullCAN Interrupt and Capture Register 1 */ +} LPC_CANAF_TypeDef; + +/** @brief Controller Area Network Central (CANCR) register structure definition */ +typedef struct /* Central Registers */ +{ + __I uint32_t TxSR; /*!< Offset: 0x000 (R/ ) CAN Central Transmit Status Register */ + __I uint32_t RxSR; /*!< Offset: 0x004 (R/ ) CAN Central Receive Status Register */ + __I uint32_t MSR; /*!< Offset: 0x008 (R/ ) CAN Central Miscellaneous Register */ +} LPC_CANCR_TypeDef; + +/** @brief Controller Area Network Controller (CAN) register structure definition */ +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) CAN Mode Register */ + __O uint32_t CMR; /*!< Offset: 0x004 ( /W) CAN Command Register */ + __IO uint32_t GSR; /*!< Offset: 0x008 (R/W) CAN Global Status Register */ + __I uint32_t ICR; /*!< Offset: 0x00C (R/ ) CAN Interrupt and Capture Register */ + __IO uint32_t IER; /*!< Offset: 0x010 (R/W) CAN Interrupt Enable Register */ + __IO uint32_t BTR; /*!< Offset: 0x014 (R/W) CAN Bus Timing Register */ + __IO uint32_t EWL; /*!< Offset: 0x018 (R/W) CAN Error Warning Limit Register */ + __I uint32_t SR; /*!< Offset: 0x01C (R/ ) CAN Status Register */ + __IO uint32_t RFS; /*!< Offset: 0x020 (R/W) CAN Receive Frame Status Register */ + __IO uint32_t RID; /*!< Offset: 0x024 (R/W) CAN Receive Identifier Register */ + __IO uint32_t RDA; /*!< Offset: 0x028 (R/W) CAN Receive Data Register A */ + __IO uint32_t RDB; /*!< Offset: 0x02C (R/W) CAN Receive Data Register B */ + __IO uint32_t TFI1; /*!< Offset: 0x030 (R/W) CAN Transmit Frame Information Register 1 */ + __IO uint32_t TID1; /*!< Offset: 0x034 (R/W) CAN Transmit Identifier Register 1 */ + __IO uint32_t TDA1; /*!< Offset: 0x038 (R/W) CAN Transmit Data Register A 1 */ + __IO uint32_t TDB1; /*!< Offset: 0x03C (R/W) CAN Transmit Data Register B 1 */ + __IO uint32_t TFI2; /*!< Offset: 0x040 (R/W) CAN Transmit Frame Information Register 2 */ + __IO uint32_t TID2; /*!< Offset: 0x044 (R/W) CAN Transmit Identifier Register 2 */ + __IO uint32_t TDA2; /*!< Offset: 0x048 (R/W) CAN Transmit Data Register A 2 */ + __IO uint32_t TDB2; /*!< Offset: 0x04C (R/W) CAN Transmit Data Register B 2 */ + __IO uint32_t TFI3; /*!< Offset: 0x050 (R/W) CAN Transmit Frame Information Register 3 */ + __IO uint32_t TID3; /*!< Offset: 0x054 (R/W) CAN Transmit Identifier Register 3 */ + __IO uint32_t TDA3; /*!< Offset: 0x058 (R/W) CAN Transmit Data Register A 3 */ + __IO uint32_t TDB3; /*!< Offset: 0x05C (R/W) CAN Transmit Data Register B 3 */ +} LPC_CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +/** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */ +typedef struct /* Common Registers */ +{ + __I uint32_t IntStat; /*!< Offset: 0x000 (R/ ) DMA Interrupt Status Register */ + __I uint32_t IntTCStat; /*!< Offset: 0x004 (R/ ) DMA Interrupt Terminal Count Request Status Register */ + __O uint32_t IntTCClear; /*!< Offset: 0x008 ( /W) DMA Interrupt Terminal Count Request Clear Register */ + __I uint32_t IntErrStat; /*!< Offset: 0x00C (R/ ) DMA Interrupt Error Status Register */ + __O uint32_t IntErrClr; /*!< Offset: 0x010 ( /W) DMA Interrupt Error Clear Register */ + __I uint32_t RawIntTCStat; /*!< Offset: 0x014 (R/ ) DMA Raw Interrupt Terminal Count Status Register */ + __I uint32_t RawIntErrStat; /*!< Offset: 0x018 (R/ ) DMA Raw Error Interrupt Status Register */ + __I uint32_t EnbldChns; /*!< Offset: 0x01C (R/ ) DMA Enabled Channel Register */ + __IO uint32_t SoftBReq; /*!< Offset: 0x020 (R/W) DMA Software Burst Request Register */ + __IO uint32_t SoftSReq; /*!< Offset: 0x024 (R/W) DMA Software Single Request Register */ + __IO uint32_t SoftLBReq; /*!< Offset: 0x028 (R/W) DMA Software Last Burst Request Register */ + __IO uint32_t SoftLSReq; /*!< Offset: 0x02C (R/W) DMA Software Last Single Request Register */ + __IO uint32_t Config; /*!< Offset: 0x030 (R/W) DMA Configuration Register */ + __IO uint32_t Sync; /*!< Offset: 0x034 (R/W) DMA Synchronization Register */ +} LPC_GPDMA_TypeDef; + +/** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */ +typedef struct /* Channel Registers */ +{ + __IO uint32_t CSrcAddr; /*!< Offset: 0x000 (R/W) DMA Channel # Source Address Register */ + __IO uint32_t CDestAddr; /*!< Offset: 0x004 (R/W) DMA Channel # Destination Address Register */ + __IO uint32_t CLLI; /*!< Offset: 0x008 (R/W) DMA Channel # Linked List Item Register */ + __IO uint32_t CControl; /*!< Offset: 0x00C (R/W) DMA Channel # Control Register */ + __IO uint32_t CConfig; /*!< Offset: 0x010 (R/W) DMA Channel # Configuration Register */ +} LPC_GPDMACH_TypeDef; + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +/** @brief Universal Serial Bus (USB) register structure definition */ +typedef struct +{ + __I uint32_t Revision; /*!< Offset: 0x000 (R/ ) Revision Register */ + __IO uint32_t Control; /*!< Offset: 0x004 (R/W) Control Register */ + __IO uint32_t CommandStatus; /*!< Offset: 0x008 (R/W) Command / Status Register */ + __IO uint32_t InterruptStatus; /*!< Offset: 0x00C (R/W) Interrupt Status Register */ + __IO uint32_t InterruptEnable; /*!< Offset: 0x010 (R/W) Interrupt Enable Register */ + __IO uint32_t InterruptDisable; /*!< Offset: 0x014 (R/W) Interrupt Disable Register */ + __IO uint32_t HCCA; /*!< Offset: 0x018 (R/W) Host Controller communication Area Register */ + __I uint32_t PeriodCurrentED; /*!< Offset: 0x01C (R/ ) Register */ + __IO uint32_t ControlHeadED; /*!< Offset: 0x020 (R/W) Register */ + __IO uint32_t ControlCurrentED; /*!< Offset: 0x024 (R/W) Register */ + __IO uint32_t BulkHeadED; /*!< Offset: 0x028 (R/W) Register */ + __IO uint32_t BulkCurrentED; /*!< Offset: 0x02C (R/W) Register */ + __I uint32_t DoneHead; /*!< Offset: 0x030 (R/ ) Register */ + __IO uint32_t FmInterval; /*!< Offset: 0x034 (R/W) Register */ + __I uint32_t FmRemaining; /*!< Offset: 0x038 (R/ ) Register */ + __I uint32_t FmNumber; /*!< Offset: 0x03C (R/ ) Register */ + __IO uint32_t PeriodicStart; /*!< Offset: 0x040 (R/W) Register */ + __IO uint32_t LSTreshold; /*!< Offset: 0x044 (R/W) Register */ + __IO uint32_t RhDescriptorA; /*!< Offset: 0x048 (R/W) Register */ + __IO uint32_t RhDescriptorB; /*!< Offset: 0x04C (R/W) Register */ + __IO uint32_t RhStatus; /*!< Offset: 0x050 (R/W) Register */ + __IO uint32_t RhPortStatus1; /*!< Offset: 0x054 (R/W) Register */ + __IO uint32_t RhPortStatus2; /*!< Offset: 0x05C (R/W) Register */ + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; /*!< Offset: 0x0FC (R/ ) Module ID / Version Reverence ID Register */ + /* USB On-The-Go Registers */ + __I uint32_t IntSt; /*!< Offset: 0x100 (R/ ) OTG Interrupt Status Register */ + __IO uint32_t IntEn; /*!< Offset: 0x104 (R/W) OTG Interrupt Enable Register */ + __O uint32_t IntSet; /*!< Offset: 0x108 ( /W) OTG Interrupt Set Register */ + __O uint32_t IntClr; /*!< Offset: 0x10C ( /W) OTG Interrupt Clear Register */ + __IO uint32_t StCtrl; /*!< Offset: 0x110 (R/W) OTG Status and Control Register */ + __IO uint32_t Tmr; /*!< Offset: 0x114 (R/W) OTG Timer Register */ + uint32_t RESERVED1[58]; + /* USB Device Interrupt Registers */ + __I uint32_t DevIntSt; /*!< Offset: 0x200 (R/ ) USB Device Interrupt Status Register */ + __IO uint32_t DevIntEn; /*!< Offset: 0x204 (R/W) USB Device Interrupt Enable Register */ + __O uint32_t DevIntClr; /*!< Offset: 0x208 ( /W) USB Device Interrupt Clear Register */ + __O uint32_t DevIntSet; /*!< Offset: 0x20C ( /W) USB Device Interrupt Set Register */ + /* USB Device SIE Command Registers */ + __O uint32_t CmdCode; /*!< Offset: 0x210 (R/W) USB Command Code Register */ + __I uint32_t CmdData; /*!< Offset: 0x214 (R/W) USB Command Data Register */ + /* USB Device Transfer Registers */ + __I uint32_t RxData; /*!< Offset: 0x218 (R/ ) USB Receive Data Register */ + __O uint32_t TxData; /*!< Offset: 0x21C ( /W) USB Transmit Data Register */ + __I uint32_t RxPLen; /*!< Offset: 0x220 (R/ ) USB Receive Packet Length Register */ + __O uint32_t TxPLen; /*!< Offset: 0x224 ( /W) USB Transmit Packet Length Register */ + __IO uint32_t Ctrl; /*!< Offset: 0x228 (R/W) USB Control Register */ + __O uint32_t DevIntPri; /*!< Offset: 0x22C (R/W) USB Device Interrupt Priority Register */ + /* USB Device Endpoint Interrupt Regs */ + __I uint32_t EpIntSt; /*!< Offset: 0x230 (R/ ) USB Endpoint Interrupt Status Register */ + __IO uint32_t EpIntEn; /*!< Offset: 0x234 (R/W) USB Endpoint Interrupt Enable Register */ + __O uint32_t EpIntClr; /*!< Offset: 0x238 ( /W) USB Endpoint Interrupt Clear Register */ + __O uint32_t EpIntSet; /*!< Offset: 0x23C ( /W) USB Endpoint Interrupt Set Register */ + __O uint32_t EpIntPri; /*!< Offset: 0x240 ( /W) USB Endpoint Interrupt Priority Register */ + /* USB Device Endpoint Realization Reg*/ + __IO uint32_t ReEp; /*!< Offset: 0x244 (R/W) USB Realize Endpoint Register */ + __O uint32_t EpInd; /*!< Offset: 0x248 ( /W) USB Endpoint Index Register */ + __IO uint32_t MaxPSize; /*!< Offset: 0x24C (R/W) USB MaxPacketSize Register */ + /* USB Device DMA Registers */ + __I uint32_t DMARSt; /*!< Offset: 0x250 (R/ ) USB DMA Request Status Register */ + __O uint32_t DMARClr; /*!< Offset: 0x254 ( /W) USB DMA Request Clear Register */ + __O uint32_t DMARSet; /*!< Offset: 0x258 ( /W) USB DMA Request Set Register */ + uint32_t RESERVED2[9]; + __IO uint32_t UDCAH; /*!< Offset: 0x280 (R/W) USB UDCA Head Register */ + __I uint32_t EpDMASt; /*!< Offset: 0x284 (R/ ) USB EP DMA Status Register */ + __O uint32_t EpDMAEn; /*!< Offset: 0x288 ( /W) USB EP DMA Enable Register */ + __O uint32_t EpDMADis; /*!< Offset: 0x28C ( /W) USB EP DMA Disable Register */ + __I uint32_t DMAIntSt; /*!< Offset: 0x290 (R/ ) USB DMA Interrupt Status Register */ + __IO uint32_t DMAIntEn; /*!< Offset: 0x294 (R/W) USB DMA Interrupt Enable Register */ + uint32_t RESERVED3[2]; + __I uint32_t EoTIntSt; /*!< Offset: 0x2A0 (R/ ) USB End of Transfer Interrupt Status Register */ + __O uint32_t EoTIntClr; /*!< Offset: 0x2A4 ( /W) USB End of Transfer Interrupt Clear Register */ + __O uint32_t EoTIntSet; /*!< Offset: 0x2A8 ( /W) USB End of Transfer Interrupt Set Register */ + __I uint32_t NDDRIntSt; /*!< Offset: 0x2AC (R/ ) USB New DD Request Interrupt Status Register */ + __O uint32_t NDDRIntClr; /*!< Offset: 0x2B0 ( /W) USB New DD Request Interrupt Clear Register */ + __O uint32_t NDDRIntSet; /*!< Offset: 0x2B4 ( /W) USB New DD Request Interrupt Set Register */ + __I uint32_t SysErrIntSt; /*!< Offset: 0x2B8 (R/ ) USB System Error Interrupt Status Register */ + __O uint32_t SysErrIntClr; /*!< Offset: 0x2BC ( /W) USB System Error Interrupt Clear Register */ + __O uint32_t SysErrIntSet; /*!< Offset: 0x2C0 ( /W) USB System Error Interrupt Set Register */ + uint32_t RESERVED4[15]; + /* USB OTG I2C Registers */ + union { + __I uint32_t I2C_RX; /*!< Offset: 0x300 (R/ ) OTG I2C Receive Register */ + __O uint32_t I2C_TX; /*!< Offset: 0x300 ( /W) OTG I2C Transmit Register */ + }; + __I uint32_t I2C_STS; /*!< Offset: 0x304 (R/ ) OTG I2C Status Register */ + __IO uint32_t I2C_CTL; /*!< Offset: 0x308 (R/W) OTG I2C Control Register */ + __IO uint32_t I2C_CLKHI; /*!< Offset: 0x30C (R/W) OTG I2C Clock High Register */ + __O uint32_t I2C_CLKLO; /*!< Offset: 0x310 ( /W) OTG I2C Clock Low Register */ + uint32_t RESERVED5[824]; + /* USB Clock Control Registers */ + union { + __IO uint32_t USBClkCtrl; /*!< Offset: 0xFF4 (R/W) OTG clock controller Register */ + __IO uint32_t OTGClkCtrl; /*!< Offset: 0xFF4 (R/W) USB clock controller Register */ + }; + union { + __I uint32_t USBClkSt; /*!< Offset: 0xFF8 (R/ ) OTG clock status Register */ + __I uint32_t OTGClkSt; /*!< Offset: 0xFF8 (R/ ) USB clock status Register */ + }; +} LPC_USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +/** @brief Ethernet Media Access Controller (EMAC) register structure definition */ +typedef struct +{ + __IO uint32_t MAC1; /*!< Offset: 0x000 (R/W) MAC Configuration Register 1 */ + __IO uint32_t MAC2; /*!< Offset: 0x004 (R/W) MAC Configuration Register 2 */ + __IO uint32_t IPGT; /*!< Offset: 0x008 (R/W) Back-to-Back Inter-Packet-Gap Register */ + __IO uint32_t IPGR; /*!< Offset: 0x00C (R/W) Non Back-to-Back Inter-Packet-Gap Register */ + __IO uint32_t CLRT; /*!< Offset: 0x010 (R/W) Collision Window / Retry Register */ + __IO uint32_t MAXF; /*!< Offset: 0x014 (R/W) Maximum Frame Register */ + __IO uint32_t SUPP; /*!< Offset: 0x018 (R/W) PHY Support Register */ + __IO uint32_t TEST; /*!< Offset: 0x01C (R/W) Test Register */ + __IO uint32_t MCFG; /*!< Offset: 0x020 (R/W) MII Mgmt Configuration Register */ + __IO uint32_t MCMD; /*!< Offset: 0x024 (R/W) MII Mgmt Command Register */ + __IO uint32_t MADR; /*!< Offset: 0x028 (R/W) MII Mgmt Address Register */ + __O uint32_t MWTD; /*!< Offset: 0x02C ( /W) MII Mgmt Write Data Register */ + __I uint32_t MRDD; /*!< Offset: 0x030 (R/ ) MII Mgmt Read Data Register */ + __I uint32_t MIND; /*!< Offset: 0x034 (R/ ) MII Mgmt Indicators Register */ + uint32_t RESERVED0[2]; + __IO uint32_t SA0; /*!< Offset: 0x040 (R/W) Station Address 0 Register */ + __IO uint32_t SA1; /*!< Offset: 0x044 (R/W) Station Address 1 Register */ + __IO uint32_t SA2; /*!< Offset: 0x048 (R/W) Station Address 2 Register */ + uint32_t RESERVED1[45]; + __IO uint32_t Command; /*!< Offset: 0x100 (R/W) Command Register */ + __I uint32_t Status; /*!< Offset: 0x104 (R/ ) Status Register */ + __IO uint32_t RxDescriptor; /*!< Offset: 0x108 (R/W) Receive Descriptor Base Address Register */ + __IO uint32_t RxStatus; /*!< Offset: 0x10C (R/W) Receive Status Base Address Register */ + __IO uint32_t RxDescriptorNumber; /*!< Offset: 0x110 (R/W) Receive Number of Descriptors Register */ + __I uint32_t RxProduceIndex; /*!< Offset: 0x114 (R/ ) Receive Produce Index Register */ + __IO uint32_t RxConsumeIndex; /*!< Offset: 0x118 (R/W) Receive Consume Index Register */ + __IO uint32_t TxDescriptor; /*!< Offset: 0x11C (R/W) Transmit Descriptor Base Address Register */ + __IO uint32_t TxStatus; /*!< Offset: 0x120 (R/W) Transmit Status Base Address Register */ + __IO uint32_t TxDescriptorNumber; /*!< Offset: 0x124 (R/W) Transmit Number of Descriptors Register */ + __IO uint32_t TxProduceIndex; /*!< Offset: 0x128 (R/W) Transmit Produce Index Register */ + __I uint32_t TxConsumeIndex; /*!< Offset: 0x12C (R/ ) Transmit Consume Index Register */ + uint32_t RESERVED2[10]; + __I uint32_t TSV0; /*!< Offset: 0x158 (R/ ) Transmit Status Vector 0 Register */ + __I uint32_t TSV1; /*!< Offset: 0x15C (R/ ) Transmit Status Vector 1 Register */ + __I uint32_t RSV; /*!< Offset: 0x160 (R/ ) Receive Status Vector Register */ + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; /*!< Offset: 0x170 (R/W) Flow Control Counter Register */ + __I uint32_t FlowControlStatus; /*!< Offset: 0x174 (R/ ) Flow Control Status egister */ + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /*!< Offset: 0x200 (R/W) Receive Filter Control Register */ + __I uint32_t RxFilterWoLStatus; /*!< Offset: 0x204 (R/ ) Receive Filter WoL Status Register */ + __O uint32_t RxFilterWoLClear; /*!< Offset: 0x208 ( /W) Receive Filter WoL Clear Register */ + uint32_t RESERVED5; + __IO uint32_t HashFilterL; /*!< Offset: 0x210 (R/W) Hash Filter Table LSBs Register */ + __IO uint32_t HashFilterH; /*!< Offset: 0x214 (R/W) Hash Filter Table MSBs Register */ + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /*!< Offset: 0xFE0 (R/ ) Interrupt Status Register */ + __IO uint32_t IntEnable; /*!< Offset: 0xFE4 (R/W) Interrupt Enable Register */ + __O uint32_t IntClear; /*!< Offset: 0xFE8 ( /W) Interrupt Clear Register */ + __O uint32_t IntSet; /*!< Offset: 0xFEC ( /W) Interrupt Set Register */ + uint32_t RESERVED7; + __IO uint32_t PowerDown; /*!< Offset: 0xFF4 (R/W) Power-Down Register */ +} LPC_EMAC_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#ifdef __LPC17XX_REV00 +#define LPC_AHBRAM0_BASE (0x20000000UL) +#define LPC_AHBRAM1_BASE (0x20004000UL) +#else +#define LPC_AHBRAM0_BASE (0x2007C000UL) +#define LPC_AHBRAM1_BASE (0x20080000UL) +#endif +#define LPC_GPIO_BASE (0x2009C000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_APB1_BASE (0x40080000UL) +#define LPC_AHB_BASE (0x50000000UL) +#define LPC_CM3_BASE (0xE0000000UL) + +/* APB0 peripherals */ +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) +#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) +#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) +#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) +#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) +#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) +#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) +#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) +#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) +#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) +#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) +#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) +#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) +#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) +#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) +#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) +#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) +#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) +#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) +#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) +#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) +#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) +#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) +#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) +#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) +#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) + +/* GPIOs */ +#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) +#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) +#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) +#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) +#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) +#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) +#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) +#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) +#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) +#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) +#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) +#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) +#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) +#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) +#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) +#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) +#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) +#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) +#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) +#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) +#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) +#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) +#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) +#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) +#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) +#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) +#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) +#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) +#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) +#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) +#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) +#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) +#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) +#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) +#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) +#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) +#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) +#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) +#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) +#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) +#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) + +/** + * @} + */ + +#endif // __LPC17xx_H__
diff -r bc8c1cec3da6 -r 12e6183f04d4 host/z