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host/Source/CMSIS/CM3/CoreSupport/core_cm3.h@23:12e6183f04d4, 2016-02-03 (annotated)

Committer:
Kovalev_D
Date:
Wed Feb 03 10:44:42 2016 +0300
Revision:
23:12e6183f04d4
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Kovalev_D 23:12e6183f04d4 1 /**************************************************************************//**
Kovalev_D 23:12e6183f04d4 2 * @file core_cm3.h
Kovalev_D 23:12e6183f04d4 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kovalev_D 23:12e6183f04d4 4 * @version V1.30
Kovalev_D 23:12e6183f04d4 5 * @date 30. October 2009
Kovalev_D 23:12e6183f04d4 6 *
Kovalev_D 23:12e6183f04d4 7 * @note
Kovalev_D 23:12e6183f04d4 8 * Copyright (C) 2009 ARM Limited. All rights reserved.
Kovalev_D 23:12e6183f04d4 9 *
Kovalev_D 23:12e6183f04d4 10 * @par
Kovalev_D 23:12e6183f04d4 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Kovalev_D 23:12e6183f04d4 12 * processor based microcontrollers. This file can be freely distributed
Kovalev_D 23:12e6183f04d4 13 * within development tools that are supporting such ARM based processors.
Kovalev_D 23:12e6183f04d4 14 *
Kovalev_D 23:12e6183f04d4 15 * @par
Kovalev_D 23:12e6183f04d4 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Kovalev_D 23:12e6183f04d4 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Kovalev_D 23:12e6183f04d4 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Kovalev_D 23:12e6183f04d4 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Kovalev_D 23:12e6183f04d4 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Kovalev_D 23:12e6183f04d4 21 *
Kovalev_D 23:12e6183f04d4 22 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 23
Kovalev_D 23:12e6183f04d4 24 #ifndef __CM3_CORE_H__
Kovalev_D 23:12e6183f04d4 25 #define __CM3_CORE_H__
Kovalev_D 23:12e6183f04d4 26
Kovalev_D 23:12e6183f04d4 27 /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
Kovalev_D 23:12e6183f04d4 28 *
Kovalev_D 23:12e6183f04d4 29 * List of Lint messages which will be suppressed and not shown:
Kovalev_D 23:12e6183f04d4 30 * - Error 10: \n
Kovalev_D 23:12e6183f04d4 31 * register uint32_t __regBasePri __asm("basepri"); \n
Kovalev_D 23:12e6183f04d4 32 * Error 10: Expecting ';'
Kovalev_D 23:12e6183f04d4 33 * .
Kovalev_D 23:12e6183f04d4 34 * - Error 530: \n
Kovalev_D 23:12e6183f04d4 35 * return(__regBasePri); \n
Kovalev_D 23:12e6183f04d4 36 * Warning 530: Symbol '__regBasePri' (line 264) not initialized
Kovalev_D 23:12e6183f04d4 37 * .
Kovalev_D 23:12e6183f04d4 38 * - Error 550: \n
Kovalev_D 23:12e6183f04d4 39 * __regBasePri = (basePri & 0x1ff); \n
Kovalev_D 23:12e6183f04d4 40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed
Kovalev_D 23:12e6183f04d4 41 * .
Kovalev_D 23:12e6183f04d4 42 * - Error 754: \n
Kovalev_D 23:12e6183f04d4 43 * uint32_t RESERVED0[24]; \n
Kovalev_D 23:12e6183f04d4 44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
Kovalev_D 23:12e6183f04d4 45 * .
Kovalev_D 23:12e6183f04d4 46 * - Error 750: \n
Kovalev_D 23:12e6183f04d4 47 * #define __CM3_CORE_H__ \n
Kovalev_D 23:12e6183f04d4 48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
Kovalev_D 23:12e6183f04d4 49 * .
Kovalev_D 23:12e6183f04d4 50 * - Error 528: \n
Kovalev_D 23:12e6183f04d4 51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
Kovalev_D 23:12e6183f04d4 52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
Kovalev_D 23:12e6183f04d4 53 * .
Kovalev_D 23:12e6183f04d4 54 * - Error 751: \n
Kovalev_D 23:12e6183f04d4 55 * } InterruptType_Type; \n
Kovalev_D 23:12e6183f04d4 56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
Kovalev_D 23:12e6183f04d4 57 * .
Kovalev_D 23:12e6183f04d4 58 * Note: To re-enable a Message, insert a space before 'lint' *
Kovalev_D 23:12e6183f04d4 59 *
Kovalev_D 23:12e6183f04d4 60 */
Kovalev_D 23:12e6183f04d4 61
Kovalev_D 23:12e6183f04d4 62 /*lint -save */
Kovalev_D 23:12e6183f04d4 63 /*lint -e10 */
Kovalev_D 23:12e6183f04d4 64 /*lint -e530 */
Kovalev_D 23:12e6183f04d4 65 /*lint -e550 */
Kovalev_D 23:12e6183f04d4 66 /*lint -e754 */
Kovalev_D 23:12e6183f04d4 67 /*lint -e750 */
Kovalev_D 23:12e6183f04d4 68 /*lint -e528 */
Kovalev_D 23:12e6183f04d4 69 /*lint -e751 */
Kovalev_D 23:12e6183f04d4 70
Kovalev_D 23:12e6183f04d4 71
Kovalev_D 23:12e6183f04d4 72 /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
Kovalev_D 23:12e6183f04d4 73 This file defines all structures and symbols for CMSIS core:
Kovalev_D 23:12e6183f04d4 74 - CMSIS version number
Kovalev_D 23:12e6183f04d4 75 - Cortex-M core registers and bitfields
Kovalev_D 23:12e6183f04d4 76 - Cortex-M core peripheral base address
Kovalev_D 23:12e6183f04d4 77 @{
Kovalev_D 23:12e6183f04d4 78 */
Kovalev_D 23:12e6183f04d4 79
Kovalev_D 23:12e6183f04d4 80 #ifdef __cplusplus
Kovalev_D 23:12e6183f04d4 81 extern "C" {
Kovalev_D 23:12e6183f04d4 82 #endif
Kovalev_D 23:12e6183f04d4 83
Kovalev_D 23:12e6183f04d4 84 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
Kovalev_D 23:12e6183f04d4 85 #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
Kovalev_D 23:12e6183f04d4 86 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kovalev_D 23:12e6183f04d4 87
Kovalev_D 23:12e6183f04d4 88 #define __CORTEX_M (0x03) /*!< Cortex core */
Kovalev_D 23:12e6183f04d4 89
Kovalev_D 23:12e6183f04d4 90 #include <stdint.h> /* Include standard types */
Kovalev_D 23:12e6183f04d4 91
Kovalev_D 23:12e6183f04d4 92 #if defined (__ICCARM__)
Kovalev_D 23:12e6183f04d4 93 #include <intrinsics.h> /* IAR Intrinsics */
Kovalev_D 23:12e6183f04d4 94 #endif
Kovalev_D 23:12e6183f04d4 95
Kovalev_D 23:12e6183f04d4 96
Kovalev_D 23:12e6183f04d4 97 #ifndef __NVIC_PRIO_BITS
Kovalev_D 23:12e6183f04d4 98 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
Kovalev_D 23:12e6183f04d4 99 #endif
Kovalev_D 23:12e6183f04d4 100
Kovalev_D 23:12e6183f04d4 101
Kovalev_D 23:12e6183f04d4 102
Kovalev_D 23:12e6183f04d4 103
Kovalev_D 23:12e6183f04d4 104 /**
Kovalev_D 23:12e6183f04d4 105 * IO definitions
Kovalev_D 23:12e6183f04d4 106 *
Kovalev_D 23:12e6183f04d4 107 * define access restrictions to peripheral registers
Kovalev_D 23:12e6183f04d4 108 */
Kovalev_D 23:12e6183f04d4 109
Kovalev_D 23:12e6183f04d4 110 #ifdef __cplusplus
Kovalev_D 23:12e6183f04d4 111 #define __I volatile /*!< defines 'read only' permissions */
Kovalev_D 23:12e6183f04d4 112 #else
Kovalev_D 23:12e6183f04d4 113 #define __I volatile const /*!< defines 'read only' permissions */
Kovalev_D 23:12e6183f04d4 114 #endif
Kovalev_D 23:12e6183f04d4 115 #define __O volatile /*!< defines 'write only' permissions */
Kovalev_D 23:12e6183f04d4 116 #define __IO volatile /*!< defines 'read / write' permissions */
Kovalev_D 23:12e6183f04d4 117
Kovalev_D 23:12e6183f04d4 118
Kovalev_D 23:12e6183f04d4 119
Kovalev_D 23:12e6183f04d4 120 /*******************************************************************************
Kovalev_D 23:12e6183f04d4 121 * Register Abstraction
Kovalev_D 23:12e6183f04d4 122 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 123 /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
Kovalev_D 23:12e6183f04d4 124 @{
Kovalev_D 23:12e6183f04d4 125 */
Kovalev_D 23:12e6183f04d4 126
Kovalev_D 23:12e6183f04d4 127
Kovalev_D 23:12e6183f04d4 128 /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
Kovalev_D 23:12e6183f04d4 129 memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
Kovalev_D 23:12e6183f04d4 130 @{
Kovalev_D 23:12e6183f04d4 131 */
Kovalev_D 23:12e6183f04d4 132 typedef struct
Kovalev_D 23:12e6183f04d4 133 {
Kovalev_D 23:12e6183f04d4 134 __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
Kovalev_D 23:12e6183f04d4 135 uint32_t RESERVED0[24];
Kovalev_D 23:12e6183f04d4 136 __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
Kovalev_D 23:12e6183f04d4 137 uint32_t RSERVED1[24];
Kovalev_D 23:12e6183f04d4 138 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
Kovalev_D 23:12e6183f04d4 139 uint32_t RESERVED2[24];
Kovalev_D 23:12e6183f04d4 140 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
Kovalev_D 23:12e6183f04d4 141 uint32_t RESERVED3[24];
Kovalev_D 23:12e6183f04d4 142 __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
Kovalev_D 23:12e6183f04d4 143 uint32_t RESERVED4[56];
Kovalev_D 23:12e6183f04d4 144 __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
Kovalev_D 23:12e6183f04d4 145 uint32_t RESERVED5[644];
Kovalev_D 23:12e6183f04d4 146 __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
Kovalev_D 23:12e6183f04d4 147 } NVIC_Type;
Kovalev_D 23:12e6183f04d4 148 /*@}*/ /* end of group CMSIS_CM3_NVIC */
Kovalev_D 23:12e6183f04d4 149
Kovalev_D 23:12e6183f04d4 150
Kovalev_D 23:12e6183f04d4 151 /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
Kovalev_D 23:12e6183f04d4 152 memory mapped structure for System Control Block (SCB)
Kovalev_D 23:12e6183f04d4 153 @{
Kovalev_D 23:12e6183f04d4 154 */
Kovalev_D 23:12e6183f04d4 155 typedef struct
Kovalev_D 23:12e6183f04d4 156 {
Kovalev_D 23:12e6183f04d4 157 __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
Kovalev_D 23:12e6183f04d4 158 __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
Kovalev_D 23:12e6183f04d4 159 __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
Kovalev_D 23:12e6183f04d4 160 __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
Kovalev_D 23:12e6183f04d4 161 __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
Kovalev_D 23:12e6183f04d4 162 __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
Kovalev_D 23:12e6183f04d4 163 __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kovalev_D 23:12e6183f04d4 164 __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
Kovalev_D 23:12e6183f04d4 165 __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
Kovalev_D 23:12e6183f04d4 166 __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
Kovalev_D 23:12e6183f04d4 167 __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
Kovalev_D 23:12e6183f04d4 168 __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
Kovalev_D 23:12e6183f04d4 169 __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
Kovalev_D 23:12e6183f04d4 170 __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
Kovalev_D 23:12e6183f04d4 171 __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
Kovalev_D 23:12e6183f04d4 172 __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
Kovalev_D 23:12e6183f04d4 173 __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
Kovalev_D 23:12e6183f04d4 174 __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
Kovalev_D 23:12e6183f04d4 175 __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
Kovalev_D 23:12e6183f04d4 176 } SCB_Type;
Kovalev_D 23:12e6183f04d4 177
Kovalev_D 23:12e6183f04d4 178 /* SCB CPUID Register Definitions */
Kovalev_D 23:12e6183f04d4 179 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kovalev_D 23:12e6183f04d4 180 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kovalev_D 23:12e6183f04d4 181
Kovalev_D 23:12e6183f04d4 182 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kovalev_D 23:12e6183f04d4 183 #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kovalev_D 23:12e6183f04d4 184
Kovalev_D 23:12e6183f04d4 185 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kovalev_D 23:12e6183f04d4 186 #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kovalev_D 23:12e6183f04d4 187
Kovalev_D 23:12e6183f04d4 188 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kovalev_D 23:12e6183f04d4 189 #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kovalev_D 23:12e6183f04d4 190
Kovalev_D 23:12e6183f04d4 191 /* SCB Interrupt Control State Register Definitions */
Kovalev_D 23:12e6183f04d4 192 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kovalev_D 23:12e6183f04d4 193 #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kovalev_D 23:12e6183f04d4 194
Kovalev_D 23:12e6183f04d4 195 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kovalev_D 23:12e6183f04d4 196 #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kovalev_D 23:12e6183f04d4 197
Kovalev_D 23:12e6183f04d4 198 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kovalev_D 23:12e6183f04d4 199 #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kovalev_D 23:12e6183f04d4 200
Kovalev_D 23:12e6183f04d4 201 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kovalev_D 23:12e6183f04d4 202 #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kovalev_D 23:12e6183f04d4 203
Kovalev_D 23:12e6183f04d4 204 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kovalev_D 23:12e6183f04d4 205 #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kovalev_D 23:12e6183f04d4 206
Kovalev_D 23:12e6183f04d4 207 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kovalev_D 23:12e6183f04d4 208 #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kovalev_D 23:12e6183f04d4 209
Kovalev_D 23:12e6183f04d4 210 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kovalev_D 23:12e6183f04d4 211 #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kovalev_D 23:12e6183f04d4 212
Kovalev_D 23:12e6183f04d4 213 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kovalev_D 23:12e6183f04d4 214 #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kovalev_D 23:12e6183f04d4 215
Kovalev_D 23:12e6183f04d4 216 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kovalev_D 23:12e6183f04d4 217 #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kovalev_D 23:12e6183f04d4 218
Kovalev_D 23:12e6183f04d4 219 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kovalev_D 23:12e6183f04d4 220 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kovalev_D 23:12e6183f04d4 221
Kovalev_D 23:12e6183f04d4 222 /* SCB Interrupt Control State Register Definitions */
Kovalev_D 23:12e6183f04d4 223 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Kovalev_D 23:12e6183f04d4 224 #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kovalev_D 23:12e6183f04d4 225
Kovalev_D 23:12e6183f04d4 226 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kovalev_D 23:12e6183f04d4 227 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kovalev_D 23:12e6183f04d4 228
Kovalev_D 23:12e6183f04d4 229 /* SCB Application Interrupt and Reset Control Register Definitions */
Kovalev_D 23:12e6183f04d4 230 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kovalev_D 23:12e6183f04d4 231 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kovalev_D 23:12e6183f04d4 232
Kovalev_D 23:12e6183f04d4 233 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kovalev_D 23:12e6183f04d4 234 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kovalev_D 23:12e6183f04d4 235
Kovalev_D 23:12e6183f04d4 236 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kovalev_D 23:12e6183f04d4 237 #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kovalev_D 23:12e6183f04d4 238
Kovalev_D 23:12e6183f04d4 239 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kovalev_D 23:12e6183f04d4 240 #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kovalev_D 23:12e6183f04d4 241
Kovalev_D 23:12e6183f04d4 242 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kovalev_D 23:12e6183f04d4 243 #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kovalev_D 23:12e6183f04d4 244
Kovalev_D 23:12e6183f04d4 245 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kovalev_D 23:12e6183f04d4 246 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kovalev_D 23:12e6183f04d4 247
Kovalev_D 23:12e6183f04d4 248 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kovalev_D 23:12e6183f04d4 249 #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
Kovalev_D 23:12e6183f04d4 250
Kovalev_D 23:12e6183f04d4 251 /* SCB System Control Register Definitions */
Kovalev_D 23:12e6183f04d4 252 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kovalev_D 23:12e6183f04d4 253 #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kovalev_D 23:12e6183f04d4 254
Kovalev_D 23:12e6183f04d4 255 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kovalev_D 23:12e6183f04d4 256 #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kovalev_D 23:12e6183f04d4 257
Kovalev_D 23:12e6183f04d4 258 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kovalev_D 23:12e6183f04d4 259 #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kovalev_D 23:12e6183f04d4 260
Kovalev_D 23:12e6183f04d4 261 /* SCB Configuration Control Register Definitions */
Kovalev_D 23:12e6183f04d4 262 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kovalev_D 23:12e6183f04d4 263 #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kovalev_D 23:12e6183f04d4 264
Kovalev_D 23:12e6183f04d4 265 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kovalev_D 23:12e6183f04d4 266 #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kovalev_D 23:12e6183f04d4 267
Kovalev_D 23:12e6183f04d4 268 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kovalev_D 23:12e6183f04d4 269 #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kovalev_D 23:12e6183f04d4 270
Kovalev_D 23:12e6183f04d4 271 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kovalev_D 23:12e6183f04d4 272 #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kovalev_D 23:12e6183f04d4 273
Kovalev_D 23:12e6183f04d4 274 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kovalev_D 23:12e6183f04d4 275 #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kovalev_D 23:12e6183f04d4 276
Kovalev_D 23:12e6183f04d4 277 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kovalev_D 23:12e6183f04d4 278 #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
Kovalev_D 23:12e6183f04d4 279
Kovalev_D 23:12e6183f04d4 280 /* SCB System Handler Control and State Register Definitions */
Kovalev_D 23:12e6183f04d4 281 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kovalev_D 23:12e6183f04d4 282 #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kovalev_D 23:12e6183f04d4 283
Kovalev_D 23:12e6183f04d4 284 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kovalev_D 23:12e6183f04d4 285 #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kovalev_D 23:12e6183f04d4 286
Kovalev_D 23:12e6183f04d4 287 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kovalev_D 23:12e6183f04d4 288 #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kovalev_D 23:12e6183f04d4 289
Kovalev_D 23:12e6183f04d4 290 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kovalev_D 23:12e6183f04d4 291 #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kovalev_D 23:12e6183f04d4 292
Kovalev_D 23:12e6183f04d4 293 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kovalev_D 23:12e6183f04d4 294 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kovalev_D 23:12e6183f04d4 295
Kovalev_D 23:12e6183f04d4 296 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kovalev_D 23:12e6183f04d4 297 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kovalev_D 23:12e6183f04d4 298
Kovalev_D 23:12e6183f04d4 299 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kovalev_D 23:12e6183f04d4 300 #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kovalev_D 23:12e6183f04d4 301
Kovalev_D 23:12e6183f04d4 302 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kovalev_D 23:12e6183f04d4 303 #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kovalev_D 23:12e6183f04d4 304
Kovalev_D 23:12e6183f04d4 305 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kovalev_D 23:12e6183f04d4 306 #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kovalev_D 23:12e6183f04d4 307
Kovalev_D 23:12e6183f04d4 308 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kovalev_D 23:12e6183f04d4 309 #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kovalev_D 23:12e6183f04d4 310
Kovalev_D 23:12e6183f04d4 311 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kovalev_D 23:12e6183f04d4 312 #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kovalev_D 23:12e6183f04d4 313
Kovalev_D 23:12e6183f04d4 314 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kovalev_D 23:12e6183f04d4 315 #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kovalev_D 23:12e6183f04d4 316
Kovalev_D 23:12e6183f04d4 317 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kovalev_D 23:12e6183f04d4 318 #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kovalev_D 23:12e6183f04d4 319
Kovalev_D 23:12e6183f04d4 320 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kovalev_D 23:12e6183f04d4 321 #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kovalev_D 23:12e6183f04d4 322
Kovalev_D 23:12e6183f04d4 323 /* SCB Configurable Fault Status Registers Definitions */
Kovalev_D 23:12e6183f04d4 324 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kovalev_D 23:12e6183f04d4 325 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kovalev_D 23:12e6183f04d4 326
Kovalev_D 23:12e6183f04d4 327 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kovalev_D 23:12e6183f04d4 328 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kovalev_D 23:12e6183f04d4 329
Kovalev_D 23:12e6183f04d4 330 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kovalev_D 23:12e6183f04d4 331 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kovalev_D 23:12e6183f04d4 332
Kovalev_D 23:12e6183f04d4 333 /* SCB Hard Fault Status Registers Definitions */
Kovalev_D 23:12e6183f04d4 334 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kovalev_D 23:12e6183f04d4 335 #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kovalev_D 23:12e6183f04d4 336
Kovalev_D 23:12e6183f04d4 337 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kovalev_D 23:12e6183f04d4 338 #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kovalev_D 23:12e6183f04d4 339
Kovalev_D 23:12e6183f04d4 340 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kovalev_D 23:12e6183f04d4 341 #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kovalev_D 23:12e6183f04d4 342
Kovalev_D 23:12e6183f04d4 343 /* SCB Debug Fault Status Register Definitions */
Kovalev_D 23:12e6183f04d4 344 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kovalev_D 23:12e6183f04d4 345 #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kovalev_D 23:12e6183f04d4 346
Kovalev_D 23:12e6183f04d4 347 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kovalev_D 23:12e6183f04d4 348 #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kovalev_D 23:12e6183f04d4 349
Kovalev_D 23:12e6183f04d4 350 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kovalev_D 23:12e6183f04d4 351 #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kovalev_D 23:12e6183f04d4 352
Kovalev_D 23:12e6183f04d4 353 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kovalev_D 23:12e6183f04d4 354 #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kovalev_D 23:12e6183f04d4 355
Kovalev_D 23:12e6183f04d4 356 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kovalev_D 23:12e6183f04d4 357 #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
Kovalev_D 23:12e6183f04d4 358 /*@}*/ /* end of group CMSIS_CM3_SCB */
Kovalev_D 23:12e6183f04d4 359
Kovalev_D 23:12e6183f04d4 360
Kovalev_D 23:12e6183f04d4 361 /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
Kovalev_D 23:12e6183f04d4 362 memory mapped structure for SysTick
Kovalev_D 23:12e6183f04d4 363 @{
Kovalev_D 23:12e6183f04d4 364 */
Kovalev_D 23:12e6183f04d4 365 typedef struct
Kovalev_D 23:12e6183f04d4 366 {
Kovalev_D 23:12e6183f04d4 367 __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
Kovalev_D 23:12e6183f04d4 368 __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
Kovalev_D 23:12e6183f04d4 369 __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
Kovalev_D 23:12e6183f04d4 370 __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
Kovalev_D 23:12e6183f04d4 371 } SysTick_Type;
Kovalev_D 23:12e6183f04d4 372
Kovalev_D 23:12e6183f04d4 373 /* SysTick Control / Status Register Definitions */
Kovalev_D 23:12e6183f04d4 374 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kovalev_D 23:12e6183f04d4 375 #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kovalev_D 23:12e6183f04d4 376
Kovalev_D 23:12e6183f04d4 377 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kovalev_D 23:12e6183f04d4 378 #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kovalev_D 23:12e6183f04d4 379
Kovalev_D 23:12e6183f04d4 380 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kovalev_D 23:12e6183f04d4 381 #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kovalev_D 23:12e6183f04d4 382
Kovalev_D 23:12e6183f04d4 383 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kovalev_D 23:12e6183f04d4 384 #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kovalev_D 23:12e6183f04d4 385
Kovalev_D 23:12e6183f04d4 386 /* SysTick Reload Register Definitions */
Kovalev_D 23:12e6183f04d4 387 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kovalev_D 23:12e6183f04d4 388 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kovalev_D 23:12e6183f04d4 389
Kovalev_D 23:12e6183f04d4 390 /* SysTick Current Register Definitions */
Kovalev_D 23:12e6183f04d4 391 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kovalev_D 23:12e6183f04d4 392 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kovalev_D 23:12e6183f04d4 393
Kovalev_D 23:12e6183f04d4 394 /* SysTick Calibration Register Definitions */
Kovalev_D 23:12e6183f04d4 395 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kovalev_D 23:12e6183f04d4 396 #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kovalev_D 23:12e6183f04d4 397
Kovalev_D 23:12e6183f04d4 398 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kovalev_D 23:12e6183f04d4 399 #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kovalev_D 23:12e6183f04d4 400
Kovalev_D 23:12e6183f04d4 401 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kovalev_D 23:12e6183f04d4 402 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kovalev_D 23:12e6183f04d4 403 /*@}*/ /* end of group CMSIS_CM3_SysTick */
Kovalev_D 23:12e6183f04d4 404
Kovalev_D 23:12e6183f04d4 405
Kovalev_D 23:12e6183f04d4 406 /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
Kovalev_D 23:12e6183f04d4 407 memory mapped structure for Instrumentation Trace Macrocell (ITM)
Kovalev_D 23:12e6183f04d4 408 @{
Kovalev_D 23:12e6183f04d4 409 */
Kovalev_D 23:12e6183f04d4 410 typedef struct
Kovalev_D 23:12e6183f04d4 411 {
Kovalev_D 23:12e6183f04d4 412 __O union
Kovalev_D 23:12e6183f04d4 413 {
Kovalev_D 23:12e6183f04d4 414 __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
Kovalev_D 23:12e6183f04d4 415 __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
Kovalev_D 23:12e6183f04d4 416 __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
Kovalev_D 23:12e6183f04d4 417 } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
Kovalev_D 23:12e6183f04d4 418 uint32_t RESERVED0[864];
Kovalev_D 23:12e6183f04d4 419 __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
Kovalev_D 23:12e6183f04d4 420 uint32_t RESERVED1[15];
Kovalev_D 23:12e6183f04d4 421 __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
Kovalev_D 23:12e6183f04d4 422 uint32_t RESERVED2[15];
Kovalev_D 23:12e6183f04d4 423 __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
Kovalev_D 23:12e6183f04d4 424 uint32_t RESERVED3[29];
Kovalev_D 23:12e6183f04d4 425 __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
Kovalev_D 23:12e6183f04d4 426 __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
Kovalev_D 23:12e6183f04d4 427 __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
Kovalev_D 23:12e6183f04d4 428 uint32_t RESERVED4[43];
Kovalev_D 23:12e6183f04d4 429 __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
Kovalev_D 23:12e6183f04d4 430 __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
Kovalev_D 23:12e6183f04d4 431 uint32_t RESERVED5[6];
Kovalev_D 23:12e6183f04d4 432 __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
Kovalev_D 23:12e6183f04d4 433 __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
Kovalev_D 23:12e6183f04d4 434 __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
Kovalev_D 23:12e6183f04d4 435 __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
Kovalev_D 23:12e6183f04d4 436 __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
Kovalev_D 23:12e6183f04d4 437 __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
Kovalev_D 23:12e6183f04d4 438 __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
Kovalev_D 23:12e6183f04d4 439 __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
Kovalev_D 23:12e6183f04d4 440 __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
Kovalev_D 23:12e6183f04d4 441 __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
Kovalev_D 23:12e6183f04d4 442 __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
Kovalev_D 23:12e6183f04d4 443 __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
Kovalev_D 23:12e6183f04d4 444 } ITM_Type;
Kovalev_D 23:12e6183f04d4 445
Kovalev_D 23:12e6183f04d4 446 /* ITM Trace Privilege Register Definitions */
Kovalev_D 23:12e6183f04d4 447 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kovalev_D 23:12e6183f04d4 448 #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
Kovalev_D 23:12e6183f04d4 449
Kovalev_D 23:12e6183f04d4 450 /* ITM Trace Control Register Definitions */
Kovalev_D 23:12e6183f04d4 451 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kovalev_D 23:12e6183f04d4 452 #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kovalev_D 23:12e6183f04d4 453
Kovalev_D 23:12e6183f04d4 454 #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
Kovalev_D 23:12e6183f04d4 455 #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
Kovalev_D 23:12e6183f04d4 456
Kovalev_D 23:12e6183f04d4 457 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kovalev_D 23:12e6183f04d4 458 #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kovalev_D 23:12e6183f04d4 459
Kovalev_D 23:12e6183f04d4 460 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kovalev_D 23:12e6183f04d4 461 #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kovalev_D 23:12e6183f04d4 462
Kovalev_D 23:12e6183f04d4 463 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kovalev_D 23:12e6183f04d4 464 #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kovalev_D 23:12e6183f04d4 465
Kovalev_D 23:12e6183f04d4 466 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kovalev_D 23:12e6183f04d4 467 #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kovalev_D 23:12e6183f04d4 468
Kovalev_D 23:12e6183f04d4 469 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kovalev_D 23:12e6183f04d4 470 #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kovalev_D 23:12e6183f04d4 471
Kovalev_D 23:12e6183f04d4 472 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kovalev_D 23:12e6183f04d4 473 #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
Kovalev_D 23:12e6183f04d4 474
Kovalev_D 23:12e6183f04d4 475 /* ITM Integration Write Register Definitions */
Kovalev_D 23:12e6183f04d4 476 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kovalev_D 23:12e6183f04d4 477 #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
Kovalev_D 23:12e6183f04d4 478
Kovalev_D 23:12e6183f04d4 479 /* ITM Integration Read Register Definitions */
Kovalev_D 23:12e6183f04d4 480 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kovalev_D 23:12e6183f04d4 481 #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
Kovalev_D 23:12e6183f04d4 482
Kovalev_D 23:12e6183f04d4 483 /* ITM Integration Mode Control Register Definitions */
Kovalev_D 23:12e6183f04d4 484 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kovalev_D 23:12e6183f04d4 485 #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
Kovalev_D 23:12e6183f04d4 486
Kovalev_D 23:12e6183f04d4 487 /* ITM Lock Status Register Definitions */
Kovalev_D 23:12e6183f04d4 488 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kovalev_D 23:12e6183f04d4 489 #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kovalev_D 23:12e6183f04d4 490
Kovalev_D 23:12e6183f04d4 491 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kovalev_D 23:12e6183f04d4 492 #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kovalev_D 23:12e6183f04d4 493
Kovalev_D 23:12e6183f04d4 494 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kovalev_D 23:12e6183f04d4 495 #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
Kovalev_D 23:12e6183f04d4 496 /*@}*/ /* end of group CMSIS_CM3_ITM */
Kovalev_D 23:12e6183f04d4 497
Kovalev_D 23:12e6183f04d4 498
Kovalev_D 23:12e6183f04d4 499 /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
Kovalev_D 23:12e6183f04d4 500 memory mapped structure for Interrupt Type
Kovalev_D 23:12e6183f04d4 501 @{
Kovalev_D 23:12e6183f04d4 502 */
Kovalev_D 23:12e6183f04d4 503 typedef struct
Kovalev_D 23:12e6183f04d4 504 {
Kovalev_D 23:12e6183f04d4 505 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 506 __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
Kovalev_D 23:12e6183f04d4 507 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Kovalev_D 23:12e6183f04d4 508 __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
Kovalev_D 23:12e6183f04d4 509 #else
Kovalev_D 23:12e6183f04d4 510 uint32_t RESERVED1;
Kovalev_D 23:12e6183f04d4 511 #endif
Kovalev_D 23:12e6183f04d4 512 } InterruptType_Type;
Kovalev_D 23:12e6183f04d4 513
Kovalev_D 23:12e6183f04d4 514 /* Interrupt Controller Type Register Definitions */
Kovalev_D 23:12e6183f04d4 515 #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
Kovalev_D 23:12e6183f04d4 516 #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
Kovalev_D 23:12e6183f04d4 517
Kovalev_D 23:12e6183f04d4 518 /* Auxiliary Control Register Definitions */
Kovalev_D 23:12e6183f04d4 519 #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
Kovalev_D 23:12e6183f04d4 520 #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
Kovalev_D 23:12e6183f04d4 521
Kovalev_D 23:12e6183f04d4 522 #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
Kovalev_D 23:12e6183f04d4 523 #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
Kovalev_D 23:12e6183f04d4 524
Kovalev_D 23:12e6183f04d4 525 #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
Kovalev_D 23:12e6183f04d4 526 #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
Kovalev_D 23:12e6183f04d4 527 /*@}*/ /* end of group CMSIS_CM3_InterruptType */
Kovalev_D 23:12e6183f04d4 528
Kovalev_D 23:12e6183f04d4 529
Kovalev_D 23:12e6183f04d4 530 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
Kovalev_D 23:12e6183f04d4 531 /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
Kovalev_D 23:12e6183f04d4 532 memory mapped structure for Memory Protection Unit (MPU)
Kovalev_D 23:12e6183f04d4 533 @{
Kovalev_D 23:12e6183f04d4 534 */
Kovalev_D 23:12e6183f04d4 535 typedef struct
Kovalev_D 23:12e6183f04d4 536 {
Kovalev_D 23:12e6183f04d4 537 __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
Kovalev_D 23:12e6183f04d4 538 __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
Kovalev_D 23:12e6183f04d4 539 __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
Kovalev_D 23:12e6183f04d4 540 __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
Kovalev_D 23:12e6183f04d4 541 __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 542 __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
Kovalev_D 23:12e6183f04d4 543 __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 544 __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
Kovalev_D 23:12e6183f04d4 545 __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 546 __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
Kovalev_D 23:12e6183f04d4 547 __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 548 } MPU_Type;
Kovalev_D 23:12e6183f04d4 549
Kovalev_D 23:12e6183f04d4 550 /* MPU Type Register */
Kovalev_D 23:12e6183f04d4 551 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kovalev_D 23:12e6183f04d4 552 #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kovalev_D 23:12e6183f04d4 553
Kovalev_D 23:12e6183f04d4 554 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kovalev_D 23:12e6183f04d4 555 #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kovalev_D 23:12e6183f04d4 556
Kovalev_D 23:12e6183f04d4 557 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kovalev_D 23:12e6183f04d4 558 #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kovalev_D 23:12e6183f04d4 559
Kovalev_D 23:12e6183f04d4 560 /* MPU Control Register */
Kovalev_D 23:12e6183f04d4 561 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kovalev_D 23:12e6183f04d4 562 #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kovalev_D 23:12e6183f04d4 563
Kovalev_D 23:12e6183f04d4 564 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kovalev_D 23:12e6183f04d4 565 #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kovalev_D 23:12e6183f04d4 566
Kovalev_D 23:12e6183f04d4 567 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kovalev_D 23:12e6183f04d4 568 #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kovalev_D 23:12e6183f04d4 569
Kovalev_D 23:12e6183f04d4 570 /* MPU Region Number Register */
Kovalev_D 23:12e6183f04d4 571 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kovalev_D 23:12e6183f04d4 572 #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kovalev_D 23:12e6183f04d4 573
Kovalev_D 23:12e6183f04d4 574 /* MPU Region Base Address Register */
Kovalev_D 23:12e6183f04d4 575 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kovalev_D 23:12e6183f04d4 576 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kovalev_D 23:12e6183f04d4 577
Kovalev_D 23:12e6183f04d4 578 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kovalev_D 23:12e6183f04d4 579 #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kovalev_D 23:12e6183f04d4 580
Kovalev_D 23:12e6183f04d4 581 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kovalev_D 23:12e6183f04d4 582 #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kovalev_D 23:12e6183f04d4 583
Kovalev_D 23:12e6183f04d4 584 /* MPU Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
Kovalev_D 23:12e6183f04d4 586 #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
Kovalev_D 23:12e6183f04d4 587
Kovalev_D 23:12e6183f04d4 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
Kovalev_D 23:12e6183f04d4 589 #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
Kovalev_D 23:12e6183f04d4 590
Kovalev_D 23:12e6183f04d4 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
Kovalev_D 23:12e6183f04d4 592 #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
Kovalev_D 23:12e6183f04d4 593
Kovalev_D 23:12e6183f04d4 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
Kovalev_D 23:12e6183f04d4 595 #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
Kovalev_D 23:12e6183f04d4 596
Kovalev_D 23:12e6183f04d4 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
Kovalev_D 23:12e6183f04d4 598 #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
Kovalev_D 23:12e6183f04d4 599
Kovalev_D 23:12e6183f04d4 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
Kovalev_D 23:12e6183f04d4 601 #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
Kovalev_D 23:12e6183f04d4 602
Kovalev_D 23:12e6183f04d4 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kovalev_D 23:12e6183f04d4 604 #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kovalev_D 23:12e6183f04d4 605
Kovalev_D 23:12e6183f04d4 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kovalev_D 23:12e6183f04d4 607 #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kovalev_D 23:12e6183f04d4 608
Kovalev_D 23:12e6183f04d4 609 #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kovalev_D 23:12e6183f04d4 610 #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kovalev_D 23:12e6183f04d4 611
Kovalev_D 23:12e6183f04d4 612 /*@}*/ /* end of group CMSIS_CM3_MPU */
Kovalev_D 23:12e6183f04d4 613 #endif
Kovalev_D 23:12e6183f04d4 614
Kovalev_D 23:12e6183f04d4 615
Kovalev_D 23:12e6183f04d4 616 /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
Kovalev_D 23:12e6183f04d4 617 memory mapped structure for Core Debug Register
Kovalev_D 23:12e6183f04d4 618 @{
Kovalev_D 23:12e6183f04d4 619 */
Kovalev_D 23:12e6183f04d4 620 typedef struct
Kovalev_D 23:12e6183f04d4 621 {
Kovalev_D 23:12e6183f04d4 622 __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
Kovalev_D 23:12e6183f04d4 623 __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
Kovalev_D 23:12e6183f04d4 624 __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
Kovalev_D 23:12e6183f04d4 625 __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
Kovalev_D 23:12e6183f04d4 626 } CoreDebug_Type;
Kovalev_D 23:12e6183f04d4 627
Kovalev_D 23:12e6183f04d4 628 /* Debug Halting Control and Status Register */
Kovalev_D 23:12e6183f04d4 629 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kovalev_D 23:12e6183f04d4 630 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kovalev_D 23:12e6183f04d4 631
Kovalev_D 23:12e6183f04d4 632 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kovalev_D 23:12e6183f04d4 633 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kovalev_D 23:12e6183f04d4 634
Kovalev_D 23:12e6183f04d4 635 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kovalev_D 23:12e6183f04d4 636 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kovalev_D 23:12e6183f04d4 637
Kovalev_D 23:12e6183f04d4 638 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kovalev_D 23:12e6183f04d4 639 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kovalev_D 23:12e6183f04d4 640
Kovalev_D 23:12e6183f04d4 641 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kovalev_D 23:12e6183f04d4 642 #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kovalev_D 23:12e6183f04d4 643
Kovalev_D 23:12e6183f04d4 644 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kovalev_D 23:12e6183f04d4 645 #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kovalev_D 23:12e6183f04d4 646
Kovalev_D 23:12e6183f04d4 647 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kovalev_D 23:12e6183f04d4 648 #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kovalev_D 23:12e6183f04d4 649
Kovalev_D 23:12e6183f04d4 650 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kovalev_D 23:12e6183f04d4 651 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kovalev_D 23:12e6183f04d4 652
Kovalev_D 23:12e6183f04d4 653 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kovalev_D 23:12e6183f04d4 654 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kovalev_D 23:12e6183f04d4 655
Kovalev_D 23:12e6183f04d4 656 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kovalev_D 23:12e6183f04d4 657 #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kovalev_D 23:12e6183f04d4 658
Kovalev_D 23:12e6183f04d4 659 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kovalev_D 23:12e6183f04d4 660 #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kovalev_D 23:12e6183f04d4 661
Kovalev_D 23:12e6183f04d4 662 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kovalev_D 23:12e6183f04d4 663 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kovalev_D 23:12e6183f04d4 664
Kovalev_D 23:12e6183f04d4 665 /* Debug Core Register Selector Register */
Kovalev_D 23:12e6183f04d4 666 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kovalev_D 23:12e6183f04d4 667 #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kovalev_D 23:12e6183f04d4 668
Kovalev_D 23:12e6183f04d4 669 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kovalev_D 23:12e6183f04d4 670 #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
Kovalev_D 23:12e6183f04d4 671
Kovalev_D 23:12e6183f04d4 672 /* Debug Exception and Monitor Control Register */
Kovalev_D 23:12e6183f04d4 673 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kovalev_D 23:12e6183f04d4 674 #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kovalev_D 23:12e6183f04d4 675
Kovalev_D 23:12e6183f04d4 676 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kovalev_D 23:12e6183f04d4 677 #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kovalev_D 23:12e6183f04d4 678
Kovalev_D 23:12e6183f04d4 679 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kovalev_D 23:12e6183f04d4 680 #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kovalev_D 23:12e6183f04d4 681
Kovalev_D 23:12e6183f04d4 682 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kovalev_D 23:12e6183f04d4 683 #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kovalev_D 23:12e6183f04d4 684
Kovalev_D 23:12e6183f04d4 685 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kovalev_D 23:12e6183f04d4 686 #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kovalev_D 23:12e6183f04d4 687
Kovalev_D 23:12e6183f04d4 688 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kovalev_D 23:12e6183f04d4 689 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kovalev_D 23:12e6183f04d4 690
Kovalev_D 23:12e6183f04d4 691 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kovalev_D 23:12e6183f04d4 692 #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kovalev_D 23:12e6183f04d4 693
Kovalev_D 23:12e6183f04d4 694 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kovalev_D 23:12e6183f04d4 695 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kovalev_D 23:12e6183f04d4 696
Kovalev_D 23:12e6183f04d4 697 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kovalev_D 23:12e6183f04d4 698 #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kovalev_D 23:12e6183f04d4 699
Kovalev_D 23:12e6183f04d4 700 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kovalev_D 23:12e6183f04d4 701 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kovalev_D 23:12e6183f04d4 702
Kovalev_D 23:12e6183f04d4 703 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kovalev_D 23:12e6183f04d4 704 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kovalev_D 23:12e6183f04d4 705
Kovalev_D 23:12e6183f04d4 706 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kovalev_D 23:12e6183f04d4 707 #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kovalev_D 23:12e6183f04d4 708
Kovalev_D 23:12e6183f04d4 709 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kovalev_D 23:12e6183f04d4 710 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kovalev_D 23:12e6183f04d4 711 /*@}*/ /* end of group CMSIS_CM3_CoreDebug */
Kovalev_D 23:12e6183f04d4 712
Kovalev_D 23:12e6183f04d4 713
Kovalev_D 23:12e6183f04d4 714 /* Memory mapping of Cortex-M3 Hardware */
Kovalev_D 23:12e6183f04d4 715 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
Kovalev_D 23:12e6183f04d4 716 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */
Kovalev_D 23:12e6183f04d4 717 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
Kovalev_D 23:12e6183f04d4 718 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
Kovalev_D 23:12e6183f04d4 719 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
Kovalev_D 23:12e6183f04d4 720 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
Kovalev_D 23:12e6183f04d4 721
Kovalev_D 23:12e6183f04d4 722 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
Kovalev_D 23:12e6183f04d4 723 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
Kovalev_D 23:12e6183f04d4 724 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
Kovalev_D 23:12e6183f04d4 725 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
Kovalev_D 23:12e6183f04d4 726 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
Kovalev_D 23:12e6183f04d4 727 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kovalev_D 23:12e6183f04d4 728
Kovalev_D 23:12e6183f04d4 729 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
Kovalev_D 23:12e6183f04d4 730 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
Kovalev_D 23:12e6183f04d4 731 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
Kovalev_D 23:12e6183f04d4 732 #endif
Kovalev_D 23:12e6183f04d4 733
Kovalev_D 23:12e6183f04d4 734 /*@}*/ /* end of group CMSIS_CM3_core_register */
Kovalev_D 23:12e6183f04d4 735
Kovalev_D 23:12e6183f04d4 736
Kovalev_D 23:12e6183f04d4 737 /*******************************************************************************
Kovalev_D 23:12e6183f04d4 738 * Hardware Abstraction Layer
Kovalev_D 23:12e6183f04d4 739 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 740
Kovalev_D 23:12e6183f04d4 741 #if defined ( __CC_ARM )
Kovalev_D 23:12e6183f04d4 742 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kovalev_D 23:12e6183f04d4 743 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kovalev_D 23:12e6183f04d4 744
Kovalev_D 23:12e6183f04d4 745 #elif defined ( __ICCARM__ )
Kovalev_D 23:12e6183f04d4 746 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kovalev_D 23:12e6183f04d4 747 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
Kovalev_D 23:12e6183f04d4 748
Kovalev_D 23:12e6183f04d4 749 #elif defined ( __GNUC__ )
Kovalev_D 23:12e6183f04d4 750 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kovalev_D 23:12e6183f04d4 751 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kovalev_D 23:12e6183f04d4 752
Kovalev_D 23:12e6183f04d4 753 #elif defined ( __TASKING__ )
Kovalev_D 23:12e6183f04d4 754 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kovalev_D 23:12e6183f04d4 755 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kovalev_D 23:12e6183f04d4 756
Kovalev_D 23:12e6183f04d4 757 #endif
Kovalev_D 23:12e6183f04d4 758
Kovalev_D 23:12e6183f04d4 759
Kovalev_D 23:12e6183f04d4 760 /* ################### Compiler specific Intrinsics ########################### */
Kovalev_D 23:12e6183f04d4 761
Kovalev_D 23:12e6183f04d4 762 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kovalev_D 23:12e6183f04d4 763 /* ARM armcc specific functions */
Kovalev_D 23:12e6183f04d4 764
Kovalev_D 23:12e6183f04d4 765 #define __enable_fault_irq __enable_fiq
Kovalev_D 23:12e6183f04d4 766 #define __disable_fault_irq __disable_fiq
Kovalev_D 23:12e6183f04d4 767
Kovalev_D 23:12e6183f04d4 768 #define __NOP __nop
Kovalev_D 23:12e6183f04d4 769 #define __WFI __wfi
Kovalev_D 23:12e6183f04d4 770 #define __WFE __wfe
Kovalev_D 23:12e6183f04d4 771 #define __SEV __sev
Kovalev_D 23:12e6183f04d4 772 #define __ISB() __isb(0)
Kovalev_D 23:12e6183f04d4 773 #define __DSB() __dsb(0)
Kovalev_D 23:12e6183f04d4 774 #define __DMB() __dmb(0)
Kovalev_D 23:12e6183f04d4 775 #define __REV __rev
Kovalev_D 23:12e6183f04d4 776 #define __RBIT __rbit
Kovalev_D 23:12e6183f04d4 777 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
Kovalev_D 23:12e6183f04d4 778 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
Kovalev_D 23:12e6183f04d4 779 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
Kovalev_D 23:12e6183f04d4 780 #define __STREXB(value, ptr) __strex(value, ptr)
Kovalev_D 23:12e6183f04d4 781 #define __STREXH(value, ptr) __strex(value, ptr)
Kovalev_D 23:12e6183f04d4 782 #define __STREXW(value, ptr) __strex(value, ptr)
Kovalev_D 23:12e6183f04d4 783
Kovalev_D 23:12e6183f04d4 784
Kovalev_D 23:12e6183f04d4 785 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
Kovalev_D 23:12e6183f04d4 786 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
Kovalev_D 23:12e6183f04d4 787 /* intrinsic void __enable_irq(); */
Kovalev_D 23:12e6183f04d4 788 /* intrinsic void __disable_irq(); */
Kovalev_D 23:12e6183f04d4 789
Kovalev_D 23:12e6183f04d4 790
Kovalev_D 23:12e6183f04d4 791 /**
Kovalev_D 23:12e6183f04d4 792 * @brief Return the Process Stack Pointer
Kovalev_D 23:12e6183f04d4 793 *
Kovalev_D 23:12e6183f04d4 794 * @return ProcessStackPointer
Kovalev_D 23:12e6183f04d4 795 *
Kovalev_D 23:12e6183f04d4 796 * Return the actual process stack pointer
Kovalev_D 23:12e6183f04d4 797 */
Kovalev_D 23:12e6183f04d4 798 extern uint32_t __get_PSP(void);
Kovalev_D 23:12e6183f04d4 799
Kovalev_D 23:12e6183f04d4 800 /**
Kovalev_D 23:12e6183f04d4 801 * @brief Set the Process Stack Pointer
Kovalev_D 23:12e6183f04d4 802 *
Kovalev_D 23:12e6183f04d4 803 * @param topOfProcStack Process Stack Pointer
Kovalev_D 23:12e6183f04d4 804 *
Kovalev_D 23:12e6183f04d4 805 * Assign the value ProcessStackPointer to the MSP
Kovalev_D 23:12e6183f04d4 806 * (process stack pointer) Cortex processor register
Kovalev_D 23:12e6183f04d4 807 */
Kovalev_D 23:12e6183f04d4 808 extern void __set_PSP(uint32_t topOfProcStack);
Kovalev_D 23:12e6183f04d4 809
Kovalev_D 23:12e6183f04d4 810 /**
Kovalev_D 23:12e6183f04d4 811 * @brief Return the Main Stack Pointer
Kovalev_D 23:12e6183f04d4 812 *
Kovalev_D 23:12e6183f04d4 813 * @return Main Stack Pointer
Kovalev_D 23:12e6183f04d4 814 *
Kovalev_D 23:12e6183f04d4 815 * Return the current value of the MSP (main stack pointer)
Kovalev_D 23:12e6183f04d4 816 * Cortex processor register
Kovalev_D 23:12e6183f04d4 817 */
Kovalev_D 23:12e6183f04d4 818 extern uint32_t __get_MSP(void);
Kovalev_D 23:12e6183f04d4 819
Kovalev_D 23:12e6183f04d4 820 /**
Kovalev_D 23:12e6183f04d4 821 * @brief Set the Main Stack Pointer
Kovalev_D 23:12e6183f04d4 822 *
Kovalev_D 23:12e6183f04d4 823 * @param topOfMainStack Main Stack Pointer
Kovalev_D 23:12e6183f04d4 824 *
Kovalev_D 23:12e6183f04d4 825 * Assign the value mainStackPointer to the MSP
Kovalev_D 23:12e6183f04d4 826 * (main stack pointer) Cortex processor register
Kovalev_D 23:12e6183f04d4 827 */
Kovalev_D 23:12e6183f04d4 828 extern void __set_MSP(uint32_t topOfMainStack);
Kovalev_D 23:12e6183f04d4 829
Kovalev_D 23:12e6183f04d4 830 /**
Kovalev_D 23:12e6183f04d4 831 * @brief Reverse byte order in unsigned short value
Kovalev_D 23:12e6183f04d4 832 *
Kovalev_D 23:12e6183f04d4 833 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 834 * @return reversed value
Kovalev_D 23:12e6183f04d4 835 *
Kovalev_D 23:12e6183f04d4 836 * Reverse byte order in unsigned short value
Kovalev_D 23:12e6183f04d4 837 */
Kovalev_D 23:12e6183f04d4 838 extern uint32_t __REV16(uint16_t value);
Kovalev_D 23:12e6183f04d4 839
Kovalev_D 23:12e6183f04d4 840 /**
Kovalev_D 23:12e6183f04d4 841 * @brief Reverse byte order in signed short value with sign extension to integer
Kovalev_D 23:12e6183f04d4 842 *
Kovalev_D 23:12e6183f04d4 843 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 844 * @return reversed value
Kovalev_D 23:12e6183f04d4 845 *
Kovalev_D 23:12e6183f04d4 846 * Reverse byte order in signed short value with sign extension to integer
Kovalev_D 23:12e6183f04d4 847 */
Kovalev_D 23:12e6183f04d4 848 extern int32_t __REVSH(int16_t value);
Kovalev_D 23:12e6183f04d4 849
Kovalev_D 23:12e6183f04d4 850
Kovalev_D 23:12e6183f04d4 851 #if (__ARMCC_VERSION < 400000)
Kovalev_D 23:12e6183f04d4 852
Kovalev_D 23:12e6183f04d4 853 /**
Kovalev_D 23:12e6183f04d4 854 * @brief Remove the exclusive lock created by ldrex
Kovalev_D 23:12e6183f04d4 855 *
Kovalev_D 23:12e6183f04d4 856 * Removes the exclusive lock which is created by ldrex.
Kovalev_D 23:12e6183f04d4 857 */
Kovalev_D 23:12e6183f04d4 858 extern void __CLREX(void);
Kovalev_D 23:12e6183f04d4 859
Kovalev_D 23:12e6183f04d4 860 /**
Kovalev_D 23:12e6183f04d4 861 * @brief Return the Base Priority value
Kovalev_D 23:12e6183f04d4 862 *
Kovalev_D 23:12e6183f04d4 863 * @return BasePriority
Kovalev_D 23:12e6183f04d4 864 *
Kovalev_D 23:12e6183f04d4 865 * Return the content of the base priority register
Kovalev_D 23:12e6183f04d4 866 */
Kovalev_D 23:12e6183f04d4 867 extern uint32_t __get_BASEPRI(void);
Kovalev_D 23:12e6183f04d4 868
Kovalev_D 23:12e6183f04d4 869 /**
Kovalev_D 23:12e6183f04d4 870 * @brief Set the Base Priority value
Kovalev_D 23:12e6183f04d4 871 *
Kovalev_D 23:12e6183f04d4 872 * @param basePri BasePriority
Kovalev_D 23:12e6183f04d4 873 *
Kovalev_D 23:12e6183f04d4 874 * Set the base priority register
Kovalev_D 23:12e6183f04d4 875 */
Kovalev_D 23:12e6183f04d4 876 extern void __set_BASEPRI(uint32_t basePri);
Kovalev_D 23:12e6183f04d4 877
Kovalev_D 23:12e6183f04d4 878 /**
Kovalev_D 23:12e6183f04d4 879 * @brief Return the Priority Mask value
Kovalev_D 23:12e6183f04d4 880 *
Kovalev_D 23:12e6183f04d4 881 * @return PriMask
Kovalev_D 23:12e6183f04d4 882 *
Kovalev_D 23:12e6183f04d4 883 * Return state of the priority mask bit from the priority mask register
Kovalev_D 23:12e6183f04d4 884 */
Kovalev_D 23:12e6183f04d4 885 extern uint32_t __get_PRIMASK(void);
Kovalev_D 23:12e6183f04d4 886
Kovalev_D 23:12e6183f04d4 887 /**
Kovalev_D 23:12e6183f04d4 888 * @brief Set the Priority Mask value
Kovalev_D 23:12e6183f04d4 889 *
Kovalev_D 23:12e6183f04d4 890 * @param priMask PriMask
Kovalev_D 23:12e6183f04d4 891 *
Kovalev_D 23:12e6183f04d4 892 * Set the priority mask bit in the priority mask register
Kovalev_D 23:12e6183f04d4 893 */
Kovalev_D 23:12e6183f04d4 894 extern void __set_PRIMASK(uint32_t priMask);
Kovalev_D 23:12e6183f04d4 895
Kovalev_D 23:12e6183f04d4 896 /**
Kovalev_D 23:12e6183f04d4 897 * @brief Return the Fault Mask value
Kovalev_D 23:12e6183f04d4 898 *
Kovalev_D 23:12e6183f04d4 899 * @return FaultMask
Kovalev_D 23:12e6183f04d4 900 *
Kovalev_D 23:12e6183f04d4 901 * Return the content of the fault mask register
Kovalev_D 23:12e6183f04d4 902 */
Kovalev_D 23:12e6183f04d4 903 extern uint32_t __get_FAULTMASK(void);
Kovalev_D 23:12e6183f04d4 904
Kovalev_D 23:12e6183f04d4 905 /**
Kovalev_D 23:12e6183f04d4 906 * @brief Set the Fault Mask value
Kovalev_D 23:12e6183f04d4 907 *
Kovalev_D 23:12e6183f04d4 908 * @param faultMask faultMask value
Kovalev_D 23:12e6183f04d4 909 *
Kovalev_D 23:12e6183f04d4 910 * Set the fault mask register
Kovalev_D 23:12e6183f04d4 911 */
Kovalev_D 23:12e6183f04d4 912 extern void __set_FAULTMASK(uint32_t faultMask);
Kovalev_D 23:12e6183f04d4 913
Kovalev_D 23:12e6183f04d4 914 /**
Kovalev_D 23:12e6183f04d4 915 * @brief Return the Control Register value
Kovalev_D 23:12e6183f04d4 916 *
Kovalev_D 23:12e6183f04d4 917 * @return Control value
Kovalev_D 23:12e6183f04d4 918 *
Kovalev_D 23:12e6183f04d4 919 * Return the content of the control register
Kovalev_D 23:12e6183f04d4 920 */
Kovalev_D 23:12e6183f04d4 921 extern uint32_t __get_CONTROL(void);
Kovalev_D 23:12e6183f04d4 922
Kovalev_D 23:12e6183f04d4 923 /**
Kovalev_D 23:12e6183f04d4 924 * @brief Set the Control Register value
Kovalev_D 23:12e6183f04d4 925 *
Kovalev_D 23:12e6183f04d4 926 * @param control Control value
Kovalev_D 23:12e6183f04d4 927 *
Kovalev_D 23:12e6183f04d4 928 * Set the control register
Kovalev_D 23:12e6183f04d4 929 */
Kovalev_D 23:12e6183f04d4 930 extern void __set_CONTROL(uint32_t control);
Kovalev_D 23:12e6183f04d4 931
Kovalev_D 23:12e6183f04d4 932 #else /* (__ARMCC_VERSION >= 400000) */
Kovalev_D 23:12e6183f04d4 933
Kovalev_D 23:12e6183f04d4 934 /**
Kovalev_D 23:12e6183f04d4 935 * @brief Remove the exclusive lock created by ldrex
Kovalev_D 23:12e6183f04d4 936 *
Kovalev_D 23:12e6183f04d4 937 * Removes the exclusive lock which is created by ldrex.
Kovalev_D 23:12e6183f04d4 938 */
Kovalev_D 23:12e6183f04d4 939 #define __CLREX __clrex
Kovalev_D 23:12e6183f04d4 940
Kovalev_D 23:12e6183f04d4 941 /**
Kovalev_D 23:12e6183f04d4 942 * @brief Return the Base Priority value
Kovalev_D 23:12e6183f04d4 943 *
Kovalev_D 23:12e6183f04d4 944 * @return BasePriority
Kovalev_D 23:12e6183f04d4 945 *
Kovalev_D 23:12e6183f04d4 946 * Return the content of the base priority register
Kovalev_D 23:12e6183f04d4 947 */
Kovalev_D 23:12e6183f04d4 948 static __INLINE uint32_t __get_BASEPRI(void)
Kovalev_D 23:12e6183f04d4 949 {
Kovalev_D 23:12e6183f04d4 950 register uint32_t __regBasePri __ASM("basepri");
Kovalev_D 23:12e6183f04d4 951 return(__regBasePri);
Kovalev_D 23:12e6183f04d4 952 }
Kovalev_D 23:12e6183f04d4 953
Kovalev_D 23:12e6183f04d4 954 /**
Kovalev_D 23:12e6183f04d4 955 * @brief Set the Base Priority value
Kovalev_D 23:12e6183f04d4 956 *
Kovalev_D 23:12e6183f04d4 957 * @param basePri BasePriority
Kovalev_D 23:12e6183f04d4 958 *
Kovalev_D 23:12e6183f04d4 959 * Set the base priority register
Kovalev_D 23:12e6183f04d4 960 */
Kovalev_D 23:12e6183f04d4 961 static __INLINE void __set_BASEPRI(uint32_t basePri)
Kovalev_D 23:12e6183f04d4 962 {
Kovalev_D 23:12e6183f04d4 963 register uint32_t __regBasePri __ASM("basepri");
Kovalev_D 23:12e6183f04d4 964 __regBasePri = (basePri & 0xff);
Kovalev_D 23:12e6183f04d4 965 }
Kovalev_D 23:12e6183f04d4 966
Kovalev_D 23:12e6183f04d4 967 /**
Kovalev_D 23:12e6183f04d4 968 * @brief Return the Priority Mask value
Kovalev_D 23:12e6183f04d4 969 *
Kovalev_D 23:12e6183f04d4 970 * @return PriMask
Kovalev_D 23:12e6183f04d4 971 *
Kovalev_D 23:12e6183f04d4 972 * Return state of the priority mask bit from the priority mask register
Kovalev_D 23:12e6183f04d4 973 */
Kovalev_D 23:12e6183f04d4 974 static __INLINE uint32_t __get_PRIMASK(void)
Kovalev_D 23:12e6183f04d4 975 {
Kovalev_D 23:12e6183f04d4 976 register uint32_t __regPriMask __ASM("primask");
Kovalev_D 23:12e6183f04d4 977 return(__regPriMask);
Kovalev_D 23:12e6183f04d4 978 }
Kovalev_D 23:12e6183f04d4 979
Kovalev_D 23:12e6183f04d4 980 /**
Kovalev_D 23:12e6183f04d4 981 * @brief Set the Priority Mask value
Kovalev_D 23:12e6183f04d4 982 *
Kovalev_D 23:12e6183f04d4 983 * @param priMask PriMask
Kovalev_D 23:12e6183f04d4 984 *
Kovalev_D 23:12e6183f04d4 985 * Set the priority mask bit in the priority mask register
Kovalev_D 23:12e6183f04d4 986 */
Kovalev_D 23:12e6183f04d4 987 static __INLINE void __set_PRIMASK(uint32_t priMask)
Kovalev_D 23:12e6183f04d4 988 {
Kovalev_D 23:12e6183f04d4 989 register uint32_t __regPriMask __ASM("primask");
Kovalev_D 23:12e6183f04d4 990 __regPriMask = (priMask);
Kovalev_D 23:12e6183f04d4 991 }
Kovalev_D 23:12e6183f04d4 992
Kovalev_D 23:12e6183f04d4 993 /**
Kovalev_D 23:12e6183f04d4 994 * @brief Return the Fault Mask value
Kovalev_D 23:12e6183f04d4 995 *
Kovalev_D 23:12e6183f04d4 996 * @return FaultMask
Kovalev_D 23:12e6183f04d4 997 *
Kovalev_D 23:12e6183f04d4 998 * Return the content of the fault mask register
Kovalev_D 23:12e6183f04d4 999 */
Kovalev_D 23:12e6183f04d4 1000 static __INLINE uint32_t __get_FAULTMASK(void)
Kovalev_D 23:12e6183f04d4 1001 {
Kovalev_D 23:12e6183f04d4 1002 register uint32_t __regFaultMask __ASM("faultmask");
Kovalev_D 23:12e6183f04d4 1003 return(__regFaultMask);
Kovalev_D 23:12e6183f04d4 1004 }
Kovalev_D 23:12e6183f04d4 1005
Kovalev_D 23:12e6183f04d4 1006 /**
Kovalev_D 23:12e6183f04d4 1007 * @brief Set the Fault Mask value
Kovalev_D 23:12e6183f04d4 1008 *
Kovalev_D 23:12e6183f04d4 1009 * @param faultMask faultMask value
Kovalev_D 23:12e6183f04d4 1010 *
Kovalev_D 23:12e6183f04d4 1011 * Set the fault mask register
Kovalev_D 23:12e6183f04d4 1012 */
Kovalev_D 23:12e6183f04d4 1013 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
Kovalev_D 23:12e6183f04d4 1014 {
Kovalev_D 23:12e6183f04d4 1015 register uint32_t __regFaultMask __ASM("faultmask");
Kovalev_D 23:12e6183f04d4 1016 __regFaultMask = (faultMask & 1);
Kovalev_D 23:12e6183f04d4 1017 }
Kovalev_D 23:12e6183f04d4 1018
Kovalev_D 23:12e6183f04d4 1019 /**
Kovalev_D 23:12e6183f04d4 1020 * @brief Return the Control Register value
Kovalev_D 23:12e6183f04d4 1021 *
Kovalev_D 23:12e6183f04d4 1022 * @return Control value
Kovalev_D 23:12e6183f04d4 1023 *
Kovalev_D 23:12e6183f04d4 1024 * Return the content of the control register
Kovalev_D 23:12e6183f04d4 1025 */
Kovalev_D 23:12e6183f04d4 1026 static __INLINE uint32_t __get_CONTROL(void)
Kovalev_D 23:12e6183f04d4 1027 {
Kovalev_D 23:12e6183f04d4 1028 register uint32_t __regControl __ASM("control");
Kovalev_D 23:12e6183f04d4 1029 return(__regControl);
Kovalev_D 23:12e6183f04d4 1030 }
Kovalev_D 23:12e6183f04d4 1031
Kovalev_D 23:12e6183f04d4 1032 /**
Kovalev_D 23:12e6183f04d4 1033 * @brief Set the Control Register value
Kovalev_D 23:12e6183f04d4 1034 *
Kovalev_D 23:12e6183f04d4 1035 * @param control Control value
Kovalev_D 23:12e6183f04d4 1036 *
Kovalev_D 23:12e6183f04d4 1037 * Set the control register
Kovalev_D 23:12e6183f04d4 1038 */
Kovalev_D 23:12e6183f04d4 1039 static __INLINE void __set_CONTROL(uint32_t control)
Kovalev_D 23:12e6183f04d4 1040 {
Kovalev_D 23:12e6183f04d4 1041 register uint32_t __regControl __ASM("control");
Kovalev_D 23:12e6183f04d4 1042 __regControl = control;
Kovalev_D 23:12e6183f04d4 1043 }
Kovalev_D 23:12e6183f04d4 1044
Kovalev_D 23:12e6183f04d4 1045 #endif /* __ARMCC_VERSION */
Kovalev_D 23:12e6183f04d4 1046
Kovalev_D 23:12e6183f04d4 1047
Kovalev_D 23:12e6183f04d4 1048
Kovalev_D 23:12e6183f04d4 1049 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
Kovalev_D 23:12e6183f04d4 1050 /* IAR iccarm specific functions */
Kovalev_D 23:12e6183f04d4 1051
Kovalev_D 23:12e6183f04d4 1052 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
Kovalev_D 23:12e6183f04d4 1053 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
Kovalev_D 23:12e6183f04d4 1054
Kovalev_D 23:12e6183f04d4 1055 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
Kovalev_D 23:12e6183f04d4 1056 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
Kovalev_D 23:12e6183f04d4 1057
Kovalev_D 23:12e6183f04d4 1058 #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
Kovalev_D 23:12e6183f04d4 1059 static __INLINE void __WFI() { __ASM ("wfi"); }
Kovalev_D 23:12e6183f04d4 1060 static __INLINE void __WFE() { __ASM ("wfe"); }
Kovalev_D 23:12e6183f04d4 1061 static __INLINE void __SEV() { __ASM ("sev"); }
Kovalev_D 23:12e6183f04d4 1062 static __INLINE void __CLREX() { __ASM ("clrex"); }
Kovalev_D 23:12e6183f04d4 1063
Kovalev_D 23:12e6183f04d4 1064 /* intrinsic void __ISB(void) */
Kovalev_D 23:12e6183f04d4 1065 /* intrinsic void __DSB(void) */
Kovalev_D 23:12e6183f04d4 1066 /* intrinsic void __DMB(void) */
Kovalev_D 23:12e6183f04d4 1067 /* intrinsic void __set_PRIMASK(); */
Kovalev_D 23:12e6183f04d4 1068 /* intrinsic void __get_PRIMASK(); */
Kovalev_D 23:12e6183f04d4 1069 /* intrinsic void __set_FAULTMASK(); */
Kovalev_D 23:12e6183f04d4 1070 /* intrinsic void __get_FAULTMASK(); */
Kovalev_D 23:12e6183f04d4 1071 /* intrinsic uint32_t __REV(uint32_t value); */
Kovalev_D 23:12e6183f04d4 1072 /* intrinsic uint32_t __REVSH(uint32_t value); */
Kovalev_D 23:12e6183f04d4 1073 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
Kovalev_D 23:12e6183f04d4 1074 /* intrinsic unsigned long __LDREX(unsigned long *); */
Kovalev_D 23:12e6183f04d4 1075
Kovalev_D 23:12e6183f04d4 1076
Kovalev_D 23:12e6183f04d4 1077 /**
Kovalev_D 23:12e6183f04d4 1078 * @brief Return the Process Stack Pointer
Kovalev_D 23:12e6183f04d4 1079 *
Kovalev_D 23:12e6183f04d4 1080 * @return ProcessStackPointer
Kovalev_D 23:12e6183f04d4 1081 *
Kovalev_D 23:12e6183f04d4 1082 * Return the actual process stack pointer
Kovalev_D 23:12e6183f04d4 1083 */
Kovalev_D 23:12e6183f04d4 1084 extern uint32_t __get_PSP(void);
Kovalev_D 23:12e6183f04d4 1085
Kovalev_D 23:12e6183f04d4 1086 /**
Kovalev_D 23:12e6183f04d4 1087 * @brief Set the Process Stack Pointer
Kovalev_D 23:12e6183f04d4 1088 *
Kovalev_D 23:12e6183f04d4 1089 * @param topOfProcStack Process Stack Pointer
Kovalev_D 23:12e6183f04d4 1090 *
Kovalev_D 23:12e6183f04d4 1091 * Assign the value ProcessStackPointer to the MSP
Kovalev_D 23:12e6183f04d4 1092 * (process stack pointer) Cortex processor register
Kovalev_D 23:12e6183f04d4 1093 */
Kovalev_D 23:12e6183f04d4 1094 extern void __set_PSP(uint32_t topOfProcStack);
Kovalev_D 23:12e6183f04d4 1095
Kovalev_D 23:12e6183f04d4 1096 /**
Kovalev_D 23:12e6183f04d4 1097 * @brief Return the Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1098 *
Kovalev_D 23:12e6183f04d4 1099 * @return Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1100 *
Kovalev_D 23:12e6183f04d4 1101 * Return the current value of the MSP (main stack pointer)
Kovalev_D 23:12e6183f04d4 1102 * Cortex processor register
Kovalev_D 23:12e6183f04d4 1103 */
Kovalev_D 23:12e6183f04d4 1104 extern uint32_t __get_MSP(void);
Kovalev_D 23:12e6183f04d4 1105
Kovalev_D 23:12e6183f04d4 1106 /**
Kovalev_D 23:12e6183f04d4 1107 * @brief Set the Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1108 *
Kovalev_D 23:12e6183f04d4 1109 * @param topOfMainStack Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1110 *
Kovalev_D 23:12e6183f04d4 1111 * Assign the value mainStackPointer to the MSP
Kovalev_D 23:12e6183f04d4 1112 * (main stack pointer) Cortex processor register
Kovalev_D 23:12e6183f04d4 1113 */
Kovalev_D 23:12e6183f04d4 1114 extern void __set_MSP(uint32_t topOfMainStack);
Kovalev_D 23:12e6183f04d4 1115
Kovalev_D 23:12e6183f04d4 1116 /**
Kovalev_D 23:12e6183f04d4 1117 * @brief Reverse byte order in unsigned short value
Kovalev_D 23:12e6183f04d4 1118 *
Kovalev_D 23:12e6183f04d4 1119 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 1120 * @return reversed value
Kovalev_D 23:12e6183f04d4 1121 *
Kovalev_D 23:12e6183f04d4 1122 * Reverse byte order in unsigned short value
Kovalev_D 23:12e6183f04d4 1123 */
Kovalev_D 23:12e6183f04d4 1124 extern uint32_t __REV16(uint16_t value);
Kovalev_D 23:12e6183f04d4 1125
Kovalev_D 23:12e6183f04d4 1126 /**
Kovalev_D 23:12e6183f04d4 1127 * @brief Reverse bit order of value
Kovalev_D 23:12e6183f04d4 1128 *
Kovalev_D 23:12e6183f04d4 1129 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 1130 * @return reversed value
Kovalev_D 23:12e6183f04d4 1131 *
Kovalev_D 23:12e6183f04d4 1132 * Reverse bit order of value
Kovalev_D 23:12e6183f04d4 1133 */
Kovalev_D 23:12e6183f04d4 1134 extern uint32_t __RBIT(uint32_t value);
Kovalev_D 23:12e6183f04d4 1135
Kovalev_D 23:12e6183f04d4 1136 /**
Kovalev_D 23:12e6183f04d4 1137 * @brief LDR Exclusive (8 bit)
Kovalev_D 23:12e6183f04d4 1138 *
Kovalev_D 23:12e6183f04d4 1139 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1140 * @return value of (*address)
Kovalev_D 23:12e6183f04d4 1141 *
Kovalev_D 23:12e6183f04d4 1142 * Exclusive LDR command for 8 bit values)
Kovalev_D 23:12e6183f04d4 1143 */
Kovalev_D 23:12e6183f04d4 1144 extern uint8_t __LDREXB(uint8_t *addr);
Kovalev_D 23:12e6183f04d4 1145
Kovalev_D 23:12e6183f04d4 1146 /**
Kovalev_D 23:12e6183f04d4 1147 * @brief LDR Exclusive (16 bit)
Kovalev_D 23:12e6183f04d4 1148 *
Kovalev_D 23:12e6183f04d4 1149 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1150 * @return value of (*address)
Kovalev_D 23:12e6183f04d4 1151 *
Kovalev_D 23:12e6183f04d4 1152 * Exclusive LDR command for 16 bit values
Kovalev_D 23:12e6183f04d4 1153 */
Kovalev_D 23:12e6183f04d4 1154 extern uint16_t __LDREXH(uint16_t *addr);
Kovalev_D 23:12e6183f04d4 1155
Kovalev_D 23:12e6183f04d4 1156 /**
Kovalev_D 23:12e6183f04d4 1157 * @brief LDR Exclusive (32 bit)
Kovalev_D 23:12e6183f04d4 1158 *
Kovalev_D 23:12e6183f04d4 1159 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1160 * @return value of (*address)
Kovalev_D 23:12e6183f04d4 1161 *
Kovalev_D 23:12e6183f04d4 1162 * Exclusive LDR command for 32 bit values
Kovalev_D 23:12e6183f04d4 1163 */
Kovalev_D 23:12e6183f04d4 1164 extern uint32_t __LDREXW(uint32_t *addr);
Kovalev_D 23:12e6183f04d4 1165
Kovalev_D 23:12e6183f04d4 1166 /**
Kovalev_D 23:12e6183f04d4 1167 * @brief STR Exclusive (8 bit)
Kovalev_D 23:12e6183f04d4 1168 *
Kovalev_D 23:12e6183f04d4 1169 * @param value value to store
Kovalev_D 23:12e6183f04d4 1170 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1171 * @return successful / failed
Kovalev_D 23:12e6183f04d4 1172 *
Kovalev_D 23:12e6183f04d4 1173 * Exclusive STR command for 8 bit values
Kovalev_D 23:12e6183f04d4 1174 */
Kovalev_D 23:12e6183f04d4 1175 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
Kovalev_D 23:12e6183f04d4 1176
Kovalev_D 23:12e6183f04d4 1177 /**
Kovalev_D 23:12e6183f04d4 1178 * @brief STR Exclusive (16 bit)
Kovalev_D 23:12e6183f04d4 1179 *
Kovalev_D 23:12e6183f04d4 1180 * @param value value to store
Kovalev_D 23:12e6183f04d4 1181 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1182 * @return successful / failed
Kovalev_D 23:12e6183f04d4 1183 *
Kovalev_D 23:12e6183f04d4 1184 * Exclusive STR command for 16 bit values
Kovalev_D 23:12e6183f04d4 1185 */
Kovalev_D 23:12e6183f04d4 1186 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
Kovalev_D 23:12e6183f04d4 1187
Kovalev_D 23:12e6183f04d4 1188 /**
Kovalev_D 23:12e6183f04d4 1189 * @brief STR Exclusive (32 bit)
Kovalev_D 23:12e6183f04d4 1190 *
Kovalev_D 23:12e6183f04d4 1191 * @param value value to store
Kovalev_D 23:12e6183f04d4 1192 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1193 * @return successful / failed
Kovalev_D 23:12e6183f04d4 1194 *
Kovalev_D 23:12e6183f04d4 1195 * Exclusive STR command for 32 bit values
Kovalev_D 23:12e6183f04d4 1196 */
Kovalev_D 23:12e6183f04d4 1197 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
Kovalev_D 23:12e6183f04d4 1198
Kovalev_D 23:12e6183f04d4 1199
Kovalev_D 23:12e6183f04d4 1200
Kovalev_D 23:12e6183f04d4 1201 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kovalev_D 23:12e6183f04d4 1202 /* GNU gcc specific functions */
Kovalev_D 23:12e6183f04d4 1203
Kovalev_D 23:12e6183f04d4 1204 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
Kovalev_D 23:12e6183f04d4 1205 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
Kovalev_D 23:12e6183f04d4 1206
Kovalev_D 23:12e6183f04d4 1207 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
Kovalev_D 23:12e6183f04d4 1208 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
Kovalev_D 23:12e6183f04d4 1209
Kovalev_D 23:12e6183f04d4 1210 static __INLINE void __NOP() { __ASM volatile ("nop"); }
Kovalev_D 23:12e6183f04d4 1211 static __INLINE void __WFI() { __ASM volatile ("wfi"); }
Kovalev_D 23:12e6183f04d4 1212 static __INLINE void __WFE() { __ASM volatile ("wfe"); }
Kovalev_D 23:12e6183f04d4 1213 static __INLINE void __SEV() { __ASM volatile ("sev"); }
Kovalev_D 23:12e6183f04d4 1214 static __INLINE void __ISB() { __ASM volatile ("isb"); }
Kovalev_D 23:12e6183f04d4 1215 static __INLINE void __DSB() { __ASM volatile ("dsb"); }
Kovalev_D 23:12e6183f04d4 1216 static __INLINE void __DMB() { __ASM volatile ("dmb"); }
Kovalev_D 23:12e6183f04d4 1217 static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
Kovalev_D 23:12e6183f04d4 1218
Kovalev_D 23:12e6183f04d4 1219
Kovalev_D 23:12e6183f04d4 1220 /**
Kovalev_D 23:12e6183f04d4 1221 * @brief Return the Process Stack Pointer
Kovalev_D 23:12e6183f04d4 1222 *
Kovalev_D 23:12e6183f04d4 1223 * @return ProcessStackPointer
Kovalev_D 23:12e6183f04d4 1224 *
Kovalev_D 23:12e6183f04d4 1225 * Return the actual process stack pointer
Kovalev_D 23:12e6183f04d4 1226 */
Kovalev_D 23:12e6183f04d4 1227 extern uint32_t __get_PSP(void);
Kovalev_D 23:12e6183f04d4 1228
Kovalev_D 23:12e6183f04d4 1229 /**
Kovalev_D 23:12e6183f04d4 1230 * @brief Set the Process Stack Pointer
Kovalev_D 23:12e6183f04d4 1231 *
Kovalev_D 23:12e6183f04d4 1232 * @param topOfProcStack Process Stack Pointer
Kovalev_D 23:12e6183f04d4 1233 *
Kovalev_D 23:12e6183f04d4 1234 * Assign the value ProcessStackPointer to the MSP
Kovalev_D 23:12e6183f04d4 1235 * (process stack pointer) Cortex processor register
Kovalev_D 23:12e6183f04d4 1236 */
Kovalev_D 23:12e6183f04d4 1237 extern void __set_PSP(uint32_t topOfProcStack);
Kovalev_D 23:12e6183f04d4 1238
Kovalev_D 23:12e6183f04d4 1239 /**
Kovalev_D 23:12e6183f04d4 1240 * @brief Return the Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1241 *
Kovalev_D 23:12e6183f04d4 1242 * @return Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1243 *
Kovalev_D 23:12e6183f04d4 1244 * Return the current value of the MSP (main stack pointer)
Kovalev_D 23:12e6183f04d4 1245 * Cortex processor register
Kovalev_D 23:12e6183f04d4 1246 */
Kovalev_D 23:12e6183f04d4 1247 extern uint32_t __get_MSP(void);
Kovalev_D 23:12e6183f04d4 1248
Kovalev_D 23:12e6183f04d4 1249 /**
Kovalev_D 23:12e6183f04d4 1250 * @brief Set the Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1251 *
Kovalev_D 23:12e6183f04d4 1252 * @param topOfMainStack Main Stack Pointer
Kovalev_D 23:12e6183f04d4 1253 *
Kovalev_D 23:12e6183f04d4 1254 * Assign the value mainStackPointer to the MSP
Kovalev_D 23:12e6183f04d4 1255 * (main stack pointer) Cortex processor register
Kovalev_D 23:12e6183f04d4 1256 */
Kovalev_D 23:12e6183f04d4 1257 extern void __set_MSP(uint32_t topOfMainStack);
Kovalev_D 23:12e6183f04d4 1258
Kovalev_D 23:12e6183f04d4 1259 /**
Kovalev_D 23:12e6183f04d4 1260 * @brief Return the Base Priority value
Kovalev_D 23:12e6183f04d4 1261 *
Kovalev_D 23:12e6183f04d4 1262 * @return BasePriority
Kovalev_D 23:12e6183f04d4 1263 *
Kovalev_D 23:12e6183f04d4 1264 * Return the content of the base priority register
Kovalev_D 23:12e6183f04d4 1265 */
Kovalev_D 23:12e6183f04d4 1266 extern uint32_t __get_BASEPRI(void);
Kovalev_D 23:12e6183f04d4 1267
Kovalev_D 23:12e6183f04d4 1268 /**
Kovalev_D 23:12e6183f04d4 1269 * @brief Set the Base Priority value
Kovalev_D 23:12e6183f04d4 1270 *
Kovalev_D 23:12e6183f04d4 1271 * @param basePri BasePriority
Kovalev_D 23:12e6183f04d4 1272 *
Kovalev_D 23:12e6183f04d4 1273 * Set the base priority register
Kovalev_D 23:12e6183f04d4 1274 */
Kovalev_D 23:12e6183f04d4 1275 extern void __set_BASEPRI(uint32_t basePri);
Kovalev_D 23:12e6183f04d4 1276
Kovalev_D 23:12e6183f04d4 1277 /**
Kovalev_D 23:12e6183f04d4 1278 * @brief Return the Priority Mask value
Kovalev_D 23:12e6183f04d4 1279 *
Kovalev_D 23:12e6183f04d4 1280 * @return PriMask
Kovalev_D 23:12e6183f04d4 1281 *
Kovalev_D 23:12e6183f04d4 1282 * Return state of the priority mask bit from the priority mask register
Kovalev_D 23:12e6183f04d4 1283 */
Kovalev_D 23:12e6183f04d4 1284 extern uint32_t __get_PRIMASK(void);
Kovalev_D 23:12e6183f04d4 1285
Kovalev_D 23:12e6183f04d4 1286 /**
Kovalev_D 23:12e6183f04d4 1287 * @brief Set the Priority Mask value
Kovalev_D 23:12e6183f04d4 1288 *
Kovalev_D 23:12e6183f04d4 1289 * @param priMask PriMask
Kovalev_D 23:12e6183f04d4 1290 *
Kovalev_D 23:12e6183f04d4 1291 * Set the priority mask bit in the priority mask register
Kovalev_D 23:12e6183f04d4 1292 */
Kovalev_D 23:12e6183f04d4 1293 extern void __set_PRIMASK(uint32_t priMask);
Kovalev_D 23:12e6183f04d4 1294
Kovalev_D 23:12e6183f04d4 1295 /**
Kovalev_D 23:12e6183f04d4 1296 * @brief Return the Fault Mask value
Kovalev_D 23:12e6183f04d4 1297 *
Kovalev_D 23:12e6183f04d4 1298 * @return FaultMask
Kovalev_D 23:12e6183f04d4 1299 *
Kovalev_D 23:12e6183f04d4 1300 * Return the content of the fault mask register
Kovalev_D 23:12e6183f04d4 1301 */
Kovalev_D 23:12e6183f04d4 1302 extern uint32_t __get_FAULTMASK(void);
Kovalev_D 23:12e6183f04d4 1303
Kovalev_D 23:12e6183f04d4 1304 /**
Kovalev_D 23:12e6183f04d4 1305 * @brief Set the Fault Mask value
Kovalev_D 23:12e6183f04d4 1306 *
Kovalev_D 23:12e6183f04d4 1307 * @param faultMask faultMask value
Kovalev_D 23:12e6183f04d4 1308 *
Kovalev_D 23:12e6183f04d4 1309 * Set the fault mask register
Kovalev_D 23:12e6183f04d4 1310 */
Kovalev_D 23:12e6183f04d4 1311 extern void __set_FAULTMASK(uint32_t faultMask);
Kovalev_D 23:12e6183f04d4 1312
Kovalev_D 23:12e6183f04d4 1313 /**
Kovalev_D 23:12e6183f04d4 1314 * @brief Return the Control Register value
Kovalev_D 23:12e6183f04d4 1315 *
Kovalev_D 23:12e6183f04d4 1316 * @return Control value
Kovalev_D 23:12e6183f04d4 1317 *
Kovalev_D 23:12e6183f04d4 1318 * Return the content of the control register
Kovalev_D 23:12e6183f04d4 1319 */
Kovalev_D 23:12e6183f04d4 1320 extern uint32_t __get_CONTROL(void);
Kovalev_D 23:12e6183f04d4 1321
Kovalev_D 23:12e6183f04d4 1322 /**
Kovalev_D 23:12e6183f04d4 1323 * @brief Set the Control Register value
Kovalev_D 23:12e6183f04d4 1324 *
Kovalev_D 23:12e6183f04d4 1325 * @param control Control value
Kovalev_D 23:12e6183f04d4 1326 *
Kovalev_D 23:12e6183f04d4 1327 * Set the control register
Kovalev_D 23:12e6183f04d4 1328 */
Kovalev_D 23:12e6183f04d4 1329 extern void __set_CONTROL(uint32_t control);
Kovalev_D 23:12e6183f04d4 1330
Kovalev_D 23:12e6183f04d4 1331 /**
Kovalev_D 23:12e6183f04d4 1332 * @brief Reverse byte order in integer value
Kovalev_D 23:12e6183f04d4 1333 *
Kovalev_D 23:12e6183f04d4 1334 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 1335 * @return reversed value
Kovalev_D 23:12e6183f04d4 1336 *
Kovalev_D 23:12e6183f04d4 1337 * Reverse byte order in integer value
Kovalev_D 23:12e6183f04d4 1338 */
Kovalev_D 23:12e6183f04d4 1339 extern uint32_t __REV(uint32_t value);
Kovalev_D 23:12e6183f04d4 1340
Kovalev_D 23:12e6183f04d4 1341 /**
Kovalev_D 23:12e6183f04d4 1342 * @brief Reverse byte order in unsigned short value
Kovalev_D 23:12e6183f04d4 1343 *
Kovalev_D 23:12e6183f04d4 1344 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 1345 * @return reversed value
Kovalev_D 23:12e6183f04d4 1346 *
Kovalev_D 23:12e6183f04d4 1347 * Reverse byte order in unsigned short value
Kovalev_D 23:12e6183f04d4 1348 */
Kovalev_D 23:12e6183f04d4 1349 extern uint32_t __REV16(uint16_t value);
Kovalev_D 23:12e6183f04d4 1350
Kovalev_D 23:12e6183f04d4 1351 /**
Kovalev_D 23:12e6183f04d4 1352 * @brief Reverse byte order in signed short value with sign extension to integer
Kovalev_D 23:12e6183f04d4 1353 *
Kovalev_D 23:12e6183f04d4 1354 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 1355 * @return reversed value
Kovalev_D 23:12e6183f04d4 1356 *
Kovalev_D 23:12e6183f04d4 1357 * Reverse byte order in signed short value with sign extension to integer
Kovalev_D 23:12e6183f04d4 1358 */
Kovalev_D 23:12e6183f04d4 1359 extern int32_t __REVSH(int16_t value);
Kovalev_D 23:12e6183f04d4 1360
Kovalev_D 23:12e6183f04d4 1361 /**
Kovalev_D 23:12e6183f04d4 1362 * @brief Reverse bit order of value
Kovalev_D 23:12e6183f04d4 1363 *
Kovalev_D 23:12e6183f04d4 1364 * @param value value to reverse
Kovalev_D 23:12e6183f04d4 1365 * @return reversed value
Kovalev_D 23:12e6183f04d4 1366 *
Kovalev_D 23:12e6183f04d4 1367 * Reverse bit order of value
Kovalev_D 23:12e6183f04d4 1368 */
Kovalev_D 23:12e6183f04d4 1369 extern uint32_t __RBIT(uint32_t value);
Kovalev_D 23:12e6183f04d4 1370
Kovalev_D 23:12e6183f04d4 1371 /**
Kovalev_D 23:12e6183f04d4 1372 * @brief LDR Exclusive (8 bit)
Kovalev_D 23:12e6183f04d4 1373 *
Kovalev_D 23:12e6183f04d4 1374 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1375 * @return value of (*address)
Kovalev_D 23:12e6183f04d4 1376 *
Kovalev_D 23:12e6183f04d4 1377 * Exclusive LDR command for 8 bit value
Kovalev_D 23:12e6183f04d4 1378 */
Kovalev_D 23:12e6183f04d4 1379 extern uint8_t __LDREXB(uint8_t *addr);
Kovalev_D 23:12e6183f04d4 1380
Kovalev_D 23:12e6183f04d4 1381 /**
Kovalev_D 23:12e6183f04d4 1382 * @brief LDR Exclusive (16 bit)
Kovalev_D 23:12e6183f04d4 1383 *
Kovalev_D 23:12e6183f04d4 1384 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1385 * @return value of (*address)
Kovalev_D 23:12e6183f04d4 1386 *
Kovalev_D 23:12e6183f04d4 1387 * Exclusive LDR command for 16 bit values
Kovalev_D 23:12e6183f04d4 1388 */
Kovalev_D 23:12e6183f04d4 1389 extern uint16_t __LDREXH(uint16_t *addr);
Kovalev_D 23:12e6183f04d4 1390
Kovalev_D 23:12e6183f04d4 1391 /**
Kovalev_D 23:12e6183f04d4 1392 * @brief LDR Exclusive (32 bit)
Kovalev_D 23:12e6183f04d4 1393 *
Kovalev_D 23:12e6183f04d4 1394 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1395 * @return value of (*address)
Kovalev_D 23:12e6183f04d4 1396 *
Kovalev_D 23:12e6183f04d4 1397 * Exclusive LDR command for 32 bit values
Kovalev_D 23:12e6183f04d4 1398 */
Kovalev_D 23:12e6183f04d4 1399 extern uint32_t __LDREXW(uint32_t *addr);
Kovalev_D 23:12e6183f04d4 1400
Kovalev_D 23:12e6183f04d4 1401 /**
Kovalev_D 23:12e6183f04d4 1402 * @brief STR Exclusive (8 bit)
Kovalev_D 23:12e6183f04d4 1403 *
Kovalev_D 23:12e6183f04d4 1404 * @param value value to store
Kovalev_D 23:12e6183f04d4 1405 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1406 * @return successful / failed
Kovalev_D 23:12e6183f04d4 1407 *
Kovalev_D 23:12e6183f04d4 1408 * Exclusive STR command for 8 bit values
Kovalev_D 23:12e6183f04d4 1409 */
Kovalev_D 23:12e6183f04d4 1410 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
Kovalev_D 23:12e6183f04d4 1411
Kovalev_D 23:12e6183f04d4 1412 /**
Kovalev_D 23:12e6183f04d4 1413 * @brief STR Exclusive (16 bit)
Kovalev_D 23:12e6183f04d4 1414 *
Kovalev_D 23:12e6183f04d4 1415 * @param value value to store
Kovalev_D 23:12e6183f04d4 1416 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1417 * @return successful / failed
Kovalev_D 23:12e6183f04d4 1418 *
Kovalev_D 23:12e6183f04d4 1419 * Exclusive STR command for 16 bit values
Kovalev_D 23:12e6183f04d4 1420 */
Kovalev_D 23:12e6183f04d4 1421 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
Kovalev_D 23:12e6183f04d4 1422
Kovalev_D 23:12e6183f04d4 1423 /**
Kovalev_D 23:12e6183f04d4 1424 * @brief STR Exclusive (32 bit)
Kovalev_D 23:12e6183f04d4 1425 *
Kovalev_D 23:12e6183f04d4 1426 * @param value value to store
Kovalev_D 23:12e6183f04d4 1427 * @param *addr address pointer
Kovalev_D 23:12e6183f04d4 1428 * @return successful / failed
Kovalev_D 23:12e6183f04d4 1429 *
Kovalev_D 23:12e6183f04d4 1430 * Exclusive STR command for 32 bit values
Kovalev_D 23:12e6183f04d4 1431 */
Kovalev_D 23:12e6183f04d4 1432 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
Kovalev_D 23:12e6183f04d4 1433
Kovalev_D 23:12e6183f04d4 1434
Kovalev_D 23:12e6183f04d4 1435 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
Kovalev_D 23:12e6183f04d4 1436 /* TASKING carm specific functions */
Kovalev_D 23:12e6183f04d4 1437
Kovalev_D 23:12e6183f04d4 1438 /*
Kovalev_D 23:12e6183f04d4 1439 * The CMSIS functions have been implemented as intrinsics in the compiler.
Kovalev_D 23:12e6183f04d4 1440 * Please use "carm -?i" to get an up to date list of all instrinsics,
Kovalev_D 23:12e6183f04d4 1441 * Including the CMSIS ones.
Kovalev_D 23:12e6183f04d4 1442 */
Kovalev_D 23:12e6183f04d4 1443
Kovalev_D 23:12e6183f04d4 1444 #endif
Kovalev_D 23:12e6183f04d4 1445
Kovalev_D 23:12e6183f04d4 1446
Kovalev_D 23:12e6183f04d4 1447 /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
Kovalev_D 23:12e6183f04d4 1448 Core Function Interface containing:
Kovalev_D 23:12e6183f04d4 1449 - Core NVIC Functions
Kovalev_D 23:12e6183f04d4 1450 - Core SysTick Functions
Kovalev_D 23:12e6183f04d4 1451 - Core Reset Functions
Kovalev_D 23:12e6183f04d4 1452 */
Kovalev_D 23:12e6183f04d4 1453 /*@{*/
Kovalev_D 23:12e6183f04d4 1454
Kovalev_D 23:12e6183f04d4 1455 /* ########################## NVIC functions #################################### */
Kovalev_D 23:12e6183f04d4 1456
Kovalev_D 23:12e6183f04d4 1457 /**
Kovalev_D 23:12e6183f04d4 1458 * @brief Set the Priority Grouping in NVIC Interrupt Controller
Kovalev_D 23:12e6183f04d4 1459 *
Kovalev_D 23:12e6183f04d4 1460 * @param PriorityGroup is priority grouping field
Kovalev_D 23:12e6183f04d4 1461 *
Kovalev_D 23:12e6183f04d4 1462 * Set the priority grouping field using the required unlock sequence.
Kovalev_D 23:12e6183f04d4 1463 * The parameter priority_grouping is assigned to the field
Kovalev_D 23:12e6183f04d4 1464 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
Kovalev_D 23:12e6183f04d4 1465 * In case of a conflict between priority grouping and available
Kovalev_D 23:12e6183f04d4 1466 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kovalev_D 23:12e6183f04d4 1467 */
Kovalev_D 23:12e6183f04d4 1468 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kovalev_D 23:12e6183f04d4 1469 {
Kovalev_D 23:12e6183f04d4 1470 uint32_t reg_value;
Kovalev_D 23:12e6183f04d4 1471 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kovalev_D 23:12e6183f04d4 1472
Kovalev_D 23:12e6183f04d4 1473 reg_value = SCB->AIRCR; /* read old register configuration */
Kovalev_D 23:12e6183f04d4 1474 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
Kovalev_D 23:12e6183f04d4 1475 reg_value = (reg_value |
Kovalev_D 23:12e6183f04d4 1476 (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kovalev_D 23:12e6183f04d4 1477 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
Kovalev_D 23:12e6183f04d4 1478 SCB->AIRCR = reg_value;
Kovalev_D 23:12e6183f04d4 1479 }
Kovalev_D 23:12e6183f04d4 1480
Kovalev_D 23:12e6183f04d4 1481 /**
Kovalev_D 23:12e6183f04d4 1482 * @brief Get the Priority Grouping from NVIC Interrupt Controller
Kovalev_D 23:12e6183f04d4 1483 *
Kovalev_D 23:12e6183f04d4 1484 * @return priority grouping field
Kovalev_D 23:12e6183f04d4 1485 *
Kovalev_D 23:12e6183f04d4 1486 * Get the priority grouping from NVIC Interrupt Controller.
Kovalev_D 23:12e6183f04d4 1487 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
Kovalev_D 23:12e6183f04d4 1488 */
Kovalev_D 23:12e6183f04d4 1489 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kovalev_D 23:12e6183f04d4 1490 {
Kovalev_D 23:12e6183f04d4 1491 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
Kovalev_D 23:12e6183f04d4 1492 }
Kovalev_D 23:12e6183f04d4 1493
Kovalev_D 23:12e6183f04d4 1494 /**
Kovalev_D 23:12e6183f04d4 1495 * @brief Enable Interrupt in NVIC Interrupt Controller
Kovalev_D 23:12e6183f04d4 1496 *
Kovalev_D 23:12e6183f04d4 1497 * @param IRQn The positive number of the external interrupt to enable
Kovalev_D 23:12e6183f04d4 1498 *
Kovalev_D 23:12e6183f04d4 1499 * Enable a device specific interupt in the NVIC interrupt controller.
Kovalev_D 23:12e6183f04d4 1500 * The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 1501 */
Kovalev_D 23:12e6183f04d4 1502 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1503 {
Kovalev_D 23:12e6183f04d4 1504 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
Kovalev_D 23:12e6183f04d4 1505 }
Kovalev_D 23:12e6183f04d4 1506
Kovalev_D 23:12e6183f04d4 1507 /**
Kovalev_D 23:12e6183f04d4 1508 * @brief Disable the interrupt line for external interrupt specified
Kovalev_D 23:12e6183f04d4 1509 *
Kovalev_D 23:12e6183f04d4 1510 * @param IRQn The positive number of the external interrupt to disable
Kovalev_D 23:12e6183f04d4 1511 *
Kovalev_D 23:12e6183f04d4 1512 * Disable a device specific interupt in the NVIC interrupt controller.
Kovalev_D 23:12e6183f04d4 1513 * The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 1514 */
Kovalev_D 23:12e6183f04d4 1515 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1516 {
Kovalev_D 23:12e6183f04d4 1517 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Kovalev_D 23:12e6183f04d4 1518 }
Kovalev_D 23:12e6183f04d4 1519
Kovalev_D 23:12e6183f04d4 1520 /**
Kovalev_D 23:12e6183f04d4 1521 * @brief Read the interrupt pending bit for a device specific interrupt source
Kovalev_D 23:12e6183f04d4 1522 *
Kovalev_D 23:12e6183f04d4 1523 * @param IRQn The number of the device specifc interrupt
Kovalev_D 23:12e6183f04d4 1524 * @return 1 = interrupt pending, 0 = interrupt not pending
Kovalev_D 23:12e6183f04d4 1525 *
Kovalev_D 23:12e6183f04d4 1526 * Read the pending register in NVIC and return 1 if its status is pending,
Kovalev_D 23:12e6183f04d4 1527 * otherwise it returns 0
Kovalev_D 23:12e6183f04d4 1528 */
Kovalev_D 23:12e6183f04d4 1529 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1530 {
Kovalev_D 23:12e6183f04d4 1531 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Kovalev_D 23:12e6183f04d4 1532 }
Kovalev_D 23:12e6183f04d4 1533
Kovalev_D 23:12e6183f04d4 1534 /**
Kovalev_D 23:12e6183f04d4 1535 * @brief Set the pending bit for an external interrupt
Kovalev_D 23:12e6183f04d4 1536 *
Kovalev_D 23:12e6183f04d4 1537 * @param IRQn The number of the interrupt for set pending
Kovalev_D 23:12e6183f04d4 1538 *
Kovalev_D 23:12e6183f04d4 1539 * Set the pending bit for the specified interrupt.
Kovalev_D 23:12e6183f04d4 1540 * The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 1541 */
Kovalev_D 23:12e6183f04d4 1542 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1543 {
Kovalev_D 23:12e6183f04d4 1544 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Kovalev_D 23:12e6183f04d4 1545 }
Kovalev_D 23:12e6183f04d4 1546
Kovalev_D 23:12e6183f04d4 1547 /**
Kovalev_D 23:12e6183f04d4 1548 * @brief Clear the pending bit for an external interrupt
Kovalev_D 23:12e6183f04d4 1549 *
Kovalev_D 23:12e6183f04d4 1550 * @param IRQn The number of the interrupt for clear pending
Kovalev_D 23:12e6183f04d4 1551 *
Kovalev_D 23:12e6183f04d4 1552 * Clear the pending bit for the specified interrupt.
Kovalev_D 23:12e6183f04d4 1553 * The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 1554 */
Kovalev_D 23:12e6183f04d4 1555 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1556 {
Kovalev_D 23:12e6183f04d4 1557 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kovalev_D 23:12e6183f04d4 1558 }
Kovalev_D 23:12e6183f04d4 1559
Kovalev_D 23:12e6183f04d4 1560 /**
Kovalev_D 23:12e6183f04d4 1561 * @brief Read the active bit for an external interrupt
Kovalev_D 23:12e6183f04d4 1562 *
Kovalev_D 23:12e6183f04d4 1563 * @param IRQn The number of the interrupt for read active bit
Kovalev_D 23:12e6183f04d4 1564 * @return 1 = interrupt active, 0 = interrupt not active
Kovalev_D 23:12e6183f04d4 1565 *
Kovalev_D 23:12e6183f04d4 1566 * Read the active register in NVIC and returns 1 if its status is active,
Kovalev_D 23:12e6183f04d4 1567 * otherwise it returns 0.
Kovalev_D 23:12e6183f04d4 1568 */
Kovalev_D 23:12e6183f04d4 1569 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1570 {
Kovalev_D 23:12e6183f04d4 1571 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Kovalev_D 23:12e6183f04d4 1572 }
Kovalev_D 23:12e6183f04d4 1573
Kovalev_D 23:12e6183f04d4 1574 /**
Kovalev_D 23:12e6183f04d4 1575 * @brief Set the priority for an interrupt
Kovalev_D 23:12e6183f04d4 1576 *
Kovalev_D 23:12e6183f04d4 1577 * @param IRQn The number of the interrupt for set priority
Kovalev_D 23:12e6183f04d4 1578 * @param priority The priority to set
Kovalev_D 23:12e6183f04d4 1579 *
Kovalev_D 23:12e6183f04d4 1580 * Set the priority for the specified interrupt. The interrupt
Kovalev_D 23:12e6183f04d4 1581 * number can be positive to specify an external (device specific)
Kovalev_D 23:12e6183f04d4 1582 * interrupt, or negative to specify an internal (core) interrupt.
Kovalev_D 23:12e6183f04d4 1583 *
Kovalev_D 23:12e6183f04d4 1584 * Note: The priority cannot be set for every core interrupt.
Kovalev_D 23:12e6183f04d4 1585 */
Kovalev_D 23:12e6183f04d4 1586 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kovalev_D 23:12e6183f04d4 1587 {
Kovalev_D 23:12e6183f04d4 1588 if(IRQn < 0) {
Kovalev_D 23:12e6183f04d4 1589 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
Kovalev_D 23:12e6183f04d4 1590 else {
Kovalev_D 23:12e6183f04d4 1591 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Kovalev_D 23:12e6183f04d4 1592 }
Kovalev_D 23:12e6183f04d4 1593
Kovalev_D 23:12e6183f04d4 1594 /**
Kovalev_D 23:12e6183f04d4 1595 * @brief Read the priority for an interrupt
Kovalev_D 23:12e6183f04d4 1596 *
Kovalev_D 23:12e6183f04d4 1597 * @param IRQn The number of the interrupt for get priority
Kovalev_D 23:12e6183f04d4 1598 * @return The priority for the interrupt
Kovalev_D 23:12e6183f04d4 1599 *
Kovalev_D 23:12e6183f04d4 1600 * Read the priority for the specified interrupt. The interrupt
Kovalev_D 23:12e6183f04d4 1601 * number can be positive to specify an external (device specific)
Kovalev_D 23:12e6183f04d4 1602 * interrupt, or negative to specify an internal (core) interrupt.
Kovalev_D 23:12e6183f04d4 1603 *
Kovalev_D 23:12e6183f04d4 1604 * The returned priority value is automatically aligned to the implemented
Kovalev_D 23:12e6183f04d4 1605 * priority bits of the microcontroller.
Kovalev_D 23:12e6183f04d4 1606 *
Kovalev_D 23:12e6183f04d4 1607 * Note: The priority cannot be set for every core interrupt.
Kovalev_D 23:12e6183f04d4 1608 */
Kovalev_D 23:12e6183f04d4 1609 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1610 {
Kovalev_D 23:12e6183f04d4 1611
Kovalev_D 23:12e6183f04d4 1612 if(IRQn < 0) {
Kovalev_D 23:12e6183f04d4 1613 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
Kovalev_D 23:12e6183f04d4 1614 else {
Kovalev_D 23:12e6183f04d4 1615 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kovalev_D 23:12e6183f04d4 1616 }
Kovalev_D 23:12e6183f04d4 1617
Kovalev_D 23:12e6183f04d4 1618
Kovalev_D 23:12e6183f04d4 1619 /**
Kovalev_D 23:12e6183f04d4 1620 * @brief Encode the priority for an interrupt
Kovalev_D 23:12e6183f04d4 1621 *
Kovalev_D 23:12e6183f04d4 1622 * @param PriorityGroup The used priority group
Kovalev_D 23:12e6183f04d4 1623 * @param PreemptPriority The preemptive priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1624 * @param SubPriority The sub priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1625 * @return The encoded priority for the interrupt
Kovalev_D 23:12e6183f04d4 1626 *
Kovalev_D 23:12e6183f04d4 1627 * Encode the priority for an interrupt with the given priority group,
Kovalev_D 23:12e6183f04d4 1628 * preemptive priority value and sub priority value.
Kovalev_D 23:12e6183f04d4 1629 * In case of a conflict between priority grouping and available
Kovalev_D 23:12e6183f04d4 1630 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Kovalev_D 23:12e6183f04d4 1631 *
Kovalev_D 23:12e6183f04d4 1632 * The returned priority value can be used for NVIC_SetPriority(...) function
Kovalev_D 23:12e6183f04d4 1633 */
Kovalev_D 23:12e6183f04d4 1634 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kovalev_D 23:12e6183f04d4 1635 {
Kovalev_D 23:12e6183f04d4 1636 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kovalev_D 23:12e6183f04d4 1637 uint32_t PreemptPriorityBits;
Kovalev_D 23:12e6183f04d4 1638 uint32_t SubPriorityBits;
Kovalev_D 23:12e6183f04d4 1639
Kovalev_D 23:12e6183f04d4 1640 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kovalev_D 23:12e6183f04d4 1641 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kovalev_D 23:12e6183f04d4 1642
Kovalev_D 23:12e6183f04d4 1643 return (
Kovalev_D 23:12e6183f04d4 1644 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
Kovalev_D 23:12e6183f04d4 1645 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Kovalev_D 23:12e6183f04d4 1646 );
Kovalev_D 23:12e6183f04d4 1647 }
Kovalev_D 23:12e6183f04d4 1648
Kovalev_D 23:12e6183f04d4 1649
Kovalev_D 23:12e6183f04d4 1650 /**
Kovalev_D 23:12e6183f04d4 1651 * @brief Decode the priority of an interrupt
Kovalev_D 23:12e6183f04d4 1652 *
Kovalev_D 23:12e6183f04d4 1653 * @param Priority The priority for the interrupt
Kovalev_D 23:12e6183f04d4 1654 * @param PriorityGroup The used priority group
Kovalev_D 23:12e6183f04d4 1655 * @param pPreemptPriority The preemptive priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1656 * @param pSubPriority The sub priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1657 *
Kovalev_D 23:12e6183f04d4 1658 * Decode an interrupt priority value with the given priority group to
Kovalev_D 23:12e6183f04d4 1659 * preemptive priority value and sub priority value.
Kovalev_D 23:12e6183f04d4 1660 * In case of a conflict between priority grouping and available
Kovalev_D 23:12e6183f04d4 1661 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Kovalev_D 23:12e6183f04d4 1662 *
Kovalev_D 23:12e6183f04d4 1663 * The priority value can be retrieved with NVIC_GetPriority(...) function
Kovalev_D 23:12e6183f04d4 1664 */
Kovalev_D 23:12e6183f04d4 1665 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kovalev_D 23:12e6183f04d4 1666 {
Kovalev_D 23:12e6183f04d4 1667 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kovalev_D 23:12e6183f04d4 1668 uint32_t PreemptPriorityBits;
Kovalev_D 23:12e6183f04d4 1669 uint32_t SubPriorityBits;
Kovalev_D 23:12e6183f04d4 1670
Kovalev_D 23:12e6183f04d4 1671 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kovalev_D 23:12e6183f04d4 1672 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kovalev_D 23:12e6183f04d4 1673
Kovalev_D 23:12e6183f04d4 1674 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Kovalev_D 23:12e6183f04d4 1675 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Kovalev_D 23:12e6183f04d4 1676 }
Kovalev_D 23:12e6183f04d4 1677
Kovalev_D 23:12e6183f04d4 1678
Kovalev_D 23:12e6183f04d4 1679
Kovalev_D 23:12e6183f04d4 1680 /* ################################## SysTick function ############################################ */
Kovalev_D 23:12e6183f04d4 1681
Kovalev_D 23:12e6183f04d4 1682 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
Kovalev_D 23:12e6183f04d4 1683
Kovalev_D 23:12e6183f04d4 1684 /**
Kovalev_D 23:12e6183f04d4 1685 * @brief Initialize and start the SysTick counter and its interrupt.
Kovalev_D 23:12e6183f04d4 1686 *
Kovalev_D 23:12e6183f04d4 1687 * @param ticks number of ticks between two interrupts
Kovalev_D 23:12e6183f04d4 1688 * @return 1 = failed, 0 = successful
Kovalev_D 23:12e6183f04d4 1689 *
Kovalev_D 23:12e6183f04d4 1690 * Initialise the system tick timer and its interrupt and start the
Kovalev_D 23:12e6183f04d4 1691 * system tick timer / counter in free running mode to generate
Kovalev_D 23:12e6183f04d4 1692 * periodical interrupts.
Kovalev_D 23:12e6183f04d4 1693 */
Kovalev_D 23:12e6183f04d4 1694 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
Kovalev_D 23:12e6183f04d4 1695 {
Kovalev_D 23:12e6183f04d4 1696 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kovalev_D 23:12e6183f04d4 1697
Kovalev_D 23:12e6183f04d4 1698 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
Kovalev_D 23:12e6183f04d4 1699 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
Kovalev_D 23:12e6183f04d4 1700 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kovalev_D 23:12e6183f04d4 1701 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kovalev_D 23:12e6183f04d4 1702 SysTick_CTRL_TICKINT_Msk |
Kovalev_D 23:12e6183f04d4 1703 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kovalev_D 23:12e6183f04d4 1704 return (0); /* Function successful */
Kovalev_D 23:12e6183f04d4 1705 }
Kovalev_D 23:12e6183f04d4 1706
Kovalev_D 23:12e6183f04d4 1707 #endif
Kovalev_D 23:12e6183f04d4 1708
Kovalev_D 23:12e6183f04d4 1709
Kovalev_D 23:12e6183f04d4 1710
Kovalev_D 23:12e6183f04d4 1711
Kovalev_D 23:12e6183f04d4 1712 /* ################################## Reset function ############################################ */
Kovalev_D 23:12e6183f04d4 1713
Kovalev_D 23:12e6183f04d4 1714 /**
Kovalev_D 23:12e6183f04d4 1715 * @brief Initiate a system reset request.
Kovalev_D 23:12e6183f04d4 1716 *
Kovalev_D 23:12e6183f04d4 1717 * Initiate a system reset request to reset the MCU
Kovalev_D 23:12e6183f04d4 1718 */
Kovalev_D 23:12e6183f04d4 1719 static __INLINE void NVIC_SystemReset(void)
Kovalev_D 23:12e6183f04d4 1720 {
Kovalev_D 23:12e6183f04d4 1721 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kovalev_D 23:12e6183f04d4 1722 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kovalev_D 23:12e6183f04d4 1723 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
Kovalev_D 23:12e6183f04d4 1724 __DSB(); /* Ensure completion of memory access */
Kovalev_D 23:12e6183f04d4 1725 while(1); /* wait until reset */
Kovalev_D 23:12e6183f04d4 1726 }
Kovalev_D 23:12e6183f04d4 1727
Kovalev_D 23:12e6183f04d4 1728 /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
Kovalev_D 23:12e6183f04d4 1729
Kovalev_D 23:12e6183f04d4 1730
Kovalev_D 23:12e6183f04d4 1731
Kovalev_D 23:12e6183f04d4 1732 /* ##################################### Debug In/Output function ########################################### */
Kovalev_D 23:12e6183f04d4 1733
Kovalev_D 23:12e6183f04d4 1734 /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
Kovalev_D 23:12e6183f04d4 1735 Core Debug Interface containing:
Kovalev_D 23:12e6183f04d4 1736 - Core Debug Receive / Transmit Functions
Kovalev_D 23:12e6183f04d4 1737 - Core Debug Defines
Kovalev_D 23:12e6183f04d4 1738 - Core Debug Variables
Kovalev_D 23:12e6183f04d4 1739 */
Kovalev_D 23:12e6183f04d4 1740 /*@{*/
Kovalev_D 23:12e6183f04d4 1741
Kovalev_D 23:12e6183f04d4 1742 extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
Kovalev_D 23:12e6183f04d4 1743 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
Kovalev_D 23:12e6183f04d4 1744
Kovalev_D 23:12e6183f04d4 1745
Kovalev_D 23:12e6183f04d4 1746 /**
Kovalev_D 23:12e6183f04d4 1747 * @brief Outputs a character via the ITM channel 0
Kovalev_D 23:12e6183f04d4 1748 *
Kovalev_D 23:12e6183f04d4 1749 * @param ch character to output
Kovalev_D 23:12e6183f04d4 1750 * @return character to output
Kovalev_D 23:12e6183f04d4 1751 *
Kovalev_D 23:12e6183f04d4 1752 * The function outputs a character via the ITM channel 0.
Kovalev_D 23:12e6183f04d4 1753 * The function returns when no debugger is connected that has booked the output.
Kovalev_D 23:12e6183f04d4 1754 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
Kovalev_D 23:12e6183f04d4 1755 */
Kovalev_D 23:12e6183f04d4 1756 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
Kovalev_D 23:12e6183f04d4 1757 {
Kovalev_D 23:12e6183f04d4 1758 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
Kovalev_D 23:12e6183f04d4 1759 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
Kovalev_D 23:12e6183f04d4 1760 (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
Kovalev_D 23:12e6183f04d4 1761 {
Kovalev_D 23:12e6183f04d4 1762 while (ITM->PORT[0].u32 == 0);
Kovalev_D 23:12e6183f04d4 1763 ITM->PORT[0].u8 = (uint8_t) ch;
Kovalev_D 23:12e6183f04d4 1764 }
Kovalev_D 23:12e6183f04d4 1765 return (ch);
Kovalev_D 23:12e6183f04d4 1766 }
Kovalev_D 23:12e6183f04d4 1767
Kovalev_D 23:12e6183f04d4 1768
Kovalev_D 23:12e6183f04d4 1769 /**
Kovalev_D 23:12e6183f04d4 1770 * @brief Inputs a character via variable ITM_RxBuffer
Kovalev_D 23:12e6183f04d4 1771 *
Kovalev_D 23:12e6183f04d4 1772 * @return received character, -1 = no character received
Kovalev_D 23:12e6183f04d4 1773 *
Kovalev_D 23:12e6183f04d4 1774 * The function inputs a character via variable ITM_RxBuffer.
Kovalev_D 23:12e6183f04d4 1775 * The function returns when no debugger is connected that has booked the output.
Kovalev_D 23:12e6183f04d4 1776 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
Kovalev_D 23:12e6183f04d4 1777 */
Kovalev_D 23:12e6183f04d4 1778 static __INLINE int ITM_ReceiveChar (void) {
Kovalev_D 23:12e6183f04d4 1779 int ch = -1; /* no character available */
Kovalev_D 23:12e6183f04d4 1780
Kovalev_D 23:12e6183f04d4 1781 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kovalev_D 23:12e6183f04d4 1782 ch = ITM_RxBuffer;
Kovalev_D 23:12e6183f04d4 1783 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kovalev_D 23:12e6183f04d4 1784 }
Kovalev_D 23:12e6183f04d4 1785
Kovalev_D 23:12e6183f04d4 1786 return (ch);
Kovalev_D 23:12e6183f04d4 1787 }
Kovalev_D 23:12e6183f04d4 1788
Kovalev_D 23:12e6183f04d4 1789
Kovalev_D 23:12e6183f04d4 1790 /**
Kovalev_D 23:12e6183f04d4 1791 * @brief Check if a character via variable ITM_RxBuffer is available
Kovalev_D 23:12e6183f04d4 1792 *
Kovalev_D 23:12e6183f04d4 1793 * @return 1 = character available, 0 = no character available
Kovalev_D 23:12e6183f04d4 1794 *
Kovalev_D 23:12e6183f04d4 1795 * The function checks variable ITM_RxBuffer whether a character is available or not.
Kovalev_D 23:12e6183f04d4 1796 * The function returns '1' if a character is available and '0' if no character is available.
Kovalev_D 23:12e6183f04d4 1797 */
Kovalev_D 23:12e6183f04d4 1798 static __INLINE int ITM_CheckChar (void) {
Kovalev_D 23:12e6183f04d4 1799
Kovalev_D 23:12e6183f04d4 1800 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kovalev_D 23:12e6183f04d4 1801 return (0); /* no character available */
Kovalev_D 23:12e6183f04d4 1802 } else {
Kovalev_D 23:12e6183f04d4 1803 return (1); /* character available */
Kovalev_D 23:12e6183f04d4 1804 }
Kovalev_D 23:12e6183f04d4 1805 }
Kovalev_D 23:12e6183f04d4 1806
Kovalev_D 23:12e6183f04d4 1807 /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
Kovalev_D 23:12e6183f04d4 1808
Kovalev_D 23:12e6183f04d4 1809
Kovalev_D 23:12e6183f04d4 1810 #ifdef __cplusplus
Kovalev_D 23:12e6183f04d4 1811 }
Kovalev_D 23:12e6183f04d4 1812 #endif
Kovalev_D 23:12e6183f04d4 1813
Kovalev_D 23:12e6183f04d4 1814 /*@}*/ /* end of group CMSIS_CM3_core_definitions */
Kovalev_D 23:12e6183f04d4 1815
Kovalev_D 23:12e6183f04d4 1816 #endif /* __CM3_CORE_H__ */
Kovalev_D 23:12e6183f04d4 1817
Kovalev_D 23:12e6183f04d4 1818 /*lint -restore */