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host/Source/CMSIS/Documentation/CMSIS_Core.htm@23:12e6183f04d4, 2016-02-03 (annotated)

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Kovalev_D 23:12e6183f04d4 4 <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
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Kovalev_D 23:12e6183f04d4 49 /*----------------------------------------------------------------------------------------------------------------------*/
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Kovalev_D 23:12e6183f04d4 58 <body>
Kovalev_D 23:12e6183f04d4 59 <h1>Cortex Microcontroller Software Interface Standard</h1>
Kovalev_D 23:12e6183f04d4 60
Kovalev_D 23:12e6183f04d4 61 <p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
Kovalev_D 23:12e6183f04d4 62 <p align="center">Version: 1.30 - 30. October 2009</p>
Kovalev_D 23:12e6183f04d4 63
Kovalev_D 23:12e6183f04d4 64 <p class="TinyT">Information in this file, the accompany manuals, and software is<br>
Kovalev_D 23:12e6183f04d4 65 Copyright © ARM Ltd.<br>All rights reserved.
Kovalev_D 23:12e6183f04d4 66 </p>
Kovalev_D 23:12e6183f04d4 67
Kovalev_D 23:12e6183f04d4 68 <hr>
Kovalev_D 23:12e6183f04d4 69
Kovalev_D 23:12e6183f04d4 70 <p><span style="FONT-WEIGHT: bold">Revision History</span></p>
Kovalev_D 23:12e6183f04d4 71 <ul>
Kovalev_D 23:12e6183f04d4 72 <li>Version 1.00: initial release. </li>
Kovalev_D 23:12e6183f04d4 73 <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
Kovalev_D 23:12e6183f04d4 74 <li>Version 1.02: added Cortex-M0. </li>
Kovalev_D 23:12e6183f04d4 75 <li>Version 1.10: second review. </li>
Kovalev_D 23:12e6183f04d4 76 <li>Version 1.20: third review. </li>
Kovalev_D 23:12e6183f04d4 77 <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>
Kovalev_D 23:12e6183f04d4 78 <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>
Kovalev_D 23:12e6183f04d4 79 <li>Version 1.30: updated Device Support Packages.</li>
Kovalev_D 23:12e6183f04d4 80 </ul>
Kovalev_D 23:12e6183f04d4 81
Kovalev_D 23:12e6183f04d4 82 <hr>
Kovalev_D 23:12e6183f04d4 83
Kovalev_D 23:12e6183f04d4 84 <h2>Contents</h2>
Kovalev_D 23:12e6183f04d4 85
Kovalev_D 23:12e6183f04d4 86 <ol>
Kovalev_D 23:12e6183f04d4 87 <li class="LI2"><a href="#1">About</a></li>
Kovalev_D 23:12e6183f04d4 88 <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
Kovalev_D 23:12e6183f04d4 89 <li class="LI2"><a href="#3">CMSIS Files</a></li>
Kovalev_D 23:12e6183f04d4 90 <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
Kovalev_D 23:12e6183f04d4 91 <li class="LI2"><a href="#5">CMSIS Example</a></li>
Kovalev_D 23:12e6183f04d4 92 </ol>
Kovalev_D 23:12e6183f04d4 93
Kovalev_D 23:12e6183f04d4 94 <h2><a name="1"></a>About</h2>
Kovalev_D 23:12e6183f04d4 95
Kovalev_D 23:12e6183f04d4 96 <p>
Kovalev_D 23:12e6183f04d4 97 The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
Kovalev_D 23:12e6183f04d4 98 that are faced when software components are deployed to physical microcontroller devices based on a
Kovalev_D 23:12e6183f04d4 99 Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
Kovalev_D 23:12e6183f04d4 100 processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
Kovalev_D 23:12e6183f04d4 101 with various silicon and software vendors and provides a common approach to interface to peripherals,
Kovalev_D 23:12e6183f04d4 102 real-time operating systems, and middleware components.
Kovalev_D 23:12e6183f04d4 103 </p>
Kovalev_D 23:12e6183f04d4 104
Kovalev_D 23:12e6183f04d4 105 <p>ARM provides as part of the CMSIS the following software layers that are
Kovalev_D 23:12e6183f04d4 106 available for various compiler implementations:</p>
Kovalev_D 23:12e6183f04d4 107 <ul>
Kovalev_D 23:12e6183f04d4 108 <li><strong>Core Peripheral Access Layer</strong>: contains name definitions,
Kovalev_D 23:12e6183f04d4 109 address definitions and helper functions to
Kovalev_D 23:12e6183f04d4 110 access core registers and peripherals. It defines also a device
Kovalev_D 23:12e6183f04d4 111 independent interface for RTOS Kernels that includes debug channel
Kovalev_D 23:12e6183f04d4 112 definitions.</li>
Kovalev_D 23:12e6183f04d4 113 </ul>
Kovalev_D 23:12e6183f04d4 114
Kovalev_D 23:12e6183f04d4 115 <p>These software layers are expanded by Silicon partners with:</p>
Kovalev_D 23:12e6183f04d4 116 <ul>
Kovalev_D 23:12e6183f04d4 117 <li><strong>Device Peripheral Access Layer</strong>: provides definitions
Kovalev_D 23:12e6183f04d4 118 for all device peripherals</li>
Kovalev_D 23:12e6183f04d4 119 <li><strong>Access Functions for Peripherals (optional)</strong>: provides
Kovalev_D 23:12e6183f04d4 120 additional helper functions for peripherals</li>
Kovalev_D 23:12e6183f04d4 121 </ul>
Kovalev_D 23:12e6183f04d4 122
Kovalev_D 23:12e6183f04d4 123 <p>CMSIS defines for a Cortex-M Microcontroller System:</p>
Kovalev_D 23:12e6183f04d4 124 <ul>
Kovalev_D 23:12e6183f04d4 125 <li style="text-align: left;">A common way to access peripheral registers
Kovalev_D 23:12e6183f04d4 126 and a common way to define exception vectors.</li>
Kovalev_D 23:12e6183f04d4 127 <li style="text-align: left;">The register names of the <strong>Core
Kovalev_D 23:12e6183f04d4 128 Peripherals</strong> and<strong> </strong>the names of the <strong>Core
Kovalev_D 23:12e6183f04d4 129 Exception Vectors</strong>.</li>
Kovalev_D 23:12e6183f04d4 130 <li>An device independent interface for RTOS Kernels including a debug
Kovalev_D 23:12e6183f04d4 131 channel.</li>
Kovalev_D 23:12e6183f04d4 132 </ul>
Kovalev_D 23:12e6183f04d4 133
Kovalev_D 23:12e6183f04d4 134 <p>
Kovalev_D 23:12e6183f04d4 135 By using CMSIS compliant software components, the user can easier re-use template code.
Kovalev_D 23:12e6183f04d4 136 CMSIS is intended to enable the combination of software components from multiple middleware vendors.
Kovalev_D 23:12e6183f04d4 137 </p>
Kovalev_D 23:12e6183f04d4 138
Kovalev_D 23:12e6183f04d4 139 <h2><a name="2"></a>Coding Rules and Conventions</h2>
Kovalev_D 23:12e6183f04d4 140
Kovalev_D 23:12e6183f04d4 141 <p>
Kovalev_D 23:12e6183f04d4 142 The following section describes the coding rules and conventions used in the CMSIS
Kovalev_D 23:12e6183f04d4 143 implementation. It contains also information about data types and version number information.
Kovalev_D 23:12e6183f04d4 144 </p>
Kovalev_D 23:12e6183f04d4 145
Kovalev_D 23:12e6183f04d4 146 <h3>Essentials</h3>
Kovalev_D 23:12e6183f04d4 147 <ul>
Kovalev_D 23:12e6183f04d4 148 <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
Kovalev_D 23:12e6183f04d4 149 there are disable and enable sequences for PC-LINT inserted.</li>
Kovalev_D 23:12e6183f04d4 150 <li>ANSI standard data types defined in the ANSI C header file
Kovalev_D 23:12e6183f04d4 151 <strong>&lt;stdint.h&gt;</strong> are used.</li>
Kovalev_D 23:12e6183f04d4 152 <li>#define constants that include expressions must be enclosed by
Kovalev_D 23:12e6183f04d4 153 parenthesis.</li>
Kovalev_D 23:12e6183f04d4 154 <li>Variables and parameters have a complete data type.</li>
Kovalev_D 23:12e6183f04d4 155 <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
Kovalev_D 23:12e6183f04d4 156 re-entrant.</li>
Kovalev_D 23:12e6183f04d4 157 <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
Kovalev_D 23:12e6183f04d4 158 (which means that wait/query loops are done at other software layers).</li>
Kovalev_D 23:12e6183f04d4 159 <li>For each exception/interrupt there is definition for:
Kovalev_D 23:12e6183f04d4 160 <ul>
Kovalev_D 23:12e6183f04d4 161 <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
Kovalev_D 23:12e6183f04d4 162 (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
Kovalev_D 23:12e6183f04d4 163 <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
Kovalev_D 23:12e6183f04d4 164 <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
Kovalev_D 23:12e6183f04d4 165 </ul></li>
Kovalev_D 23:12e6183f04d4 166 </ul>
Kovalev_D 23:12e6183f04d4 167
Kovalev_D 23:12e6183f04d4 168 <h3>Recommendations</h3>
Kovalev_D 23:12e6183f04d4 169
Kovalev_D 23:12e6183f04d4 170 <p>The CMSIS recommends the following conventions for identifiers.</p>
Kovalev_D 23:12e6183f04d4 171 <ul>
Kovalev_D 23:12e6183f04d4 172 <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
Kovalev_D 23:12e6183f04d4 173 <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
Kovalev_D 23:12e6183f04d4 174 <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
Kovalev_D 23:12e6183f04d4 175 <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
Kovalev_D 23:12e6183f04d4 176 </ul>
Kovalev_D 23:12e6183f04d4 177
Kovalev_D 23:12e6183f04d4 178 <b>Comments</b>
Kovalev_D 23:12e6183f04d4 179
Kovalev_D 23:12e6183f04d4 180 <ul>
Kovalev_D 23:12e6183f04d4 181 <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style
Kovalev_D 23:12e6183f04d4 182 (<em>// comment</em>). It is assumed that the programming tools support today
Kovalev_D 23:12e6183f04d4 183 consistently the C++ comment style.</li>
Kovalev_D 23:12e6183f04d4 184 <li><strong>Function Comments</strong> provide for each function the following information:
Kovalev_D 23:12e6183f04d4 185 <ul>
Kovalev_D 23:12e6183f04d4 186 <li>one-line brief function overview.</li>
Kovalev_D 23:12e6183f04d4 187 <li>detailed parameter explanation.</li>
Kovalev_D 23:12e6183f04d4 188 <li>detailed information about return values.</li>
Kovalev_D 23:12e6183f04d4 189 <li>detailed description of the actual function.</li>
Kovalev_D 23:12e6183f04d4 190 </ul>
Kovalev_D 23:12e6183f04d4 191 <p><b>Doxygen Example:</b></p>
Kovalev_D 23:12e6183f04d4 192 <pre>
Kovalev_D 23:12e6183f04d4 193 /**
Kovalev_D 23:12e6183f04d4 194 * @brief Enable Interrupt in NVIC Interrupt Controller
Kovalev_D 23:12e6183f04d4 195 * @param IRQn interrupt number that specifies the interrupt
Kovalev_D 23:12e6183f04d4 196 * @return none.
Kovalev_D 23:12e6183f04d4 197 * Enable the specified interrupt in the NVIC Interrupt Controller.
Kovalev_D 23:12e6183f04d4 198 * Other settings of the interrupt such as priority are not affected.
Kovalev_D 23:12e6183f04d4 199 */</pre>
Kovalev_D 23:12e6183f04d4 200 </li>
Kovalev_D 23:12e6183f04d4 201 </ul>
Kovalev_D 23:12e6183f04d4 202
Kovalev_D 23:12e6183f04d4 203 <h3>Data Types and IO Type Qualifiers</h3>
Kovalev_D 23:12e6183f04d4 204
Kovalev_D 23:12e6183f04d4 205 <p>
Kovalev_D 23:12e6183f04d4 206 The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file
Kovalev_D 23:12e6183f04d4 207 <strong>&lt;stdint.h&gt;</strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
Kovalev_D 23:12e6183f04d4 208 to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
Kovalev_D 23:12e6183f04d4 209 debug information of peripheral registers.
Kovalev_D 23:12e6183f04d4 210 </p>
Kovalev_D 23:12e6183f04d4 211
Kovalev_D 23:12e6183f04d4 212 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 213 <tbody>
Kovalev_D 23:12e6183f04d4 214 <tr>
Kovalev_D 23:12e6183f04d4 215 <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
Kovalev_D 23:12e6183f04d4 216 <th class="kt">#define</th>
Kovalev_D 23:12e6183f04d4 217 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 218 </tr>
Kovalev_D 23:12e6183f04d4 219 <tr>
Kovalev_D 23:12e6183f04d4 220 <td class="kt" nowrap="nowrap">__I</td>
Kovalev_D 23:12e6183f04d4 221 <td class="kt">volatile const</td>
Kovalev_D 23:12e6183f04d4 222 <td class="kt">Read access only</td>
Kovalev_D 23:12e6183f04d4 223 </tr>
Kovalev_D 23:12e6183f04d4 224 <tr>
Kovalev_D 23:12e6183f04d4 225 <td class="kt" nowrap="nowrap">__O</td>
Kovalev_D 23:12e6183f04d4 226 <td class="kt">volatile</td>
Kovalev_D 23:12e6183f04d4 227 <td class="kt">Write access only</td>
Kovalev_D 23:12e6183f04d4 228 </tr>
Kovalev_D 23:12e6183f04d4 229 <tr>
Kovalev_D 23:12e6183f04d4 230 <td class="kt" nowrap="nowrap">__IO</td>
Kovalev_D 23:12e6183f04d4 231 <td class="kt">volatile</td>
Kovalev_D 23:12e6183f04d4 232 <td class="kt">Read and write access</td>
Kovalev_D 23:12e6183f04d4 233 </tr>
Kovalev_D 23:12e6183f04d4 234 </tbody>
Kovalev_D 23:12e6183f04d4 235 </table>
Kovalev_D 23:12e6183f04d4 236
Kovalev_D 23:12e6183f04d4 237 <h3>CMSIS Version Number</h3>
Kovalev_D 23:12e6183f04d4 238 <p>
Kovalev_D 23:12e6183f04d4 239 File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
Kovalev_D 23:12e6183f04d4 240 </p>
Kovalev_D 23:12e6183f04d4 241
Kovalev_D 23:12e6183f04d4 242 <pre>
Kovalev_D 23:12e6183f04d4 243 #define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
Kovalev_D 23:12e6183f04d4 244 #define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
Kovalev_D 23:12e6183f04d4 245 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM3_CMSIS_VERSION_SUB)</pre>
Kovalev_D 23:12e6183f04d4 246
Kovalev_D 23:12e6183f04d4 247 <p>
Kovalev_D 23:12e6183f04d4 248 File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
Kovalev_D 23:12e6183f04d4 249 </p>
Kovalev_D 23:12e6183f04d4 250
Kovalev_D 23:12e6183f04d4 251 <pre>
Kovalev_D 23:12e6183f04d4 252 #define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
Kovalev_D 23:12e6183f04d4 253 #define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
Kovalev_D 23:12e6183f04d4 254 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM0_CMSIS_VERSION_SUB)</pre>
Kovalev_D 23:12e6183f04d4 255
Kovalev_D 23:12e6183f04d4 256
Kovalev_D 23:12e6183f04d4 257 <h3>CMSIS Cortex Core</h3>
Kovalev_D 23:12e6183f04d4 258 <p>
Kovalev_D 23:12e6183f04d4 259 File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:
Kovalev_D 23:12e6183f04d4 260 </p>
Kovalev_D 23:12e6183f04d4 261
Kovalev_D 23:12e6183f04d4 262 <pre>
Kovalev_D 23:12e6183f04d4 263 #define __CORTEX_M (0x03)</pre>
Kovalev_D 23:12e6183f04d4 264
Kovalev_D 23:12e6183f04d4 265 <p>
Kovalev_D 23:12e6183f04d4 266 File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:
Kovalev_D 23:12e6183f04d4 267 </p>
Kovalev_D 23:12e6183f04d4 268
Kovalev_D 23:12e6183f04d4 269 <pre>
Kovalev_D 23:12e6183f04d4 270 #define __CORTEX_M (0x00)</pre>
Kovalev_D 23:12e6183f04d4 271
Kovalev_D 23:12e6183f04d4 272
Kovalev_D 23:12e6183f04d4 273 <h2><a name="3"></a>CMSIS Files</h2>
Kovalev_D 23:12e6183f04d4 274 <p>
Kovalev_D 23:12e6183f04d4 275 This section describes the Files provided in context with the CMSIS to access the Cortex-M
Kovalev_D 23:12e6183f04d4 276 hardware and peripherals.
Kovalev_D 23:12e6183f04d4 277 </p>
Kovalev_D 23:12e6183f04d4 278
Kovalev_D 23:12e6183f04d4 279 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 280 <tbody>
Kovalev_D 23:12e6183f04d4 281 <tr>
Kovalev_D 23:12e6183f04d4 282 <th class="kt" nowrap="nowrap">File</th>
Kovalev_D 23:12e6183f04d4 283 <th class="kt">Provider</th>
Kovalev_D 23:12e6183f04d4 284 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 285 </tr>
Kovalev_D 23:12e6183f04d4 286 <tr>
Kovalev_D 23:12e6183f04d4 287 <td class="kt" nowrap="nowrap"><i>device.h</i></td>
Kovalev_D 23:12e6183f04d4 288 <td class="kt">Device specific (provided by silicon partner)</td>
Kovalev_D 23:12e6183f04d4 289 <td class="kt">Defines the peripherals for the actual device. The file may use
Kovalev_D 23:12e6183f04d4 290 several other include files to define the peripherals of the actual device.</td>
Kovalev_D 23:12e6183f04d4 291 </tr>
Kovalev_D 23:12e6183f04d4 292 <tr>
Kovalev_D 23:12e6183f04d4 293 <td class="kt" nowrap="nowrap">core_cm0.h</td>
Kovalev_D 23:12e6183f04d4 294 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
Kovalev_D 23:12e6183f04d4 295 <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
Kovalev_D 23:12e6183f04d4 296 </tr>
Kovalev_D 23:12e6183f04d4 297 <tr>
Kovalev_D 23:12e6183f04d4 298 <td class="kt" nowrap="nowrap">core_cm3.h</td>
Kovalev_D 23:12e6183f04d4 299 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
Kovalev_D 23:12e6183f04d4 300 <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
Kovalev_D 23:12e6183f04d4 301 </tr>
Kovalev_D 23:12e6183f04d4 302 <tr>
Kovalev_D 23:12e6183f04d4 303 <td class="kt" nowrap="nowrap">core_cm0.c</td>
Kovalev_D 23:12e6183f04d4 304 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
Kovalev_D 23:12e6183f04d4 305 <td class="kt">Provides helper functions that access core registers.</td>
Kovalev_D 23:12e6183f04d4 306 </tr>
Kovalev_D 23:12e6183f04d4 307 <tr>
Kovalev_D 23:12e6183f04d4 308 <td class="kt" nowrap="nowrap">core_cm3.c</td>
Kovalev_D 23:12e6183f04d4 309 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
Kovalev_D 23:12e6183f04d4 310 <td class="kt">Provides helper functions that access core registers.</td>
Kovalev_D 23:12e6183f04d4 311 </tr>
Kovalev_D 23:12e6183f04d4 312 <tr>
Kovalev_D 23:12e6183f04d4 313 <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
Kovalev_D 23:12e6183f04d4 314 <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
Kovalev_D 23:12e6183f04d4 315 <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>
Kovalev_D 23:12e6183f04d4 316 </tr>
Kovalev_D 23:12e6183f04d4 317 <tr>
Kovalev_D 23:12e6183f04d4 318 <td class="kt" nowrap="nowrap">system<i>_device</i></td>
Kovalev_D 23:12e6183f04d4 319 <td class="kt">ARM (adapted by silicon partner)</td>
Kovalev_D 23:12e6183f04d4 320 <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes
Kovalev_D 23:12e6183f04d4 321 typically the oscillator (PLL) that is part of the microcontroller device</td>
Kovalev_D 23:12e6183f04d4 322 </tr>
Kovalev_D 23:12e6183f04d4 323 </tbody>
Kovalev_D 23:12e6183f04d4 324 </table>
Kovalev_D 23:12e6183f04d4 325
Kovalev_D 23:12e6183f04d4 326 <h3><em>device.h</em></h3>
Kovalev_D 23:12e6183f04d4 327
Kovalev_D 23:12e6183f04d4 328 <p>
Kovalev_D 23:12e6183f04d4 329 The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the
Kovalev_D 23:12e6183f04d4 330 <u><strong>central include file</strong></u> that the application programmer is using in
Kovalev_D 23:12e6183f04d4 331 the C source code. This file contains:
Kovalev_D 23:12e6183f04d4 332 </p>
Kovalev_D 23:12e6183f04d4 333 <ul>
Kovalev_D 23:12e6183f04d4 334 <li>
Kovalev_D 23:12e6183f04d4 335 <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers
Kovalev_D 23:12e6183f04d4 336 (IRQn) for all core and device specific exceptions and interrupts.</p>
Kovalev_D 23:12e6183f04d4 337 </li>
Kovalev_D 23:12e6183f04d4 338 <li>
Kovalev_D 23:12e6183f04d4 339 <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the
Kovalev_D 23:12e6183f04d4 340 actual configuration of the Cortex-M processor that is part of the actual
Kovalev_D 23:12e6183f04d4 341 device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that
Kovalev_D 23:12e6183f04d4 342 implements access to processor registers and core peripherals. </p>
Kovalev_D 23:12e6183f04d4 343 </li>
Kovalev_D 23:12e6183f04d4 344 <li>
Kovalev_D 23:12e6183f04d4 345 <p><strong>Device Peripheral Access Layer</strong>: provides definitions
Kovalev_D 23:12e6183f04d4 346 for all device peripherals. It contains all data structures and the address
Kovalev_D 23:12e6183f04d4 347 mapping for the device specific peripherals. </p>
Kovalev_D 23:12e6183f04d4 348 </li>
Kovalev_D 23:12e6183f04d4 349 <li><strong>Access Functions for Peripherals (optional)</strong>: provides
Kovalev_D 23:12e6183f04d4 350 additional helper functions for peripherals that are useful for programming
Kovalev_D 23:12e6183f04d4 351 of these peripherals. Access Functions may be provided as inline functions
Kovalev_D 23:12e6183f04d4 352 or can be extern references to a device specific library provided by the
Kovalev_D 23:12e6183f04d4 353 silicon vendor.</li>
Kovalev_D 23:12e6183f04d4 354 </ul>
Kovalev_D 23:12e6183f04d4 355
Kovalev_D 23:12e6183f04d4 356
Kovalev_D 23:12e6183f04d4 357 <h4><strong>Interrupt Number Definition</strong></h4>
Kovalev_D 23:12e6183f04d4 358
Kovalev_D 23:12e6183f04d4 359 <p>To access the device specific interrupts the device.h file defines IRQn
Kovalev_D 23:12e6183f04d4 360 numbers for the complete device using a enum typedef as shown below:</p>
Kovalev_D 23:12e6183f04d4 361 <pre>
Kovalev_D 23:12e6183f04d4 362 typedef enum IRQn
Kovalev_D 23:12e6183f04d4 363 {
Kovalev_D 23:12e6183f04d4 364 /****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
Kovalev_D 23:12e6183f04d4 365 NonMaskableInt_IRQn = -14, /*!&lt; 2 Non Maskable Interrupt */
Kovalev_D 23:12e6183f04d4 366 HardFault_IRQn = -13, /*!&lt; 3 Cortex-M3 Hard Fault Interrupt */
Kovalev_D 23:12e6183f04d4 367 MemoryManagement_IRQn = -12, /*!&lt; 4 Cortex-M3 Memory Management Interrupt */
Kovalev_D 23:12e6183f04d4 368 BusFault_IRQn = -11, /*!&lt; 5 Cortex-M3 Bus Fault Interrupt */
Kovalev_D 23:12e6183f04d4 369 UsageFault_IRQn = -10, /*!&lt; 6 Cortex-M3 Usage Fault Interrupt */
Kovalev_D 23:12e6183f04d4 370 SVCall_IRQn = -5, /*!&lt; 11 Cortex-M3 SV Call Interrupt */
Kovalev_D 23:12e6183f04d4 371 DebugMonitor_IRQn = -4, /*!&lt; 12 Cortex-M3 Debug Monitor Interrupt */
Kovalev_D 23:12e6183f04d4 372 PendSV_IRQn = -2, /*!&lt; 14 Cortex-M3 Pend SV Interrupt */
Kovalev_D 23:12e6183f04d4 373 SysTick_IRQn = -1, /*!&lt; 15 Cortex-M3 System Tick Interrupt */
Kovalev_D 23:12e6183f04d4 374 /****** STM32 specific Interrupt Numbers ****************************************************************/
Kovalev_D 23:12e6183f04d4 375 WWDG_STM_IRQn = 0, /*!&lt; Window WatchDog Interrupt */
Kovalev_D 23:12e6183f04d4 376 PVD_STM_IRQn = 1, /*!&lt; PVD through EXTI Line detection Interrupt */
Kovalev_D 23:12e6183f04d4 377 :
Kovalev_D 23:12e6183f04d4 378 :
Kovalev_D 23:12e6183f04d4 379 } IRQn_Type;</pre>
Kovalev_D 23:12e6183f04d4 380
Kovalev_D 23:12e6183f04d4 381
Kovalev_D 23:12e6183f04d4 382 <h4>Configuration for core_cm0.h / core_cm3.h</h4>
Kovalev_D 23:12e6183f04d4 383 <p>
Kovalev_D 23:12e6183f04d4 384 The Cortex-M core configuration options which are defined for each device implementation. Some
Kovalev_D 23:12e6183f04d4 385 configuration options are reflected in the CMSIS layer using the #define settings described below.
Kovalev_D 23:12e6183f04d4 386 </p>
Kovalev_D 23:12e6183f04d4 387 <p>
Kovalev_D 23:12e6183f04d4 388 To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
Kovalev_D 23:12e6183f04d4 389 Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be
Kovalev_D 23:12e6183f04d4 390 defined before <strong>#include &lt;core_cm0.h&gt;</strong> / <strong>#include &lt;core_cm3.h&gt;</strong>
Kovalev_D 23:12e6183f04d4 391 preprocessor command.
Kovalev_D 23:12e6183f04d4 392 </p>
Kovalev_D 23:12e6183f04d4 393
Kovalev_D 23:12e6183f04d4 394 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 395 <tbody>
Kovalev_D 23:12e6183f04d4 396 <tr>
Kovalev_D 23:12e6183f04d4 397 <th class="kt" nowrap="nowrap">#define</th>
Kovalev_D 23:12e6183f04d4 398 <th class="kt" nowrap="nowrap">File</th>
Kovalev_D 23:12e6183f04d4 399 <th class="kt" nowrap="nowrap">Value</th>
Kovalev_D 23:12e6183f04d4 400 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 401 </tr>
Kovalev_D 23:12e6183f04d4 402 <tr>
Kovalev_D 23:12e6183f04d4 403 <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
Kovalev_D 23:12e6183f04d4 404 <td class="kt">core_cm0.h</td>
Kovalev_D 23:12e6183f04d4 405 <td class="kt" nowrap="nowrap">(2)</td>
Kovalev_D 23:12e6183f04d4 406 <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
Kovalev_D 23:12e6183f04d4 407 </tr>
Kovalev_D 23:12e6183f04d4 408 <tr>
Kovalev_D 23:12e6183f04d4 409 <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
Kovalev_D 23:12e6183f04d4 410 <td class="kt">core_cm3.h</td>
Kovalev_D 23:12e6183f04d4 411 <td class="kt" nowrap="nowrap">(2 ... 8)</td>
Kovalev_D 23:12e6183f04d4 412 <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
Kovalev_D 23:12e6183f04d4 413 </tr>
Kovalev_D 23:12e6183f04d4 414 <tr>
Kovalev_D 23:12e6183f04d4 415 <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
Kovalev_D 23:12e6183f04d4 416 <td class="kt">core_cm0.h, core_cm3.h</td>
Kovalev_D 23:12e6183f04d4 417 <td class="kt" nowrap="nowrap">(0, 1)</td>
Kovalev_D 23:12e6183f04d4 418 <td class="kt">Defines if an MPU is present or not</td>
Kovalev_D 23:12e6183f04d4 419 </tr>
Kovalev_D 23:12e6183f04d4 420 <tr>
Kovalev_D 23:12e6183f04d4 421 <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
Kovalev_D 23:12e6183f04d4 422 <td class="kt">core_cm0.h, core_cm3.h</td>
Kovalev_D 23:12e6183f04d4 423 <td class="kt" nowrap="nowrap">(1)</td>
Kovalev_D 23:12e6183f04d4 424 <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function
Kovalev_D 23:12e6183f04d4 425 in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em>
Kovalev_D 23:12e6183f04d4 426 file must contain a vendor specific implementation of this function.</td>
Kovalev_D 23:12e6183f04d4 427 </tr>
Kovalev_D 23:12e6183f04d4 428 </tbody>
Kovalev_D 23:12e6183f04d4 429 </table>
Kovalev_D 23:12e6183f04d4 430
Kovalev_D 23:12e6183f04d4 431
Kovalev_D 23:12e6183f04d4 432 <h4>Device Peripheral Access Layer</h4>
Kovalev_D 23:12e6183f04d4 433 <p>
Kovalev_D 23:12e6183f04d4 434 Each peripheral uses a prefix which consists of <strong>&lt;device abbreviation&gt;_</strong>
Kovalev_D 23:12e6183f04d4 435 and <strong>&lt;peripheral name&gt;_</strong> to identify peripheral registers that access this
Kovalev_D 23:12e6183f04d4 436 specific peripheral. The intention of this is to avoid name collisions caused
Kovalev_D 23:12e6183f04d4 437 due to short names. If more than one peripheral of the same type exists,
Kovalev_D 23:12e6183f04d4 438 identifiers have a postfix (digit or letter). For example:
Kovalev_D 23:12e6183f04d4 439 </p>
Kovalev_D 23:12e6183f04d4 440 <ul>
Kovalev_D 23:12e6183f04d4 441 <li>&lt;device abbreviation&gt;_UART_Type: defines the generic register layout for all UART channels in a device.
Kovalev_D 23:12e6183f04d4 442 <pre>
Kovalev_D 23:12e6183f04d4 443 typedef struct
Kovalev_D 23:12e6183f04d4 444 {
Kovalev_D 23:12e6183f04d4 445 union {
Kovalev_D 23:12e6183f04d4 446 __I uint8_t RBR; /*!< Offset: 0x000 Receiver Buffer Register */
Kovalev_D 23:12e6183f04d4 447 __O uint8_t THR; /*!< Offset: 0x000 Transmit Holding Register */
Kovalev_D 23:12e6183f04d4 448 __IO uint8_t DLL; /*!< Offset: 0x000 Divisor Latch LSB */
Kovalev_D 23:12e6183f04d4 449 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 450 };
Kovalev_D 23:12e6183f04d4 451 union {
Kovalev_D 23:12e6183f04d4 452 __IO uint8_t DLM; /*!< Offset: 0x004 Divisor Latch MSB */
Kovalev_D 23:12e6183f04d4 453 __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 454 };
Kovalev_D 23:12e6183f04d4 455 union {
Kovalev_D 23:12e6183f04d4 456 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register */
Kovalev_D 23:12e6183f04d4 457 __O uint8_t FCR; /*!< Offset: 0x008 FIFO Control Register */
Kovalev_D 23:12e6183f04d4 458 };
Kovalev_D 23:12e6183f04d4 459 __IO uint8_t LCR; /*!< Offset: 0x00C Line Control Register */
Kovalev_D 23:12e6183f04d4 460 uint8_t RESERVED1[7];
Kovalev_D 23:12e6183f04d4 461 __I uint8_t LSR; /*!< Offset: 0x014 Line Status Register */
Kovalev_D 23:12e6183f04d4 462 uint8_t RESERVED2[7];
Kovalev_D 23:12e6183f04d4 463 __IO uint8_t SCR; /*!< Offset: 0x01C Scratch Pad Register */
Kovalev_D 23:12e6183f04d4 464 uint8_t RESERVED3[3];
Kovalev_D 23:12e6183f04d4 465 __IO uint32_t ACR; /*!< Offset: 0x020 Autobaud Control Register */
Kovalev_D 23:12e6183f04d4 466 __IO uint8_t ICR; /*!< Offset: 0x024 IrDA Control Register */
Kovalev_D 23:12e6183f04d4 467 uint8_t RESERVED4[3];
Kovalev_D 23:12e6183f04d4 468 __IO uint8_t FDR; /*!< Offset: 0x028 Fractional Divider Register */
Kovalev_D 23:12e6183f04d4 469 uint8_t RESERVED5[7];
Kovalev_D 23:12e6183f04d4 470 __IO uint8_t TER; /*!< Offset: 0x030 Transmit Enable Register */
Kovalev_D 23:12e6183f04d4 471 uint8_t RESERVED6[39];
Kovalev_D 23:12e6183f04d4 472 __I uint8_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register */
Kovalev_D 23:12e6183f04d4 473 } LPC_UART_TypeDef;</pre>
Kovalev_D 23:12e6183f04d4 474 </li>
Kovalev_D 23:12e6183f04d4 475 <li>&lt;device abbreviation&gt;_UART1: is a pointer to a register structure that refers to a specific UART.
Kovalev_D 23:12e6183f04d4 476 For example UART1-&gt;DR is the data register of UART1.
Kovalev_D 23:12e6183f04d4 477 <pre>
Kovalev_D 23:12e6183f04d4 478 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
Kovalev_D 23:12e6183f04d4 479 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</pre>
Kovalev_D 23:12e6183f04d4 480 </li>
Kovalev_D 23:12e6183f04d4 481 </ul>
Kovalev_D 23:12e6183f04d4 482
Kovalev_D 23:12e6183f04d4 483 <h5>Minimal Requiements</h5>
Kovalev_D 23:12e6183f04d4 484 <p>
Kovalev_D 23:12e6183f04d4 485 To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong>
Kovalev_D 23:12e6183f04d4 486 and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
Kovalev_D 23:12e6183f04d4 487 </p>
Kovalev_D 23:12e6183f04d4 488 <ul>
Kovalev_D 23:12e6183f04d4 489 <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
Kovalev_D 23:12e6183f04d4 490 Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
Kovalev_D 23:12e6183f04d4 491 the peripheral registers. For example:
Kovalev_D 23:12e6183f04d4 492 <pre>
Kovalev_D 23:12e6183f04d4 493 typedef struct {
Kovalev_D 23:12e6183f04d4 494 __IO uint32_t CTRL; /* SysTick Control and Status Register */
Kovalev_D 23:12e6183f04d4 495 __IO uint32_t LOAD; /* SysTick Reload Value Register */
Kovalev_D 23:12e6183f04d4 496 __IO uint32_t VAL; /* SysTick Current Value Register */
Kovalev_D 23:12e6183f04d4 497 __I uint32_t CALIB; /* SysTick Calibration Register */
Kovalev_D 23:12e6183f04d4 498 } SysTick_Type;</pre>
Kovalev_D 23:12e6183f04d4 499 </li>
Kovalev_D 23:12e6183f04d4 500
Kovalev_D 23:12e6183f04d4 501 <li>
Kovalev_D 23:12e6183f04d4 502 <strong>Base Address</strong> for each peripheral (in case of multiple peripherals
Kovalev_D 23:12e6183f04d4 503 that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
Kovalev_D 23:12e6183f04d4 504 <pre>
Kovalev_D 23:12e6183f04d4 505 #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre>
Kovalev_D 23:12e6183f04d4 506 </li>
Kovalev_D 23:12e6183f04d4 507
Kovalev_D 23:12e6183f04d4 508 <li>
Kovalev_D 23:12e6183f04d4 509 <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use
Kovalev_D 23:12e6183f04d4 510 the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0,
Kovalev_D 23:12e6183f04d4 511 LPC_UART2). For Example:
Kovalev_D 23:12e6183f04d4 512 <pre>
Kovalev_D 23:12e6183f04d4 513 #define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre>
Kovalev_D 23:12e6183f04d4 514 </li>
Kovalev_D 23:12e6183f04d4 515 </ul>
Kovalev_D 23:12e6183f04d4 516
Kovalev_D 23:12e6183f04d4 517 <p>
Kovalev_D 23:12e6183f04d4 518 These definitions allow to access the peripheral registers from user code with simple assignments like:
Kovalev_D 23:12e6183f04d4 519 </p>
Kovalev_D 23:12e6183f04d4 520 <pre>SysTick-&gt;CTRL = 0;</pre>
Kovalev_D 23:12e6183f04d4 521
Kovalev_D 23:12e6183f04d4 522 <h5>Optional Features</h5>
Kovalev_D 23:12e6183f04d4 523 <p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
Kovalev_D 23:12e6183f04d4 524 <ul>
Kovalev_D 23:12e6183f04d4 525 <li>
Kovalev_D 23:12e6183f04d4 526 #define constants that simplify access to the peripheral registers.
Kovalev_D 23:12e6183f04d4 527 These constant define bit-positions or other specific patterns are that required for the
Kovalev_D 23:12e6183f04d4 528 programming of the peripheral registers. The identifiers used start with
Kovalev_D 23:12e6183f04d4 529 <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>.
Kovalev_D 23:12e6183f04d4 530 It is recommended to use CAPITAL letters for such #define constants.
Kovalev_D 23:12e6183f04d4 531 </li>
Kovalev_D 23:12e6183f04d4 532 <li>
Kovalev_D 23:12e6183f04d4 533 Functions that perform more complex functions with the peripheral (i.e. status query before
Kovalev_D 23:12e6183f04d4 534 a sending register is accessed). Again these function start with
Kovalev_D 23:12e6183f04d4 535 <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>.
Kovalev_D 23:12e6183f04d4 536 </li>
Kovalev_D 23:12e6183f04d4 537 </ul>
Kovalev_D 23:12e6183f04d4 538
Kovalev_D 23:12e6183f04d4 539 <h3>core_cm0.h and core_cm0.c</h3>
Kovalev_D 23:12e6183f04d4 540 <p>
Kovalev_D 23:12e6183f04d4 541 File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does
Kovalev_D 23:12e6183f04d4 542 the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
Kovalev_D 23:12e6183f04d4 543 and core peripherals with efficient functions (defined as <strong>static inline</strong>).
Kovalev_D 23:12e6183f04d4 544 </p>
Kovalev_D 23:12e6183f04d4 545 <p>
Kovalev_D 23:12e6183f04d4 546 File <b>core_cm0.c</b> defines several helper functions that access processor registers.
Kovalev_D 23:12e6183f04d4 547 </p>
Kovalev_D 23:12e6183f04d4 548 <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
Kovalev_D 23:12e6183f04d4 549
Kovalev_D 23:12e6183f04d4 550 <h3>core_cm3.h and core_cm3.c</h3>
Kovalev_D 23:12e6183f04d4 551 <p>
Kovalev_D 23:12e6183f04d4 552 File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does
Kovalev_D 23:12e6183f04d4 553 the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
Kovalev_D 23:12e6183f04d4 554 and core peripherals with efficient functions (defined as <strong>static inline</strong>).
Kovalev_D 23:12e6183f04d4 555 </p>
Kovalev_D 23:12e6183f04d4 556 <p>
Kovalev_D 23:12e6183f04d4 557 File <b>core_cm3.c</b> defines several helper functions that access processor registers.
Kovalev_D 23:12e6183f04d4 558 </p>
Kovalev_D 23:12e6183f04d4 559 <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
Kovalev_D 23:12e6183f04d4 560
Kovalev_D 23:12e6183f04d4 561 <h3>startup_<em>device</em></h3>
Kovalev_D 23:12e6183f04d4 562 <p>
Kovalev_D 23:12e6183f04d4 563 A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
Kovalev_D 23:12e6183f04d4 564 compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
Kovalev_D 23:12e6183f04d4 565 interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function
Kovalev_D 23:12e6183f04d4 566 to an dummy handler. Therefore the interrupt handler can be directly used in application software
Kovalev_D 23:12e6183f04d4 567 without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
Kovalev_D 23:12e6183f04d4 568 </p>
Kovalev_D 23:12e6183f04d4 569 <p>
Kovalev_D 23:12e6183f04d4 570 The following exception names are fixed and define the start of the vector table for a Cortex-M0:
Kovalev_D 23:12e6183f04d4 571 </p>
Kovalev_D 23:12e6183f04d4 572 <pre>
Kovalev_D 23:12e6183f04d4 573 __Vectors DCD __initial_sp ; Top of Stack
Kovalev_D 23:12e6183f04d4 574 DCD Reset_Handler ; Reset Handler
Kovalev_D 23:12e6183f04d4 575 DCD NMI_Handler ; NMI Handler
Kovalev_D 23:12e6183f04d4 576 DCD HardFault_Handler ; Hard Fault Handler
Kovalev_D 23:12e6183f04d4 577 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 578 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 579 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 580 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 581 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 582 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 583 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 584 DCD SVC_Handler ; SVCall Handler
Kovalev_D 23:12e6183f04d4 585 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 586 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 587 DCD PendSV_Handler ; PendSV Handler
Kovalev_D 23:12e6183f04d4 588 DCD SysTick_Handler ; SysTick Handler</pre>
Kovalev_D 23:12e6183f04d4 589
Kovalev_D 23:12e6183f04d4 590 <p>
Kovalev_D 23:12e6183f04d4 591 The following exception names are fixed and define the start of the vector table for a Cortex-M3:
Kovalev_D 23:12e6183f04d4 592 </p>
Kovalev_D 23:12e6183f04d4 593 <pre>
Kovalev_D 23:12e6183f04d4 594 __Vectors DCD __initial_sp ; Top of Stack
Kovalev_D 23:12e6183f04d4 595 DCD Reset_Handler ; Reset Handler
Kovalev_D 23:12e6183f04d4 596 DCD NMI_Handler ; NMI Handler
Kovalev_D 23:12e6183f04d4 597 DCD HardFault_Handler ; Hard Fault Handler
Kovalev_D 23:12e6183f04d4 598 DCD MemManage_Handler ; MPU Fault Handler
Kovalev_D 23:12e6183f04d4 599 DCD BusFault_Handler ; Bus Fault Handler
Kovalev_D 23:12e6183f04d4 600 DCD UsageFault_Handler ; Usage Fault Handler
Kovalev_D 23:12e6183f04d4 601 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 602 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 603 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 604 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 605 DCD SVC_Handler ; SVCall Handler
Kovalev_D 23:12e6183f04d4 606 DCD DebugMon_Handler ; Debug Monitor Handler
Kovalev_D 23:12e6183f04d4 607 DCD 0 ; Reserved
Kovalev_D 23:12e6183f04d4 608 DCD PendSV_Handler ; PendSV Handler
Kovalev_D 23:12e6183f04d4 609 DCD SysTick_Handler ; SysTick Handler</pre>
Kovalev_D 23:12e6183f04d4 610
Kovalev_D 23:12e6183f04d4 611 <p>
Kovalev_D 23:12e6183f04d4 612 In the following examples for device specific interrupts are shown:
Kovalev_D 23:12e6183f04d4 613 </p>
Kovalev_D 23:12e6183f04d4 614 <pre>
Kovalev_D 23:12e6183f04d4 615 ; External Interrupts
Kovalev_D 23:12e6183f04d4 616 DCD WWDG_IRQHandler ; Window Watchdog
Kovalev_D 23:12e6183f04d4 617 DCD PVD_IRQHandler ; PVD through EXTI Line detect
Kovalev_D 23:12e6183f04d4 618 DCD TAMPER_IRQHandler ; Tamper</pre>
Kovalev_D 23:12e6183f04d4 619
Kovalev_D 23:12e6183f04d4 620 <p>
Kovalev_D 23:12e6183f04d4 621 Device specific interrupts must have a dummy function that can be overwritten in user code.
Kovalev_D 23:12e6183f04d4 622 Below is an example for this dummy function.
Kovalev_D 23:12e6183f04d4 623 </p>
Kovalev_D 23:12e6183f04d4 624 <pre>
Kovalev_D 23:12e6183f04d4 625 Default_Handler PROC
Kovalev_D 23:12e6183f04d4 626 EXPORT WWDG_IRQHandler [WEAK]
Kovalev_D 23:12e6183f04d4 627 EXPORT PVD_IRQHandler [WEAK]
Kovalev_D 23:12e6183f04d4 628 EXPORT TAMPER_IRQHandler [WEAK]
Kovalev_D 23:12e6183f04d4 629 :
Kovalev_D 23:12e6183f04d4 630 :
Kovalev_D 23:12e6183f04d4 631 WWDG_IRQHandler
Kovalev_D 23:12e6183f04d4 632 PVD_IRQHandler
Kovalev_D 23:12e6183f04d4 633 TAMPER_IRQHandler
Kovalev_D 23:12e6183f04d4 634 :
Kovalev_D 23:12e6183f04d4 635 :
Kovalev_D 23:12e6183f04d4 636 B .
Kovalev_D 23:12e6183f04d4 637 ENDP</pre>
Kovalev_D 23:12e6183f04d4 638
Kovalev_D 23:12e6183f04d4 639 <p>
Kovalev_D 23:12e6183f04d4 640 The user application may simply define an interrupt handler function by using the handler name
Kovalev_D 23:12e6183f04d4 641 as shown below.
Kovalev_D 23:12e6183f04d4 642 </p>
Kovalev_D 23:12e6183f04d4 643 <pre>
Kovalev_D 23:12e6183f04d4 644 void WWDG_IRQHandler(void)
Kovalev_D 23:12e6183f04d4 645 {
Kovalev_D 23:12e6183f04d4 646 :
Kovalev_D 23:12e6183f04d4 647 :
Kovalev_D 23:12e6183f04d4 648 }</pre>
Kovalev_D 23:12e6183f04d4 649
Kovalev_D 23:12e6183f04d4 650
Kovalev_D 23:12e6183f04d4 651 <h3><a name="4"></a>system_<em>device</em>.c</h3>
Kovalev_D 23:12e6183f04d4 652 <p>
Kovalev_D 23:12e6183f04d4 653 A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by
Kovalev_D 23:12e6183f04d4 654 the silicon vendor to match their actual device. As a <strong>minimum requirement</strong>
Kovalev_D 23:12e6183f04d4 655 this file must provide a device specific system configuration function and a global variable
Kovalev_D 23:12e6183f04d4 656 that contains the system frequency. It configures the device and initializes typically the
Kovalev_D 23:12e6183f04d4 657 oscillator (PLL) that is part of the microcontroller device.
Kovalev_D 23:12e6183f04d4 658 </p>
Kovalev_D 23:12e6183f04d4 659 <p>
Kovalev_D 23:12e6183f04d4 660 The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
Kovalev_D 23:12e6183f04d4 661 as a minimum requirement the SystemInit function as shown below.
Kovalev_D 23:12e6183f04d4 662 </p>
Kovalev_D 23:12e6183f04d4 663
Kovalev_D 23:12e6183f04d4 664 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 665 <tbody>
Kovalev_D 23:12e6183f04d4 666 <tr>
Kovalev_D 23:12e6183f04d4 667 <th class="kt">Function Definition</th>
Kovalev_D 23:12e6183f04d4 668 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 669 </tr>
Kovalev_D 23:12e6183f04d4 670 <tr>
Kovalev_D 23:12e6183f04d4 671 <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
Kovalev_D 23:12e6183f04d4 672 <td class="kt">Setup the microcontroller system. Typically this function configures the
Kovalev_D 23:12e6183f04d4 673 oscillator (PLL) that is part of the microcontroller device. For systems
Kovalev_D 23:12e6183f04d4 674 with variable clock speed it also updates the variable SystemCoreClock.<br>
Kovalev_D 23:12e6183f04d4 675 SystemInit is called from startup<i>_device</i> file.</td>
Kovalev_D 23:12e6183f04d4 676 </tr>
Kovalev_D 23:12e6183f04d4 677 <tr>
Kovalev_D 23:12e6183f04d4 678 <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>
Kovalev_D 23:12e6183f04d4 679 <td class="kt">Updates the variable SystemCoreClock and must be called whenever the
Kovalev_D 23:12e6183f04d4 680 core clock is changed during program execution. SystemCoreClockUpdate()
Kovalev_D 23:12e6183f04d4 681 evaluates the clock register settings and calculates the current core clock.
Kovalev_D 23:12e6183f04d4 682 </td>
Kovalev_D 23:12e6183f04d4 683 </tr>
Kovalev_D 23:12e6183f04d4 684 </tbody>
Kovalev_D 23:12e6183f04d4 685 </table>
Kovalev_D 23:12e6183f04d4 686
Kovalev_D 23:12e6183f04d4 687 <p>
Kovalev_D 23:12e6183f04d4 688 Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong>
Kovalev_D 23:12e6183f04d4 689 is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.
Kovalev_D 23:12e6183f04d4 690 </p>
Kovalev_D 23:12e6183f04d4 691
Kovalev_D 23:12e6183f04d4 692 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 693 <tbody>
Kovalev_D 23:12e6183f04d4 694 <tr>
Kovalev_D 23:12e6183f04d4 695 <th class="kt">Variable Definition</th>
Kovalev_D 23:12e6183f04d4 696 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 697 </tr>
Kovalev_D 23:12e6183f04d4 698 <tr>
Kovalev_D 23:12e6183f04d4 699 <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>
Kovalev_D 23:12e6183f04d4 700 <td class="kt">Contains the system core clock (which is the system clock frequency supplied
Kovalev_D 23:12e6183f04d4 701 to the SysTick timer and the processor core clock). This variable can be
Kovalev_D 23:12e6183f04d4 702 used by the user application to setup the SysTick timer or configure other
Kovalev_D 23:12e6183f04d4 703 parameters. It may also be used by debugger to query the frequency of the
Kovalev_D 23:12e6183f04d4 704 debug timer or configure the trace clock speed.<br>
Kovalev_D 23:12e6183f04d4 705 SystemCoreClock is initialized with a correct predefined value.<br><br>
Kovalev_D 23:12e6183f04d4 706 The compiler must be configured to avoid the removal of this variable in
Kovalev_D 23:12e6183f04d4 707 case that the application program is not using it. It is important for
Kovalev_D 23:12e6183f04d4 708 debug systems that the variable is physically present in memory so that
Kovalev_D 23:12e6183f04d4 709 it can be examined to configure the debugger.</td>
Kovalev_D 23:12e6183f04d4 710 </tr>
Kovalev_D 23:12e6183f04d4 711 </tbody>
Kovalev_D 23:12e6183f04d4 712 </table>
Kovalev_D 23:12e6183f04d4 713
Kovalev_D 23:12e6183f04d4 714 <p class="Note">Note</p>
Kovalev_D 23:12e6183f04d4 715 <ul>
Kovalev_D 23:12e6183f04d4 716 <li><p>The above definitions are the minimum requirements for the file <strong>
Kovalev_D 23:12e6183f04d4 717 system_</strong><em><strong>device</strong></em><strong>.c</strong>. This
Kovalev_D 23:12e6183f04d4 718 file may export more functions or variables that provide a more flexible
Kovalev_D 23:12e6183f04d4 719 configuration of the microcontroller system.</p>
Kovalev_D 23:12e6183f04d4 720 </li>
Kovalev_D 23:12e6183f04d4 721 </ul>
Kovalev_D 23:12e6183f04d4 722
Kovalev_D 23:12e6183f04d4 723
Kovalev_D 23:12e6183f04d4 724 <h2>Core Peripheral Access Layer</h2>
Kovalev_D 23:12e6183f04d4 725
Kovalev_D 23:12e6183f04d4 726 <h3>Cortex-M Core Register Access</h3>
Kovalev_D 23:12e6183f04d4 727 <p>
Kovalev_D 23:12e6183f04d4 728 The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
Kovalev_D 23:12e6183f04d4 729 and provide access to Cortex-M core registers.
Kovalev_D 23:12e6183f04d4 730 </p>
Kovalev_D 23:12e6183f04d4 731
Kovalev_D 23:12e6183f04d4 732 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 733 <tbody>
Kovalev_D 23:12e6183f04d4 734 <tr>
Kovalev_D 23:12e6183f04d4 735 <th class="kt">Function Definition</th>
Kovalev_D 23:12e6183f04d4 736 <th class="kt">Core</th>
Kovalev_D 23:12e6183f04d4 737 <th class="kt">Core Register</th>
Kovalev_D 23:12e6183f04d4 738 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 739 </tr>
Kovalev_D 23:12e6183f04d4 740 <tr>
Kovalev_D 23:12e6183f04d4 741 <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
Kovalev_D 23:12e6183f04d4 742 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 743 <td class="kt">PRIMASK = 0</td>
Kovalev_D 23:12e6183f04d4 744 <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE
Kovalev_D 23:12e6183f04d4 745 i</strong>)</td>
Kovalev_D 23:12e6183f04d4 746 </tr>
Kovalev_D 23:12e6183f04d4 747 <tr>
Kovalev_D 23:12e6183f04d4 748 <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
Kovalev_D 23:12e6183f04d4 749 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 750 <td class="kt">PRIMASK = 1</td>
Kovalev_D 23:12e6183f04d4 751 <td class="kt">Global Interrupt disable (using the instruction <strong>
Kovalev_D 23:12e6183f04d4 752 CPSID i</strong>)</td>
Kovalev_D 23:12e6183f04d4 753 </tr>
Kovalev_D 23:12e6183f04d4 754 <tr>
Kovalev_D 23:12e6183f04d4 755 <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
Kovalev_D 23:12e6183f04d4 756 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 757 <td class="kt">PRIMASK = value</td>
Kovalev_D 23:12e6183f04d4 758 <td class="kt">Assign value to Priority Mask Register (using the instruction
Kovalev_D 23:12e6183f04d4 759 <strong>MSR</strong>)</td>
Kovalev_D 23:12e6183f04d4 760 </tr>
Kovalev_D 23:12e6183f04d4 761 <tr>
Kovalev_D 23:12e6183f04d4 762 <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
Kovalev_D 23:12e6183f04d4 763 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 764 <td class="kt">return PRIMASK</td>
Kovalev_D 23:12e6183f04d4 765 <td class="kt">Return Priority Mask Register (using the instruction
Kovalev_D 23:12e6183f04d4 766 <strong>MRS</strong>)</td>
Kovalev_D 23:12e6183f04d4 767 </tr>
Kovalev_D 23:12e6183f04d4 768 <tr>
Kovalev_D 23:12e6183f04d4 769 <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
Kovalev_D 23:12e6183f04d4 770 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 771 <td class="kt">FAULTMASK = 0</td>
Kovalev_D 23:12e6183f04d4 772 <td class="kt">Global Fault exception and Interrupt enable (using the
Kovalev_D 23:12e6183f04d4 773 instruction <strong>CPSIE
Kovalev_D 23:12e6183f04d4 774 f</strong>)</td>
Kovalev_D 23:12e6183f04d4 775 </tr>
Kovalev_D 23:12e6183f04d4 776 <tr>
Kovalev_D 23:12e6183f04d4 777 <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
Kovalev_D 23:12e6183f04d4 778 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 779 <td class="kt">FAULTMASK = 1</td>
Kovalev_D 23:12e6183f04d4 780 <td class="kt">Global Fault exception and Interrupt disable (using the
Kovalev_D 23:12e6183f04d4 781 instruction <strong>CPSID f</strong>)</td>
Kovalev_D 23:12e6183f04d4 782 </tr>
Kovalev_D 23:12e6183f04d4 783 <tr>
Kovalev_D 23:12e6183f04d4 784 <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
Kovalev_D 23:12e6183f04d4 785 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 786 <td class="kt">FAULTMASK = value</td>
Kovalev_D 23:12e6183f04d4 787 <td class="kt">Assign value to Fault Mask Register (using the instruction
Kovalev_D 23:12e6183f04d4 788 <strong>MSR</strong>)</td>
Kovalev_D 23:12e6183f04d4 789 </tr>
Kovalev_D 23:12e6183f04d4 790 <tr>
Kovalev_D 23:12e6183f04d4 791 <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
Kovalev_D 23:12e6183f04d4 792 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 793 <td class="kt">return FAULTMASK</td>
Kovalev_D 23:12e6183f04d4 794 <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
Kovalev_D 23:12e6183f04d4 795 </tr>
Kovalev_D 23:12e6183f04d4 796 <tr>
Kovalev_D 23:12e6183f04d4 797 <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
Kovalev_D 23:12e6183f04d4 798 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 799 <td class="kt">BASEPRI = value</td>
Kovalev_D 23:12e6183f04d4 800 <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
Kovalev_D 23:12e6183f04d4 801 </tr>
Kovalev_D 23:12e6183f04d4 802 <tr>
Kovalev_D 23:12e6183f04d4 803 <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
Kovalev_D 23:12e6183f04d4 804 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 805 <td class="kt">return BASEPRI</td>
Kovalev_D 23:12e6183f04d4 806 <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
Kovalev_D 23:12e6183f04d4 807 </tr>
Kovalev_D 23:12e6183f04d4 808 <tr>
Kovalev_D 23:12e6183f04d4 809 <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
Kovalev_D 23:12e6183f04d4 810 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 811 <td class="kt">CONTROL = value</td>
Kovalev_D 23:12e6183f04d4 812 <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
Kovalev_D 23:12e6183f04d4 813 </tr>
Kovalev_D 23:12e6183f04d4 814 <tr>
Kovalev_D 23:12e6183f04d4 815 <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
Kovalev_D 23:12e6183f04d4 816 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 817 <td class="kt">return CONTROL</td>
Kovalev_D 23:12e6183f04d4 818 <td class="kt">Return Control Register Value (using the instruction
Kovalev_D 23:12e6183f04d4 819 <strong>MRS</strong>)</td>
Kovalev_D 23:12e6183f04d4 820 </tr>
Kovalev_D 23:12e6183f04d4 821 <tr>
Kovalev_D 23:12e6183f04d4 822 <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
Kovalev_D 23:12e6183f04d4 823 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 824 <td class="kt">PSP = TopOfProcStack</td>
Kovalev_D 23:12e6183f04d4 825 <td class="kt">Set Process Stack Pointer value (using the instruction
Kovalev_D 23:12e6183f04d4 826 <strong>MSR</strong>)</td>
Kovalev_D 23:12e6183f04d4 827 </tr>
Kovalev_D 23:12e6183f04d4 828 <tr>
Kovalev_D 23:12e6183f04d4 829 <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
Kovalev_D 23:12e6183f04d4 830 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 831 <td class="kt">return PSP</td>
Kovalev_D 23:12e6183f04d4 832 <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
Kovalev_D 23:12e6183f04d4 833 </tr>
Kovalev_D 23:12e6183f04d4 834 <tr>
Kovalev_D 23:12e6183f04d4 835 <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
Kovalev_D 23:12e6183f04d4 836 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 837 <td class="kt">MSP = TopOfMainStack</td>
Kovalev_D 23:12e6183f04d4 838 <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
Kovalev_D 23:12e6183f04d4 839 </tr>
Kovalev_D 23:12e6183f04d4 840 <tr>
Kovalev_D 23:12e6183f04d4 841 <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
Kovalev_D 23:12e6183f04d4 842 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 843 <td class="kt">return MSP</td>
Kovalev_D 23:12e6183f04d4 844 <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
Kovalev_D 23:12e6183f04d4 845 </tr>
Kovalev_D 23:12e6183f04d4 846 </tbody>
Kovalev_D 23:12e6183f04d4 847 </table>
Kovalev_D 23:12e6183f04d4 848
Kovalev_D 23:12e6183f04d4 849 <h3>Cortex-M Instruction Access</h3>
Kovalev_D 23:12e6183f04d4 850 <p>
Kovalev_D 23:12e6183f04d4 851 The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
Kovalev_D 23:12e6183f04d4 852 generate specific Cortex-M instructions. The functions are implemented in the file
Kovalev_D 23:12e6183f04d4 853 <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
Kovalev_D 23:12e6183f04d4 854 </p>
Kovalev_D 23:12e6183f04d4 855
Kovalev_D 23:12e6183f04d4 856 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 857 <tbody>
Kovalev_D 23:12e6183f04d4 858 <tr>
Kovalev_D 23:12e6183f04d4 859 <th class="kt">Name</th>
Kovalev_D 23:12e6183f04d4 860 <th class="kt">Core</th>
Kovalev_D 23:12e6183f04d4 861 <th class="kt">Generated CPU Instruction</th>
Kovalev_D 23:12e6183f04d4 862 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 863 </tr>
Kovalev_D 23:12e6183f04d4 864 <tr>
Kovalev_D 23:12e6183f04d4 865 <td class="kt" nowrap="nowrap">void __NOP (void)</td>
Kovalev_D 23:12e6183f04d4 866 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 867 <td class="kt">NOP</td>
Kovalev_D 23:12e6183f04d4 868 <td class="kt">No Operation</td>
Kovalev_D 23:12e6183f04d4 869 </tr>
Kovalev_D 23:12e6183f04d4 870 <tr>
Kovalev_D 23:12e6183f04d4 871 <td class="kt" nowrap="nowrap">void __WFI (void)</td>
Kovalev_D 23:12e6183f04d4 872 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 873 <td class="kt">WFI</td>
Kovalev_D 23:12e6183f04d4 874 <td class="kt">Wait for Interrupt</td>
Kovalev_D 23:12e6183f04d4 875 </tr>
Kovalev_D 23:12e6183f04d4 876 <tr>
Kovalev_D 23:12e6183f04d4 877 <td class="kt" nowrap="nowrap">void __WFE (void)</td>
Kovalev_D 23:12e6183f04d4 878 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 879 <td class="kt">WFE</td>
Kovalev_D 23:12e6183f04d4 880 <td class="kt">Wait for Event</td>
Kovalev_D 23:12e6183f04d4 881 </tr>
Kovalev_D 23:12e6183f04d4 882 <tr>
Kovalev_D 23:12e6183f04d4 883 <td class="kt" nowrap="nowrap">void __SEV (void)</td>
Kovalev_D 23:12e6183f04d4 884 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 885 <td class="kt">SEV</td>
Kovalev_D 23:12e6183f04d4 886 <td class="kt">Set Event</td>
Kovalev_D 23:12e6183f04d4 887 </tr>
Kovalev_D 23:12e6183f04d4 888 <tr>
Kovalev_D 23:12e6183f04d4 889 <td class="kt" nowrap="nowrap">void __ISB (void)</td>
Kovalev_D 23:12e6183f04d4 890 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 891 <td class="kt">ISB</td>
Kovalev_D 23:12e6183f04d4 892 <td class="kt">Instruction Synchronization Barrier</td>
Kovalev_D 23:12e6183f04d4 893 </tr>
Kovalev_D 23:12e6183f04d4 894 <tr>
Kovalev_D 23:12e6183f04d4 895 <td class="kt" nowrap="nowrap">void __DSB (void)</td>
Kovalev_D 23:12e6183f04d4 896 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 897 <td class="kt">DSB</td>
Kovalev_D 23:12e6183f04d4 898 <td class="kt">Data Synchronization Barrier</td>
Kovalev_D 23:12e6183f04d4 899 </tr>
Kovalev_D 23:12e6183f04d4 900 <tr>
Kovalev_D 23:12e6183f04d4 901 <td class="kt" nowrap="nowrap">void __DMB (void)</td>
Kovalev_D 23:12e6183f04d4 902 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 903 <td class="kt">DMB</td>
Kovalev_D 23:12e6183f04d4 904 <td class="kt">Data Memory Barrier</td>
Kovalev_D 23:12e6183f04d4 905 </tr>
Kovalev_D 23:12e6183f04d4 906 <tr>
Kovalev_D 23:12e6183f04d4 907 <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
Kovalev_D 23:12e6183f04d4 908 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 909 <td class="kt">REV</td>
Kovalev_D 23:12e6183f04d4 910 <td class="kt">Reverse byte order in integer value.</td>
Kovalev_D 23:12e6183f04d4 911 </tr>
Kovalev_D 23:12e6183f04d4 912 <tr>
Kovalev_D 23:12e6183f04d4 913 <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
Kovalev_D 23:12e6183f04d4 914 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 915 <td class="kt">REV16</td>
Kovalev_D 23:12e6183f04d4 916 <td class="kt">Reverse byte order in unsigned short value. </td>
Kovalev_D 23:12e6183f04d4 917 </tr>
Kovalev_D 23:12e6183f04d4 918 <tr>
Kovalev_D 23:12e6183f04d4 919 <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
Kovalev_D 23:12e6183f04d4 920 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 921 <td class="kt">REVSH</td>
Kovalev_D 23:12e6183f04d4 922 <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
Kovalev_D 23:12e6183f04d4 923 </tr>
Kovalev_D 23:12e6183f04d4 924 <tr>
Kovalev_D 23:12e6183f04d4 925 <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
Kovalev_D 23:12e6183f04d4 926 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 927 <td class="kt">RBIT</td>
Kovalev_D 23:12e6183f04d4 928 <td class="kt">Reverse bit order of value</td>
Kovalev_D 23:12e6183f04d4 929 </tr>
Kovalev_D 23:12e6183f04d4 930 <tr>
Kovalev_D 23:12e6183f04d4 931 <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
Kovalev_D 23:12e6183f04d4 932 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 933 <td class="kt">LDREXB</td>
Kovalev_D 23:12e6183f04d4 934 <td class="kt">Load exclusive byte</td>
Kovalev_D 23:12e6183f04d4 935 </tr>
Kovalev_D 23:12e6183f04d4 936 <tr>
Kovalev_D 23:12e6183f04d4 937 <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
Kovalev_D 23:12e6183f04d4 938 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 939 <td class="kt">LDREXH</td>
Kovalev_D 23:12e6183f04d4 940 <td class="kt">Load exclusive half-word</td>
Kovalev_D 23:12e6183f04d4 941 </tr>
Kovalev_D 23:12e6183f04d4 942 <tr>
Kovalev_D 23:12e6183f04d4 943 <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
Kovalev_D 23:12e6183f04d4 944 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 945 <td class="kt">LDREXW</td>
Kovalev_D 23:12e6183f04d4 946 <td class="kt">Load exclusive word</td>
Kovalev_D 23:12e6183f04d4 947 </tr>
Kovalev_D 23:12e6183f04d4 948 <tr>
Kovalev_D 23:12e6183f04d4 949 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
Kovalev_D 23:12e6183f04d4 950 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 951 <td class="kt">STREXB</td>
Kovalev_D 23:12e6183f04d4 952 <td class="kt">Store exclusive byte</td>
Kovalev_D 23:12e6183f04d4 953 </tr>
Kovalev_D 23:12e6183f04d4 954 <tr>
Kovalev_D 23:12e6183f04d4 955 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
Kovalev_D 23:12e6183f04d4 956 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 957 <td class="kt">STREXH</td>
Kovalev_D 23:12e6183f04d4 958 <td class="kt">Store exclusive half-word</td>
Kovalev_D 23:12e6183f04d4 959 </tr>
Kovalev_D 23:12e6183f04d4 960 <tr>
Kovalev_D 23:12e6183f04d4 961 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
Kovalev_D 23:12e6183f04d4 962 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 963 <td class="kt">STREXW</td>
Kovalev_D 23:12e6183f04d4 964 <td class="kt">Store exclusive word</td>
Kovalev_D 23:12e6183f04d4 965 </tr>
Kovalev_D 23:12e6183f04d4 966 <tr>
Kovalev_D 23:12e6183f04d4 967 <td class="kt" nowrap="nowrap">void __CLREX (void)</td>
Kovalev_D 23:12e6183f04d4 968 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 969 <td class="kt">CLREX</td>
Kovalev_D 23:12e6183f04d4 970 <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
Kovalev_D 23:12e6183f04d4 971 </tr>
Kovalev_D 23:12e6183f04d4 972 </tbody>
Kovalev_D 23:12e6183f04d4 973 </table>
Kovalev_D 23:12e6183f04d4 974
Kovalev_D 23:12e6183f04d4 975
Kovalev_D 23:12e6183f04d4 976 <h3>NVIC Access Functions</h3>
Kovalev_D 23:12e6183f04d4 977 <p>
Kovalev_D 23:12e6183f04d4 978 The CMSIS provides access to the NVIC via the register interface structure and several helper
Kovalev_D 23:12e6183f04d4 979 functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
Kovalev_D 23:12e6183f04d4 980 identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
Kovalev_D 23:12e6183f04d4 981 IRQn values are used for processor core exceptions.
Kovalev_D 23:12e6183f04d4 982 </p>
Kovalev_D 23:12e6183f04d4 983 <p>
Kovalev_D 23:12e6183f04d4 984 For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides
Kovalev_D 23:12e6183f04d4 985 the following enum names.
Kovalev_D 23:12e6183f04d4 986 </p>
Kovalev_D 23:12e6183f04d4 987
Kovalev_D 23:12e6183f04d4 988 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 989 <tbody>
Kovalev_D 23:12e6183f04d4 990 <tr>
Kovalev_D 23:12e6183f04d4 991 <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
Kovalev_D 23:12e6183f04d4 992 <th class="kt">Core</th>
Kovalev_D 23:12e6183f04d4 993 <th class="kt">IRQn</th>
Kovalev_D 23:12e6183f04d4 994 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 995 </tr>
Kovalev_D 23:12e6183f04d4 996 <tr>
Kovalev_D 23:12e6183f04d4 997 <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
Kovalev_D 23:12e6183f04d4 998 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 999 <td class="kt">-14</td>
Kovalev_D 23:12e6183f04d4 1000 <td class="kt">Cortex-M Non Maskable Interrupt</td>
Kovalev_D 23:12e6183f04d4 1001 </tr>
Kovalev_D 23:12e6183f04d4 1002 <tr>
Kovalev_D 23:12e6183f04d4 1003 <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
Kovalev_D 23:12e6183f04d4 1004 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1005 <td class="kt">-13</td>
Kovalev_D 23:12e6183f04d4 1006 <td class="kt">Cortex-M Hard Fault Interrupt</td>
Kovalev_D 23:12e6183f04d4 1007 </tr>
Kovalev_D 23:12e6183f04d4 1008 <tr>
Kovalev_D 23:12e6183f04d4 1009 <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
Kovalev_D 23:12e6183f04d4 1010 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1011 <td class="kt">-12</td>
Kovalev_D 23:12e6183f04d4 1012 <td class="kt">Cortex-M Memory Management Interrupt</td>
Kovalev_D 23:12e6183f04d4 1013 </tr>
Kovalev_D 23:12e6183f04d4 1014 <tr>
Kovalev_D 23:12e6183f04d4 1015 <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
Kovalev_D 23:12e6183f04d4 1016 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1017 <td class="kt">-11</td>
Kovalev_D 23:12e6183f04d4 1018 <td class="kt">Cortex-M Bus Fault Interrupt</td>
Kovalev_D 23:12e6183f04d4 1019 </tr>
Kovalev_D 23:12e6183f04d4 1020 <tr>
Kovalev_D 23:12e6183f04d4 1021 <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
Kovalev_D 23:12e6183f04d4 1022 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1023 <td class="kt">-10</td>
Kovalev_D 23:12e6183f04d4 1024 <td class="kt">Cortex-M Usage Fault Interrupt</td>
Kovalev_D 23:12e6183f04d4 1025 </tr>
Kovalev_D 23:12e6183f04d4 1026 <tr>
Kovalev_D 23:12e6183f04d4 1027 <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
Kovalev_D 23:12e6183f04d4 1028 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1029 <td class="kt">-5</td>
Kovalev_D 23:12e6183f04d4 1030 <td class="kt">Cortex-M SV Call Interrupt </td>
Kovalev_D 23:12e6183f04d4 1031 </tr>
Kovalev_D 23:12e6183f04d4 1032 <tr>
Kovalev_D 23:12e6183f04d4 1033 <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
Kovalev_D 23:12e6183f04d4 1034 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1035 <td class="kt">-4</td>
Kovalev_D 23:12e6183f04d4 1036 <td class="kt">Cortex-M Debug Monitor Interrupt</td>
Kovalev_D 23:12e6183f04d4 1037 </tr>
Kovalev_D 23:12e6183f04d4 1038 <tr>
Kovalev_D 23:12e6183f04d4 1039 <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
Kovalev_D 23:12e6183f04d4 1040 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1041 <td class="kt">-2</td>
Kovalev_D 23:12e6183f04d4 1042 <td class="kt">Cortex-M Pend SV Interrupt</td>
Kovalev_D 23:12e6183f04d4 1043 </tr>
Kovalev_D 23:12e6183f04d4 1044 <tr>
Kovalev_D 23:12e6183f04d4 1045 <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
Kovalev_D 23:12e6183f04d4 1046 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1047 <td class="kt">-1</td>
Kovalev_D 23:12e6183f04d4 1048 <td class="kt">Cortex-M System Tick Interrupt</td>
Kovalev_D 23:12e6183f04d4 1049 </tr>
Kovalev_D 23:12e6183f04d4 1050 </tbody>
Kovalev_D 23:12e6183f04d4 1051 </table>
Kovalev_D 23:12e6183f04d4 1052
Kovalev_D 23:12e6183f04d4 1053 <p>The following functions simplify the setup of the NVIC.
Kovalev_D 23:12e6183f04d4 1054 The functions are defined as <strong>static inline</strong>.</p>
Kovalev_D 23:12e6183f04d4 1055
Kovalev_D 23:12e6183f04d4 1056 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 1057 <tbody>
Kovalev_D 23:12e6183f04d4 1058 <tr>
Kovalev_D 23:12e6183f04d4 1059 <th class="kt" nowrap="nowrap">Name</th>
Kovalev_D 23:12e6183f04d4 1060 <th class="kt">Core</th>
Kovalev_D 23:12e6183f04d4 1061 <th class="kt">Parameter</th>
Kovalev_D 23:12e6183f04d4 1062 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 1063 </tr>
Kovalev_D 23:12e6183f04d4 1064 <tr>
Kovalev_D 23:12e6183f04d4 1065 <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
Kovalev_D 23:12e6183f04d4 1066 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1067 <td class="kt">Priority Grouping Value</td>
Kovalev_D 23:12e6183f04d4 1068 <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
Kovalev_D 23:12e6183f04d4 1069 </tr>
Kovalev_D 23:12e6183f04d4 1070 <tr>
Kovalev_D 23:12e6183f04d4 1071 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>
Kovalev_D 23:12e6183f04d4 1072 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1073 <td class="kt">(void)</td>
Kovalev_D 23:12e6183f04d4 1074 <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>
Kovalev_D 23:12e6183f04d4 1075 </tr>
Kovalev_D 23:12e6183f04d4 1076 <tr>
Kovalev_D 23:12e6183f04d4 1077 <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
Kovalev_D 23:12e6183f04d4 1078 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1079 <td class="kt">IRQ Number</td>
Kovalev_D 23:12e6183f04d4 1080 <td class="kt">Enable IRQn</td>
Kovalev_D 23:12e6183f04d4 1081 </tr>
Kovalev_D 23:12e6183f04d4 1082 <tr>
Kovalev_D 23:12e6183f04d4 1083 <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
Kovalev_D 23:12e6183f04d4 1084 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1085 <td class="kt">IRQ Number</td>
Kovalev_D 23:12e6183f04d4 1086 <td class="kt">Disable IRQn</td>
Kovalev_D 23:12e6183f04d4 1087 </tr>
Kovalev_D 23:12e6183f04d4 1088 <tr>
Kovalev_D 23:12e6183f04d4 1089 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
Kovalev_D 23:12e6183f04d4 1090 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1091 <td class="kt">IRQ Number</td>
Kovalev_D 23:12e6183f04d4 1092 <td class="kt">Return 1 if IRQn is pending else 0</td>
Kovalev_D 23:12e6183f04d4 1093 </tr>
Kovalev_D 23:12e6183f04d4 1094 <tr>
Kovalev_D 23:12e6183f04d4 1095 <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
Kovalev_D 23:12e6183f04d4 1096 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1097 <td class="kt">IRQ Number</td>
Kovalev_D 23:12e6183f04d4 1098 <td class="kt">Set IRQn Pending</td>
Kovalev_D 23:12e6183f04d4 1099 </tr>
Kovalev_D 23:12e6183f04d4 1100 <tr>
Kovalev_D 23:12e6183f04d4 1101 <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
Kovalev_D 23:12e6183f04d4 1102 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1103 <td class="kt">IRQ Number</td>
Kovalev_D 23:12e6183f04d4 1104 <td class="kt">Clear IRQn Pending Status</td>
Kovalev_D 23:12e6183f04d4 1105 </tr>
Kovalev_D 23:12e6183f04d4 1106 <tr>
Kovalev_D 23:12e6183f04d4 1107 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
Kovalev_D 23:12e6183f04d4 1108 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1109 <td class="kt">IRQ Number</td>
Kovalev_D 23:12e6183f04d4 1110 <td class="kt">Return 1 if IRQn is active else 0</td>
Kovalev_D 23:12e6183f04d4 1111 </tr>
Kovalev_D 23:12e6183f04d4 1112 <tr>
Kovalev_D 23:12e6183f04d4 1113 <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
Kovalev_D 23:12e6183f04d4 1114 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1115 <td class="kt">IRQ Number, Priority</td>
Kovalev_D 23:12e6183f04d4 1116 <td class="kt">Set Priority for IRQn<br>
Kovalev_D 23:12e6183f04d4 1117 (not threadsafe for Cortex-M0)</td>
Kovalev_D 23:12e6183f04d4 1118 </tr>
Kovalev_D 23:12e6183f04d4 1119 <tr>
Kovalev_D 23:12e6183f04d4 1120 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
Kovalev_D 23:12e6183f04d4 1121 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1122 <td class="kt">IRQ Number</td>
Kovalev_D 23:12e6183f04d4 1123 <td class="kt">Get Priority for IRQn</td>
Kovalev_D 23:12e6183f04d4 1124 </tr>
Kovalev_D 23:12e6183f04d4 1125 <tr>
Kovalev_D 23:12e6183f04d4 1126 <!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
Kovalev_D 23:12e6183f04d4 1127 <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td>
Kovalev_D 23:12e6183f04d4 1128 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1129 <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td>
Kovalev_D 23:12e6183f04d4 1130 <td class="kt">Encode priority for given group, preemptive and sub priority</td>
Kovalev_D 23:12e6183f04d4 1131 </tr>
Kovalev_D 23:12e6183f04d4 1132 <!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
Kovalev_D 23:12e6183f04d4 1133 <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td>
Kovalev_D 23:12e6183f04d4 1134 <td class="kt">M3</td>
Kovalev_D 23:12e6183f04d4 1135 <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td>
Kovalev_D 23:12e6183f04d4 1136 <td class="kt">Deccode given priority to group, preemptive and sub priority</td>
Kovalev_D 23:12e6183f04d4 1137 </tr>
Kovalev_D 23:12e6183f04d4 1138 <tr>
Kovalev_D 23:12e6183f04d4 1139 <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
Kovalev_D 23:12e6183f04d4 1140 <td class="kt">M0, M3</td>
Kovalev_D 23:12e6183f04d4 1141 <td class="kt">(void)</td>
Kovalev_D 23:12e6183f04d4 1142 <td class="kt">Resets the System</td>
Kovalev_D 23:12e6183f04d4 1143 </tr>
Kovalev_D 23:12e6183f04d4 1144 </tbody>
Kovalev_D 23:12e6183f04d4 1145 </table>
Kovalev_D 23:12e6183f04d4 1146 <p class="Note">Note</p>
Kovalev_D 23:12e6183f04d4 1147 <ul>
Kovalev_D 23:12e6183f04d4 1148 <li><p>The processor exceptions have negative enum values. Device specific interrupts
Kovalev_D 23:12e6183f04d4 1149 have positive enum values and start with 0. The values are defined in
Kovalev_D 23:12e6183f04d4 1150 <b><em>device.h</em></b> file.
Kovalev_D 23:12e6183f04d4 1151 </p>
Kovalev_D 23:12e6183f04d4 1152 </li>
Kovalev_D 23:12e6183f04d4 1153 <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
Kovalev_D 23:12e6183f04d4 1154 used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
Kovalev_D 23:12e6183f04d4 1155 depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
Kovalev_D 23:12e6183f04d4 1156 </p>
Kovalev_D 23:12e6183f04d4 1157 </li>
Kovalev_D 23:12e6183f04d4 1158 </ul>
Kovalev_D 23:12e6183f04d4 1159
Kovalev_D 23:12e6183f04d4 1160
Kovalev_D 23:12e6183f04d4 1161 <h3>SysTick Configuration Function</h3>
Kovalev_D 23:12e6183f04d4 1162
Kovalev_D 23:12e6183f04d4 1163 <p>The following function is used to configure the SysTick timer and start the
Kovalev_D 23:12e6183f04d4 1164 SysTick interrupt.</p>
Kovalev_D 23:12e6183f04d4 1165
Kovalev_D 23:12e6183f04d4 1166 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 1167 <tbody>
Kovalev_D 23:12e6183f04d4 1168 <tr>
Kovalev_D 23:12e6183f04d4 1169 <th class="kt" nowrap="nowrap">Name</th>
Kovalev_D 23:12e6183f04d4 1170 <th class="kt">Parameter</th>
Kovalev_D 23:12e6183f04d4 1171 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 1172 </tr>
Kovalev_D 23:12e6183f04d4 1173 <tr>
Kovalev_D 23:12e6183f04d4 1174 <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig
Kovalev_D 23:12e6183f04d4 1175 (uint32_t ticks)</span></td>
Kovalev_D 23:12e6183f04d4 1176 <td class="kt">ticks is SysTick counter reload value</td>
Kovalev_D 23:12e6183f04d4 1177 <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this
Kovalev_D 23:12e6183f04d4 1178 call the SysTick timer creates interrupts with the specified time
Kovalev_D 23:12e6183f04d4 1179 interval. <br>
Kovalev_D 23:12e6183f04d4 1180 <br>
Kovalev_D 23:12e6183f04d4 1181 Return: 0 when successful, 1 on failure.<br>
Kovalev_D 23:12e6183f04d4 1182 </td>
Kovalev_D 23:12e6183f04d4 1183 </tr>
Kovalev_D 23:12e6183f04d4 1184 </tbody>
Kovalev_D 23:12e6183f04d4 1185 </table>
Kovalev_D 23:12e6183f04d4 1186
Kovalev_D 23:12e6183f04d4 1187
Kovalev_D 23:12e6183f04d4 1188 <h3>Cortex-M3 ITM Debug Access</h3>
Kovalev_D 23:12e6183f04d4 1189
Kovalev_D 23:12e6183f04d4 1190 <p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
Kovalev_D 23:12e6183f04d4 1191 provides together with the Serial Viewer Output trace capabilities for the
Kovalev_D 23:12e6183f04d4 1192 microcontroller system. The ITM has 32 communication channels; two ITM
Kovalev_D 23:12e6183f04d4 1193 communication channels are used by CMSIS to output the following information:</p>
Kovalev_D 23:12e6183f04d4 1194 <ul>
Kovalev_D 23:12e6183f04d4 1195 <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function
Kovalev_D 23:12e6183f04d4 1196 which can be used for printf-style output via the debug interface.</li>
Kovalev_D 23:12e6183f04d4 1197 <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for
Kovalev_D 23:12e6183f04d4 1198 kernel awareness debugging.</li>
Kovalev_D 23:12e6183f04d4 1199 </ul>
Kovalev_D 23:12e6183f04d4 1200 <p class="Note">Note</p>
Kovalev_D 23:12e6183f04d4 1201 <ul>
Kovalev_D 23:12e6183f04d4 1202 <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels
Kovalev_D 23:12e6183f04d4 1203 may use the Privileged level for program execution. ITM
Kovalev_D 23:12e6183f04d4 1204 channels have 4 groups with 8 channels each, whereby each group can be
Kovalev_D 23:12e6183f04d4 1205 configured for access rights in the Unprivileged level. The ITM channel 0
Kovalev_D 23:12e6183f04d4 1206 may be therefore enabled for the user task whereas ITM channel 31 may be
Kovalev_D 23:12e6183f04d4 1207 accessible only in Privileged level from the RTOS kernel itself.</p>
Kovalev_D 23:12e6183f04d4 1208 </li>
Kovalev_D 23:12e6183f04d4 1209 </ul>
Kovalev_D 23:12e6183f04d4 1210
Kovalev_D 23:12e6183f04d4 1211 <p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the
Kovalev_D 23:12e6183f04d4 1212 table below.</p>
Kovalev_D 23:12e6183f04d4 1213
Kovalev_D 23:12e6183f04d4 1214 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 1215 <tbody>
Kovalev_D 23:12e6183f04d4 1216 <tr>
Kovalev_D 23:12e6183f04d4 1217 <th class="kt" nowrap="nowrap">Name</th>
Kovalev_D 23:12e6183f04d4 1218 <th class="kt">Parameter</th>
Kovalev_D 23:12e6183f04d4 1219 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 1220 </tr>
Kovalev_D 23:12e6183f04d4 1221 <tr>
Kovalev_D 23:12e6183f04d4 1222 <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>
Kovalev_D 23:12e6183f04d4 1223 <td class="kt">character to output</td>
Kovalev_D 23:12e6183f04d4 1224 <td class="kt">The function outputs a character via the ITM channel 0. The
Kovalev_D 23:12e6183f04d4 1225 function returns when no debugger is connected that has booked the
Kovalev_D 23:12e6183f04d4 1226 output. It is blocking when a debugger is connected, but the
Kovalev_D 23:12e6183f04d4 1227 previous character send is not transmitted. <br><br>
Kovalev_D 23:12e6183f04d4 1228 Return: the input character 'chr'.</td>
Kovalev_D 23:12e6183f04d4 1229 </tr>
Kovalev_D 23:12e6183f04d4 1230 </tbody>
Kovalev_D 23:12e6183f04d4 1231 </table>
Kovalev_D 23:12e6183f04d4 1232
Kovalev_D 23:12e6183f04d4 1233 <p>
Kovalev_D 23:12e6183f04d4 1234 Example for the usage of the ITM Channel 31 for RTOS Kernels:
Kovalev_D 23:12e6183f04d4 1235 </p>
Kovalev_D 23:12e6183f04d4 1236 <pre>
Kovalev_D 23:12e6183f04d4 1237 // check if debugger connected and ITM channel enabled for tracing
Kovalev_D 23:12e6183f04d4 1238 if ((CoreDebug-&gt;DEMCR &amp; CoreDebug_DEMCR_TRCENA) &amp;&amp;
Kovalev_D 23:12e6183f04d4 1239 (ITM-&gt;TCR &amp; ITM_TCR_ITMENA) &amp;&amp;
Kovalev_D 23:12e6183f04d4 1240 (ITM-&gt;TER &amp; (1UL &lt;&lt; 31))) {
Kovalev_D 23:12e6183f04d4 1241 // transmit trace data
Kovalev_D 23:12e6183f04d4 1242 while (ITM-&gt;PORT31_U32 == 0);
Kovalev_D 23:12e6183f04d4 1243 ITM-&gt;PORT[31].u8 = task_id; // id of next task
Kovalev_D 23:12e6183f04d4 1244 while (ITM-&gt;PORT[31].u32 == 0);
Kovalev_D 23:12e6183f04d4 1245 ITM-&gt;PORT[31].u32 = task_status; // status information
Kovalev_D 23:12e6183f04d4 1246 }</pre>
Kovalev_D 23:12e6183f04d4 1247
Kovalev_D 23:12e6183f04d4 1248
Kovalev_D 23:12e6183f04d4 1249 <h3>Cortex-M3 additional Debug Access</h3>
Kovalev_D 23:12e6183f04d4 1250
Kovalev_D 23:12e6183f04d4 1251 <p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
Kovalev_D 23:12e6183f04d4 1252 Data can be transmitted via a certain global buffer variable towards the target system.</p>
Kovalev_D 23:12e6183f04d4 1253
Kovalev_D 23:12e6183f04d4 1254 <p>The buffer variable and the prototypes of the additional functions are shown in the
Kovalev_D 23:12e6183f04d4 1255 table below.</p>
Kovalev_D 23:12e6183f04d4 1256
Kovalev_D 23:12e6183f04d4 1257 <table class="kt" border="0" cellpadding="0" cellspacing="0">
Kovalev_D 23:12e6183f04d4 1258 <tbody>
Kovalev_D 23:12e6183f04d4 1259 <tr>
Kovalev_D 23:12e6183f04d4 1260 <th class="kt" nowrap="nowrap">Name</th>
Kovalev_D 23:12e6183f04d4 1261 <th class="kt">Parameter</th>
Kovalev_D 23:12e6183f04d4 1262 <th class="kt">Description</th>
Kovalev_D 23:12e6183f04d4 1263 </tr>
Kovalev_D 23:12e6183f04d4 1264 <tr>
Kovalev_D 23:12e6183f04d4 1265 <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>
Kovalev_D 23:12e6183f04d4 1266 <td class="kt"> </td>
Kovalev_D 23:12e6183f04d4 1267 <td class="kt">Buffer to transmit data towards debug system. <br><br>
Kovalev_D 23:12e6183f04d4 1268 Value 0x5AA55AA5 indicates that buffer is empty.</td>
Kovalev_D 23:12e6183f04d4 1269 </tr>
Kovalev_D 23:12e6183f04d4 1270 <tr>
Kovalev_D 23:12e6183f04d4 1271 <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>
Kovalev_D 23:12e6183f04d4 1272 <td class="kt">none</td>
Kovalev_D 23:12e6183f04d4 1273 <td class="kt">The nonblocking functions returns the character stored in
Kovalev_D 23:12e6183f04d4 1274 ITM_RxBuffer. <br><br>
Kovalev_D 23:12e6183f04d4 1275 Return: -1 indicates that no character was received.</td>
Kovalev_D 23:12e6183f04d4 1276 </tr>
Kovalev_D 23:12e6183f04d4 1277 <tr>
Kovalev_D 23:12e6183f04d4 1278 <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>
Kovalev_D 23:12e6183f04d4 1279 <td class="kt">none</td>
Kovalev_D 23:12e6183f04d4 1280 <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>
Kovalev_D 23:12e6183f04d4 1281 Return: 1 indicates that a character is available, 0 indicates that
Kovalev_D 23:12e6183f04d4 1282 no character is available.</td>
Kovalev_D 23:12e6183f04d4 1283 </tr>
Kovalev_D 23:12e6183f04d4 1284 </tbody>
Kovalev_D 23:12e6183f04d4 1285 </table>
Kovalev_D 23:12e6183f04d4 1286
Kovalev_D 23:12e6183f04d4 1287
Kovalev_D 23:12e6183f04d4 1288 <h2><a name="5"></a>CMSIS Example</h2>
Kovalev_D 23:12e6183f04d4 1289 <p>
Kovalev_D 23:12e6183f04d4 1290 The following section shows a typical example for using the CMSIS layer in user applications.
Kovalev_D 23:12e6183f04d4 1291 The example is based on a STM32F10x Device.
Kovalev_D 23:12e6183f04d4 1292 </p>
Kovalev_D 23:12e6183f04d4 1293 <pre>
Kovalev_D 23:12e6183f04d4 1294 #include "stm32f10x.h"
Kovalev_D 23:12e6183f04d4 1295
Kovalev_D 23:12e6183f04d4 1296 volatile uint32_t msTicks; /* timeTicks counter */
Kovalev_D 23:12e6183f04d4 1297
Kovalev_D 23:12e6183f04d4 1298 void SysTick_Handler(void) {
Kovalev_D 23:12e6183f04d4 1299 msTicks++; /* increment timeTicks counter */
Kovalev_D 23:12e6183f04d4 1300 }
Kovalev_D 23:12e6183f04d4 1301
Kovalev_D 23:12e6183f04d4 1302 __INLINE static void Delay (uint32_t dlyTicks) {
Kovalev_D 23:12e6183f04d4 1303 uint32_t curTicks = msTicks;
Kovalev_D 23:12e6183f04d4 1304
Kovalev_D 23:12e6183f04d4 1305 while ((msTicks - curTicks) &lt; dlyTicks);
Kovalev_D 23:12e6183f04d4 1306 }
Kovalev_D 23:12e6183f04d4 1307
Kovalev_D 23:12e6183f04d4 1308 __INLINE static void LED_Config(void) {
Kovalev_D 23:12e6183f04d4 1309 ; /* Configure the LEDs */
Kovalev_D 23:12e6183f04d4 1310 }
Kovalev_D 23:12e6183f04d4 1311
Kovalev_D 23:12e6183f04d4 1312 __INLINE static void LED_On (uint32_t led) {
Kovalev_D 23:12e6183f04d4 1313 ; /* Turn On LED */
Kovalev_D 23:12e6183f04d4 1314 }
Kovalev_D 23:12e6183f04d4 1315
Kovalev_D 23:12e6183f04d4 1316 __INLINE static void LED_Off (uint32_t led) {
Kovalev_D 23:12e6183f04d4 1317 ; /* Turn Off LED */
Kovalev_D 23:12e6183f04d4 1318 }
Kovalev_D 23:12e6183f04d4 1319
Kovalev_D 23:12e6183f04d4 1320 int main (void) {
Kovalev_D 23:12e6183f04d4 1321 if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
Kovalev_D 23:12e6183f04d4 1322 ; /* Handle Error */
Kovalev_D 23:12e6183f04d4 1323 while (1);
Kovalev_D 23:12e6183f04d4 1324 }
Kovalev_D 23:12e6183f04d4 1325
Kovalev_D 23:12e6183f04d4 1326 LED_Config(); /* configure the LEDs */
Kovalev_D 23:12e6183f04d4 1327
Kovalev_D 23:12e6183f04d4 1328 while(1) {
Kovalev_D 23:12e6183f04d4 1329 LED_On (0x100); /* Turn on the LED */
Kovalev_D 23:12e6183f04d4 1330 Delay (100); /* delay 100 Msec */
Kovalev_D 23:12e6183f04d4 1331 LED_Off (0x100); /* Turn off the LED */
Kovalev_D 23:12e6183f04d4 1332 Delay (100); /* delay 100 Msec */
Kovalev_D 23:12e6183f04d4 1333 }
Kovalev_D 23:12e6183f04d4 1334 }</pre>
Kovalev_D 23:12e6183f04d4 1335
Kovalev_D 23:12e6183f04d4 1336
Kovalev_D 23:12e6183f04d4 1337 </body></html>