Dmitry Kovalev
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Dmitry Kovalev
host/Source/App/el_lin.h@23:12e6183f04d4, 2016-02-03 (annotated)
- Committer:
- Kovalev_D
- Date:
- Wed Feb 03 10:44:42 2016 +0300
- Revision:
- 23:12e6183f04d4
[thyz
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kovalev_D |
23:12e6183f04d4 | 1 | |
| Kovalev_D |
23:12e6183f04d4 | 2 | /**--------------File Info--------------------------------------------------------------------------------- |
| Kovalev_D |
23:12e6183f04d4 | 3 | ** File name: el_lin.h |
| Kovalev_D |
23:12e6183f04d4 | 4 | ** Last modified Date: 2011-08-22 |
| Kovalev_D |
23:12e6183f04d4 | 5 | ** Last Version: V1.00 |
| Kovalev_D |
23:12e6183f04d4 | 6 | ** Descriptions: |
| Kovalev_D |
23:12e6183f04d4 | 7 | ** |
| Kovalev_D |
23:12e6183f04d4 | 8 | **-------------------------------------------------------------------------------------------------------- |
| Kovalev_D |
23:12e6183f04d4 | 9 | ** Created by: Electrooptika incor. |
| Kovalev_D |
23:12e6183f04d4 | 10 | ** Created date: 2011-08-22 |
| Kovalev_D |
23:12e6183f04d4 | 11 | ** Version: V1.00 |
| Kovalev_D |
23:12e6183f04d4 | 12 | ** |
| Kovalev_D |
23:12e6183f04d4 | 13 | **-------------------------------------------------------------------------------------------------------- |
| Kovalev_D |
23:12e6183f04d4 | 14 | *********************************************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 15 | #ifndef __DMA_H |
| Kovalev_D |
23:12e6183f04d4 | 16 | #define __DMA_H |
| Kovalev_D |
23:12e6183f04d4 | 17 | |
| Kovalev_D |
23:12e6183f04d4 | 18 | |
| Kovalev_D |
23:12e6183f04d4 | 19 | |
| Kovalev_D |
23:12e6183f04d4 | 20 | #define STRT_ERR 0x0080 //e. error of the start bit //r. îøèáêà ñòàðò-áèòà |
| Kovalev_D |
23:12e6183f04d4 | 21 | #define STOP_ERR 0x0040 //e. error of the stop bit //r. îøèáêà ñòîï-áèòà |
| Kovalev_D |
23:12e6183f04d4 | 22 | #define SIZE_ERR 0x0004 //e. size of the received data packet mismatches the agreement //r. ðàçìåð ïðèíÿòîãî ïàêåòà íå ñîîòâåòñòâóåò ñîãëàøåíèþ |
| Kovalev_D |
23:12e6183f04d4 | 23 | #define LCC_ERR 0x0002 //e. checksum has not coincided //r. íå ñîâïàëà êîíòðîëüíàÿ ñóììà |
| Kovalev_D |
23:12e6183f04d4 | 24 | #define NO_CMD_ERR 0x0100 //e. in the received packet there is no attribute of command //r. â ïðèíÿòîì ïàêåòå íåò ïðèçíàêà êîìàíäû |
| Kovalev_D |
23:12e6183f04d4 | 25 | #define CODE_ERR 0x0200 //e. unknown code of a command //r. íåèçâåñòíûé êîä êîìàíäû |
| Kovalev_D |
23:12e6183f04d4 | 26 | #define MODE_ERR 0x0400 //e. code of a command mismatches a current mode //r. êîä êîìàíäû íå ñîîòâåòñòâóåò òåêóùåìó ðåæèìó |
| Kovalev_D |
23:12e6183f04d4 | 27 | #define PARAM_ERR 0x0800 //e. parameters of a command was set incorrectly //r. íåâåðíî çàäàííûå ïàðàìåòðû êîìàíäû |
| Kovalev_D |
23:12e6183f04d4 | 28 | #define MAXSIZE_ERR 0x1000 //e. receiver buffer overflow //r. ïåðåïîëíåíèå áóôåðà ïðèåìíèêà |
| Kovalev_D |
23:12e6183f04d4 | 29 | #define ADDR_ERR 0x2000 //e. incorrect address of the device //r. íåâåðíûé àäðåñ óñòðîéñòâà |
| Kovalev_D |
23:12e6183f04d4 | 30 | #define READ_ERR 0x4000 //e. stop of link because of untimely data read //r. îñòàíîâ ñâÿçè íåñâîåâðåìåííûì ÷òåíèåì äàííûõ |
| Kovalev_D |
23:12e6183f04d4 | 31 | #define WASQ_ERR 0x8000 //e. error of waiting of authentic answer //r. îøèáêà îæèäàíèÿ äîñòîâåðíîãî îòâåòà |
| Kovalev_D |
23:12e6183f04d4 | 32 | |
| Kovalev_D |
23:12e6183f04d4 | 33 | #define Trm_En_Rd 0x0080 //e. a mask of permission/readiness of transmitter of the 2 line //r. ìàñêà ðàçðåøåíèÿ/ãîòîâíîñòè ïåðåäàò÷èêà ëèíèè 2 |
| Kovalev_D |
23:12e6183f04d4 | 34 | #define Rcv_Rdy 0x0040 //e. a mask of the readiness bit of the receiver //r. ìàñêà áèòà ãîòîâíîñòè ïðèåìíèêà |
| Kovalev_D |
23:12e6183f04d4 | 35 | #define Rcv_Ferr 0x0020 //e. a mask of the "format error" bit //r. ìàñêà áèòà "îøèáêà ôîðìàòà" |
| Kovalev_D |
23:12e6183f04d4 | 36 | #define Rcv_Tout 0x0010 //e. a mask of the "time-out" bit //r. ìàñêà áèòà "òàéì-àóò" |
| Kovalev_D |
23:12e6183f04d4 | 37 | #define Rcv_Rful 0x0008 //e. a mask of the "stack is full" bit //r. ìàñêà áèòà "ñòåê ïîëîí" |
| Kovalev_D |
23:12e6183f04d4 | 38 | |
| Kovalev_D |
23:12e6183f04d4 | 39 | |
| Kovalev_D |
23:12e6183f04d4 | 40 | #define FIFOs_En 0x00000001 |
| Kovalev_D |
23:12e6183f04d4 | 41 | #define RX_FIFO_Reset 0x00000002 |
| Kovalev_D |
23:12e6183f04d4 | 42 | #define TX_FIFO_Reset 0x00000004 |
| Kovalev_D |
23:12e6183f04d4 | 43 | #define DMA_Mode_UART 0x00000008 |
| Kovalev_D |
23:12e6183f04d4 | 44 | #define RX_TrigLvl_1 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 45 | #define RX_TrigLvl_4 0x00000040 |
| Kovalev_D |
23:12e6183f04d4 | 46 | #define RX_TrigLvl_8 0x00000080 |
| Kovalev_D |
23:12e6183f04d4 | 47 | #define RX_TrigLvl_14 0x000000C0 |
| Kovalev_D |
23:12e6183f04d4 | 48 | |
| Kovalev_D |
23:12e6183f04d4 | 49 | #define word_length_8 0x00000003 |
| Kovalev_D |
23:12e6183f04d4 | 50 | |
| Kovalev_D |
23:12e6183f04d4 | 51 | #define one_stop_bit 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 52 | |
| Kovalev_D |
23:12e6183f04d4 | 53 | #define no_parity 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 54 | |
| Kovalev_D |
23:12e6183f04d4 | 55 | #define back_trans_dis 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 56 | |
| Kovalev_D |
23:12e6183f04d4 | 57 | #define DLAB_access 0x00000080 |
| Kovalev_D |
23:12e6183f04d4 | 58 | |
| Kovalev_D |
23:12e6183f04d4 | 59 | #define TRANS_SHIFT_BUF_EMPTY 0x00000040 |
| Kovalev_D |
23:12e6183f04d4 | 60 | #define DMA_BUSY 0x00020000 |
| Kovalev_D |
23:12e6183f04d4 | 61 | #define RecievBufEmpty 0x00000001 |
| Kovalev_D |
23:12e6183f04d4 | 62 | #define DIS_ALL_INT 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 63 | #define RBR_IntEnabl 0x00000001 |
| Kovalev_D |
23:12e6183f04d4 | 64 | /* Second half of the second RAM is used for GPDMA operation. */ |
| Kovalev_D |
23:12e6183f04d4 | 65 | |
| Kovalev_D |
23:12e6183f04d4 | 66 | #define DMA_UART0_TX 8 |
| Kovalev_D |
23:12e6183f04d4 | 67 | #define DMA_UART0_RX 9 |
| Kovalev_D |
23:12e6183f04d4 | 68 | #define DMA_UART1_TX 10 |
| Kovalev_D |
23:12e6183f04d4 | 69 | #define DMA_UART1_RX 11 |
| Kovalev_D |
23:12e6183f04d4 | 70 | #define DMA_UART2_TX 12 |
| Kovalev_D |
23:12e6183f04d4 | 71 | #define DMA_UART2_RX 13 |
| Kovalev_D |
23:12e6183f04d4 | 72 | #define DMA_UART3_TX 14 |
| Kovalev_D |
23:12e6183f04d4 | 73 | #define DMA_UART3_RX 15 |
| Kovalev_D |
23:12e6183f04d4 | 74 | |
| Kovalev_D |
23:12e6183f04d4 | 75 | #define DMA_MEMORY 0 |
| Kovalev_D |
23:12e6183f04d4 | 76 | #define SrcDMA_UART0_RX DMA_UART0_RX << 1 |
| Kovalev_D |
23:12e6183f04d4 | 77 | #define SrcDMA_UART0_TX DMA_UART0_TX << 1 |
| Kovalev_D |
23:12e6183f04d4 | 78 | #define SrcDMA_UART1_TX DMA_UART1_TX << 1 |
| Kovalev_D |
23:12e6183f04d4 | 79 | #define DstDMA_UART0_TX DMA_UART0_TX << 6 |
| Kovalev_D |
23:12e6183f04d4 | 80 | #define DstDMA_UART1_TX DMA_UART1_TX << 6 |
| Kovalev_D |
23:12e6183f04d4 | 81 | #define DstDMA_UART0_RX DMA_UART0_RX << 6 |
| Kovalev_D |
23:12e6183f04d4 | 82 | #define SrcDMA_UART1_RX DMA_UART1_RX << 1 |
| Kovalev_D |
23:12e6183f04d4 | 83 | #define DstDMA_UART1_RX DMA_UART1_RX << 6 |
| Kovalev_D |
23:12e6183f04d4 | 84 | |
| Kovalev_D |
23:12e6183f04d4 | 85 | /* UART0 TX and RX */ |
| Kovalev_D |
23:12e6183f04d4 | 86 | #define UART0_DMA_TX_SRC 0x2007C800 /* starting addr of DATA register in UART0 */ |
| Kovalev_D |
23:12e6183f04d4 | 87 | #define UART0_DMA_TX_DST LPC_UART0_BASE |
| Kovalev_D |
23:12e6183f04d4 | 88 | #define UART0_DMA_RX_SRC LPC_UART0_BASE |
| Kovalev_D |
23:12e6183f04d4 | 89 | #define UART0_DMA_RX_DST 0x2007C900 |
| Kovalev_D |
23:12e6183f04d4 | 90 | |
| Kovalev_D |
23:12e6183f04d4 | 91 | #define UART2_DMA_TX_DST LPC_UART2_BASE |
| Kovalev_D |
23:12e6183f04d4 | 92 | #define UART1_DMA_TX_DST LPC_UART1_BASE |
| Kovalev_D |
23:12e6183f04d4 | 93 | |
| Kovalev_D |
23:12e6183f04d4 | 94 | #define GPDMA_POWER_ON 0x20000000 |
| Kovalev_D |
23:12e6183f04d4 | 95 | |
| Kovalev_D |
23:12e6183f04d4 | 96 | #define UART_REQ 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 97 | |
| Kovalev_D |
23:12e6183f04d4 | 98 | //To clear particular DMA TC-interrupts |
| Kovalev_D |
23:12e6183f04d4 | 99 | #define DMA0_IntTCClear 0x00000001 |
| Kovalev_D |
23:12e6183f04d4 | 100 | #define DMA1_IntTCClear 0x00000002 |
| Kovalev_D |
23:12e6183f04d4 | 101 | #define DMA2_IntTCClear 0x00000004 |
| Kovalev_D |
23:12e6183f04d4 | 102 | #define DMA3_IntTCClear 0x00000008 |
| Kovalev_D |
23:12e6183f04d4 | 103 | #define DMA4_IntTCClear 0x00000010 |
| Kovalev_D |
23:12e6183f04d4 | 104 | #define DMA5_IntTCClear 0x00000020 |
| Kovalev_D |
23:12e6183f04d4 | 105 | #define DMA6_IntTCClear 0x00000040 |
| Kovalev_D |
23:12e6183f04d4 | 106 | #define DMA7_IntTCClear 0x00000080 |
| Kovalev_D |
23:12e6183f04d4 | 107 | |
| Kovalev_D |
23:12e6183f04d4 | 108 | //To clear particular DMA Error-interrupts |
| Kovalev_D |
23:12e6183f04d4 | 109 | #define DMA0_IntErrClear 0x00000001 |
| Kovalev_D |
23:12e6183f04d4 | 110 | #define DMA1_IntErrClear 0x00000002 |
| Kovalev_D |
23:12e6183f04d4 | 111 | #define DMA2_IntErrClear 0x00000004 |
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23:12e6183f04d4 | 112 | #define DMA3_IntErrClear 0x00000008 |
| Kovalev_D |
23:12e6183f04d4 | 113 | #define DMA4_IntErrClear 0x00000010 |
| Kovalev_D |
23:12e6183f04d4 | 114 | #define DMA5_IntErrClear 0x00000020 |
| Kovalev_D |
23:12e6183f04d4 | 115 | #define DMA6_IntErrClear 0x00000040 |
| Kovalev_D |
23:12e6183f04d4 | 116 | #define DMA7_IntErrClear 0x00000080 |
| Kovalev_D |
23:12e6183f04d4 | 117 | #define DMACH1_IntTCPend 0x00000002 |
| Kovalev_D |
23:12e6183f04d4 | 118 | |
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23:12e6183f04d4 | 119 | #define DMA_ControllerEn 0x00000001 |
| Kovalev_D |
23:12e6183f04d4 | 120 | |
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23:12e6183f04d4 | 121 | #define DMA_AHB_Little 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 122 | #define DMA_AHB_Big 0x00000002 |
| Kovalev_D |
23:12e6183f04d4 | 123 | |
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23:12e6183f04d4 | 124 | #define SrcBSize_1 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 125 | #define SrcBSize_4 0x00001000 |
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23:12e6183f04d4 | 126 | #define SrcBSize_8 0x00002000 |
| Kovalev_D |
23:12e6183f04d4 | 127 | #define SrcBSize_16 0x00003000 |
| Kovalev_D |
23:12e6183f04d4 | 128 | #define SrcBSize_32 0x00004000 |
| Kovalev_D |
23:12e6183f04d4 | 129 | #define SrcBSize_64 0x00005000 |
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23:12e6183f04d4 | 130 | #define SrcBSize_128 0x00006000 |
| Kovalev_D |
23:12e6183f04d4 | 131 | #define SrcBSize_256 0x00007000 |
| Kovalev_D |
23:12e6183f04d4 | 132 | |
| Kovalev_D |
23:12e6183f04d4 | 133 | #define DstBSize_1 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 134 | #define DstBSize_4 0x00008000 |
| Kovalev_D |
23:12e6183f04d4 | 135 | #define DstBSize_8 0x00010000 |
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23:12e6183f04d4 | 136 | #define DstBSize_16 0x00018000 |
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23:12e6183f04d4 | 137 | #define DstBSize_32 0x00020000 |
| Kovalev_D |
23:12e6183f04d4 | 138 | #define DstBSize_64 0x00028000 |
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23:12e6183f04d4 | 139 | #define DstBSize_128 0x00030000 |
| Kovalev_D |
23:12e6183f04d4 | 140 | #define DstBSize_256 0x00038000 |
| Kovalev_D |
23:12e6183f04d4 | 141 | |
| Kovalev_D |
23:12e6183f04d4 | 142 | #define SrcWidth_8b 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 143 | #define SrcWidth_16b 0x00020000 |
| Kovalev_D |
23:12e6183f04d4 | 144 | #define SrcWidth_32b 0x00040000 |
| Kovalev_D |
23:12e6183f04d4 | 145 | |
| Kovalev_D |
23:12e6183f04d4 | 146 | #define DstWidth_8b 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 147 | #define DstWidth_16b 0x00200000 |
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23:12e6183f04d4 | 148 | #define DstWidth_32b 0x00400000 |
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23:12e6183f04d4 | 149 | |
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23:12e6183f04d4 | 150 | #define SrcInc 0x04000000 |
| Kovalev_D |
23:12e6183f04d4 | 151 | #define SrcFixed 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 152 | |
| Kovalev_D |
23:12e6183f04d4 | 153 | #define DstInc 0x08000000 |
| Kovalev_D |
23:12e6183f04d4 | 154 | #define DstFixed 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 155 | |
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23:12e6183f04d4 | 156 | #define TCIntEnabl 0x80000000 |
| Kovalev_D |
23:12e6183f04d4 | 157 | #define TCIntDisabl 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 158 | |
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23:12e6183f04d4 | 159 | #define DMAChannelEn 0x00000001 |
| Kovalev_D |
23:12e6183f04d4 | 160 | #define DMAChannelDis 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 161 | |
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23:12e6183f04d4 | 162 | #define CH2_ENABLED 0x00000004 |
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23:12e6183f04d4 | 163 | |
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23:12e6183f04d4 | 164 | #define DONtMaskTCInt 0x00008000 |
| Kovalev_D |
23:12e6183f04d4 | 165 | #define MaskTCInt 0x00000000 |
| Kovalev_D |
23:12e6183f04d4 | 166 | #define DONtMaskErrInt 0x00004000 |
| Kovalev_D |
23:12e6183f04d4 | 167 | #define MaskErrInt 0x00000000 |
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23:12e6183f04d4 | 168 | |
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23:12e6183f04d4 | 169 | #define INT_DMA_Disabl 0x04000000 |
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23:12e6183f04d4 | 170 | /* DMA mode */ |
| Kovalev_D |
23:12e6183f04d4 | 171 | #define M2M 0x00 |
| Kovalev_D |
23:12e6183f04d4 | 172 | #define M2P 0x01 |
| Kovalev_D |
23:12e6183f04d4 | 173 | #define P2M 0x02 |
| Kovalev_D |
23:12e6183f04d4 | 174 | #define P2P 0x03 |
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23:12e6183f04d4 | 175 | |
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23:12e6183f04d4 | 176 | #define Sp38400 0x00000 |
| Kovalev_D |
23:12e6183f04d4 | 177 | #define Sp115200 0x00010 |
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23:12e6183f04d4 | 178 | #define Sp460800 0x00020 |
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23:12e6183f04d4 | 179 | #define Sp921600 0x00030 |
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23:12e6183f04d4 | 180 | |
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23:12e6183f04d4 | 181 | extern unsigned int trm_num_byt; |
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23:12e6183f04d4 | 182 | extern unsigned int rcv_num_byt; |
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23:12e6183f04d4 | 183 | extern unsigned int rcv_Rdy; |
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23:12e6183f04d4 | 184 | extern char trm_buf[64]; |
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23:12e6183f04d4 | 185 | extern char rcv_buf[64]; |
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23:12e6183f04d4 | 186 | extern char rcv_copy[64]; |
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23:12e6183f04d4 | 187 | extern unsigned int trm_cycl; |
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23:12e6183f04d4 | 188 | extern unsigned int num_of_par; |
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23:12e6183f04d4 | 189 | extern void* addr_param[16]; |
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23:12e6183f04d4 | 190 | extern unsigned int size_param[16]; |
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23:12e6183f04d4 | 191 | extern unsigned int trm_rate; |
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23:12e6183f04d4 | 192 | extern unsigned int trm_cycl; |
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23:12e6183f04d4 | 193 | extern unsigned int rcv_num_byt_old; |
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23:12e6183f04d4 | 194 | extern int rcv_byt_copy; |
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23:12e6183f04d4 | 195 | extern unsigned int trm_ena; |
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23:12e6183f04d4 | 196 | extern int cycl_phase; |
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23:12e6183f04d4 | 197 | extern unsigned int line_err; |
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23:12e6183f04d4 | 198 | extern unsigned int line_sts; |
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23:12e6183f04d4 | 199 | extern int rx_buf_copy; |
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23:12e6183f04d4 | 200 | extern char zeros; |
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23:12e6183f04d4 | 201 | extern unsigned int SystemCoreClock; |
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23:12e6183f04d4 | 202 | |
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23:12e6183f04d4 | 203 | extern void DMA_Init(void); |
| Kovalev_D |
23:12e6183f04d4 | 204 | extern void transm_DAT(void); |
| Kovalev_D |
23:12e6183f04d4 | 205 | extern void Line_1_Rcv(void); |
| Kovalev_D |
23:12e6183f04d4 | 206 | |
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23:12e6183f04d4 | 207 | extern void UARTInit(void); |
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23:12e6183f04d4 | 208 | extern void UART1_Init(void); |
| Kovalev_D |
23:12e6183f04d4 | 209 | //extern int UART0_SendByte(int); |
| Kovalev_D |
23:12e6183f04d4 | 210 | extern int UART1_SendByte(int); |
| Kovalev_D |
23:12e6183f04d4 | 211 | extern void UART_SwitchSpeed(unsigned); |
| Kovalev_D |
23:12e6183f04d4 | 212 | extern void UART_DMA_Init(void); |
| Kovalev_D |
23:12e6183f04d4 | 213 | extern void SystemCoreClockUpdate (void); |
| Kovalev_D |
23:12e6183f04d4 | 214 | |
| Kovalev_D |
23:12e6183f04d4 | 215 | #endif /* end __DMA_H */ |
| Kovalev_D |
23:12e6183f04d4 | 216 |